WO2016194092A1 - Semiconductor memory device, method for manufacturing same, and device for manufacturing semiconductor memory device - Google Patents
Semiconductor memory device, method for manufacturing same, and device for manufacturing semiconductor memory device Download PDFInfo
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- WO2016194092A1 WO2016194092A1 PCT/JP2015/065691 JP2015065691W WO2016194092A1 WO 2016194092 A1 WO2016194092 A1 WO 2016194092A1 JP 2015065691 W JP2015065691 W JP 2015065691W WO 2016194092 A1 WO2016194092 A1 WO 2016194092A1
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Images
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/10—Phase change RAM [PCRAM, PRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Shaping switching materials
- H10N70/066—Shaping switching materials by filling of openings, e.g. damascene method
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
- H10N70/8265—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8828—Tellurides, e.g. GeSbTe
Definitions
- the present invention relates to a semiconductor memory device, a manufacturing method thereof, and a manufacturing apparatus of a semiconductor memory device, and more particularly to an electrically rewritable phase change memory, a manufacturing method thereof, and a manufacturing apparatus thereof.
- phase change memory using a phase change material as a recording layer.
- the phase change memory stores the difference in resistance of each state (crystalline phase and amorphous phase) of the phase change material as information, and the conventional memory that stores information by the difference in the amount of charge accumulated in the stacked gate structure.
- the thickness for holding the charge in the memory portion is not required, and since the operating voltage is low, the thickness for the insulating film is also not required, so compared to the case of the memory cell with a stacked gate structure, There are few restrictions on miniaturization.
- phase change memory In the phase change memory, the difference in resistance value between the amorphous phase and the crystal phase is large, and the difference between these resistance values is used as a read signal, so that the sensing operation is easy and the read speed is high. Therefore, the phase change memory is expected to provide a high-density (large capacity) and high-speed memory device in the future.
- the recording layer includes a second portion having a relatively higher nitrogen content than the first portion, thereby stabilizing the crystalline state and the amorphous state and reducing power consumption.
- a configuration of a non-volatile storage device configured as described above is disclosed.
- phase change material of the phase change memory cell for example, chalcogenide represented by Ge 2 Sb 2 Te 5 is known to be suitable. It has been pointed out that such phase change materials generally have low thermal stability.
- Patent Document 2 discloses a sidewall protective film 123 made of a silicon nitride film on the sidewall of the chalcogenide material layer 114 in order to prevent the chalcogenite material from sublimating due to its low thermal stability in the manufacturing process of the phase change memory cell. Techniques for forming the are disclosed.
- the phase change material layer is concerned about deterioration of phase change characteristics due to oxidation due to its low thermal stability.
- a conductive electrode 33 and a base electrode 32 made of a metal material are formed on the upper and lower surfaces of the phase change material layer 31, respectively.
- the phase change region is formed in a dome shape with the surface of the phase change material layer 31 in contact with the base electrode 32 as the center.
- the area of the surface of the phase change material layer 31 on the base electrode 32 side is equal to the area of the base electrode 32 on the phase change material layer 31 side.
- the phase change region formed around the contact surface with the base electrode 32 is isolated from the end face of the phase change material layer 31 to prevent deterioration of phase change characteristics due to oxidation. Is possible.
- phase change memory has been attracting attention from the viewpoint of increasing the capacity of the memory.
- the phase change material is oxidized when the gap fill portion 14 is formed.
- the rewriting characteristics of the phase change material are deteriorated, and the number of rewritable times is reduced.
- the phase change memory cell disclosed in Patent Document 2 is a planar type, and cannot solve the problem of oxidation of the phase change material at the time of manufacturing the above-described three-dimensional type phase change memory. That is, in the three-dimensional type phase change memory, there is a problem that the phase change region is easily oxidized as compared with the planar type phase change memory, and the rewrite characteristics of the phase change material may be deteriorated.
- an object of the present invention is to provide a semiconductor memory device having excellent rewriting characteristics and high reliability, a manufacturing method thereof, and a manufacturing device thereof.
- a preferred embodiment of the semiconductor memory device is a semiconductor memory device having a memory chain in which a plurality of phase change memory cells having a phase change material film are connected in series, wherein the phase change material film includes An insulating layer having oxidation resistance is formed on the main surface side of the center side of the memory chain.
- a stacked body is formed by alternately stacking select gate electrodes and interphase insulating films on the lower electrode, and penetrates the stacked body.
- a memory hole is formed, a phase change material is formed in a vacuum state in a region in the memory hole to form a phase change material layer, and an insulating layer having oxidation resistance is formed on a main surface of the phase change material layer It is characterized by forming.
- a phase change material film forming chamber for forming a phase change material layer by forming a phase change material on an object in a vacuum state
- An insulator forming chamber for forming an insulating material having oxidation resistance in a vacuum state on the object on which the change material layer is formed, and the phase change material layer formed in the phase change material deposition chamber.
- a transfer chamber for transferring the object to the insulator forming chamber while maintaining a vacuum state.
- a highly reliable semiconductor memory device having excellent rewrite characteristics, a manufacturing method thereof, and a manufacturing device thereof can be realized.
- FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. It is a cross-sectional schematic diagram which shows 1 process of the manufacturing process of the three-dimensional type phase change memory of a comparative example. It is a figure which shows the relationship between the oxygen content of a phase change material, and the frequency
- 1 is a bird's-eye view showing an overall configuration of a three-dimensional phase change memory according to Embodiment 1.
- FIG. 1 is a bird's-eye view showing an overall configuration of a three-dimensional phase change memory according to Embodiment 1.
- FIG. 3 is a diagram illustrating a partial equivalent circuit of the three-dimensional type phase change memory according to the first embodiment.
- FIG. 3 is a diagram illustrating a partial equivalent circuit of the three-dimensional type phase change memory according to the first embodiment.
- FIG. 3 is a schematic cross-sectional view showing a step of the manufacturing process for the three-dimensional type phase change memory according to the first embodiment.
- FIG. 3 is a schematic cross-sectional view showing a step of the manufacturing process for the three-dimensional type phase change memory according to the first embodiment.
- FIG. 3 is a schematic cross-sectional view showing a step of the manufacturing process for the three-dimensional type phase change memory according to the first embodiment.
- FIG. 3 is a schematic cross-sectional view showing a step of the manufacturing process for the three-dimensional type phase change memory according to the first embodiment.
- FIG. 3 is a schematic cross-sectional view showing a step of the manufacturing process for the three-dimensional type phase change memory according to the first embodiment.
- FIG. 3 is a schematic cross-sectional view showing a step of the manufacturing process for the three-dimensional type phase change memory according to the first embodiment. It is a figure which shows the relationship between the nitrogen / Ar gas flow ratio at the time of the sputter film-forming of GeSbTe which is a phase change material, and the rewrite frequency
- FIG. 3 is a schematic cross-sectional view showing a step of the manufacturing process for the three-dimensional type phase change memory according to the first embodiment.
- FIG. 3 is a schematic cross-sectional view showing a step of the manufacturing process for the three-dimensional type phase change memory according to the first embodiment.
- FIG. 3 is a schematic cross-sectional view showing a step of the manufacturing process for the three-dimensional type phase change memory according to the first embodiment.
- 1 is a schematic diagram illustrating a schematic configuration of a manufacturing apparatus for a three-dimensional type phase change memory (semiconductor memory device) according to Embodiment 1.
- FIG. 1 is a schematic diagram illustrating a schematic configuration of a manufacturing apparatus for a three-dimensional type phase change memory (semiconductor memory device) according to Embodiment 1.
- FIG. 1 is a schematic diagram illustrating a schematic configuration of a manufacturing apparatus for a three-dimensional type phase change memory (semiconductor memory device) according to Embodiment 1.
- FIG. FIG. 10 is a schematic cross-sectional view showing one step in a manufacturing process for the three-dimensional phase change memory according to the second embodiment.
- FIG. 10 is a schematic cross-sectional view showing one step in the manufacturing process of the three-dimensional phase change memory according to Example 3.
- the phase change material used for the recording layer of the phase change memory includes a high resistance phase (amorphous phase, hereinafter referred to as an amorphous phase) having a high electrical resistance and a crystal phase (amorphous phase lower than the high resistance phase).
- the crystal phase has a low resistance (hereinafter referred to as a crystal phase).
- the phase change memory stores information by making the difference in resistance between the amorphous phase and the crystalline phase correspond to “0” and “1”.
- the electric resistance value hereinafter referred to as a unit resistance value
- a unit resistance value is approximately 2 to 3 digits higher than that in the crystalline phase.
- a state in which the phase change material is amorphous and the resistance of the memory portion is high is referred to as a reset state
- a state in which the phase change material is a crystal and the resistance of the memory portion is low is referred to as a set state.
- 0 is a reset state, that is, an amorphous phase
- “1” is a set state, that is, a crystal phase.
- Reading information from the phase change memory is performed by applying a low voltage to the phase change material, measuring a current value passing through the phase change material, reading a resistance value of the phase change material, and identifying the information. At this time, since the voltage applied to the phase change material is low, the phase state of the phase change material does not change.
- the rewriting of the phase change memory is performed by causing a current to flow through the phase change material itself or a heater adjacent thereto to generate Joule heat in the phase change material.
- phase change part for example, a phase change material layer
- a pulse that rapidly cools the phase change material after heating it above the melting point is applied.
- the melting point of the phase change material is, for example, about 600 ° C.
- the rapid cooling time is, for example, about 3 nsec (nanoseconds).
- the temperature of the phase change part is locally maintained at a temperature not lower than the crystallization temperature and not higher than the melting point.
- the temperature at this time is 400 ° C., for example.
- the time required for crystallization varies depending on the composition of the phase change material, but is, for example, 50 nsec.
- crystallization of the phase change material is referred to as a set operation, and amorphization of the phase change material is referred to as a reset operation.
- a current that flows through the memory cell when performing the reset operation is referred to as a reset current.
- FIGS. 3, 13, and 14 are referred to.
- FIG. 13 is a schematic view showing a cross section in one step of the method of manufacturing the three-dimensional phase change memory.
- the channel 19 of the X chain selection element 64 is formed on a silicon wafer (not shown). Between the X chain selection element 64 and the upper electrode 17, a cell selection gate electrode 15 and an interlayer insulating film are formed. 16 is formed.
- the memory hole 52 is formed so as to penetrate the upper electrode 17 and the stacked body of the cell selection gate electrode 15 and the interlayer insulating film 16.
- a gate insulating film 18 is formed on the side wall of the memory hole 52, and a polysilicon channel 13 is formed on one main surface of the gate insulating film 18.
- the phase change material layer 11 is formed on one main surface of the polysilicon channel 13. Further, in the next step, as shown in FIG. 3, an insulating gap fill portion 14 is formed so as to be in direct contact with one main surface of the phase change material layer 11. Oxidation is a problem.
- the gap fill portion 14 is roughly classified into an insulating film formed by curing an insulating film coating material or an insulating film formed by a CVD method.
- the gap fill portion 14 is formed by coating a coating material for an insulating film on the phase change material layer 11 by a spin coating method.
- the phase change material layer 11 is applied around the contact surface with the gap fill portion 14 due to moisture contained in the insulating film coating material or moisture released when the insulating film coating material is cured. It is oxidized in the mold insulating film forming process and the subsequent wiring process.
- the film forming atmosphere is an oxidizing atmosphere, and the silicon wafer is heated to about 400 ° C., so that the phase change material layer 11 is oxidized in the process of forming the gap fill portion 14.
- phase change material layer 11 is oxidized in this way, phase change characteristics are lost in the oxidized region.
- Fig. 4 shows the relationship between the oxygen content of the phase change material and the number of times the phase change memory can be rewritten.
- the number of rewritable times in the phase change memory decreases as the oxygen content of the phase change material increases as shown in FIG. That is, as the gap fill portion 14 is formed, the phase change material is oxidized, so that the rewritable characteristics of the phase change material deteriorate, and in particular, the number of rewritable times decreases.
- FIG. 5 shows an enlarged view of the region 101 shown in FIG.
- FIG. 5 shows a region 121 where the phase changes during the rewrite operation of the phase change memory.
- the phase change region 121 is a phase in which the phase state changes to an amorphous phase or a crystalline phase in “0” writing or “1” writing, that is, in a reset operation or a set operation.
- the resistance ratio between the reset state and the set state becomes small.
- the resistance ratio between the set state and the reset state becomes small.
- the main surface of the phase change material layer 11 on the side wall side of the memory chain (main surface on the left side in FIG. 5) is changed to the main surface on the center side of the memory chain (main surface on the right side in FIG. 5).
- the entire region in the thickness direction up to) needs to be the phase change region 121.
- the main surface on the center side of the memory chain is easily oxidized when the gap fill portion 14 is formed. It is a problem to prevent the phase change region from being reduced.
- FIG. 6 shows an analysis result of thermal desorption gas mass analysis (TDS) of the GeSbTe film.
- TDS thermal desorption gas mass analysis
- FIG. 2 shows the result of Ge analysis.
- TDS thermal desorption gas mass analysis
- the chalcogenide material has extremely low thermal stability, which is a problem in the stability during the manufacture and use of the phase change memory cell.
- FIG. 1 is a schematic plan view showing a schematic structure of the planar memory
- FIG. 2 is a cross-sectional view taken along the line II ′ of FIG.
- the memory cell 41 of the planar memory is formed at the intersection of the bit line 42 and the word line 43. Selection of the memory cell 41 is performed by a selection element (not shown) provided for each memory cell, for example, a diode element.
- a selection element not shown
- the conductive electrode 33 is formed on the main surface of the phase change material layer 31. A region between the stacked body of the base electrode 32, the phase change material layer 31 and the conductive electrode 33 is filled with an interlayer insulating film 35.
- a bit line 34 is formed on the upper surfaces of the interlayer insulating film 35 and the conductive electrode 33.
- main surface refers to a surface perpendicular to the stacking direction 36 (vertical direction in FIG. 2) of the phase change material layer 31 on the base electrode 32.
- the main surface In the configuration shown in FIG. 2, of the two main surfaces of the phase change film, the main surface that is not in contact with the phase change film base (the base electrode 32 in the configuration of FIG. 2) is referred to as the surface.
- the other main surface facing the main surface (that is, the surface) on the side where the conductive electrode 33 is formed is a surface in contact with the base. That is, the base surface is a surface on which the phase change material layer 31 is applied, and is formed on the base surface of the phase change material layer 31 before the phase change material 31 is formed.
- the base electrode 32 is the base.
- phase change material layer 31 In such a planar phase change memory, sublimation of the phase change material layer 31 is prevented by the conductive electrode 33 formed on the main surface of the phase change material layer 31 for the following reason. That is, in the configuration shown in FIG. 2, even if the phase change material is heated and a part of the phase change material is slightly sublimated, the conductive electrode 33, the base electrode 32, and the interlayer insulating film 35 are not substantially deformed.
- the gas pressure of the phase change material jumps in the phase change memory.
- the temperature required for sublimation increases accordingly, so that when the sublimation temperature becomes equal to the heating temperature, a thermodynamic equilibrium state is reached. Once the thermodynamic equilibrium is reached, the phase change material will no longer sublime.
- the end face of the phase change material is open, the area of the end face is smaller than the area of the main surface suppressed by the conductive electrode 33 and the base electrode 32, and thus the same as described above. For this reason, the rate at which the phase change material sublimes decreases.
- the “end face” refers to a plane perpendicular to the main surface.
- the temperature used in the chemical vapor deposition method is about 400 to 700 ° C.
- FIG. 7 is a bird's-eye view showing the overall configuration of the three-dimensional phase change memory according to the first embodiment
- FIG. 8 is a schematic diagram showing a part of a cross section of the three-dimensional phase change memory shown in FIG.
- a Y chain selection element 62 and an X chain selection element 64 are provided in this order from the lower electrode 63 side.
- the memory chain 61 is provided in a plurality of rows between the upper electrode 17 and the X chain selection element 64.
- a plurality of cell selection gate electrodes 15 and interlayer insulating films 16 are alternately stacked between the upper electrode 17 and the lower electrode 63, and penetrate through these stacked bodies and the upper electrode 17 in the stacking direction. Thus, a memory hole 52 is formed.
- phase change material film 55 In the memory hole 52, the gate insulating film 18, the polysilicon channel 13, and a stacked layer 55 of a phase change material layer and an insulating layer having oxidation resistance (hereinafter referred to as a phase change material film 55) are sequentially formed from the side wall side. ) A stack 55 of phase change material and protective film is stacked in order from the side wall side of the memory hole 52, and a gap fill portion 14 is formed in a region surrounded by the phase change material film 55.
- the phase change memory cell 51 is provided for each layer of the cell selection gate electrode 15 in the stacked body formed of the gate insulating film 18, the polysilicon channel 13, and the phase change material film 55 formed in the memory hole 52. ing. That is, the phase change material film 55 is connected to the cell selection gate electrode 15 via the gate insulating film 18.
- the memory chain 61 is configured by connecting a plurality of such phase change memory cells 51 in series in the stacking direction of the cell selection gate electrode 15 and the interlayer insulating film 16.
- the main surface of the phase change material film 55 refers to a surface extending in the stacking direction of the cell selection gate electrode 15 and the interlayer insulating film 16.
- FIG. 8 shows a direction 53 perpendicular to the end face of the phase change material film 55 and a direction 54 perpendicular to the main surface of the phase change material film 55.
- FIG. 9 is a diagram illustrating a part of an equivalent circuit of the three-dimensional type phase change memory according to the first embodiment.
- the memory cell 51 is configured by connecting a phase change unit 231 and a polysilicon MOS 232 in parallel.
- the selection method of the memory chain 61 will be described with reference to FIG. 10 by taking as an example the case of a reset operation (that is, a write operation, a “0” write operation, a high resistance operation).
- the memory chain 61 is selected using an X chain selection element 64 and a Y chain selection element 62 (see FIG. 7).
- a selection operation is performed by applying an on voltage or an off voltage to the gate electrodes X1, X2, and X3 of the selection element.
- a selection operation is performed by applying an on voltage or an off voltage to the gate electrodes Y1, Y2, and Y3 of the selection element.
- the X chain selection element 64 and the Y chain selection element 62 are double gate polysilicon MOS. That is, since there are two gate electrodes for each MOS and the channel thickness of the MOS is thin, the MOS is turned on only when an on-voltage is applied to the two gate electrodes. In other cases, that is, when an on-voltage is applied to one of the gate electrodes and an off-voltage is applied to the other, or when an off-voltage is applied to both of the two gate electrodes, the MOS is turned off. For example, when the source voltage of the MOS is ⁇ 7.5, an example of the on voltage is 0V, and an example of the off voltage is ⁇ 7.5V.
- the X chain selection element 64 and the Y chain selection element 62 are connected in series. When both are turned on, electrons pass from the lower electrode 63 through the Y chain selection element 62, the X chain selection element 64, and the memory chain 61. To the upper electrode 17. Needless to say, the direction of current flow is opposite to the direction of electrons. At this time, a pulse current is applied to the selected memory cell 221 in the memory chain 61, and the selected memory cell 221 is written.
- An off voltage is applied to the cell selection gate electrode 15 connected to the selected memory cell 221 so as not to induce a channel in the polysilicon MOS 232 of the selected memory cell 221, so that no current flows through the polysilicon MOS 232, and the phase change unit 231 Current is passed through.
- an on-voltage is applied to the cell selection gate electrode 15 connected to the non-selected memory cell, and a channel is induced in the polysilicon MOS 232 of the selected memory cell, thereby causing a current to flow in the polysilicon MOS 232 and causing the phase change portion 231 to flow. Do not pass current.
- the channel 19 and the interlayer insulating film 16 of the X chain selection element 64 are formed on a Y chain selection element 62 (not shown).
- the upper electrode is formed on the uppermost interlayer insulating film 16 of the stacked body. 17 is laminated. Note that the material and manufacturing method of the cell selection gate electrode 15 and the interlayer insulating film 16 are not described in detail, but can be formed using materials and manufacturing methods used in general semiconductor processes.
- the memory hole 52 is opened so as to penetrate the upper electrode 17 and the stacked body of the cell selection gate electrode 15 and the interlayer insulating film 16 to the upper surface of the channel 19 in the stacking direction of the stacked body.
- the gate insulating film 18 and the polysilicon channel 13 are formed sequentially from the side wall side of the memory hole 52. Thereafter, the gate insulating film 18 and the polysilicon channel 13 under the memory hole 52 are removed by anisotropic etch back. At the same time, the gate insulating film 18 near the upper electrode 17 is removed. After performing anisotropic etch back, the polysilicon channel 13 is formed again in the memory hole 52. A schematic cross-sectional view at this time is shown in FIG.
- a silicon oxide film is preferably used as the gate insulating film 18.
- a silicon oxide film is widely used as a gate insulating film of a MOSFET, and has an effect that can be stably applied to manufacture of a three-dimensional phase change memory.
- a high-k insulating film can be used as the gate insulating film 18.
- By using a high-k insulating film it becomes possible to increase the driving force of the cell selection MOS, and it is possible to increase the number of memory cells included in the memory chain (that is, increase the number of stacked memory cells). A larger-capacity phase change memory can be realized.
- the formation temperature of the gate insulating film 18 is desirable that the formation temperature of the gate insulating film 18 is low in a so-called memory chain stacked structure in which a plurality of memory chains are stacked in the Z direction. Thereby, when forming the gate insulating film 18 included in the upper memory chain, it is possible to reduce the thermal load on the phase change material 11 that is already formed and included in the lower memory chain.
- a method for forming the gate insulating film 18 an insulating film formed by a deposition insulating film, plasma CVD, plasma oxidation of a cell selection gate electrode, or thermal oxidation thermal oxidation can be used.
- FIG. 14 is a schematic cross-sectional view around the memory chain at the time after the phase change material layer 11 is formed.
- Chalcogenide is a material containing at least one element of sulfur, selenium, and tellurium.
- the chalcogenide that is currently considered promising as a phase change material is an alloy composed of Ge (germanium), Sb (antimony), and Te (tellurium), and a GeSbTe alloy, particularly a Ge 2 Sb 2 Te 5 alloy may be used.
- the Ge 2 Sb 2 Te 5 alloy is a material that has been successfully commercialized in DVD-RAM, and can reduce the time and cost required for product development. Furthermore, as the phase change material, an alloy mainly composed of InGeSbTe, ZnGeSbTe, BiGeSbTe, or Sb, particularly InSb, AgInSbTe, or AgInSb can be used. Above all, by using a phase change material with excellent retention characteristics such as InGeSbTe, ZnGeSbTe, BiGeSbTe, it becomes possible to increase the upper limit of the environmental temperature where phase change memory can be used, and it can be used for a wider range of applications. Therefore, it becomes possible to increase the sales volume.
- CVD Chemical Vapor Deposition
- ALD Atomic Layer Deposition
- sputtering or sol-gel method.
- CVD has an advantage that the film formation rate is fast and the phase change memory can be manufactured in a short time. Furthermore, CVD is superior in film thickness uniformity (coverage) for deep hole memory holes compared to sputtering.
- the film of the phase change material is formed in a vacuum state.
- the film formation temperature of CVD is preferably a low temperature of 130 to 200 ° C. By lowering the temperature, the phase change material is deposited in an amorphous state, and the film thickness uniformity is increased. Note that the inventors have confirmed that when the phase change material is formed in a crystalline state, non-uniformity in film thickness accompanying crystal grain growth is observed.
- ALD has the advantage that it can realize a phase change memory with low power consumption and little variation in rewrite current, and low power consumption. Furthermore, ALD is excellent in coverage. In the case of sputtering, since it can be performed by the same manufacturing process as that of the planar type phase change memory, there is an advantage that the development period of the phase change memory can be shortened.
- the sol-gel method has an advantage that the manufacturing cost can be reduced.
- phase change material layer 11 formed in the memory hole 52 is nitrided.
- nitriding layer 12 is formed on main surface 111 thereof.
- phase change material film 55 having nitriding layer 12 and phase change material layer 11 which are insulating layers having oxidation resistance is formed.
- a schematic cross-sectional view at this point is shown in FIG.
- 11 is a phase change material layer
- 12 is a nitridation treatment layer formed by nitriding treatment of the phase change material layer
- 55 is a phase change material layer 11 and a nitridation treatment layer 12.
- It is a phase change material film comprised.
- the phase change material layer 11 and the nitriding layer 12 are shown as separate layers.
- the nitriding layer 12 is a series of layers that are continuous with the phase change material layer 11. It is.
- a remote plasma having a nitriding action or a method of generating radicals or plasma having a nitriding action in the vicinity of the phase change material layer 11 can be used.
- remote plasma is preferably used.
- the phase change material precursor contains nitrogen, and this precursor is decomposed.
- the phase change material precursor contains nitrogen, and this precursor is decomposed.
- a method of generating nitrogen radicals and a method of generating plasma and radicals by electrolysis using a cracker while flowing ammonia.
- radical generation temperature can be reduced and the amount of radicals generated can be increased.
- radicals having a nitriding action include N and NH 2 .
- the main surface of the phase change material layer 11 is covered with an oxidation-resistant insulator, that is, a nitrided phase change material. For this reason, the thermal stability of the phase change material layer 11 is improved, and the oxidation resistance of the phase change material layer 11 is improved when a gap fill portion 14 described later is formed.
- the thermal stability is improved by the nitriding treatment is explained for the same reason as described in the planar phase change memory. That is, in the configuration shown in FIG. 15 after the nitriding treatment, the nitriding treatment layer 12 and the polysilicon channel 13 sandwiching the phase change material layer 11 are not substantially deformed even if a part of the phase change material is sublimated.
- the gas pressure of the phase change material vaporized by sublimation rises rapidly in the phase change memory. For this reason, due to the increase in sublimation temperature accompanying the increase in gas pressure, a thermodynamic equilibrium state is reached, and the phase change material does not sublime further.
- the inventors of the present invention have confirmed that the nitrided phase change material maintains thermal stability even at 400 ° C. and does not cause sublimation.
- the other main surface with respect to the main surface on which the nitriding layer 12 is formed is a surface in contact with the base, and the base is the polysilicon channel 13 in FIG. .
- FIG. 16 is an example showing the relationship between the nitrogen / Ar gas flow rate ratio during sputtering deposition of GeSbTe, which is a phase change material, and the number of rewritable times of the phase change memory to which the obtained GeSbTe film is applied.
- the flow rate ratio of nitrogen / Ar gas introduced into the sputtering chamber is increased when the phase change material is formed by the sputtering method, the number of rewritable phases of the phase change memory decreases.
- the nitrogen concentration in the phase change region needs to be approximately the same as the nitrogen content ratio of the film formation obtained when the nitrogen / Ar gas flow rate ratio is 0.5% or less. is there.
- the nitrogen content ratio in the entire phase change material layer when the nitrogen / Ar gas flow ratio is 0.5% is estimated to be approximately 20 at% or less.
- the nitrogen / Ar gas flow ratio is set to 0.5%. It is necessary to make it the same as the nitrogen concentration of the film formation obtained sometimes.
- the surface 551 that is, the main surface on the center side of the memory chain 61 among the main surfaces of the phase change material film 55, which is a main surface on the gap fill portion 14 formation side described later.
- the nitrogen concentration of the nitriding layer 12 formed in the above is higher than the average nitrogen concentration of the entire phase change material film 55.
- the nitrogen concentration of the nitriding layer 12 is preferably 20 at% or more.
- the present inventors have confirmed through experiments that nitrogen contained in the phase change material layer 11 is swept out of the phase change region from the phase change region by performing a rewrite operation of the phase change memory. . That is, even if the nitrogen concentration in the phase change region exceeds the nitrogen concentration suitable for rewriting in the phase change memory immediately after the completion of manufacturing (that is, before the start of the first energization), for example, the memory chip test process or the customer It is considered that the nitrogen concentration in the phase change region decreases and reaches a nitrogen concentration suitable for rewriting by performing the rewriting operation at the initial time of starting use.
- the gap fill portion 14 is formed in a region surrounded by the phase change material film 55.
- a schematic cross-sectional view at this point is shown in FIG.
- a coating method formation of an insulating film by curing a coating material for an insulating film
- a CVD method can be employed as a method of forming the gap fill portion 14.
- a coating method is preferably used.
- the coating material for the insulating film a material having low temperature curability is preferably used.
- the film forming temperature of the gap fill portion can be reduced to, for example, 200 ° C., and the deterioration of the phase change material during the manufacture of the phase change memory can be reduced. I can do it.
- phase change material it is preferable to use a material having a low water content as the insulating film coating material or the gap fill portion 14 after the curing reaction thereof.
- the gap fill portion 14 it is sufficient if it has at least an insulating property, and for example, a material made of SiO 2 is suitably used. If the constituent material of the gap fill part 14 is conductive, a current flows through the gap fill part 14, the resistance of the memory cell in the reset state (high resistance state) is lowered, and the resistance ratio is lowered. As a constituent material of the gap fill portion 14, it is needless to say that other insulating films mainly composed of SiO 2 and insulating films formed of Al 2 O 3 or low-k materials can be used. Yes.
- the film formation atmosphere during the formation of the insulating film is an oxidizing atmosphere, and the silicon wafer is heated to about 400 ° C. during the film formation.
- the phase change material 11 is oxidized in the film forming process of the fill portion 14.
- the temperature at the time of film formation by the CVD method can be lowered to about 300 ° C., in this case, the density of the obtained insulating film (gap fill portion 14) is lowered and formed on the upper surface of the insulating film. Adhesiveness with a layer to be formed is reduced. In this case, since the residual stress of the insulating film increases, film peeling easily occurs during manufacturing. As a result, the yield of the phase change memory decreases.
- phase change material layer 11 is exposed by the etch back, the phase change region of the phase change memory due to the exposure of the end face is slight because there is no phase change region in the vicinity of the end face.
- the nitriding treatment of the phase change material can be performed again after the end face is exposed. By doing so, it is possible to increase the number of times the phase change memory can be rewritten, thereby realizing a highly reliable phase change memory.
- an interlayer insulating film 16 is further formed on the surface from which unnecessary portions have been removed by etch back.
- a schematic cross-sectional view at this point is shown in FIG. Thereafter, the phase change memory is manufactured by a normal semiconductor manufacturing process.
- the phase change material film 55 of the three-dimensional type phase change memory cell according to the first embodiment has a main surface 551 adjacent to the gap fill portion 14 among the main surfaces (that is, the phase change).
- the nitriding layer 12 is formed on the main surface of the material film 55 on the main surface on the center side of the memory chain 61.
- phase change material layer 11 it is desirable to reduce the heat load after the phase change material layer 11 is formed. This makes it possible to prevent sublimation of the phase change material constituting the phase change material layer 11, non-uniform composition, and a decrease in density, thereby realizing a highly reliable phase change memory.
- the polysilicon channel 13 is used as the channel of the cell selection MOS.
- other semiconductors are used as the channel of the cell selection MOS. It goes without saying that it is possible.
- an oxide semiconductor in particular, indium gallium zinc oxide (IGZO), In 2 O 3 , SrTiO 3 , KTaO 3 , TiO 2 , Ge, GaAs, GaP, GaN, carbon (graphene, fullerene) , Diamond), chalcogenide semiconductors, in particular ZnTe, layered chalcogenides, transition metal dichalcogenides, and organic semiconductors, in particular porphyrins.
- the three-dimensional phase change memory manufacturing apparatus 170 includes a phase change material film forming chamber 171 that forms a phase change material layer by forming a phase change material in a vacuum state, and a nitride that is an oxidation-resistant insulator. Is formed in a vacuum state.
- the nitride forming chamber 181 performs nitriding treatment on the main surface of the phase change material layer 11 formed in the phase change material film forming chamber 171 or forms a nitride layer on the main surface.
- the phase change material film forming chamber 171 and the nitride forming chamber 181 are connected by a transfer chamber 174 so that a vacuum state can be maintained.
- the transfer chamber 174 further includes a load / unload chamber 173, and a deposition target such as a silicon wafer is introduced into the transfer chamber 174 from the evacuated load / unload chamber 173 and provided in the transfer chamber 174.
- the robot arm 175 is transported toward the phase change material film forming chamber 171 and the nitride forming chamber 181.
- a deposition target such as a silicon wafer is introduced from the evacuated load / unload chamber 173, and then the inside of the transfer chamber 174, the phase change material deposition chamber 171 and the nitride formation chamber 181 is in a high vacuum state.
- a deposition target such as a silicon wafer is introduced from the evacuated load / unload chamber 173, and then the inside of the transfer chamber 174, the phase change material deposition chamber 171 and the nitride formation chamber 181 is in a high vacuum state.
- the main surface of the phase change material layer 11 is formed in the nitride formation chamber 181 while maintaining the vacuum state. Is nitrided or a nitride layer is formed on this main surface.
- phase change material film 55 having the nitrided layer 12 is formed.
- nitride layer 241 is formed on the surface of phase change material layer 11, phase change material film 55 having phase change material layer 11 and nitride layer 241 is formed.
- phase change material layer 11 is not oxidized in the subsequent steps until the phase change material layer 11 is stabilized.
- a phase change memory can be manufactured. As a result, a highly reliable phase change memory can be realized.
- the three-dimensional phase change memory manufacturing apparatus 180 shown in FIG. 21 has a configuration including a nitridation chamber 172 for nitriding the main surface of the phase change material layer 11 as the nitride forming chamber 181.
- the configuration of is the same as that of the phase change memory manufacturing apparatus 170 shown in FIG.
- FIG. 22 is a schematic diagram of a manufacturing apparatus 190 that can manufacture a more reliable three-dimensional phase change memory.
- the three-dimensional phase change memory manufacturing apparatus 190 includes a phase change material film forming chamber 171, a nitriding chamber 172, a precleaning chamber 191, a heat treatment chamber 192, and a protective film CVD film forming chamber 193. .
- a silicon wafer as a film formation target is introduced into the load / unload chamber 173, and evacuation is performed in the load / unload chamber 173.
- the subsequent steps are performed in a reduced pressure atmosphere.
- the silicon wafer is transferred to the transfer chamber 174.
- the transfer chamber 174 is kept in a high vacuum state.
- the silicon wafer is transferred to the pre-cleaning chamber 191 by the robot arm 175 in the transfer chamber 174.
- the natural oxide film layer formed on the polysilicon of the polysilicon channel 13 which is the base for forming the phase change material layer is removed.
- the interface resistance between the polysilicon channel 13 and the phase change material layer 11 can be reduced, and the phase change with low operating voltage and low power consumption. Memory can be realized.
- the method for removing the natural oxide film layer As a method for removing the natural oxide film layer, it is preferable to use isotropic etching using plasma. By using plasma, it is possible to remove the natural oxide film of polysilicon that is insensitive to the hole bottom. Needless to say, the method for removing the natural oxide film layer formed on the polysilicon can be performed by hydrofluoric acid cleaning. When hydrofluoric acid cleaning is used, the process until the hydrofluoric acid cleaning step is performed under atmospheric pressure, and after the cleaning, the silicon wafer is transferred to the phase change material film formation chamber 171 via the load / unload chamber 173. good. Thereby, the whole manufacturing apparatus can be reduced in size and an inexpensive manufacturing apparatus can be realized.
- the silicon wafer is transferred to the phase change material film forming chamber 171 by the robot arm 175.
- the phase change material layer 11 is deposited on the polysilicon channel 13 by the phase change material deposition chamber 171.
- the silicon wafer is transferred to the nitriding chamber 172 by the robot arm 175.
- the main surface of the phase change material layer 11 is nitrided by the nitridation chamber 172.
- the phase change material film 55 having the nitriding layer 12 is formed.
- the total film thickness of the phase change material layer 11 and the nitriding layer 12 is slightly higher than that of the phase change material layer 11 before nitriding. To increase.
- the silicon wafer is transferred to the heat treatment chamber 192 by the robot arm 175.
- the heat treatment chamber 192 is kept at a high temperature in advance, and the temperature of the transferred silicon wafer rises quickly.
- the silicon wafer is annealed in vacuum by being held in a high-temperature heat treatment chamber 192 for a predetermined time.
- the phase change material film 55 (the phase change material layer 11 and the nitriding layer 12) is held at a high temperature, thereby releasing impurities such as hydrogen contained therein (degas in vacuum) and increasing the density. If the density of the phase change material layer 11 is low, voids are generated along with rewriting, and stable rewriting becomes difficult.
- the present inventors have experimented with hydrogen forward scattering analysis (HFS) and Rutherford backscattering analysis (RBS) that the phase change material formed by the CVD method contains hydrogen. Have confirmed. Furthermore, the present inventors have experimentally confirmed by thermal thermal spectroscopy (TDS) analysis that hydrogen contained in the phase change material layer 11 is released by the heat treatment.
- the temperature for the heat treatment is preferably about 400 ° C., for example. If the heat treatment temperature is too high, the phase change material sublimes, and if it is too low, the reduction of impurities is insufficient.
- the manufacturing time can be shortened when the heat treatment is performed after the nitriding treatment as compared with the case where the heat treatment is performed before and after the nitriding treatment.
- the heat treatment is preferably performed after the nitriding treatment.
- the heat treatment can be performed before the nitriding treatment, or that the heat treatment can be performed before and after the nitriding treatment.
- the heat treatment can be performed before the nitriding treatment, deformation of the phase change material layer 11 and the nitriding treatment layer 12 can be reduced when impurities such as hydrogen are released.
- the heat treatment temperature before nitriding is desirably about 200 ° C. If the heat treatment temperature is too high, the phase change material will sublime, and if it is too low, the reduction of impurities will be insufficient. Further, by performing before and after the nitriding treatment, the amount of impurities contained in the phase change material layer can be further reduced, and a phase change memory with higher reliability can be realized.
- the silicon wafer is transferred to the protective film CVD chamber 193 by the robot arm 175.
- the gap fill portion 14 is formed in the region surrounded by the phase change material film 55 by the protective film CVD chamber 193.
- the method of forming the gap fill portion 14 is not limited to CVD.
- the gap fill portion 14 may be formed by ALD or a coating method.
- the amount of oxidation of the phase change material can be reduced by consistently performing the steps before and after the phase change material film forming step in a reduced pressure atmosphere. As a result, a phase change memory having a large number of rewritable times can be realized.
- Example 2 an example of a three-dimensional phase change memory having a phase change part with more excellent heat resistance and oxidation resistance will be described with reference to FIGS.
- FIG. 23 is a schematic cross-sectional view in one step of the manufacturing method of the three-dimensional type phase change memory according to the second embodiment.
- Example 2 as shown in FIG. 23, the nitride layer 241 is formed so as to be in contact with the main surface 111 on the center side of the memory chain 61 among the main surfaces of the phase change material layer 11. Thereby, phase change material film 55 having phase change material layer 11 and nitride layer 241 is formed.
- the nitride layer 241 can be formed by the nitride forming chamber 181 of the three-dimensional phase change memory manufacturing apparatus 170 shown in FIG.
- the nitride constituting the nitride layer 241 may be an insulating material formed in a non-oxidizing atmosphere.
- SiN silicon nitride
- the nitride layer 241 may have any so-called oxidation resistance that prevents the phase change material layer 11 from being oxidized during the film formation, and may be insulative.
- As the nitride in addition to SiN, AlN, GaN, CrN, MgN, ZrN, MoN, and nitrides containing these and other elements can be used.
- the constituent material of the film formed on the main surface of the phase change material layer 11 is not limited to nitride, and is formed in a non-oxidizing atmosphere. Any insulating material may be used. For example, chalcogenide that is in an amorphous state and can maintain a high resistance state even through a manufacturing process such as ZnTe can be used.
- the nitride layer 241 is provided in direct contact with the main surface 111 of the phase change material layer 11, the heat resistance and oxidation resistance of the phase change material layer 11 are more efficiently improved. Can be improved.
- Example 2 is the same as Example 1 except that a nitride layer 241 is formed instead of the nitriding layer 12 as a region having an insulating material having oxidation resistance, and other phase changes are performed. Description of the configuration and manufacturing method of the memory is omitted.
- Example 3 an example of a three-dimensional type phase change memory having a phase change part with more excellent heat resistance and oxidation resistance and capable of being manufactured in a short period will be described with reference to FIG.
- FIG. 24 is a schematic cross-sectional view in one step of the manufacturing method of the three-dimensional type phase change memory according to the third embodiment.
- a nitride fill portion 242 is formed so as to be in contact with the main surface 111 of the phase change material layer 11. That is, the region surrounded by the phase change material layer 11 in the memory hole 52 is filled with the nitride fill portion 242.
- the nitride fill portion 242 prevents oxidation of the phase change material layer 11 and improves thermal stability, and it is necessary to form the gap fill portion 14 after the nitride fill portion 242 formation step. Absent. That is, the time required for manufacturing can be shortened by omitting the step of forming the gap fill portion 14.
- the nitride fill portion 242 can be formed, for example, by a coating method or a CVD method.
- the third embodiment is different from the first and second embodiments except that a nitride fill portion 242 is formed instead of the nitridation treatment layer 12 or the nitride layer 241 as a region having an oxidation resistant insulator.
- a nitride fill portion 242 is formed instead of the nitridation treatment layer 12 or the nitride layer 241 as a region having an oxidation resistant insulator.
- Phase change material layer 111 ... Main surface (main surface) of phase change material layer 11, 12 ... Nitrided layer, 13 ... Polysilicon channel, 131 ... Main surface of polysilicon channel 13, 14 ... Gap fill Part 15, cell selection gate electrode 16, 35 interlayer insulating film 17 upper electrode 18 gate insulating film 19 channel 32 base electrode 33 conductive electrode 36 laminating direction 41 Memory cell, 42 bit line, 43 word line, 51 phase change memory cell, 52 memory hole, 53 direction perpendicular to end face of phase change material film 55, main surface of phase change material film 55 , 55: phase change material film, 551: main surface of phase change material film 55, 61: memory chain, 62 ...
- phase change memory semiconductor memory device 171 ... phase change material deposition chamber, 172 ... nitriding chamber, 173 ... load / unload chamber, 174 ... transfer chamber, 175 ... robot arm, 181 ... nitride forming chamber, 191 ... precleaning chamber, 192 ... heat treatment chamber, 193 ... Protective film CVD deposition chamber, 221... Selected memory cell, 231... Phase change portion, 232... Polysilicon MOS, X1, X2, X3, Y1, Y2, Y3... Gate electrode, 241. Fill part
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Abstract
Provided is a semiconductor memory device having an excellent rewritability and high reliability. A semiconductor memory device having a memory chain 61, in which a plurality of phase-change memory cells 51 having a phase change material film 55 are serially connected, wherein the phase change material film 55 has an oxidation-resistant insulation layer 12 formed on the main surface side on the central side of the memory chain 61.
Description
本発明は、半導体記憶装置及びその製造方法並びに半導体記憶装置の製造装置に関し、特に電気的に書き換え可能な相変化メモリ及びその製造方法並びにその製造装置に関するものである。
The present invention relates to a semiconductor memory device, a manufacturing method thereof, and a manufacturing apparatus of a semiconductor memory device, and more particularly to an electrically rewritable phase change memory, a manufacturing method thereof, and a manufacturing apparatus thereof.
高密度集積メモリ装置として、相変化材料を記録層として用いる相変化メモリが提案されている。相変化メモリは、相変化材料の各状態（結晶相とアモルファス相）の抵抗の違いを情報として記憶するものであり、積層ゲート構造に蓄積された電荷量の違いにより情報を記憶する従来の記憶セルと異なり、記憶部において電荷保持のための厚さが求められず、また動作電圧が低いため、絶縁膜に対する厚さも求められないことから、積層ゲート構造の記憶セルの場合と比較して、微細化における制約が少ない。また、相変化メモリでは、アモルファス相と結晶相との抵抗値の差が大きく、これらの抵抗値の違いを読み出し信号として用いるため、センス動作が容易であり、読み出し速度は高速である。このため、相変化メモリは、将来にわたって高密度（大容量）でかつ高速のメモリ装置を提供できるものとして期待されている。
As a high-density integrated memory device, a phase change memory using a phase change material as a recording layer has been proposed. The phase change memory stores the difference in resistance of each state (crystalline phase and amorphous phase) of the phase change material as information, and the conventional memory that stores information by the difference in the amount of charge accumulated in the stacked gate structure. Unlike the cell, the thickness for holding the charge in the memory portion is not required, and since the operating voltage is low, the thickness for the insulating film is also not required, so compared to the case of the memory cell with a stacked gate structure, There are few restrictions on miniaturization. In the phase change memory, the difference in resistance value between the amorphous phase and the crystal phase is large, and the difference between these resistance values is used as a read signal, so that the sensing operation is easy and the read speed is high. Therefore, the phase change memory is expected to provide a high-density (large capacity) and high-speed memory device in the future.
例えば特許文献１には、記録層において、第１の部分より窒素の含有量が相対的に高い第２の部分を有することで、結晶状態及び非晶質状態を安定化し、かつ消費電力を低減するようにした不揮発性記憶装置の構成が開示されている。
For example, in Patent Document 1, the recording layer includes a second portion having a relatively higher nitrogen content than the first portion, thereby stabilizing the crystalline state and the amorphous state and reducing power consumption. A configuration of a non-volatile storage device configured as described above is disclosed.
相変化メモリセルの相変化材料としては、例えばＧｅ２Ｓｂ２Ｔｅ５に代表されるカルコゲナイドが適していることが知られている。このような相変化材料は、一般に熱安定性が低い点が問題点として指摘されている。例えば特許文献２には、相変化メモリセルの製造工程において、カルコゲナイト材料が、その低熱安定性により昇華するのを防止するため、カルコゲナイド材料層１１４の側壁に、シリコン窒化膜からなる側壁保護膜１２３を形成する技術が開示されている。
As a phase change material of the phase change memory cell, for example, chalcogenide represented by Ge 2 Sb 2 Te 5 is known to be suitable. It has been pointed out that such phase change materials generally have low thermal stability. For example, Patent Document 2 discloses a sidewall protective film 123 made of a silicon nitride film on the sidewall of the chalcogenide material layer 114 in order to prevent the chalcogenite material from sublimating due to its low thermal stability in the manufacturing process of the phase change memory cell. Techniques for forming the are disclosed.
また、相変化材料層は、その低熱安定性により、酸化による相変化特性の劣化が懸念されている。図１～２に示す平面型相変化メモリでは、相変化材料層３１の上面及び下面に、それぞれ金属材料からなる導電性電極３３及び下地電極３２が形成されている。図２に示す構成では、相変化領域は、相変化材料層３１のうち下地電極３２に接する面を中心にドーム状に形成される。平面型相変化メモリの相変化材料層３１においては、端面の領域が酸化され易いため、相変化材料層３１の下地電極３２側の面の面積を、下地電極３２の相変化材料層３１側の面の面積より大きく形成することで、下地電極３２との接触面を中心に形成される相変化領域を、相変化材料層３１の端面から隔離し、酸化による相変化特性の劣化を防止することが可能である。
Also, the phase change material layer is concerned about deterioration of phase change characteristics due to oxidation due to its low thermal stability. In the planar phase change memory shown in FIGS. 1 and 2, a conductive electrode 33 and a base electrode 32 made of a metal material are formed on the upper and lower surfaces of the phase change material layer 31, respectively. In the configuration shown in FIG. 2, the phase change region is formed in a dome shape with the surface of the phase change material layer 31 in contact with the base electrode 32 as the center. In the phase change material layer 31 of the planar phase change memory, since the end face region is easily oxidized, the area of the surface of the phase change material layer 31 on the base electrode 32 side is equal to the area of the base electrode 32 on the phase change material layer 31 side. By forming the surface area larger than the surface area, the phase change region formed around the contact surface with the base electrode 32 is isolated from the end face of the phase change material layer 31 to prevent deterioration of phase change characteristics due to oxidation. Is possible.
このような平面型相変化メモリに対し、近年、メモリの大容量化の観点から、三次元型の相変化メモリが注目されている。三次元型のメモリでは、絶縁性材料からなるギャップフィル部が、相変化材料層の主面に隣接するように形成されるため、ギャップフィル部１４の成膜時に、相変化材料が酸化されることがある。この場合、相変化材料の書き換え特性が劣化し、書き換え可能回数が低下する。
In recent years, a three-dimensional type phase change memory has been attracting attention from the viewpoint of increasing the capacity of the memory. In the three-dimensional memory, since the gap fill portion made of an insulating material is formed adjacent to the main surface of the phase change material layer, the phase change material is oxidized when the gap fill portion 14 is formed. Sometimes. In this case, the rewriting characteristics of the phase change material are deteriorated, and the number of rewritable times is reduced.
特許文献２の技術では、カルコゲナイド材料層１１４の側壁のみが保護されており、その主面は保護されていないため、カルコゲナイド材料層１１４の保護としては、必ずしも十分でなかった。また、特許文献２に開示されている相変化メモリセルは平面型であり、上記した三次元型の相変化メモリの製造時における、相変化材料の酸化の問題を解決できるものではなかった。すなわち、三次元型の相変化メモリでは、平面型の相変化メモリと比較して、相変化領域が酸化され易く、相変化材料の書き換え特性の劣化が懸念される課題がある。
In the technique of Patent Document 2, since only the side wall of the chalcogenide material layer 114 is protected and its main surface is not protected, the protection of the chalcogenide material layer 114 is not always sufficient. Further, the phase change memory cell disclosed in Patent Document 2 is a planar type, and cannot solve the problem of oxidation of the phase change material at the time of manufacturing the above-described three-dimensional type phase change memory. That is, in the three-dimensional type phase change memory, there is a problem that the phase change region is easily oxidized as compared with the planar type phase change memory, and the rewrite characteristics of the phase change material may be deteriorated.
そこで、本発明の目的は、書き換え特性に優れ、かつ信頼性の高い半導体記憶装置及びその製造方法並びにその製造装置を提供することである。
Therefore, an object of the present invention is to provide a semiconductor memory device having excellent rewriting characteristics and high reliability, a manufacturing method thereof, and a manufacturing device thereof.
本発明に係る半導体記憶装置の好ましい実施形態としては、相変化材料膜を有する複数の相変化メモリセルが直列に接続されたメモリチェーンを有する半導体記憶装置であって、前記相変化材料膜には、前記メモリチェーンの中心側の主面側に、耐酸化性を有する絶縁層が形成されていることを特徴とする。
A preferred embodiment of the semiconductor memory device according to the present invention is a semiconductor memory device having a memory chain in which a plurality of phase change memory cells having a phase change material film are connected in series, wherein the phase change material film includes An insulating layer having oxidation resistance is formed on the main surface side of the center side of the memory chain.
また、本発明に係る半導体記憶装置の製造方法の好ましい実施形態としては、下部電極上に、選択ゲート電極と相間絶縁膜とを交互に積層して積層体を形成し、前記積層体を貫通するメモリホールを形成し、前記メモリホール内の領域に、相変化材料を真空状態で成膜して相変化材料層を形成し、前記相変化材料層の主表面に、耐酸化性を有する絶縁層を形成することを特徴とする。
As a preferred embodiment of the method for manufacturing a semiconductor memory device according to the present invention, a stacked body is formed by alternately stacking select gate electrodes and interphase insulating films on the lower electrode, and penetrates the stacked body. A memory hole is formed, a phase change material is formed in a vacuum state in a region in the memory hole to form a phase change material layer, and an insulating layer having oxidation resistance is formed on a main surface of the phase change material layer It is characterized by forming.
また、本発明に係る半導体記憶装置の製造装置の好ましい実施形態としては、対象物に相変化材料を真空状態で製膜して相変化材料層を形成する相変化材料製膜チャンバと、前記相変化材料層が形成された前記対象物に、耐酸化性を有する絶縁物を真空状態で形成する絶縁物形成チャンバと、前記相変化材料製膜チャンバ内で前記相変化材料層が形成された前記対象物を、真空状態を維持しつつ前記絶縁物形成チャンバに搬送する搬送室と、を有することを特徴とする。
Further, as a preferred embodiment of the semiconductor memory device manufacturing apparatus according to the present invention, a phase change material film forming chamber for forming a phase change material layer by forming a phase change material on an object in a vacuum state; An insulator forming chamber for forming an insulating material having oxidation resistance in a vacuum state on the object on which the change material layer is formed, and the phase change material layer formed in the phase change material deposition chamber. And a transfer chamber for transferring the object to the insulator forming chamber while maintaining a vacuum state.
本発明によれば、書き換え特性に優れ、信頼性の高い半導体記憶装置及びその製造方法並びにその製造装置を実現することができる。
According to the present invention, a highly reliable semiconductor memory device having excellent rewrite characteristics, a manufacturing method thereof, and a manufacturing device thereof can be realized.
以下に、相変化メモリの基本的な構成について説明する。
相変化メモリの記録層に用いられる相変化材料は、電気抵抗が高い高抵抗相（アモルファス相。以下、アモルファス相とする。）と、高抵抗相よりも電気抵抗が低い結晶相（アモルファス相より抵抗の低い結晶相。以下、結晶相とする。）の２つの準安定な状態を有している。相変化メモリは、アモルファス相と結晶相の抵抗の違いを「０」と「１」に対応させることで情報を記憶する。相変化材料がアモルファス相のときは、結晶相のときと比較すると、その電気抵抗値（以下、単位抵抗値と示す。）が概ね２桁から３桁も高い値を示す。 The basic configuration of the phase change memory will be described below.
The phase change material used for the recording layer of the phase change memory includes a high resistance phase (amorphous phase, hereinafter referred to as an amorphous phase) having a high electrical resistance and a crystal phase (amorphous phase lower than the high resistance phase). The crystal phase has a low resistance (hereinafter referred to as a crystal phase). The phase change memory stores information by making the difference in resistance between the amorphous phase and the crystalline phase correspond to “0” and “1”. When the phase change material is in an amorphous phase, the electric resistance value (hereinafter referred to as a unit resistance value) is approximately 2 to 3 digits higher than that in the crystalline phase.
相変化メモリの記録層に用いられる相変化材料は、電気抵抗が高い高抵抗相（アモルファス相。以下、アモルファス相とする。）と、高抵抗相よりも電気抵抗が低い結晶相（アモルファス相より抵抗の低い結晶相。以下、結晶相とする。）の２つの準安定な状態を有している。相変化メモリは、アモルファス相と結晶相の抵抗の違いを「０」と「１」に対応させることで情報を記憶する。相変化材料がアモルファス相のときは、結晶相のときと比較すると、その電気抵抗値（以下、単位抵抗値と示す。）が概ね２桁から３桁も高い値を示す。 The basic configuration of the phase change memory will be described below.
The phase change material used for the recording layer of the phase change memory includes a high resistance phase (amorphous phase, hereinafter referred to as an amorphous phase) having a high electrical resistance and a crystal phase (amorphous phase lower than the high resistance phase). The crystal phase has a low resistance (hereinafter referred to as a crystal phase). The phase change memory stores information by making the difference in resistance between the amorphous phase and the crystalline phase correspond to “0” and “1”. When the phase change material is in an amorphous phase, the electric resistance value (hereinafter referred to as a unit resistance value) is approximately 2 to 3 digits higher than that in the crystalline phase.
以下、相変化材料がアモルファスであり、記憶部の抵抗が高い状態をリセット状態と示し、相変化材料が結晶であり、記憶部の抵抗が低い状態をセット状態と示す。また、以下、「０」をリセット状態、すなわちアモルファス相とし、「１」をセット状態、すなわち結晶相とする。
Hereinafter, a state in which the phase change material is amorphous and the resistance of the memory portion is high is referred to as a reset state, and a state in which the phase change material is a crystal and the resistance of the memory portion is low is referred to as a set state. Hereinafter, “0” is a reset state, that is, an amorphous phase, and “1” is a set state, that is, a crystal phase.
次に、相変化メモリの動作原理を簡単に説明する。
相変化メモリの情報の読み出しは、相変化材料に低電圧を印加して相変化材料を通過する電流値を測定し、相変化材料の抵抗値を読み取って、情報を識別することにより行う。このとき、相変化材料に印加する電圧は低いため、相変化材料の相状態は変化しない。 Next, the operation principle of the phase change memory will be briefly described.
Reading information from the phase change memory is performed by applying a low voltage to the phase change material, measuring a current value passing through the phase change material, reading a resistance value of the phase change material, and identifying the information. At this time, since the voltage applied to the phase change material is low, the phase state of the phase change material does not change.
相変化メモリの情報の読み出しは、相変化材料に低電圧を印加して相変化材料を通過する電流値を測定し、相変化材料の抵抗値を読み取って、情報を識別することにより行う。このとき、相変化材料に印加する電圧は低いため、相変化材料の相状態は変化しない。 Next, the operation principle of the phase change memory will be briefly described.
Reading information from the phase change memory is performed by applying a low voltage to the phase change material, measuring a current value passing through the phase change material, reading a resistance value of the phase change material, and identifying the information. At this time, since the voltage applied to the phase change material is low, the phase state of the phase change material does not change.
相変化メモリの書換えは、相変化材料自体、若しくはこれに近接するヒータに電流を流し、相変化材料にジュール熱を発生させることにより行う。
The rewriting of the phase change memory is performed by causing a current to flow through the phase change material itself or a heater adjacent thereto to generate Joule heat in the phase change material.
相変化部（例えば相変化材料層）をアモルファス相にする場合、相変化材料を融点以上に熱してから急冷するパルスを印可する。相変化材料の融点は例えば６００℃程度であり、急冷時間は例えば３ｎｓｅｃ（ナノ秒）程度である。相変化部を結晶相にする場合、局所的に相変化部の温度を結晶化温度以上、融点以下の温度に保持する。このときの温度は例えば４００℃である。結晶化に要する時間は相変化材料の組成によって異なるが、例えば５０ｎｓｅｃである。
When applying a phase change part (for example, a phase change material layer) to an amorphous phase, a pulse that rapidly cools the phase change material after heating it above the melting point is applied. The melting point of the phase change material is, for example, about 600 ° C., and the rapid cooling time is, for example, about 3 nsec (nanoseconds). When the phase change part is made into a crystal phase, the temperature of the phase change part is locally maintained at a temperature not lower than the crystallization temperature and not higher than the melting point. The temperature at this time is 400 ° C., for example. The time required for crystallization varies depending on the composition of the phase change material, but is, for example, 50 nsec.
以後、相変化材料を結晶化させることをセット動作と示し、相変化材料をアモルファス化させることをリセット動作と示す。また、リセット動作を行う際にメモリセルに流す電流をリセット電流と呼ぶ。
Hereinafter, crystallization of the phase change material is referred to as a set operation, and amorphization of the phase change material is referred to as a reset operation. In addition, a current that flows through the memory cell when performing the reset operation is referred to as a reset current.
次に、本発明の三次元型の相変化メモリの特徴の比較のため、本発明以前の例の三次元型メモリの問題点について説明する。なお、便宜上、図３、１３、１４を参照する。
Next, in order to compare the characteristics of the three-dimensional phase change memory of the present invention, problems of the three-dimensional memory of the example before the present invention will be described. For convenience, FIGS. 3, 13, and 14 are referred to.
第１の問題点は、相変化メモリの製造工程時における、相変化材料の酸化の問題である。図１３は、三次元型相変化メモリの製造方法の一工程における断面を示す模式図である。図１３では、不図示のシリコンウェハ上に、Ｘチェーン選択素子６４のチャネル１９が形成されており、Ｘチェーン選択素子６４と上部電極１７との間には、セル選択ゲート電極１５と層間絶縁膜１６との積層体が形成されている。
The first problem is the problem of oxidation of the phase change material during the manufacturing process of the phase change memory. FIG. 13 is a schematic view showing a cross section in one step of the method of manufacturing the three-dimensional phase change memory. In FIG. 13, the channel 19 of the X chain selection element 64 is formed on a silicon wafer (not shown). Between the X chain selection element 64 and the upper electrode 17, a cell selection gate electrode 15 and an interlayer insulating film are formed. 16 is formed.
メモリホール５２は、上部電極１７、及びセル選択ゲート電極１５と層間絶縁膜１６との積層体を貫通するように形成されている。メモリホール５２の側壁にはゲート絶縁膜１８が形成されており、ゲート絶縁膜１８の一方の主面には、ポリシリコンチャネル１３が形成されている。
The memory hole 52 is formed so as to penetrate the upper electrode 17 and the stacked body of the cell selection gate electrode 15 and the interlayer insulating film 16. A gate insulating film 18 is formed on the side wall of the memory hole 52, and a polysilicon channel 13 is formed on one main surface of the gate insulating film 18.
図１３の次工程では、図１４に示すように、ポリシリコンチャネル１３の一方の主面に相変化材料層１１を成膜する。さらにその次工程では、図３に示すように、相変化材料層１１の一方の主面に直接接触させるように、絶縁性のギャップフィル部１４を成膜するが、この工程での相変化材料の酸化が問題となる。
In the next step of FIG. 13, as shown in FIG. 14, the phase change material layer 11 is formed on one main surface of the polysilicon channel 13. Further, in the next step, as shown in FIG. 3, an insulating gap fill portion 14 is formed so as to be in direct contact with one main surface of the phase change material layer 11. Oxidation is a problem.
ギャップフィル部１４の形成方法には、大別して２種類ある。一つは塗布法により形成する方法であり、他の一つはＣＶＤ法により形成する方法である。すなわち、ギャップフィル部１４は、絶縁膜用塗布材料の硬化による絶縁膜か、又はＣＶＤ法により成膜された絶縁膜に大別される。
There are roughly two types of methods for forming the gap fill portion 14. One is a method of forming by a coating method, and the other is a method of forming by a CVD method. That is, the gap fill portion 14 is roughly classified into an insulating film formed by curing an insulating film coating material or an insulating film formed by a CVD method.
塗布法では、絶縁膜用塗布材料を、スピンコート法により相変化材料層１１上に塗布することで、ギャップフィル部１４を形成する。このとき、相変化材料層１１は、絶縁膜用塗布材料に含まれる水分や、絶縁膜用塗布材料が硬化するときに放出される水分により、ギャップフィル部１４との接触面を中心に、塗布型絶縁膜の形成工程や、その後の配線工程において酸化される。一方、ＣＶＤ法では、成膜雰囲気は酸化雰囲気となり、またシリコンウェハは４００℃程度に加熱されるため、相変化材料層１１は、ギャップフィル部１４の形成過程において酸化される。このように相変化材料層１１が酸化されると、酸化領域において、相変化特性が失われる。
In the coating method, the gap fill portion 14 is formed by coating a coating material for an insulating film on the phase change material layer 11 by a spin coating method. At this time, the phase change material layer 11 is applied around the contact surface with the gap fill portion 14 due to moisture contained in the insulating film coating material or moisture released when the insulating film coating material is cured. It is oxidized in the mold insulating film forming process and the subsequent wiring process. On the other hand, in the CVD method, the film forming atmosphere is an oxidizing atmosphere, and the silicon wafer is heated to about 400 ° C., so that the phase change material layer 11 is oxidized in the process of forming the gap fill portion 14. When the phase change material layer 11 is oxidized in this way, phase change characteristics are lost in the oxidized region.
相変化材料の酸素含有量と、相変化メモリの書き換え可能回数との関係を図４に示す。本発明者らの実験による検討の結果、図４に示すように、相変化材料の酸素含有量の増加に伴い、相変化メモリにおける書換え可能回数が低下することが確認されている。すなわち、ギャップフィル部１４の形成に伴い、相変化材料が酸化されることで、相変化材料の書換え特性が劣化し、特に書換え可能回数が低下する。
Fig. 4 shows the relationship between the oxygen content of the phase change material and the number of times the phase change memory can be rewritten. As a result of examinations by the inventors, it has been confirmed that the number of rewritable times in the phase change memory decreases as the oxygen content of the phase change material increases as shown in FIG. That is, as the gap fill portion 14 is formed, the phase change material is oxidized, so that the rewritable characteristics of the phase change material deteriorate, and in particular, the number of rewritable times decreases.
相変化材料の書換え特性の劣化について、さらに詳細に説明する。図１４に示す領域１０１の拡大図を図５に示す。図５には、相変化メモリの書換え動作時に相変化する領域１２１が示されている。相変化領域１２１は、「０」書き込みや「１」書き込み、すなわちリセット動作やセット動作において、その相状態がアモルファス相若しくは結晶相に変化する相である。
Deterioration of the rewrite characteristics of phase change materials will be described in more detail. FIG. 5 shows an enlarged view of the region 101 shown in FIG. FIG. 5 shows a region 121 where the phase changes during the rewrite operation of the phase change memory. The phase change region 121 is a phase in which the phase state changes to an amorphous phase or a crystalline phase in “0” writing or “1” writing, that is, in a reset operation or a set operation.
図５に示すように、領域１０１の相変化材料層１１の上部１２２から下部１２３に至る経路において、相変化領域１２１を経由せずに下部１２３に至る経路が存在しないようにすることがよい。
As shown in FIG. 5, in the path from the upper part 122 to the lower part 123 of the phase change material layer 11 in the area 101, it is preferable that there is no path to the lower part 123 without passing through the phase change area 121.
すなわち、上部１２２から下部１２３に至るまでに、相変化領域１２１を経由しない経路が存在すると、仮にその経路が低抵抗である場合、リセット状態（高抵抗状態）において、この低抵抗の経路を通じて電流が流れることでメモリセルの抵抗が低くなる。この場合、リセット状態のセット状態との抵抗比が小さくなる。一方、仮に相変化領域１２１を経由しない経路が高抵抗である場合、セット状態（低抵抗状態）において、この高抵抗の経路に電流が流れず、メモリセルの抵抗が高くなる。この場合、セット状態のリセット状態との抵抗比が小さくなる。このように、セット状態とリセット状態との抵抗比が小さくなると、その分読み出しマージンが小さくなり、安定した読み出し動作が困難となり、相変化メモリとしての信頼性が低下する。
That is, if there is a path that does not pass through the phase change region 121 from the upper part 122 to the lower part 123, if the path has a low resistance, the current flows through the low resistance path in the reset state (high resistance state). The resistance of the memory cell is lowered. In this case, the resistance ratio between the reset state and the set state becomes small. On the other hand, if the path that does not pass through the phase change region 121 has a high resistance, current does not flow through the high resistance path in the set state (low resistance state), and the resistance of the memory cell increases. In this case, the resistance ratio between the set state and the reset state becomes small. Thus, when the resistance ratio between the set state and the reset state is reduced, the read margin is reduced accordingly, and a stable read operation becomes difficult, and the reliability as the phase change memory is lowered.
上記した不具合を防止するためには、相変化材料層１１のメモリチェーン側壁側の主面（図５中左側の主面）から、メモリチェーンの中心側の主面（図５中右側の主面）に至るまでの厚さ方向全域が、相変化領域１２１である必要がある。特に上記したように、相変化材料層の主面のうち、メモリチェーンの中心側の主面は、ギャップフィル部１４の形成時に酸化され易いことから、この主面近傍の酸化と、これに伴う相変化領域の縮小を防止することが課題となる。
In order to prevent the above problems, the main surface of the phase change material layer 11 on the side wall side of the memory chain (main surface on the left side in FIG. 5) is changed to the main surface on the center side of the memory chain (main surface on the right side in FIG. 5). The entire region in the thickness direction up to) needs to be the phase change region 121. In particular, as described above, of the main surfaces of the phase change material layer, the main surface on the center side of the memory chain is easily oxidized when the gap fill portion 14 is formed. It is a problem to prevent the phase change region from being reduced.
第２の問題点は、相変化材料の昇華の問題である。
図６に、ＧｅＳｂＴｅ膜の昇温脱離ガスマス分析（Ｔｈｅｒｍａｌ Ｄｅｓｏｒｐｔｉｏｎ Ｓｐｅｃｔｒｏｍｅｔｒｙ，ＴＤＳ）の分析結果を示す。分析は、１０－７Ｐａ程度の超高真空中で行い、図２では、Ｇｅの分析結果について示した。ＧｅＳｂＴｅ膜を加熱すると、３００℃程度の温度でＧｅが昇華することが確認できる。なお、同様の分析により、Ｓｂ、Ｔｅについても、Ｇｅと同様に昇華することが確認されている。 The second problem is the problem of sublimation of the phase change material.
FIG. 6 shows an analysis result of thermal desorption gas mass analysis (TDS) of the GeSbTe film. The analysis was performed in an ultrahigh vacuum of about 10 −7 Pa, and FIG. 2 shows the result of Ge analysis. When the GeSbTe film is heated, it can be confirmed that Ge sublimates at a temperature of about 300 ° C. In addition, it is confirmed by the same analysis that Sb and Te are sublimated similarly to Ge.
図６に、ＧｅＳｂＴｅ膜の昇温脱離ガスマス分析（Ｔｈｅｒｍａｌ Ｄｅｓｏｒｐｔｉｏｎ Ｓｐｅｃｔｒｏｍｅｔｒｙ，ＴＤＳ）の分析結果を示す。分析は、１０－７Ｐａ程度の超高真空中で行い、図２では、Ｇｅの分析結果について示した。ＧｅＳｂＴｅ膜を加熱すると、３００℃程度の温度でＧｅが昇華することが確認できる。なお、同様の分析により、Ｓｂ、Ｔｅについても、Ｇｅと同様に昇華することが確認されている。 The second problem is the problem of sublimation of the phase change material.
FIG. 6 shows an analysis result of thermal desorption gas mass analysis (TDS) of the GeSbTe film. The analysis was performed in an ultrahigh vacuum of about 10 −7 Pa, and FIG. 2 shows the result of Ge analysis. When the GeSbTe film is heated, it can be confirmed that Ge sublimates at a temperature of about 300 ° C. In addition, it is confirmed by the same analysis that Sb and Te are sublimated similarly to Ge.
分析後、６００℃まで加熱した試料（ＧｅＳｂＴｅ膜）を室温まで冷却して分析装置から取り出したところ、ＧｅＳｂＴｅ膜は完全に消失していた。このように、カルコゲナイド材料は熱安定性が極めて低く、この点が、相変化メモリセルの製造時及び使用時における安定性において問題となっている。
After the analysis, when the sample (GeSbTe film) heated to 600 ° C. was cooled to room temperature and taken out from the analyzer, the GeSbTe film was completely disappeared. As described above, the chalcogenide material has extremely low thermal stability, which is a problem in the stability during the manufacture and use of the phase change memory cell.
なお、平面型の相変化メモリにおいては、相変化材料の昇華は大きな問題とはならない。この点について、図１～２の模式図を用いて以下に説明する。図１は、平面型メモリの概略構造を示す平面模式図であり、図２は、図１のＩ－Ｉ´線断面図である。
It should be noted that sublimation of the phase change material is not a big problem in the planar type phase change memory. This point will be described below with reference to the schematic diagrams of FIGS. FIG. 1 is a schematic plan view showing a schematic structure of the planar memory, and FIG. 2 is a cross-sectional view taken along the line II ′ of FIG.
図１に示すように、平面型メモリのメモリセル４１は、ビット線４２とワード線４３の交点に形成されている。メモリセル４１の選択は、メモリセル毎に設けられた不図示の選択素子、例えばダイオード素子により行われる。平面型相変化メモリにおいては、下地電極３２上に相変化材料層３１が成膜された後、相変化材料層３１の主面に導電性電極３３が形成される。下地電極３２、相変化材料層３１及び導電性電極３３の積層体の間の領域は、層間絶縁膜３５により充填されている。図１の断面においては、層間絶縁膜３５及び導電性電極３３の上面に、ビット線３４が形成されている。
As shown in FIG. 1, the memory cell 41 of the planar memory is formed at the intersection of the bit line 42 and the word line 43. Selection of the memory cell 41 is performed by a selection element (not shown) provided for each memory cell, for example, a diode element. In the planar phase change memory, after the phase change material layer 31 is formed on the base electrode 32, the conductive electrode 33 is formed on the main surface of the phase change material layer 31. A region between the stacked body of the base electrode 32, the phase change material layer 31 and the conductive electrode 33 is filled with an interlayer insulating film 35. In the cross section of FIG. 1, a bit line 34 is formed on the upper surfaces of the interlayer insulating film 35 and the conductive electrode 33.
なお、図２において「主面」とは、下地電極３２上への相変化材料層３１の積層方向３６（図２における上下方向）に対して垂直な面をいう。また、図２に示す構成において、相変化膜が有する２つの主面のうち、相変化膜下地（図２の構成では下地電極３２）と接していない方の主面を表面という。
In FIG. 2, “main surface” refers to a surface perpendicular to the stacking direction 36 (vertical direction in FIG. 2) of the phase change material layer 31 on the base electrode 32. In the configuration shown in FIG. 2, of the two main surfaces of the phase change film, the main surface that is not in contact with the phase change film base (the base electrode 32 in the configuration of FIG. 2) is referred to as the surface.
なお、相変化材料層３１において、導電性電極３３の形成側の主面（すなわち表面）に対向するもう一方の主面は、下地に接する面となる。すなわち、下地面とは、相変化材料層３１が被着された下地における、相変化材料層の被着面であり、相変化材料３１の成膜前に形成されている。図２の場合は下地電極３２が下地となる。
In the phase change material layer 31, the other main surface facing the main surface (that is, the surface) on the side where the conductive electrode 33 is formed is a surface in contact with the base. That is, the base surface is a surface on which the phase change material layer 31 is applied, and is formed on the base surface of the phase change material layer 31 before the phase change material 31 is formed. In the case of FIG. 2, the base electrode 32 is the base.
このような平面型相変化メモリでは、以下の理由から、相変化材料層３１の主面に形成された導電性電極３３により、相変化材料層３１の昇華が防止される。すなわち、図２に示す構成において、相変化材料が加熱されてその一部がわずかに昇華しても、導電性電極３３、下地電極３２、層間絶縁膜３５は略変形しないため、昇華により気化した相変化材料のガス圧力が、相変化メモリ内で急上昇する。相変化メモリ内のガス圧が上昇すると、その分、昇華に必要とされる温度も上昇することから、昇華温度と加熱温度が同等となったとき、熱力的な平衡状態に到達する。熱力学的な平衡状態に達すると、相変化材料はそれ以上昇華しなくなる。
In such a planar phase change memory, sublimation of the phase change material layer 31 is prevented by the conductive electrode 33 formed on the main surface of the phase change material layer 31 for the following reason. That is, in the configuration shown in FIG. 2, even if the phase change material is heated and a part of the phase change material is slightly sublimated, the conductive electrode 33, the base electrode 32, and the interlayer insulating film 35 are not substantially deformed. The gas pressure of the phase change material jumps in the phase change memory. When the gas pressure in the phase change memory increases, the temperature required for sublimation also increases accordingly, so that when the sublimation temperature becomes equal to the heating temperature, a thermodynamic equilibrium state is reached. Once the thermodynamic equilibrium is reached, the phase change material will no longer sublime.
なお、仮に相変化材料の端面が開放されている場合でも、端面の面積は、導電性電極３３と下地電極３２により抑えられている主面の面積と比較して小さいため、上記したのと同様の理由から、相変化材料が昇華する割合は少なくなる。ここで「端面」とは、主面に対して垂直な面をいう。
Even if the end face of the phase change material is open, the area of the end face is smaller than the area of the main surface suppressed by the conductive electrode 33 and the base electrode 32, and thus the same as described above. For this reason, the rate at which the phase change material sublimes decreases. Here, the “end face” refers to a plane perpendicular to the main surface.
半導体集積回路装置では、４００℃程度に加熱される配線工程が必要とされるため、熱的に不安定なカルコゲナイド材料を取り入れるには注意が必要であるが、上記した理由から、平面型相変化メモリセルでは、相対的に重要な問題とはならなかった。なお、半導体集積回路装置の製造工程において、例えば化学的気相成長法で用いられる温度は４００～７００℃程度である。
Since a semiconductor integrated circuit device requires a wiring process heated to about 400 ° C., care must be taken to incorporate a thermally unstable chalcogenide material. In memory cells, it was not a relatively important issue. In the manufacturing process of the semiconductor integrated circuit device, for example, the temperature used in the chemical vapor deposition method is about 400 to 700 ° C.
以下の本発明の実施形態について、図面を参照して説明する。
まず、図７～８を用いて、実施例１の半導体記憶装置である三次元型相変化メモリの構成例を説明する。図７は、実施例１の三次元型相変化メモリの全体構成を示す鳥瞰図であり、図８は、図７に示す三次元型相変化メモリの断面の一部を示す模式図である。 Embodiments of the present invention will be described with reference to the drawings.
First, a configuration example of a three-dimensional phase change memory that is the semiconductor memory device ofEmbodiment 1 will be described with reference to FIGS. FIG. 7 is a bird's-eye view showing the overall configuration of the three-dimensional phase change memory according to the first embodiment, and FIG. 8 is a schematic diagram showing a part of a cross section of the three-dimensional phase change memory shown in FIG.
まず、図７～８を用いて、実施例１の半導体記憶装置である三次元型相変化メモリの構成例を説明する。図７は、実施例１の三次元型相変化メモリの全体構成を示す鳥瞰図であり、図８は、図７に示す三次元型相変化メモリの断面の一部を示す模式図である。 Embodiments of the present invention will be described with reference to the drawings.
First, a configuration example of a three-dimensional phase change memory that is the semiconductor memory device of
図７に示すように、上部電極１７と下部電極６３との間には、下部電極６３側から順に、Ｙチェーン選択素子６２、Ｘチェーン選択素子６４が設けられている。メモリチェーン６１は、上部電極１７とＸチェーン選択素子６４との間に複数列設けられている。
As shown in FIG. 7, between the upper electrode 17 and the lower electrode 63, a Y chain selection element 62 and an X chain selection element 64 are provided in this order from the lower electrode 63 side. The memory chain 61 is provided in a plurality of rows between the upper electrode 17 and the X chain selection element 64.
以下に、メモリチェーン６１の構成について図８を用いて説明する。上部電極１７と下部電極６３との間には、セル選択ゲート電極１５と層間絶縁膜１６とが交互に複数層積層されており、これらの積層体及び上部電極１７を、その積層方向に貫通するように、メモリホール５２が形成されている。
Hereinafter, the configuration of the memory chain 61 will be described with reference to FIG. A plurality of cell selection gate electrodes 15 and interlayer insulating films 16 are alternately stacked between the upper electrode 17 and the lower electrode 63, and penetrate through these stacked bodies and the upper electrode 17 in the stacking direction. Thus, a memory hole 52 is formed.
メモリホール５２内には、その側壁側から順に、ゲート絶縁膜１８、ポリシリコンチャネル１３、及び相変化材料層と耐酸化性を有する絶縁層の積層５５（以下、相変化材料膜５５と示す。）相変化材料と保護膜の積層５５が、メモリホール５２の側壁側から順に積層されており、相変化材料膜５５で囲まれた領域には、ギャップフィル部１４が形成されている。
In the memory hole 52, the gate insulating film 18, the polysilicon channel 13, and a stacked layer 55 of a phase change material layer and an insulating layer having oxidation resistance (hereinafter referred to as a phase change material film 55) are sequentially formed from the side wall side. ) A stack 55 of phase change material and protective film is stacked in order from the side wall side of the memory hole 52, and a gap fill portion 14 is formed in a region surrounded by the phase change material film 55.
相変化メモリセル５１は、メモリホール５２内に形成されたゲート絶縁膜１８、ポリシリコンチャネル１３、及び相変化材料膜５５で構成される積層体において、セル選択ゲート電極１５の層毎に設けられている。すなわち、相変化材料膜５５は、ゲート絶縁膜１８を介して、セル選択ゲート電極１５と接続されている。
The phase change memory cell 51 is provided for each layer of the cell selection gate electrode 15 in the stacked body formed of the gate insulating film 18, the polysilicon channel 13, and the phase change material film 55 formed in the memory hole 52. ing. That is, the phase change material film 55 is connected to the cell selection gate electrode 15 via the gate insulating film 18.
メモリチェーン６１は、このような相変化メモリセル５１の複数個が、セル選択ゲート電極１５と層間絶縁膜１６の積層方向に直列に接続されて構成されている。
The memory chain 61 is configured by connecting a plurality of such phase change memory cells 51 in series in the stacking direction of the cell selection gate electrode 15 and the interlayer insulating film 16.
なお、以下の説明において、相変化材料膜５５の主面とは、セル選択ゲート電極１５と層間絶縁膜１６との積層方向に延在する面をいう。
In the following description, the main surface of the phase change material film 55 refers to a surface extending in the stacking direction of the cell selection gate electrode 15 and the interlayer insulating film 16.
図８には、相変化材料膜５５の端面と垂直をなす方向５３及び相変化材料膜５５の主面と垂直をなす方向５４を示している。
FIG. 8 shows a direction 53 perpendicular to the end face of the phase change material film 55 and a direction 54 perpendicular to the main surface of the phase change material film 55.
図９は、実施例１の三次元型相変化メモリの等価回路の一部を示す図である。図９に示すように、メモリセル５１は、相変化部２３１とポリシリコンＭＯＳ２３２が並列に接続されて構成されている。
FIG. 9 is a diagram illustrating a part of an equivalent circuit of the three-dimensional type phase change memory according to the first embodiment. As shown in FIG. 9, the memory cell 51 is configured by connecting a phase change unit 231 and a polysilicon MOS 232 in parallel.
次に、メモリチェーン６１の選択方法について、リセット動作（すなわちライト動作、「０」書き込み動作、高抵抗化動作。）の場合を例に、図１０を用いて説明する。メモリチェーン６１はＸチェーン選択素子６４及びＹチェーン選択素子６２（図７参照。）を用いて選択される。
Next, the selection method of the memory chain 61 will be described with reference to FIG. 10 by taking as an example the case of a reset operation (that is, a write operation, a “0” write operation, a high resistance operation). The memory chain 61 is selected using an X chain selection element 64 and a Y chain selection element 62 (see FIG. 7).
Ｘチェーン選択素子６４では、その選択素子のゲート電極Ｘ１、Ｘ２、Ｘ３にオン電圧又はオフ電圧が印加されることにより選択動作が行われる。Ｙチェーン選択素子６２では、その選択素子のゲート電極Ｙ１、Ｙ２、Ｙ３にオン電圧又はオフ電圧が印加されることにより、選択動作が行われる。
In the X chain selection element 64, a selection operation is performed by applying an on voltage or an off voltage to the gate electrodes X1, X2, and X3 of the selection element. In the Y chain selection element 62, a selection operation is performed by applying an on voltage or an off voltage to the gate electrodes Y1, Y2, and Y3 of the selection element.
Ｘチェーン選択素子６４とＹチェーン選択素子６２はダブルゲートのポリシリコンＭＯＳとなっている。すなわち、１つのＭＯＳにつき、２つのゲート電極が存在しており、さらにＭＯＳのチャネル膜厚が薄いため、この２つのゲート電極にともにオン電圧が印加されたときのみＭＯＳがオンする。そのほかの場合、すなわち、ゲート電極の一方にオン電圧が印加され、もう一方にオフ電圧が印加された場合や、２つのゲート電極にともにオフ電圧が印加された場合には、ＭＯＳはオフする。例えばＭＯＳのソース電圧を－７．５としたとき、オン電圧の例は０Ｖであり、オフ電圧の例は－７．５Ｖである。
The X chain selection element 64 and the Y chain selection element 62 are double gate polysilicon MOS. That is, since there are two gate electrodes for each MOS and the channel thickness of the MOS is thin, the MOS is turned on only when an on-voltage is applied to the two gate electrodes. In other cases, that is, when an on-voltage is applied to one of the gate electrodes and an off-voltage is applied to the other, or when an off-voltage is applied to both of the two gate electrodes, the MOS is turned off. For example, when the source voltage of the MOS is −7.5, an example of the on voltage is 0V, and an example of the off voltage is −7.5V.
ＭＯＳがオンの場合には低抵抗状態となり、ＭＯＳがオフの場合には高抵抗状態となる。Ｘチェーン選択素子６４とＹチェーン選択素子６２は直列に接続されており、両方がオンすることで、電子が下部電極６３からＹチェーン選択素子６２、Ｘチェーン選択素子６４、メモリチェーン６１を通って、上部電極１７に流れる。電流の流れる方向が電子の方向と逆であることは言うまでもない。このときにメモリチェーン６１内の選択メモリセル２２１にパルス電流が印加されて、選択メモリセル２２１のライト動作が行われる。
When the MOS is on, the resistance state is low, and when the MOS is off, the resistance state is high. The X chain selection element 64 and the Y chain selection element 62 are connected in series. When both are turned on, electrons pass from the lower electrode 63 through the Y chain selection element 62, the X chain selection element 64, and the memory chain 61. To the upper electrode 17. Needless to say, the direction of current flow is opposite to the direction of electrons. At this time, a pulse current is applied to the selected memory cell 221 in the memory chain 61, and the selected memory cell 221 is written.
次に、メモリチェーン６１内のメモリセルの選択動作について図９～１０を用いて説明する。
選択メモリセル２２１に接続されたセル選択ゲート電極１５にオフ電圧を印加し、選択メモリセル２２１のポリシリコンＭＯＳ２３２にチャネルを誘起しないようにして、ポリシリコンＭＯＳ２３２に電流を流さず、相変化部２３１に電流を流す。なお、非選択メモリセルに接続されたセル選択ゲート電極１５にオン電圧を印加し、選択メモリセルのポリシリコンＭＯＳ２３２にチャネルを誘起することにより、ポリシリコンＭＯＳ２３２に電流を流し、相変化部２３１に電流を流さない。 Next, the memory cell selection operation in thememory chain 61 will be described with reference to FIGS.
An off voltage is applied to the cellselection gate electrode 15 connected to the selected memory cell 221 so as not to induce a channel in the polysilicon MOS 232 of the selected memory cell 221, so that no current flows through the polysilicon MOS 232, and the phase change unit 231 Current is passed through. Note that an on-voltage is applied to the cell selection gate electrode 15 connected to the non-selected memory cell, and a channel is induced in the polysilicon MOS 232 of the selected memory cell, thereby causing a current to flow in the polysilicon MOS 232 and causing the phase change portion 231 to flow. Do not pass current.
選択メモリセル２２１に接続されたセル選択ゲート電極１５にオフ電圧を印加し、選択メモリセル２２１のポリシリコンＭＯＳ２３２にチャネルを誘起しないようにして、ポリシリコンＭＯＳ２３２に電流を流さず、相変化部２３１に電流を流す。なお、非選択メモリセルに接続されたセル選択ゲート電極１５にオン電圧を印加し、選択メモリセルのポリシリコンＭＯＳ２３２にチャネルを誘起することにより、ポリシリコンＭＯＳ２３２に電流を流し、相変化部２３１に電流を流さない。 Next, the memory cell selection operation in the
An off voltage is applied to the cell
なお、セット動作及びリード動作についての説明は省略するが、上記したリセット動作と同様に行うことが可能である。
Note that the description of the set operation and the read operation is omitted, but it can be performed in the same manner as the above-described reset operation.
次に、三次元型相変化メモリの製造方法について説明する。
まず、図１１に示すように、Ｘチェーン選択素子６４のチャネル１９及び層間絶縁膜１６を、不図示のＹチェーン選択素子６２上に形成する。 Next, a method for manufacturing a three-dimensional phase change memory will be described.
First, as shown in FIG. 11, thechannel 19 and the interlayer insulating film 16 of the X chain selection element 64 are formed on a Y chain selection element 62 (not shown).
まず、図１１に示すように、Ｘチェーン選択素子６４のチャネル１９及び層間絶縁膜１６を、不図示のＹチェーン選択素子６２上に形成する。 Next, a method for manufacturing a three-dimensional phase change memory will be described.
First, as shown in FIG. 11, the
次に、図１２に示すように、Ｘチェーン選択素子６４上に、セル選択ゲート電極１５及び層間絶縁膜１６を交互に複数積層した後、積層体の最上層の層間絶縁膜１６に、上部電極１７を積層する。
なお、セル選択ゲート電極１５及び層間絶縁膜１６の材料及び製法に関しては、詳細は省略するが、一般的な半導体工程で使用される材料及び製法を用いて形成することが可能である。 Next, as shown in FIG. 12, after a plurality of cellselection gate electrodes 15 and interlayer insulating films 16 are alternately stacked on the X chain selection element 64, the upper electrode is formed on the uppermost interlayer insulating film 16 of the stacked body. 17 is laminated.
Note that the material and manufacturing method of the cellselection gate electrode 15 and the interlayer insulating film 16 are not described in detail, but can be formed using materials and manufacturing methods used in general semiconductor processes.
なお、セル選択ゲート電極１５及び層間絶縁膜１６の材料及び製法に関しては、詳細は省略するが、一般的な半導体工程で使用される材料及び製法を用いて形成することが可能である。 Next, as shown in FIG. 12, after a plurality of cell
Note that the material and manufacturing method of the cell
次いで、上部電極１７、及びセル選択ゲート電極１５と層間絶縁膜１６との積層体を、この積層体の積層方向にチャネル１９の上面まで貫通するように、メモリホール５２を開口する。
Next, the memory hole 52 is opened so as to penetrate the upper electrode 17 and the stacked body of the cell selection gate electrode 15 and the interlayer insulating film 16 to the upper surface of the channel 19 in the stacking direction of the stacked body.
次いで、メモリホール５２の側壁側から順に、ゲート絶縁膜１８及びポリシリコンチャネル１３を成膜する。その後、異方性エッチバックにより、メモリホール５２下部のゲート絶縁膜１８及びポリシリコンチャネル１３を除去する。このとき同時に、上部電極１７付近のゲート絶縁膜１８が除去される。
異方性エッチバックを行った後、メモリホール５２内に再度ポリシリコンチャネル１３を成膜する。この時点の断面模式図を図１３に示す。 Next, thegate insulating film 18 and the polysilicon channel 13 are formed sequentially from the side wall side of the memory hole 52. Thereafter, the gate insulating film 18 and the polysilicon channel 13 under the memory hole 52 are removed by anisotropic etch back. At the same time, the gate insulating film 18 near the upper electrode 17 is removed.
After performing anisotropic etch back, thepolysilicon channel 13 is formed again in the memory hole 52. A schematic cross-sectional view at this time is shown in FIG.
異方性エッチバックを行った後、メモリホール５２内に再度ポリシリコンチャネル１３を成膜する。この時点の断面模式図を図１３に示す。 Next, the
After performing anisotropic etch back, the
ゲート絶縁膜１８としては、シリコン酸化膜を用いるのが良い。シリコン酸化膜は、ＭＯＳＦＥＴのゲート絶縁膜として幅広く用いられており、三次元型相変化メモリの製造に安定して適用できる効果がある。その他、ゲート絶縁膜１８として、Ｈｉｇｈ－ｋ絶縁膜を用いることが可能であることは言うまでもない。Ｈｉｇｈ－ｋ絶縁膜を用いることで、セル選択ＭＯＳの駆動力を大きくすることが可能となり、メモリチェーンに含まれるメモリセルの数を増やす（すなわち、メモリセル積層数を増やす）ことが可能となり、より大容量の相変化メモリを実現できる。
As the gate insulating film 18, a silicon oxide film is preferably used. A silicon oxide film is widely used as a gate insulating film of a MOSFET, and has an effect that can be stably applied to manufacture of a three-dimensional phase change memory. In addition, it goes without saying that a high-k insulating film can be used as the gate insulating film 18. By using a high-k insulating film, it becomes possible to increase the driving force of the cell selection MOS, and it is possible to increase the number of memory cells included in the memory chain (that is, increase the number of stacked memory cells). A larger-capacity phase change memory can be realized.
ゲート絶縁膜１８の形成温度に関しては、メモリチェーンをＺ方向に複数個積層する、所謂メモリチェーン積層構造では、ゲート絶縁膜１８の形成温度は低いことが望ましい。これにより、上段のメモリチェーンに含まれるゲート絶縁膜１８を形成するときに、下段のメモリチェーンに含まれる、既に形成済みの相変化材料１１への熱負荷を低減することができる。ゲート絶縁膜１８の形成方法としては、堆積法堆積絶縁膜、プラズマＣＶＤ、セル選択ゲート電極のプラズマ酸化、又は熱酸化熱酸化して形成する絶縁膜を用いることが出来る。
Regarding the formation temperature of the gate insulating film 18, it is desirable that the formation temperature of the gate insulating film 18 is low in a so-called memory chain stacked structure in which a plurality of memory chains are stacked in the Z direction. Thereby, when forming the gate insulating film 18 included in the upper memory chain, it is possible to reduce the thermal load on the phase change material 11 that is already formed and included in the lower memory chain. As a method for forming the gate insulating film 18, an insulating film formed by a deposition insulating film, plasma CVD, plasma oxidation of a cell selection gate electrode, or thermal oxidation thermal oxidation can be used.
次いで、図１３に示すメモリホール５２内のポリシリコンチャネル１３の主表面１３１に、相変化材料を成膜して相変化材料層１１を形成する。ここで、主表面とは、各層の主面のうち、空間側に露出している面をいう。相変化材料層１１を成膜した後の時点でのメモリチェーン周辺の断面模式図を図１４に示す。
Next, a phase change material is formed on the main surface 131 of the polysilicon channel 13 in the memory hole 52 shown in FIG. 13 to form the phase change material layer 11. Here, the main surface means the surface exposed to the space side among the main surfaces of each layer. FIG. 14 is a schematic cross-sectional view around the memory chain at the time after the phase change material layer 11 is formed.
相変化材料層１１を形成する相変化材料としては、カルコゲナイドが好適に用いられる。カルコゲナイドとは、硫黄、セレン、テルルのうちの少なくとも１元素を含む材料のことである。相変化材料として現在有望視されているカルコゲナイドは、Ｇｅ（ゲルマニウム）、Ｓｂ（アンチモン）、Ｔｅ（テルル）からなる合金であり、ＧｅＳｂＴｅ合金、特にＧｅ２Ｓｂ２Ｔｅ５合金を用いるのが良い。
As the phase change material for forming the phase change material layer 11, chalcogenide is preferably used. Chalcogenide is a material containing at least one element of sulfur, selenium, and tellurium. The chalcogenide that is currently considered promising as a phase change material is an alloy composed of Ge (germanium), Sb (antimony), and Te (tellurium), and a GeSbTe alloy, particularly a Ge 2 Sb 2 Te 5 alloy may be used.
Ｇｅ２Ｓｂ２Ｔｅ５合金は、ＤＶＤ－ＲＡＭで製品化の実績のある材料であり、製品開発に要する時間と費用を低減することが出来る。さらに、相変化材料としては、ＩｎＧｅＳｂＴｅ、ＺｎＧｅＳｂＴｅ、ＢｉＧｅＳｂＴｅ、Ｓｂを主体とする合金、特にＩｎＳｂやＡｇＩｎＳｂＴｅ、ＡｇＩｎＳｂを用いることが出来る。中でも、ＩｎＧｅＳｂＴｅ、ＺｎＧｅＳｂＴｅ、ＢｉＧｅＳｂＴｅなどのリテンション特性に優れた相変化材料を用いることで、相変化メモリの使用可能環境温度の上限を高くすることが可能となり、より広範囲な用途への使用が可能となるため、販売数量を増加させることが可能になる。
The Ge 2 Sb 2 Te 5 alloy is a material that has been successfully commercialized in DVD-RAM, and can reduce the time and cost required for product development. Furthermore, as the phase change material, an alloy mainly composed of InGeSbTe, ZnGeSbTe, BiGeSbTe, or Sb, particularly InSb, AgInSbTe, or AgInSb can be used. Above all, by using a phase change material with excellent retention characteristics such as InGeSbTe, ZnGeSbTe, BiGeSbTe, it becomes possible to increase the upper limit of the environmental temperature where phase change memory can be used, and it can be used for a wider range of applications. Therefore, it becomes possible to increase the sales volume.
相変化材料層１１の成膜方法としては、Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ（ＣＶＤ）、Ａｔｏｍｉｃ Ｌａｙｅｒ Ｄｅｐｏｓｉｔｉｏｎ（ＡＬＤ）、スパッタ、ゾルーゲル法を用いることが可能である。これらの中でも、ＣＶＤを用いるのが良い。ＣＶＤは成膜レートが速く、相変化メモリを短時間で製造できる利点がある。さらにＣＶＤは、スパッタと比較して、深穴のメモリホールに対する膜厚均一性（カバレッジ）に優れている。
As a method for forming the phase change material layer 11, it is possible to use Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), sputtering, or sol-gel method. Among these, it is preferable to use CVD. CVD has an advantage that the film formation rate is fast and the phase change memory can be manufactured in a short time. Furthermore, CVD is superior in film thickness uniformity (coverage) for deep hole memory holes compared to sputtering.
相変化材料の成膜は、真空状態で行う。ＣＶＤの成膜温度は１３０～２００℃の低温にするのが良い。低温にすることで、相変化材料がアモルファス状態で成膜され、膜厚の均一性が高くなる。なお、発明者らは、相変化材料を結晶状態で成膜すると、結晶粒成長に伴う膜厚の不均一性が観察されることを確認している。
The film of the phase change material is formed in a vacuum state. The film formation temperature of CVD is preferably a low temperature of 130 to 200 ° C. By lowering the temperature, the phase change material is deposited in an amorphous state, and the film thickness uniformity is increased. Note that the inventors have confirmed that when the phase change material is formed in a crystalline state, non-uniformity in film thickness accompanying crystal grain growth is observed.
一方、ＡＬＤは膜厚ムラが少なく、書き換え電流のばらつきが少なく、低消費電力の相変化メモリを実現できる利点がある。さらに、ＡＬＤは、カバレッジに優れている。なお、スパッタの場合は、平面型相変化メモリと同じ製造プロセスで行うことが可能であるため、相変化メモリの開発期間を短縮できる利点がある。ゾルーゲル法は、製造コストを安価にすることが可能である利点がある。
On the other hand, ALD has the advantage that it can realize a phase change memory with low power consumption and little variation in rewrite current, and low power consumption. Furthermore, ALD is excellent in coverage. In the case of sputtering, since it can be performed by the same manufacturing process as that of the planar type phase change memory, there is an advantage that the development period of the phase change memory can be shortened. The sol-gel method has an advantage that the manufacturing cost can be reduced.
次いで、メモリホール５２内に形成された相変化材料層１１の主表面１１１を、窒化処理する。
相変化材料層１１の窒化処理により、その主表面１１１に、窒化処理層１２が形成される。これにより、耐酸化性を有する絶縁層である、窒化処理層１２と、相変化材料層１１とを有する相変化材料膜５５が形成される。この時点での断面模式図を図１５に示す。 Next, themain surface 111 of the phase change material layer 11 formed in the memory hole 52 is nitrided.
By nitriding of phasechange material layer 11, nitriding layer 12 is formed on main surface 111 thereof. Thereby, phase change material film 55 having nitriding layer 12 and phase change material layer 11 which are insulating layers having oxidation resistance is formed. A schematic cross-sectional view at this point is shown in FIG.
相変化材料層１１の窒化処理により、その主表面１１１に、窒化処理層１２が形成される。これにより、耐酸化性を有する絶縁層である、窒化処理層１２と、相変化材料層１１とを有する相変化材料膜５５が形成される。この時点での断面模式図を図１５に示す。 Next, the
By nitriding of phase
すなわち、図１５において、１１は相変化材料層であり、１２は、相変化材料層の窒化処理により形成された窒化処理層であり、５５は、相変化材料層１１と窒化処理層１２とで構成される相変化材料膜である。なお、図１５では、相変化材料層１１と窒化処理層１２とを、別の層として示しているが、実施例１では、窒化処理層１２は、相変化材料層１１と連続する一連の層である。
That is, in FIG. 15, 11 is a phase change material layer, 12 is a nitridation treatment layer formed by nitriding treatment of the phase change material layer, and 55 is a phase change material layer 11 and a nitridation treatment layer 12. It is a phase change material film comprised. In FIG. 15, the phase change material layer 11 and the nitriding layer 12 are shown as separate layers. However, in Example 1, the nitriding layer 12 is a series of layers that are continuous with the phase change material layer 11. It is.
窒化の手段としては、窒化作用を有するリモートプラズマを用いるか、又は相変化材料層１１の近傍で、窒化作用を有するラジカル又はプラズマを生成させる等の方法を用いることができる。中でも、リモートプラズマを用いるのが良い。リモートプラズマを用いることで、窒化作用を有するプラズマを発生させる領域と窒化対象である相変化材料層１１との距離を離すことが可能になり、窒化処理装置の設計自由度を向上させることが可能となる。その結果、窒化の均一性が向上し、相変化メモリの歩留まりを向上させることが出来る。
As a means for nitriding, a remote plasma having a nitriding action or a method of generating radicals or plasma having a nitriding action in the vicinity of the phase change material layer 11 can be used. Among these, remote plasma is preferably used. By using remote plasma, it is possible to increase the distance between the region where the plasma having nitriding action is generated and the phase change material layer 11 to be nitrided, and the degree of freedom in designing the nitriding apparatus can be improved. It becomes. As a result, the uniformity of nitriding can be improved and the yield of phase change memory can be improved.
なお、相変化材料層１１の近傍で、窒化作用を有するラジカル又はプラズマを生成する方法に関しては、具体的には相変化材料の前駆体（プリカーサ）に窒素を含有させ、この前駆体が分解するときに窒素ラジカルを生成させる方法や、アンモニアを流しつつクラッカーを用いて電気的に分解することで、プラズマやラジカルを生成する方法がある。
Regarding the method of generating radicals or plasma having a nitriding action in the vicinity of the phase change material layer 11, specifically, the phase change material precursor (precursor) contains nitrogen, and this precursor is decomposed. Sometimes there are a method of generating nitrogen radicals and a method of generating plasma and radicals by electrolysis using a cracker while flowing ammonia.
また、ラジカルの生成に白金等の触媒を用いる方法も採用することが可能である。ラジカルの生成に白金等の触媒を用いることで、ラジカル生成温度を低減することができ、またラジカルの生成量を増加させることができる。窒化作用のあるラジカルの例としては、ＮやＮＨ２が挙げられる。
It is also possible to employ a method using a catalyst such as platinum for the generation of radicals. By using a catalyst such as platinum for the generation of radicals, the radical generation temperature can be reduced and the amount of radicals generated can be increased. Examples of radicals having a nitriding action include N and NH 2 .
上記したように、相変化材料層１１を窒化処理することにより、相変化材料層１１の主表面が、耐酸化性を有する絶縁物、すなわち窒化した相変化材料で覆われる。このため、相変化材料層１１の熱安定性が向上し、また後述するギャップフィル部１４の形成時における、相変化材料層１１の耐酸化性が向上する。
As described above, by nitriding the phase change material layer 11, the main surface of the phase change material layer 11 is covered with an oxidation-resistant insulator, that is, a nitrided phase change material. For this reason, the thermal stability of the phase change material layer 11 is improved, and the oxidation resistance of the phase change material layer 11 is improved when a gap fill portion 14 described later is formed.
なお、窒化処理により熱安定性が向上する点は、平面型相変化メモリで述べたのと同様の理由から説明される。すなわち、窒化処理後の図１５に示す構成では、相変化材料層１１を挟んでいる、窒化処理層１２とポリシリコンチャネル１３とは、相変化材料の一部が昇華しても略変形しないため、昇華により気化した相変化材料のガス圧力が、相変化メモリ内で急上昇する。このため、ガス圧力の上昇に伴う昇華温度の上昇により、熱力的な平衡状態に到達し、相変化材料がそれ以上昇華しなくなる。
The point that the thermal stability is improved by the nitriding treatment is explained for the same reason as described in the planar phase change memory. That is, in the configuration shown in FIG. 15 after the nitriding treatment, the nitriding treatment layer 12 and the polysilicon channel 13 sandwiching the phase change material layer 11 are not substantially deformed even if a part of the phase change material is sublimated. The gas pressure of the phase change material vaporized by sublimation rises rapidly in the phase change memory. For this reason, due to the increase in sublimation temperature accompanying the increase in gas pressure, a thermodynamic equilibrium state is reached, and the phase change material does not sublime further.
なお、仮に相変化材料の端面が開放されている場合でも、窒化処理層１２及び下地（ポリシリコンチャネル１３）により抑えつけられている主面の面積と比較すると、端面の面積は小さいため、相変化材料が昇華する割合が少なくなることに変わりはない。
Even if the end face of the phase change material is open, the area of the end face is small compared to the area of the main face suppressed by the nitriding layer 12 and the base (polysilicon channel 13). There is no change in the rate at which the change material sublimates.
本発明者らは、窒化した相変化材料について、４００℃においても熱安定性が保たれて、昇華が生じないことを確認している。なお、相変化材料膜５５において、窒化処理層１２が形成されている側の主面に対するもう一方の主面は、下地と接する面であり、図１５の場合は下地はポリシリコンチャネル１３となる。
The inventors of the present invention have confirmed that the nitrided phase change material maintains thermal stability even at 400 ° C. and does not cause sublimation. In the phase change material film 55, the other main surface with respect to the main surface on which the nitriding layer 12 is formed is a surface in contact with the base, and the base is the polysilicon channel 13 in FIG. .
ここで、相変化材料層１１の窒化度合いとメモリ特性に対する影響との関係について説明する。図１６は、相変化材料であるＧｅＳｂＴｅのスパッタ成膜時の窒素／Ａｒガス流量比と、得られたＧｅＳｂＴｅ膜を適用した相変化メモリの書き換え可能回数との関係を示す例である。図１６に示すように、スパッタ法による相変化材料製膜時に、スパッタ室に導入される窒素／Ａｒガス流量比が大きくなると、相変化メモリの書き換え可能回数が低下することが確認できる。
Here, the relationship between the nitridation degree of the phase change material layer 11 and the influence on the memory characteristics will be described. FIG. 16 is an example showing the relationship between the nitrogen / Ar gas flow rate ratio during sputtering deposition of GeSbTe, which is a phase change material, and the number of rewritable times of the phase change memory to which the obtained GeSbTe film is applied. As shown in FIG. 16, it can be confirmed that when the flow rate ratio of nitrogen / Ar gas introduced into the sputtering chamber is increased when the phase change material is formed by the sputtering method, the number of rewritable phases of the phase change memory decreases.
すなわち、例えば窒素／Ａｒガス流量比を３％とした場合のように、相変化材料層１１全体が強い窒化条件で成膜されると、相変化メモリとしての書き換え可能回数が低下する。このため、相変化領域の窒素濃度は、例えば図１６の例において、窒素／Ａｒガス流量比を０．５％以下としたときに得られる成膜体の窒素含有比と同程度とする必要がある。本発明者らの実験による検討の結果、窒素／Ａｒガス流量比が０．５％の時の、相変化材料層全体における窒素含有比は、概ね２０ａｔ％以下であると推定される。
That is, when the entire phase change material layer 11 is formed under strong nitriding conditions, for example, when the nitrogen / Ar gas flow rate ratio is 3%, the number of rewritable times as the phase change memory decreases. Therefore, for example, in the example of FIG. 16, the nitrogen concentration in the phase change region needs to be approximately the same as the nitrogen content ratio of the film formation obtained when the nitrogen / Ar gas flow rate ratio is 0.5% or less. is there. As a result of examination by the inventors, the nitrogen content ratio in the entire phase change material layer when the nitrogen / Ar gas flow ratio is 0.5% is estimated to be approximately 20 at% or less.
一方、相変化材料層１１において、半導体製造に必要とされる耐熱性、例えば４００℃程度の温度条件下での耐熱性を得るためには、窒素／Ａｒガス流量比を０．５％としたときに得られる成膜体の窒素濃度と同程度とする必要がある。
On the other hand, in the phase change material layer 11, in order to obtain heat resistance required for semiconductor manufacturing, for example, heat resistance under a temperature condition of about 400 ° C., the nitrogen / Ar gas flow ratio is set to 0.5%. It is necessary to make it the same as the nitrogen concentration of the film formation obtained sometimes.
すなわち、相変化材料膜５５において、後述するギャップフィル部１４形成側の主面である面５５１（すなわち、相変化材料膜５５の主面のうち、メモリチェーン６１の中心側の主面。）側に形成した窒化処理層１２の窒素濃度を、相変化材料膜５５全体の平均窒素濃度より高くすることがよい。具体的には、窒化処理層１２の窒素濃度が、２０ａｔ％以上であることが好ましい。これにより、相変化材料膜５５の、ギャップフィル部１４に隣接する面５５１においては、耐熱性、耐酸化性が得られるとともに、相変化材料層１１としては、良好な書換え特性を確保することができる。
That is, in the phase change material film 55, the surface 551 (that is, the main surface on the center side of the memory chain 61 among the main surfaces of the phase change material film 55), which is a main surface on the gap fill portion 14 formation side described later. It is preferable that the nitrogen concentration of the nitriding layer 12 formed in the above is higher than the average nitrogen concentration of the entire phase change material film 55. Specifically, the nitrogen concentration of the nitriding layer 12 is preferably 20 at% or more. As a result, heat resistance and oxidation resistance can be obtained on the surface 551 of the phase change material film 55 adjacent to the gap fill portion 14, and good rewrite characteristics can be secured for the phase change material layer 11. it can.
また、本発明者らは、相変化メモリの書換え動作を行うことにより、相変化材料層１１に含まれる窒素が、相変化領域から相変化領域外に掃出されることを実験により確認している。すなわち、仮に製造完了直後（すなわち、最初の通電開始前）の相変化メモリにおいて、相変化領域の窒素濃度が、書換えに適した窒素濃度を超えていた場合でも、例えばメモリチップテスト工程や、顧客による使用開始の初期時点において、書換え動作が行われることにより、相変化領域の窒素濃度は減少し、書換えに適した窒素濃度に到達すると考えられる。
In addition, the present inventors have confirmed through experiments that nitrogen contained in the phase change material layer 11 is swept out of the phase change region from the phase change region by performing a rewrite operation of the phase change memory. . That is, even if the nitrogen concentration in the phase change region exceeds the nitrogen concentration suitable for rewriting in the phase change memory immediately after the completion of manufacturing (that is, before the start of the first energization), for example, the memory chip test process or the customer It is considered that the nitrogen concentration in the phase change region decreases and reaches a nitrogen concentration suitable for rewriting by performing the rewriting operation at the initial time of starting use.
次いで、相変化材料膜５５で囲まれた領域に、ギャップフィル部１４を形成する。この時点における断面模式図を図１７に示す。
Next, the gap fill portion 14 is formed in a region surrounded by the phase change material film 55. A schematic cross-sectional view at this point is shown in FIG.
ギャップフィル部１４を形成する方法としては、例えば塗布法（絶縁膜用塗布材料の硬化による絶縁膜の形成）やＣＶＤ法を採用することができる。これらの中でも塗布法を用いることがよく、例えば絶縁膜用塗布材料を、スピンコート法で成膜することが望ましい。絶縁膜用塗布材料としては、低温硬化性を有するものを用いることが良い。絶縁膜用塗布材料として低温硬化性を有するものを用いることにより、ギャップフィル部の成膜温度を例えば２００℃に低減することが出来、相変化メモリの製造時における相変化材料の劣化を軽減することが出来る。
As a method of forming the gap fill portion 14, for example, a coating method (formation of an insulating film by curing a coating material for an insulating film) or a CVD method can be employed. Among these, a coating method is preferably used. For example, it is desirable to form a coating material for an insulating film by spin coating. As the coating material for the insulating film, a material having low temperature curability is preferably used. By using an insulating film coating material having a low temperature curing property, the film forming temperature of the gap fill portion can be reduced to, for example, 200 ° C., and the deterioration of the phase change material during the manufacture of the phase change memory can be reduced. I can do it.
また、絶縁膜用塗布材料又はその硬化反応後のギャップフィル部１４として、水分含有量の少ないものを用いることが良い。これにより、相変化メモリの製造時や使用時における相変化材料の劣化を軽減することが出来る。相変化材料の劣化を軽減することにより、書き換え可能回数が多く、信頼性の高い相変化メモリを実現することが出来る。
Also, it is preferable to use a material having a low water content as the insulating film coating material or the gap fill portion 14 after the curing reaction thereof. Thereby, deterioration of the phase change material at the time of manufacture and use of the phase change memory can be reduced. By reducing the deterioration of the phase change material, it is possible to realize a highly reliable phase change memory with a large number of rewritable times.
ギャップフィル部１４としては、少なくとも絶縁性を有していればよく、例えばＳｉＯ２からなるものが好適に用いられる。ギャップフィル部１４の構成材料が導電性であると、ギャップフィル部１４を経由して電流が流れ、リセット状態（高抵抗状態）のメモリセルの抵抗が低くなり，抵抗比が低下する。ギャップフィル部１４の構成材料としては、この他にも、ＳｉＯ２を主成分とするその他の絶縁膜や、Ａｌ２Ｏ３、Ｌｏｗ－ｋ材料で形成された絶縁膜を用いることができることは言うまでもない。
As the gap fill portion 14, it is sufficient if it has at least an insulating property, and for example, a material made of SiO 2 is suitably used. If the constituent material of the gap fill part 14 is conductive, a current flows through the gap fill part 14, the resistance of the memory cell in the reset state (high resistance state) is lowered, and the resistance ratio is lowered. As a constituent material of the gap fill portion 14, it is needless to say that other insulating films mainly composed of SiO 2 and insulating films formed of Al 2 O 3 or low-k materials can be used. Yes.
一方、ＣＶＤ法により絶縁膜を形成する場合、絶縁膜製膜時の成膜雰囲気は酸化雰囲気となり、また製膜時には、シリコンウェハが４００℃程度に加熱されるため、塗布法と比較すると、ギャップフィル部１４の成膜過程において相変化材料１１が酸化される可能性がある。
On the other hand, when the insulating film is formed by the CVD method, the film formation atmosphere during the formation of the insulating film is an oxidizing atmosphere, and the silicon wafer is heated to about 400 ° C. during the film formation. There is a possibility that the phase change material 11 is oxidized in the film forming process of the fill portion 14.
なお、ＣＶＤ法による製膜時の温度を３００℃程度に低温化することも可能であるが、この場合、得られる絶縁膜（ギャップフィル部１４）の密度が低下し、絶縁膜の上面に形成される層との密着性が低下する。またこの場合、絶縁膜の残留応力が増加するため、製造中に膜ハガレが生じやすくなる。その結果、相変化メモリの歩留まりが低下する。
Although the temperature at the time of film formation by the CVD method can be lowered to about 300 ° C., in this case, the density of the obtained insulating film (gap fill portion 14) is lowered and formed on the upper surface of the insulating film. Adhesiveness with a layer to be formed is reduced. In this case, since the residual stress of the insulating film increases, film peeling easily occurs during manufacturing. As a result, the yield of the phase change memory decreases.
次いで、エッチバックにより、不要部を除去する。この時点の断面模式図を図１８に示す。エッチバックにより、相変化材料層１１の端面が露出するが、端面付近には相変化領域は存在しないため、端面が露出することによる相変化メモリの相変化特性の劣化は軽微である。
Next, unnecessary portions are removed by etch back. A schematic cross-sectional view at this point is shown in FIG. Although the end face of the phase change material layer 11 is exposed by the etch back, the phase change region of the phase change memory due to the exposure of the end face is slight because there is no phase change region in the vicinity of the end face.
なお、端面の露出後に、相変化材料の窒化処理を再度行うことが可能であることは言うまでもない。このようにすることで相変化メモリの書き換え可能回数を多くすることが可能となり、信頼性の高い相変化メモリを実現できる。
Needless to say, the nitriding treatment of the phase change material can be performed again after the end face is exposed. By doing so, it is possible to increase the number of times the phase change memory can be rewritten, thereby realizing a highly reliable phase change memory.
次いで、エッチバックにより不要部が除去された面上に、さらに層間絶縁膜１６を形成する。この時点の断面模式図を図１９に示す。以降は、通常の半導体製造工程により、相変化メモリを製造する。
Next, an interlayer insulating film 16 is further formed on the surface from which unnecessary portions have been removed by etch back. A schematic cross-sectional view at this point is shown in FIG. Thereafter, the phase change memory is manufactured by a normal semiconductor manufacturing process.
図１９に示すように、実施例１の三次元型相変化メモリセルの相変化材料膜５５には、その主面のうち、ギャップフィル部１４に隣接する側の主面５５１（すなわち、相変化材料膜５５の主面のうち、メモリチェーン６１の中心側の主面。）側に、窒化処理層１２が形成されている。これにより、ギャップフィル部１４の製膜時における相変化材料層１１の酸化が防止されるとともに、メモリ製造工程時における相変化材料層１１の熱安定性が向上する。このため、相変化材料層における書換え特性に優れた三次元型相変化メモリセルを得ることができる。
As shown in FIG. 19, the phase change material film 55 of the three-dimensional type phase change memory cell according to the first embodiment has a main surface 551 adjacent to the gap fill portion 14 among the main surfaces (that is, the phase change). The nitriding layer 12 is formed on the main surface of the material film 55 on the main surface on the center side of the memory chain 61. Thereby, oxidation of the phase change material layer 11 during film formation of the gap fill portion 14 is prevented, and thermal stability of the phase change material layer 11 during memory manufacturing process is improved. Therefore, it is possible to obtain a three-dimensional phase change memory cell having excellent rewriting characteristics in the phase change material layer.
なお、相変化材料層１１形成後における熱負荷は低くすることが望ましい。これにより、相変化材料層１１を構成する相変化材料の昇華や組成の不均一化、密度の低下を防止することが可能となり、信頼性の高い相変化メモリを実現できる。
In addition, it is desirable to reduce the heat load after the phase change material layer 11 is formed. This makes it possible to prevent sublimation of the phase change material constituting the phase change material layer 11, non-uniform composition, and a decrease in density, thereby realizing a highly reliable phase change memory.
なお、上記した説明では、例えば図５等に示すように、セル選択ＭＯＳのチャネルとして、ポリシリコンチャネル１３を用いることとして説明を行ってきたが、セル選択ＭＯＳのチャネルとして、その他の半導体を用いることが可能であることは言うまでもない。
In the above description, as shown in FIG. 5 and the like, for example, the polysilicon channel 13 is used as the channel of the cell selection MOS. However, other semiconductors are used as the channel of the cell selection MOS. It goes without saying that it is possible.
セル選択ＭＯＳのチャネルとしては、例えば酸化物半導体、特にＩｎｄｉｕｍ ｇａｌｌｉｕｍ ｚｉｎｃ ｏｘｉｄｅ（ＩＧＺＯ）、Ｉｎ２Ｏ３、ＳｒＴｉＯ３、ＫＴａＯ３、ＴｉＯ２や、Ｇｅ、ＧａＡｓ、ＧａＰ、ＧａＮ、炭素（グラフェン、フラーレン、ダイアモンド）、カルコゲナイド半導体、特にＺｎＴｅ、層状カルコゲナイド、遷移金属ダイカルコゲナイドや、有機半導体、特にポルフィリンを用いることが可能である。ポリシリコンよりキャリア移動度の優れた半導体を用いることで、相変化メモリの動作電圧を低減し、低消費電力化することが可能になる。
As a channel of the cell selection MOS, for example, an oxide semiconductor, in particular, indium gallium zinc oxide (IGZO), In 2 O 3 , SrTiO 3 , KTaO 3 , TiO 2 , Ge, GaAs, GaP, GaN, carbon (graphene, fullerene) , Diamond), chalcogenide semiconductors, in particular ZnTe, layered chalcogenides, transition metal dichalcogenides, and organic semiconductors, in particular porphyrins. By using a semiconductor having a carrier mobility superior to that of polysilicon, the operating voltage of the phase change memory can be reduced and the power consumption can be reduced.
次に、実施例１に係る三次元型相変化メモリの製造装置について、図２０の模式図を用いて説明する。
三次元型相変化メモリの製造装置１７０は、相変化材料を真空状態で製膜して相変化材料層を形成する相変化材料成膜チャンバ１７１と、耐酸化性を有する絶縁物である窒化物を、真空状態で形成する窒化物形成チャンバ１８１とを有している。窒化物形成チャンバ１８１は、相変化材料成膜チャンバ１７１で形成された相変化材料層１１の主表面を窒化処理するか、又はこの主表面に窒化物層を成膜するものである。 Next, the three-dimensional phase change memory manufacturing apparatus according to the first embodiment will be described with reference to the schematic diagram of FIG.
The three-dimensional phase changememory manufacturing apparatus 170 includes a phase change material film forming chamber 171 that forms a phase change material layer by forming a phase change material in a vacuum state, and a nitride that is an oxidation-resistant insulator. Is formed in a vacuum state. The nitride forming chamber 181 performs nitriding treatment on the main surface of the phase change material layer 11 formed in the phase change material film forming chamber 171 or forms a nitride layer on the main surface.
三次元型相変化メモリの製造装置１７０は、相変化材料を真空状態で製膜して相変化材料層を形成する相変化材料成膜チャンバ１７１と、耐酸化性を有する絶縁物である窒化物を、真空状態で形成する窒化物形成チャンバ１８１とを有している。窒化物形成チャンバ１８１は、相変化材料成膜チャンバ１７１で形成された相変化材料層１１の主表面を窒化処理するか、又はこの主表面に窒化物層を成膜するものである。 Next, the three-dimensional phase change memory manufacturing apparatus according to the first embodiment will be described with reference to the schematic diagram of FIG.
The three-dimensional phase change
相変化材料成膜チャンバ１７１と窒化物形成チャンバ１８１とは、搬送室１７４により、真空状態を維持可能に接続されている。搬送室１７４は、さらにロードアンロード室１７３を備えており、シリコンウェハ等の被成膜体は、真空引きされたロードアンロード室１７３から搬送室１７４内に導入され、搬送室１７４内に設けられたロボットアーム１７５により、相変化材料成膜チャンバ１７１や窒化物形成チャンバ１８１に向けて搬送される。
The phase change material film forming chamber 171 and the nitride forming chamber 181 are connected by a transfer chamber 174 so that a vacuum state can be maintained. The transfer chamber 174 further includes a load / unload chamber 173, and a deposition target such as a silicon wafer is introduced into the transfer chamber 174 from the evacuated load / unload chamber 173 and provided in the transfer chamber 174. The robot arm 175 is transported toward the phase change material film forming chamber 171 and the nitride forming chamber 181.
このとき、シリコンウェハ等の被成膜体は、真空引きされたロードアンロード室１７３から導入された後、搬送室１７４、相変化材料成膜チャンバ１７１及び窒化物形成チャンバ１８１内を高真空状態として、搬送されることが好ましい。これにより、真空条件下において、相変化材料成膜チャンバ１７１により相変化材料層１１が成膜された後、真空状態を維持したまま、窒化物形成チャンバ１８１により、相変化材料層１１の主表面が窒化処理されるか、又はこの主表面に窒化物層が形成される。
At this time, a deposition target such as a silicon wafer is introduced from the evacuated load / unload chamber 173, and then the inside of the transfer chamber 174, the phase change material deposition chamber 171 and the nitride formation chamber 181 is in a high vacuum state. Are preferably conveyed. Thus, after the phase change material layer 11 is formed in the phase change material film formation chamber 171 under vacuum conditions, the main surface of the phase change material layer 11 is formed in the nitride formation chamber 181 while maintaining the vacuum state. Is nitrided or a nitride layer is formed on this main surface.
相変化材料層１１の主表面が窒化処理された場合には、窒化処理層１２を有する相変化材料膜５５が形成される。なお、相変化材料層１１の表面に窒化物層２４１（図２３参照。）が形成された場合には、相変化材料層１１と窒化物層２４１を有する相変化材料膜５５が形成される。
When the main surface of the phase change material layer 11 is nitrided, a phase change material film 55 having the nitrided layer 12 is formed. When nitride layer 241 (see FIG. 23) is formed on the surface of phase change material layer 11, phase change material film 55 having phase change material layer 11 and nitride layer 241 is formed.
すなわち、相変化材料膜５５の主表面側に、窒化処理層１２が形成されることで、その後の工程において、相変化材料層１１が安定化されるまで相変化材料層１１を酸化させることなく、相変化メモリを製造することができる。結果として，信頼性の高い相変化メモリを実現することができる。
That is, by forming the nitriding layer 12 on the main surface side of the phase change material film 55, the phase change material layer 11 is not oxidized in the subsequent steps until the phase change material layer 11 is stabilized. A phase change memory can be manufactured. As a result, a highly reliable phase change memory can be realized.
なお、図２１に示す三次元型相変化メモリの製造装置１８０は、窒化物形成チャンバ１８１として、相変化材料層１１の主表面を窒化処理する窒化チャンバ１７２を備えた構成を示しており、その他の構成は、図２０に示す相変化メモリの製造装置１７０と同様である。
The three-dimensional phase change memory manufacturing apparatus 180 shown in FIG. 21 has a configuration including a nitridation chamber 172 for nitriding the main surface of the phase change material layer 11 as the nitride forming chamber 181. The configuration of is the same as that of the phase change memory manufacturing apparatus 170 shown in FIG.
図２２に、さらに信頼性の高い三次元型相変化メモリを製造可能な製造装置１９０の模式図を示す。
三次元型相変化メモリの製造装置１９０は、相変化材料成膜チャンバ１７１と、窒化チャンバ１７２と、前洗浄チャンバ１９１と、熱処理チャンバ１９２と、保護膜ＣＶＤ成膜チャンバ１９３とを有している。 FIG. 22 is a schematic diagram of amanufacturing apparatus 190 that can manufacture a more reliable three-dimensional phase change memory.
The three-dimensional phase changememory manufacturing apparatus 190 includes a phase change material film forming chamber 171, a nitriding chamber 172, a precleaning chamber 191, a heat treatment chamber 192, and a protective film CVD film forming chamber 193. .
三次元型相変化メモリの製造装置１９０は、相変化材料成膜チャンバ１７１と、窒化チャンバ１７２と、前洗浄チャンバ１９１と、熱処理チャンバ１９２と、保護膜ＣＶＤ成膜チャンバ１９３とを有している。 FIG. 22 is a schematic diagram of a
The three-dimensional phase change
三次元型相変化メモリの製造装置１９０では、まず、被成膜体であるシリコンウェハをロードアンロード室１７３に導入し、ロードアンロード室１７３で真空引きを行う。以降の工程は減圧雰囲気で行う。
In the three-dimensional phase change memory manufacturing apparatus 190, first, a silicon wafer as a film formation target is introduced into the load / unload chamber 173, and evacuation is performed in the load / unload chamber 173. The subsequent steps are performed in a reduced pressure atmosphere.
次に、シリコンウェハを搬送室１７４に搬送する。搬送室１７４は高真空状態に保たれている。
次に、搬送室１７４のロボットアーム１７５により、シリコンウェハを前洗浄チャンバ１９１に搬送する。 Next, the silicon wafer is transferred to thetransfer chamber 174. The transfer chamber 174 is kept in a high vacuum state.
Next, the silicon wafer is transferred to thepre-cleaning chamber 191 by the robot arm 175 in the transfer chamber 174.
次に、搬送室１７４のロボットアーム１７５により、シリコンウェハを前洗浄チャンバ１９１に搬送する。 Next, the silicon wafer is transferred to the
Next, the silicon wafer is transferred to the
前洗浄チャンバ１９１では、相変化材料層を成膜する下地となるポリシリコンチャネル１３のポリシリコンに形成された自然酸化膜層が除去される。ポリシリコンチャネル１３上の自然酸化膜を除去することにより、ポリシリコンチャネル１３と相変化材料層１１との間の界面抵抗を低減することが可能となり、動作電圧が低く、消費電力の少ない相変化メモリを実現出来る。
In the pre-clean chamber 191, the natural oxide film layer formed on the polysilicon of the polysilicon channel 13 which is the base for forming the phase change material layer is removed. By removing the natural oxide film on the polysilicon channel 13, the interface resistance between the polysilicon channel 13 and the phase change material layer 11 can be reduced, and the phase change with low operating voltage and low power consumption. Memory can be realized.
自然酸化膜層の除去の方法としては、プラズマを用いた等方性エッチングを用いるのが良い。プラズマを用いることで、穴底不覚のポリシリコンの自然酸化膜を除去することができる。なお、ポリシリコンに形成された自然酸化膜層の除去の方法としては、フッ酸洗浄により行うことが可能であることは言うまでもない。なお、フッ酸洗浄を用いる場合には、フッ酸洗浄工程までは大気圧下で行い、洗浄後に、シリコンウェハをロードアンロード室１７３を経由して相変化材料成膜チャンバ１７１に搬送するのが良い。これにより、製造装置全体を小型化し、安価な製造装置を実現することが出来る。
As a method for removing the natural oxide film layer, it is preferable to use isotropic etching using plasma. By using plasma, it is possible to remove the natural oxide film of polysilicon that is insensitive to the hole bottom. Needless to say, the method for removing the natural oxide film layer formed on the polysilicon can be performed by hydrofluoric acid cleaning. When hydrofluoric acid cleaning is used, the process until the hydrofluoric acid cleaning step is performed under atmospheric pressure, and after the cleaning, the silicon wafer is transferred to the phase change material film formation chamber 171 via the load / unload chamber 173. good. Thereby, the whole manufacturing apparatus can be reduced in size and an inexpensive manufacturing apparatus can be realized.
次に、ロボットアーム１７５により、シリコンウェハを相変化材料成膜チャンバ１７１に搬送する。相変化材料成膜チャンバ１７１により、ポリシリコンチャネル１３上に相変化材料層１１が成膜される。
Next, the silicon wafer is transferred to the phase change material film forming chamber 171 by the robot arm 175. The phase change material layer 11 is deposited on the polysilicon channel 13 by the phase change material deposition chamber 171.
次に、ロボットアーム１７５により、シリコンウェハを窒化チャンバ１７２に搬送する。窒化チャンバ１７２により、相変化材料層１１の主表面が窒化処理される。これにより、窒化処理層１２を有する相変化材料膜５５が形成される。このとき、窒化されることにより、相変化材料層１１と窒化処理層１２の合計膜厚（相変化材料膜５５の膜厚）は、窒化処理前の相変化材料層１１と比較して、やや増加する。
Next, the silicon wafer is transferred to the nitriding chamber 172 by the robot arm 175. The main surface of the phase change material layer 11 is nitrided by the nitridation chamber 172. Thereby, the phase change material film 55 having the nitriding layer 12 is formed. At this time, by nitriding, the total film thickness of the phase change material layer 11 and the nitriding layer 12 (the film thickness of the phase change material film 55) is slightly higher than that of the phase change material layer 11 before nitriding. To increase.
次に、ロボットアーム１７５により、シリコンウェハを熱処理チャンバ１９２に搬送する。熱処理チャンバ１９２は、予め高温に保たれており、搬送されたシリコンウェハの温度は速やかに上昇する。シリコンウェハは、高温の熱処理チャンバ１９２内に所定時間保持されることで、真空中アニールされる。相変化材料膜５５（相変化材料層１１と窒化処理層１２）は、高温で保持されることにより、内部に含まれる水素などの不純物が放出され（真空中デガス）、密度が高くなる。相変化材料層１１の密度が低いと、書き換えに伴い空隙が生じ、安定的な書き換えが困難になる。
Next, the silicon wafer is transferred to the heat treatment chamber 192 by the robot arm 175. The heat treatment chamber 192 is kept at a high temperature in advance, and the temperature of the transferred silicon wafer rises quickly. The silicon wafer is annealed in vacuum by being held in a high-temperature heat treatment chamber 192 for a predetermined time. The phase change material film 55 (the phase change material layer 11 and the nitriding layer 12) is held at a high temperature, thereby releasing impurities such as hydrogen contained therein (degas in vacuum) and increasing the density. If the density of the phase change material layer 11 is low, voids are generated along with rewriting, and stable rewriting becomes difficult.
なお、本発明者らは、ＣＶＤ法により成膜した相変化材料に水素が含まれることを、水素前方散乱分析（Ｈｙｄｒｏｇｅｎ Ｆｏｒｗａｒｄ Ｓｃａｔｔｅｒｉｎｇ，ＨＦＳ）及びラザフォード後方散乱分析（Ｒｕｔｈｅｒｆｏｒｄ Ｂａｃｋｓｃａｔｔｅｒｉｎｇ Ｓｐｅｃｔｒｏｍｅｔｒｙ，ＲＢＳ）により実験的に確認している。またさらに、本発明者らは、加熱処理により相変化材料層１１に含まれる水素が放出されることを、Ｔｈｅｒｍａｌ ｄｅｓｏｒｐｔｉｏｎ ｓｐｅｃｔｒｏｓｃｏｐｙ（ＴＤＳ）分析により実験的に確認している。熱処理の温度としては例えば４００℃程度が望ましい。熱処理温度が高過ぎると相変化材料が昇華し、低すぎると不純物の低減が不十分となる。
In addition, the present inventors have experimented with hydrogen forward scattering analysis (HFS) and Rutherford backscattering analysis (RBS) that the phase change material formed by the CVD method contains hydrogen. Have confirmed. Furthermore, the present inventors have experimentally confirmed by thermal thermal spectroscopy (TDS) analysis that hydrogen contained in the phase change material layer 11 is released by the heat treatment. The temperature for the heat treatment is preferably about 400 ° C., for example. If the heat treatment temperature is too high, the phase change material sublimes, and if it is too low, the reduction of impurities is insufficient.
なお、熱処理を行うタイミングについては、製造時間の観点や相変化材料の昇華を低減できる観点から、窒化処理後に行うのが好ましい。すなわち、熱処理を窒化処理前後にそれぞれ熱処理を行う場合と比べて、窒化処理後に熱処理を行う方が、製造時間を短くすることができる。また、窒化処理前に熱処理を行うと、相変化材料が昇華するおそれがあることから、熱処理は、窒化処理後に行うのが好ましい。
In addition, it is preferable to perform the heat treatment after the nitriding treatment from the viewpoint of manufacturing time and the viewpoint of reducing sublimation of the phase change material. That is, the manufacturing time can be shortened when the heat treatment is performed after the nitriding treatment as compared with the case where the heat treatment is performed before and after the nitriding treatment. Further, if the heat treatment is performed before the nitriding treatment, the phase change material may be sublimated. Therefore, the heat treatment is preferably performed after the nitriding treatment.
ただし、熱処理を窒化処理前に行うことや、窒化処理前と窒化処理後にそれぞれ熱処理を行うことが可能であることは言うまでもない。窒化処理前に熱処理を行うことで、水素などの不純物が放出されるときに相変化材料層１１や窒化処理層１２の変形を軽減することが出来る。
However, it goes without saying that the heat treatment can be performed before the nitriding treatment, or that the heat treatment can be performed before and after the nitriding treatment. By performing the heat treatment before the nitriding treatment, deformation of the phase change material layer 11 and the nitriding treatment layer 12 can be reduced when impurities such as hydrogen are released.
窒化処理前の熱処理温度は２００℃程度とすることが望ましい。熱処理温度が高過ぎると、相変化材料が昇華し、低すぎると不純物の低減が不十分となる。また、窒化処理前後に行うことで、相変化材料層に含まれる不純物の量をさらに減らすことが可能になり、より信頼性の高い相変化メモリを実現することが出来る。
The heat treatment temperature before nitriding is desirably about 200 ° C. If the heat treatment temperature is too high, the phase change material will sublime, and if it is too low, the reduction of impurities will be insufficient. Further, by performing before and after the nitriding treatment, the amount of impurities contained in the phase change material layer can be further reduced, and a phase change memory with higher reliability can be realized.
さらに、ロボットアーム１７５により、シリコンウェハを保護膜ＣＶＤチャンバ１９３に搬送する。保護膜ＣＶＤチャンバ１９３により、相変化材料膜５５で囲まれた領域に、ギャップフィル部１４が形成される。なお、ギャップフィル部１４の形成方法がＣＶＤに限定されないことは言うまでもない。例えば、ギャップフィル部１４は、ＡＬＤや塗布法により成膜しても良い。
Furthermore, the silicon wafer is transferred to the protective film CVD chamber 193 by the robot arm 175. The gap fill portion 14 is formed in the region surrounded by the phase change material film 55 by the protective film CVD chamber 193. Needless to say, the method of forming the gap fill portion 14 is not limited to CVD. For example, the gap fill portion 14 may be formed by ALD or a coating method.
上記の通り、減圧された雰囲気で相変化材料成膜工程の前後の工程を一貫して行うことにより、相変化材料の酸化量を軽減することが出来る。その結果、書き換え可能回数が多い、相変化メモリを実現できる。
As described above, the amount of oxidation of the phase change material can be reduced by consistently performing the steps before and after the phase change material film forming step in a reduced pressure atmosphere. As a result, a phase change memory having a large number of rewritable times can be realized.
実施例２では、より耐熱性及び耐酸化性に優れた相変化部を有する三次元型相変化メモリの例を、図２３及び図２０を用いて説明する。図２３に、実施例２の三次元型相変化メモリの製造方法の一工程における断面模式図を示す。
In Example 2, an example of a three-dimensional phase change memory having a phase change part with more excellent heat resistance and oxidation resistance will be described with reference to FIGS. FIG. 23 is a schematic cross-sectional view in one step of the manufacturing method of the three-dimensional type phase change memory according to the second embodiment.
実施例２では、図２３に示すように、相変化材料層１１の主面のうち、メモリチェーン６１の中心側の主面１１１に接触させるように、窒化物層２４１を形成する。これにより、相変化材料層１１と、窒化物層２４１とを有する相変化材料膜５５が形成される。窒化物層２４１は、具体的には、図２０に示す三次元型相変化メモリの製造装置１７０の、窒化物形成チャンバ１８１により形成することができる。
In Example 2, as shown in FIG. 23, the nitride layer 241 is formed so as to be in contact with the main surface 111 on the center side of the memory chain 61 among the main surfaces of the phase change material layer 11. Thereby, phase change material film 55 having phase change material layer 11 and nitride layer 241 is formed. Specifically, the nitride layer 241 can be formed by the nitride forming chamber 181 of the three-dimensional phase change memory manufacturing apparatus 170 shown in FIG.
窒化物層２４１を構成する窒化物は、非酸化性雰囲気で形成された絶縁性材料であればよく、例えばＳｉＮ（窒化ケイ素）を用いることが望ましい。窒化物層２４１の窒化物として、半導体製造工程で多用されるＳｉＮ、特にＳｉ３Ｎ４を用いることで相変化メモリの開発期間を短縮することが出来る。
The nitride constituting the nitride layer 241 may be an insulating material formed in a non-oxidizing atmosphere. For example, SiN (silicon nitride) is preferably used. By using SiN frequently used in the semiconductor manufacturing process, particularly Si 3 N 4 as the nitride of the nitride layer 241, the development period of the phase change memory can be shortened.
窒化物層２４１は、その成膜時における相変化材料層１１の酸化を防止する、所謂耐酸化性を有し、かつ絶縁性のものであれば良い。窒化物としては、ＳｉＮの他、ＡｌＮ、ＧａＮ、ＣｒＮ、ＭｇＮ、ＺｒＮ、ＭｏＮ及びこれらとさらにその他の元素を含む窒化物を用いることができる。また、窒化物としては、これらの他、相変化材料層の成膜条件において、窒素流量比を増加させることで、相変化材料に含まれる窒素量を増加させた膜（すなわち、窒素含有量を多くした相変化材料）を用いることが出来る。
The nitride layer 241 may have any so-called oxidation resistance that prevents the phase change material layer 11 from being oxidized during the film formation, and may be insulative. As the nitride, in addition to SiN, AlN, GaN, CrN, MgN, ZrN, MoN, and nitrides containing these and other elements can be used. In addition to these, as a nitride, a film in which the amount of nitrogen contained in the phase change material is increased by increasing the nitrogen flow rate ratio in the film formation conditions of the phase change material layer (that is, the nitrogen content is reduced). Many phase change materials) can be used.
なお、窒化物層２４１と同様の効果が得られるものであれば、相変化材料層１１の主面に形成する膜の構成材料は、窒化物に限定されず、非酸化雰囲気で形成された、絶縁性の材料であればよい。例えば、ＺｎＴｅなどの製造工程を経ても、アモルファス状態であり高抵抗状態を維持し得る、カルコゲナイドを用いることが出来る。
Note that, as long as the same effect as that of the nitride layer 241 can be obtained, the constituent material of the film formed on the main surface of the phase change material layer 11 is not limited to nitride, and is formed in a non-oxidizing atmosphere. Any insulating material may be used. For example, chalcogenide that is in an amorphous state and can maintain a high resistance state even through a manufacturing process such as ZnTe can be used.
実施例２によれば、相変化材料層１１の主面１１１に、窒化物層２４１を直接接触させて設けているため、相変化材料層１１の耐熱性及び耐酸化性を、より効率的に向上させることができる。
According to the second embodiment, since the nitride layer 241 is provided in direct contact with the main surface 111 of the phase change material layer 11, the heat resistance and oxidation resistance of the phase change material layer 11 are more efficiently improved. Can be improved.
なお、実施例２は、耐酸化性を有する絶縁物を有する領域として、窒化処理層１２に代えて、窒化物層２４１を形成する点以外は、実施例１と同様であり、その他の相変化メモリの構成及び製法については、説明を省略する。
Example 2 is the same as Example 1 except that a nitride layer 241 is formed instead of the nitriding layer 12 as a region having an insulating material having oxidation resistance, and other phase changes are performed. Description of the configuration and manufacturing method of the memory is omitted.
実施例３では、より耐熱性及び耐酸化性に優れた相変化部を有し、かつ短期間での製造が可能な三次元型相変化メモリの例を、図２４を用いて説明する。図２４に、実施例３の三次元型相変化メモリの製造方法の一工程における断面模式図を示す。
In Example 3, an example of a three-dimensional type phase change memory having a phase change part with more excellent heat resistance and oxidation resistance and capable of being manufactured in a short period will be described with reference to FIG. FIG. 24 is a schematic cross-sectional view in one step of the manufacturing method of the three-dimensional type phase change memory according to the third embodiment.
実施例３では、相変化材料層１１の主面１１１に接触させるように、窒化物のフィル部２４２が形成されている。すなわち、メモリホール５２の相変化材料層１１で囲まれた領域は、窒化物のフィル部２４２により充填されている。窒化物のフィル部２４２により、相変化材料層１１の酸化の酸化が防止されかつ熱安定性が向上されるとともに、窒化物のフィル部２４２形成工程の後、ギャップフィル部１４を形成する必要がない。すなわち、ギャップフィル部１４の形成工程が省略されることで、製造に要する時間を短縮することが出来る。窒化物のフィル部２４２の形成は、例えば塗布法やＣＶＤ法により行うことができる。
In Example 3, a nitride fill portion 242 is formed so as to be in contact with the main surface 111 of the phase change material layer 11. That is, the region surrounded by the phase change material layer 11 in the memory hole 52 is filled with the nitride fill portion 242. The nitride fill portion 242 prevents oxidation of the phase change material layer 11 and improves thermal stability, and it is necessary to form the gap fill portion 14 after the nitride fill portion 242 formation step. Absent. That is, the time required for manufacturing can be shortened by omitting the step of forming the gap fill portion 14. The nitride fill portion 242 can be formed, for example, by a coating method or a CVD method.
なお、実施例３は、耐酸化性を有する絶縁物を有する領域として、窒化処理層１２又は窒化物層２４１に代えて、窒化物のフィル部２４２を形成する点以外は、実施例１、２と同様であり、その他の相変化メモリの構成及び製法については、説明を省略する。
The third embodiment is different from the first and second embodiments except that a nitride fill portion 242 is formed instead of the nitridation treatment layer 12 or the nitride layer 241 as a region having an oxidation resistant insulator. The description of other phase change memory configurations and manufacturing methods is omitted.
１１、３１…相変化材料層、１１１…相変化材料層１１の主面（主表面）、１２…窒化処理層、１３…ポリシリコンチャネル、１３１…ポリシリコンチャネル１３の主表面、１４…ギャップフィル部、１５…セル選択ゲート電極、１６、３５…層間絶縁膜、１７…上部電極、１８…ゲート絶縁膜、１９…チャネル、３２…下地電極、３３…導電性電極、３６…積層方向、４１…メモリセル、４２…ビット線、４３…ワード線、５１…相変化メモリセル、５２…メモリホール、５３…相変化材料膜５５の端面と垂直をなす方向、５４…相変化材料膜５５の主面と垂直をなす方向、５５…相変化材料膜、５５１…相変化材料膜５５の主面、６１…メモリチェーン、６２…Ｙチェーン選択素子、６３…下部電極、６４…Ｘチェーン選択素子、１０１…領域、１２１…相変化領域、１２２…相変化材料層１１の上部、１２３…相変化材料層１１の下部、１７０、１８０、１９０…三次元型相変化メモリ（半導体記憶装置）の製造装置、１７１…相変化材料成膜チャンバ、１７２…窒化チャンバ、１７３…ロードアンロード室、１７４…搬送室、１７５…ロボットアーム、１８１…窒化物形成チャンバ、１９１…前洗浄チャンバ、１９２…熱処理チャンバ、１９３…保護膜ＣＶＤ成膜チャンバ、２２１…選択メモリセル、２３１…相変化部、２３２…ポリシリコンＭＯＳ、Ｘ１、Ｘ２、Ｘ３、Ｙ１、Ｙ２、Ｙ３…ゲート電極、２４１…窒化物層、２４２…窒化物のフィル部
DESCRIPTION OF SYMBOLS 11, 31 ... Phase change material layer, 111 ... Main surface (main surface) of phase change material layer 11, 12 ... Nitrided layer, 13 ... Polysilicon channel, 131 ... Main surface of polysilicon channel 13, 14 ... Gap fill Part 15, cell selection gate electrode 16, 35 interlayer insulating film 17 upper electrode 18 gate insulating film 19 channel 32 base electrode 33 conductive electrode 36 laminating direction 41 Memory cell, 42 bit line, 43 word line, 51 phase change memory cell, 52 memory hole, 53 direction perpendicular to end face of phase change material film 55, main surface of phase change material film 55 , 55: phase change material film, 551: main surface of phase change material film 55, 61: memory chain, 62 ... Y chain selection element, 63 ... lower electrode, 64 ... X chain selection element, 101 Region 121, phase change region 122, upper portion of phase change material layer 11, 123, lower portion of phase change material layer 11, 170, 180, 190, manufacturing apparatus of three-dimensional phase change memory (semiconductor memory device) 171 ... phase change material deposition chamber, 172 ... nitriding chamber, 173 ... load / unload chamber, 174 ... transfer chamber, 175 ... robot arm, 181 ... nitride forming chamber, 191 ... precleaning chamber, 192 ... heat treatment chamber, 193 ... Protective film CVD deposition chamber, 221... Selected memory cell, 231... Phase change portion, 232... Polysilicon MOS, X1, X2, X3, Y1, Y2, Y3... Gate electrode, 241. Fill part
Claims (15)
- 相変化材料膜を有する複数の相変化メモリセルが直列に接続されたメモリチェーンを有する半導体記憶装置であって、
前記相変化材料膜には、前記メモリチェーンの中心側の主面側に、耐酸化性を有する絶縁層が形成されていることを特徴とする半導体記憶装置。 A semiconductor memory device having a memory chain in which a plurality of phase change memory cells having a phase change material film are connected in series,
The semiconductor memory device, wherein an insulating layer having oxidation resistance is formed on the phase change material film on a main surface side at a center side of the memory chain. - 前記メモリチェーンは、選択ゲート電極と層間絶縁膜とが電極間に交互に複数積層されてなる積層体を、その積層方向に貫通するように設けられており、
前記相変化材料膜は、絶縁性材料からなるギャップフィル部とゲート絶縁膜との間の領域に、該ゲート絶縁膜を介して前記選択ゲート電極と接続されるように形成されていることを特徴とする請求項１に記載の半導体記憶装置。 The memory chain is provided so as to penetrate a stacked body in which a plurality of select gate electrodes and interlayer insulating films are alternately stacked between the electrodes in the stacking direction,
The phase change material film is formed in a region between a gap fill portion made of an insulating material and a gate insulating film so as to be connected to the selection gate electrode through the gate insulating film. The semiconductor memory device according to claim 1. - 前記絶縁層は、前記相変化材料の窒化処理層であることを特徴とする請求項１に記載の半導体記憶装置。 The semiconductor memory device according to claim 1, wherein the insulating layer is a nitriding layer of the phase change material.
- 前記絶縁層の窒素濃度が、前記相変化材料膜全体の窒素濃度より高いことを特徴とする請求項３に記載の半導体記憶装置。 4. The semiconductor memory device according to claim 3, wherein the nitrogen concentration of the insulating layer is higher than the nitrogen concentration of the entire phase change material film.
- 前記絶縁層の窒素濃度が、２０ａｔ％以上であることを特徴とする請求項４に記載の半導体記憶装置。 5. The semiconductor memory device according to claim 4, wherein the nitrogen concentration of the insulating layer is 20 at% or more.
- 前記相変化材料膜は、相変化材料を主体とする相変化材料層の主面に形成された窒化物層を有することを特徴とする請求項１に記載の半導体記憶装置。 2. The semiconductor memory device according to claim 1, wherein the phase change material film has a nitride layer formed on a main surface of a phase change material layer mainly composed of a phase change material.
- 前記窒化物層は、窒化ケイ素を主体とする層であることを特徴とする請求項６に記載の半導体記憶装置。 7. The semiconductor memory device according to claim 6, wherein the nitride layer is a layer mainly composed of silicon nitride.
- 下部電極上に、選択ゲート電極と相間絶縁膜とを交互に積層して積層体を形成し、
前記積層体を貫通するメモリホールを形成し、
前記メモリホール内の領域に、相変化材料を真空状態で成膜して相変化材料層を形成し、
前記相変化材料層の主表面に、耐酸化性を有する絶縁層を形成することを特徴とする半導体記憶装置の製造方法。 On the lower electrode, a selective gate electrode and an interphase insulating film are alternately laminated to form a laminate,
Forming a memory hole penetrating the laminate;
Forming a phase change material layer in a vacuum state in a region in the memory hole to form a phase change material layer;
A method of manufacturing a semiconductor memory device, comprising forming an insulating layer having oxidation resistance on a main surface of the phase change material layer. - 前記メモリホール内の領域に、該メモリホールの側壁側から順に、ゲート絶縁膜と、ポリシリコンチャネルと、前記相変化材料層及び前記絶縁層を有する相変化材料膜と、を形成した後、
前記相変化材料膜で囲まれた領域に、絶縁性材料を充填してギャップフィル部を形成することを特徴とする請求項８に記載の半導体記憶装置の製造方法。 After forming the gate insulating film, the polysilicon channel, the phase change material layer and the phase change material film having the insulating layer in order from the side wall side of the memory hole in the region in the memory hole,
9. The method of manufacturing a semiconductor memory device according to claim 8, wherein a gap fill portion is formed by filling an insulating material in a region surrounded by the phase change material film. - 前記相変化材料層の主表面を真空中で窒化処理することを特徴とする請求項８に記載の半導体記憶装置の製造方法。 9. The method of manufacturing a semiconductor memory device according to claim 8, wherein the main surface of the phase change material layer is nitrided in a vacuum.
- 前記相変化材料層の主表面に、窒化物層を製膜することを特徴とする請求項８に記載の半導体記憶装置の製造方法。 9. The method of manufacturing a semiconductor memory device according to claim 8, wherein a nitride layer is formed on a main surface of the phase change material layer.
- 対象物に相変化材料を真空状態で製膜して相変化材料層を形成する相変化材料製膜チャンバと、
前記相変化材料層が形成された前記対象物に、耐酸化性を有する絶縁物を真空状態で形成する絶縁物形成チャンバと、
前記相変化材料製膜チャンバ内で前記相変化材料層が形成された前記対象物を、真空状態を維持しつつ前記絶縁物形成チャンバに搬送する搬送室と、
を有することを特徴とする半導体記憶装置の製造装置。 A phase change material deposition chamber for depositing a phase change material on an object in a vacuum state to form a phase change material layer;
An insulator forming chamber for forming an oxidation-resistant insulator in a vacuum state on the object on which the phase change material layer is formed;
A transfer chamber for transferring the object on which the phase change material layer is formed in the phase change material deposition chamber to the insulator forming chamber while maintaining a vacuum state;
An apparatus for manufacturing a semiconductor memory device, comprising: - 前記絶縁物形成チャンバは、前記相変化材料製膜チャンバで形成された前記相変化材料層の窒化処理を行う窒化チャンバであることを特徴とする請求項１２に記載の半導体記憶装置の製造装置。 13. The semiconductor memory device manufacturing apparatus according to claim 12, wherein the insulator forming chamber is a nitriding chamber for performing nitriding treatment of the phase change material layer formed in the phase change material film forming chamber.
- 前記絶縁物形成チャンバは、前記相変化材料製膜チャンバで形成された前記相変化材料層の主表面に窒化物を製膜する窒化物製膜チャンバであることを特徴とする請求項１２に記載の半導体記憶装置の製造装置。 13. The nitride film forming chamber according to claim 12, wherein the insulator forming chamber is a nitride film forming chamber for forming nitride on a main surface of the phase change material layer formed in the phase change material film forming chamber. Semiconductor memory device manufacturing apparatus.
- 相変化材料製膜チャンバで前記相変化材料層を製膜処理する前の対象物の前洗浄を行う前洗浄チャンバと、
前記絶縁物形成チャンバで絶縁物が形成された対象物を、熱処理により真空中アニールする熱処理チャンバと、
前記絶縁物形成チャンバで絶縁物が形成された対象物上に、保護膜を製膜する保護膜チャンバとをさらに有することを特徴とする請求項１２に記載の半導体記憶装置の製造装置。 A pre-cleaning chamber for pre-cleaning an object before forming the phase-change material layer in the phase-change material film forming chamber;
A heat treatment chamber for annealing the object on which the insulator is formed in the insulator formation chamber in a vacuum by heat treatment; and
13. The semiconductor memory device manufacturing apparatus according to claim 12, further comprising a protective film chamber for forming a protective film on an object on which an insulator is formed in the insulator forming chamber.
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