WO2016184840A2 - Cellule solaire et procédé de réalisation d'une cellule solaire présentant des zones intermédiaires oxydées entre des contacts de polysilicium - Google Patents

Cellule solaire et procédé de réalisation d'une cellule solaire présentant des zones intermédiaires oxydées entre des contacts de polysilicium Download PDF

Info

Publication number
WO2016184840A2
WO2016184840A2 PCT/EP2016/060989 EP2016060989W WO2016184840A2 WO 2016184840 A2 WO2016184840 A2 WO 2016184840A2 EP 2016060989 W EP2016060989 W EP 2016060989W WO 2016184840 A2 WO2016184840 A2 WO 2016184840A2
Authority
WO
WIPO (PCT)
Prior art keywords
regions
type doped
layer
silicon
doped regions
Prior art date
Application number
PCT/EP2016/060989
Other languages
German (de)
English (en)
Other versions
WO2016184840A3 (fr
Inventor
Robby Peibst
Udo Römer
Original Assignee
Institut Für Solarenergieforschung Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institut Für Solarenergieforschung Gmbh filed Critical Institut Für Solarenergieforschung Gmbh
Publication of WO2016184840A2 publication Critical patent/WO2016184840A2/fr
Publication of WO2016184840A3 publication Critical patent/WO2016184840A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/546—Polycrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a method for producing a solar cell and to a correspondingly producible solar cell.
  • Solar cells are used for photovoltaic conversion of light into electrical power.
  • a solar cell is manufactured on the basis of a semiconductor substrate, for example a silicon substrate.
  • a semiconductor substrate for example a silicon substrate.
  • both p-type doped regions and n-type doped regions are provided, which form base or emitter regions of the solar cell. In regions between the base and emitter regions forms an electrical
  • Potential difference for example in the form of a pn junction, from which charge carrier pairs generated by absorbed light can be separated.
  • both types of contact ie contacts which make contact with the base regions and also contacts which make contact with emitter regions, are arranged on a rear side of the semiconductor substrate facing away from the sun.
  • the contacts Both types of contact are thus arranged laterally adjacent to each other and extend at the back of the solar cell usually in the form of, for example, comb-like into one another
  • Silicon substrates both p-type doped regions and n-type doped regions are provided, each of an associated contact of a corresponding
  • the p-type doped regions and the n-type doped regions are in this case formed as a layer applied to the silicon substrate and consist of polycrystalline silicon (poly-Si) or amorphous silicon (a-Si).
  • poly-Si polycrystalline silicon
  • a-Si amorphous silicon
  • Silicon substrate usually consists of monocrystalline or multicrystalline silicon.
  • a very thin dielectric layer for example of silicon oxide, is usually provided between the p-type doped regions or the n-type doped regions and the silicon substrate serving as the absorber.
  • a very thin dielectric layer for example of silicon oxide.
  • very high efficiencies were observed, which is due to a particularly good passivation of the surfaces of the silicon substrate and thus particularly low recombination losses.
  • a method for producing a solar cell which has at least the following method steps, preferably in the order given.
  • a silicon substrate is provided.
  • an interface dielectric layer for example, in the form of only a few nanometers thick
  • Silicon layer of amoiphemic or polycrystalline silicon deposited, wherein the silicon layer laterally adjacent to each other p-type doped regions and n-type doped regions. The silicon layer is then interposed in intermediate areas
  • a solar cell is described, as can be produced in particular by means of the method according to the first aspect.
  • the solar cell comprises a silicon substrate, an interfacial dielectric layer on a surface of the silicon substrate, a silicon layer of amorphous or polycrystalline silicon on the interfacial dielectric layer, and p-type contacts and n-type contacts.
  • the silicon layer has laterally adjacent p-type doped regions and n-type doped regions and is present in intermediate regions between adjacent p-type doped regions and n-type doped regions over their entire layer thickness oxidized.
  • the p-contacts contact the p-type doped regions of the silicon layer, and the n-ontacts contact the n-type doped regions of the silicon layer.
  • Embodiments of the invention are briefly summarized inter alia as being based on the findings and ideas described below.
  • Silicon substrate can be achieved. However, it was also observed that in the p-type doped regions and the n-type doped regions of the polycrystalline or
  • amorphous silicon layer especially in the intermediate regions, i. where they adjoin one another adjacent to each other, a strong recombination can occur, which can lead to losses in efficiency.
  • This is attributed, inter alia, to the fact that in the polycrystalline or amorphous silicon layer, as compared to a monocrystalline or multicrystalline silicon layer, there are typically many impurities or impurities acting as recombination centers. Especially in the intermediate areas, these recombination centers seem to have a negative effect on the efficiency of the solar cell.
  • Solar cell efficiency It is proposed there to separate the differently doped regions of the poly-Si layer by means of a trench from each other.
  • the trench can be generated for example by local etching.
  • Process steps such as a supplementary deposition of a passivation layer may be required.
  • the silicon layer can be deposited and left as a large-area layer, and only in the intermediate areas, i. where the n-type regions are closest to or directly adjacent to the p-type regions, the silicon layer is locally oxidized in a specially adapted oxidation process.
  • the polycrystalline or amorphous silicon layer can thus be used both in the p-type doped regions and the n-type doped regions as well as in the oxidized
  • Intermediate areas have a substantially constant thickness, i. the layer thickness should be less than 50% relative to all regions of the silicon layer, for example,
  • Areas and the n-type doped areas are oxidized to have the same or even greater layer thickness after Aufoxidieren as before the oxidation.
  • a volume of the layer in the oxidized areas can even increase significantly locally, i. depending on the initial configuration and
  • the oxidized intermediate regions produced in this manner cause both an electrical separation between the adjacent n-type regions and p-type regions and a very efficient passivation in these intermediate regions.
  • the oxidized intermediate regions preferably extend along the entire edges of the adjacent p-type doped regions and n-type doped regions of the polycrystalline and amorphous silicon layer, respectively, and passivate the underlying substrate excellently.
  • the locally limited oxidation of the intermediate areas can be carried out technologically simple and with industrially common process steps or process sequences.
  • An electrical separation and passivation of the adjacent p-type doped regions and n-type doped regions of the polycrystalline or amorphous silicon layer can thus be implemented cost-effectively and reliably in terms of process technology.
  • the locally limited oxidation-on of the silicon layer is carried out in such a way that the silicon layer in the intermediate regions is oxidized over its entire layer thickness.
  • the polycrystalline or amorphous silicon layer is to be locally oxidized in the intermediate regions so strongly or so long until their silicon provided there is oxidized over the entire layer thickness towards silicon oxide (SiO 2). After such an oxidation, a silicon oxide layer produced thereby extends transversely through the polycrystalline or amorphous layer
  • a structured oxidation barrier layer is applied which has sufficient thickness in first regions remote from the intermediate regions to protect underlying regions of the silicon layer against oxidation in an oxidation process and in second regions adjacent to the intermediate regions has a smaller or vanishing thickness to allow oxidation locally in the underlying areas of the silicon layer in the context of the oxidation process.
  • an oxidation barrier layer can be applied to the polycrystalline or amorphous silicon layer, which protects the latter locally against oxidation during an oxidation process.
  • the oxidation barrier layer may in this case be designed or structured in such a way that during the oxidation process in the second regions, ie near and / or at the intermediate regions, oxygen is allowed to penetrate into the silicon layer and thus oxidize. In contrast, in the first regions, ie, away from the intermediate regions, the oxidation barrier layer can largely prevent such oxygen penetration. In the first regions, the
  • Oxidation barrier layer thus be dense to oxygen, i. essentially not let oxygen through.
  • the oxidation barrier layer may be, for example, a dielectric layer.
  • the oxidation barrier layer may be silicon nitride (Si x N y , eg Si 3 N 4 ),
  • Silicon oxide SiO x , eg Si0 2
  • silicon oxynitride Si x O y N z
  • Silicon nitride has proven to be a very efficient oxidation barrier. Even a layer with a layer thickness of at least 20 nm, preferably at least 50 nm, may be sufficient to sufficiently inhibit the oxidation of the underlying silicon layer. At a layer thickness of more than 100 nm, even with strongly oxidizing process steps, i. especially at high process temperatures, essentially no further oxidation of underlying layers.
  • a layer of silicon dioxide (S1O2) which has a layer thickness of at least 100 nm, preferably at least 200 nm, as sufficient
  • Oxidation barrier layer act.
  • the oxidation banana layer should preferably have a thickness of less than 5nm, preferably less than lnm.
  • the oxidation barrier layer should be at least so thin in the second regions that it does not substantially penetrate oxygen to the underlying
  • Silicon layer hinders. Preferably, none can occur in the second regions
  • Oxidation barrier layer be provided, i. the oxidation barrier layer a
  • the Oxid michid michidtechniksbanieren harsh is first applied as a whole-area layer and then removed material of Oxid michsbanier harsh locally in the second regions.
  • the oxidation banana layer can only be used as a spatially homogeneous layer, i. both in the first and in the second regions, are deposited on the silicon layer and then partially thinned out in the second regions or preferably completely removed. Material of the
  • Oxidierungsban Schluensky can be etched away locally, for example, or evaporated by means of a laser or ablated. Such process steps or process sequences can be implemented easily and reliably industrially.
  • the oxidation barrier layer may be formed, for example, by a printing technique, such as e.g. Screen printing, stencil printing or inkjet printing can be applied as a structured layer.
  • the oxidation barrier layer is not applied over the entire surface but selectively only locally to the first regions, but not to the second regions.
  • the Oxidleitersbanier Anlagen can be printed, for example, using dielectric pastes. Imprinting of a structured Oxid michsbanier Anlagen can be realized inexpensively on an industrial scale.
  • the localized oxidation of the silicon layer is performed by dry and / or wet chemical oxidation.
  • the silicon substrate provided with the polycrystalline or amorphous silicon layer is exposed to an oxygen-containing atmosphere at high temperatures of, for example, more than 700 ° C.
  • a wet thermal oxidation is carried out with the addition of water vapor and usually leads to a faster
  • Silicon oxide produced by thermal oxidation is e.g. known to passivate surfaces of silicon very well and thus is particularly well suited as a passivating separation between adjacent p-type and n-type doped regions of the silicon layer.
  • the p-type doped regions and the n-type doped regions differ in local oxidation during their local oxidation
  • Oxidation rates and the intermediate regions include both edge regions of the p-type doped regions and adjacent edge regions of the n-type doped regions.
  • the oxidation-oxidation of the silicon layer is then carried out in such a way that the silicon layer is oxidized over its entire layer thickness either in the p-type doped edge regions or in the n-type doped edge regions, but in the other,
  • oppositely doped edge regions is not oxidized over its entire layer thickness down.
  • the p-type doped regions and the n-type doped regions may differ in their oxidizability, in particular depending on a concentration of dopants contained therein.
  • concentration of dopants contained therein typically, the higher a dopant concentration contained in it, the faster it oxidizes a silicon layer.
  • This property can be exploited if, for example, both edge regions of a heavily doped p-type doped region and edge regions of a less heavily doped n-type doped region (or vice versa) are contained during the oxidation in the intermediate regions left free by an oxidation barrier layer.
  • the oxidation process can then be carried out for so long that the heavily doped edge region is completely oxidized, ie, over its entire layer thickness, whereas it is weaker doped edge region only partially, ie only over part of its entire
  • positioning the contacts e.g. in the context of a screen printing of the contacts can be made with greater tolerances.
  • a passivation of the silicon substrate due to the large area remaining in the silicon layer, non-oxidized regions can be very good.
  • Edge regions have a greater width than the oppositely doped edge regions. In other words, for example, at a
  • Oxidianssbarr Schlieren harsh the oxidation of a locally permitting second regions be chosen such that they do not symmetrically cover edge regions of adjacent p-type doped regions and n-type doped regions, but further in those edge region rich, for example, is weaker doped and thus oxidized slower becomes. Areas in which advantageously oxidized on an outer surface of the silicon
  • Silicon layer and further inside non-oxidized polycrystalline or amorphous silicon exists can thus be made advantageously large.
  • a solar cell according to the invention may have, in addition to the structures and features mentioned, further structures and features, such as e.g. further layers, which are e.g. act as passivation layers, protective layers, antireflection layers or the like.
  • Figure 1 (a) to (j) illustrates a processing sequence of a method for
  • FIGS. 2 (e) and (f) illustrate process steps of a processing sequence of FIG
  • a method of manufacturing a solar cell according to an alternative embodiment of the present invention is a method of manufacturing a solar cell according to an alternative embodiment of the present invention.
  • FIG. 3 shows an enlarged view of an image detail marked in FIG. 2 (f).
  • the details shown in the figures are each only schematically illustrated and not reproduced to scale.
  • Like reference numerals refer to like or equivalent features throughout the several parts of the figures.
  • Figure lj illustrates a finished solar cell according to a
  • Embodiment of the invention as it can be produced by a method according to the invention.
  • sectional views are each represented by parts of a solar cell. For reasons of illustration, size ratios are not
  • a silicon substrate 3 is initially provided.
  • Silicon substrate for example, a wafer of crystalline, in particular
  • the silicon substrate 3 may typically have thicknesses in the range of 50 to 500 ⁇ m, preferably 100 to 300 ⁇ m. Lateral dimensions are typically in the range of 10 x 10 cm 2 to 20 x 20 cm 2 .
  • a damage introduced, for example, by a preceding sawing operation has been removed from surfaces of the silicon substrate 3, ie
  • Silicon substrate 3 superficially etched back, and / or the silicon substrate 3 cleaned.
  • the silicon substrate 3 may be n-type doped or p-type doped. In the example described below, an n-type doped silicon substrate 3 is assumed.
  • Surface morphology of the silicon substrate 3 can be either planar on the front and back, as shown in Figure la.
  • front panel shown above be textured and the back may be planar or textured both front and back textured.
  • an interface dielectric layer 5 is subsequently produced on a surface of the silicon substrate 3.
  • the interface dielectric layer 5 can be produced, for example, as a thin oxide layer. In this case, it may have a thickness of typically between 1 nm and 5 nm.
  • Such thin oxide layers are sometimes also referred to as tunnel oxide layers, since charge carriers can optionally tunnel through them and thus an electrically conductive contact between
  • adjacent structures can be established through the oxide layer.
  • the interfacial dielectric layer 5 should have a very good
  • the interfacial dielectric layer 5 should be of high quality, i. as few impurities and / or impurities in and at the interface to the
  • the interfacial dielectric layer 5 may be wet-chemically oxidized during or subsequent to an oxidizing step
  • Cleaning procedure in a thermal oxidation, in an ozone atmosphere or by chemical vapor deposition (CVD), optionally plasma assisted or thermally assisted in a low pressure process, are generated.
  • CVD chemical vapor deposition
  • a silicon layer 7 of amorphous or polycrystalline silicon is then deposited on the interface dielectric layer 5.
  • Silicon layer 7 may be substantially thicker than interfacial dielectric layer 5. Typically, this silicon layer is deposited to a thickness in the range of 5 nm to 500 nm, preferably between 40 and 100 nm.
  • the silicon layer 7 can be undoped, p Type-doped or n-type doped deposited. In the illustrated example, the silicon layer 7 is p-type doped, ie of the opposite doping type as that
  • the amorphous or polycrystalline silicon layer 7 may be deposited by various deposition methods. For example, it can be deposited using chemical vapor deposition (CVD). In particular, plasma-assisted CVD (PECVD) allows deposition of high-quality silicon layers. Alternatively, the silicon layer 7 may also be deposited using thermally assisted CVD in a low pressure process. As a further alternative, the silicon layer 7 can also be applied by means of a silicon-containing solution.
  • CVD chemical vapor deposition
  • PECVD plasma-assisted CVD
  • the silicon layer 7 may also be deposited using thermally assisted CVD in a low pressure process.
  • the silicon layer 7 can also be applied by means of a silicon-containing solution.
  • the amorphous polycrystalline silicon layer 7 is of lower electronic quality than the silicon substrate 3, ie, an impurity density and / or a density of impurities is higher in the silicon layer 7 than in the monocrystalline or multicrystalline silicon substrate 3, and accordingly, a carrier lifetime in FIG of the
  • laterally adjacent p-type doped regions 9 and n-type doped regions 11 are formed in the silicon layer 7.
  • the p-type doped regions 9 can be directly adjacent to the n-type doped regions 1 1.
  • undoped or intrinsic regions may exist between the p-type doped regions 9 and the n-type doped regions 11 (not shown).
  • the p- and n-type doped regions 9, 11 may, for example, extend in the form of elongated interlaced fingers along the back side of the silicon substrate 3 and may typically have feature widths in the range of 0.05 to 10 mm, preferably in the range of 0, 1 to 3 mm.
  • the amorphous or polycrystalline silicon layer 7 has already been deposited in situ p-type doped, only an additional realization of local net n-type doped regions 11 is necessary.
  • the previously existing p-type Doping be locally overcompensated by local introduction of dopants locally. If the silicon layer 7 is n-type doped, local overcompensation with acceptor-like dopants is possible to produce net p-type doped regions. If the amorphous or polycrystalline silicon layer 7 had been deposited undoped, would be in this
  • Process step a generation of local n-type doped regions 11 and local p-type doped regions 9 necessary.
  • the generation of laterally adjacent p-type doped and n-type doped regions 9, 11 can take place, for example, by means of masked ion implantation.
  • the generation of locally doped regions 11 by overcompensation of a previously existing doping in the silicon layer 7 may in this case require a masked implantation step in which a suitably structured mask 13 protects those regions 9 which are to remain p-type doped against the penetration of ion beams 15 protects.
  • Implantation steps can be performed masked. Alternatively, a full-area first implantation can be performed, wherein a dose should be chosen low enough to allow local overcompensation by dopants of the opposite polarity.
  • locally adjacent p-type doped regions 9 and n-type doped regions 11 may also be produced by other methods.
  • doped regions can be generated by means of thermal diffusion, for example by locally doping dopants from a BBr 3 -containing or POCb-containing atmosphere or from a dopant-containing oxide layer formed in a dopant-containing atmosphere at high temperatures Silicon layer 7 are diffused.
  • a diffusion of dopants from structured applied doping sources such as boron or phosphorus-containing layers done.
  • differently doped silicon-containing layers can be applied locally.
  • the amorphous or polycrystalline silicon layer 7 is provided with local p-type doped regions 9 and n-type doped regions 11 arranged adjacent to one another up to the process step shown in FIG. 1d, it extends as
  • the p-type doped regions 9 either directly adjoin the n-type doped regions 11 or are connected to these at least via semiconductor-like undoped or intrinsic regions.
  • increased local recombination may occur in intrinsic regions, which may affect the efficiency of the resulting solar cell.
  • Oxidation barrier layer 17 are applied to the outwardly exposed surface of the silicon layer 7.
  • This oxidation barrier layer 17 may be structured such that it forms a mask which leaves only intermediate regions 19 between adjacent p- and n-type doped regions 9, 1 1 unprotected.
  • the oxidation barrier layer 17 may be, for example, a dielectric layer, for example, silicon nitride, silicon oxide, silicon oxynitride, or the like.
  • Oxidation barrier layer 17 may have a sufficient thickness in first regions 21, which are laterally removed to the intermediate regions 19, to a diffusion or penetration of oxygen or OH groups toward the surface of the amorphous or polycrystalline in a subsequent oxidation process Silicon layer 7 to prevent or slow down.
  • the oxidation barrier layer 17 has a substantially smaller thickness, for example less than 5 nm, or is completely removed in these second regions, i. open, so as part of a
  • Oxidation process in the underlying intermediate regions 19 can diffuse oxygen or OH groups and thus an oxidation is locally approved.
  • the oxidation barrier layer 17 can first be applied over the whole area and then patterned.
  • the structuring may be wet-chemically, for example, via locally printed etching pastes or etching barriers or by means of
  • the oxidation barrier layer 17 can be applied in a structured manner, for example by screen printing or inkjet printing of oxide or nitride-containing layers.
  • an oxidation barrier layer 17 may be applied not only to the back surface of the silicon layer 7 on the back side of the silicon substrate 3 but also to the front surface of the silicon substrate 3 or to an interface dielectric layer 5 and / or silicon layer 7 formed thereon become.
  • the oxidation barrier layer 17 may optionally later remain on the silicon substrate 3 and, for example, an improvement of optical properties,
  • the oxidation barrier layer 17 in a subsequent process step as protection for the back, for example, during a texturing process of
  • the amorphous or polycrystalline silicon layer 7 is subsequently oxidized locally into the second regions 23 which have been left free by the oxidation barrier layer 17, ie in the intermediate regions 19.
  • the silicon substrate 3, together with the silicon layer 7 applied thereon can be subjected to a dry or moist thermal oxidation in which oxygen or OH groups in the unprotected second regions 23 reach the silicon layer 7 and oxidize the silicon there.
  • the oxidation process is carried out until the silicon layer 7 is oxidized in the intermediate regions 19 over their entire layer thickness.
  • a silicon oxide layer 25 formed in this process completely separates the amorphous or polycrystalline layer 7 in the intermediate regions 19, ie between adjacent p-type regions 9 and n-type regions 11.
  • Silicon oxide layer 25 locally the surface of the silicon substrate 3rd
  • a high-temperature step used for local oxidation can improve properties of contact between the p- and n-type doped regions 9, 11 of the silicon layer 7 with the silicon substrate 3.
  • an oxide layer 27 can also be produced on the front side of the silicon substrate, provided that side of the silicon substrate 3 is not protected over its entire surface by an oxidation barrier layer. As shown in FIG. 1g, the oxide layer 27 produced in the described example on the front side of the silicon substrate 3 can subsequently be removed, while the dielectric layers can remain on the back side. Should the front side have been protected by a dielectric oxidation buffer layer during the preceding oxidation process, this too can subsequently be removed again.
  • a one-sided removal of the oxide layer 27 or an oxidation buffer layer can be carried out, for example, in a suitably wet-chemical system or by means of plasma etching.
  • the front side of the silicon substrate 3 can subsequently be textured.
  • the oxidation buffer layer 17 and the silicon oxide 25 can protect the back surface of the silicon substrate 3.
  • proper cleaning may take place to prepare the front for subsequent passivation.
  • this step can be omitted.
  • the silicon substrate 3 should have received an amorphous layer 7 and / or an underlying interface oxide 5 on the front side not only on the back side but also on the front side in the preceding processing, these layers may also be used in texturing the front side to be removed.
  • the front side of the silicon substrate 3 can then be passivated with a dielectric layer 29, for example.
  • This layer 29 can additionally achieve an anti-reflection effect.
  • the silicon substrate 3 has already received a front side texture at the beginning of the processing sequence and the front side has also been passivated with an amorphous or polycrystalline silicon layer, where appropriate, only a layer is applied at this point, which provides an anti-reflection effect.
  • the layer 29 may be either a single dielectric layer or a stack of multiple dielectric layers, for example a stack of an alumina layer and a silicon nitride layer.
  • Various deposition methods that can also be combined with each other, such as plasma-assisted
  • PECVD Chemical vapor deposition
  • ALD atomic layer deposition
  • LPCVD low pressure chemical vapor deposition
  • p-type contacts 31 which contact the p-type doped regions 9 and n-type contacts 33 which contact the n-type doped regions 11 of the silicon layer 9 can subsequently be produced ,
  • Silicon substrate 3 produced by screen printing.
  • the contacts 31, 33 for both polarities can already be applied in a structured manner and do not have to be subsequently separated, as in the case of an initially full-area metal deposition.
  • a screen printing paste is used, which is initially printed locally limited to remaining in the first regions OxidationsbaiTieren Anlagen 17 and cause their components in a subsequent fire process at high temperatures above 600 ° C, a local dissolution of the underlying oxidation barrier layer 17. As shown in FIG. 1j, such a "firing" paste penetrates the
  • Oxidation barrier layer 17 It is therefore not absolutely necessary, previously local
  • non-firing screen-printing pastes can be used, in which case optionally in advance contact openings in intermediate insulating Layers such as the oxidation barrier layer 17 would have to be generated.
  • metallization could also be used by physical vapor deposition (PVD), electroplating, or a combination of these techniques.
  • Figure 3 illustrates an enlarged view of the area labeled "A" in Figure 2f but in a more advanced processing stage where the oxidation barrier layer 17 has already been removed and contacts 31, 33 have been applied
  • the oxidation barrier layer 17 is patterned such that edge regions 35 of lower dopant concentration p-type doped regions 9, in which the mask caused by the oxidation barrier layer 17 subsequently allows for oxidizing the amorphous silicon layer 7, are wider as edge regions 37 of n-type doped regions 11 formed with a higher doping concentration, which likewise depend on the
  • Oxidation barrier layer 17 remain unmasked.
  • the second regions 23 not masked by the oxidation buffer layer 17 are asymmetrical with respect to the interface between adjacent p-type regions. doped regions 9 and n-type doped regions 1 1, so that the intermediate regions 19 not masked by the oxidation barrier layer 17 extend mainly over the p-type doped regions 9 and less over the n-type doped regions 11.
  • the n-type doped regions 11, which are substantially smaller and are substantially more heavily doped in the illustrated example, are almost completely separated from the
  • oxidation barrier layer 17 Covered oxidation barrier layer 17 and thus protected against oxidation, whereas the oxidation barrier layer 17 is applied to the larger area and much weaker doped p-type doped regions 9 only in small areas, that is only where later, for example, contact openings for associated p-contacts are to arise ,
  • FIG. 1 j thus shows an embodiment of a finished-processed solar cell 1 in which p-type doped regions 9 and n-type doped regions 11 are separated from one another on the rear side of the silicon substrate 3 by an oxide layer 25 produced by local oxidation on top of each other.
  • the amorphous or polycrystalline silicon layer 7 has a substantially constant thickness both in the p-type doped regions 9 and the n-type doped regions 11 and in the oxidized intermediate regions 19.
  • the edge region 35 of the weakly doped p-type doped regions 9 also left free by the oxidation barrier layer 17 is only partially oxidized due to its lower rate of oxidation. Adjacent to the interface dielectric layer 5, a portion 39 of the p-type doped regions 9 remains in a non-oxidized state, ie, furthermore in the form of amorphous or polycrystalline silicon.
  • Process parameters ie in particular a duration of the oxidation process, should in this embodiment therefore be selected on the one hand such that in the faster oxidizing n-type edge regions 37, oxidation over the entire layer thickness of the On the other hand, however, so that in the slower oxidizing p-type edge regions 35, a Aufoxidation only over parts of the layer thickness of
  • Silicon layer 7 out and parts 39 of the silicon layer remain unoxidized.
  • the p-type doped regions 9 thus have a "T" -shaped structure after onoxidation
  • the non-oxidized parts 39 of the edge regions 35 of the p-type doped regions 9 in the intermediate regions 19 and adjacent to the interfacial dielectric layer 5 can thereby ensure optimum passivation on the back of the solar cell produced in this way.
  • the intermediate regions 19 thus comprise both edge regions 35 of the p-type doped regions 9 and adjacent edge regions 37 of the n-type doped regions 1 1.
  • the n-type doped edge regions 37 are over their entire layer thickness is oxidized and the oppositely doped edge regions 35 are not oxidized over their entire layer thickness.
  • the configuration of the edge regions 35, 37 can also be reversed.
  • the deoxidized parts 41 in this edge region 35 can be used, for example, after a selective removal of the oxidation barrier layer 17 for improving the optical properties of the back side of the solar cell, since the silicon oxide layer 25 formed by the oxidation on can improve the optical reflectivity at the backside of the solar cell.
  • a kind of self-alignment can advantageously be achieved in a subsequent application of p-contacts and n-contacts.
  • it can be exploited, for example, that after removing the oxidation barrier layer 17, only the non-oxidized parts 43 of the p-type doped regions 9 are exposed on a rear surface of the silicon layer 7, whereas other parts 39 of these p-type doped regions 9 are protected by the overlying oxidized parts 41 against electrical contact from the outside.
  • Parts of the p-type doped regions 9 and the n-type doped regions 11 which are exposed on the rear surface of the silicon layer 7 are thus separated from one another by relatively wide intermediate regions 19 which are at least superficially oxidized.
  • p-contacts 31 and n-contacts 33 can be advantageous, for example, when applying p-contacts 31 and n-contacts 33 by means of screen printing, since only relatively large spatial tolerances need to be observed when printing on screen-printing pastes.
  • p-type contacts 31 and n-type contacts 33 may be printed imprecisely positioned protruding into the intermediate regions 19, without resulting in unwanted short circuits, since the broad silicon oxide layers of the edge regions produced there by the oxidation-on process 35, 37 are electrically insulating and thus prevent short circuits.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Sustainable Development (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Energy (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Photovoltaic Devices (AREA)

Abstract

L'invention concerne un procédé de réalisation d'une cellule solaire (1), présentant les étapes consistant : (a) à fournir un substrat de silicium (3) ; (b) à produire une couche diélectrique de surface limite (5) sur une surface du substrat de silicium (3) ; (c) à déposer une couche de silicium (7) en silicium amorphe ou polycristallin sur la couche diélectrique de surface limite (5), la couche de silicium (7) présentant des zones dopées p (9) et des zones dopées n (11) voisines latéralement entre elles ; (d) à réaliser une oxydation limitée localement de la couche de silicium (7) dans des zones intermédiaires (19) entre des zones dopées p (9) et des zones dopées n (11) voisines ; (e) à produire des contacts p (31) qui mettent en contact les zones dopées p (9) de la couche de silicium (7), et des contacts n (33) qui mettent en contact les zones dopées n (11) de la couche de silicium (7). L'oxydation limitée localement permet aux zones dopées p (9) et zones dopées n (11) voisines d'être séparées électriquement tout en assurant une bonne passivation.
PCT/EP2016/060989 2015-05-19 2016-05-17 Cellule solaire et procédé de réalisation d'une cellule solaire présentant des zones intermédiaires oxydées entre des contacts de polysilicium WO2016184840A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102015107842.2 2015-05-19
DE102015107842.2A DE102015107842B3 (de) 2015-05-19 2015-05-19 Verfahren zum Herstellen einer Solarzelle mit oxidierten Zwischenbereichen zwischen Poly-Silizium-Kontakten

Publications (2)

Publication Number Publication Date
WO2016184840A2 true WO2016184840A2 (fr) 2016-11-24
WO2016184840A3 WO2016184840A3 (fr) 2017-02-02

Family

ID=55971020

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2016/060989 WO2016184840A2 (fr) 2015-05-19 2016-05-17 Cellule solaire et procédé de réalisation d'une cellule solaire présentant des zones intermédiaires oxydées entre des contacts de polysilicium

Country Status (2)

Country Link
DE (1) DE102015107842B3 (fr)
WO (1) WO2016184840A2 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020170830A (ja) * 2019-04-05 2020-10-15 株式会社アルバック ＴＯＰＣｏｎ−ＢＣ構造の結晶系太陽電池の製造方法、及びＴＯＰＣｏｎ−ＢＣ構造の結晶系太陽電池
EP3982421A1 (fr) 2020-10-09 2022-04-13 International Solar Energy Research Center Konstanz E.V. Procédé de modification locale de la résistance à la gravure dans une couche de silicium, utilisation de ce procédé pour la production de cellules solaires à contact de passivation et cellule solaire ainsi créée

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7812250B2 (en) 2008-06-12 2010-10-12 Sunpower Corporation Trench process and structure for backside contact solar cells with polysilicon doped regions
US20120322199A1 (en) 2011-06-15 2012-12-20 Varian Semiconductor Equipment Associates, Inc. Patterned doping for polysilicon emitter solar cells
US20140090701A1 (en) 2012-09-28 2014-04-03 Sunpower Corporation Spacer formation in a solar cell using oxygen ion implantation

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61134065A (ja) * 1984-12-04 1986-06-21 Fuji Electric Co Ltd サイリスタの製造方法
JP2010232530A (ja) * 2009-03-27 2010-10-14 Sharp Corp 光電変換素子の製造方法および光電変換素子
DE102010004497A1 (de) * 2010-01-12 2011-07-14 centrotherm photovoltaics AG, 89143 Verfahren zur Erhöhung des Schichtwiderstands in einem dotierten Halbleiterbereich
KR101186529B1 (ko) * 2011-10-26 2012-10-08 엘지전자 주식회사 태양 전지
KR101613843B1 (ko) * 2013-04-23 2016-04-20 엘지전자 주식회사 태양 전지 및 이의 제조 방법
KR101627204B1 (ko) * 2013-11-28 2016-06-03 엘지전자 주식회사 태양 전지 및 이의 제조 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7812250B2 (en) 2008-06-12 2010-10-12 Sunpower Corporation Trench process and structure for backside contact solar cells with polysilicon doped regions
US20120322199A1 (en) 2011-06-15 2012-12-20 Varian Semiconductor Equipment Associates, Inc. Patterned doping for polysilicon emitter solar cells
US20140090701A1 (en) 2012-09-28 2014-04-03 Sunpower Corporation Spacer formation in a solar cell using oxygen ion implantation

Also Published As

Publication number Publication date
DE102015107842B3 (de) 2016-10-27
WO2016184840A3 (fr) 2017-02-02

Similar Documents

Publication Publication Date Title
EP3930013B1 (fr) Procédé de fabrication d'une cellule solaire photovoltaïque dotée d'au moins une hétérojonction
DE69837143T2 (de) Ein Verfahren zur Herstellung einer Solarzelle
EP3378104B1 (fr) Cellule solaire comprenant plusieurs absorbeurs reliés entre eux par des contacts sélectifs porteurs de charge
EP1872411B1 (fr) Cellule solaire a contact arriere et procede de fabrication associe
WO2009074469A2 (fr) Cellule solaire à contact arrière comportant des zones d'émetteur de côté arrière de grande surface et procédé de fabrication de la cellule solaire
DE102009025977A1 (de) Solarzelle und Herstellungsverfahren einer Solarzelle
DE112017001811B4 (de) Dreischichtige Halbleiterstapel zum Bilden von Strukturmerkmalen auf Solarzellen
WO2015044122A1 (fr) Procédé de fabrication d'une cellule solaire photovoltaïque comprenant une hétérojonction et une zone dopée par diffusion sur deux surfaces différentes
WO2011091959A2 (fr) Procédé de dopage élevé local et de mise en contact d'une structure semi-conductrice qui est une cellule solaire ou une ébauche de cellule solaire
DE212021000261U1 (de) Vergrabene Solarzelle mit einem selektiven Kontaktbereich und zugehörige Rückseitenkontaktstruktur
EP2135291A2 (fr) Procédé de fabrication d'une cellule solaire et cellule solaire ainsi fabriquée
EP4203078A1 (fr) Structure de cellule solaire à émetteur arrière à hétérojonction
EP3044813A1 (fr) Procédé de production d'une cellule solaire impliquant un dopage par implantation ionique et la séparation d'une barrière de diffusion vers l'extérieur
EP2347448B1 (fr) Procédé pour produire une cellule solaire à hétérojonction sur plaquette à mise en contact sur la face arrière et cellule solaire à hétérojonction produite selon ce procédé
DE102014103303A1 (de) Verfahren zum Herstellen von Solarzellen mit simultan rückgeätzten dotierten Bereichen
DE102014205350B4 (de) Photoaktives Halbleiterbauelement sowie Verfahren zum Herstellen eines photoaktiven Halbleiterbauelementes
DE102015107842B3 (de) Verfahren zum Herstellen einer Solarzelle mit oxidierten Zwischenbereichen zwischen Poly-Silizium-Kontakten
DE102011115581A1 (de) Solarzelle und Verfahren zur Herstellung derselben
EP3050118A1 (fr) Procédé de fabrication d'une cellule solaire
DE102013219565A1 (de) Photovoltaische Solarzelle und Verfahren zum Herstellen einer photovoltaischen Solarzelle
DE102010060303A1 (de) Verfahren zum Herstellen einer Solarzelle
WO2009121344A2 (fr) Procédé de fabrication d'une cellule solaire à dopage biétagé
DE102013106272B4 (de) Wafersolarzelle und Solarzellenherstellungsverfahren
WO2024104976A1 (fr) Cellule solaire ayant une structure de contact avant qui comprend une couche de carbure de silicium, et procédé de fabrication de ladite cellule solaire
DE102010016992B4 (de) Herstellungsverfahren einer Halbleitervorrichtung

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16722907

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16722907

Country of ref document: EP

Kind code of ref document: A2