WO2016155614A1 - 一种效率提高的共源共栅射频功率放大器 - Google Patents

一种效率提高的共源共栅射频功率放大器 Download PDF

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WO2016155614A1
WO2016155614A1 PCT/CN2016/077789 CN2016077789W WO2016155614A1 WO 2016155614 A1 WO2016155614 A1 WO 2016155614A1 CN 2016077789 W CN2016077789 W CN 2016077789W WO 2016155614 A1 WO2016155614 A1 WO 2016155614A1
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transistor
bias circuit
output
resistor
power amplifier
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PCT/CN2016/077789
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English (en)
French (fr)
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陈高鹏
陈俊
刘磊
张辉
黄清华
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宜确半导体（苏州）有限公司
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Publication of WO2016155614A1 publication Critical patent/WO2016155614A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation

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  • the invention belongs to the technical field of radio frequency integrated circuits, and particularly relates to a cascode radio frequency power amplifier with improved efficiency.
  • the RF power amplifier is an indispensable key component in various wireless communication applications for power amplifying the modulated RF signal output by the transceiver to meet the power requirements of the RF signal required for wireless communication.
  • RF power amplifiers are large-signal devices, and therefore semiconductor devices for manufacturing RF power amplifiers are required to have high breakdown voltage, high current density, and the like.
  • semiconductor devices for manufacturing RF power amplifiers are required to have high breakdown voltage, high current density, and the like.
  • small-signal circuits such as digital circuits and analog circuits, Si-based CMOS processes, GaAs-based HBT, pHEMT, etc., due to their high breakdown voltage and carrier mobility, in the field of RF power amplifiers It has been widely used.
  • a typical RF power amplifier circuit, transistor 103 as an important active device in the RF power amplifier, is usually fabricated in Si or GaAs process in practice; RF power amplifier input signal port RFin through the input matching network 101 is coupled to the gate of transistor 103; the gate of transistor 103 is also coupled to bias voltage port Vbias of the RF power amplifier via bias circuit 102; the source of transistor 103 is coupled to ground; the drain of transistor 103 is passed through a choke inductor 104 is coupled to the supply voltage port Vcc of the RF power amplifier; the supply voltage port Vcc is also coupled to one end of the decoupling capacitor 105, the other end of the decoupling capacitor 105 is coupled to ground; the drain of the transistor 103 is also coupled through the output matching network 106 The output signal port RFout of the RF power amplifier.
  • the input signal voltage swing of the RF power amplifier is low, and after the power amplification of the transistor 103, the voltage swing of the output signal is greatly increased.
  • the voltage swing across the transistor's drain can typically reach 2 ⁇ Vcc.
  • the voltage swing on the drain of the transistor will reach 10V.
  • the RF power amplifier is operating in the Class-E state, the voltage swing across the drain of the transistor will be higher, above 3.5 ⁇ Vcc. It can be seen that the transistor in the RF power amplifier will withstand a swing much higher than the supply voltage, and breakdown of the transistor. Voltage and reliability put forward high requirements. The use of semiconductor processes with sufficiently high breakdown voltages to fabricate RF power amplifiers will severely limit the choice, losing design flexibility and reducing integration.
  • the industry typically increases the breakdown voltage of devices by designing the RF power amplifier circuit as a cascode structure. As shown in Figure 2, it is a typical cascode RF power amplifier.
  • the transistor 203 and the transistor 204 are active devices for realizing power amplification in the radio frequency power amplifier, and are usually fabricated by a Si or GaAs process in practice; the input signal port RFin of the radio frequency power amplifier is connected to the gate of the transistor 203 through the input matching network 201;
  • the gate of transistor 203 is also coupled to bias voltage port Vbias1 of the RF power amplifier via bias circuit 202; the source of transistor 203 is coupled to ground; the drain of transistor 203 is coupled to the source of transistor 204; the gate of transistor 204 Connected to the bias voltage port Vbias2 of the RF power amplifier via bias circuit 205; the gate of transistor 204 is also coupled to one end of decoupling capacitor 206, the other end of decoupling capacitor 206 is coupled to
  • transistor 203 is a common source stage and transistor 204 is a common gate; such a cascode structure has a higher power gain and a higher inverse than a single transistor common source structure. To the isolation; more importantly, the cascode structure has a higher breakdown voltage than the single transistor common source structure, allowing the RF power amplifier to have a higher operating voltage.
  • the cascode RF power amplifier operating in the Class-A/AB/B state has a RF voltage swing of 2 ⁇ Vcc at the drain of the transistor 204 and a RF voltage swing at the drain of the transistor 203. Not more than Vcc. Therefore, the voltage swing between the drain and the source of the transistor 203 and the transistor 204 does not exceed 2 ⁇ Vcc, which ensures that the transistor operates in a safe region.
  • RF power amplifiers for modern wireless communications are generally classified into saturated power amplifiers and linear power amplifiers.
  • the saturated power amplifier generally works in the saturated power output state, and its output power is mainly determined by the power supply voltage of the power device; when the power supply voltage is high, the output RF power is high, and when the power supply voltage is low, the output RF power is low. Therefore, the work of the saturated power amplifier Rate control is usually done by controlling the supply voltage.
  • Linear power amplifiers usually use different power control methods than saturated power amplifiers. In the normal operating range, linear power amplifiers usually maintain a constant power gain, and the output power is determined by the input power.
  • linear power amplifiers operate at lower power levels with a sharp decrease in efficiency; in battery powered handheld wireless communication devices, the inefficient operation of linear power amplifiers can severely impact the device's uptime. Therefore, it is extremely important to improve the efficiency of linear power amplifiers, especially the efficiency of linear power amplifiers at lower power levels.
  • the object of the present invention is to provide an improved efficiency cascode RF power amplifier, which can dynamically adjust the output bias voltage of the bias circuit, thereby dynamically adjusting the working state of the entire RF power amplifier, whether at a low power level or at a high power.
  • Grades, RF power amplifiers have good linearity specifications.
  • An efficacious cascode RF power amplifier comprising at least one cascode transistor pair consisting of a first RF transistor and a second RF transistor; the first RF transistor and the second RF transistor being GaAs E/ D pHEMT transistor, the gate of the first RF transistor is connected to the input signal terminal through an input matching network, the source is connected to the ground, the drain is connected to the source of the second RF transistor; the drain of the second RF transistor is connected through the choke inductor connection At the voltage end, the drain of the second RF transistor is also connected to the output signal terminal through the output matching network; one end of the first decoupling capacitor is connected to the supply voltage terminal, and the other end is grounded; the gate of the first RF transistor is also connected to the first bias a circuit, the gate of the second RF transistor is further connected to the second bias circuit, and is connected to the second decoupling capacitor, and the other end of the second decoupling capacitor is grounded; the first bias circuit and the second bias circuit are respectively connected a power control unit having at least one input
  • cascode transistor pairs form a parallel structure.
  • the input control signal end is connected to the system controller or is connected to the output end of the RF power amplifier output detection processing circuit.
  • the first bias circuit and the second bias circuit comprise a third transistor, a fourth transistor, and a fifth transistor; a source of the third transistor is grounded, and a gate is connected through a first resistor a source of the fifth transistor, a source of the fifth transistor is further connected to a grounded second resistor; a drain of the third transistor is connected to the third resistor, the first capacitor and the gate of the fourth transistor, and the other end of the third resistor Connecting the fourth resistor and the gate of the fifth transistor, the other end of the fourth resistor is connected to the input control signal end, the other end of the first capacitor is grounded; the drains of the fourth transistor and the fifth transistor are connected to the supply voltage terminal, and the fourth transistor is The source is connected to a grounded fifth resistor and a sixth resistor, and the other end of the sixth resistor is connected to the output end.
  • the cascode transistor pair is two, including a first cascode transistor pair composed of a first RF transistor and a second RF transistor, and a third RF transistor and a fourth RF transistor.
  • a second cascode transistor pair; the first RF transistor, the second RF transistor, the third RF transistor, and the fourth RF transistor are GaAs E/D pHEMT transistors, the source of the first RF transistor is grounded, and the gate is connected One end of the first DC blocking capacitor and the output end of the first bias circuit, the other end of the first DC blocking capacitor is connected to the input signal terminal through an input matching network, and the drain of the first RF transistor is connected to the source of the second RF transistor,
  • the gate of the second RF transistor is connected to one end of the first decoupling capacitor and the output end of the second bias circuit, the other end of the first decoupling capacitor is grounded, and the drain of the second RF transistor is connected to the drain of the fourth RF transistor and One end of the choke inductor is connected to the output signal end through
  • the input control signal end is connected to the system controller or is connected to the output end of the RF power amplifier output detection processing circuit.
  • the first bias circuit, the second bias circuit, the third bias circuit, and the fourth bias circuit comprise a third transistor, a fourth transistor, and a fifth transistor; a source of the third transistor The pole is grounded, the gate is connected to the source of the fifth transistor through the first resistor, the source of the fifth transistor is further connected to a grounded second resistor; the drain of the third transistor is connected to the third resistor, the first capacitor and the fourth transistor The other end of the third resistor is connected to the gates of the fourth resistor and the fifth transistor, and the other end of the fourth resistor is connected to the input control signal terminal, the other end of the first capacitor is grounded; the drain of the fourth transistor and the fifth transistor The pole is connected to the supply voltage terminal, the source of the fourth transistor is connected to a grounded fifth resistor and a sixth resistor, and the other end of the sixth resistor is connected to the output terminal.
  • the output bias voltage of the bias circuit can be dynamically adjusted to dynamically adjust the operating state of the entire RF power amplifier.
  • the RF power amplifier can have a good linearity index regardless of the low power level or the high power level.
  • the RF transistor uses the GaAs E/D pHEMT process, and the performance of the RF power amplifier is higher.
  • the Ctrl signal By properly arranging the device size of the two cascode transistor pairs and properly controlling the operating state of the cascode transistor pair (including on, off, high bias voltage, low bias voltage, etc.) by the Ctrl signal, It can optimize the performance and linearity of RF power amplifiers at different output power levels.
  • 1 is a circuit diagram of a typical RF power amplifier
  • FIG. 2 is a circuit diagram of a conventional RF power amplifier of a common cascode structure
  • FIG. 3 is a circuit diagram of a radio frequency power amplifier of a cascode structure of the present invention.
  • FIG. 4 is a circuit diagram of a bias circuit of a radio frequency power amplifier of a cascode structure according to the present invention.
  • FIG. 5 is a circuit diagram of a radio frequency power amplifier of two cascode structures according to the present invention.
  • the transistor is based on a gallium arsenide-enhanced/depleted-type high-electron mobility field-effect transistor process, namely GaAs E/D pHEMT.
  • the enhanced pHEMT transistor 303 and the depletion mode pHEMT transistor 304 form a basic cascode structure: the gate of the transistor 303 is connected to the input signal port RFin through the input matching network 301, the source of the transistor 303. Connected to ground, the drain of transistor 303 is coupled to the source of transistor 304, the drain of transistor 304 is coupled to the supply voltage port Vcc of the RF power amplifier via choke inductor 308, and the drain of transistor 304 is also coupled through output matching network 310. To the output signal port RFout of the RF power amplifier.
  • the supply voltage port Vcc of the RF power amplifier is connected to one end of the decoupling capacitor 309, and the other end of the decoupling capacitor 309 is connected to the ground.
  • the gate of transistor 303 is also coupled to the output of bias circuit 302; the gate of transistor 304 is also coupled to the output of bias circuit 305 and to one end of decoupling capacitor 307, the other end of decoupling capacitor 307 being coupled arrived.
  • the input terminal Vbias1 of the bias circuit 302, the input terminal Vbias2 of the bias circuit 305 are connected to the two output terminals of the power control circuit 306, respectively; the power control circuit 306 has at least one input control signal port Ctrl.
  • the output bias voltages of the bias circuit 302 and the bias circuit 305 can be dynamically adjusted to dynamically adjust the bias states of the transistors 303 and 304, thereby dynamically adjusting the operation of the entire RF power amplifier.
  • the purpose of the state is to dynamically adjust the bias states of the transistors 303 and 304, thereby dynamically adjusting the operation of the entire RF power amplifier.
  • At least one input control signal Ctrl of the power control circuit 306 may be from a system controller (such as a central processing unit in a wireless communication device, a radio frequency transceiver, etc.), or may be outputted from an RF power amplifier output. Processing the output signal of the circuit.
  • the RF power amplifier proposed in the present scheme is a linear power amplifier. In order to optimize the linearity of the RF power amplifier, at a low output power level, the Ctrl signal can control the bias circuit 302 and the bias circuit 305 such that the transistor 303 and the transistor 304 have a comparison.
  • the Ctrl signal can control bias circuit 302 and bias circuit 305 such that transistor 303 and transistor 304 have a lower bias voltage; thus, whether at low power levels or high Power grade, RF power amplifier can have a good linearity index.
  • FIG. 4 shows a circuit of an embodiment of the bias circuit proposed by the present invention.
  • the enhanced GaAs pHEMT transistors 411, 417, 420 are the main active devices in the bias circuit.
  • the source of the transistor 411 is connected to the ground, the gate of the transistor 411 is connected to one end of the resistor 412, and the other end of the resistor 412 is connected to one end of the resistor 413 and the source of the transistor 420, and the other end of the resistor 413 is connected.
  • the drain of the transistor 411 is connected to one end of the resistor 418, one end of the capacitor 414, and the gate of the transistor 417.
  • the other end of the resistor 418 is connected to one end of the resistor 419 and the gate of the transistor 420, and one end of the resistor 419 is connected.
  • the other end of the capacitor 414 is connected to ground;
  • the drain of the transistor 420 is connected to the supply voltage VBias of the bias circuit;
  • the drain of the transistor 417 is connected to the supply voltage VBias of the bias circuit, the transistor 417
  • the source is connected to one end of the resistor 415 and one end of the resistor 416, the other end of the resistor 415 is connected to ground, and the other end of the resistor 416 is connected to the output terminal Vg of the bias circuit.
  • the output terminal Vg of the bias circuit is connected to the gate of the amplifying transistor in the radio frequency power amplifier to provide a bias voltage for the amplifying transistor.
  • the magnitude of the output voltage Vg can be adjusted by the magnitude of the control voltage Ctrl of the bias circuit, and the function of dynamically adjusting the bias circuit can be realized.
  • FIG. 5 shows a multi-biased RF power amplifier based on the GaAs E/D pHEMT process proposed by the present invention.
  • the enhanced pHEMT transistor 509 and the depletion pHEMT transistor 510 form a pair of cascode structures
  • the enhanced pHEMT transistor 511 and the depletion pHEMT transistor 512 form another pair of cascode structures, two pairs of common sources.
  • the gate structure is a parallel structure on the circuit, which together constitute a power amplification core circuit of the RF power amplifier.
  • the source of the transistor 509 is connected to the ground, the gate of the transistor 509 is connected to one end of the DC blocking capacitor 503 and the output of the bias circuit 506, and the other end of the DC blocking capacitor 503 is connected to the input of the RF power amplifier through the input matching network 501.
  • a drain of the transistor 509 is connected to the source of the transistor 510; a gate of the transistor 510 is connected to one end of the decoupling capacitor 513 and an output terminal of the bias circuit 508, and the other end of the decoupling capacitor 513 is connected to the ground;
  • the drain of transistor 510 is coupled to the drain of transistor 512 and one end of choke inductor 515 and is coupled to the output signal port RFout of the RF power amplifier via output matching network 517; the other end of choke inductor 515 is coupled to the RF power amplifier.
  • One end of the supply voltage Vcc and the decoupling capacitor 516, the other end of the decoupling capacitor 516 is connected to the ground;
  • the source of the transistor 511 is connected to the ground, and the gate of the transistor 511 is connected to one end of the DC blocking capacitor 502 and the bias circuit 505
  • the other end of the DC blocking capacitor 502 is connected to the input signal port RFin of the RF power amplifier through the input matching network 501;
  • the transistor 511 The drain is coupled to the source of transistor 512;
  • the gate of transistor 512 is coupled to one end of decoupling capacitor 514 and the output of bias circuit 507, the other end of decoupling capacitor 514 is coupled to ground;
  • the drain of transistor 512 is coupled to a drain of the transistor 510 and one end of the choke inductor 515, and
  • the output signal port RFout is connected to the RF power amplifier through an output matching network 517.
  • the input terminal Vbias 1 of the bias circuit 505, the input terminal Vbias2 of the bias circuit 506, the input terminal Vbias3 of the bias circuit 507, and the input terminal Vbias4 of the bias circuit 508 are respectively connected to the four output terminals of the power control circuit 504;
  • Power control circuit 504 has at least one input control signal port Ctrl. Under the control of the input control signal Ctrl, the output bias voltages of the bias circuit 505, the bias circuit 506, the bias circuit 507, and the bias circuit 508 can be dynamically adjusted to dynamically adjust the transistor 509 and the transistor 510 and the transistor 511 and The bias state of the transistor 512, thereby achieving the purpose of dynamically adjusting the operating state of the entire RF power amplifier.
  • At least one input control signal Ctrl of the power control circuit 504 may be from a system controller (such as a central processing unit in a wireless communication device, a radio frequency transceiver, etc.), or may be derived from an output signal of the RF power amplifier output detection processing circuit. .
  • the RF power amplifier proposed in this solution is a linear power amplifier. In order to optimize the linearity of the RF power amplifier, the Ctrl signal can control the bias circuit 505, the bias circuit 506, the bias circuit 507, and the bias at a low output power level.
  • Circuitry 508 causes transistor 509 and transistor 510 and transistor 511 and transistor 512 to have a higher bias voltage; at high output power levels, the Ctrl signal can control bias circuit 505, bias circuit 506, bias circuit 507, bias Circuitry 508 causes transistor 509 and transistor 510 and transistor 511 and transistor 512 to have a lower bias voltage; thus, the RF power amplifier can have a better linearity specification, both at low power levels and at high power levels.
  • the bias circuit 506 and the bias circuit 508, or the bias circuit 505 and the bias circuit 508 can be turned off by the Ctrl signal control so that the two pairs of cascode transistor structures are only A pair remains in working condition.
  • the corresponding bias circuit is controlled by the Ctrl signal to turn off the transistor 511 and the transistor 512; the benefits are obvious, and the static power consumption of the RF power amplifier is reduced, which can be improved. The efficiency of the RF power amplifier at lower output power levels.
  • the present invention takes the parallel connection of two pairs of cascode transistor pairs as an embodiment, but according to the idea of the present invention, a practically more number of cascode transistor pairs can be formed into a parallel structure, and these The bias voltages of the source cascode transistor pairs are separately controlled to achieve higher performance of the RF power amplifier.

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Abstract

本发明公开了一种效率提高的共源共栅射频功率放大器，包括至少一个由第一射频晶体管和第二射频晶体管组成的共源共栅晶体管对，射频晶体管连接的第一偏置电路和第二偏置电路分别连接功率控制单元，所述功率控制单元具有至少一个用于调整第一偏置电路和第二偏置电路的输出偏置电压的输入控制信号端。通过输入控制信号端Ctrl信号合理地控制共源共栅晶体管对的工作状态(包括打开、关闭、高偏置电压、低偏置电压等)，可以优化射频功率放大器在不同输出功率等级下的效率及线性度等性能指标。

Description

一种效率提高的共源共栅射频功率放大器 技术领域
本发明属于射频集成电路技术领域，具体涉及一种效率提高的共源共栅射频功率放大器。
背景技术
射频功率放大器是各种无线通信应用中必不可少的关键部件，用于将收发信机输出的已调制射频信号进行功率放大，以满足无线通信所需的射频信号的功率要求。射频功率放大器属于大信号器件，因此要求用于制造射频功率放大器的半导体器件具有高击穿电压、高电流密度等特性。相对于数字电路、模拟电路等小信号电路所普遍采用的基于Si CMOS工艺，基于GaAs材料的HBT、pHEMT等工艺，由于其较高的击穿电压和载流子迁移速率，在射频功率放大器领域中得到了广泛的应用。
如图1所示为一个典型的射频功率放大器电路，晶体管103作为射频功率放大器中的重要有源器件，在实际中通常采用Si或GaAs工艺制造；射频功率放大器的输入信号端口RFin通过输入匹配网络101连接到晶体管103的栅极；晶体管103的栅极还通过偏置电路102连接到射频功率放大器的偏置电压端口Vbias；晶体管103的源极连接到地；晶体管103的漏极通过扼流电感104连接到射频功率放大器的供电电压端口Vcc；供电电压端口Vcc还连接到去耦电容105的一端，去耦电容105的另外一端连接到地；晶体管103的漏极还通过输出匹配网络106连接到射频功率放大器的输出信号端口RFout。射频功率放大器的输入信号电压摆幅较低，经过晶体管103功率放大之后，输出信号的电压摆幅大幅提升。对于一个典型的Class-A/B/AB射频功率放大器，在供电电压Vcc下工作，晶体管漏极上的电压摆幅通常可以达到2×Vcc。譬如，当射频功率放大器的供电电压Vcc为5V时，晶体管漏极上的电压摆幅将达到10V。如果射频功率放大器工作于Class-E状态，那么晶体管漏极上的电压摆幅将会更高，达到3.5×Vcc以上。由此可见，射频功率放大器中的晶体管上将承受远高于供电电压的摆幅，对晶体管的击穿 电压及可靠性提出了很高的要求。选用足够高击穿电压的半导体工艺来制造射频功率放大器，将使得选择余地严重受限，丧失了设计灵活性并将降低集成度。
为了使得较小击穿电压半导体工艺也可以用于制造射频功率放大器，业界通常通过将射频功率放大器电路设计为共源共栅结构来提高器件的击穿电压。如图2所示，为一个典型的共源共栅结构的射频功率放大器。晶体管203和晶体管204为射频功率放大器中实现功率放大的有源器件，在实际中通常采用Si或GaAs工艺制造；射频功率放大器的输入信号端口RFin通过输入匹配网络201连接到晶体管203的栅极；晶体管203的栅极还通过偏置电路202连接到射频功率放大器的偏置电压端口Vbias1；晶体管203的源极连接到地；晶体管203的漏极连接到晶体管204的源极；晶体管204的栅极通过偏置电路205连接到射频功率放大器的偏置电压端口Vbias2；晶体管204的栅极还连接到去耦电容206的一端，去耦电容206的另外一端连接到地；晶体管204的漏极通过扼流电感207连接到射频功率放大器的供电电压端口Vcc；供电电压端口Vcc还连接到去耦电容208的一端，去耦电容208的另外一端连接到地；晶体管207的漏极还通过输出匹配网络209连接到射频功率放大器的输出信号端口RFout。射频功率放大器的输入信号电压摆幅较低，经过晶体管203及晶体管204功率放大之后，输出信号的电压摆幅大幅提升。在共源共栅结构射频功率放大器中，晶体管203为共源级，晶体管204为共栅极；这样的共源共栅结构相比单晶体管共源结构具有更高的功率增益和更高的反向隔离度；更为重要的是，共源共栅结构比单晶体管共源结构具有更高的击穿电压，允许射频功率放大器有更高的工作电压。
如图2所示，工作于Class-A/AB/B状态的共源共栅结构射频功率放大器，晶体管204漏极的射频电压摆幅为2×Vcc，晶体管203漏极的射频电压摆幅则不超过Vcc。因此，晶体管203及晶体管204各自漏极与源极之间的电压摆幅都不超过2×Vcc，保证了晶体管工作于安全区域。
用于现代无线通信的射频功率放大器，通常可以分为饱和功率放大器和线性功率放大器。饱和功率放大器一般工作在饱和功率输出状态，其输出功率主要由功率器件的供电电压大小决定；当供电电压较高时，输出射频功率较高，当供电电压较低时，输出射频功率较低。因此，饱和功率放大器的功 率控制通常通过控制供电电压高低来完成。线性功率放大器通常采用与饱和功率放大器不同的功率控制方式，在正常工作范围内线性功率放大器通常保持功率增益恒定，其输出功率高低由输入功率高低决定。本领域专业人员众所周知的，线性功率放大器在较低功率等级工作时，效率将急剧降低；在依靠电池供电的手持无线通信设备中，线性功率放大器的低效率工作将严重影响设备的正常工作时间。因此，提高线性功率放大器的效率，尤其是提高较低功率等级时线性功率放大器的效率，极为重要。
发明内容
本发明目的是：提供一种效率提高的共源共栅射频功率放大器，可以动态调整偏置电路的输出偏置电压，进而动态调整整个射频功率放大器工作状态，无论在低功率等级还是在高功率等级，射频功率放大器都能具有较好的线性度指标。
本发明的技术方案是：
一种效率提高的共源共栅射频功率放大器，包括至少一个由第一射频晶体管和第二射频晶体管组成的共源共栅晶体管对；所述第一射频晶体管和第二射频晶体管为GaAs E/D pHEMT晶体管，第一射频晶体管的栅极通过输入匹配网络连接输入信号端，源极连接到地，漏极连接第二射频晶体管的源极；第二射频晶体管的漏极通过扼流电感连接供电电压端，第二射频晶体管的漏极还通过输出匹配网络连接输出信号端；第一去耦电容的一端与供电电压端连接，另一端接地；第一射频晶体管的栅极还连接第一偏置电路，第二射频晶体管的栅极还连接第二偏置电路，并连接第二去耦电容，第二去耦电容的另一端接地；所述第一偏置电路和第二偏置电路分别连接功率控制单元，所述功率控制单元具有至少一个用于调整第一偏置电路和第二偏置电路的输出偏置电压的输入控制信号端。
进一步的，所述共源共栅晶体管对组成并联结构。
进一步的，所述输入控制信号端连接***控制器或者连接射频功率放大器输出检测处理电路的输出端。
进一步的，所述第一偏置电路和第二偏置电路包括第三晶体管、第四晶体管、和第五晶体管；所述第三晶体管的源极接地，栅极通过第一电阻连接 第五晶体管的源极，第五晶体管的源极还连接一接地的第二电阻；第三晶体管的漏极连接第三电阻、第一电容和第四晶体管的栅极，第三电阻的另一端连接第四电阻和第五晶体管的栅极，第四电阻另一端连接输入控制信号端，第一电容的另一端接地；第四晶体管和第五晶体管的漏极连接供电电压端，第四晶体管的源极连接一接地的第五电阻和第六电阻，第六电阻的另一端连接输出端。
进一步的，所述共源共栅晶体管对为2个，包括由第一射频晶体管和第二射频晶体管组成的第一共源共栅晶体管对，以及由第三射频晶体管和第四射频晶体管组成的第二共源共栅晶体管对；所述第一射频晶体管、第二射频晶体管、第三射频晶体管和第四射频晶体管为GaAs E/D pHEMT晶体管，第一射频晶体管的源极接地，栅极连接第一隔直电容的一端及第一偏置电路的输出端，第一隔直电容的另一端通过输入匹配网络连接输入信号端，第一射频晶体管的漏极连接第二射频晶体管的源极，第二射频晶体管的栅极连接第一去耦电容的一端及第二偏置电路输出端，第一去耦电容的另一端接地，第二射频晶体管的漏极连接第四射频晶体管的漏极及扼流电感的一端，并通过输出匹配网络连接输出信号端，扼流电感的另一端连接供电电压端及第三去耦电容的一端，第三去耦电容的另一端接地，第三射频晶体管的源极接地，第三射频晶体管的栅极连接第二隔直电容的一端及第三偏置电路的输出端，第二隔直电容的另一端通过输入匹配网络连接输入信号端，第三射频晶体管的漏极连接第四射频晶体管的源极；第四射频晶体管的栅极连接第二去耦电容的一端及第四偏置电路的输出端，第二去耦电容的另一端接地，第四射频晶体管的漏极连接第二射频晶体管的漏极及扼流电感的一端，并通过输出匹配网络连接到输出信号端，第一偏置电路、第二偏置电路、第三偏置电路和第四偏置电路的输入端，分别连接功率控制单元的四个输出端，所述功率控制单元具有至少一个用于调整第一偏置电路、第二偏置电路、第三偏置电路和第四偏置电路的输出偏置电压的输入控制信号端。
进一步的，所述输入控制信号端连接***控制器或者连接射频功率放大器输出检测处理电路的输出端。
进一步的，所述第一偏置电路、第二偏置电路、第三偏置电路和第四偏置电路包括第三晶体管、第四晶体管、和第五晶体管；所述第三晶体管的源 极接地，栅极通过第一电阻连接第五晶体管的源极，第五晶体管的源极还连接一接地的第二电阻；第三晶体管的漏极连接第三电阻、第一电容和第四晶体管的栅极，第三电阻的另一端连接第四电阻和第五晶体管的栅极，第四电阻另一端连接输入控制信号端，第一电容的另一端接地；第四晶体管和第五晶体管的漏极连接供电电压端，第四晶体管的源极连接一接地的第五电阻和第六电阻，第六电阻的另一端连接输出端。
本发明的优点是：
1.可以动态调整偏置电路的输出偏置电压，进而动态调整整个射频功率放大器工作状态，无论在低功率等级还是在高功率等级，射频功率放大器都能具有较好的线性度指标。
2.射频晶体管采用GaAs E/D pHEMT工艺，射频功率放大器的性能更高。通过合理配置两个共源共栅晶体管对的器件尺寸大小，及通过Ctrl信号合理地控制共源共栅晶体管对的工作状态(包括打开、关闭、高偏置电压、低偏置电压等)，可以优化射频功率放大器在不同输出功率等级下的效率及线性度等性能指标。
附图说明
下面结合附图及实施例对本发明作进一步描述：
图1为现有典型的射频功率放大器电路图；
图2为现有典型的共源共栅结构的射频功率放大器电路图；
图3为本发明一个共源共栅结构的射频功率放大器电路图；
图4为本发明共源共栅结构的射频功率放大器的偏置电路的电路图；
图5为本发明二个共源共栅结构的射频功率放大器电路图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明了，下面结合具体实施方式并参照附图，对本发明进一步详细说明。应该理解，这些描述只是示例性的，而并非要限制本发明的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本发明的概念。
实施例1：
晶体管采用基于砷化镓增强型/耗尽型赝配高电子迁移率场效应晶体管工艺，即GaAs E/D pHEMT。
如图3所示，增强型pHEMT晶体管303与耗尽型pHEMT晶体管304组成了基本的共源共栅结构：晶体管303的栅极通过输入匹配网络301连接到输入信号端口RFin，晶体管303的源极连接到地，晶体管303的漏极连接到晶体管304的源极，晶体管304的漏极通过扼流电感308连接到射频功率放大器的供电电压端口Vcc，晶体管304的漏极还通过输出匹配网络310连接到射频功率放大器的输出信号端口RFout。射频功率放大器的供电电压端口Vcc连接到去耦电容309的一端，去耦电容309的另外一端连接到地。晶体管303的栅极还连接到偏置电路302的输出端；晶体管304的栅极还连接到偏置电路305的输出端，并连接到去耦电容307的一端，去耦电容307的另外一端连接到地。偏置电路302的输入端Vbias1、偏置电路305的输入端Vbias2分别连接到功率控制电路306的两个输出端；功率控制电路306具有至少一个输入控制信号端口Ctrl。在输入控制信号Ctrl的控制下，偏置电路302和偏置电路305的输出偏置电压可以被动态调整，从而动态调整晶体管303和晶体管304的偏置状态，进而达到动态调整整个射频功率放大器工作状态的目的。
需要说明的是，功率控制电路306的至少一个输入控制信号Ctrl，既可以来自于***控制器(如无线通信设备中的中央处理器、射频收发器等)，也可以来自于射频功率放大器输出检测处理电路的输出信号。本方案所提出的射频功率放大器为线性功率放大器，为了优化射频功率放大器的线性度，在低输出功率等级时，Ctrl信号可以控制偏置电路302和偏置电路305使得晶体管303和晶体管304具有较高的偏置电压；在高输出功率等级时，Ctrl信号可以控制偏置电路302和偏置电路305使得晶体管303和晶体管304具有较低的偏置电压；从而，无论在低功率等级还是在高功率等级，射频功率放大器都能具有较好的线性度指标。
如图4所示为本发明提出的偏置电路的一个实施例电路。增强型GaAs pHEMT晶体管411、417、420是偏置电路中的主要有源器件。晶体管411的源极连接到地，晶体管411的栅极连接到电阻412的一端，电阻412的另外一端连接到电阻413的一端和晶体管420的源极，电阻413的另外一端连 接到地；晶体管411的漏极连接到电阻418的一端、电容414的一端及晶体管417的栅极，电阻418的另外一端连接到电阻419的一端及晶体管420的栅极，电阻419的一端连接到偏置电路的控制电压Ctrl，电容414的另外一端连接到地；晶体管420的漏极连接到偏置电路的供电电压VBias；晶体管417的漏极连接到偏置电路的供电电压VBias，晶体管417的源极连接到电阻415的一端和电阻416的一端，电阻415的另外一端连接到地，电阻416的另外一端连接到偏置电路的输出端Vg。这里，偏置电路的输出端Vg连接到射频功率放大器中放大晶体管的栅极，为放大晶体管提供偏置电压。本实施例的偏置电路，其输出电压Vg的大小，可以通过偏置电路的控制电压Ctrl的大小来调整，可以实现前述可动态调整偏置电路的功能。
实施例2：
如图5所示为本发明所提出的基于GaAs E/D pHEMT工艺的多偏置射频功率放大器。增强型pHEMT晶体管509与耗尽型pHEMT晶体管510组成了一对共源共栅结构，增强型pHEMT晶体管511与耗尽型pHEMT晶体管512组成了另一对共源共栅结构，两对共源共栅结构在电路上为并联结构，共同组成射频功率放大器的功率放大核心电路。
晶体管509的源极连接到地，晶体管509的栅极连接到隔直电容503的一端及偏置电路506的输出端，隔直电容503的另外一端通过输入匹配网络501连接到射频功率放大器的输入信号端口RFin；晶体管509的漏极连接到晶体管510的源极；晶体管510的栅极连接到去耦电容513的一端及偏置电路508的输出端，去耦电容513的另外一端连接到地；晶体管510的漏极连接到晶体管512的漏极及扼流电感515的一端，并通过输出匹配网络517连接到射频功率放大器的输出信号端口RFout；扼流电感515的另外一端连接到射频功率放大器的供电电压Vcc及去耦电容516的一端，去耦电容516的另外一端连接到地；晶体管511的源极连接到地，晶体管511的栅极连接到隔直电容502的一端及偏置电路505的输出端，隔直电容502的另外一端通过输入匹配网络501连接到射频功率放大器的输入信号端口RFin；晶体管511的漏极连接到晶体管512的源极；晶体管512的栅极连接到去耦电容514的一端及偏置电路507的输出端，去耦电容514的另外一端连接到地；晶体管512的漏极连接到晶体管510的漏极及扼流电感515的一端，并 通过输出匹配网络517连接到射频功率放大器的输出信号端口RFout。偏置电路505的输入端Vbias 1、偏置电路506的输入端Vbias2、偏置电路507的输入端Vbias3、偏置电路508的输入端Vbias4，分别连接到功率控制电路504的四个输出端；功率控制电路504具有至少一个输入控制信号端口Ctrl。在输入控制信号Ctrl的控制下，偏置电路505、偏置电路506、偏置电路507、偏置电路508的输出偏置电压可以被动态调整，从而动态调整晶体管509和晶体管510及晶体管511和晶体管512的偏置状态，进而达到动态调整整个射频功率放大器工作状态的目的。
功率控制电路504的至少一个输入控制信号Ctrl，既可以来自于***控制器(如无线通信设备中的中央处理器、射频收发器等)，也可以来自于射频功率放大器输出检测处理电路的输出信号。本方案所提出的射频功率放大器为线性功率放大器，为了优化射频功率放大器的线性度，在低输出功率等级时，Ctrl信号可以控制偏置电路505、偏置电路506、偏置电路507、偏置电路508使得晶体管509和晶体管510及晶体管511和晶体管512具有较高的偏置电压；在高输出功率等级时，Ctrl信号可以控制偏置电路505、偏置电路506、偏置电路507、偏置电路508使得晶体管509和晶体管510及晶体管511和晶体管512具有较低的偏置电压；从而，无论在低功率等级还是在高功率等级，射频功率放大器都能具有较好的线性度指标。
特别地，在某些应用场合下，可以通过Ctrl信号控制使得偏置电路506和偏置电路508，或者偏置电路505和偏置电路508关闭，从而使得两对共源共栅晶体管结构只有其中一对保持在工作状态。譬如，在较低输出功率等级时，通过Ctrl信号控制相应的偏置电路使晶体管511和晶体管512处于关闭状态；这样带来的好处是显而易见的，降低了射频功率放大器的静态功耗，可以提高射频功率放大器在较低输出功率等级时的工作效率。
特别地，通过合理配置两个共源共栅晶体管对的器件尺寸大小，及通过Ctrl信号合理地控制两个共源共栅晶体管对的工作状态(包括打开、关闭、高偏置电压、低偏置电压等)，可以优化射频功率放大器在不同输出功率等级下的效率及线性度等性能指标。
本发明以两对共源共栅晶体管对的并联作为实施例，但根据本发明的思想，实际上可以有更多数目的共源共栅晶体管对组成并联结构，并对这些共 源共栅晶体管对的偏置电压进行分别控制，以达到射频功率放大器的更高性能。
应当理解的是，本发明的上述具体实施方式仅仅用于示例性说明或解释本发明的原理，而不构成对本发明的限制。因此，在不偏离本发明的精神和范围的情况下所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。此外，本发明所附权利要求旨在涵盖落入所附权利要求范围和边界、或者这种范围和边界的等同形式内的全部变化和修改例。

Claims (7)

  1. 一种效率提高的共源共栅射频功率放大器，其特征在于，包括至少一个由第一射频晶体管和第二射频晶体管组成的共源共栅晶体管对；所述第一射频晶体管和第二射频晶体管为GaAs E/D pHEMT晶体管，第一射频晶体管的栅极通过输入匹配网络连接输入信号端，源极连接到地，漏极连接第二射频晶体管的源极；第二射频晶体管的漏极通过扼流电感连接供电电压端，第二射频晶体管的漏极还通过输出匹配网络连接输出信号端；第一去耦电容的一端与供电电压端连接，另一端接地；第一射频晶体管的栅极还连接第一偏置电路，第二射频晶体管的栅极还连接第二偏置电路，并连接第二去耦电容，第二去耦电容的另一端接地；所述第一偏置电路和第二偏置电路分别连接功率控制单元，所述功率控制单元具有至少一个用于调整第一偏置电路和第二偏置电路的输出偏置电压的输入控制信号端。
  2. 根据权利要求1所述的效率提高的共源共栅射频功率放大器，其特征在于，所述共源共栅晶体管对组成并联结构。
  3. 根据权利要求1所述的效率提高的共源共栅射频功率放大器，其特征在于，所述输入控制信号端连接***控制器或者连接射频功率放大器输出检测处理电路的输出端。
  4. 根据权利要求1所述的效率提高的共源共栅射频功率放大器，其特征在于，所述第一偏置电路和第二偏置电路包括第三晶体管、第四晶体管、和第五晶体管；所述第三晶体管的源极接地，栅极通过第一电阻连接第五晶体管的源极，第五晶体管的源极还连接一接地的第二电阻；第三晶体管的漏极连接第三电阻、第一电容和第四晶体管的栅极，第三电阻的另一端连接第四电阻和第五晶体管的栅极，第四电阻另一端连接输入控制信号端，第一电容的另一端接地；第四晶体管和第五晶体管的漏极连接供电电压端，第四晶体管的源极连接一接地的第五电阻和第六电阻，第六电阻的另一端连接输出端。
  5. 根据权利要求2所述的效率提高的共源共栅射频功率放大器，其特征在于，所述共源共栅晶体管对为2个，包括由第一射频晶体管和第二射频晶体管组成的第一共源共栅晶体管对，以及由第三射频晶体管和第四射频晶体管组成的第二共源共栅晶体管对；所述第一射频晶体管、第二射频晶体管、第三射频晶体管和第四射频晶体管为GaAs E/D pHEMT晶体管，第一射频 晶体管的源极接地，栅极连接第一隔直电容的一端及第一偏置电路的输出端，第一隔直电容的另一端通过输入匹配网络连接输入信号端，第一射频晶体管的漏极连接第二射频晶体管的源极，第二射频晶体管的栅极连接第一去耦电容的一端及第二偏置电路输出端，第一去耦电容的另一端接地，第二射频晶体管的漏极连接第四射频晶体管的漏极及扼流电感的一端，并通过输出匹配网络连接输出信号端，扼流电感的另一端连接供电电压端及第三去耦电容的一端，第三去耦电容的另一端接地，第三射频晶体管的源极接地，第三射频晶体管的栅极连接第二隔直电容的一端及第三偏置电路的输出端，第二隔直电容的另一端通过输入匹配网络连接输入信号端，第三射频晶体管的漏极连接第四射频晶体管的源极；第四射频晶体管的栅极连接第二去耦电容的一端及第四偏置电路的输出端，第二去耦电容的另一端接地，第四射频晶体管的漏极连接第二射频晶体管的漏极及扼流电感的一端，并通过输出匹配网络连接到输出信号端，第一偏置电路、第二偏置电路、第三偏置电路和第四偏置电路的输入端，分别连接功率控制单元的四个输出端，所述功率控制单元具有至少一个用于调整第一偏置电路、第二偏置电路、第三偏置电路和第四偏置电路的输出偏置电压的输入控制信号端。
  6. 根据权利要求5所述的效率提高的共源共栅射频功率放大器，其特征在于，所述输入控制信号端连接***控制器或者连接射频功率放大器输出检测处理电路的输出端。
  7. 根据权利要求5所述的效率提高的共源共栅射频功率放大器，其特征在于，所述第一偏置电路、第二偏置电路、第三偏置电路和第四偏置电路包括第三晶体管、第四晶体管、和第五晶体管；所述第三晶体管的源极接地，栅极通过第一电阻连接第五晶体管的源极，第五晶体管的源极还连接一接地的第二电阻；第三晶体管的漏极连接第三电阻、第一电容和第四晶体管的栅极，第三电阻的另一端连接第四电阻和第五晶体管的栅极，第四电阻另一端连接输入控制信号端，第一电容的另一端接地；第四晶体管和第五晶体管的漏极连接供电电压端，第四晶体管的源极连接一接地的第五电阻和第六电阻，第六电阻的另一端连接输出端。
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