WO2016146053A1

WO2016146053A1 - Display device, and pixel circuit and driving method thereof

Info

Publication number: WO2016146053A1
Application number: PCT/CN2016/076344
Authority: WO
Inventors: 张盛东; 孟雪; 冷传利; 王翠翠
Original assignee: 北京大学深圳研究生院
Priority date: 2015-03-19
Filing date: 2016-03-15
Publication date: 2016-09-22
Also published as: CN104715723A; CN104715723B

Abstract

A pixel circuit comprises: a driving transistor (T1) and a light emitting element serially-connected between a first power level end (VDD) and a second power level end (VSS), wherein a first gate of the driving transistor (T1) is connected to a first end of the light emitting element, a second transistor (T2) and a storage capacitor (C1) are connected between a control gate of the driving transistor (T1) and a conduction electrode. At an initialization stage, the second transistor (T2) conducts to separately initialize voltage levels of two ends of the storage capacitor (C1) and a voltage level of the control gate of the driving transistor (T1). At a threshold compensation stage, a reference voltage level (V REF) is provided to the control gate of the driving transistor (T1), so as to read a threshold voltage (V TH) of the driving transistor (T1) and store the same in the storage capacitor (C1), thereby compensating for the threshold voltage (V TH) of the driving transistor (T1) and inhomogeneity shown in the pixel circuit.

Description

显示装置及其像素电路和驱动方法Display device, pixel circuit thereof and driving method thereof

技术领域Technical field

本申请涉及显示器件领域，具体涉及一种显示装置及其像素电路和驱动方法。The present application relates to the field of display devices, and in particular, to a display device, a pixel circuit thereof, and a driving method.

背景技术Background technique

有机发光二极管(Organic Light-Emitting Diode，OLED)显示因具有高亮度、高发光效率、宽视角和低功耗等优点，近年来被人们广泛研究，并迅速应用到新一代的显示当中。OLED显示的驱动方式可以为无源矩阵驱动(Passive Matrix OLED，PMOLED)和有源矩阵驱动(Active Matrix OLED，AMOLED)两种。无源矩阵驱动虽然成本低廉，但是存在交叉串扰现象不能实现高分辨率的显示，且无源矩阵驱动电流大，降低了OLED的使用寿命。相比之下，有源矩阵驱动方式在每个像素上设置数目不同的晶体管作为电流源，避免了交叉串扰，所需的驱动电流较小，功耗较低，使OLED的寿命增加，可以实现高分辨的显示，同时，有源矩阵驱动更容易满足大面积和高灰度级显示的需要。Organic Light-Emitting Diode (OLED) has been widely studied in recent years due to its high brightness, high luminous efficiency, wide viewing angle and low power consumption, and has been rapidly applied to a new generation of displays. The OLED display can be driven by either a passive matrix OLED (PMOLED) or an active matrix OLED (AMOLED). Although the passive matrix drive is low in cost, the crosstalk phenomenon cannot achieve high-resolution display, and the passive matrix drive current is large, which reduces the service life of the OLED. In contrast, the active matrix driving method sets a different number of transistors as current sources on each pixel, avoiding crosstalk, requiring less driving current, lower power consumption, and increasing the lifetime of the OLED, which can be realized. High resolution display, while active matrix drive is easier to meet the needs of large area and high gray level display.

传统AMOLED的像素电路是简单的两薄膜场效应晶体管(Thin Film Transistor，TFT)结构，这种电路虽然结构简单，但是不能补偿驱动晶体管T1和OLED阈值电压漂移或因TFT器件采用多晶材料制成而导致面板各处TFT器件的阈值电压不均匀性。当驱动晶体管T1阈值电压、OLED阈值电压发生漂移或在面板上各处的值不一致时，驱动电流I_DS就会改变，并且面板上不同的像素因偏置电压的不同漂移情况也不一样，这样就会造成面板显示的不均匀性。The pixel circuit of the conventional AMOLED is a simple two-film Thin Film Transistor (TFT) structure. Although this structure is simple, it cannot compensate for the threshold voltage drift of the driving transistor T1 and the OLED or is made of a polycrystalline material for the TFT device. This results in threshold voltage non-uniformity of the TFT devices throughout the panel. When the threshold voltage of the driving transistor T1, the threshold voltage of the OLED drifts, or the values across the panel are inconsistent, the driving current I _DS changes, and different pixels on the panel drift differently due to different bias voltages. This will cause unevenness in the display of the panel.

发明内容Summary of the invention

本申请提供一种显示装置及其像素电路和驱动方法，以补偿驱动晶体管的阈值电压的不均匀性或者阈值电压漂移。The present application provides a display device and a pixel circuit and a driving method thereof to compensate for a non-uniformity of a threshold voltage or a threshold voltage drift of a driving transistor.

根据第一方面，一种实施例中提供一种像素电路，包括：According to a first aspect, an embodiment provides a pixel circuit, including:

用于串联在第一电平端和第二电平端之间的驱动晶体管和发光元件，以及第二晶体管、第三晶体管和存储电容；驱动晶体管的第一极连接至发光元件的第一端形成第三节点，驱动晶体管的第二极和发光元件的第二端分别用于连接至第一电平端和第二电平端；驱动晶体管的控制极连接至第二晶体管的第一极形成第一节点，第二晶体管的第二极连接至第三晶体管的第一极形成第二节点，第二晶体管的控制极用于输入发光控制信号；第三晶体管的第二极用于连接至用于提供数据信号或者参考电位的数据线，第三晶体管的控制极用于输入扫描信号；存储电容连接至第二节点和第三节点之间。a driving transistor and a light emitting element connected in series between the first level end and the second level end, and a second transistor, a third transistor and a storage capacitor; the first end of the driving transistor is connected to the first end of the light emitting element to form a first a three node, a second end of the driving transistor and a second end of the light emitting element are respectively connected to the first level end and the second level end; the control electrode of the driving transistor is connected to the first pole of the second transistor to form the first node, Second pole connection of the second transistor The first pole to the third transistor forms a second node, the gate of the second transistor is used to input the illumination control signal; and the second pole of the third transistor is used to connect to the data line for providing the data signal or the reference potential, A three-transistor gate is used to input the scan signal; a storage capacitor is connected between the second node and the third node.

根据第二方面，一种实施例中提供一种像素电路，包括：According to a second aspect, an embodiment provides a pixel circuit, including:

用于串联在第一电平端和第二电平端之间的驱动晶体管和发光元件，以及第二晶体管、第三晶体管、第四晶体管、第五晶体管和存储电容；驱动晶体管的第一极连接至发光元件的第一端形成第三节点，驱动晶体管的第二极和发光元件的第二端分别用于连接至第一电平端和第二电平端；驱动晶体管的控制极连接至第二晶体管的第一极形成第一节点，第二晶体管的第二极连接至第三晶体管的第一极形成第二节点，第二晶体管的控制极用于输入发光控制信号；第三晶体管的第二极用于连接至用于提供数据信号的数据线，第三晶体管的控制极用于输入扫描信号；第五晶体管的第一极连接至第一节点，第五晶体管的第二极用于输入参考电位，第五晶体管的控制极连接至第三晶体管的控制极；第四晶体管的第一极连接至第三节点，第四晶体管的第二极用于输入初始化电位，第四晶体管的控制极用于输入初始化控制信号；存储电容连接至第二节点和第三节点之间。a driving transistor and a light emitting element connected in series between the first level end and the second level end, and a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a storage capacitor; the first pole of the driving transistor is connected to a first end of the light emitting element forms a third node, a second end of the driving transistor and a second end of the light emitting element are respectively connected to the first level end and the second level end; the control electrode of the driving transistor is connected to the second transistor The first pole forms a first node, the second pole of the second transistor is connected to the first pole of the third transistor to form a second node, the control pole of the second transistor is used for inputting the illumination control signal, and the second pole of the third transistor is used Connected to a data line for providing a data signal, a control electrode of the third transistor is used to input the scan signal; a first pole of the fifth transistor is connected to the first node, and a second pole of the fifth transistor is used for inputting the reference potential, a control electrode of the fifth transistor is connected to the control electrode of the third transistor; a first electrode of the fourth transistor is connected to the third node, and a second electrode of the fourth transistor is used for input Initialization potential, the control electrode of the fourth transistor for inputting an initialization control signal; storage capacitor connected between the second node and a third node.

根据第三方面，一种实施例中提供一种显示装置，包括：According to a third aspect, an embodiment provides a display device, including:

像素电路矩阵，所述像素电路矩阵包括排列成n行m列矩阵的上述的像素电路，其中，n和m为大于0的整数；栅极驱动电路，用于产生扫描脉冲信号，并通过沿第一方向形成的各行扫描线向像素电路提供所需的控制信号；数据驱动电路，用于产生代表灰度信息的数据电压信号，并通过沿第二方向形成的各数据线向像素电路提供数据信号；控制器，用于向栅极驱动电路和数据驱动电路提供控制时序。a pixel circuit matrix, the pixel circuit matrix comprising the above pixel circuit arranged in a matrix of n rows and m columns, wherein n and m are integers greater than 0; a gate driving circuit for generating a scan pulse signal and passing along Each row of scan lines formed in one direction supplies a desired control signal to the pixel circuit; a data driving circuit for generating a data voltage signal representative of gray scale information, and providing a data signal to the pixel circuit through each data line formed along the second direction a controller for providing control timing to the gate drive circuit and the data drive circuit.

根据第四方面，一种实施例中提供一种像素电路驱动方法，像素电路的每一驱动周期包括初始化阶段、阈值补偿阶段、数据写入阶段和发光阶段，驱动方法包括：According to a fourth aspect, an embodiment provides a pixel circuit driving method. Each driving cycle of the pixel circuit includes an initialization phase, a threshold compensation phase, a data writing phase, and an illumination phase. The driving method includes:

在初始化阶段，第二晶体管导通，分别初始化存储电容两端的电位和驱动晶体管控制极的电位；在阈值补偿阶段，第三晶体管和/或第五晶体管导通，向驱动晶体管控制极提供参考电位，读取驱动晶体管的阈值电压信息并通过存储电容存储；在数据写入阶段，第三晶体管导通传输数据电压并存储于存储电容；在发光阶段，第一晶体管根据存储电容两端的压差驱动产生驱动电流，并驱动发光元件发光。In the initialization phase, the second transistor is turned on to initialize the potential across the storage capacitor and the potential of the control transistor control terminal respectively; in the threshold compensation phase, the third transistor and/or the fifth transistor are turned on to provide a reference potential to the control transistor control electrode. Reading the threshold voltage information of the driving transistor and storing it through the storage capacitor; during the data writing phase, the third transistor is turned on The data voltage is stored in the storage capacitor; in the light emitting phase, the first transistor drives the driving current according to the voltage difference across the storage capacitor, and drives the light emitting element to emit light.

依据上述实施例的像素电路，通过在驱动晶体管的控制极和第一极之间连接第二晶体管和存储电容，并配合时序的控制，利用向驱动晶体管控制极提供参考电位读取驱动晶体管的阈值电压并存储于存储电容，从而实现了对驱动晶体管阈值电压的补偿，继而补偿了像素电路显示的不均匀性。According to the pixel circuit of the above embodiment, by connecting the second transistor and the storage capacitor between the gate electrode of the driving transistor and the first electrode, and controlling the timing, the threshold value of the reference potential reading driving transistor is supplied to the driving transistor control electrode. The voltage is stored in the storage capacitor, thereby compensating for the threshold voltage of the drive transistor, which in turn compensates for the non-uniformity of the display of the pixel circuit.

附图说明DRAWINGS

图1a为实施例一公开的一种像素电路结构图；1a is a structural diagram of a pixel circuit disclosed in Embodiment 1;

图1b为实施例一公开的另一种像素电路结构图；FIG. 1b is a structural diagram of another pixel circuit disclosed in Embodiment 1; FIG.

图2为实施例一公开的一种像素电路驱动时序图；2 is a timing chart of driving a pixel circuit disclosed in Embodiment 1;

图3a为实施例二公开的一种像素电路结构图；FIG. 3a is a structural diagram of a pixel circuit disclosed in Embodiment 2; FIG.

图3b为实施例二公开的另一种像素电路结构图；FIG. 3b is a structural diagram of another pixel circuit disclosed in Embodiment 2; FIG.

图4为实施例二公开的一种像素电路驱动时序图；4 is a timing chart of driving a pixel circuit disclosed in Embodiment 2;

图5a为实施例二公开的一种提供初始化电位变形方案；FIG. 5a is a schematic diagram showing an initialization potential deformation scheme disclosed in Embodiment 2; FIG.

图5b为实施例二公开的另一种提供初始化电位变形方案；FIG. 5b is another embodiment of providing an initialization potential deformation scheme disclosed in Embodiment 2; FIG.

图6a为实施例三公开的一种像素电路结构图；FIG. 6a is a structural diagram of a pixel circuit disclosed in Embodiment 3; FIG.

图6b为实施例三公开的另一种像素电路结构图；FIG. 6b is a structural diagram of another pixel circuit disclosed in Embodiment 3; FIG.

图7为实施例三公开的一种像素电路驱动时序图；7 is a timing chart of driving a pixel circuit disclosed in Embodiment 3;

图8a为实施例四公开的一种像素电路结构图；FIG. 8a is a structural diagram of a pixel circuit disclosed in Embodiment 4; FIG.

图8b为实施例四公开的另一种像素电路结构图；FIG. 8b is a structural diagram of another pixel circuit disclosed in Embodiment 4; FIG.

图9为实施例四公开的一种像素电路驱动时序图；9 is a timing chart of driving a pixel circuit disclosed in Embodiment 4;

图10a为实施例五公开的一种像素电路结构图；FIG. 10a is a structural diagram of a pixel circuit disclosed in Embodiment 5; FIG.

图10b为实施例五公开的另一种像素电路结构图；FIG. 10b is a structural diagram of another pixel circuit disclosed in Embodiment 5; FIG.

图11为实施例五公开的一种像素电路驱动时序图；11 is a timing chart of driving a pixel circuit disclosed in Embodiment 5;

图12为实施例六公开的一种显示装置结构原理图。FIG. 12 is a schematic structural diagram of a display device disclosed in Embodiment 6.

具体实施方式detailed description

下面通过具体实施方式结合附图对本发明作进一步详细说明。The present invention will be further described in detail below with reference to the accompanying drawings.

首先对一些术语进行说明：本申请中的晶体管可以是任何结构的晶体管，比如双极型晶体管(BJT)或者场效应晶体管(FET)。当晶体管为双极型晶体管时，其控制极是指双极型晶体管的基极，第一极可以为双极型晶体管的集电极或发射极，对应的第二极可以为双极型晶体管的发射极或集电极，在实际应用过程中，“发射极”和“集电极”可以依据信号流向而互换；当晶体管为场效应晶体管时，其控制极是指场效应晶体管的栅极，第一极可以为场效应晶体管的漏极或源极，对应的第二极可以为场效应晶体管的源极或漏极，在实际应用过程中，“源极”和“漏极”可以依据信号流向而互换。显示器中的晶体管通常为一种场效应晶体管：薄膜晶体管(TFT)。下面以晶体管为场效应晶体管为例对本申请做详细的说明，在其它实施例中晶体管也可以是双极型晶体管。First, some terms are explained: the transistor in the present application may be a transistor of any structure, such as a bipolar transistor (BJT) or a field effect transistor (FET). When the transistor is a bipolar transistor, the gate of the transistor is the base of the bipolar transistor, the first pole can be the collector or emitter of the bipolar transistor, and the corresponding second pole can be a bipolar transistor. Launch The pole or collector, in the actual application process, the "emitter" and "collector" can be interchanged according to the signal flow direction; when the transistor is a field effect transistor, the control pole refers to the gate of the field effect transistor, first The pole may be the drain or the source of the field effect transistor, and the corresponding second pole may be the source or the drain of the field effect transistor. In practical applications, the “source” and “drain” may depend on the signal flow direction. exchange. The transistor in the display is typically a field effect transistor: a thin film transistor (TFT). In the following, the present application will be described in detail by taking a transistor as a field effect transistor. In other embodiments, the transistor may also be a bipolar transistor.

发光元件为有机发光二极管(Organic Light-Emitting Diode，OLED)，在其它实施例中，也可以是其它发光元件。发光元件的第一端可以是阴极或阳极，相应地，则发光元件的第二端为阳极或阴极。本领域技术人员应当理解：电流应从发光元件的阳极流向阴极，因此，基于电流的流向，可以确定发光元件的阳极和阴极。The light-emitting element is an Organic Light-Emitting Diode (OLED). In other embodiments, other light-emitting elements may also be used. The first end of the illuminating element can be a cathode or an anode, and correspondingly, the second end of the illuminating element is an anode or a cathode. It will be understood by those skilled in the art that the current should flow from the anode of the light-emitting element to the cathode, and therefore, based on the flow direction of the current, the anode and cathode of the light-emitting element can be determined.

有效电平可以是高电平，也可以是低电平，可根据具体元器件的功能实现作适应性地置换。The effective level can be either a high level or a low level, which can be adaptively replaced according to the function of the specific component.

第一电平端和第二电平端是为像素电路工作所提供的电源两端。在一种实施例中，第一电平端可以为高电平端V_DD，第二电平端为低电平端V_SS或地线，在其它实施例中，也可以作适应性地置换。需要说明的是：对于像素电路而言，第一电平端(例如高电平端V_DD)和第二电平端(例如低电平端V_SS)并非本申请像素电路的一部分，为了使本领域技术人员更好地理解本申请的技术方案，而特别引入第一电平端和第二电平端予以描述。The first level terminal and the second level terminal are both ends of the power supply provided for the operation of the pixel circuit. In one embodiment, the first level terminal may be a high level terminal V _DD and the second level terminal may be a low level terminal V _SS or a ground line, and in other embodiments, may be adaptively replaced. It should be noted that, for the pixel circuit, the first level terminal (eg, the high level terminal V _DD ) and the second level terminal (eg, the low level terminal V _SS ) are not part of the pixel circuit of the present application, in order to enable those skilled in the art. A better understanding of the technical solution of the present application, and particularly introducing the first level terminal and the second level terminal, will be described.

需要说明的是，为了描述方便，也为了使本领域技术人员更清楚地理解本申请的技术方案，本申请文件中引入第一节点A、第二节点B和第三节点C对电路结构相关部分进行标识，不能认定为电路中额外引入的端子。It should be noted that, for the convenience of description, and in order to make the technical solutions of the present application more clearly understood by those skilled in the art, the first node A, the second node B, and the third node C are introduced in the present application. Identification is not recognized as an additional terminal introduced in the circuit.

为描述方便，高电平采用V_H表征，低电平采用V_L表征。For convenience of description, the high level is characterized by V _H and the low level is characterized by V _L .

实施例一：Embodiment 1:

请参考图1a和图1b，为本实施例公开的一种像素电路结构图，包括：用于串联在第一电平端VDD和第二电平端VSS之间的驱动晶体管T1和发光元件OLED，以及第二晶体管T2、第三晶体管T3和存储电容C1。其中，图1a所示的像素电路中，各晶体管(驱动晶体管T1、第二晶体管T2和第三晶体管T3)为N型薄膜晶体管；图1b所示的像素电路中，各晶体管(驱动晶体管T1、第二晶体管T2和第三晶体管T3)为P型薄膜晶体管。Referring to FIG. 1a and FIG. 1b, a structure of a pixel circuit disclosed in the embodiment includes: a driving transistor T1 and a light emitting element OLED connected in series between a first level terminal VDD and a second level terminal VSS, and The second transistor T2, the third transistor T3, and the storage capacitor C1. In the pixel circuit shown in FIG. 1a, each transistor (the driving transistor T1, the second transistor T2, and the third transistor T3) is an N-type thin film transistor; the pixel device shown in FIG. 1b In the path, each of the transistors (the driving transistor T1, the second transistor T2, and the third transistor T3) is a P-type thin film transistor.

驱动晶体管T1的第一极连接至发光元件OLED的第一端形成第三节点C，驱动晶体管T1的第二极和发光元件OLED的第二端分别用于连接至第一电平端VDD和第二电平端VSS。在一种实施例中，请参考图1a，发光元件OLED的第一端为阳极，发光元件OLED的第二端为阴极；驱动晶体管T1的第二极用于连接至第一电平端VDD，发光元件OLED的第二端用于连接至第二电平端VSS。在另一种实施例中，请参考图1b，发光元件OLED的第一端为阴极，发光元件OLED的第二端为阳极；驱动晶体管T1的第二极用于连接至第二电平端VSS，发光元件OLED的第二端用于连接至第一电平端VDD。The first end of the driving transistor T1 is connected to the first end of the light emitting element OLED to form a third node C, and the second end of the driving transistor T1 and the second end of the light emitting element OLED are respectively connected to the first level terminal VDD and the second Level terminal VSS. In one embodiment, referring to FIG. 1a, the first end of the light emitting element OLED is an anode, the second end of the light emitting element OLED is a cathode, and the second end of the driving transistor T1 is used to connect to the first level terminal VDD, and emit light. The second end of the element OLED is for connection to the second level terminal VSS. In another embodiment, referring to FIG. 1b, the first end of the light emitting element OLED is a cathode, the second end of the light emitting element OLED is an anode, and the second end of the driving transistor T1 is used to be connected to the second level terminal VSS. The second end of the light emitting element OLED is for connection to the first level terminal VDD.

驱动晶体管T1的控制极连接至第二晶体管T2的第一极形成第一节点A，第二晶体管T2的第二极连接至第三晶体管T3的第一极形成第二节点B，第二晶体管T2的控制极用于输入发光控制信号V_EM。The control electrode of the driving transistor T1 is connected to the first electrode of the second transistor T2 to form the first node A, the second electrode of the second transistor T2 is connected to the first electrode of the third transistor T3 to form the second node B, and the second transistor T2 The control electrode is used to input the illumination control signal V _EM .

第三晶体管T3的第二极用于连接至数据线DATA，在具体实施例中，数据线DATA用于提供数据信号V_DATA或者参考电位V_REF，在其它实施例中，数据线DATA还可以用于提供初始化电位，以初始化各节点的电位；第三晶体管T3的控制极用于输入扫描信号V_Scan。The second pole of the third transistor T3 is for connection to the data line DATA. In a specific embodiment, the data line DATA is used to provide the data signal V _DATA or the reference potential V _REF . In other embodiments, the data line DATA can also be used. An initialization potential is provided to initialize the potential of each node; a gate of the third transistor T3 is used to input the scan signal _VScan .

存储电容C1连接至第二节点B和第三节点C之间。The storage capacitor C1 is connected between the second node B and the third node C.

在具体实施例中，像素电路依次工作于第一阶段、第二阶段和第三阶段。在本实施例中，第一阶段可以依次包括初始化阶段和阈值补偿阶段，第二阶段为数据写入阶段，第三阶段为发光阶段。In a particular embodiment, the pixel circuits operate in a first phase, a second phase, and a third phase in sequence. In this embodiment, the first phase may sequentially include an initialization phase and a threshold compensation phase, the second phase is a data writing phase, and the third phase is a lighting phase.

在第一阶段，第二晶体管T2和第三晶体管T3分别响应发光控制信号V_EM的第一有效电平和扫描信号V_Scan的第一有效电平导通，向第一节点A和第二节点B传输参考电位V_REF初始化第一节点A和第二节点B的电位，并通过相应的信号源向第三节点C提供初始化电位，以初始化第三节点C的电位，在本实施例中，第三节点C的初始化电位由第一电平端VDD通过导通的驱动晶体管T1提供，并读取驱动晶体管T1的阈值电压V_TH。在一种实施例中，请参考图1a，在初始化阶段，驱动晶体管T1的第二极传输第一电平端VDD提供的初始化电位(例如低电平)初始化第三节点C的电位；在阈值补偿阶段，驱动晶体管T1的第二极传输第一电平端VDD的有效电平(例如高电平)，于是，第三节点C的电位发生变化(例如升高)，直到该节点电位与驱动晶体管T1的控制极相差一个驱动晶体管T1的阈值电压时为止，存储电容C1根据驱动晶体管T1的控制极(即第二节点B或者第一节点A)的电位和与第三节点C之间的压差得到驱动晶体管T1的阈值电压V_TH。在另一种实施例中，请参考图1b，在初始化阶段，第三节点C的初始化电位由第二电平端VSS提供，即驱动晶体管T1的第二极传输第二电平端VSS提供的初始化电位(例如高电平)初始化第三节点C的电位；在阈值补偿阶段，驱动晶体管T1的第二极传输第二电平端VSS的有效电平(例如低电平)，于是，第三节点C的电位发生变化(例如下降)，直到该节点电位与驱动晶体管T1的控制极相差一个驱动晶体管T1的阈值电压时为止，存储电容C1根据驱动晶体管T1的控制极(即第二节点B或者第一节点A)的电位和与第三节点C之间的压差得到驱动晶体管T1的阈值电压V_TH。In the first stage, the second transistor T2 and the third transistor T3 are respectively turned on in response to the first active level of the light emission control signal V _{EM and} the first active level of the scan signal V _Scan , to the first node A and the second node B The transfer reference potential V _REF initializes the potentials of the first node A and the second node B, and supplies an initialization potential to the third node C through the corresponding signal source to initialize the potential of the third node C, in this embodiment, the third The initialization potential of the node C is supplied from the first level terminal VDD through the driving transistor T1 that is turned on, and the threshold voltage V _{TH of the} driving transistor T1 is read. In an embodiment, referring to FIG. 1a, in the initialization phase, the second pole of the driving transistor T1 transmits an initializing potential (eg, a low level) provided by the first level terminal VDD to initialize the potential of the third node C; at the threshold compensation In the stage, the second pole of the driving transistor T1 transmits an active level (for example, a high level) of the first level terminal VDD, and then the potential of the third node C changes (eg, rises) until the node potential and the driving transistor T1 The storage capacitor C1 is obtained according to the potential difference between the control electrode of the driving transistor T1 (ie, the second node B or the first node A) and the voltage difference between the third node C and the threshold voltage of the driving transistor T1. The threshold voltage V _{TH of the} driving transistor T1 is driven. In another embodiment, referring to FIG. 1b, in the initialization phase, the initialization potential of the third node C is provided by the second level terminal VSS, that is, the second pole of the driving transistor T1 transmits the initialization potential provided by the second level terminal VSS. (eg, a high level) initializes the potential of the third node C; in the threshold compensation phase, the second pole of the driving transistor T1 transmits an active level (eg, a low level) of the second level terminal VSS, and thus, the third node C The potential changes (eg, drops) until the node potential is different from the control electrode of the driving transistor T1 by a threshold voltage of the driving transistor T1, and the storage capacitor C1 is based on the control electrode of the driving transistor T1 (ie, the second node B or the first node) The potential difference between A) and the third node C results in a threshold voltage _{VTH of the} driving transistor T1.

在第二阶段，第二晶体管T2由发光控制信号V_EM控制在截止状态，第三晶体管T3响应扫描信号V_Scan的第二有效电平导通向第二节点B传输数据信号V_DATA；In the second stage, the second transistor T2 is controlled to be in an off state by the illumination control signal V _EM , and the third transistor T3 is turned on to transmit the data signal V _DATA to the second node B in response to the second active level of the scan signal V _Scan ;

在第三阶段，第三晶体管T3由扫描信号V_Scan控制在截止状态，第二晶体管T2响应发光控制信号V_EM的第二有效电平导通，驱动晶体管T1响应第一节点A的电位导通驱动发光元件OLED发光。In the third stage, the third transistor T3 is controlled to be in an off state by the scan signal _VScan , the second transistor T2 is turned on in response to the second active level of the light emission control signal _VEM , and the driving transistor T1 is turned on in response to the potential of the first node A. The light emitting element OLED is driven to emit light.

需要说明的是，在一种实施例中，请参考图1a，发光控制信号V_EM有效电平(包括第一有效电平和第二有效电平)和扫描信号V_Scan的有效电平(包括第一有效电平和第二有效电平)均为高电平；在另一种实施例中，请参考图1b，发光控制信号V_EM的有效电平(包括第一有效电平和第二有效电平)和扫描信号V_Scan的有效电平(包括第一有效电平和第二有效电平)均为低电平。It should be noted that, in an embodiment, please refer to FIG. 1a, the active level of the illumination control signal V _EM (including the first active level and the second active level) and the active level of the scan signal V _Scan (including the first An active level and a second active level are both high levels; in another embodiment, please refer to FIG. 1b, the active level of the illumination control signal V _EM (including the first active level and the second active level) And the active level of the scan signal _VScan (including the first active level and the second active level) are both low.

在本实施例中，扫描信号V_Scan的第二有效电平滞后于所述扫描信号V_Scan的第一有效电平和发光控制信号V_EM的第一有效电平，发光控制信号V_EM的第二有效电平滞后于扫描信号V_Scan的第二有效电平。In the present embodiment, the second active level of the scanning signal V _Scan lags a first active level and the scanning signal V _Scan emitting a first active-level control signal V _EM, the light emission control signal V _EM second The effective level lags behind the second active level of the scan signal _VScan .

下文以图1a为例对本实施例公开的像素电路驱动过程予以说明。本实施例的像素电路驱动过程分为初始化阶段、阈值补偿阶段、数据写入阶段和发光阶段，如图2所示为本实施例的信号时序，结合图2和图1a具体描述本实施例的驱动过程。The pixel circuit driving process disclosed in this embodiment will be described below by taking FIG. 1a as an example. The pixel circuit driving process of this embodiment is divided into an initialization phase, a threshold compensation phase, a data writing phase, and an illuminating phase. As shown in FIG. 2, the signal timing of the present embodiment is specifically described in conjunction with FIG. 2 and FIG. Drive process.

在初始化阶段：向第三晶体管T3提供的扫描信号V_Scan为高电平V_H，即为第一有效电平；发光控制信号V_EM为高电平V_H，即为第一有效电平。于是，第三晶体管T3和第二晶体管T2导通。数据线DATA向第三晶体管T3传输参考电位V_REF，该参考电位V_REF通过导通的晶体管T3和T2输入到第一节点A，使得第一节点A的电位为V_REF，由于第一节点A和第二节点B通过第二晶体管T2连通，所以两个节点电压相同。与此同时，驱动晶体管T1处于导通状态，第一电平端VDD输出一初始化电位低电平信号V_L，该电平信号并通过开关晶体管T1输入到第三节点C，使得第三节点C电平变为V_L。从而，完成了对第一节点A、第二节点B和第三节点C的电位初始化。In the initialization phase: the scan signal V _Scan supplied to the third transistor T3 is at a high level V _H , that is, a first active level; and the light emission control signal V _EM is at a high level V _H , that is, a first active level. Thus, the third transistor T3 and the second transistor T2 are turned on. The data line DATA transmits a reference potential V _REF to the third transistor T3, and the reference potential V _REF is input to the first node A through the turned-on transistors T3 and T2 such that the potential of the first node A is V _REF due to the first node A And the second node B is connected through the second transistor T2, so the two node voltages are the same. At the same time, the driving transistor T1 is in an on state, and the first level terminal VDD outputs an initializing potential low level signal V _L , and the level signal is input to the third node C through the switching transistor T1, so that the third node C is electrically Flat becomes V _L . Thereby, the potential initialization of the first node A, the second node B, and the third node C is completed.

在阈值补偿阶段：扫描信号V_Scan和发光控制信号V_EM继续维持第一有效电平，高电平V_H，数据线DATA依旧传输参考电位V_REF。第一电平端VDD提供的信号由低电平V_L变回高电平V_H，并通过驱动晶体管T1给第三节点C充电。第三节点C的电位因此会慢慢升高，直到该节点升高到V_REF-V_TH时，驱动晶体管T1会进入截止状态，第三节点C的电位维持为V_REF-V_TH。其中V_TH为驱动晶体管T1的阈值电压。阈值补偿阶段结束后，驱动晶体管T1的阈值电压信息通过存储电容C1被存储到节点C上。需要注意的是，V_REF-V_TH小于发光元件OLED的阈值电压。In the threshold compensation phase: the scan signal V _Scan and the illumination control signal V _EM continue to maintain the first active level, the high level V _H , and the data line DATA still transmits the reference potential V _REF . The signal supplied from the first level terminal VDD is changed from the low level V _L back to the high level V _H , and the third node C is charged through the driving transistor T1. The potential of the third node C is thus slowly increased until the node rises to V _REF -V _TH , the driving transistor T1 enters an off state, and the potential of the third node C is maintained at V _REF -V _TH . Where V _TH is the threshold voltage of the driving transistor T1. After the threshold compensation phase ends, the threshold voltage information of the driving transistor T1 is stored to the node C through the storage capacitor C1. It should be noted that V _REF —V _{TH is} smaller than the threshold voltage of the light-emitting element OLED.

数据写入阶段：发光控制信号V_EM变为低电平，扫描信号V_Scan变为第二有效电平，如高电平V_H。此时，第二晶体管T2处于截止状态，第三晶体管T3处于导通状态，数据线DATA提供数据电压V_DATA并通过导通的第三晶体管T3写入到第二节点B中。需要说明的是，在其它实施例中，当存在多行像素电路并采用同时发光的方式时，则在该阶段，各行扫描信号V_Scan的第二有效电平依次到来，以逐行完成第二节点B的数据电压V_DATA写入。在第二节点B的电位由V_REF充电到V_DATA的过程中，数据电压V_DATA会通过存储电容C1和发光元件OLED的本征电容C2的耦合作用被耦合到节点C中从而使节点C的电位变化为：Data writing phase: The lighting control signal V _EM becomes a low level, and the scanning signal V _Scan becomes a second active level, such as a high level V _H . At this time, the second transistor T2 is in an off state, the third transistor T3 is in an on state, and the data line DATA supplies the data voltage V _DATA and is written into the second node B through the turned-on third transistor T3. It should be noted that, in other embodiments, when there are multiple rows of pixel circuits and adopt the manner of simultaneous illumination, then at this stage, the second active level of each row of scan signals V _Scan comes in order to complete the second row by row. Node B's data voltage V _{DATA is} written. During the charging of the potential of the second node B from V _REF to V _DATA , the data voltage V _DATA is coupled to the node C through the coupling of the storage capacitor C1 and the intrinsic capacitance C2 of the light emitting element OLED to thereby make the node C The potential change is:

其中，VnodeC代表第三节点C的电位，C1和C2则分别是存储电容C1和发光元件OLED的本征电容的电容值。Wherein, VnodeC represents the potential of the third node C, and C1 and C2 are the capacitance values of the storage capacitor C1 and the intrinsic capacitance of the light emitting element OLED, respectively.

发光阶段：发光控制信号V_EM第二有效电平如高电V_H平到来，扫描信号V_Scan维持为低电平。此时，第二晶体管T2处于导通状态，发光元件OLED开始发光，并且第三节点C的电位也变为V_OLED。V_OLED为发光元件OLED在发光时阳极的电位。此时，由于第二节点B和第一节点A通过第二晶体管T2耦合，两节点电位相同，节点A(B)由于存储电容C1的耦合作用而变为：Illumination phase: The second active level of the illumination control signal V _EM, such as the high voltage V _{H ,} comes, and the scan signal V _{Scan is} maintained at a low level. At this time, the second transistor T2 is in an on state, the light emitting element OLED starts to emit light, and the potential of the third node C also becomes V _OLED . The V _OLED is the potential of the anode of the light-emitting element OLED when it emits light. At this time, since the second node B and the first node A are coupled by the second transistor T2, the two nodes have the same potential, and the node A(B) becomes due to the coupling effect of the storage capacitor C1:

由(1-2)可以得出，发光阶段流过发光元件OLED的电流为：It can be concluded from (1-2) that the current flowing through the light-emitting element OLED in the light-emitting phase is:

其中，μ_n、C_ox、W、L分别为驱动晶体管T1的有效迁移率、单位面积栅电容、沟道宽度和沟道长度。从(1-3)可以看出，最终流过发光元件OLED的电流与驱动晶体管T1的阈值电压以及OLED本身的阈值电压都无关，从而本示例的像素电路可以很好的补偿显示的不均匀性。Wherein, μ _n , C _ox , W, and L are the effective mobility, the gate capacitance per unit area, the channel width, and the channel length of the driving transistor T1, respectively. It can be seen from (1-3) that the current finally flowing through the light-emitting element OLED is independent of the threshold voltage of the driving transistor T1 and the threshold voltage of the OLED itself, so that the pixel circuit of the present example can well compensate the display unevenness. .

需要说明的是，在其它实施例中，当存在多行像素电路并采用同时发光的方式时，则应在各行第二节点B的数据电压V_DATA写入完成后，发光控制信号V_EM第二有效电平才到来。It should be noted that, in other embodiments, when there are multiple rows of pixel circuits and adopt the manner of simultaneous illumination, the illumination control signal V _{EM should be} second after the writing of the data voltage V _{DATA of the} second node B of each row is completed. The effective level is coming.

本实施例的优点是，电路结构简单，只有三个晶体管和一个存储电容，可以增加像素开口率，能够减小发光元件OLED的电流密度，提高发光元件OLED使用寿命；电路采用充电式的阈值提取方式，即源跟随器结构，对于正负阈值都有补偿作用，所以这种方法对于采用耗尽型的晶体管同样有效；并且，在其它实施例中，当电路采用同时发光的驱动模式时，在3D显示中可以有效避免串扰的影响，此外，在初始化和阈值补偿过程中，电路在发光元件OLED的阳极输入一低电平，此低电平可以有效延长发光元件OLED的使用寿命。The advantage of this embodiment is that the circuit structure is simple, only three transistors and one storage capacitor can increase the pixel aperture ratio, can reduce the current density of the OLED of the light-emitting element, and improve the service life of the OLED of the light-emitting element; the circuit adopts the threshold extraction of the charging type The mode, that is, the source follower structure, has a compensating effect on the positive and negative thresholds, so this method is also effective for a depletion type transistor; and, in other embodiments, when the circuit adopts a simultaneous illumination driving mode, In the 3D display, the influence of crosstalk can be effectively avoided. In addition, in the initialization and threshold compensation process, the circuit inputs a low level at the anode of the light emitting element OLED, and this low level can effectively extend the service life of the light emitting element OLED.

需要说明的是，当各晶体管采用P型薄膜晶体管时，请参考图1b，其驱动过程与图1a的驱动过程相同，不同之处在于：各晶体管导通的有效电平为低电平V_L；在初始化阶段，第二电平端VSS提供高电平，向第三节点C(发光元件OLED的阴极)充电至高电平。 It should be noted that when each transistor adopts a P-type thin film transistor, please refer to FIG. 1b, and the driving process is the same as the driving process of FIG. 1a, except that the effective level of each transistor is low level V _{L .} In the initialization phase, the second level terminal VSS supplies a high level to charge the third node C (the cathode of the light emitting element OLED) to a high level.

实施例二：Embodiment 2:

实施例一中，第三节点C的初始化电位通过第一电平端VDD或第二电平端VSS提供，本实施例与上述实施例不同之处在于，本实施例公开的像素电路中还包括第四晶体管T4，以向第三节点C提供相应的电位。请参考图3a和图3b，为本实施例公开的一种像素电路结构图。In the first embodiment, the initialization potential of the third node C is provided by the first level terminal VDD or the second level terminal VSS. The difference between the embodiment and the embodiment is that the pixel circuit disclosed in the embodiment further includes the fourth Transistor T4 is to supply a corresponding potential to the third node C. Please refer to FIG. 3a and FIG. 3b, which are structural diagrams of a pixel circuit disclosed in this embodiment.

第四晶体管T4的第一极连接至第三节点C，第四晶体管T4的第二极用于输入初始化电位，第四晶体管T4的控制极用于输入初始化控制信号V_Ini。在初始化阶段，第四晶体管T4响应初始化控制信号V_Ini的有效电平导通，第四晶体管T4的第二极向第三节点C传输第四晶体管T4的第二极输入的初始化电位。The first pole of the fourth transistor T4 is connected to the third node C, the second pole of the fourth transistor T4 is used to input the initialization potential, and the gate of the fourth transistor T4 is used to input the initialization control signal V _Ini . In the initialization phase, the fourth transistor T4 is turned on in response to the active level of the initialization control signal V _Ini , and the second electrode of the fourth transistor T4 transmits the initialization potential of the second polarity input of the fourth transistor T4 to the third node C.

需要说明的是，当驱动晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4为N型薄膜晶体管时，请参考图3a，第四晶体管T4的第二极输入的初始化电位为低电平V_L，初始化控制信号V_Ini的有效电平为高电平V_H。当驱动晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4为P型薄膜晶体管时，请参考图3b，第四晶体管T4的第二极输入的初始化电位为高电平V_H，初始化控制信号V_Ini的有效电平为低电平V_L。It should be noted that when the driving transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are N-type thin film transistors, please refer to FIG. 3a, the initializing potential of the second polarity input of the fourth transistor T4 is low. The level V _L , the active level of the initialization control signal V _Ini is a high level V _H . When the driving transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are P-type thin film transistors, please refer to FIG. 3b, the initializing potential of the second polarity input of the fourth transistor T4 is a high level _VH , The active level of the initialization control signal V _Ini is a low level V _L .

以图3a为例，请参考图4，为图3a所示像素电路驱动过程的时序图。该像素电路的驱动过程与实施例一的驱动过程大致相同，依次包括：初始化阶段、阈值补偿阶段、数据写入阶段和发光阶段，不同之处在于初始化阶段，第三节点C的低电平V_L由第四晶体管T4的第二极提供而不是由第一电平端VDD提供，其余皆驱动过程和实施例一的驱动过程相同，此处不再赘述。Taking FIG. 3a as an example, please refer to FIG. 4, which is a timing diagram of the pixel circuit driving process shown in FIG. 3a. The driving process of the pixel circuit is substantially the same as the driving process of the first embodiment, and includes: an initialization phase, a threshold compensation phase, a data writing phase, and an illumination phase, respectively, except that the initialization phase, the low level V of the third node C _{L is} provided by the second pole of the fourth transistor T4 instead of the first level terminal VDD, and the rest of the driving process is the same as that of the first embodiment, and details are not described herein again.

需要说明的是，由于第三节点C的初始化电位为低电平V_L，因此，第四晶体管T4的第二极可以连接至第二电平端VSS，请参考图5a，由第二电平端VSS向第四晶体管T4的第二极提供低电平V_L的初始化电位。It should be noted that, since the initialization potential of the third node C is a low level V _L , the second electrode of the fourth transistor T4 can be connected to the second level terminal VSS. Please refer to FIG. 5a, and the second level terminal VSS. An initialization potential of a low level V _L is supplied to the second electrode of the fourth transistor T4.

当然，当采用图3b所示的像素电路即各晶体管为P型薄膜晶体管时，初始化控制信号V_Ini的有效电平为低电平V_L，第四晶体管T4的第二极提供的初始化电位为高电平V_H。此时，第四晶体管T4的第二极可以连接至第一电平端VDD，请参考图5b，由第一电平端VDD向第四晶体管T4的第二极提供高电平V_H的初始化电位。 Of course, when the pixel circuit shown in FIG. 3b is used, that is, each transistor is a P-type thin film transistor, the active level of the initialization control signal V _Ini is a low level V _L , and the initial potential provided by the second electrode of the fourth transistor T4 is High level V _H . At this time, the second pole of the fourth transistor T4 may be connected to the first level terminal VDD. Referring to FIG. 5b, the initial potential of the high level V _H is supplied from the first level terminal VDD to the second electrode of the fourth transistor T4.

相比实施例一，本实施例的优点在于第一电平端VDD或者第二电平端VSS为恒定的高电平V_H或者低电平V_L，不需要输出初始化电位。当第一电平端VDD或者第二电平端VSS为恒定电位时，时序控制更易实现。Compared with the first embodiment, the advantage of this embodiment is that the first level terminal VDD or the second level terminal VSS is a constant high level V _H or a low level V _L , and it is not necessary to output an initializing potential. Timing control is easier to implement when the first level terminal VDD or the second level terminal VSS is at a constant potential.

实施例三：Embodiment 3:

请参考图6a和图6b，为本实施例公开的像素电路结构图，与上述实施例不同之处在于，第四晶体管T4的第二极用于耦合至数据线DATA，第四晶体管T4第二极的初始化电位由数据线DATA提供。Referring to FIG. 6a and FIG. 6b, the structure of the pixel circuit disclosed in the embodiment is different from the above embodiment in that the second transistor of the fourth transistor T4 is used for coupling to the data line DATA, and the fourth transistor T4 is second. The initialization potential of the pole is provided by the data line DATA.

请参考图7，为本实施例图6a所示像素电路的驱动时序图，本实施例像素电路的驱动过程和实施例二的驱动过程大体相同，不同之处在于，在初始化阶段，第三节点C的初始化电位(例如低电平V_L)由数据线DATA提供，在阈值补偿阶段和数据写入阶段，数据线DATA则向第三晶体管T3分别提供参考电位V_REF和数据电压V_DATA。Please refer to FIG. 7 , which is a driving sequence diagram of the pixel circuit shown in FIG. 6 a of the present embodiment. The driving process of the pixel circuit in this embodiment is substantially the same as the driving process of the second embodiment, except that in the initialization phase, the third node is The initialization potential of C (e.g., low level V _L ) is supplied from the data line DATA. In the threshold compensation phase and the data writing phase, the data line DATA supplies the reference potential V _REF and the data voltage V _DATA to the third transistor T3, respectively.

图6a所示的具体工作过程为：The specific working process shown in Figure 6a is:

在初始化阶段时，初始化控制信号V_Ini变为有效电平高电平，将第四晶体管T4置于导通状态，扫描信号V_Scan和发光控制信号V_EM也同时处于有效电平高电平，晶体管T2和T3处于导通状态，数据线DATA上的初始化电位低电平V_L同时通过晶体管T4写入到第三节点C中，通过晶体管T3和T2写入到第一节点A和第二节点B中，使三个节点A、B和C的电位同处于低电平V_L。In the initialization phase, the initialization control signal V _Ini becomes the active level high level, the fourth transistor T4 is placed in the on state, and the scan signal V _Scan and the illumination control signal V _EM are also at the active level high level. transistors T2 and T3 in the conductive state, the initialization potential on the data line dATA is written to the low level V _L while the third node C through transistor T4, a is written to the first node and the second node through the transistors T3 and T2 In B, the potentials of the three nodes A, B, and C are at the same low level V _L .

在阈值补偿阶段时，初始化控制信号V_Ini变为低电平V_L，使第四晶体管T4处于截止状态。扫描信号V_Scan和发光控制信号V_EM继续处于有效电平高电平，数据线DATA输出参考电位V_REF，此参考电位通过晶体管T3和T2输入到节点A和B，使得节点A和B电平为V_REF。第一电平端VDD通过驱动晶体管T1给节点C充电。其余驱动过程和实施例二相同，此处不再赘述。In the threshold compensation phase, the initialization control signal V _Ini becomes a low level V _L , causing the fourth transistor T4 to be in an off state. The scan signal V _Scan and the light emission control signal V _EM continue to be at the active level high level, and the data line DATA outputs the reference potential V _REF , which is input to the nodes A and B through the transistors T3 and T2, so that the node A and B levels Is V _REF . The first level terminal VDD charges the node C through the driving transistor T1. The rest of the driving process is the same as that of the second embodiment, and details are not described herein again.

相比于实施例二，本实施示例的优点在于少了一根向第四晶体管T4第二极提供初始化电位的电源线，减少了工艺复杂度，简化了结构。Compared with the second embodiment, the advantage of this embodiment is that a power supply line that supplies an initializing potential to the second electrode of the fourth transistor T4 is omitted, which reduces the process complexity and simplifies the structure.

需要说明的是，对于图6b所示的像素电路，其驱动过程与图6a的驱动过程原理相似，不同之处在于，图6b所示像素电路的有效电平为低电平，初始化电位为高电平。在此不再赘述。It should be noted that, for the pixel circuit shown in FIG. 6b, the driving process is similar to the driving process of FIG. 6a, except that the effective level of the pixel circuit shown in FIG. 6b is low level, and the initializing potential is high. Level. I will not repeat them here.

实施例四： Embodiment 4:

请参考图8a和图8b，为本实施例公开的像素电路结构图，与上述实施例不同之处在于，第四晶体管T4的控制极连接至第四晶体管T4的第一极；在初始化阶段，第四晶体管T4的控制极所输入的初始化控制信号V_Ini的有效电平由第四晶体管T4的第一极提供。Referring to FIG. 8a and FIG. 8b, the structure of the pixel circuit disclosed in the embodiment is different from the above embodiment in that the control electrode of the fourth transistor T4 is connected to the first pole of the fourth transistor T4; in the initialization phase, The active level of the initialization control signal V _Ini input by the gate of the fourth transistor T4 is supplied from the first electrode of the fourth transistor T4.

请参考图9，为本实施例图8a所示电路的驱动过程时序图，本实施例像素电路的驱动过程与实施例二的驱动过程大致相同，不同之处在于初始化阶段第三节点C电位的提供方式和阈值补偿阶段第四晶体管T4的关闭方式。Please refer to FIG. 9 , which is a timing diagram of the driving process of the circuit shown in FIG. 8 a according to the embodiment. The driving process of the pixel circuit in this embodiment is substantially the same as the driving process of the second embodiment, except that the potential of the third node C in the initialization phase is The mode of supply and the manner in which the fourth transistor T4 is turned off in the threshold compensation phase.

具体工作过程为：在初始化阶段，第四晶体管T4第二极输入的电位Vx为初始化电位例如低电平，此时，由于第四晶体管T4的控制极连接至其第一极，于是通过二级管连接方式的第四晶体管T4对第三节点C进行放电，从而将第三节点C电位拉低，完成第三节点C电位的初始化。在阈值补偿阶段及后续阶段，第四晶体管T4第二极输入的电位Vx变为高电平，使第四晶体管T4处于截止状态。其余驱动过程和实施例二相同，此处不再赘述。The specific working process is: in the initialization phase, the potential Vx of the second pole input of the fourth transistor T4 is an initializing potential, for example, a low level. At this time, since the control electrode of the fourth transistor T4 is connected to the first pole thereof, then the second level is passed. The fourth transistor T4 of the tube connection mode discharges the third node C, thereby pulling the potential of the third node C low, and completing the initialization of the potential of the third node C. In the threshold compensation phase and the subsequent phase, the potential Vx of the second pole input of the fourth transistor T4 becomes a high level, and the fourth transistor T4 is turned off. The rest of the driving process is the same as that of the second embodiment, and details are not described herein again.

相比于实施例二，本实施示例的优点在于少了一根电源线，减少了工艺复杂度，简化了结构。Compared with the second embodiment, the advantage of this embodiment is that one power line is missing, the process complexity is reduced, and the structure is simplified.

需要说明的是，对于图8b所示的像素电路，其驱动过程与图8a的驱动过程原理相似，不同之处在于，图8b所示像素电路的有效电平为低电平，初始化电位为高电平。在此不再赘述。It should be noted that, for the pixel circuit shown in FIG. 8b, the driving process is similar to the driving process of FIG. 8a, except that the effective level of the pixel circuit shown in FIG. 8b is low level, and the initializing potential is high. Level. I will not repeat them here.

实施例五：Embodiment 5:

请参考图10a和图10b，为本实施例公开的一种像素电路结构图，与上述实施例不同之处在于，本实施例公开的像素电路中还包括第五晶体管T5，第一节点A所需的参考电位V_REF由第五晶体管T5传输，数据线DATA则只提供数据信号V_DATA，从而简化了数据线DATA的时序控制。具体地，像素电路包括：用于串联在第一电平端VDD和第二电平端VSS之间的驱动晶体管T1和发光元件OLED，以及第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和存储电容C1。其中，图10a所示的像素电路中，各晶体管(驱动晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4和第五晶体管T5)为N型薄膜晶体管；图10b所示的像素电路中，各晶体管(驱动晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4和第五晶体管T5)为P型薄膜晶体管。 Referring to FIG. 10a and FIG. 10b, a structure diagram of a pixel circuit disclosed in the embodiment is different from the above embodiment in that the pixel circuit disclosed in this embodiment further includes a fifth transistor T5, and the first node A is The required reference potential V _REF is transmitted by the fifth transistor T5, and the data line DATA provides only the data signal V _DATA , thereby simplifying the timing control of the data line DATA. Specifically, the pixel circuit includes: a driving transistor T1 and a light emitting element OLED for connecting in series between the first level terminal VDD and the second level terminal VSS, and a second transistor T2, a third transistor T3, a fourth transistor T4, and a Five transistors T5 and storage capacitor C1. In the pixel circuit shown in FIG. 10a, each transistor (the driving transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5) is an N-type thin film transistor; the pixel shown in FIG. 10b In the circuit, each of the transistors (the driving transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5) is a P-type thin film transistor.

驱动晶体管T1的第一极连接至发光元件OLED的第一端形成第三节点C，驱动晶体管T1的第二极和发光元件OLED的第二端分别用于连接至第一电平端VDD和第二电平端VSS。在一种实施例中，请参考图10a，发光元件OLED的第一端为阳极，发光元件OLED的第二端为阴极；驱动晶体管T1的第二极用于连接至第一电平端VDD，发光元件OLED的第二端用于连接至第二电平端VSS。在另一种实施例中，请参考图10b，发光元件OLED的第一端为阴极，发光元件OLED的第二端为阳极；驱动晶体管T1的第二极用于连接至第二电平端VSS，发光元件OLED的第二端用于连接至第一电平端VDD。The first end of the driving transistor T1 is connected to the first end of the light emitting element OLED to form a third node C, and the second end of the driving transistor T1 and the second end of the light emitting element OLED are respectively connected to the first level terminal VDD and the second Level terminal VSS. In one embodiment, referring to FIG. 10a, the first end of the light emitting element OLED is an anode, the second end of the light emitting element OLED is a cathode, and the second end of the driving transistor T1 is used to connect to the first level terminal VDD, and emits light. The second end of the element OLED is for connection to the second level terminal VSS. In another embodiment, referring to FIG. 10b, the first end of the light emitting element OLED is a cathode, the second end of the light emitting element OLED is an anode, and the second end of the driving transistor T1 is used to be connected to the second level terminal VSS. The second end of the light emitting element OLED is for connection to the first level terminal VDD.

第三晶体管T3的第二极用于连接至数据线DATA，在具体实施例中，数据线DATA用于提供数据信号V_DATA，第三晶体管T3的控制极用于输入扫描信号V_Scan。The second pole of the third transistor T3 is for connection to the data line DATA. In a particular embodiment, the data line DATA is used to provide the data signal V _DATA and the gate of the third transistor T3 is used to input the scan signal V _Scan .

第五晶体管T5的第一极连接至第一节点A，第五晶体管T5的第二极用于输入参考电位V_REF，第五晶体管T5的控制极连接至第三晶体管T3的控制极。The first pole of the fifth transistor T5 is connected to the first node A, the second pole of the fifth transistor T5 is for inputting the reference potential V _REF , and the gate of the fifth transistor T5 is connected to the gate of the third transistor T3.

第四晶体管T4的第一极连接至第三节点C，第四晶体管T4的第二极用于输入初始化电位，第四晶体管T4的控制极用于输入初始化控制信号V_Ini。The first pole of the fourth transistor T4 is connected to the third node C, the second pole of the fourth transistor T4 is used to input the initialization potential, and the gate of the fourth transistor T4 is used to input the initialization control signal V _Ini .

在具体实施例中，像素电路依次工作于第一阶段、第二阶段和第三阶段。在本实施例中，第一阶段为初始化阶段，第二阶段可以依次包括阈值补偿阶段和数据写入阶段，第三阶段为发光阶段。In a particular embodiment, the pixel circuits operate in a first phase, a second phase, and a third phase in sequence. In this embodiment, the first phase is an initialization phase, and the second phase may include a threshold compensation phase and a data writing phase in sequence, and the third phase is an illumination phase.

在第一阶段，第四晶体管T4响应初始化控制信号V_Ini的有效电平导通初始化第三节点C的电位；或者，优选地，在第一阶段，第二晶体管T2还响应发光控制信号V_EM的第一有效电平导通初始化第一节点A和第二节点B的电位，并且，发光控制信号V_EM的第一有效电平结束时间早于初始化控制信号V_Ini的有效电平结束时间。In the first stage, the fourth transistor T4 is turned on to initialize the potential of the third node C in response to the active level of the initialization control signal V _Ini ; or, preferably, in the first phase, the second transistor T2 is further responsive to the illumination control signal V _EM The first active level is turned on to initialize the potentials of the first node A and the second node B, and the first active level end time of the light emission control signal V _EM is earlier than the active level end time of the initialization control signal V _Ini .

在第二阶段，第五晶体管T5和第三晶体管T3响应扫描信号V_Scan的有效电平导通，导通的第五晶体管T5向第一节点A传输参考电位 V_REF，导通的第三晶体管T3向第二节点B传输数据信号V_DATA；驱动晶体管T1在其控制极电位(例如栅极电位，对应第一节点A的电位)V_REF的作用下导通，导通的驱动晶体管T1会传输第一电平端VDD或者第二电平端VSS的电信号以调整(可以是充电，也可以是放电)第三节点C的电位，直到该节点C的电位调整为V_REF-V_TH时，驱动晶体管T1则进入截止状态，此时，第三节点C的电位就会维持为V_REF-V_TH，该电位通过存储电容C1存储，其中，V_TH为驱动晶体管T1的阈值电压。在第三阶段，第二晶体管T2响应发光控制信号V_EM的第二有效电平导通，驱动晶体管T1响应第一节点A的电位导通驱动发光元件OLED发光。In the second phase, the fifth transistor T5 and the third transistor T3 are turned on in response to the active level of the scan signal _VScan , and the turned-on fifth transistor T5 transmits the reference potential V _REF to the first node A, and the turned-on third transistor T3 transmits the data signal V _DATA to the second node B; the driving transistor T1 is turned on by its control potential (for example, the gate potential, corresponding to the potential of the first node A) V _REF , and the turned-on driving transistor T1 transmits The electrical signal of the first level terminal VDD or the second level terminal VSS is adjusted (may be charged or discharged) to the potential of the third node C until the potential of the node C is adjusted to V _REF -V _TH , the driving transistor T1 enters an off state. At this time, the potential of the third node C is maintained at V _REF -V _TH , and the potential is stored by the storage capacitor C1, wherein V _TH is the threshold voltage of the driving transistor T1. In the third stage, the second transistor T2 is turned on in response to the second active level of the light emission control signal V _EM , and the driving transistor T1 is driven to emit light in response to the potential of the first node A to drive the light emitting element OLED.

需要说明的是，在一种实施例中，请参考图10a，发光控制信号V_EM有效电平(包括第一有效电平和第二有效电平)、初始化控制信号V_Ini的有效电平和扫描信号V_Scan的有效电平均为高电平；在另一种实施例中，请参考图10b，发光控制信号V_EM的有效电平(包括第一有效电平和第二有效电平)、初始化控制信号V_Ini的有效电平和扫描信号V_Scan的有效电平均为低电平。It should be noted that, in an embodiment, referring to FIG. 10a, the illuminating control signal V _EM active level (including the first active level and the second active level), the active level of the initialization control signal V _Ini , and the scan signal The effective level of V _Scan is high level; in another embodiment, please refer to FIG. 10b, the active level of the illumination control signal V _EM (including the first active level and the second active level), and the initialization control signal. The active level of V _{Ini and} the active level of the scan signal V _Scan are both low.

在本实施例中，初始化控制信号V_Ini、扫描信号V_Scan的有效电平和发光控制信号V_EM的第二有效电平依次到来。In the present embodiment, the initialization control signal V _Ini , the effective level of the scan signal V _Scan , and the second active level of the light emission control signal V _EM sequentially come.

由于初始化控制信号V_Ini的有效电平超前于扫描信号V_Scan的有效电平到来时间，因此，当存在多行像素电路，并逐行发光时，第四晶体管T4控制极所输入的初始化控制信号V_Ini可以优选由上一级像素电路的扫描信号V_Scan提供，即本行像素电路第四晶体管T4控制极可以优选耦合至上一行像素电路第三晶体管T3的控制极。Since the effective level of the initialization control signal V _Ini leads the effective level arrival time of the scan signal V _Scan , when there are a plurality of rows of pixel circuits and emits light row by row, the fourth transistor T4 controls the initialization control signal input by the pole V _Ini may preferably be provided by the scan signal V _{Scan of the} upper level pixel circuit, that is, the control electrode of the fourth transistor T4 of the pixel circuit of the current row may be preferably coupled to the gate electrode of the third transistor T3 of the previous row of pixel circuits.

下文以图10a为例对本实施例公开的像素电路驱动过程予以说明。本实施例的像素电路驱动过程分为初始化阶段、阈值补偿阶段、数据写入阶段和发光阶段，如图11所示为本实施例的信号时序，结合图11和图10a具体描述本实施例的驱动过程。The pixel circuit driving process disclosed in this embodiment will be described below by taking FIG. 10a as an example. The pixel circuit driving process of this embodiment is divided into an initialization phase, a threshold compensation phase, a data writing phase, and an illuminating phase. As shown in FIG. 11 , the signal timing of the embodiment is described in detail with reference to FIG. 11 and FIG. 10 a . Drive process.

在初始化阶段：初始化控制信号V_Ini为有效电平高电平，将第四晶体管T4置于导通状态，第四晶体管T4的第二极输入初始化电位低电平V_L，并通过导通的第四晶体管T4写入到第三节点C中。于是，第三节点C的电位降为初始化电位低电平V_L，在存储电容C1的耦合下，第二节点B的电位也拉低。在优选的实施例中，在刚进入初始化阶段时，发光控制信号V_EM可以为有效电平高电平，在进入初始化阶段延迟一段时间之后，发光控制信号V_EM变为低电平。在发光控制信号V_EM为有效电平高电平时，第三节点C可以通过存储电容C1的耦合作用将第一节点A和第二节点B的电位拉低，拉低第一节点A的电位可以防止有大电流流过发光元件OLED。In the initialization phase: the initialization control signal V _Ini is at an active level high level, the fourth transistor T4 is placed in an on state, and the second transistor input of the fourth transistor T4 is initialized to a potential low level V _L and is turned on. The fourth transistor T4 is written to the third node C. Thus, the potential of the third node C drops to the initialization potential low level V _L , and the potential of the second node B is also pulled low under the coupling of the storage capacitor C1. In a preferred embodiment, the lighting control signal V _EM may be at an active level high level just after entering the initialization phase, and the lighting control signal V _EM becomes a low level after a delay in the initialization phase. When the light emission control signal V _EM is at an active level high level, the third node C can pull down the potentials of the first node A and the second node B by the coupling action of the storage capacitor C1, and pull down the potential of the first node A. A large current is prevented from flowing through the light emitting element OLED.

在数据写入和阈值补偿阶段：初始化控制信号V_Ini变为低电平，使第四晶体管T4处于截止状态；扫描信号V_Scan变为有效电平高电平，使晶体管T3和T5处于导通状态，第五晶体管T5第二极输入的参考电位V_REF通过导通的第五晶体管T5写入到第一节点A中，数据线DATA提供的数据电压V_DATA通过第三晶体管T3写入到第二节点B中。与此同时，驱动晶体管T1处于导通状态，第一电平端VDD通过驱动晶体管T1给第三节点C充电，因此，第三节点C的电位会慢慢升高，直到它升高到V_REF-V_TH的时候，驱动晶体管T1会进入截止状态，第三节点C的电位就会维持为V_REF-V_TH。其中V_TH为驱动晶体管T1的阈值电压。数据输入和阈值补偿阶段结束后，驱动晶体管T1的阈值电压信息就通过存储电容C1被存储到节点C上。需要注意的是，V_REF-V_TH小于发光元件OLED的阈值电压，以保证发光元件OLED在该两个阶段不发光。In the data writing and threshold compensation phase: the initialization control signal V _Ini becomes a low level, causing the fourth transistor T4 to be in an off state; the scan signal V _Scan becomes an active level high level, causing the transistors T3 and T5 to be turned on In the state, the reference potential V _{REF of the} second transistor input of the fifth transistor T5 is written into the first node A through the turned-on fifth transistor T5, and the data voltage V _DATA supplied from the data line DATA is written to the third transistor T3. Two nodes B. At the same time, the driving transistor T1 is in an on state, and the first level terminal VDD charges the third node C through the driving transistor T1, so that the potential of the third node C gradually rises until it rises to V _REF - At V _TH , the driving transistor T1 enters an off state, and the potential of the third node C is maintained at V _REF -V _TH . Where V _TH is the threshold voltage of the driving transistor T1. After the data input and threshold compensation phases are completed, the threshold voltage information of the driving transistor T1 is stored to the node C through the storage capacitor C1. It should be noted that V _REF —V _{TH is} smaller than the threshold voltage of the light-emitting element OLED to ensure that the light-emitting element OLED does not emit light in the two stages.

在发光阶段：扫描信号V_Scan变为低电平，使晶体管T3和T5处于截止状态；发光控制信号V_EM变为有效电平高电平，使得第二晶体管T2处于导通状态，此时，发光元件OLED开始发光，并且第三节点C的电位也变为V_OLED。V_OLED为发光元件OLED在发光时阳极的电位。此时，由于第二节点B和第一节点A通过第二晶体管T2耦合连接，两节点电位相同，节点A(B)由于存储电容C1的耦合作用而变为：In the light-emitting phase: the scan signal V _Scan becomes a low level, so that the transistors T3 and T5 are in an off state; the light-emission control signal V _EM becomes an active level high level, so that the second transistor T2 is in an on state, at this time, The light emitting element OLED starts to emit light, and the potential of the third node C also becomes V _OLED . The V _OLED is the potential of the anode of the light-emitting element OLED when it emits light. At this time, since the second node B and the first node A are coupled and coupled by the second transistor T2, the two nodes have the same potential, and the node A(B) becomes due to the coupling effect of the storage capacitor C1:

VnodeA＝V_OLED+V_DATA-V_REF+V_TH …(4-1)VnodeA=V _OLED +V _DATA -V _REF +V _TH ...(4-1)

由(4-1)可以得出，发光阶段流过OLED的电流为：From (4-1), it can be concluded that the current flowing through the OLED during the illumination phase is:

其中，μ_n、C_ox、W、L分别为驱动晶体管T1的有效迁移率、单位面积栅电容、沟道宽度和沟道长度。从(4-2)可以看出，最终流过发光元件OLED的电流与驱动晶体管T1的阈值电压以及发光元件OLED本身的阈值电压都无关，从而本示例的像素电路可以很好的补偿显示的不均匀性。Wherein, μ _n , C _ox , W, and L are the effective mobility, the gate capacitance per unit area, the channel width, and the channel length of the driving transistor T1, respectively. It can be seen from (4-2) that the current finally flowing through the light-emitting element OLED is independent of the threshold voltage of the driving transistor T1 and the threshold voltage of the light-emitting element OLED itself, so that the pixel circuit of the present example can well compensate for the display. Uniformity.

对于具有多行像素电路的实例中，可以优选采用传统的逐行扫描发光模式，第一电平端VDD是一个恒定电位，各行的扫描信号V_Scan不需要在某一时刻同时输出高电平或者低电平脉冲。For an example with a plurality of rows of pixel circuits, a conventional progressive scan illumination mode may be preferred, the first level terminal VDD is a constant potential, and the scan signals V _{Scan of} each row do not need to simultaneously output a high level or a low level at a certain time. Level pulse.

需要说明的是，当各晶体管采用P型薄膜晶体管时，请参考图10b，其驱动过程与图10a的驱动过程相同，不同之处在于：各晶体管导通的有效电平为低电平V_L；在初始化阶段，第四晶体管T4的第二极提供高电平，向第三节点C(发光元件OLED的阴极)充电至高电平V_H。It should be noted that when each transistor adopts a P-type thin film transistor, please refer to FIG. 10b, and the driving process is the same as the driving process of FIG. 10a, except that the effective level of each transistor is low level V _{L .} In the initialization phase, the second electrode of the fourth transistor T4 supplies a high level to charge the third node C (the cathode of the light emitting element OLED) to a high level V _H .

相对于上述实施例，本实施例增加了像素电路驱动时所需的信号线，有利于时序控制。Compared with the above embodiment, the present embodiment increases the signal lines required for driving the pixel circuit, which is advantageous for timing control.

本实施例还公开了一种显示电路驱动方法，显示电路采用上述实施例的像素电路，像素电路的每一驱动周期包括初始化阶段、阈值补偿阶段、数据写入阶段和发光阶段，驱动方法包括：The embodiment further discloses a display circuit driving method. The display circuit adopts the pixel circuit of the above embodiment. Each driving cycle of the pixel circuit includes an initialization phase, a threshold compensation phase, a data writing phase, and an illumination phase. The driving method includes:

在初始化阶段，第二晶体管T2导通，分别初始化存储电容C1两端的电位和驱动晶体管T1控制极的电位。在其它实施例中，还可以导通第四晶体管T4，辅助初始化存储电容C1两端的电位。In the initialization phase, the second transistor T2 is turned on to initialize the potential across the storage capacitor C1 and the potential of the control transistor T1, respectively. In other embodiments, the fourth transistor T4 can also be turned on to assist in initializing the potential across the storage capacitor C1.

在阈值补偿阶段，第三晶体管T3和/或第五晶体管T5导通，向驱动晶体管T1控制极提供参考电位，读取驱动晶体管T1的阈值电压信息并通过存储电容C1存储。在一种实施例中，可以通过第三晶体管T3提供参考电位；在另一种实施例中，也可以通过第五晶体管T5提供参考电位。In the threshold compensation phase, the third transistor T3 and/or the fifth transistor T5 are turned on, the reference potential is supplied to the gate of the driving transistor T1, the threshold voltage information of the driving transistor T1 is read and stored by the storage capacitor C1. In one embodiment, the reference potential can be provided by the third transistor T3; in another embodiment, the reference potential can also be provided by the fifth transistor T5.

在数据写入阶段，第三晶体管T3导通传输数据电压V_DATA并存储于存储电容C1。In the data writing phase, the third transistor T3 turns on the transmission data voltage V _DATA and stores it in the storage capacitor C1.

需要说明的是，在具体实施例中，阈值补偿阶段和数据写入阶段也可以同时进行，譬如同时导通第三晶体管T3和第五晶体管T5，由第五晶体管T5提供参考电位，由第三晶体管T3传输数据电压V_DATA，从而实现了驱动晶体管T1阈值电压补偿和数据电压V_DATA写入的同时进行。It should be noted that, in a specific embodiment, the threshold compensation phase and the data writing phase may also be performed simultaneously, for example, simultaneously turning on the third transistor T3 and the fifth transistor T5, and providing the reference potential by the fifth transistor T5, by the third The transistor T3 transmits the data voltage V _DATA , thereby achieving simultaneous operation of the threshold voltage compensation of the driving transistor T1 and the writing of the data voltage V _DATA .

在发光阶段，第一晶体管T1根据存储电容C1两端的压差驱动产生驱动电流，并驱动发光元件OLED发光。In the light emitting phase, the first transistor T1 drives the driving current according to the voltage difference across the storage capacitor C1, and drives the light emitting element OLED to emit light.

实施例六：Example 6:

本实施例还公开了一种显示装置，请参考图12，为本实施例还公开的显示装置结构原理图，该显示装置包括： The present embodiment also discloses a display device. Referring to FIG. 12, a schematic structural diagram of a display device is also disclosed. The display device includes:

显示面板100，显示面板100包括排列成n行m列矩阵的上述实施例提供的像素电路Pixel[1][1]……Pixel[n][m]，其中，n和m为大于0的整数，Pixel[n][m]表征第n行m列的像素电路；与每个像素相连的第一方向(例如横向)的多条扫描线Gate[1]……Gate[n]，其中，Gate[n]表示第n行像素电路对应的扫描线，用于向提供向本行像素电路提供扫描控制信号，例如初始化控制信号V_Ini、扫描信号V_Scan、发光控制信号V_EM等；和第二方向(例如纵向)的多条数据线Data[1]……Data[m]，其中，Data[m]表示第m列像素电路对应的数据线，用于提供各像素电路的数据电压V_DATA。显示面板可以是液晶显示面板、有机发光显示面板、电子纸显示面板等，而对应的显示装置可以是液晶显示器、有机发光显示器、电子纸显示器等。需要说明的是，在其它实施例中，像素电路所需的有些扫描控制信号也可以通过全局线的方式来提供，比如第一电平端所需的电源线、初始化控制信号V_Ini所需的初始化控制线、阈值提取控制线和发光控制线等，本领域技术人员可以依据具体像素电路的需求来调整。The display panel 100 includes the pixel circuits Pixel[1][1]...Pixel[n][m] provided by the above embodiments arranged in a matrix of n rows and m columns, where n and m are integers greater than 0. , Pixel[n][m] represents a pixel circuit of the nth row and m columns; a plurality of scan lines Gate[1]...Gate[n] in a first direction (for example, a lateral direction) connected to each pixel, wherein, Gate [n] represents a scan line corresponding to the pixel circuit of the nth row, for providing a scan control signal to the pixel circuit of the line, for example, an initialization control signal V _Ini , a scan signal V _Scan , a light emission control signal V _{EM ,} etc.; and a second A plurality of data lines Data[1]...Data[m] in a direction (for example, a vertical direction), wherein Data[m] represents a data line corresponding to the m-th column pixel circuit for providing a data voltage V _{DATA of} each pixel circuit. The display panel may be a liquid crystal display panel, an organic light emitting display panel, an electronic paper display panel, or the like, and the corresponding display device may be a liquid crystal display, an organic light emitting display, an electronic paper display, or the like. It should be noted that, in other embodiments, some scan control signals required by the pixel circuit may also be provided by a global line, such as a power line required for the first level terminal, and an initialization required for initializing the control signal V _Ini . The control line, the threshold extraction control line, the illumination control line, and the like can be adjusted by those skilled in the art according to the requirements of the specific pixel circuit.

栅极驱动电路200，用于产生扫描脉冲信号，并通过沿第一方向形成的各行扫描线Gate[1]……Gate[n]向像素电路提供所需的控制信号。The gate driving circuit 200 is configured to generate a scan pulse signal and supply a desired control signal to the pixel circuit through the respective scan lines Gate[1]...Gate[n] formed along the first direction.

数据驱动电路300，数据驱动电路300的信号输出端耦合到显示面板100中与其对应的数据线Data[1]……Data[m]上，数据驱动电路300产生的数据电压信号V_DATA通过数据线Data[1]……Data[m]传输到对应的像素单元内以实现图像灰度。The data driving circuit 300, the signal output end of the data driving circuit 300 is coupled to the corresponding data lines Data[1]...Data[m] in the display panel 100, and the data voltage signal V _DATA generated by the data driving circuit 300 passes through the data line. Data[1]...Data[m] is transferred to the corresponding pixel unit to achieve image gray scale.

控制器400，控制器400用于向栅极驱动电路和数据驱动电路提供控制时序。The controller 400 is configured to provide control timing to the gate driving circuit and the data driving circuit.

以上应用了具体个例对本发明进行阐述，只是用于帮助理解本发明，并不用以限制本发明。对于本发明所属技术领域的技术人员，依据本发明的思想，还可以做出若干简单推演、变形或替换。 The invention has been described above with reference to specific examples, which are merely intended to aid the understanding of the invention and are not intended to limit the invention. For the person skilled in the art to which the invention pertains, several simple derivations, variations or substitutions can be made in accordance with the inventive concept.

Claims

一种像素电路，其特征在于，包括：A pixel circuit, comprising:

用于串联在第一电平端(VDD)和第二电平端(VSS)之间的驱动晶体管(T1)和发光元件(OLED)，以及第二晶体管(T2)、第三晶体管(T3)和存储电容(C1)；Driving transistor (T1) and light emitting element (OLED) connected in series between a first level terminal (VDD) and a second level terminal (VSS), and a second transistor (T2), a third transistor (T3), and a memory Capacitor (C1);

驱动晶体管(T1)的第一极连接至发光元件(OLED)的第一端形成第三节点(C)，驱动晶体管(T1)的第二极和发光元件(OLED)的第二端分别用于连接至第一电平端(VDD)和第二电平端(VSS)；The first end of the driving transistor (T1) is connected to the first end of the light emitting element (OLED) to form a third node (C), and the second end of the driving transistor (T1) and the second end of the light emitting element (OLED) are respectively used for Connected to a first level terminal (VDD) and a second level terminal (VSS);

驱动晶体管(T1)的控制极连接至第二晶体管(T2)的第一极形成第一节点(A)，第二晶体管(T2)的第二极连接至第三晶体管(T3)的第一极形成第二节点(B)，第二晶体管(T2)的控制极用于输入发光控制信号(V_EM)；The first pole of the driving transistor (T1) whose control electrode is connected to the second transistor (T2) forms a first node (A), and the second pole of the second transistor (T2) is connected to the first pole of the third transistor (T3) Forming a second node (B), the gate of the second transistor (T2) is used to input an illumination control signal (V _EM );

第三晶体管(T3)的第二极用于连接至用于提供数据信号(V_DATA)或者参考电位(V_REF)的数据线(DATA)，第三晶体管(T3)的控制极用于输入扫描信号(V_Scan)；The second pole of the third transistor (T3) is for connection to a data line (DATA) for providing a data signal (V _DATA ) or a reference potential (V _REF ), and the gate of the third transistor (T3) is used for input scanning Signal (V _Scan );

存储电容(C1)连接至第二节点(B)和第三节点(C)之间。The storage capacitor (C1) is connected between the second node (B) and the third node (C).
如权利要求1所述的像素电路，其特征在于，The pixel circuit of claim 1 wherein:

在第一阶段，第二晶体管(T2)和第三晶体管(T3)分别响应发光控制信号(V_EM)的第一有效电平和扫描信号(V_Scan)的第一有效电平导通，向第一节点(A)和第二节点(B)传输参考电位(V_REF)初始化第一节点(A)和第二节点(B)的电位，通过相应的信号源向第三节点(C)提供初始化电位，并读取驱动晶体管(T1)的阈值电压(V_TH)；In the first stage, the second transistor (T2) and the third transistor (T3) are respectively turned on in response to the first active level of the light emission control signal (V _EM ) and the first active level of the scan signal (V _Scan ), A node (A) and a second node (B) transmit a reference potential (V _REF ) to initialize the potentials of the first node (A) and the second node (B), and provide initialization to the third node (C) through the corresponding signal source. Potential, and reading the threshold voltage (V _TH ) of the driving transistor (T1);

在第二阶段，第二晶体管(T2)由发光控制信号(V_EM)控制在截止状态，第三晶体管(T3)响应扫描信号(V_Scan)的第二有效电平导通向第二节点(B)传输数据信号(V_DATA)；In the second phase, the second transistor (T2) is controlled to be in an off state by an illumination control signal (V _EM ), and the third transistor (T3) is turned on to the second node in response to a second active level of the scan signal (V _Scan ) ( B) transmitting a data signal (V _DATA );

在第三阶段，第三晶体管(T3)由扫描信号(V_Scan)控制在截止状态，第二晶体管(T2)响应发光控制信号(V_EM)的第二有效电平导通，驱动晶体管(T1)响应第一节点(A)的电位导通驱动发光元件(OLED)发光。In the third stage, the third transistor (T3) is controlled to be in an off state by a scan signal ( _VScan ), and the second transistor (T2) is turned on in response to a second active level of the light emission control signal (V _EM ) to drive the transistor (T1) The light-emitting element (OLED) in response to the potential conduction of the first node (A) emits light.
如权利要求2所述的像素电路，其特征在于，所述第一阶段依次包括：初始化阶段和阈值补偿阶段；The pixel circuit according to claim 2, wherein said first phase comprises: an initialization phase and a threshold compensation phase;

驱动晶体管(T1)的第二极用于连接至第一电平端(VDD)，发光元件(OLED)的第二端用于连接至第二电平端(VSS)；在初始化阶段，驱动晶体管(T1)的第二极传输第一电平端(VDD)的初始化电位初始化第三节点(C)的电位；在阈值补偿阶段，驱动晶体管(T1)的第二极传输第一电平端(VDD)的有效电平，存储电容(C1)根据第二节点(B)的电位和第三节点(C)的电位读取驱动晶体管(T1)的阈值电压(V_TH)；或者，The second pole of the driving transistor (T1) is for connecting to the first level terminal (VDD), the second terminal of the light emitting element (OLED) is for connecting to the second level terminal (VSS); during the initialization phase, the driving transistor (T1) The second pole transmits an initial potential of the first level terminal (VDD) to initialize the potential of the third node (C); in the threshold compensation phase, the second pole of the driving transistor (T1) transmits the first level terminal (VDD) effective Level, the storage capacitor (C1) reads the threshold voltage (V _TH ) of the driving transistor (T1) according to the potential of the second node (B) and the potential of the third node (C); or

驱动晶体管(T1)的第二极用于连接至第二电平端(VSS)，发光元件(OLED)的第二端用于连接至第一电平端(VDD)；在初始化阶段，驱动晶体管(T1)的第二极传输第二电平端(VSS)的初始化电位初始化第三节点(C)的电位；在阈值补偿阶段，驱动晶体管(T1)的第二极传输第二电平端(VSS)的有效电平，存储电容(C1)根据第二节点(B)的电位和第三节点(C)的电位读取驱动晶体管(T1)的阈值电压(V_TH)。The second pole of the driving transistor (T1) is for connecting to the second level terminal (VSS), the second end of the light emitting element (OLED) is for connecting to the first level terminal (VDD); during the initialization phase, the driving transistor (T1) The second pole of the second level terminal (VSS) initializes the potential of the third node (C); in the threshold compensation phase, the second pole of the driving transistor (T1) transmits the second level terminal (VSS) effective The level, storage capacitor (C1) reads the threshold voltage (V _TH ) of the driving transistor (T1) according to the potential of the second node (B) and the potential of the third node (C).
如权利要求2所述的像素电路，其特征在于，还包括第四晶体管(T4)，所述第一阶段依次包括：初始化阶段和阈值补偿阶段；The pixel circuit according to claim 2, further comprising a fourth transistor (T4), wherein said first phase comprises: an initialization phase and a threshold compensation phase;

第四晶体管(T4)的第一极连接至第三节点(C)，第四晶体管(T4)的第二极用于输入初始化电位，第四晶体管(T4)的控制极用于输入初始化控制信号(V_Ini)；The first pole of the fourth transistor (T4) is connected to the third node (C), the second pole of the fourth transistor (T4) is used for inputting the initialization potential, and the gate of the fourth transistor (T4) is used for inputting the initialization control signal (V _Ini );

在初始化阶段，第四晶体管(T4)响应初始化控制信号(V_Ini)的有效电平导通，向第三节点(C)传输第四晶体管(T4)的第二极输入的初始化电位。In the initialization phase, the fourth transistor (T4) is turned on in response to the active level of the initialization control signal (V _Ini ), and the initialization potential of the second pole input of the fourth transistor (T4) is transmitted to the third node (C).
如权利要求4所述的像素电路，其特征在于，驱动晶体管(T1)、第二晶体管(T2)、第三晶体管(T3)和第四晶体管(T4)为N型薄膜晶体管；The pixel circuit according to claim 4, wherein the driving transistor (T1), the second transistor (T2), the third transistor (T3), and the fourth transistor (T4) are N-type thin film transistors;

驱动晶体管(T1)的第二极用于连接至第一电平端(VDD)，发光元件(OLED)的第二端用于连接至第二电平端(VSS)；The second pole of the driving transistor (T1) is for connecting to the first level terminal (VDD), and the second end of the light emitting element (OLED) is for connecting to the second level terminal (VSS);

第四晶体管(T4)的第二极连接至第二电平端(VSS)，在初始化阶段，第四晶体管(T4)的第二极输入的初始化电位由第二电平端(VSS)提供；或者，The second electrode of the fourth transistor (T4) is connected to the second level terminal (VSS). In the initialization phase, the initialization potential of the second polarity input of the fourth transistor (T4) is provided by the second level terminal (VSS); or

第四晶体管(T4)的第二极用于连接至数据线(DATA)，在初始化阶段，第四晶体管(T4)的第二极输入的初始化电位由数据线(DATA)提供。 The second pole of the fourth transistor (T4) is for connection to a data line (DATA), and in the initialization phase, the initialization potential of the second pole input of the fourth transistor (T4) is provided by the data line (DATA).
如权利要求4所述的像素电路，其特征在于，驱动晶体管(T1)、第二晶体管(T2)、第三晶体管(T3)和第四晶体管(T4)为P型薄膜晶体管；The pixel circuit according to claim 4, wherein the driving transistor (T1), the second transistor (T2), the third transistor (T3), and the fourth transistor (T4) are P-type thin film transistors;

驱动晶体管(T1)的第二极用于连接至第二电平端(VSS)，发光元件(OLED)的第二端用于连接至第一电平端(VDD)；The second pole of the driving transistor (T1) is for connecting to the second level terminal (VSS), and the second end of the light emitting element (OLED) is for connecting to the first level terminal (VDD);

第四晶体管(T4)的第二极连接至第一电平端(VDD)，在初始化阶段，第四晶体管(T4)的第二极输入的初始化电位由第一电平端(VDD)提供；或者，The second electrode of the fourth transistor (T4) is connected to the first level terminal (VDD). In the initialization phase, the initialization potential of the second polarity input of the fourth transistor (T4) is provided by the first level terminal (VDD); or

第四晶体管(T4)的第二极用于连接至数据线(DATA)，在初始化阶段，第四晶体管(T4)的第二极输入的初始化电位由数据线(DATA)提供。The second pole of the fourth transistor (T4) is for connection to a data line (DATA), and in the initialization phase, the initialization potential of the second pole input of the fourth transistor (T4) is provided by the data line (DATA).
如权利要求4-6任意一项所述的像素电路，其特征在于，第四晶体管(T4)的控制极连接至第四晶体管(T4)的第一极；在初始化阶段，第四晶体管(T4)的控制极所输入的初始化控制信号(V_Ini)的有效电平由第四晶体管(T4)的第一极提供。A pixel circuit according to any one of claims 4-6, wherein the control electrode of the fourth transistor (T4) is connected to the first electrode of the fourth transistor (T4); in the initialization phase, the fourth transistor (T4) The active level of the initialization control signal (V _Ini ) input by the gate is supplied by the first pole of the fourth transistor (T4).
一种像素电路，其特征在于，包括：A pixel circuit, comprising:

用于串联在第一电平端(VDD)和第二电平端(VSS)之间的驱动晶体管(T1)和发光元件(OLED)，以及第二晶体管(T2)、第三晶体管(T3)、第四晶体管(T4)、第五晶体管(T5)和存储电容(C1)；a driving transistor (T1) and a light emitting element (OLED) connected in series between a first level terminal (VDD) and a second level terminal (VSS), and a second transistor (T2), a third transistor (T3), Four transistors (T4), fifth transistors (T5), and storage capacitors (C1);

驱动晶体管(T1)的第一极连接至发光元件(OLED)的第一端形成第三节点(C)，驱动晶体管(T1)的第二极和发光元件(OLED)的第二端分别用于连接至第一电平端(VDD)和第二电平端(VSS)；The first end of the driving transistor (T1) is connected to the first end of the light emitting element (OLED) to form a third node (C), and the second end of the driving transistor (T1) and the second end of the light emitting element (OLED) are respectively used for Connected to a first level terminal (VDD) and a second level terminal (VSS);

驱动晶体管(T1)的控制极连接至第二晶体管(T2)的第一极形成第一节点(A)，第二晶体管(T2)的第二极连接至第三晶体管(T3)的第一极形成第二节点(B)，第二晶体管(T2)的控制极用于输入发光控制信号(V_EM)；The first pole of the driving transistor (T1) whose control electrode is connected to the second transistor (T2) forms a first node (A), and the second pole of the second transistor (T2) is connected to the first pole of the third transistor (T3) Forming a second node (B), the gate of the second transistor (T2) is used to input an illumination control signal (V _EM );

第三晶体管(T3)的第二极用于连接至用于提供数据信号(V_DATA)的数据线(DATA)，第三晶体管(T3)的控制极用于输入扫描信号(V_Scan)；A third transistor (T3) for connection to a second electrode for providing a data signal (V _DATA) of the data line (DATA), the third control transistor (T3) of the scan electrode for inputting a signal (V _Scan);

第五晶体管(T5)的第一极连接至第一节点(A)，第五晶体管(T5)的第二极用于输入参考电位(V_REF)，第五晶体管(T5)的控制极连接至第三晶体管(T3)的控制极；a first transistor of the fifth transistor (T5) is connected to the first node (A), a second electrode of the fifth transistor (T5) is used for inputting a reference potential (V _REF ), and a control electrode of the fifth transistor (T5) is connected to a control electrode of the third transistor (T3);

第四晶体管(T4)的第一极连接至第三节点(C)，第四晶体管(T4) 的第二极用于输入初始化电位，第四晶体管(T4)的控制极用于输入初始化控制信号(V_Ini)；The first pole of the fourth transistor (T4) is connected to the third node (C), the second pole of the fourth transistor (T4) is used for inputting the initialization potential, and the gate of the fourth transistor (T4) is used for inputting the initialization control signal (V _Ini );

存储电容(C1)连接至第二节点(B)和第三节点(C)之间。The storage capacitor (C1) is connected between the second node (B) and the third node (C).
如权利要求8所述的像素电路，其特征在于，The pixel circuit of claim 8 wherein:

在第一阶段，第四晶体管(T4)响应初始化控制信号(V_Ini)的有效电平导通初始化第三节点(C)的电位；或者，在第一阶段，第二晶体管(T2)还响应发光控制信号(V_EM)的第一有效电平导通初始化第一节点(A)和第二节点(B)的电位，发光控制信号(V_EM)的第一有效电平结束时间早于初始化控制信号(V_Ini)的有效电平结束时间；In the first stage, the fourth transistor (T4) is turned on to initialize the potential of the third node (C) in response to the active level of the initialization control signal (V _Ini ); or, in the first phase, the second transistor (T2) is also responsive The first active level of the illumination control signal (V _EM ) is turned on to initialize the potentials of the first node (A) and the second node (B), and the first active level end time of the illumination control signal (V _EM ) is earlier than the initialization The effective level end time of the control signal (V _Ini );

在第二阶段，第五晶体管(T5)和第三晶体管(T3)响应扫描信号(V_Scan)的有效电平导通，导通的第五晶体管(T5)向第一节点(A)传输参考电位(V_REF)，导通的第三晶体管(T3)向第二节点(B)传输数据信号(V_DATA)；存储电容(C1)根据第一节点(A)的电位读取驱动晶体管(T1)的阈值电压(V_TH)；In the second stage, the fifth transistor (T5) and the third transistor (T3) are turned on in response to the active level of the scan signal ( _VScan ), and the turned-on fifth transistor (T5) transmits the reference to the first node (A). Potential (V _REF ), the turned-on third transistor (T3) transmits a data signal (V _DATA ) to the second node (B); the storage capacitor (C1) reads the driving transistor according to the potential of the first node (A) (T1) Threshold voltage (V _TH );

在第三阶段，第二晶体管(T2)响应发光控制信号(V_EM)的第二有效电平导通，驱动晶体管(T1)响应第一节点(A)的电位导通驱动发光元件(OLED)发光；In the third stage, the second transistor (T2) is turned on in response to the second active level of the light emission control signal (V _EM ), and the driving transistor (T1) is turned on in response to the potential of the first node (A) to drive the light emitting element (OLED). Illuminate

初始化控制信号(V_Ini)、扫描信号(V_Scan)的有效电平和发光控制信号(V_EM)的第二有效电平依次到来。The initialization control signal (V _Ini ), the active level of the scan signal (V _Scan ), and the second active level of the illumination control signal (V _EM ) are sequentially applied.
如权利要求9所述的像素电路，其特征在于，第四晶体管(T4)控制极所输入的初始化控制信号(V_Ini)由上一级像素电路的扫描信号(V_Scan)提供。The pixel circuit according to claim 9, wherein the initialization control signal (V _Ini ) input to the gate of the fourth transistor (T4) is supplied from a scan signal (V _Scan ) of the pixel circuit of the previous stage.
一种显示装置，其特征在于，包括：A display device, comprising:

像素电路矩阵，所述像素电路矩阵包括排列成n行m列矩阵的如权利要求1-10任意一项所述的像素电路，所述n和m为大于0的整数；a pixel circuit matrix, the pixel circuit matrix comprising the pixel circuit according to any one of claims 1 to 10 arranged in a matrix of n rows and m columns, wherein n and m are integers greater than 0;

栅极驱动电路，用于产生扫描脉冲信号，并通过沿第一方向形成的各行扫描线向像素电路提供所需的控制信号；a gate driving circuit for generating a scan pulse signal and providing a desired control signal to the pixel circuit through each row of scan lines formed along the first direction;

数据驱动电路，用于产生代表灰度信息的数据电压信号，并通过沿第二方向形成的各数据线向像素电路提供数据信号；a data driving circuit for generating a data voltage signal representing gray scale information, and providing a data signal to the pixel circuit through each data line formed along the second direction;

控制器，用于向栅极驱动电路和数据驱动电路提供控制时序。A controller for providing control timing to the gate drive circuit and the data drive circuit.
一种像素电路驱动方法，其特征在于，所述像素电路的每一驱动周期包括初始化阶段、阈值补偿阶段、数据写入阶段和发光阶段，所述驱动方法包括：A pixel circuit driving method, wherein each driving cycle of the pixel circuit includes an initialization phase, a threshold compensation phase, a data writing phase, and an illumination phase, The driving methods include:

在所述初始化阶段，第二晶体管(T2)导通，分别初始化存储电容(C1)两端的电位和驱动晶体管(T1)控制极的电位；In the initialization phase, the second transistor (T2) is turned on to initialize the potential across the storage capacitor (C1) and the potential of the control transistor (T1) control terminal;

在所述阈值补偿阶段，第三晶体管(T3)和/或第五晶体管(T5)导通，向驱动晶体管(T1)控制极提供参考电位，读取驱动晶体管(T1)的阈值电压信息并通过存储电容(C1)存储；In the threshold compensation phase, the third transistor (T3) and/or the fifth transistor (T5) are turned on, providing a reference potential to the control transistor (T1) control electrode, reading the threshold voltage information of the driving transistor (T1) and passing Storage capacitor (C1) storage;

在所述数据写入阶段，第三晶体管(T3)导通传输数据电压V_DATA并存储于存储电容(C1)；In the data writing phase, the third transistor (T3) turns on the transmission data voltage V _DATA and stores it in the storage capacitor (C1);

在所述发光阶段，第一晶体管(T1)根据存储电容(C1)两端的压差驱动产生驱动电流，并驱动发光元件(OLED)发光。 In the light-emitting phase, the first transistor (T1) drives a drive current according to a voltage difference across the storage capacitor (C1) and drives the light-emitting element (OLED) to emit light.