WO2016116005A1 - 相位处理方法及装置 - Google Patents

相位处理方法及装置 Download PDF

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Publication number
WO2016116005A1
WO2016116005A1 PCT/CN2016/070903 CN2016070903W WO2016116005A1 WO 2016116005 A1 WO2016116005 A1 WO 2016116005A1 CN 2016070903 W CN2016070903 W CN 2016070903W WO 2016116005 A1 WO2016116005 A1 WO 2016116005A1
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Prior art keywords
phase
data signal
disturbance
offset
optical power
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PCT/CN2016/070903
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English (en)
French (fr)
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张理维
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中兴通讯股份有限公司
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Publication of WO2016116005A1 publication Critical patent/WO2016116005A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/50—Transmitters
    • H04B10/516—Details of coding or modulation
    • H04B10/548—Phase or frequency modulation
    • H04B10/556—Digital modulation, e.g. differential phase shift keying [DPSK] or frequency shift keying [FSK]

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  • the present invention relates to the field of communications, and in particular to a phase processing method and apparatus.
  • the RZ clock In a system of optical transmission clock modulation (for example, RZ clock modulation), in order to maintain the best transmission performance of the system, the RZ clock is aligned with the center of the data signal to be transmitted.
  • RZ clock modulation for example, RZ clock modulation
  • the alignment state of the RZ clock signal and the data signal will deviate from the alignment state, resulting in deterioration of transmission performance, for example, edge jitter causes RZ data signal eye diagram Compression, the transmission side optical power detection error increases.
  • the present invention provides a phase processing method and apparatus to at least solve the problem of deterioration in transmission performance due to misalignment of a clock signal and a data signal existing in the related art.
  • a phase processing method comprising: adding a phase disturbance of a predetermined amplitude to a data signal; and controlling the data signal and the clock signal to perform phase alignment processing according to the phase disturbance.
  • the phase disturbance comprises positive perturbation and/or negative perturbation.
  • performing phase alignment processing on the data signal and the clock signal according to the phase disturbance comprises: adding a predetermined number of phase offsets on the data signal during a period of the phase disturbance; collecting corresponding to the a voltage of the phase-shifted optical power; determining a target phase offset added to the data signal according to the collected voltage of the optical power; controlling the data signal and the clock signal to perform phase by using the target phase offset Align processing.
  • determining, according to the collected voltage of the optical power, the target phase offset added to the data signal comprises: selecting a phase offset when the collected optical power is zero or a phase difference from zero is less than a predetermined threshold; Determining the selected phase offset is the target phase offset.
  • the data signal is a four-phase relative in a zero-to-four phase relative phase shift keying RZ-DQPSK system Phase shift keying DQPSK data.
  • a phase processing apparatus comprising: an adding module configured to add a phase disturbance of a predetermined amplitude to a data signal; a control module configured to control the data signal according to the phase disturbance and The clock signal is phase aligned.
  • the phase disturbance comprises positive perturbation and/or negative perturbation.
  • control module includes: an adding unit, configured to add a predetermined number of phase offsets on the data signal during a period of the phase disturbance; and an acquiring unit configured to collect corresponding to the phase offset a voltage of the shifted optical power; a determining unit configured to determine a target phase offset added to the data signal according to the collected voltage of the optical power; and a control unit configured to control the phase shift using the target
  • the data signal and the clock signal are phase aligned.
  • the determining unit includes: a selecting subunit, configured to select a phase offset when the collected optical power is zero or a phase difference from zero is less than a predetermined threshold; determining a subunit, configured to determine the selected phase The offset is the phase offset of the destination.
  • the data signal is four phase relative phase shift keyed DQPSK data in a zero-to-four phase relative phase shift keyed RZ-DQPSK system.
  • a phase disturbance of a predetermined amplitude is added to the data signal; and the phase alignment processing is performed according to the phase disturbance to control the data signal and the clock signal, thereby solving the problem that the clock signal and the data signal are not aligned due to the related art.
  • the performance of the transmission performance is degraded, thereby achieving the effect of achieving alignment of the clock signal and the data signal.
  • FIG. 1 is a flow chart of a phase processing method according to an embodiment of the present invention.
  • FIG. 2 is a block diagram showing the structure of a phase processing apparatus according to an embodiment of the present invention.
  • FIG. 3 is a block diagram showing the structure of a control module 24 in a phase processing device according to an embodiment of the present invention
  • FIG. 4 is a block diagram showing the structure of the determining unit 36 in the phase processing apparatus according to an embodiment of the present invention.
  • FIG. 5 is a transmission block diagram of an RZ-DQPSK system according to an embodiment of the present invention.
  • FIG. 6 is a detailed block diagram of transmission of an RZ-DQPSK system in accordance with an embodiment of the present invention.
  • Figure 7 is an eye diagram of a monitoring point in accordance with an embodiment of the present invention.
  • FIG. 8a is a monitoring eye diagram 1 of a phase mismatch in an RZ-DQPSK system according to an embodiment of the present invention
  • 8b is a second embodiment of a monitoring point in phase mismatch in an RZ-DQPSK system according to an embodiment of the present invention.
  • FIG. 8c is a third embodiment of a monitoring point in the phase mismatch in the RZ-DQPSK system according to an embodiment of the present invention.
  • FIG. 9 is a diagram showing relationship between phase shift and light output power according to an embodiment of the present invention.
  • FIG. 10 is a block diagram showing the principle of a clock data phase shift controller according to an embodiment of the present invention.
  • FIG. 11 is a timing diagram of a perturbation cycle in accordance with an embodiment of the present invention.
  • FIG. 12 is a timing diagram of a clock data phase shift controller in accordance with an embodiment of the present invention.
  • FIG. 13 is a block diagram showing a control structure of a MUX phase display lookup table LUT according to an embodiment of the present invention.
  • FIG. 1 is a flowchart of a phase processing method according to an embodiment of the present invention. As shown in FIG. 1, the process includes the following steps:
  • Step S102 adding a phase disturbance of a predetermined amplitude to the data signal
  • Step S104 performing phase alignment processing according to the phase disturbance control data signal and the clock signal.
  • the phase alignment processing is performed on the data signal and the clock signal by adding a phase disturbance in the data signal, thereby solving the problem that the transmission performance is degraded due to misalignment of the clock signal and the data signal existing in the related art, thereby achieving The effect of aligning the clock signal and the data signal is achieved.
  • phase disturbances described above may be of various types.
  • positive perturbations may be added or negative perturbations may be added when phase disturbance is added.
  • phase alignment processing according to the phase disturbance control data signal and the clock signal, a plurality of manners may be adopted.
  • the phase may be processed in the following manner: in the phase of the phase disturbance, in the data signal Adding a predetermined number of phase offsets; collecting a voltage corresponding to the optical power of the phase offset; determining a target phase offset added to the data signal according to the voltage of the collected optical power; using the target phase offset control data
  • the signal and clock signals are phase aligned.
  • determining the target phase offset added to the data signal according to the collected voltage of the optical power may adopt a scheme of: selecting a phase offset when the collected optical power is zero or a phase difference from zero is less than a predetermined threshold; determining the selected phase The offset is the target phase offset. That is, when the optical power is zero or close to zero, the phase of the data signal and the clock signal are aligned, and therefore, the characteristic can be utilized to determine the phase offset that causes the phase of the data signal and the clock signal to be aligned.
  • the above technical solution can be applied to a plurality of systems.
  • the above technical solution can be applied to a zero-quadrature phase-shift keyed RZ-DQPSK system, and the data signal is Four-phase relative phase shift keying DQPSK data in the RZ-DQPSK system.
  • a phase processing device is also provided, which is used to implement the above-mentioned embodiments and preferred embodiments, and has not been described again.
  • the term "module” may implement a combination of software and/or hardware of a predetermined function.
  • the apparatus described in the following embodiments is preferably implemented in software, hardware, or a combination of software and hardware, is also possible and contemplated.
  • FIG. 2 is a block diagram showing the structure of a phase processing apparatus according to an embodiment of the present invention. As shown in FIG. 2, the apparatus includes an adding module 22 and a control module 24. The apparatus will be described below.
  • the adding module 22 is arranged to add a phase disturbance of a predetermined amplitude to the data signal; the control module 24 is connected to the adding module 22, and is arranged to perform phase alignment processing on the data signal and the clock signal according to the phase disturbance.
  • phase disturbance described above may include positive perturbation and/or negative perturbation.
  • control module 24 includes an adding unit 32, an acquiring unit 34, a determining unit 36, and a control unit 38.
  • the device control module 24 will be described below.
  • the adding unit 32 is arranged to add a predetermined number of phase offsets on the data signal during the period of the phase disturbance;
  • the collecting unit 34 is connected to the adding unit 32, and is configured to collect the voltage corresponding to the optical power of the phase shift a determining unit 36, coupled to the collecting unit 34, configured to determine a target phase offset added to the data signal according to the voltage of the collected optical power;
  • the control unit 38 is coupled to the determining unit 36, and configured to utilize the target phase
  • the offset control data signal and the clock signal are phase aligned.
  • the determining unit 36 includes a selecting subunit 42 and a determining subunit 44.
  • the determining unit 36 will be described below. .
  • the selecting subunit 42 is arranged to select a phase offset when the collected optical power is zero or a phase difference from zero is less than a predetermined threshold; the determining subunit 44 is connected to the selecting subunit 42 and is set to determine the selected phase offset. Phase offset.
  • the data signal may be four-phase relative phase shift keying DQPSK data in a zero-to-four phase relative phase shift keying RZ-DQPSK system.
  • a method and an implementation device for automatically controlling the alignment of the RZ clock and the transmission data are also proposed in the embodiment of the present invention.
  • the DQPSK system is taken as an example to explain the present invention.
  • the phase relationship between the RZ clock and the transmitted data can be automatically aligned according to the change caused by the perturbation.
  • the RZ clock phase is fixed, and only the phase shift of the data signal is added, which has little effect on the jitter of the RZ optical signal.
  • FIG. 5 is a transmission block diagram of an RZ-DQPSK system according to an embodiment of the present invention
  • FIG. 6 is a detailed block diagram of transmission of an RZ-DQPSK system according to an embodiment of the present invention.
  • Output port phase end, cancellation end.
  • the phase end output is the RZ-DQPSK signal
  • the light output of the cancellation end is connected to the backlight monitoring diode MPD to generate a photocurrent proportional to the light output intensity.
  • FIG. 6 includes three related optical signal detection points A, B, and C, wherein the A point is used for the DQPSK modulator to output the DQPSK optical signal, and the B point is the DQPSK for the RZ modulation.
  • the phase end of the device, point C is the cancellation output of the RZ modulator.
  • Fig. 7, is an eye diagram of a monitoring point according to an embodiment of the present invention.
  • FIG. 8a is a monitoring eye diagram of a phase mismatch in an RZ-DQPSK system according to an embodiment of the present invention.
  • FIG. 8b is a monitoring eye diagram 2 and FIG. 8c of a phase mismatch in an RZ-DQPSK system according to an embodiment of the present invention.
  • It is a monitoring point eye diagram 3 in the case of phase mismatch in the RZ-DQPSK system according to the embodiment of the present invention, wherein the uppermost picture in FIG. 8a, FIG. 8b, and FIG. 8c is a schematic diagram of the data clock alignment state, and the middle figure is the constructive The end output photo eye diagram, the bottommost diagram is the destructive end output eye diagram.
  • FIG. 9 is a relationship diagram of phase shift and light output power according to an embodiment of the present invention.
  • FIG. 9 shows clock data mismatch and RZ phase. The relationship between the average optical power after normalization.
  • the device that controls the alignment of the data clock is the optical power minimum point lock controller.
  • FIG. 10 is a block diagram showing the clock data phase shifting controller according to an embodiment of the present invention.
  • the phase dither produces an optical power perturbation that causes a slight change in the Vtz of the MPD output.
  • the Auto-zero loop will eliminate the DC level of Vtz's stable DC signal, only amplifying the phase micro
  • the Auto-zero loop is disabled during the time slice of the perturbation signal, and the loop is enabled between positive and negative perturbations, ie, when the non-perturbative time slice is enabled.
  • the clock data alignment controller samples the Ts sampling period plus the voltage Va of the MPD output after the perturbation, and the clock phase correlation detector averages the Ns positive perturbations to produce an average positive perturbation PHp, and averages Ns negative perturbations. Average negative perturbation PHn.
  • the integrator updates the enable output according to the three different voltage state inputs described below.
  • the step size of the clock phase perturbation is set by Kdf.
  • the forward phase offset is added to the phase shifters of data I, Q, which produces a positive phase shift of IQ data relative to the RZ clock. Then set a suitable delay, so that the high gain amplifier in the figure is configured, Va is acquired, PHp is updated, the control loop is removed from the forward phase offset, and the Auto-zero loop restores Va to zero.
  • the negative phase shift is added to the phase shifters of data I, Q, which produces a negative phase shift of IQ data relative to the RZ clock. Then set a suitable delay so that the high gain amplifier in the figure is configured, Va is acquired, PHn is updated, the control loop is removed from the negative phase offset, and the Auto-zero loop restores Va to zero.
  • FIG. 11 is a timing diagram of a perturbation period according to an embodiment of the present invention
  • FIG. 12 is a timing diagram of a clock data phase shift controller according to an embodiment of the present invention.
  • the correlation detector SD is Ns positive.
  • the phase offset and the Ns negative phase offset sample values are averaged to produce an error signal for Vdiff, and then the error signal value is symbolized.
  • the clock data phase shift integrator obtains the symbolized error signal and enables the output, and simultaneously updates the phase value of IQ.
  • FIG. 13 is a block diagram of a control structure of a MUX phase display lookup table LUT according to an embodiment of the present invention. As shown in FIG. 13, a method of clock and data phase shifting is different in different MUXs, so the phase of the clock data offset controller is executed. The manner of movement is also different. In the practice of the present invention, a lookup table can be used to convert the output of the clock data phase shift controller to the phase change of IQ.
  • the present invention effectively solves the problem that the clock signal and the data signal are not correct.
  • the problem of deterioration of transmission performance leads to the alignment of the clock signal and the data signal.
  • modules or steps of the present invention described above can be implemented by a general-purpose computing device that can be centralized on a single computing device or distributed across a network of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein.
  • the steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps thereof are fabricated as a single integrated circuit module.
  • the invention is not limited to any specific combination of hardware and software.
  • the phase processing method and apparatus provided by the embodiments of the present invention have the following beneficial effects: solving the problem that the transmission performance is degraded due to misalignment of the clock signal and the data signal existing in the related art, thereby achieving the realization of the clock signal.
  • the effect of aligning with the data signal is described above.

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Abstract

本发明提供了一种相位处理方法及装置，其中，该方法包括：在数据信号上添加预定幅度的相位扰动；根据上述相位扰动控制数据信号和时钟信号进行相位对齐处理，通过本发明，解决了相关技术中存在的由于时钟信号和数据信号未对齐导致传输性能劣化的问题，进而达到了实现时钟信号和数据信号对齐的效果。

Description

相位处理方法及装置 技术领域
本发明涉及通信领域，具体而言，涉及一种相位处理方法及装置。
背景技术
在光传输的时钟调制方式(例如：RZ时钟调制方式)的***中，为了保持***最好的传输性能，RZ时钟要和所要传输的数据信号中心对齐。但是，在实际应用中，由于温度变化和输出波长在不同波道内切换，RZ时钟信号和数据信号中心对齐状态会偏离对准状态，从而导致传输性能劣化，例如：边沿抖动引起RZ数据信号眼图压缩，发送侧出光功率检测误差加大。
针对相关技术中存在的由于时钟信号和数据信号未对齐导致传输性能劣化的问题，目前尚未提出有效的解决方案。
发明内容
本发明提供了一种相位处理方法及装置，以至少解决相关技术中存在的由于时钟信号和数据信号未对齐导致传输性能劣化的问题。
根据本发明的一个方面，提供了一种相位处理方法，包括：在数据信号上添加预定幅度的相位扰动；根据所述相位扰动控制所述数据信号和时钟信号进行相位对齐处理。
可选地，所述相位扰动包括正微扰和/或负微扰。
可选地，根据所述相位扰动控制所述数据信号和时钟信号进行相位对齐处理包括：在所述相位扰动的周期内，在所述数据信号上添加预定数量的相位偏移；采集对应于所述相位偏移的光功率的电压；根据采集的所述光功率的电压确定添加到所述数据信号上的目的相位偏移；利用所述目的相位偏移控制所述数据信号和时钟信号进行相位对齐处理。
可选地，根据采集的所述光功率的电压确定添加到所述数据信号上的目的相位偏移包括：选择采集的所述光功率为零或与零相差小于预定阈值时的相位偏移；确定选择的所述相位偏移为所述目的相位偏移。
可选地，所述数据信号为归零-四相相对相移键控RZ-DQPSK***中的四相相对 相移键控DQPSK数据。
根据本发明的另一方面，提供了一种相位处理装置，包括：添加模块，设置为在数据信号上添加预定幅度的相位扰动；控制模块，设置为根据所述相位扰动控制所述数据信号和时钟信号进行相位对齐处理。
可选地，所述相位扰动包括正微扰和/或负微扰。
可选地，所述控制模块包括：添加单元，设置为在所述相位扰动的周期内，在所述数据信号上添加预定数量的相位偏移；采集单元，设置为采集对应于所述相位偏移的光功率的电压；确定单元，设置为根据采集的所述光功率的电压确定添加到所述数据信号上的目的相位偏移；控制单元，设置为利用所述目的相位偏移控制所述数据信号和时钟信号进行相位对齐处理。
可选地，所述确定单元包括：选择子单元，设置为选择采集的所述光功率为零或与零相差小于预定阈值时的相位偏移；确定子单元，设置为确定选择的所述相位偏移为所述目的相位偏移。
可选地，所述数据信号为归零-四相相对相移键控RZ-DQPSK***中的四相相对相移键控DQPSK数据。
通过本发明，采用在数据信号上添加预定幅度的相位扰动；根据所述相位扰动控制所述数据信号和时钟信号进行相位对齐处理，解决了相关技术中存在的由于时钟信号和数据信号未对齐导致传输性能劣化的问，进而达到了实现时钟信号和数据信号对齐的效果。
附图说明
此处所说明的附图用来提供对本发明的进一步理解，构成本申请的一部分，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：
图1是根据本发明实施例的相位处理方法的流程图；
图2是根据本发明实施例的相位处理装置的结构框图；
图3是根据本发明实施例的相位处理装置中控制模块24的结构框图；
图4是根据本发明实施例的相位处理装置中确定单元36的结构框图；
图5是根据本发明实施例的RZ-DQPSK***的发送框图；
图6是根据本发明实施例的RZ-DQPSK***的发送的细节框图；
图7是根据本发明实施例的监测点的眼图；
图8a是根据本发明实施例的RZ-DQPSK***中相位失配时的监测点眼图一；
图8b是根据本发明实施例的RZ-DQPSK***中相位失配时的监测点眼图二；
图8c是根据本发明实施例的RZ-DQPSK***中相位失配时的监测点眼图三；
图9是根据本发明实施例的相移和出光功率的关系图；
图10是根据本发明实施例的时钟数据相移控制器原理框图；
图11是根据本发明实施例的微扰周期时序图；
图12是根据本发明实施例的时钟数据相移控制器的时序图；
图13是根据本发明实施例的MUX相位显示查找表LUT控制结构框图。
具体实施方式
下文中将参考附图并结合实施例来详细说明本发明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
在本实施例中提供了一种相位处理方法，图1是根据本发明实施例的相位处理方法的流程图，如图1所示，该流程包括如下步骤：
步骤S102，在数据信号上添加预定幅度的相位扰动；
步骤S104，根据该相位扰动控制数据信号和时钟信号进行相位对齐处理。
通过上述步骤，利用在数据信号中添加相位扰动的方式对数据信号和时钟信号进行相位对齐处理，从而解决了相关技术中存在的由于时钟信号和数据信号未对齐导致传输性能劣化的问题，进而达到了实现时钟信号和数据信号对齐的效果。
并且，上述相位扰动的类型可以为多种类型，在一个可选的实施例中，在进行相位扰动的添加时，可以添加正微扰，也可以添加负微扰。
在根据相位扰动控制数据信号和时钟信号进行相位对齐处理时可以采用多种方式，在一个可选的实施例中，可以采用如下方式进行相位对其处理：在相位扰动的周期内，在数据信号上添加预定数量的相位偏移；采集对应于上述相位偏移的光功率的电压；根据采集的光功率的电压确定添加到上述数据信号上的目的相位偏移；利用该目的相位偏移控制数据信号和时钟信号进行相位对齐处理。
其中，根据采集的上述光功率的电压确定添加到数据信号上的目的相位偏移可以采用如下方案：选择采集的光功率为零或与零相差小于预定阈值时的相位偏移；确定选择的相位偏移为目的相位偏移。即，当光功率为零或接近零时，说明数据信号和时钟信号的相位为对齐的，因此，可以利用该特性确定使得数据信号和时钟信号的相位对齐的相位偏移。
上述技术方案可以应用于多种***中，在一个可选的实施例中，上述的技术方案可以应用于归零-四相相对相移键控RZ-DQPSK***中中，上述数据信号便为该RZ-DQPSK***中的四相相对相移键控DQPSK数据。
在本实施例中还提供了一种相位处理装置，该装置用于实现上述实施例及优选实施方式，已经进行过说明的不再赘述。如以下所使用的，术语“模块”可以实现预定功能的软件和/或硬件的组合。尽管以下实施例所描述的装置较佳地以软件来实现，但是硬件，或者软件和硬件的组合的实现也是可能并被构想的。
图2是根据本发明实施例的相位处理装置的结构框图，如图2所示，该装置包括添加模块22和控制模块24，下面对该装置进行说明。
添加模块22，设置为在数据信号上添加预定幅度的相位扰动；控制模块24，连接至上述添加模块22，设置为根据相位扰动控制上述数据信号和时钟信号进行相位对齐处理。
其中，上述相位扰动可以包括正微扰和/或负微扰。
图3是根据本发明实施例的相位处理装置中控制模块24的结构框图，如图3所示，该控制模块24包括添加单元32、采集单元34、确定单元36和控制单元38。下面对该装置控制模块24进行说明。
添加单元32，设置为在相位扰动的周期内，在数据信号上添加预定数量的相位偏移；采集单元34，连接至上述添加单元32，设置为采集对应于上述相位偏移的光功率的电压；确定单元36，连接在上述采集单元34，设置为根据采集的光功率的电压确定添加到数据信号上的目的相位偏移；控制单元38，连接至上述确定单元36，设置为利用上述目的相位偏移控制数据信号和时钟信号进行相位对齐处理。
图4是根据本发明实施例的相位处理装置中确定单元36的结构框图，如图4所示，该确定单元36包括选择子单元42和确定子单元44，下面对该确定单元36进行说明。
选择子单元42，设置为选择采集的光功率为零或与零相差小于预定阈值时的相位偏移；确定子单元44，连接至上述选择子单元42，设置为确定选择的相位偏移为目的相位偏移。
其中，上述数据信号可以为归零-四相相对相移键控RZ-DQPSK***中的四相相对相移键控DQPSK数据。
针对相关技术中存在的由于时钟信号和数据信号未对齐导致传输性能劣化的问题，在本发明实施例中还提出了一种自动控制RZ时钟和传输数据对齐的方法和实现装置，下面以RZ-DQPSK***为例对本发明进行说明。
本发明实施例是通过在RZ-DQPSK***的DQPSK数据中加入一个微小的相位扰动，RZ时钟和传输数据的相位关系可以依据这个微扰产生的变化实现自动对齐的。在这个方案中，RZ时钟相位是固定的，只给数据信号加相位上的移动，这对RZ光信号的抖动影响很小。
图5是根据本发明实施例的RZ-DQPSK***的发送框图，图6是根据本发明实施例的RZ-DQPSK***的发送的细节框图，如图5、6所示，RZ调制器有两个输出端口：相长端、相消端。相长端输出的是RZ-DQPSK信号，相消端的出光接在背光监测二极管MPD上产生与出光强度成比例的光电流。其中，在图6所示的结构框图中包括三个相关的光信号检测点A点、B点和C点，其中，A点用于DQPSK调制器输出DQPSK光信号，B点为DQPSK在RZ调制器的相长端，C点为RZ调制器的相消端输出。这三个信号在数据时钟对齐点的状态如图7所示，图7是根据本发明实施例的监测点的眼图。
图8a是根据本发明实施例的RZ-DQPSK***中相位失配时的监测点眼图一、图8b是根据本发明实施例的RZ-DQPSK***中相位失配时的监测点眼图二、图8c是根据本发明实施例的RZ-DQPSK***中相位失配时的监测点眼图三，其中，图8a、图8b、图8c中最上边的图是数据时钟对齐状态示意图，中间的图是相长端输出光眼图，最下边的图是相消端输出眼图。
RZ时钟和数据对齐以后，相消端平均光功率值是最小的，图9是根据本发明实施例的相移和出光功率的关系图，在图9中表示的是时钟数据失配和RZ相消端归一化后平均光功率之间的关系图。能控制数据时钟对齐的装置就是光功率最小点锁定控制器。
在初始化过程中，时钟数据相移控制器中积分器会被设置到校准列表中的初始值，在这个位置时钟会出在数据的中心位置附近。当所有发送侧控制环出在锁定状态时，时钟数据控制器开始使能，整个控制框图可以如图10所示，该图10是根据本发明实施例的时钟数据相移控制器原理框图。
在图10中，相位dither产生一个光功率微扰，导致MPD输出的Vtz有微小的变化。Auto-zero环路会把Vtz的稳定直流电信号DC电平消除掉，仅仅放大相位上的微 扰信号，Auto-zero环路在微扰信号的时间片内是禁使能的，在正微扰和负微扰之间环路使能，即在非微扰时间片时是使能的。
时钟数据对齐控制器以Ts采样周期采样加上微扰后MPD输出的电压Va，时钟相位相关检测器将Ns个正微扰做平均产生平均正微扰PHp，将Ns个负微扰做平均产生平均负微扰PHn。根据下述的三种不同的电压状态输入，积分器会更新使能输出。时钟相位微扰的步长由Kdf设置。
Figure PCTCN2016070903-appb-000001
其中，
Figure PCTCN2016070903-appb-000002
在正微扰的周期内，正向相位偏移会加到数据I、Q的相位偏移器中，即产生一个IQ数据相对于RZ时钟的正相移。然后设置一个合适的延时，使得图中高增益放大器配置完毕，采集Va，将PHp更新出来，控制环路再去掉正向相位偏移，Auto-zero环路将Va恢复到零点。
在负微扰的周期内，负向相位偏移会加到数据I、Q的相位偏移器中，即产生一个IQ数据相对于RZ时钟的负相移。然后设置一个合适的延时，使得图中高增益放大器配置完毕，采集Va，将PHn更新出来，控制环路再去掉负向相位偏移，Auto-zero环路将Va恢复到零点。
图11是根据本发明实施例的微扰周期时序图，图12是根据本发明实施例的时钟数据相移控制器的时序图，如图11、12所示，相关检测器SD对Ns个正向相位偏移和Ns个负向相位偏移采样值进行平均后产生Vdiff的误差信号，然后对误差信号数值进行符号化。时钟数据相位偏移积分器得到符号化的误差信号后使能输出，将IQ的phase值同时更新。
图13是根据本发明实施例的MUX相位显示查找表LUT控制结构框图，如图13所示，不同的MUX中时钟和数据相位移动的方法也不一样，所以时钟数据偏移控制器执行的相位移动的方式也不同，在本发明实施了中可以用查找表去把时钟数据相移控制器的输出转化到IQ的相位变化。
在初始校准环路时设置Vph＝0，将IQ数据的相位偏移设置到变化范围的中心点。关闭RZ时钟，调整I、Q两路数据到最优对齐点，然后使能RZ时钟信号输出，调节RZ时钟信号对齐都DQPSK数据。
通过上述各实施例，有效解决了相关技术中存在的由于时钟信号和数据信号未对 齐导致传输性能劣化的问题，进而实现了时钟信号和数据信号对齐的目的。
显然，本领域的技术人员应该明白，上述的本发明的各模块或各步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，可选地，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本发明不限制于任何特定的硬件和软件结合。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。
工业实用性
如上所述，本发明实施例提供的一种相位处理方法及装置具有以下有益效果：解决了相关技术中存在的由于时钟信号和数据信号未对齐导致传输性能劣化的问题，进而达到了实现时钟信号和数据信号对齐的效果。

Claims (10)

  1. 一种相位处理方法，包括：
    在数据信号上添加预定幅度的相位扰动；
    根据所述相位扰动控制所述数据信号和时钟信号进行相位对齐处理。
  2. 根据权利要求1所述的方法，其中，所述相位扰动包括正微扰和/或负微扰。
  3. 根据权利要求2所述的方法，其中，根据所述相位扰动控制所述数据信号和时钟信号进行相位对齐处理包括：
    在所述相位扰动的周期内，在所述数据信号上添加预定数量的相位偏移；
    采集对应于所述相位偏移的光功率的电压；
    根据采集的所述光功率的电压确定添加到所述数据信号上的目的相位偏移；
    利用所述目的相位偏移控制所述数据信号和时钟信号进行相位对齐处理。
  4. 根据权利要求3所述的方法，其中，根据采集的所述光功率的电压确定添加到所述数据信号上的目的相位偏移包括：
    选择采集的所述光功率为零或与零相差小于预定阈值时的相位偏移；
    确定选择的所述相位偏移为所述目的相位偏移。
  5. 根据权利要求1至4中任一项所述的方法，其中，所述数据信号为归零-四相相对相移键控RZ-DQPSK***中的四相相对相移键控DQPSK数据。
  6. 一种相位处理装置，包括：
    添加模块，设置为在数据信号上添加预定幅度的相位扰动；
    控制模块，设置为根据所述相位扰动控制所述数据信号和时钟信号进行相位对齐处理。
  7. 根据权利要求6所述的装置，其中，所述相位扰动包括正微扰和/或负微扰。
  8. 根据权利要求7所述的装置，其中，所述控制模块包括：
    添加单元，设置为在所述相位扰动的周期内，在所述数据信号上添加预定数量的相位偏移；
    采集单元，设置为采集对应于所述相位偏移的光功率的电压；
    确定单元，设置为根据采集的所述光功率的电压确定添加到所述数据信号上 的目的相位偏移；
    控制单元，设置为利用所述目的相位偏移控制所述数据信号和时钟信号进行相位对齐处理。
  9. 根据权利要求8所述的装置，其中，所述确定单元包括：
    选择子单元，设置为选择采集的所述光功率为零或与零相差小于预定阈值时的相位偏移；
    确定子单元，设置为确定选择的所述相位偏移为所述目的相位偏移。
  10. 根据权利要求6至9中任一项所述的装置，其中，所述数据信号为归零-四相相对相移键控RZ-DQPSK***中的四相相对相移键控DQPSK数据。
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