WO2016109988A1 - Cmos on-chip direct-current negative voltage generation circuit - Google Patents

Cmos on-chip direct-current negative voltage generation circuit Download PDF

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Publication number
WO2016109988A1
WO2016109988A1 PCT/CN2015/070982 CN2015070982W WO2016109988A1 WO 2016109988 A1 WO2016109988 A1 WO 2016109988A1 CN 2015070982 W CN2015070982 W CN 2015070982W WO 2016109988 A1 WO2016109988 A1 WO 2016109988A1
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Prior art keywords
unit
capacitor
nmos transistor
source
output
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PCT/CN2015/070982
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French (fr)
Chinese (zh)
Inventor
胡蓉彬
王永禄
胡刚毅
陈光炳
王育新
付东兵
张正平
朱璨
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中国电子科技集团公司第二十四研究所
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Publication of WO2016109988A1 publication Critical patent/WO2016109988A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/50—Analogue/digital converters with intermediate conversion to time interval
    • H03M1/54—Input signal sampled and held with linear return to datum

Definitions

  • the invention belongs to the field of analog/mixed signal integrated circuits, and in particular relates to a CMOS on-chip DC negative voltage generating circuit.
  • CMOS Complementary Metal Oxide
  • P-type semiconductor Today's integrated circuit manufacturing process - Complementary Metal Oxide (Complementary Metal Oxide)
  • CMOS Complementary Metal Oxide
  • the semiconductor (referred to as CMOS) process has a substrate of a P-type semiconductor.
  • the CMOS integrated circuit chip substrate is connected to the lowest potential - ground potential, and is powered by a positive supply voltage.
  • the power supply voltage must be expanded inside the chip to generate a voltage higher than the power supply voltage or lower than the ground potential - negative voltage .
  • FIG. 1 is a circuit for expanding a power supply voltage inside a CMOS chip in the prior art, the circuit comprising a pair of cross-coupled NMOS transistors N1 and N2, a pair of capacitors C1 and C2, and a pair for inverting an inverted clock.
  • the INV1 and INV2 are constructed.
  • the gate of the transistor N1 is connected to the source of the transistor N2, the gate of the transistor N2 is connected to the source of the transistor N1, the drains of the transistors N1 and N2 are both connected to the positive power supply voltage VCC, and the substrate ends of the transistors N1 and N2 are grounded;
  • the upper plate of the capacitor C1 is connected to the source of the transistor N1, the upper plate of the capacitor C2 is connected to the source of the transistor N2, the lower plate of the capacitor C1 is connected to the output of the inverter INV1, and the lower plate of the capacitor C2 is connected in reverse.
  • the output terminal of the inverter INV1 is connected to the input terminal of the inverter INV2, and after the input clock CLK passes through the inverters INV1 and INV2, a pair of inverted phases are generated at the output ends of the inverters INV1 and INV2. clock.
  • the supply voltages of the inverters INV1 and INV2 are also VCC, so the inverted clock output of the inverters INV1 and INV2 is at a high level of VCC and the low level is a ground potential.
  • FIG. 1 The circuit shown operates with the input clock signal CLK driven. Without loss of generality, it is assumed that in the initial state, the upper plates of capacitors C1 and C2 are at the positive supply voltage potential VCC.
  • the output of the inverter INV1 changes from a low level to a high level. Due to the charge retention function of the capacitor, the upper plate of the capacitor C1 will be pumped 2 times positive.
  • the output of the inverter INV2 changes from a high level to a low level, and the upper plate of the capacitor C2 is pulled to the ground potential.
  • the gate potential of the NMOS transistor N1 since the gate potential of the NMOS transistor N1 is lower than its source-drain potential, it will be in an off state; thus, the upper plate of the capacitor C1 will remain at twice the positive supply voltage potential until the next clock transition.
  • the gate potential of the NMOS transistor N2 is higher than its source and drain potential, and reaches the threshold voltage of the NMOS transistor, the transistor N2 will be turned on, and the capacitor C2 is charged until the upper plate potential of the capacitor C2 reaches the positive power supply voltage VCC.
  • the external input clock signal CLK is inverted, from low level to high level, the output of the inverter INV1 changes from high level to low level, and the potential of the plate on the capacitor C1 is pulled again.
  • the power supply voltage VCC is returned; at the same time, the output of the inverter INV2 changes from a low level to a high level, and the upper plate potential of the capacitor C2 is pumped to twice the positive power supply voltage potential.
  • the gate potential of the NMOS transistor N2 since the gate potential of the NMOS transistor N2 is lower than its source-drain potential, it will be in an off state; thus, the upper plate of the capacitor C2 will remain at twice the positive supply voltage potential until the next clock transition.
  • the gate potential of the NMOS transistor N1 is higher than its source-drain potential, and reaches the threshold voltage of the NMOS transistor, the transistor N1 will be turned on, and the capacitor C1 is charged, supplementing the charge lost during the operation, so that the capacitor C1 is charged.
  • the plate potential always reaches the positive supply voltage VCC.
  • the inventors of the present invention have found through research that although the circuit shown in FIG. 1 can realize the expansion of the internal voltage range of the chip, it can only generate a positive voltage higher than the power supply voltage, and can only generate a pulse voltage; and the analog circuit unit usually A DC voltage is required, and in some cases a DC negative voltage is required, but the existing circuit does not.
  • the present invention provides a CMOS on-chip DC negative voltage generating circuit capable of solving the problem that the DC negative voltage cannot be provided inside the existing CMOS analog/hybrid integrated circuit.
  • a CMOS on-chip DC negative voltage generating circuit includes a charging unit, a clock unit, a charge pump unit, an output unit, and a charge storage unit;
  • the charging unit is configured to charge the charge pump unit
  • the clock unit is configured to provide a required clock signal to the charge pump unit
  • the charge pump unit is configured to generate a negative pulse voltage having an amplitude equal to a positive power supply voltage
  • the output unit is configured to convert a negative pulse voltage generated by the charge pump unit into a DC negative voltage, the magnitude of the DC negative voltage being equal to a positive power supply voltage;
  • the charge storage unit is configured to store the charge brought to the negative potential by the charge pump unit while the DC negative voltage output by the output unit is stable during the operation of the CMOS chip.
  • the CMOS on-chip DC negative voltage generating circuit provided by the invention firstly generates a negative pulse voltage equal to the CMOS chip DC positive power supply voltage through the charging unit, the clock unit and the charge pump unit under the external clock driving, and then passes through The output unit circuit converts the negative pulse voltage into a DC negative voltage, thereby well solving the problem of generating a DC negative voltage inside the chip under the condition of a single DC positive power supply of the CMOS chip; thereby further solving the problem in the deep Asia
  • the traditional analog circuit structure does not work properly under the low power supply voltage of the micron CMOS process.
  • the charging unit is composed of a pair of cross-coupled first PMOS transistors and a second PMOS transistor, the source of the first PMOS transistor is connected to the gate of the second PMOS transistor, and the source of the second PMOS transistor Connecting a gate of the first PMOS transistor, the drains of the first PMOS transistor and the second PMOS transistor are both grounded to GND, and the substrates of the first PMOS transistor and the second PMOS transistor are connected to a DC positive power supply voltage VCC, The sources of the first PMOS transistor and the second PMOS transistor are respectively connected to the charge pump unit, and the charge pump unit is alternately charged during circuit operation.
  • the clock unit is composed of a pair of serially connected first inverters and second inverters, an input end of the first inverter receives an external clock signal CLKIN, and an output terminal is connected to the second counter
  • the input end of the phase converter outputs a first clock signal CK1; the output end of the second inverter outputs a second clock signal CK2, and the first clock signal CK1 and the second clock signal CK2 are both connected to the charge pump unit.
  • first inverter and the second inverter have the same structure, each of which is composed of an NMOS transistor and a PMOS transistor, and the drains of the NMOS transistor and the PMOS transistor are connected together as an output terminal of the inverter.
  • the gates are connected together as an input of an inverter whose source and substrate are connected together to ground GND, the source of which is connected to the substrate and connected to a DC positive supply voltage VCC.
  • the charge pump unit is composed of a first capacitor and a second capacitor, an upper plate of the first capacitor is connected to a first clock signal CK1 output by the clock unit, and an upper plate of the second capacitor is connected a second clock signal CK2 outputted by the clock unit, a lower plate of the first capacitor is connected to a source of the first PMOS transistor in the charging unit, and a lower plate of the second capacitor is connected to the charging unit The source of the two PMOS transistors.
  • a third PMOS transistor is connected in parallel between the upper plate and the lower plate of the first capacitor, and a fourth PMOS transistor is connected in parallel between the upper plate and the lower plate of the second capacitor; a source and a gate of the PMOS transistor are connected to an upper plate of the first capacitor, a drain is connected to a lower plate of the first capacitor, and a substrate is connected to a DC positive power supply voltage VCC; a source of the fourth PMOS transistor The upper plate of the second capacitor is connected to the gate, the lower plate of the second capacitor is connected to the drain, and the substrate is connected to the DC positive power supply voltage VCC.
  • the output unit is composed of a pair of cross-coupled first deep well NMOS transistors and a second deep well NMOS transistor, and a drain of the first deep well NMOS transistor is connected to a gate of the second deep well NMOS transistor a drain of the second deep well NMOS transistor connected to a gate of the first deep well NMOS transistor, a substrate of the first deep well NMOS transistor being connected to a source thereof, the second deep well NMOS transistor The substrate is connected to the source thereof, and the source of the first deep well NMOS transistor and the source of the second deep well NMOS transistor are connected together to form an output end of the output unit, and a DC negative voltage VD is output, the first The drains of the deep well NMOS transistor and the second deep well NMOS transistor are respectively connected to the charge pump unit.
  • the charge storage unit is composed of a large-capacity capacitor Co, the upper plate of the capacitor Co is grounded, and the lower plate is connected to the output end of the output unit.
  • the charge pump unit is composed of a third deep well NMOS transistor and a fourth deep well NMOS transistor, and a gate of the third deep well NMOS transistor is connected to the first clock signal CK1 output by the clock unit, a gate of the four deep well NMOS transistor is connected to the second clock signal CK1 output by the clock unit, and a drain, a substrate and a source of the third deep well NMOS transistor are connected to the first PMOS transistor of the charging unit a source, a drain, a substrate and a source of the fourth deep well NMOS transistor are connected to a source of the second PMOS transistor in the charging unit;
  • the charge storage unit is formed by a large size fifth deep well NMOS transistor having a gate grounded, a drain, a substrate and a source connected to an output of the output unit.
  • FIG. 1 is a schematic diagram of a circuit structure for extending an internal power supply voltage of a CMOS chip according to the prior art.
  • FIG. 2 is a schematic diagram showing the principle structure of a CMOS on-chip DC negative voltage generating circuit provided by the present invention.
  • FIG. 3 is a schematic structural view of an embodiment of a CMOS on-chip DC negative voltage generating circuit provided by the present invention.
  • FIG. 4 is a timing diagram showing the operation of a CMOS on-chip DC negative voltage generating circuit provided by the present invention.
  • FIG. 5 is a schematic structural diagram of another embodiment of a CMOS on-chip DC negative voltage generating circuit provided by the present invention.
  • FIG. 6 is a schematic structural view of still another embodiment of a CMOS on-chip DC negative voltage generating circuit provided by the present invention.
  • charging unit 2, clock unit; 3, charge pump unit; 4, output unit; 5, charge storage unit.
  • the present invention provides a CMOS on-chip DC negative voltage generating circuit, including a charging unit 1, a clock unit 2, a charge pump unit 3, an output unit 4, and a charge storage unit 5;
  • the charging unit 1 is configured to charge the charge pump unit 3;
  • the clock unit 2 is configured to provide a required clock signal to the charge pump unit 3;
  • the charge pump unit 3 is configured to generate a negative pulse voltage having a magnitude equal to a positive power supply voltage
  • the output unit 4 is configured to convert a negative pulse voltage generated by the charge pump unit 3 into a DC negative voltage, the magnitude of the DC negative voltage being equal to a positive power supply voltage;
  • the charge storage unit 5 is configured to store the charge brought to the negative potential by the charge pump unit 3 while keeping the DC negative voltage output by the output unit 4 stable during the operation of the CMOS chip.
  • the CMOS on-chip DC negative voltage generating circuit provided by the invention firstly generates a negative pulse voltage equal to the CMOS chip DC positive power supply voltage through the charging unit, the clock unit and the charge pump unit under the external clock driving, and then passes through The output unit circuit converts the negative pulse voltage into a DC negative voltage, thereby well solving the problem of generating a DC negative voltage inside the chip under the condition of a single DC positive power supply of the CMOS chip; thereby further solving the problem in the deep Asia
  • the traditional analog circuit structure does not work properly under the low power supply voltage of the micron CMOS process.
  • the charging unit 1 is composed of a pair of cross-coupled first PMOS transistor P1 and a second PMOS transistor P2, and the source of the first PMOS transistor P1 is connected to the second.
  • the gate of the PMOS transistor P2, the source of the second PMOS transistor P2 is connected to the gate of the first PMOS transistor P1, and the drains of the first PMOS transistor P1 and the second PMOS transistor P2 are both grounded to GND, the first A substrate of a PMOS transistor P1 and a second PMOS transistor P2 are connected to a DC positive power supply voltage VCC, and sources of the first PMOS transistor P1 and the second PMOS transistor P2 are respectively connected to the charge pump unit 3, during circuit operation The charge pump unit 3 is charged in a middle turn.
  • the clock unit 2 is composed of a pair of serially connected first inverters and second inverters.
  • the input end of the first inverter receives an external clock signal CLKIN, and outputs The end is connected to the input end of the second inverter and outputs a first clock signal CK1; the output end of the second inverter outputs a second clock signal CK2, the first clock signal CK1 and the second clock signal CK2 Both are connected to the charge pump unit.
  • the first inverter and the second inverter have the same structure, and each is composed of an NMOS transistor and a PMOS transistor, and the drains of the NMOS transistor and the PMOS transistor are connected together.
  • the gates are connected together as an input of an inverter whose source and substrate are connected together to ground GND, the source of which is connected to the substrate Connect the DC positive supply voltage VCC.
  • the first clock signal CK1 and the second clock signal CK2 are a pair of mutually inverted clock signals, and the high level of the first clock signal CK1 and the second clock signal CK2 is a positive DC power supply voltage VCC.
  • the low level is ground GND.
  • the charge pump unit 3 is composed of a first capacitor C3 and a second capacitor C4.
  • the upper plate of the first capacitor C3 is connected to the first clock signal CK1 output by the clock unit 2
  • the upper plate of the second capacitor C4 is connected to the second clock signal CK2 outputted by the clock unit 2
  • the lower plate of the first capacitor C3 is connected to the source of the first PMOS transistor P1 of the charging unit 1.
  • the lower plate of the second capacitor C4 is connected to the source of the second PMOS transistor P2 in the charging unit 1.
  • a third PMOS transistor P3 is connected in parallel between the upper and lower plates of the first capacitor C3, and the upper and lower poles of the second capacitor C4 are connected.
  • a fourth PMOS transistor P4 is connected in parallel between the boards; a source and a gate of the third PMOS transistor P3 are connected to an upper plate of the first capacitor C3, and a drain is connected to a lower plate of the first capacitor C3.
  • the substrate is connected to the DC positive power supply voltage VCC; the source and the gate of the fourth PMOS transistor P4 are connected to the upper plate of the second capacitor C4, and the drain is connected to the lower plate of the second capacitor C4, the substrate Connect the DC positive supply voltage VCC.
  • a protection transistor P3 is added between the upper and lower plates of the first capacitor C3, and a protection transistor is added between the upper and lower plates of the second capacitor C4.
  • P4 the transistor P3 and the transistor P4 function as diode-connected PMOS transistors for preventing the lower plates of the first capacitor C3 and the second capacitor C4 from being at an excessively high potential in the initial state, so as to prevent the circuit from being locked during the startup process. At the same time, it also increases the startup speed of the circuit.
  • the output unit 4 is composed of a pair of cross-coupled first deep well NMOS transistor N3 and a second deep well NMOS transistor N4, and the drain connection of the first deep well NMOS transistor N3
  • the gate of the second deep well NMOS transistor N4, the drain of the second deep well NMOS transistor N4 is connected to the gate of the first deep well NMOS transistor N3, the substrate of the first deep well NMOS transistor N3 and its source
  • the poles are connected together, the substrate of the second deep well NMOS transistor N4 is connected to its source, and the source of the first deep well NMOS transistor N3 is connected to the source of the second deep well NMOS transistor N4
  • Forming an output end of the output unit 4, outputting a DC negative voltage VD, the drains of the first deep well NMOS transistor N3 and the second deep well NMOS transistor N4 are respectively connected to the charge pump unit 3, specifically the first deep well a drain of the NMOS transistor N3 is connected to a lower plate of the first capacitor 3 of
  • the charge storage unit 5 is composed of a large-capacity capacitor Co.
  • the upper plate of the capacitor Co is grounded, and the lower plate is connected to the output end of the output unit 4.
  • the large-capacity capacitor Co is used to store the charge pumped to the negative potential by the charge pump unit 3 while stabilizing the negative voltage output from the voltage output unit 4.
  • the charge pump unit 3 is composed of a third deep well NMOS transistor N5 and a fourth deep well NMOS transistor N6, and the gate of the third deep well NMOS transistor N5.
  • the gate of the fourth deep-well NMOS transistor N6 is connected to the second clock signal CK1 output by the clock unit 2
  • the third deep-well NMOS transistor N5 a drain, a substrate and a source are connected to a source of the first PMOS transistor P1 in the charging unit 1, and a drain, a substrate and a source of the fourth deep-well NMOS transistor N6 are connected to the charging unit 1
  • the source of the second PMOS transistor P2; at the same time, the charge storage unit 5 is composed of a large-sized fifth deep-well NMOS transistor N7, the gate of the fifth deep-well NMOS transistor N7 is grounded, the drain, the substrate And a source is connected to the output of the output unit 4.
  • the transistors N5, N6, and N7 are in an on state, so that the gates of the transistors N5, N6, and N7 form an excellent capacitive relationship with their conductive channels. It can work in place of the capacitor; compared to the embodiment circuit shown in FIG. 3, the circuit of this embodiment uses fewer types of devices, and actually only uses PMOS and NMOS transistors. Thus, the circuit of the present embodiment can be implemented not only under CMOS mixed-signal process conditions, but also under digital CMOS process conditions where no capacitive device is provided.
  • the present invention refers to the circuit portion formed by the charging unit 1, the clock unit 2 and the charge pump unit 3 as a negative pulse voltage generating circuit, and the working principle of the negative pulse voltage generating circuit is as follows:
  • the negative pulse voltage generating circuit operates under the driving of the external clock signal CLKIN, and the initial level of the external clock signal CLKIN is assumed to be low level without loss of generality. GND.
  • the first clock signal CK1 outputted by the first inverter of the clock unit 2 is at a high level VCC
  • the second clock signal CK2 outputted by the second inverter is at a low level GND
  • the charge pump unit 3 The lower plate potential V1 of the first capacitor C3 and the lower plate potential V2 of the second capacitor C4 are not determined, but the difference between them cannot be greater than the threshold voltage of the PMOS transistor, because if the difference therebetween is greater than the threshold voltage of the PMOS transistor, One of the PMOS transistors in the charging unit 1 will be turned on and begin to charge the respective capacitors of the charge pump unit 3 such that their difference is less than or equal to the threshold voltage of the PMOS transistor. Also, without loss of generality, it is assumed that the initial potentials V1 and V2 of
  • the external clock signal CLKIN flips from low level to high level.
  • the first clock signal CK1 is changed from a high level to a low level, so that the lower plate potential V1 of the first capacitor C3 is changed from the DC positive power supply voltage potential VCC to the ground potential GND; meanwhile, the second clock signal CK2 changes from a low level to a high level, so that the second capacitor C4 lower plate potential V2 is doubled from the direct current power supply voltage potential VCC by a direct current positive power supply voltage potential of 2VCC.
  • the second PMOS transistor P2 of the charging unit 1 is turned on, and the second capacitor C4 is charged until the lower plate potential of the second capacitor C4 reaches a PMOS transistor threshold voltage potential.
  • the external clock signal CLKIN is inverted again, from a high level to a low level.
  • the first clock signal CK1 changes from a low level to a high level, so that the lower plate potential V1 of the first capacitor C3 is changed from the ground potential GND to a DC positive power supply voltage potential VCC; meanwhile, the second clock signal CK2 changes from a high level to a low level, so that the second capacitor C4 lower plate potential V2 drops by a DC positive power supply voltage potential VCC, and the threshold voltage potential of a PMOS transistor becomes equal to the DC positive power supply voltage minus The negative potential of a PMOS transistor threshold voltage.
  • the first PMOS transistor P1 of the charging unit 1 is turned on, and the first capacitor C3 is charged until the potential of the lower plate of the first capacitor C3 reaches the ground potential.
  • the external clock signal CLKIN flips again, from low level to high level.
  • the first clock signal CK1 is changed from a high level to a low level, so that the lower plate potential V1 of the first capacitor C3 is changed from a ground potential to a negative potential -VCC equal to a DC positive power supply voltage;
  • the second clock signal CK2 changes from a low level to a high level, so that the lower plate potential V2 of the second capacitor C4 rises by a DC positive power supply voltage potential, and returns to a PMOS transistor threshold voltage potential again.
  • the second PMOS transistor P2 of the charging unit 1 is turned on, and the second capacitor C4 is charged until the potential of the lower plate of the second capacitor C4 reaches the ground potential GND.
  • the external clock signal CLKIN is flipped again, from a high level to a low level.
  • the first clock signal CK1 changes from a low level to a high level, so that the lower plate potential V1 of the first capacitor C3 rises by a DC positive power supply voltage VCC, and returns to the ground potential GND; meanwhile, the second The clock signal CK2 is changed from a high level to a low level, so that the lower plate potential V2 of the second capacitor C4 is lowered by a DC positive power supply voltage potential to a negative potential -VCC equal to the DC positive power supply voltage.
  • the present invention refers to the lower plate voltage signal of the first capacitor C3 as the first pulse voltage signal, and the lower plate voltage signal of the second capacitor C4 as the second pulse voltage signal, and is constituted by the foregoing structure. The description shows that they are respectively connected to the first deep well NMOS transistor N3 and the second deep well NMOS transistor N4 of the output unit 4.
  • the first pulse voltage signal V1 and the second pulse voltage signal V2 are alternately at the ground potential GND and a negative potential -VCC equal to the DC positive power supply voltage.
  • the first pulse voltage signal V1 is at the ground potential GND and the second pulse voltage signal V2 is at the negative potential -VCC
  • the first deep well NMOS transistor N3 of the output unit 4 is turned off, and the second deep well NMOS transistor N4 is turned on.
  • the second pulse voltage signal V2 charges the bulk capacitor Co of the charge storage unit 5 through the second deep well NMOS transistor N4.
  • the first pulse voltage signal V1 When the first pulse voltage signal V1 is at a negative potential -VCC and the second pulse voltage signal V2 is at a ground potential GND, the first deep well NMOS transistor N3 of the output unit 4 is turned on, and the second deep well NMOS transistor N4 is turned on.
  • the first pulse voltage signal V1 charges the bulk capacitor Co of the charge storage unit 5 through the first deep well NMOS transistor N3.
  • the first negative pulse voltage signal and the second negative pulse voltage signal alternately charge the large capacity capacitor Co until the output voltage VD reaches -VCC, as shown in FIG. 4; afterwards, the output voltage VD Will remain at -VCC potential all the time.

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Abstract

A CMOS on-chip direct-current negative voltage generation circuit, comprising a charging unit (1), a clock unit (2), a charge pump unit (3), an output unit (4) and a charge storage unit (5). The charging unit (1) is used for charging the charge pump unit (3); the clock unit (2) is used for providing needed clock signals to the charge pump unit (3); the charge pump unit (3) is used for generating a negative impulse voltage that is equal to a positive supply voltage in amplitude; the output unit (4) is used for converting the negative impulse voltage generated by the charge pump unit (3) into a direct-current negative voltage, and the direct-current negative voltage is equal to the positive supply voltage; the charge storage unit (5) is used for storing charges brought by the charge pump unit (3) to a negative potential, and meanwhile the direct-current negative voltage output by the output unit (4) is kept stable in the working process of a CMOS chip. The problem that the direct-current negative voltage is generated inside a chip under the condition that the CMOS chip has single direct-current positive power supply is solved.

Description

一种CMOS片上直流负电压产生电路 CMOS on-chip DC negative voltage generating circuit 一种CMOS片上直流负电压产生电路CMOS on-chip DC negative voltage generating circuit
技术领域Technical field
本发明属于模拟/混合信号集成电路领域，具体涉及一种CMOS片上直流负电压产生电路。The invention belongs to the field of analog/mixed signal integrated circuits, and in particular relates to a CMOS on-chip DC negative voltage generating circuit.
背景技术Background technique
当今集成电路制造工艺—互补金属氧化物半导体（Complementary Metal Oxide Semiconductor，简称CMOS）工艺，其衬底为P型半导体。为了实现器件间的有效隔离，CMOS集成电路芯片衬底接最低电位—地电位，采用正电源电压供电。Today's integrated circuit manufacturing process - Complementary Metal Oxide (Complementary Metal Oxide) The semiconductor (referred to as CMOS) process has a substrate of a P-type semiconductor. In order to achieve effective isolation between devices, the CMOS integrated circuit chip substrate is connected to the lowest potential - ground potential, and is powered by a positive supply voltage.
随着CMOS工艺特征尺寸向着深亚微米（90 nm以下）方面发展，芯片供电电压越来越低，甚至低于1V。在如此低的电源电压下，传统的模拟电路结构（如运放、电流源等）将不能正常工作。因此，为了使传统的模拟电路结构在深亚微米CMOS芯片极低电源电压下也能正常工作，必须在芯片内部对电源电压进行扩展，产生高于电源电压或者低于地电位的电压—负电压。With the CMOS process feature size toward deep submicron (90 In terms of nm development, the chip supply voltage is getting lower and lower, even lower than 1V. At such low supply voltages, traditional analog circuit structures (such as op amps, current sources, etc.) will not function properly. Therefore, in order to make the traditional analog circuit structure work well under the extremely low power supply voltage of the deep submicron CMOS chip, the power supply voltage must be expanded inside the chip to generate a voltage higher than the power supply voltage or lower than the ground potential - negative voltage .
图1为现有技术中用于CMOS芯片内部扩展电源电压的电路，该电路由一对交叉耦合的NMOS晶体管N1和N2、一对电容C1和C2、一对用于产生反相时钟的反相器INV1和INV2构成。其中晶体管N1的栅极连接晶体管N2的源极，晶体管N2的栅极连接晶体管N1的源极，晶体管N1和N2的漏极均连接至正电源电压VCC，晶体管N1和N2的衬底端接地；电容C1的上极板连接晶体管N1的源极，电容C2的上极板连接晶体管N2的源极，电容C1的下极板连接反相器INV1的输出端，电容C2的下极板连接反相器INV2的输出端；反相器INV1的输出端连接反相器INV2的输入端，输入时钟CLK经过反相器INV1和INV2后，在反相器INV1和INV2的输出端产生一对反相的时钟。反相器INV1和INV2的供电电压也为VCC，所以反相器INV1和INV2输出的反相时钟高电平为VCC，低电平为地电位。1 is a circuit for expanding a power supply voltage inside a CMOS chip in the prior art, the circuit comprising a pair of cross-coupled NMOS transistors N1 and N2, a pair of capacitors C1 and C2, and a pair for inverting an inverted clock. The INV1 and INV2 are constructed. The gate of the transistor N1 is connected to the source of the transistor N2, the gate of the transistor N2 is connected to the source of the transistor N1, the drains of the transistors N1 and N2 are both connected to the positive power supply voltage VCC, and the substrate ends of the transistors N1 and N2 are grounded; The upper plate of the capacitor C1 is connected to the source of the transistor N1, the upper plate of the capacitor C2 is connected to the source of the transistor N2, the lower plate of the capacitor C1 is connected to the output of the inverter INV1, and the lower plate of the capacitor C2 is connected in reverse. The output terminal of the inverter INV1 is connected to the input terminal of the inverter INV2, and after the input clock CLK passes through the inverters INV1 and INV2, a pair of inverted phases are generated at the output ends of the inverters INV1 and INV2. clock. The supply voltages of the inverters INV1 and INV2 are also VCC, so the inverted clock output of the inverters INV1 and INV2 is at a high level of VCC and the low level is a ground potential.
图1 所示电路在输入时钟信号CLK驱动下工作。在不损失一般性的前提下，假设在初始态，电容C1和C2的上极板处于正电源电压电位VCC。当输入时钟CLK由高电平变为低电平时，反相器INV1的输出由低电平变为高电平，由于电容器的电荷保持功能，电容C1上极板将被泵到2倍于正电源电压的电位；与此同时，反相器INV2的输出由高电平变为低电平，电容C2的上极板被拉到地电位。此时，由于NMOS晶体管N1的栅电位低于其源漏电位，将处于截止态；这样，电容C1的上极板将保持在2倍于正电源电压电位，直到下一次时钟变换来临。同时，NMOS晶体管N2的栅电位高于其源漏电位，并达到了NMOS晶体管的阈值电压，晶体管N2将导通，并对电容C2充电，直到电容C2的上极板电位达到正电源电压VCC。figure 1 The circuit shown operates with the input clock signal CLK driven. Without loss of generality, it is assumed that in the initial state, the upper plates of capacitors C1 and C2 are at the positive supply voltage potential VCC. When the input clock CLK changes from a high level to a low level, the output of the inverter INV1 changes from a low level to a high level. Due to the charge retention function of the capacitor, the upper plate of the capacitor C1 will be pumped 2 times positive. At the same time, the output of the inverter INV2 changes from a high level to a low level, and the upper plate of the capacitor C2 is pulled to the ground potential. At this time, since the gate potential of the NMOS transistor N1 is lower than its source-drain potential, it will be in an off state; thus, the upper plate of the capacitor C1 will remain at twice the positive supply voltage potential until the next clock transition. At the same time, the gate potential of the NMOS transistor N2 is higher than its source and drain potential, and reaches the threshold voltage of the NMOS transistor, the transistor N2 will be turned on, and the capacitor C2 is charged until the upper plate potential of the capacitor C2 reaches the positive power supply voltage VCC.
经过半个时钟周期后，外部输入时钟信号CLK发生翻转，由低电平变为高电平，反相器INV1的输出由高电平变为低电平，电容C1上极板电位重新被拉回正电源电压VCC；与此同时，反相器INV2的输出由低电平变为高电平，电容C2的上极板电位被泵到2倍于正电源电压电位。此时，由于NMOS晶体管N2的栅电位低于其源漏电位，将处于截止态；这样，电容C2的上极板将保持在2倍于正电源电压电位，直到下一次时钟变换来临。同时，NMOS晶体管N1的栅电位高于其源漏电位，并达到了NMOS晶体管的阈值电压，晶体管N1将导通，并对电容C1充电，补充在工作过程中损失的电荷，使电容C1的上极板电位总是达到正电源电压VCC。这样，在时钟CLK的驱动下，NMOS晶体管N1和N2的源极电位交替地被泵到2倍于正电源电压的电位。After half a clock cycle, the external input clock signal CLK is inverted, from low level to high level, the output of the inverter INV1 changes from high level to low level, and the potential of the plate on the capacitor C1 is pulled again. The power supply voltage VCC is returned; at the same time, the output of the inverter INV2 changes from a low level to a high level, and the upper plate potential of the capacitor C2 is pumped to twice the positive power supply voltage potential. At this time, since the gate potential of the NMOS transistor N2 is lower than its source-drain potential, it will be in an off state; thus, the upper plate of the capacitor C2 will remain at twice the positive supply voltage potential until the next clock transition. At the same time, the gate potential of the NMOS transistor N1 is higher than its source-drain potential, and reaches the threshold voltage of the NMOS transistor, the transistor N1 will be turned on, and the capacitor C1 is charged, supplementing the charge lost during the operation, so that the capacitor C1 is charged. The plate potential always reaches the positive supply voltage VCC. Thus, under the driving of the clock CLK, the source potentials of the NMOS transistors N1 and N2 are alternately pumped to a potential twice the positive power supply voltage.
本发明的发明人经过研究发现，图1所示的电路虽然能实现芯片内部电压范围的扩展，但是它只能产生高于电源电压的正电压，并且只能产生脉冲电压；而模拟电路单元通常需要直流电压，且在某些情况下需要直流负电压，可是现有电路却不能提供。The inventors of the present invention have found through research that although the circuit shown in FIG. 1 can realize the expansion of the internal voltage range of the chip, it can only generate a positive voltage higher than the power supply voltage, and can only generate a pulse voltage; and the analog circuit unit usually A DC voltage is required, and in some cases a DC negative voltage is required, but the existing circuit does not.
发明内容Summary of the invention
针对现有技术存在的技术问题，本发明提供一种CMOS片上直流负电压产生电路，该电路能够解决现有CMOS模拟/混合集成电路内部不能提供直流负电压的问题。In view of the technical problems existing in the prior art, the present invention provides a CMOS on-chip DC negative voltage generating circuit capable of solving the problem that the DC negative voltage cannot be provided inside the existing CMOS analog/hybrid integrated circuit.
为了实现上述目的，本发明采用如下技术方案：In order to achieve the above object, the present invention adopts the following technical solutions:
一种CMOS片上直流负电压产生电路，包括充电单元、时钟单元、电荷泵单元、输出单元和电荷存储单元；其中，A CMOS on-chip DC negative voltage generating circuit includes a charging unit, a clock unit, a charge pump unit, an output unit, and a charge storage unit; wherein
所述充电单元，用于向所述电荷泵单元充电；The charging unit is configured to charge the charge pump unit;
所述时钟单元，用于向所述电荷泵单元提供所需时钟信号；The clock unit is configured to provide a required clock signal to the charge pump unit;
所述电荷泵单元，用于产生幅度大小等于正电源电压的负脉冲电压；The charge pump unit is configured to generate a negative pulse voltage having an amplitude equal to a positive power supply voltage;
所述输出单元，用于把所述电荷泵单元产生的负脉冲电压转换成直流负电压，该直流负电压的大小等于正电源电压；The output unit is configured to convert a negative pulse voltage generated by the charge pump unit into a DC negative voltage, the magnitude of the DC negative voltage being equal to a positive power supply voltage;
所述电荷存储单元，用于存储被所述电荷泵单元带到负电位的电荷，同时使所述输出单元输出的直流负电压在CMOS芯片工作过程中保持稳定。The charge storage unit is configured to store the charge brought to the negative potential by the charge pump unit while the DC negative voltage output by the output unit is stable during the operation of the CMOS chip.
本发明提供的CMOS片上直流负电压产生电路，在外部时钟驱动下，先通过所述充电单元、时钟单元和电荷泵单元产生一幅度大小与CMOS芯片直流正电源电压相等的负脉冲电压，再通过所述输出单元电路把负脉冲电压转换成直流负电压，从而很好地解决了在CMOS芯片单一直流正电源供电的情况下，在芯片内部产生直流负电压的问题；从而进一步解决了在深亚微米CMOS工艺较低的电源电压供电下，传统的模拟电路结构不能正常工作的问题。The CMOS on-chip DC negative voltage generating circuit provided by the invention firstly generates a negative pulse voltage equal to the CMOS chip DC positive power supply voltage through the charging unit, the clock unit and the charge pump unit under the external clock driving, and then passes through The output unit circuit converts the negative pulse voltage into a DC negative voltage, thereby well solving the problem of generating a DC negative voltage inside the chip under the condition of a single DC positive power supply of the CMOS chip; thereby further solving the problem in the deep Asia The traditional analog circuit structure does not work properly under the low power supply voltage of the micron CMOS process.
进一步，所述充电单元由一对交叉耦合的第一PMOS晶体管和第二PMOS晶体管构成，所述第一PMOS晶体管的源极连接第二PMOS晶体管的栅极，所述第二PMOS晶体管的源极连接第一PMOS晶体管的栅极，所述第一PMOS晶体管和第二PMOS晶体管的漏极均接地GND，所述第一PMOS晶体管和第二PMOS晶体管的衬底均连接直流正电源电压VCC，所述第一PMOS晶体管和第二PMOS晶体管的源极分别连接所述电荷泵单元，在电路工作过程中轮流给所述电荷泵单元充电。Further, the charging unit is composed of a pair of cross-coupled first PMOS transistors and a second PMOS transistor, the source of the first PMOS transistor is connected to the gate of the second PMOS transistor, and the source of the second PMOS transistor Connecting a gate of the first PMOS transistor, the drains of the first PMOS transistor and the second PMOS transistor are both grounded to GND, and the substrates of the first PMOS transistor and the second PMOS transistor are connected to a DC positive power supply voltage VCC, The sources of the first PMOS transistor and the second PMOS transistor are respectively connected to the charge pump unit, and the charge pump unit is alternately charged during circuit operation.
进一步，所述时钟单元由一对串行连接的第一反相器和第二反相器构成，所述第一反相器的输入端接收外部时钟信号CLKIN，输出端连接所述第二反相器的输入端并输出第一时钟信号CK1；所述第二反相器的输出端输出第二时钟信号CK2，所述第一时钟信号CK1和第二时钟信号CK2均连接至所述电荷泵单元。Further, the clock unit is composed of a pair of serially connected first inverters and second inverters, an input end of the first inverter receives an external clock signal CLKIN, and an output terminal is connected to the second counter The input end of the phase converter outputs a first clock signal CK1; the output end of the second inverter outputs a second clock signal CK2, and the first clock signal CK1 and the second clock signal CK2 are both connected to the charge pump unit.
进一步，所述第一反相器和第二反相器具有相同的结构，均由一NMOS晶体管和PMOS晶体管构成，所述NMOS晶体管和PMOS晶体管的漏极连接到一起作为反相器的输出端，栅极连接到一起作为反相器的输入端，所述NMOS晶体管的源极和衬底连接到一起接地GND，所述PMOS晶体管的源极和衬底连接到一起接直流正电源电压VCC。Further, the first inverter and the second inverter have the same structure, each of which is composed of an NMOS transistor and a PMOS transistor, and the drains of the NMOS transistor and the PMOS transistor are connected together as an output terminal of the inverter. The gates are connected together as an input of an inverter whose source and substrate are connected together to ground GND, the source of which is connected to the substrate and connected to a DC positive supply voltage VCC.
进一步，所述电荷泵单元由第一电容器和第二电容器构成，所述第一电容器的上极板连接所述时钟单元输出的第一时钟信号CK1，所述第二电容器的上极板连接所述时钟单元输出的第二时钟信号CK2，所述第一电容器的下极板连接所述充电单元中第一PMOS晶体管的源极，所述第二电容器的下极板连接所述充电单元中第二PMOS晶体管的源极。Further, the charge pump unit is composed of a first capacitor and a second capacitor, an upper plate of the first capacitor is connected to a first clock signal CK1 output by the clock unit, and an upper plate of the second capacitor is connected a second clock signal CK2 outputted by the clock unit, a lower plate of the first capacitor is connected to a source of the first PMOS transistor in the charging unit, and a lower plate of the second capacitor is connected to the charging unit The source of the two PMOS transistors.
进一步，所述第一电容器的上极板和下极板之间并联有第三PMOS晶体管，所述第二电容器的上极板和下极板之间并联有第四PMOS晶体管；所述第三PMOS晶体管的源极和栅极连接所述第一电容器的上极板，漏极连接所述第一电容器的下极板，衬底连接直流正电源电压VCC；所述第四PMOS晶体管的源极和栅极连接所述第二电容器的上极板，漏极连接所述第二电容器的下极板，衬底连接直流正电源电压VCC。Further, a third PMOS transistor is connected in parallel between the upper plate and the lower plate of the first capacitor, and a fourth PMOS transistor is connected in parallel between the upper plate and the lower plate of the second capacitor; a source and a gate of the PMOS transistor are connected to an upper plate of the first capacitor, a drain is connected to a lower plate of the first capacitor, and a substrate is connected to a DC positive power supply voltage VCC; a source of the fourth PMOS transistor The upper plate of the second capacitor is connected to the gate, the lower plate of the second capacitor is connected to the drain, and the substrate is connected to the DC positive power supply voltage VCC.
进一步，所述输出单元由一对交叉耦合的第一深阱NMOS晶体管和第二深阱NMOS晶体管构成，所述第一深阱NMOS晶体管的漏极连接所述第二深阱NMOS晶体管的栅极，所述第二深阱NMOS晶体管的漏极连接第一深阱NMOS晶体管的棚极，所述第一深阱NMOS晶体管的衬底与其源极连接在一起，所述第二深阱NMOS晶体管的衬底与其源极连接在一起，所述第一深阱NMOS晶体管的源极和第二深阱NMOS晶体管的源极连接在一起构成输出单元的输出端，输出直流负电压VD，所述第一深阱NMOS晶体管和第二深阱NMOS晶体管的漏极分别连接所述电荷泵单元。Further, the output unit is composed of a pair of cross-coupled first deep well NMOS transistors and a second deep well NMOS transistor, and a drain of the first deep well NMOS transistor is connected to a gate of the second deep well NMOS transistor a drain of the second deep well NMOS transistor connected to a gate of the first deep well NMOS transistor, a substrate of the first deep well NMOS transistor being connected to a source thereof, the second deep well NMOS transistor The substrate is connected to the source thereof, and the source of the first deep well NMOS transistor and the source of the second deep well NMOS transistor are connected together to form an output end of the output unit, and a DC negative voltage VD is output, the first The drains of the deep well NMOS transistor and the second deep well NMOS transistor are respectively connected to the charge pump unit.
进一步，所述电荷存储单元由一大容量电容器Co构成，所述电容器Co的上极板接地，下极板连接所述输出单元的输出端。Further, the charge storage unit is composed of a large-capacity capacitor Co, the upper plate of the capacitor Co is grounded, and the lower plate is connected to the output end of the output unit.
进一步，所述电荷泵单元由第三深阱NMOS晶体管和第四深阱NMOS晶体管构成，所述第三深阱NMOS晶体管的栅极连接所述时钟单元输出的第一时钟信号CK1，所述第四深阱NMOS晶体管的栅极连接所述时钟单元输出的第二时钟信号CK1，所述第三深阱NMOS晶体管的漏极、衬底和源极连接至所述充电单元中第一PMOS晶体管的源极，所述第四深阱NMOS晶体管的漏极、衬底和源极连接至所述充电单元中第二PMOS晶体管的源极；同时，Further, the charge pump unit is composed of a third deep well NMOS transistor and a fourth deep well NMOS transistor, and a gate of the third deep well NMOS transistor is connected to the first clock signal CK1 output by the clock unit, a gate of the four deep well NMOS transistor is connected to the second clock signal CK1 output by the clock unit, and a drain, a substrate and a source of the third deep well NMOS transistor are connected to the first PMOS transistor of the charging unit a source, a drain, a substrate and a source of the fourth deep well NMOS transistor are connected to a source of the second PMOS transistor in the charging unit;
所述电荷存储单元由一大尺寸第五深阱NMOS晶体管构成，所述第五深阱NMOS晶体管的栅极接地，漏极、衬底和源极连接至所述输出单元的输出端。The charge storage unit is formed by a large size fifth deep well NMOS transistor having a gate grounded, a drain, a substrate and a source connected to an output of the output unit.
附图说明DRAWINGS
图1是现有技术提供的用于CMOS芯片内部扩展电源电压的电路结构示意图。FIG. 1 is a schematic diagram of a circuit structure for extending an internal power supply voltage of a CMOS chip according to the prior art.
图2是本发明提供的CMOS片上直流负电压产生电路的原理结构示意图。2 is a schematic diagram showing the principle structure of a CMOS on-chip DC negative voltage generating circuit provided by the present invention.
图3是本发明提供的CMOS片上直流负电压产生电路一实施例结构示意图。3 is a schematic structural view of an embodiment of a CMOS on-chip DC negative voltage generating circuit provided by the present invention.
图4是本发明提供的CMOS片上直流负电压产生电路工作时序示意图。4 is a timing diagram showing the operation of a CMOS on-chip DC negative voltage generating circuit provided by the present invention.
图5是本发明提供的CMOS片上直流负电压产生电路另一实施例结构示意图。FIG. 5 is a schematic structural diagram of another embodiment of a CMOS on-chip DC negative voltage generating circuit provided by the present invention.
图6是本发明提供的CMOS片上直流负电压产生电路又一实施例结构示意图。6 is a schematic structural view of still another embodiment of a CMOS on-chip DC negative voltage generating circuit provided by the present invention.
图中，1、充电单元；2、时钟单元；3、电荷泵单元；4、输出单元；5、电荷存储单元。In the figure, 1, charging unit; 2, clock unit; 3, charge pump unit; 4, output unit; 5, charge storage unit.
具体实施方式detailed description
为了使本发明实现的技术手段、创作特征、达成目的与功效易于明白了解，下面结合具体图示，进一步阐述本发明。In order to make the technical means, creative features, achievement goals and effects achieved by the present invention easy to understand, the present invention will be further described below in conjunction with specific illustrations.
请参考图2所示，本发明提供一种CMOS片上直流负电压产生电路，包括充电单元1、时钟单元2、电荷泵单元3、输出单元4和电荷存储单元5；其中，Referring to FIG. 2, the present invention provides a CMOS on-chip DC negative voltage generating circuit, including a charging unit 1, a clock unit 2, a charge pump unit 3, an output unit 4, and a charge storage unit 5;
所述充电单元1，用于向所述电荷泵单元3充电；The charging unit 1 is configured to charge the charge pump unit 3;
所述时钟单元2，用于向所述电荷泵单元3提供所需时钟信号；The clock unit 2 is configured to provide a required clock signal to the charge pump unit 3;
所述电荷泵单元3，用于产生幅度大小等于正电源电压的负脉冲电压；The charge pump unit 3 is configured to generate a negative pulse voltage having a magnitude equal to a positive power supply voltage;
所述输出单元4，用于把所述电荷泵单元3产生的负脉冲电压转换成直流负电压，该直流负电压的大小等于正电源电压；The output unit 4 is configured to convert a negative pulse voltage generated by the charge pump unit 3 into a DC negative voltage, the magnitude of the DC negative voltage being equal to a positive power supply voltage;
所述电荷存储单元5，用于存储被所述电荷泵单元3带到负电位的电荷，同时使所述输出单元4输出的直流负电压在CMOS芯片工作过程中保持稳定。The charge storage unit 5 is configured to store the charge brought to the negative potential by the charge pump unit 3 while keeping the DC negative voltage output by the output unit 4 stable during the operation of the CMOS chip.
本发明提供的CMOS片上直流负电压产生电路，在外部时钟驱动下，先通过所述充电单元、时钟单元和电荷泵单元产生一幅度大小与CMOS芯片直流正电源电压相等的负脉冲电压，再通过所述输出单元电路把负脉冲电压转换成直流负电压，从而很好地解决了在CMOS芯片单一直流正电源供电的情况下，在芯片内部产生直流负电压的问题；从而进一步解决了在深亚微米CMOS工艺较低的电源电压供电下，传统的模拟电路结构不能正常工作的问题。The CMOS on-chip DC negative voltage generating circuit provided by the invention firstly generates a negative pulse voltage equal to the CMOS chip DC positive power supply voltage through the charging unit, the clock unit and the charge pump unit under the external clock driving, and then passes through The output unit circuit converts the negative pulse voltage into a DC negative voltage, thereby well solving the problem of generating a DC negative voltage inside the chip under the condition of a single DC positive power supply of the CMOS chip; thereby further solving the problem in the deep Asia The traditional analog circuit structure does not work properly under the low power supply voltage of the micron CMOS process.
作为一具体实施例，请参考图3所示，所述充电单元1由一对交叉耦合的第一PMOS晶体管P1和第二PMOS晶体管P2构成，所述第一PMOS晶体管P1的源极连接第二PMOS晶体管P2的栅极，所述第二PMOS晶体管P2的源极连接第一PMOS晶体管P1的栅极，所述第一PMOS晶体管P1和第二PMOS晶体管P2的漏极均接地GND，所述第一PMOS晶体管P1和第二PMOS晶体管P2的衬底均连接直流正电源电压VCC，所述第一PMOS晶体管P1和第二PMOS晶体管P2的源极分别连接所述电荷泵单元3，在电路工作过程中轮流给所述电荷泵单元3充电。As a specific embodiment, referring to FIG. 3, the charging unit 1 is composed of a pair of cross-coupled first PMOS transistor P1 and a second PMOS transistor P2, and the source of the first PMOS transistor P1 is connected to the second. The gate of the PMOS transistor P2, the source of the second PMOS transistor P2 is connected to the gate of the first PMOS transistor P1, and the drains of the first PMOS transistor P1 and the second PMOS transistor P2 are both grounded to GND, the first A substrate of a PMOS transistor P1 and a second PMOS transistor P2 are connected to a DC positive power supply voltage VCC, and sources of the first PMOS transistor P1 and the second PMOS transistor P2 are respectively connected to the charge pump unit 3, during circuit operation The charge pump unit 3 is charged in a middle turn.
请继续参考图3所示，所述时钟单元2由一对串行连接的第一反相器和第二反相器构成，所述第一反相器的输入端接收外部时钟信号CLKIN，输出端连接所述第二反相器的输入端并输出第一时钟信号CK1；所述第二反相器的输出端输出第二时钟信号CK2，所述第一时钟信号CK1和第二时钟信号CK2均连接至所述电荷泵单元。Referring to FIG. 3, the clock unit 2 is composed of a pair of serially connected first inverters and second inverters. The input end of the first inverter receives an external clock signal CLKIN, and outputs The end is connected to the input end of the second inverter and outputs a first clock signal CK1; the output end of the second inverter outputs a second clock signal CK2, the first clock signal CK1 and the second clock signal CK2 Both are connected to the charge pump unit.
具体地，作为一种实施方式，所述第一反相器和第二反相器具有相同的结构，均由一NMOS晶体管和PMOS晶体管构成，所述NMOS晶体管和PMOS晶体管的漏极连接到一起作为反相器的输出端，栅极连接到一起作为反相器的输入端，所述NMOS晶体管的源极和衬底连接到一起接地GND，所述PMOS晶体管的源极和衬底连接到一起接直流正电源电压VCC。由此可见，所述第一时钟信号CK1和第二时钟信号CK2是一对互相反相的时钟信号，并且所述第一时钟信号CK1和第二时钟信号CK2的高正平为正直流电源电压VCC，低电平为地GND。Specifically, as an implementation manner, the first inverter and the second inverter have the same structure, and each is composed of an NMOS transistor and a PMOS transistor, and the drains of the NMOS transistor and the PMOS transistor are connected together. As an output of the inverter, the gates are connected together as an input of an inverter whose source and substrate are connected together to ground GND, the source of which is connected to the substrate Connect the DC positive supply voltage VCC. It can be seen that the first clock signal CK1 and the second clock signal CK2 are a pair of mutually inverted clock signals, and the high level of the first clock signal CK1 and the second clock signal CK2 is a positive DC power supply voltage VCC. The low level is ground GND.
请继续参考图3所示，所述电荷泵单元3由第一电容器C3和第二电容器C4构成，所述第一电容器C3的上极板连接所述时钟单元2输出的第一时钟信号CK1，所述第二电容器C4的上极板连接所述时钟单元2输出的第二时钟信号CK2，所述第一电容器C3的下极板连接所述充电单元1中第一PMOS晶体管P1的源极，所述第二电容器C4的下极板连接所述充电单元1中第二PMOS晶体管P2的源极。Referring to FIG. 3, the charge pump unit 3 is composed of a first capacitor C3 and a second capacitor C4. The upper plate of the first capacitor C3 is connected to the first clock signal CK1 output by the clock unit 2, The upper plate of the second capacitor C4 is connected to the second clock signal CK2 outputted by the clock unit 2, and the lower plate of the first capacitor C3 is connected to the source of the first PMOS transistor P1 of the charging unit 1. The lower plate of the second capacitor C4 is connected to the source of the second PMOS transistor P2 in the charging unit 1.
作为一优选实施例，请参考图5所示，所述第一电容器C3的上极板和下极板之间并联有第三PMOS晶体管P3，所述第二电容器C4的上极板和下极板之间并联有第四PMOS晶体管P4；所述第三PMOS晶体管P3的源极和栅极连接所述第一电容器C3的上极板，漏极连接所述第一电容器C3的下极板，衬底连接直流正电源电压VCC；所述第四PMOS晶体管P4的源极和栅极连接所述第二电容器C4的上极板，漏极连接所述第二电容器C4的下极板，衬底连接直流正电源电压VCC。本实施例中，在所述第一电容器C3的上极板和下极板之间增加了保护晶体管P3，以及在所述第二电容器C4的上极板和下极板之间增加了保护晶体管P4，所述晶体管P3和晶体管P4作为二极管连接的PMOS晶体管，用于防止第一电容器C3和第二电容器C4的下极板在初始态处于过高的电位，以免电路在启动过程中出现闭锁情况，同时也提高了电路的启动速度。As a preferred embodiment, as shown in FIG. 5, a third PMOS transistor P3 is connected in parallel between the upper and lower plates of the first capacitor C3, and the upper and lower poles of the second capacitor C4 are connected. a fourth PMOS transistor P4 is connected in parallel between the boards; a source and a gate of the third PMOS transistor P3 are connected to an upper plate of the first capacitor C3, and a drain is connected to a lower plate of the first capacitor C3. The substrate is connected to the DC positive power supply voltage VCC; the source and the gate of the fourth PMOS transistor P4 are connected to the upper plate of the second capacitor C4, and the drain is connected to the lower plate of the second capacitor C4, the substrate Connect the DC positive supply voltage VCC. In this embodiment, a protection transistor P3 is added between the upper and lower plates of the first capacitor C3, and a protection transistor is added between the upper and lower plates of the second capacitor C4. P4, the transistor P3 and the transistor P4 function as diode-connected PMOS transistors for preventing the lower plates of the first capacitor C3 and the second capacitor C4 from being at an excessively high potential in the initial state, so as to prevent the circuit from being locked during the startup process. At the same time, it also increases the startup speed of the circuit.
请继续参考图3所示，所述输出单元4由一对交叉耦合的第一深阱NMOS晶体管N3和第二深阱NMOS晶体管N4构成，所述第一深阱NMOS晶体管N3的漏极连接所述第二深阱NMOS晶体管N4的栅极，所述第二深阱NMOS晶体管N4的漏极连接第一深阱NMOS晶体管N3的棚极，所述第一深阱NMOS晶体管N3的衬底与其源极连接在一起，所述第二深阱NMOS晶体管N4的衬底与其源极连接在一起，所述第一深阱NMOS晶体管N3的源极和第二深阱NMOS晶体管N4的源极连接在一起构成输出单元4的输出端，输出直流负电压VD，所述第一深阱NMOS晶体管N3和第二深阱NMOS晶体管N4的漏极分别连接所述电荷泵单元3，具体所述第一深阱NMOS晶体管N3的漏极连接所述电荷泵单元3中第一电容器3的下极板，所述第二深阱NMOS晶体管N4的漏极连接所述电荷泵单元3中第二电容器4的下极板。Referring to FIG. 3, the output unit 4 is composed of a pair of cross-coupled first deep well NMOS transistor N3 and a second deep well NMOS transistor N4, and the drain connection of the first deep well NMOS transistor N3 The gate of the second deep well NMOS transistor N4, the drain of the second deep well NMOS transistor N4 is connected to the gate of the first deep well NMOS transistor N3, the substrate of the first deep well NMOS transistor N3 and its source The poles are connected together, the substrate of the second deep well NMOS transistor N4 is connected to its source, and the source of the first deep well NMOS transistor N3 is connected to the source of the second deep well NMOS transistor N4 Forming an output end of the output unit 4, outputting a DC negative voltage VD, the drains of the first deep well NMOS transistor N3 and the second deep well NMOS transistor N4 are respectively connected to the charge pump unit 3, specifically the first deep well a drain of the NMOS transistor N3 is connected to a lower plate of the first capacitor 3 of the charge pump unit 3, and a drain of the second deep well NMOS transistor N4 is connected to a lower pole of the second capacitor 4 of the charge pump unit 3. board.
请继续参考图3所示，所述电荷存储单元5由一大容量电容器Co构成，所述电容器Co的上极板接地，下极板连接所述输出单元4的输出端。本实施例中，所述大容量电容器Co用于存储被电荷泵单元3泵到负电位的电荷，同时稳定电压输出单元4输出的负电压。Referring to FIG. 3, the charge storage unit 5 is composed of a large-capacity capacitor Co. The upper plate of the capacitor Co is grounded, and the lower plate is connected to the output end of the output unit 4. In the present embodiment, the large-capacity capacitor Co is used to store the charge pumped to the negative potential by the charge pump unit 3 while stabilizing the negative voltage output from the voltage output unit 4.
作为又一具体实施例，请参考图6所示，所述电荷泵单元3由第三深阱NMOS晶体管N5和第四深阱NMOS晶体管N6构成，所述第三深阱NMOS晶体管N5的栅极连接所述时钟单元2输出的第一时钟信号CK1，所述第四深阱NMOS晶体管N6的栅极连接所述时钟单元2输出的第二时钟信号CK1，所述第三深阱NMOS晶体管N5的漏极、衬底和源极连接至所述充电单元1中第一PMOS晶体管P1的源极，所述第四深阱NMOS晶体管N6的漏极、衬底和源极连接至所述充电单元1中第二PMOS晶体管P2的源极；同时，所述电荷存储单元5由一大尺寸第五深阱NMOS晶体管N7构成，所述第五深阱NMOS晶体管N7的栅极接地，漏极、衬底和源极连接至所述输出单元4的输出端。本实施例中，在电路工作过程中，晶体管N5、N6、N7处于导通状态，这样，所述晶体管N5、N6、N7的栅极与它们的导电沟道间形成了极好的容性关系，能够代替电容工作；相比于图3所示的实施例电路，本实施例电路采用的器件类型更少，实际上只采用了PMOS和NMOS两种晶体管。这样，本实施例电路不仅可以在CMOS混合信号工艺条件下实现，甚至可以在不提供电容器件的数字CMOS工艺条件下实现。As another embodiment, as shown in FIG. 6, the charge pump unit 3 is composed of a third deep well NMOS transistor N5 and a fourth deep well NMOS transistor N6, and the gate of the third deep well NMOS transistor N5. Connecting the first clock signal CK1 outputted by the clock unit 2, the gate of the fourth deep-well NMOS transistor N6 is connected to the second clock signal CK1 output by the clock unit 2, and the third deep-well NMOS transistor N5 a drain, a substrate and a source are connected to a source of the first PMOS transistor P1 in the charging unit 1, and a drain, a substrate and a source of the fourth deep-well NMOS transistor N6 are connected to the charging unit 1 The source of the second PMOS transistor P2; at the same time, the charge storage unit 5 is composed of a large-sized fifth deep-well NMOS transistor N7, the gate of the fifth deep-well NMOS transistor N7 is grounded, the drain, the substrate And a source is connected to the output of the output unit 4. In this embodiment, during the operation of the circuit, the transistors N5, N6, and N7 are in an on state, so that the gates of the transistors N5, N6, and N7 form an excellent capacitive relationship with their conductive channels. It can work in place of the capacitor; compared to the embodiment circuit shown in FIG. 3, the circuit of this embodiment uses fewer types of devices, and actually only uses PMOS and NMOS transistors. Thus, the circuit of the present embodiment can be implemented not only under CMOS mixed-signal process conditions, but also under digital CMOS process conditions where no capacitive device is provided.
为了使本领域的技术人员更加全面和清楚地理解本发明提供的CMOS片上直流负电压产生电路，以下将对本发明的工作原理进行详细介绍。为了便于说明，本发明把所述充电单元1、时钟单元2和电荷泵单元3所构成电路部分称作负脉冲电压产生电路，所述负脉冲电压产生电路的工作原理如下：In order to enable those skilled in the art to more fully and clearly understand the CMOS on-chip DC negative voltage generating circuit provided by the present invention, the working principle of the present invention will be described in detail below. For convenience of explanation, the present invention refers to the circuit portion formed by the charging unit 1, the clock unit 2 and the charge pump unit 3 as a negative pulse voltage generating circuit, and the working principle of the negative pulse voltage generating circuit is as follows:
请参考图3和图4所示，所述负脉冲电压产生电路在外部时钟信号CLKIN的驱动下工作，在不损失一般性的情况下，假设所述外部时钟信号CLKIN初始电平为低电平GND。这样，所述时钟单元2的第一反相器输出的第一时钟信号CK1为高电平VCC，第二反相器输出的第二时钟信号CK2为低电平GND；所述电荷泵单元3的第一电容器C3的下极板电位V1和第二电容器C4的下极板电位V2不确定，但是它们之差不能大于PMOS晶体管的阈值电压，因为如果它们之差大于PMOS晶体管的阈值电压，所述充电单元1中的其中一个PMOS晶体管将导通并开始对电荷泵单元3相应电容器充电，使得它们之差小于或者等于PMOS晶体管的阈值电压。同样，在不损失一般性的情况下，假设所述电荷泵单元3的第一电容器C3的下极板和第二电容器C4的下极板的初始电位V1和V2相等，并处于所述直流正电源电压电位VCC。Referring to FIG. 3 and FIG. 4, the negative pulse voltage generating circuit operates under the driving of the external clock signal CLKIN, and the initial level of the external clock signal CLKIN is assumed to be low level without loss of generality. GND. Thus, the first clock signal CK1 outputted by the first inverter of the clock unit 2 is at a high level VCC, and the second clock signal CK2 outputted by the second inverter is at a low level GND; the charge pump unit 3 The lower plate potential V1 of the first capacitor C3 and the lower plate potential V2 of the second capacitor C4 are not determined, but the difference between them cannot be greater than the threshold voltage of the PMOS transistor, because if the difference therebetween is greater than the threshold voltage of the PMOS transistor, One of the PMOS transistors in the charging unit 1 will be turned on and begin to charge the respective capacitors of the charge pump unit 3 such that their difference is less than or equal to the threshold voltage of the PMOS transistor. Also, without loss of generality, it is assumed that the initial potentials V1 and V2 of the lower plate of the first capacitor C3 of the charge pump unit 3 and the lower plate of the second capacitor C4 are equal, and are in the DC positive Power supply voltage potential VCC.
请继续参考图3和图4所示，经过半个时钟周期后，所述外部时钟信号CLKIN发生翻转，由低电平变为高电平。所述第一时钟信号CK1由高电平变为低电平，使得所述第一电容器C3下极板电位V1由直流正电源电压电位VCC变为地电位GND；同时，所述第二时钟信号CK2由低电平变为高电平，使得所述第二电容器C4下极板电位V2由直流正电源电压电位VCC变为2倍于直流正电源电压电位2VCC。这时，所述充电单元1的第二PMOS晶体管P2开启，对所述第二电容器C4充电，直到所述第二电容器C4的下极板电位达到一个PMOS晶体管阈值电压电位。Referring to FIG. 3 and FIG. 4, after half a clock cycle, the external clock signal CLKIN flips from low level to high level. The first clock signal CK1 is changed from a high level to a low level, so that the lower plate potential V1 of the first capacitor C3 is changed from the DC positive power supply voltage potential VCC to the ground potential GND; meanwhile, the second clock signal CK2 changes from a low level to a high level, so that the second capacitor C4 lower plate potential V2 is doubled from the direct current power supply voltage potential VCC by a direct current positive power supply voltage potential of 2VCC. At this time, the second PMOS transistor P2 of the charging unit 1 is turned on, and the second capacitor C4 is charged until the lower plate potential of the second capacitor C4 reaches a PMOS transistor threshold voltage potential.
请继续参考图3和图4所示，再经过半个时钟周期后，所述外部时钟信号CLKIN再次发生翻转，由高电平变为低电平。所述第一时钟信号CK1由低电平变为高电平，使得所述第一电容器C3下极板电位V1由地电位GND变为直流正电源电压电位VCC；同时，所述第二时钟信号CK2由高电平变为低电平，使得所述第二电容器C4下极板电位V2下降了一个直流正电源电压电位VCC，由一个PMOS晶体管阈值电压电位变为大小等于直流正电源电压减去一个PMOS晶体管阈值电压的负电位。这时，所述充电单元1的第一PMOS晶体管P1开启，对所述第一电容器C3充电，直到所述第一电容器C3的下极板电位达到地电位。Please continue to refer to FIG. 3 and FIG. 4, after another half clock cycle, the external clock signal CLKIN is inverted again, from a high level to a low level. The first clock signal CK1 changes from a low level to a high level, so that the lower plate potential V1 of the first capacitor C3 is changed from the ground potential GND to a DC positive power supply voltage potential VCC; meanwhile, the second clock signal CK2 changes from a high level to a low level, so that the second capacitor C4 lower plate potential V2 drops by a DC positive power supply voltage potential VCC, and the threshold voltage potential of a PMOS transistor becomes equal to the DC positive power supply voltage minus The negative potential of a PMOS transistor threshold voltage. At this time, the first PMOS transistor P1 of the charging unit 1 is turned on, and the first capacitor C3 is charged until the potential of the lower plate of the first capacitor C3 reaches the ground potential.
请继续参考图3和图4所示，又经过半个时钟周期后，所述外部时钟信号CLKIN再次发生翻转，由低电平变为高电平。所述第一时钟信号CK1由高电平变为低电平，使得所述第一电容器C3下极板电位V1由地电位变为大小等于直流正电源电压的负电位-VCC；同时，所述第二时钟信号CK2由低电平变为高电平，使得所述第二电容器C4下极板电位V2上升了一个直流正电源电压电位，再次回到一个PMOS晶体管阈值电压电位。这时，所述充电单元1的第二PMOS晶体管P2开启，对所述第二电容器C4充电，直到所述第二电容器C4的下极板电位达到地电位GND。Please continue to refer to FIG. 3 and FIG. 4, after another half clock cycle, the external clock signal CLKIN flips again, from low level to high level. The first clock signal CK1 is changed from a high level to a low level, so that the lower plate potential V1 of the first capacitor C3 is changed from a ground potential to a negative potential -VCC equal to a DC positive power supply voltage; The second clock signal CK2 changes from a low level to a high level, so that the lower plate potential V2 of the second capacitor C4 rises by a DC positive power supply voltage potential, and returns to a PMOS transistor threshold voltage potential again. At this time, the second PMOS transistor P2 of the charging unit 1 is turned on, and the second capacitor C4 is charged until the potential of the lower plate of the second capacitor C4 reaches the ground potential GND.
请继续参考图3和图4所示，还经过半个时钟周期后，所述外部时钟信号CLKIN再次发生翻转，由高电平变为低电平。所述第一时钟信号CK1由低电平变为高电平，使得所述第一电容器C3下极板电位V1上升了一个直流正电源电压VCC，回到地电位GND；同时，所述第二时钟信号CK2由高电平变为低电平，使得所述第二电容器C4下极板电位V2下降了一个直流正电源电压电位，达到大小等于直流正电源电压的负电位-VCC。自此以后，在外部时钟信号周期性驱动下，所述电荷泵单元3的第一电容器C3和第二电容器C4的下极板交替处于地电位GND和大小等于直流正电源电压的负电位-VCC。至此，本发明把所述第一电容器C3的下极板电压信号称作第一脉冲电压信号，所述第二电容器C4的下极板电压信号称作第二脉冲电压信号，且由前面的结构描述可知，它们分别被接入所述输出单元4的第一深阱NMOS晶体管N3和第二深阱NMOS晶体管N4。Referring to FIG. 3 and FIG. 4 again, after half a clock cycle, the external clock signal CLKIN is flipped again, from a high level to a low level. The first clock signal CK1 changes from a low level to a high level, so that the lower plate potential V1 of the first capacitor C3 rises by a DC positive power supply voltage VCC, and returns to the ground potential GND; meanwhile, the second The clock signal CK2 is changed from a high level to a low level, so that the lower plate potential V2 of the second capacitor C4 is lowered by a DC positive power supply voltage potential to a negative potential -VCC equal to the DC positive power supply voltage. Thereafter, after the external clock signal is periodically driven, the lower plates of the first capacitor C3 and the second capacitor C4 of the charge pump unit 3 are alternately at the ground potential GND and a negative potential equal to the DC positive supply voltage -VCC . So far, the present invention refers to the lower plate voltage signal of the first capacitor C3 as the first pulse voltage signal, and the lower plate voltage signal of the second capacitor C4 as the second pulse voltage signal, and is constituted by the foregoing structure. The description shows that they are respectively connected to the first deep well NMOS transistor N3 and the second deep well NMOS transistor N4 of the output unit 4.
下面将给出所述输出单元和电荷存储单元部分的工作原理：The operation of the output unit and the charge storage unit portion will be given below:
由上面的分析可知，所述第一脉冲电压信号V1和第二脉冲电压信号V2交替处于地电位GND和大小等于直流正电源电压的负电位-VCC。当所述第一脉冲电压信号V1处于地电位GND，第二脉冲电压信号V2处于负电位-VCC时，所述输出单元4的第一深阱NMOS晶体管N3截止，第二深阱NMOS晶体管N4导通；第二脉冲电压信号V2通过第二深阱NMOS晶体管N4给所述电荷存储单元5的大容量电容Co充电。当所述第一脉冲电压信号V1处于负电位-VCC，第二脉冲电压信号V2处于地电位GND时，所述输出单元4的第一深阱NMOS晶体管N3导通，第二深阱NMOS晶体管N4截止；第一脉冲电压信号V1通过第一深阱NMOS晶体管N3给所述电荷存储单元5的大容量电容Co充电。就这样，所述第一负脉冲电压信号和第二负脉冲电压信号交替地给大容量电容Co充电，直到输出电压VD达到-VCC，具体请参考图4所示；之后，所述输出电压VD将一直保持在-VCC电位。As can be seen from the above analysis, the first pulse voltage signal V1 and the second pulse voltage signal V2 are alternately at the ground potential GND and a negative potential -VCC equal to the DC positive power supply voltage. When the first pulse voltage signal V1 is at the ground potential GND and the second pulse voltage signal V2 is at the negative potential -VCC, the first deep well NMOS transistor N3 of the output unit 4 is turned off, and the second deep well NMOS transistor N4 is turned on. The second pulse voltage signal V2 charges the bulk capacitor Co of the charge storage unit 5 through the second deep well NMOS transistor N4. When the first pulse voltage signal V1 is at a negative potential -VCC and the second pulse voltage signal V2 is at a ground potential GND, the first deep well NMOS transistor N3 of the output unit 4 is turned on, and the second deep well NMOS transistor N4 is turned on. The first pulse voltage signal V1 charges the bulk capacitor Co of the charge storage unit 5 through the first deep well NMOS transistor N3. In this way, the first negative pulse voltage signal and the second negative pulse voltage signal alternately charge the large capacity capacitor Co until the output voltage VD reaches -VCC, as shown in FIG. 4; afterwards, the output voltage VD Will remain at -VCC potential all the time.
以上仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构，直接或间接运用在其他相关的技术领域，均同理在本发明的专利保护范围之内。The above is only the embodiment of the present invention, and is not intended to limit the scope of the invention, and the equivalent structure made by the specification and the drawings of the present invention is directly or indirectly applied to other related technical fields. Within the scope of patent protection.

Claims (9)

  1. 一种CMOS片上直流负电压产生电路，其特征在于，包括充电单元、时钟单元、电荷泵单元、输出单元和电荷存储单元；其中，A CMOS on-chip DC negative voltage generating circuit, comprising: a charging unit, a clock unit, a charge pump unit, an output unit, and a charge storage unit; wherein
    所述充电单元，用于向所述电荷泵单元充电；The charging unit is configured to charge the charge pump unit;
    所述时钟单元，用于向所述电荷泵单元提供所需时钟信号；The clock unit is configured to provide a required clock signal to the charge pump unit;
    所述电荷泵单元，用于产生幅度大小等于正电源电压的负脉冲电压；The charge pump unit is configured to generate a negative pulse voltage having an amplitude equal to a positive power supply voltage;
    所述输出单元，用于把所述电荷泵单元产生的负脉冲电压转换成直流负电压，该直流负电压的大小等于正电源电压；The output unit is configured to convert a negative pulse voltage generated by the charge pump unit into a DC negative voltage, the magnitude of the DC negative voltage being equal to a positive power supply voltage;
    所述电荷存储单元，用于存储被所述电荷泵单元带到负电位的电荷，同时使所述输出单元输出的直流负电压在CMOS芯片工作过程中保持稳定。The charge storage unit is configured to store the charge brought to the negative potential by the charge pump unit while the DC negative voltage output by the output unit is stable during the operation of the CMOS chip.
  2. 根据权利要求1所述的CMOS片上直流负电压产生电路，其特征在于，所述充电单元由一对交叉耦合的第一PMOS晶体管和第二PMOS晶体管构成，所述第一PMOS晶体管的源极连接第二PMOS晶体管的栅极，所述第二PMOS晶体管的源极连接第一PMOS晶体管的栅极，所述第一PMOS晶体管和第二PMOS晶体管的漏极均接地GND，所述第一PMOS晶体管和第二PMOS晶体管的衬底均连接直流正电源电压VCC，所述第一PMOS晶体管和第二PMOS晶体管的源极分别连接所述电荷泵单元，在电路工作过程中轮流给所述电荷泵单元充电。The CMOS on-chip DC negative voltage generating circuit according to claim 1, wherein said charging unit is constituted by a pair of cross-coupled first PMOS transistors and second PMOS transistors, and source connection of said first PMOS transistors a gate of the second PMOS transistor, a source of the second PMOS transistor is connected to a gate of the first PMOS transistor, and a drain of the first PMOS transistor and the second PMOS transistor are both grounded to a GND, the first PMOS transistor And a substrate of the second PMOS transistor is connected to the DC positive power supply voltage VCC, the sources of the first PMOS transistor and the second PMOS transistor are respectively connected to the charge pump unit, and are alternately supplied to the charge pump unit during circuit operation Charging.
  3. 根据权利要求1所述的CMOS片上直流负电压产生电路，其特征在于，所述时钟单元由一对串行连接的第一反相器和第二反相器构成，所述第一反相器的输入端接收外部时钟信号CLKIN，输出端连接所述第二反相器的输入端并输出第一时钟信号CK1；所述第二反相器的输出端输出第二时钟信号CK2，所述第一时钟信号CK1和第二时钟信号CK2均连接至所述电荷泵单元。The CMOS on-chip DC negative voltage generating circuit according to claim 1, wherein said clock unit is constituted by a pair of serially connected first inverters and second inverters, said first inverter The input terminal receives the external clock signal CLKIN, the output terminal is connected to the input end of the second inverter and outputs a first clock signal CK1; the output terminal of the second inverter outputs a second clock signal CK2, A clock signal CK1 and a second clock signal CK2 are both connected to the charge pump unit.
  4. 根据权利要求3所述的CMOS片上直流负电压产生电路，其特征在于，所述第一反相器和第二反相器具有相同的结构，均由一NMOS晶体管和PMOS晶体管构成，所述NMOS晶体管和PMOS晶体管的漏极连接到一起作为反相器的输出端，栅极连接到一起作为反相器的输入端，所述NMOS晶体管的源极和衬底连接到一起接地GND，所述PMOS晶体管的源极和衬底连接到一起接直流正电源电压VCC。The CMOS on-chip DC negative voltage generating circuit according to claim 3, wherein said first inverter and said second inverter have the same structure, each of which is composed of an NMOS transistor and a PMOS transistor, said NMOS The drains of the transistors and PMOS transistors are connected together as the output of the inverter, the gates are connected together as the input of the inverter, the source of the NMOS transistor and the substrate are connected together to ground GND, the PMOS The source of the transistor and the substrate are connected together to a DC positive supply voltage VCC.
  5. 根据权利要求1所述的CMOS片上直流负电压产生电路，其特征在于，所述电荷泵单元由第一电容器和第二电容器构成，所述第一电容器的上极板连接所述时钟单元输出的第一时钟信号CK1，所述第二电容器的上极板连接所述时钟单元输出的第二时钟信号CK2，所述第一电容器的下极板连接所述充电单元中第一PMOS晶体管的源极，所述第二电容器的下极板连接所述充电单元中第二PMOS晶体管的源极。The CMOS on-chip DC negative voltage generating circuit according to claim 1, wherein said charge pump unit is composed of a first capacitor and a second capacitor, and an upper plate of said first capacitor is connected to said clock unit output a first clock signal CK1, an upper plate of the second capacitor is connected to a second clock signal CK2 output by the clock unit, and a lower plate of the first capacitor is connected to a source of the first PMOS transistor in the charging unit The lower plate of the second capacitor is connected to the source of the second PMOS transistor in the charging unit.
  6. 根据权利要求5所述的CMOS片上直流负电压产生电路，其特征在于，所述第一电容器的上极板和下极板之间并联有第三PMOS晶体管，所述第二电容器的上极板和下极板之间并联有第四PMOS晶体管；所述第三PMOS晶体管的源极和栅极连接所述第一电容器的上极板，漏极连接所述第一电容器的下极板，衬底连接直流正电源电压VCC；所述第四PMOS晶体管的源极和栅极连接所述第二电容器的上极板，漏极连接所述第二电容器的下极板，衬底连接直流正电源电压VCC。The CMOS on-chip DC negative voltage generating circuit according to claim 5, wherein a third PMOS transistor is connected in parallel between the upper plate and the lower plate of the first capacitor, and an upper plate of the second capacitor And a fourth PMOS transistor connected in parallel with the lower plate; a source and a gate of the third PMOS transistor are connected to an upper plate of the first capacitor, and a drain is connected to a lower plate of the first capacitor, and lining The bottom is connected to the DC positive power supply voltage VCC; the source and the gate of the fourth PMOS transistor are connected to the upper plate of the second capacitor, the drain is connected to the lower plate of the second capacitor, and the substrate is connected to the DC positive power supply Voltage VCC.
  7. 根据权利要求1所述的CMOS片上直流负电压产生电路，其特征在于，所述输出单元由一对交叉耦合的第一深阱NMOS晶体管和第二深阱NMOS晶体管构成，所述第一深阱NMOS晶体管的漏极连接所述第二深阱NMOS晶体管的栅极，所述第二深阱NMOS晶体管的漏极连接第一深阱NMOS晶体管的棚极，所述第一深阱NMOS晶体管的衬底与其源极连接在一起，所述第二深阱NMOS晶体管的衬底与其源极连接在一起，所述第一深阱NMOS晶体管的源极和第二深阱NMOS晶体管的源极连接在一起构成输出单元的输出端，输出直流负电压VD，所述第一深阱NMOS晶体管和第二深阱NMOS晶体管的漏极分别连接所述电荷泵单元。The CMOS on-chip DC negative voltage generating circuit according to claim 1, wherein said output unit is constituted by a pair of cross-coupled first deep well NMOS transistors and second deep well NMOS transistors, said first deep well a drain of the NMOS transistor is connected to a gate of the second deep-well NMOS transistor, and a drain of the second deep-well NMOS transistor is connected to a gate of the first deep-well NMOS transistor, the lining of the first deep-well NMOS transistor The bottom is connected to its source, the substrate of the second deep well NMOS transistor is connected to its source, and the source of the first deep well NMOS transistor is connected to the source of the second deep well NMOS transistor The output terminal constituting the output unit outputs a DC negative voltage VD, and the drains of the first deep well NMOS transistor and the second deep well NMOS transistor are respectively connected to the charge pump unit.
  8. 根据权利要求1所述的CMOS片上直流负电压产生电路，其特征在于，所述电荷存储单元由一大容量电容器Co构成，所述电容器Co的上极板接地，下极板连接所述输出单元的输出端。The CMOS on-chip DC negative voltage generating circuit according to claim 1, wherein said charge storage unit is constituted by a large-capacity capacitor Co, an upper plate of said capacitor Co is grounded, and a lower plate is connected to said output unit. The output.
  9. 据权利要求1所述的CMOS片上直流负电压产生电路，其特征在于，所述电荷泵单元由第三深阱NMOS晶体管和第四深阱NMOS晶体管构成，所述第三深阱NMOS晶体管的栅极连接所述时钟单元输出的第一时钟信号CK1，所述第四深阱NMOS晶体管的栅极连接所述时钟单元输出的第二时钟信号CK1，所述第三深阱NMOS晶体管的漏极、衬底和源极连接至所述充电单元中第一PMOS晶体管的源极，所述第四深阱NMOS晶体管的漏极、衬底和源极连接至所述充电单元中第二PMOS晶体管的源极；同时，A CMOS on-chip DC negative voltage generating circuit according to claim 1, wherein said charge pump unit is constituted by a third deep well NMOS transistor and a fourth deep well NMOS transistor, and a gate of said third deep well NMOS transistor a pole connected to the first clock signal CK1 output by the clock unit, a gate of the fourth deep-well NMOS transistor connected to a second clock signal CK1 output by the clock unit, a drain of the third deep-well NMOS transistor, a substrate and a source connected to a source of the first PMOS transistor in the charging unit, a drain, a substrate and a source of the fourth deep well NMOS transistor being connected to a source of the second PMOS transistor in the charging unit Extremely; at the same time,
    所述电荷存储单元由一大尺寸第五深阱NMOS晶体管构成，所述第五深阱NMOS晶体管的栅极接地，漏极、衬底和源极连接至所述输出单元的输出端。The charge storage unit is formed by a large size fifth deep well NMOS transistor having a gate grounded, a drain, a substrate and a source connected to an output of the output unit.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109756107A (en) * 2019-01-31 2019-05-14 深圳市爱协生科技有限公司 A kind of efficient charge pump circuit structure

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105159372B (en) * 2015-08-24 2017-03-22 锐迪科创微电子（北京）有限公司 Negative voltage generation circuit
CN105529907A (en) * 2015-12-11 2016-04-27 中国航空工业集团公司西安航空计算技术研究所 DC-DC negative voltage generation circuit and method
DE102016109118A1 (en) 2016-05-18 2017-11-23 Infineon Technologies Ag Circuit architecture for a measuring device, a level converter circuit, a charge pumping stage and a charge pump and method for operating these
DE102016109114A1 (en) * 2016-05-18 2017-11-23 Infineon Technologies Ag Circuit architecture for a measuring device, a level converter circuit, a charge pumping stage and a charge pump and method for operating these
CN105929885B (en) * 2016-06-15 2017-07-11 深圳市飞仙智能科技有限公司 A kind of circuit for generating negative voltage and integrated chip
CN107070202B (en) * 2017-04-19 2019-06-04 中国电子科技集团公司第二十四研究所 Circuit for generating negative voltage with voltage automatic regulation function
US10461636B2 (en) 2017-10-23 2019-10-29 Stmicroelectronics International N.V. Voltage multiplier circuit with a common bulk and configured for positive and negative voltage generation
CN108230984B (en) * 2018-01-22 2021-11-16 京东方科技集团股份有限公司 Low-level voltage signal generator, gate drive circuit and display panel
CN110572027B (en) * 2019-09-02 2020-11-24 上海华虹宏力半导体制造有限公司 Charge pump circuit
CN113110684B (en) * 2021-03-30 2022-05-17 东方微电科技(武汉)有限公司 Power supply voltage output integrated circuit for magnetic sensing
CN114189147B (en) * 2021-12-13 2024-05-10 成都锐成芯微科技股份有限公司 Charge pump circuit and memory

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6515903B1 (en) * 2002-01-16 2003-02-04 Advanced Micro Devices, Inc. Negative pump regulator using MOS capacitor
CN101110257A (en) * 2006-07-18 2008-01-23 钰创科技股份有限公司 Negative voltage generator
US20100039170A1 (en) * 2008-08-12 2010-02-18 Samsung Electronics Co., Ltd. Negative supply voltage generating circuit and semiconductor integrated circuit having the same
CN101860368A (en) * 2010-05-10 2010-10-13 中国电子科技集团公司第五十八研究所 Negative-voltage effective transmission circuit suitable for standard CMOS process
JP2013021817A (en) * 2011-07-11 2013-01-31 Renesas Electronics Corp Charge pump circuit

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100208443B1 (en) * 1995-10-14 1999-07-15 김영환 Negative voltage drive circuit
CN1114265C (en) * 1999-09-03 2003-07-09 北京大学 New-type CMOS charge pump and its cascade method
TW486869B (en) * 1999-12-27 2002-05-11 Sanyo Electric Co Voltage producing circuit and a display device provided with such voltage producing circuit
US7466190B2 (en) * 2006-07-24 2008-12-16 Lattice Semiconductor Corporation Charge pump with four-well transistors
CN101674009A (en) * 2008-09-10 2010-03-17 中芯国际集成电路制造(上海)有限公司 Charge pump output voltage regulation circuit
CN101888181B (en) * 2010-08-02 2012-09-05 中国电子科技集团公司第二十四研究所 Charge pump circuit based on feedback
US8456225B1 (en) * 2011-12-27 2013-06-04 Fairchild Semiconductor Corporation Negative charge pump
CN102624222B (en) * 2012-03-27 2017-03-29 上海华虹宏力半导体制造有限公司 charge pump and charge pump system
US20140097887A1 (en) * 2012-10-10 2014-04-10 Semtech Corporation Reduction or elimination of irregular voltage distribution in a ladder of voltage elevators

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6515903B1 (en) * 2002-01-16 2003-02-04 Advanced Micro Devices, Inc. Negative pump regulator using MOS capacitor
CN101110257A (en) * 2006-07-18 2008-01-23 钰创科技股份有限公司 Negative voltage generator
US20100039170A1 (en) * 2008-08-12 2010-02-18 Samsung Electronics Co., Ltd. Negative supply voltage generating circuit and semiconductor integrated circuit having the same
CN101860368A (en) * 2010-05-10 2010-10-13 中国电子科技集团公司第五十八研究所 Negative-voltage effective transmission circuit suitable for standard CMOS process
JP2013021817A (en) * 2011-07-11 2013-01-31 Renesas Electronics Corp Charge pump circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109756107A (en) * 2019-01-31 2019-05-14 深圳市爱协生科技有限公司 A kind of efficient charge pump circuit structure

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