WO2016107140A1 - 一种阵列基板及其制备方法、显示面板及显示装置 - Google Patents

一种阵列基板及其制备方法、显示面板及显示装置 Download PDF

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Publication number
WO2016107140A1
WO2016107140A1 PCT/CN2015/084210 CN2015084210W WO2016107140A1 WO 2016107140 A1 WO2016107140 A1 WO 2016107140A1 CN 2015084210 W CN2015084210 W CN 2015084210W WO 2016107140 A1 WO2016107140 A1 WO 2016107140A1
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Prior art keywords
array substrate
terminal
junction
voltage
data line
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PCT/CN2015/084210
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English (en)
French (fr)
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乔赟
孙建
李成
安星俊
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京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to EP15832875.7A priority Critical patent/EP3242159A4/en
Priority to US14/906,350 priority patent/US9651838B2/en
Publication of WO2016107140A1 publication Critical patent/WO2016107140A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to an array substrate, a method for fabricating the same, a display panel, and a display device.
  • LTPS low temperature polysilicon
  • TFT LCD thin film transistor liquid crystal display
  • LTPS technology has the advantages of high resolution, fast response, high brightness and high aperture ratio. Based on the above advantages, LTPS technology has become one of the development directions of TFT LCD.
  • the LTPS technology is more complicated, making the TFT LCD with LTPS technology a lower yield.
  • static electricity is more likely to be generated. Therefore, in order to improve the Electro-Static Discharge (ESD) capability, TFT LCDs using LTPS technology generally Set the ESD loop to avoid damage to the TFT LCD due to ESD.
  • ESD Electro-Static Discharge
  • FIG. 1 is a schematic diagram of an ESD loop in a TFT LCD using LTPS technology.
  • the ESD circuit includes first and second transistors.
  • the gate G and the drain D of the first transistor are connected to the data line DATA, and the source S is connected to the high voltage terminal VDD on the array substrate.
  • the voltage on the high voltage terminal VDD is the highest positive voltage VGH of the TFT LCD display panel;
  • the source S of the second transistor is connected to the data line DATA, and the gate G and the drain D are connected to the low voltage terminal VSS.
  • the voltage at the low voltage terminal VSS is the lowest negative voltage VGL at which the display panel of the TFT LCD operates normally.
  • 2 is a structural view of the TFT LCD shown in FIG. 1. As shown in FIG.
  • the source S and the drain D of the first and second transistors are connected by polysilicon disposed on the array substrate, and the end of the polysilicon connected to the source S and the drain D is N-type high.
  • the concentration is doped, and a P-type low concentration doping is performed between the two ends.
  • the gate G and the drain D of the first transistor are connected to the gate G and the drain D of the second transistor, both of them are equivalent to a one-way diode.
  • the first transistor When static electricity is generated such that the voltage on the data line DATA is higher than VGH, the first transistor is turned on, connecting the data line DATA to the high voltage terminal VDD, so that the voltage on the data line DATA is not higher than VGH;
  • the second transistor When the voltage on the data line DATA is lower than VGL, the second transistor is turned on, and the data line DATA is connected to the low voltage terminal VSS, so that the voltage on the data line DATA is not lower than VGL.
  • the first and second transistors When the voltage on the data line DATA is between VGH and VGL, the first and second transistors are turned off, so that the high voltage terminal VDD and the low voltage terminal VSS do not affect the voltage on the data line DATA.
  • a first transistor and a second transistor equivalently connected to the gate G and the drain D are connected between the data line DATA and the high voltage terminal VDD and the low voltage terminal VSS.
  • the preparation process of the array substrate is not increased (the first transistor, the second transistor are simultaneously prepared with the thin film transistor in each pixel unit).
  • N-type high concentration doping is performed on both ends of the polysilicon, a large leakage current is generated between the source S and the drain D of the first and second transistors, which may cause work of the TFT LCD during operation. High consumption.
  • the present invention aims to solve at least one of the above technical problems existing in the prior art, and provides an array substrate, a preparation method thereof, a display panel and a display device.
  • the array substrate, display panel and display device of the present invention have lower power consumption.
  • an array substrate comprising a substrate, and a data line, a switching device and a voltage compensation module disposed on the substrate, the switching device being connected to the data line and the voltage compensation module Between the data line and the voltage compensation module being turned on when the voltage on the data line is lower than a preset low voltage or higher than a preset high voltage; the switching device is formed by at least one PN structure .
  • the voltage compensation module includes a high voltage terminal and a low voltage terminal, the voltage of the high voltage terminal is the preset high voltage, and the voltage of the low voltage terminal is the preset low voltage.
  • the switching device comprises a first PN junction and a second PN junction
  • the P terminal of the first PN junction is connected to the data line
  • the N terminal is connected to the high voltage terminal
  • the P terminal of the second PN junction is low
  • the voltage terminal is connected, and the N terminal is connected to the data line.
  • the voltage compensation module includes a high voltage terminal, and the voltage of the high voltage terminal is the predetermined high voltage; the switching device is formed by a PN structure, and the P terminal of the PN junction is connected to the data line, and the N terminal Connected to the high voltage side.
  • the PN junction conducts the data line to the high voltage terminal when the voltage on the data line is above a predetermined high voltage.
  • the voltage compensation module includes a low voltage terminal, the voltage of the low voltage terminal is the preset low voltage; the switching device is formed by a PN structure, and the P terminal of the PN junction is connected to the low voltage terminal, N The end is connected to the data line.
  • the PN junction conducts the data line to the low voltage terminal when the voltage on the data line is below a predetermined low voltage.
  • the P terminal and the N terminal of the PN junction are prepared by performing P-type high concentration doping and N-type high concentration doping on both ends of polysilicon or single crystal silicon, respectively.
  • the array substrate further comprises a light blocking layer prepared on the substrate, the light blocking layer being disposed directly under the PN junction.
  • the array substrate includes an effective display area and a frame area surrounding the effective display area, and the PN junction and the voltage compensation module are disposed in the frame area.
  • each of the pixel units on the array substrate is further provided with a thin film transistor, and the PN junction is formed in the process of preparing the thin film transistor.
  • the present invention further provides a method for preparing an array substrate, which is used for preparing the above array substrate provided by the present invention, and the method for preparing the array substrate comprises:
  • the step of preparing at least one PN junction connected to the data line and voltage compensation module on the substrate is a step of preparing at least one PN junction connected to the data line and voltage compensation module on the substrate.
  • the steps of preparing the PN junction include:
  • P-type high concentration doping and N-type high concentration doping are respectively performed on both ends of the polysilicon or single crystal silicon layer.
  • the method for preparing the array substrate further includes the steps of preparing a thin film transistor on a substrate;
  • the PN junction is prepared during the process of preparing the thin film transistor.
  • the method further comprises the step of preparing a light blocking layer on the substrate before preparing the PN junction.
  • the PN junction is disposed directly above the light blocking layer.
  • the present invention further provides a display panel comprising an array substrate and a counter substrate, wherein the array substrate adopts the above array substrate provided by the present invention.
  • the present invention further provides a display device comprising a display panel, wherein the display panel adopts the above display panel provided by the present invention.
  • the array substrate provided by the invention adopts a PN junction as a switching device connected between the data line and the voltage compensation module, and the P terminal of the PN junction is compared with the thin film transistor structure in which the gate and the drain are connected in the prior art.
  • the leakage current between the N terminals is smaller, so that the power consumption of the array substrate provided by the present invention is smaller.
  • the invention provides a method for preparing an array substrate, wherein a PN junction connected to a data line and a voltage compensation module is prepared as a switching device on a substrate, so that leakage current in the switching device is smaller, thereby preparing the array substrate provided by the invention.
  • the array substrate prepared by the method has lower power consumption.
  • the display panel provided by the present invention can reduce power consumption by using the above array substrate provided by the present invention.
  • the display device provided by the present invention can reduce power consumption by using the above display panel provided by the present invention.
  • FIG. 1 is a schematic diagram of an ESD loop in a TFT LCD using LTPS technology
  • FIG. 2 is a structural view of the TFT LCD shown in FIG. 1;
  • FIG. 3 is a schematic structural view of an embodiment of an array substrate provided by the present invention.
  • FIG. 4 is a circuit diagram of an ESD loop of the array substrate shown in FIG. 3;
  • Figure 5 is a circuit diagram of a first alternative of the ESD loop of Figure 4.
  • FIG. 6 is a circuit diagram of a second alternative to the ESD loop of FIG.
  • FIG. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention
  • FIG. 4 is a circuit diagram of an ESD loop of the array substrate shown in FIG.
  • the array substrate 1 includes a substrate 10, and a data line DATA, a switching device, and a voltage compensation module 12 disposed on the substrate 10.
  • the switching device is connected between the data line DATA and the voltage compensation module 12,
  • the data line DATA is turned on with the voltage compensation module 12 when the voltage on the data line DATA is lower than the preset low voltage or higher than the preset high voltage;
  • the switching device is constituted by at least one PN junction 11.
  • the preset high voltage may be the highest working positive voltage VGH of the array substrate 1, that is, the highest positive voltage allowed for the normal operation of the array substrate 1
  • the preset low voltage may be the lowest working negative voltage VGL of the array substrate 1, That is, the lowest negative voltage allowed by the array substrate 1 for normal operation; of course, the preset high voltage may also be set to a voltage value smaller than the highest working positive voltage VGH, and the preset low voltage may also be set to be greater than the minimum operation.
  • the voltage value of the negative voltage VGL may be the highest working positive voltage VGH of the array substrate 1, that is, the highest positive voltage allowed for the normal operation of the array substrate 1
  • the preset low voltage may be the lowest working negative voltage VGL of the array substrate 1, That is, the lowest negative voltage allowed by the array substrate 1 for normal operation
  • the preset high voltage may also be set to a voltage value smaller than the highest working positive voltage VGH
  • the preset low voltage may also be set to be greater than the minimum operation.
  • the voltage compensation module 12 when static electricity is generated on the array substrate 1, thereby causing the voltage on the data line DATA to be higher than a preset high voltage or lower than a preset low voltage, the voltage compensation module 12 is electrically connected to the data line DATA through the turned-on PN junction, so that the voltage on the data line DATA is not higher than the preset high voltage or lower than the preset low voltage, or the voltage on the data line DATA is neither higher than Presetting the high voltage, and not lower than the preset low voltage, so that the voltage on the data line DATA is within or within the normal working range, avoiding the array substrate 1 due to electrostatic discharge and applying the array substrate The display panel and display device of 1 are damaged.
  • the leakage current between the P terminal and the N terminal of the PN junction is smaller than that of the two N-type high concentration doped ends in the prior art, so that the array substrate 1 and the array substrate 1 can be used.
  • the power consumption of the display panel and the display device is low.
  • the voltage compensation module 12 includes a high voltage terminal VDD and a low voltage terminal VSS, and a voltage on the high voltage terminal VDD is equal to the preset high voltage, the low voltage.
  • the voltage at terminal VSS is equal to the predetermined low voltage.
  • the at least one PN junction 11 includes a first PN junction 110 and a second PN junction 111.
  • the P terminal of the first PN junction 110 is connected to the data line DATA, and the N terminal is connected to the high voltage terminal VDD, thereby making the data line DATA
  • the first PN junction 110 can be turned on to electrically connect the data line DATA with the high voltage terminal VDD;
  • the P terminal of the second PN junction 111 is connected to the low voltage terminal VSS, N
  • the second PN junction 111 can be turned on to electrically connect the data line DATA to the low voltage terminal VSS.
  • the voltage compensation module 12 may include at least a high voltage terminal VDD (which may or may not include a low voltage terminal VSS); as in the above embodiment,
  • the voltage of the high voltage terminal VDD is also the predetermined high voltage; in this case, the switching device is constituted by a PN junction 11, the P terminal of the PN junction 11 is connected to the data line DATA, and the N terminal is connected to the high voltage. Terminal VDD connection.
  • the PN junction 11 when the voltage on the data line DATA is higher than the preset high voltage, the PN junction 11 can be turned on to electrically connect the data line DATA with the high voltage terminal VDD.
  • the voltage compensation module 12 may include at least a low voltage terminal VSS (which may or may not include a high voltage terminal VDD); same as the above embodiment.
  • the voltage of the low voltage terminal VSS is also the predetermined low voltage; in this case, the switching device is composed of a PN junction 11, the P terminal of the PN junction 11 is connected to the low voltage terminal VSS, and the N terminal is Data line DATA Pick up.
  • the PN junction 11 when the voltage on the data line DATA is lower than the preset low voltage, the PN junction 11 can be turned on to electrically connect the data line DATA to the low voltage terminal VSS.
  • the P terminal (P+ region in FIG. 3) and the N terminal (N+ region in FIG. 3) of the PN junction 11 are respectively subjected to P-type high concentration doping and N at both ends of polysilicon or single crystal silicon.
  • Type high concentration doping preparation there is a space (P-region in FIG. 3) between the P terminal and the N terminal of the PN junction 11, and the spacer region is subjected to P-type low concentration doping.
  • the array substrate 1 further includes a light blocking layer 13 prepared on the substrate 10, the light blocking layer 13 being disposed on the at least one PN junction 11 (or the first PN junction 110 or the second PN junction 111) Directly below, in other words, the at least one PN junction 11 (or the first PN junction 110 or the second PN junction 111) is directly above the light blocking layer 13.
  • This arrangement prevents the light emitted from the backlight from being incident on the PN junction 11, and generates a light leakage current at the P terminal and the N terminal of the PN junction 11.
  • the array substrate 1 includes an effective display area and a frame area surrounding the effective display area. Generally, the static electricity is generated in the frame area. Therefore, in the embodiment, the PN junction 11 and the voltage compensation module 12 are disposed. In the border area.
  • a thin film transistor is further disposed in each pixel unit on the array substrate 1, and the PN junction 11 is prepared in a process of preparing the thin film transistor; such setting may not increase the process flow for preparing the array substrate 1, thereby not increasing the array. Production time and production cost of the substrate 1.
  • the array substrate 1 provided by the embodiment of the present invention uses the PN junction 11 as a switching device connected between the data line DATA and the voltage compensation module 12, and the thin film transistor structure connected to the gate and the drain in the prior art.
  • the leakage current between the P terminal and the N terminal of the PN junction 11 is smaller, so that the power consumption of the array substrate 1 provided by the present embodiment is smaller.
  • the embodiment of the present invention further provides a method for preparing an array substrate, which is used for preparing the array substrate provided by the above embodiment of the present invention, and the method for preparing the array substrate includes:
  • Preparing at least one PN junction connected to the data line and the voltage compensation module on the substrate A step of.
  • the step of preparing the PN junction may include:
  • P-type high concentration doping and N-type high concentration doping are respectively performed on both ends of the polysilicon or single crystal silicon layer. Specifically, a region between the both ends of the polysilicon or single crystal silicon layer may be subjected to P-type low concentration doping.
  • the method for fabricating the array substrate further includes the step of preparing a thin film transistor on the substrate; the PN junction is prepared in a process of preparing the thin film transistor; thus, the preparation process of the array substrate is not increased. Therefore, the production cost and production time of the array substrate are not increased.
  • the method for preparing the array substrate further includes the step of preparing a light blocking layer on the substrate before preparing the PN junction; and setting the PN junction directly above the light blocking layer, such setting may be The light from the backlight is prevented from being incident on the PN junction, and a photo-generated leakage current is generated at the P terminal and the N terminal of the PN junction.
  • the method for preparing an array substrate provided by the embodiment of the present invention prepares a PN junction connected to a data line and a voltage compensation module as a switching device on a substrate, and the PN junction serves as a switching device to make a leakage current smaller, thereby enabling the array substrate provided by the present invention.
  • the array substrate prepared by the preparation method has lower power consumption.
  • the present invention further provides a display panel.
  • the display panel includes an array substrate and a counter substrate.
  • the array substrate adopts the array substrate provided by the above embodiment of the present invention.
  • the display panel provided by the embodiment adopts the array substrate provided by the above embodiment of the present invention, and can reduce power consumption.
  • the present invention further provides a display device.
  • the display device includes a display panel, and the display panel adopts the display panel provided by the above embodiment of the present invention.
  • the display device provided by the embodiment adopts the display panel provided by the above embodiment of the present invention, and can reduce power consumption.

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Abstract

一种阵列基板及其制备方法、显示面板及显示装置，所述阵列基板（1）包括基底（10），以及设置在基底上的数据线、开关器件和电压补偿模块（12），所述开关器件连接在所述数据线与电压补偿模块（12）之间，用以在所述数据线上的电压低于预设低电压或高于预设高电压时，将所述数据线与电压补偿模块（12）导通。所述阵列基板（1）采用PN结作为数据线与电压补偿模块（12）之间的开关器件，由于PN结的P端和N端之间的漏电流较小，从而可以降低阵列基板的功耗。

Description

一种阵列基板及其制备方法、显示面板及显示装置
相关申请的交叉引用
本申请要求在2015年1月4日向中国国家知识产权局提交的申请号为201510002273.4的优先权，并在此全部引用。
技术领域
本发明涉及液晶显示技术领域，具体地，涉及一种阵列基板及其制备方法、显示面板及显示装置。
背景技术
在薄膜晶体管液晶显示器(TFT LCD)中，低温多晶硅(LTPS)技术具有分辨率高、反应速度快、亮度高和开口率高等优点；基于以上优点，LTPS技术成为TFT LCD的发展方向之一。LTPS技术较为复杂，使得采用LTPS技术的TFT LCD的产品良率较低。特别地，在采用LTPS技术的TFT LCD的生产和使用过程中，更容易产生静电，因此，为了提高抗静电释放(Electro-Static Discharge，以下简称为ESD)能力，采用LTPS技术的TFT LCD中一般设置ESD回路，以避免TFT LCD因ESD而损坏。
图1为现有采用LTPS技术的TFT LCD中的ESD回路的示意图。如图1所示，所述ESD回路包括第一、第二晶体管，第一晶体管的栅极G、漏极D与数据线DATA连接，源极S与阵列基板上的高电压端VDD连接，所述高电压端VDD上的电压为TFT LCD的显示面板正常工作的最高正电压VGH；第二晶体管的源极S与数据线DATA连接，栅极G、漏极D与低电压端VSS连接，所述低电压端VSS上的电压为TFT LCD的显示面板正常工作的最低负电压VGL。图2为图1所示TFT LCD的结构图。如图2所示，第一、第二晶体管的源极S、漏极D通过设置在阵列基板上的多晶硅连接，且该多晶硅的与源极S、漏极D连接的一端均进行N型高浓度掺杂，且该两端之间进行P型低浓度掺杂。
在上述TFT LCD中，由于第一晶体管的栅极G、漏极D相连和第二晶体管的栅极G、漏极D相连，其二者等效为单向导通的二极管。在产生静电从而使数据线DATA上的电压高于VGH时，第一晶体管开启，使数据线DATA与高电压端VDD连接，从而使数据线DATA上的电压不高于VGH；在产生静电从而使数据线DATA上的电压低于VGL时，第二晶体管开启，使数据线DATA与低电压端VSS连接，从而使数据线DATA上的电压不低于VGL。在数据线DATA上的电压处在VGH和VGL之间时，第一、第二晶体管关闭，从而使高电压端VDD、低电压端VSS不会影响数据线DATA上的电压。
在上述TFT LCD中，将栅极G与漏极D连接的第一晶体管、第二晶体管等效单向导通的二极管，连接在数据线DATA与高电压端VDD、低电压端VSS之间，可以不增加阵列基板的制备工艺(第一晶体管、第二晶体管与每个像素单元内的薄膜晶体管同时制备)。但由于在多晶硅的两端均进行N型高浓度掺杂，会使第一、第二晶体管的源极S、漏极D之间具有较大的漏电流，这样会导致TFT LCD工作时的功耗较高。
发明内容
本发明旨在至少解决现有技术中存在的上述技术问题之一，提出了一种阵列基板及其制备方法、显示面板及显示装置。本发明的所述阵列基板、显示面板及显示装置具有较低的功耗。
为实现本发明的目的而提供一种阵列基板，所述阵列基板包括基底，以及设置在基底上的数据线、开关器件和电压补偿模块，所述开关器件连接在所述数据线与电压补偿模块之间，用以在所述数据线上的电压低于预设低电压或高于预设高电压时，将所述数据线与电压补偿模块导通；所述开关器件由至少一个PN结构成。
其中，所述电压补偿模块包括高电压端和低电压端，所述高电压端的电压为所述预设高电压，所述低电压端的电压为所述预设低电压。
其中，所述开关器件包括第一PN结和第二PN结，所述第一PN结的P端与数据线连接，N端与高电压端连接；所述第二PN结的P端与低电压端连接，N端与数据线连接。当数据线上的电压高于预设高电压时，第一PN结将数据线与高电压端导通；当数据线上的电压低于预设低电压时，第二PN结将数据线与低电压端导通。
其中，所述电压补偿模块包括高电压端，所述高电压端的电压为所述预设高电压；所述开关器件由一个PN结构成，所述PN结的P端与数据线连接，N端与高电压端连接。当数据线上的电压高于预设高电压时，所述PN结将数据线与高电压端导通。
其中，所述电压补偿模块包括低电压端，所述低电压端的电压为所述预设低电压；所述开关器件由一个PN结构成，所述PN结的P端与低电压端连接，N端与数据线连接。当数据线上的电压低于预设低电压时，所述PN结将数据线与低电压端导通。
其中，所述PN结的P端和N端通过在多晶硅或单晶硅的两端分别进行P型高浓度掺杂和N型高浓度掺杂制备。
其中，所述PN结的P端和N端之间具有间隔，所述间隔区域进行P型低浓度掺杂。
其中，所述阵列基板还包括制备在基底上的光阻挡层，所述光阻挡层设置在所述PN结的正下方。
其中，所述阵列基板包括有效显示区和环绕所述有效显示区的边框区，所述PN结和电压补偿模块设置在所述边框区。
其中，所述阵列基板上的每个像素单元内还设置有薄膜晶体管，所述PN结在制备所述薄膜晶体管的过程中形成。
作为另一个技术方案，本发明还提供一种阵列基板的制备方法，用于制备本发明提供的上述阵列基板，所述阵列基板的制备方法包括：
在基底上制备数据线的步骤；
在基底上制备与数据线和电压补偿模块连接的至少一个PN结的步骤。
其中，制备所述PN结的步骤包括：
在基底上制备多晶硅或单晶硅层；
在多晶硅或单晶硅层的两端分别进行P型高浓度掺杂和N型高浓度掺杂。
其中，所述阵列基板的制备方法还包括在基底上制备薄膜晶体管的步骤；
所述PN结在制备所述薄膜晶体管的工艺过程中制备。
其中，还包括在制备所述PN结之前，在基底上制备光阻挡层的步骤。
其中，所述PN结设置在光阻挡层的正上方。
作为另一个技术方案，本发明还提供一种显示面板，包括阵列基板和对盒基板，所述阵列基板采用本发明提供的上述阵列基板。
作为另一个技术方案，本发明还提供一种显示装置，包括显示面板，所述显示面板采用本发明提供的上述显示面板。
本发明具有以下有益效果：
本发明提供的阵列基板，其采用PN结作为连接在数据线与电压补偿模块之间的开关器件，与现有技术中栅极与漏极连接的薄膜晶体管结构相比，PN结的P端和N端之间的漏电流更小，从而使本发明提供的阵列基板的功耗更小。
本发明提供的阵列基板的制备方法，其在基底上制备与数据线和电压补偿模块连接的PN结作为开关器件，使开关器件中的漏电流更小，从而使本发明提供的阵列基板的制备方法所制备出的阵列基板的功耗更小。
本发明提供的显示面板，其采用本发明上述提供的上述阵列基板，可以降低功耗。
本发明提供的显示装置，其采用本发明提供的上述显示面板，可以降低功耗。
附图说明
附图是用来提供对本发明的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本发明，但并不构成对本 发明的限制。在附图中：
图1为现有采用LTPS技术的TFT LCD中的ESD回路的示意图；
图2为图1所示TFT LCD的结构图；
图3为本发明提供的阵列基板的实施方式的结构示意图；
图4为图3所示阵列基板的ESD回路的电路图；
图5为图4所示ESD回路的第一种替代方式的电路图；
图6为图4所示ESD回路的第二种替代方式的电路图。
其中，附图标记：
1：阵列基板；10：基底；11：PN结；12：电压补偿模块；110：第一PN结；111：第二PN结；13：光阻挡层。
具体实施方式
以下结合附图对本发明的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本发明，并不用于限制本发明。
请参看图3和图4，图3为本发明实施方式提供的阵列基板的结构示意图，图4为图3所示阵列基板的ESD回路的电路图。在本实施方式中，阵列基板1包括基底10，以及设置在基底10上的数据线DATA、开关器件和电压补偿模块12，所述开关器件连接在数据线DATA与电压补偿模块12之间，用以在数据线DATA上的电压低于预设低电压或高于预设高电压时将数据线DATA与电压补偿模块12导通；所述开关器件由至少一个PN结11构成。具体地，所述预设高电压可以为阵列基板1最高工作正电压VGH，即阵列基板1正常工作所允许的最高正电压，所述预设低电压可以为阵列基板1最低工作负电压VGL，即阵列基板1正常工作所允许的最低负电压；当然，所述预设高电压也可以设置为一个小于最高工作正电压VGH的电压值，所述预设低电压也可以设置为一个大于最低工作负电压VGL的电压值。
在本实施方式中，当阵列基板1上产生静电，从而导致数据线DATA上的电压高于预设高电压或低于预设低电压时，电压补偿模块 12通过导通的PN结与数据线DATA电连接，可以使数据线DATA上的电压不高于预设高电压或不低于预设低电压，或者使数据线DATA上的电压既不高于预设高电压，也不低于预设低电压，从而使数据线DATA上的电压处在或尽可能处在正常的工作范围之内，避免由于静电释放导致阵列基板1及应用所述阵列基板1的显示面板和显示装置损坏。同时，与现有技术中的两个N型高浓度掺杂的端部相比，PN结的P端和N端之间的漏电流更小，这样可以使阵列基板1，以及采用阵列基板1的显示面板和显示装置的功耗较低。
具体地，如图3和图4所示，所述电压补偿模块12包括高电压端VDD和低电压端VSS，所述高电压端VDD上的电压等于所述预设高电压，所述低电压端VSS上的电压等于所述预设低电压。所述至少一个PN结11包括第一PN结110和第二PN结111，所述第一PN结110的P端与数据线DATA连接，N端与高电压端VDD连接，从而使数据线DATA上的电压高于预设高电压时，第一PN结110可以导通，将数据线DATA与高电压端VDD电连接；所述第二PN结111的P端与低电压端VSS连接，N端与数据线DATA连接，从而使数据线DATA上的电压低于预设低电压时，第二PN结111可以导通，将数据线DATA与低电压端VSS电连接。
作为一种替代实施例，如图5所示，所述电压补偿模块12可以至少包括高电压端VDD(可以包括低电压端VSS，也可以不包括低电压端VSS)；与上述实施例相同，高电压端VDD的电压同样为所述预设高电压；在此情况下，所述开关器件由一个PN结11构成，所述PN结11的P端与数据线DATA连接，N端与高电压端VDD连接。在本实施例中，当数据线DATA上的电压高于预设高电压时，PN结11可以导通，将数据线DATA与高电压端VDD电连接。
作为另一种替代实施例，如图6所示，所述电压补偿模块12可以至少包括低电压端VSS(可以包括高电压端VDD，也可以不包括高电压端VDD)；与上述实施例相同，低电压端VSS的电压同样为所述预设低电压；在此情况下，所述开关器件由一个PN结11构成，所述PN结11的P端与低电压端VSS连接，N端与数据线DATA连 接。在本实施例中，当数据线DATA上的电压低于预设低电压时，PN结11可以导通，将数据线DATA与低电压端VSS电连接。
具体地，所述PN结11的P端(图3中的P+区域)和N端(图3中的N+区域)通过在多晶硅或单晶硅的两端分别进行P型高浓度掺杂和N型高浓度掺杂制备。进一步地，所述PN结11的P端和N端之间具有间隔(图3中的P－区域)，所述间隔区域进行P型低浓度掺杂。
优选地，所述阵列基板1还包括制备在基底10上的光阻挡层13，所述光阻挡层13设置在所述至少一个PN结11(或第一PN结110或第二PN结111)的正下方，换言之，所述至少一个PN结11(或第一PN结110或第二PN结111)在所述光阻挡层13的正上方。这样设置可以避免背光源发出的光线照射至PN结11上，在PN结11的P端和N端产生光生漏电流。
阵列基板1包括有效显示区和环绕所述有效显示区的边框区，一般地，所述静电产生在所述边框区，因此，在本实施方式中，所述PN结11和电压补偿模块12设置在所述边框区。
阵列基板1上的每个像素单元内还设置有薄膜晶体管，所述PN结11在制备所述薄膜晶体管的工艺过程中制备；这样设置可以不增加制备阵列基板1的工艺流程，从而不增加阵列基板1的生产时间和生产成本。
综上所述，本发明实施方式提供的阵列基板1采用PN结11作为连接在数据线DATA与电压补偿模块12之间的开关器件，与现有技术中栅极与漏极连接的薄膜晶体管结构相比，PN结11的P端和N端之间的漏电流更小，从而使本实施方式提供的阵列基板1的功耗更小。
作为另一个技术方案，本发明实施方式还提供一种阵列基板的制备方法，用于制备本发明上述实施方式所提供的阵列基板，所述阵列基板的制备方法包括：
在基底上制备数据线的步骤；
在基底上制备与数据线和电压补偿模块连接的至少一个PN结 的步骤。
制备所述PN结的步骤可以包括：
在基底上制备多晶硅或单晶硅层；
在多晶硅或单晶硅层的两端分别进行P型高浓度掺杂和N型高浓度掺杂。具体地，所述多晶硅或单晶硅层的两端之间的区域可以进行P型低浓度掺杂。
在本实施方式中，所述阵列基板的制备方法还包括在基底上制备薄膜晶体管的步骤；所述PN结在制备所述薄膜晶体管的工艺过程中制备；这样可以不增加阵列基板的制备工艺，从而不会增加阵列基板的生产成本和生产时间。
优选地，所述阵列基板的制备方法还包括在制备所述PN结之前，在基底上制备光阻挡层的步骤；将所述PN结设置在所述光阻挡层的正上方，这样的设置可以避免背光源发出的光线照射至PN结上，在PN结的P端和N端产生光生漏电流。
本发明实施方式提供的阵列基板的制备方法在基底上制备与数据线和电压补偿模块连接的PN结作为开关器件，PN结作为开关器件使得漏电流更小，从而使本发明提供的阵列基板的制备方法所制备出的阵列基板的功耗更小。
作为另一个技术方案，本发明还提供了一种显示面板，在本实施方式中，显示面板包括阵列基板和对盒基板，所述阵列基板采用本发明上述实施方式提供的阵列基板。
本实施方式提供的显示面板采用本发明上述实施方式提供的阵列基板，可以降低功耗。
作为另一个技术方案，本发明还提供了一种显示装置，在本实施方式中，显示装置包括显示面板，且所述显示面板采用本发明上述实施方式提供的显示面板。
本实施方式提供的显示装置，其采用本发明上述实施方式提供的显示面板，可以降低功耗。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的 普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (17)

  1. 一种阵列基板，包括基底，以及设置在基底上的数据线、开关器件和电压补偿模块，所述开关器件连接在所述数据线与电压补偿模块之间，用以在所述数据线上的电压低于预设低电压或高于预设高电压时，将所述数据线与电压补偿模块导通；其中，所述开关器件由至少一个PN结构成。
  2. 根据权利要求1所述的阵列基板，其中，所述电压补偿模块包括高电压端和低电压端，所述高电压端的电压为所述预设高电压，所述低电压端的电压为所述预设低电压。
  3. 根据权利要求2所述的阵列基板，其中，所述开关器件包括第一PN结和第二PN结，所述第一PN结的P端与数据线连接，N端与高电压端连接；所述第二PN结的P端与低电压端连接，N端与数据线连接。
  4. 根据权利要求1所述的阵列基板，其中，所述电压补偿模块包括高电压端，所述高电压端的电压为所述预设高电压；
    所述开关器件由一个PN结构成，该PN结的P端与数据线连接，N端与高电压端连接。
  5. 根据权利要求1所述的阵列基板，其中，所述电压补偿模块包括低电压端，所述低电压端的电压为所述预设低电压；
    所述开关器件由一个PN结构成，该PN结的P端与低电压端连接，N端与数据线连接。
  6. 根据权利要求1～5任意一项所述的阵列基板，其中，所述PN 结的P端和N端通过在多晶硅或单晶硅的两端分别进行P型高浓度掺杂和N型高浓度掺杂制备。
  7. 根据权利要求6所述的阵列基板，其中，所述PN结的P端和N端之间具有间隔，所述间隔区域进行P型低浓度掺杂。
  8. 根据权利要求1至5任意一项所述的阵列基板，其中，所述阵列基板还包括制备在基底上的光阻挡层，所述光阻挡层设置在所述PN结的正下方。
  9. 根据权利要求1至5任意一项所述的阵列基板，其中，所述阵列基板包括有效显示区和环绕所述有效显示区的边框区，所述PN结和电压补偿模块设置在所述边框区。
  10. 根据权利要求1至5任意一项所述的阵列基板，其中，所述阵列基板上的每个像素单元内还设置有薄膜晶体管，所述PN结在制备所述薄膜晶体管的过程中形成。
  11. 一种权利要求1的阵列基板的制备方法，包括：
    在基底上制备数据线的步骤；
    在基底上制备与数据线和电压补偿模块连接的至少一个PN结的步骤。
  12. 根据权利要求11所述的阵列基板的制备方法，其中，制备所述PN结的步骤包括：
    在基底上制备多晶硅或单晶硅层；
    在多晶硅或单晶硅层的两端分别进行P型高浓度掺杂和N型高浓度掺杂。
  13. 根据权利要求11所述的阵列基板的制备方法，还包括在基底上制备薄膜晶体管的步骤；
    所述PN结在制备所述薄膜晶体管的工艺过程中制备。
  14. 根据权利要求11所述的阵列基板的制备方法，还包括在制备所述PN结之前，在基底上制备光阻挡层的步骤。
  15. 根据权利要求14所述的阵列基板的制备方法，其中，所述PN结设置在光阻挡层的正上方。
  16. 一种显示面板，包括阵列基板和对盒基板，其中，所述阵列基板采用权利要求1至10任意一项所述的阵列基板。
  17. 一种显示装置，包括显示面板，其中，所述显示面板采用权利要求16所述的显示面板。
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