WO2016107069A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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Publication number
WO2016107069A1
WO2016107069A1 PCT/CN2015/080550 CN2015080550W WO2016107069A1 WO 2016107069 A1 WO2016107069 A1 WO 2016107069A1 CN 2015080550 W CN2015080550 W CN 2015080550W WO 2016107069 A1 WO2016107069 A1 WO 2016107069A1
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Prior art keywords
driving
sub
gate
array substrate
module
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PCT/CN2015/080550
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English (en)
French (fr)
Inventor
永山和由
宋松
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京东方科技集团股份有限公司
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Priority to US14/891,536 priority Critical patent/US10262602B2/en
Publication of WO2016107069A1 publication Critical patent/WO2016107069A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • Embodiments of the present invention relate to an array substrate and a display device.
  • a Thin Film Transistor-Liquid Crystal Display includes a matrix of pixels defined by intersections of gate lines and data lines in both horizontal and vertical directions. For example, when the TFT-LCD performs display, a gate wave driving circuit on the gate line sequentially inputs a square wave of a certain width from the top to the bottom to gate, and then passes the source on the data line. The source driver circuit sequentially outputs the signals required for each row of pixels from top to bottom. When the resolution is high, the output of the gate drive circuit and the source drive circuit of the display is more, and the length of the drive circuit is also increased, which is not conducive to the bonding process of the module drive circuit.
  • the design of the display of the GOA Gate Driver on Array
  • the TFT Thin Film Transistor
  • Embodiments of the present invention provide an array substrate and a display device, which can solve the problem that the design of the narrow border of the display panel is disadvantageous due to the large size of the driving TFT in the GOA circuit.
  • An aspect of an embodiment of the present invention provides an array substrate including a gate driving circuit, the gate driving circuit including at least two stages of shift register units, and each stage of the shift register unit and a row of gate lines Connecting, the shift register unit includes a driving module and a logic module; the driving module includes a portion located in a display area of the array substrate; each of the driving modules respectively connecting the logic module, the gate line, and a a driving signal input end, and transmitting a signal input to the first driving signal input terminal to the gate line under the control of the logic module output signal.
  • a display device including the array as described above is provided Substrate.
  • 1a is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 1b is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a shift register unit according to an embodiment of the present invention.
  • 3a is a schematic structural diagram of another shift register unit according to an embodiment of the present invention.
  • 3b is a schematic diagram of a connection structure of various components in a shift register unit according to an embodiment of the present invention.
  • 4a is a schematic structural diagram of still another shift register unit according to an embodiment of the present invention.
  • 4b is a comparison diagram of size design of a driving transistor in a shift register unit according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a driving transistor in a shift register unit according to an embodiment of the present invention.
  • 6a is a distribution diagram of a driving transistor in another shift register unit according to an embodiment of the present invention.
  • FIG. 6b is a schematic diagram of a driving transistor in another shift register unit according to an embodiment of the present invention.
  • FIG. 6c is a structural diagram of connection of each driving transistor in a shift register unit according to an embodiment of the present invention.
  • the GOA circuit includes a plurality of TFTs, and some TFTs control the on and off of some lines in the GOA circuit by turning on and off two states, thereby realizing the logic output of the signal, so the above
  • the TFT is referred to as a logic TFT; and some TFTs are capable of inputting a scan signal to the gate line in an on state, so that the scan signal can turn on the pixel unit in the display region through the gate line, and thus the TFT is referred to as a driving TFT. Since the scanning signals of the input gate lines can control the opening and closing of a plurality of pixel units located in the same row, the load of the gate lines is large. As a result, it is necessary to increase the size of the driving TFT.
  • the size of the above driving TFT is generally much larger than the size of the logic TFT.
  • the GOA circuit is disposed on the non-display area of the array substrate, the non-display area corresponds to the frame position of the display panel. Therefore, when the size of the above driving TFT is large, a large amount of layout space is occupied, which is disadvantageous for the design trend of the narrow border of the display panel.
  • An embodiment of the present invention provides an array substrate 01, as shown in FIG. 1a, which may include a gate driving circuit 10.
  • the gate driving circuit 10, as shown in FIG. 1b may include at least two stages of shift register units (SR1, SR2, ..., SRn), each stage shift register unit (for example, SRn) and a row of gate lines (eg, Gaten) connection.
  • Each of the shift register units (eg, SRn) may include a drive module (eg, Dn) and a logic module (eg, Ln). Where n ⁇ 2 and is an integer.
  • the drive modules (D1, D2 . . . Dn) include portions of the display area 100 of the array substrate 01.
  • the logic modules (L1, L2, . . . Ln) may be located in the non-display area 101 of the array substrate 01.
  • the logic module may also be located within the display area 100 of the array substrate 01.
  • Each driving module (for example, D1) is respectively connected to a logic module (for example, L1), a gate line (for example, Gate1), and a first driving signal input terminal CLK; and under the control of a logic module (for example, L1) output signal, the first driving signal is The signal input to the input CLK is transmitted to the gate line (for example, Gate1).
  • the logic modules (L1, L2, . . . Ln) in the embodiment of the present invention may include a plurality of thin film transistors (not shown in the drawing, hereinafter referred to as logic TFTs) for implementing logic operations. Part of the circuit can be turned on and off by the above logic TFT, so that the output of the control signal can be logically operated to realize the shift output. Since the load at the output of the logic TFT is small, the size of the logic TFT is small, and may generally be 10 ⁇ m. Therefore, even if a logic module (L1, L2, ... Ln) composed of a plurality of logic TFTs is provided in the non-display area 101, it does not occupy too much wiring space.
  • logic TFTs thin film transistors
  • a plurality of horizontally intersecting gate lines (Gate1, Gate2...Gaten) in the display area 100 intersect with the data lines (Data1, Data2...Datan) to define a plurality of pixel units 102 arranged in a matrix form.
  • the driving module (D1, D2 . . . Dn) may include a portion disposed in at least one of the pixel units 102.
  • the driving module may be disposed in the pixel unit 102.
  • the specific positions of the driving modules (D1, D2, . . . Dn) in the display area 100 are not limited in the embodiment of the present invention.
  • driving modules of different rows may be disposed in the first column of pixel units 102.
  • the drive modules of different rows are located in pixel units 102 of different columns.
  • the first signal input terminal Input of each of the shift register units of each stage is adjacent to the previous one.
  • the signal output terminal Output of the shift register unit is connected.
  • the first signal input terminal Input of the first stage shift register unit SR1 receives the start signal STV or the input reset signal RST.
  • the second signal input terminal Reset of each of the shift register units of each stage is connected to the signal output terminal Output of the adjacent stage shift register unit.
  • the second signal input Reset of the last stage shift register unit SRn may input the reset signal RST or the reception start signal SVT.
  • the number of shift register units is equal to the number of gate lines Gate of the display area. That is, the signal output terminal of the current stage of each stage of the shift register unit and the row of gates of the display area are gated. Connected to shift the input scan signal through a multi-stage shift register to achieve progressive scan of each row of gate lines.
  • the last stage shift When the second signal input terminal Reset of the register unit SRn inputs the reset signal RST, the signal output terminal Output of each stage shift register (SR1, SR2, ... SRn) sequentially outputs the scan signal in the forward direction (from top to bottom). To the corresponding gate line (Gate1, Gate2...Gaten).
  • the first stage shift register unit When the second signal input terminal Reset of the last stage shift register unit SRn of the shift register units (SR1, SR2 ... SRn) of the gate drive circuit receives the start signal STV, the first stage shift register unit When the first signal input terminal Input of SR1 inputs the reset signal RST, the signal output terminals of the respective stages of the stages sequentially output the scan signals to the corresponding gate lines in reverse (from bottom to top) (Gaten, Gaten-1) ...Gate1).
  • Embodiments of the present invention provide an array substrate including a gate driving circuit.
  • the gate driving circuit includes at least two stages of shift register units, and each stage shift register unit is connected to a row of gate lines.
  • the scan signal can be input to the gate line in order to realize the progressive scan of the gate line.
  • the shift register unit includes a drive module for inputting a scan signal to the gate line and a logic module for performing a shift function by a logic output.
  • the driving module is located in a display area of the array substrate; the logic module is located in a non-display area of the array substrate.
  • the driving module is respectively connected to the logic module, the gate line and the first driving signal input end; under the control of the logic module output signal, the signal input by the first driving signal input end is transmitted to the gate line. Due to the large load of the gate lines, the drive module is relatively large in size relative to the logic module. Therefore, when the driving module with a larger size is disposed in the display area, the wiring space of the non-display area can be greatly reduced, thereby realizing the design of the narrow bezel.
  • the driving module (for example, D1) may include a first driving transistor T1 and a capacitor C.
  • the first driving transistor T1 has a gate connected to the first control signal output signal Signal_A of the logic module (for example, L1), a first electrode connected to the first driving signal input terminal CLK, and a second electrode connected to the gate line (for example, Gate1).
  • One end of the capacitor C is connected to the gate of the first driving transistor T1, and the other end is connected to the second pole of the first driving transistor T1.
  • the logic module L1 turns on the first driving transistor T1 from the control signal outputted by the first control signal output signal Signal_A
  • the signal input by the first driving signal input terminal CLK can be output as a scan signal to the shift register.
  • the gate line Gate1 corresponding to the cell SR1 is opened such that the gate line Gate1 will be connected to a row of pixel cells 102 connected thereto; when the data line (Data1, Data2...Datan) inputs a data signal, a row of pixel cells 102 connected to the gate line Gate1
  • the screen display is possible.
  • the first driving transistor T1 is used to input a scanning signal to the gate lines (Gate1, Gate2...Gaten), and the size of the first driving transistor T1 is larger because the load of the gate lines (Gate1, Gate2...Gaten) is larger.
  • the driving module (for example, D1) may further include: a second driving transistor T2.
  • the gate of the second driving transistor T2 is connected to the second control signal output signal Signal_B of the logic module (for example, L1), the first electrode is connected to the gate line (for example, Gate1), and the second electrode is connected to the second driving signal input terminal VSS. .
  • the second drive signal input terminal VSS is input with a low level, or grounding is taken as an example.
  • FIG. 3b shows a wiring connection diagram of the first driving transistor T1 and the second driving transistor T2.
  • the second pole of the first driving transistor T1 is connected to the gate line Gate through the via 31.
  • Second drive crystal The second pole of the tube T2 is connected to the second drive signal input terminal VSS through the via 31.
  • the material of the semiconductor active layer 30 constituting the first driving transistor T1 and the second driving transistor T2 may be an oxide semiconductor active layer, such as indium tin oxide or indium zinc oxide; or may be composed of low temperature polysilicon; or Made of amorphous silicon. The embodiment of the invention does not limit this.
  • the connection line of the input terminal CLK can be formed by a data metal layer for preparing the data line.
  • the connection line of the first control signal output signal Signal_A, the connection line of the second control signal output terminal Signal_B, and the connection line of the second drive signal input terminal VSS may be formed by a gate metal layer of the gate line Gate.
  • the above shift register unit (for example, SR1) can not only turn on the first driving transistor T1 through a control signal output from the first control signal output terminal Signal_A through the logic module (for example, L1) in the output stage,
  • the signal input from the first driving signal input terminal CLK may be output as a scan signal to the gate line Gate1 corresponding to the shift register unit SR1, and in the non-output stage, may also be output from the second control signal through the logic module L1.
  • the control signal outputted by the signal_B turns on the second driving transistor T2, and outputs the signal input from the second driving signal input terminal VSS to the corresponding gate line Gate1 of the shift register unit SR1, because the second driving signal input terminal VSS input is low.
  • the level therefore, in the non-output phase of the shift register unit SR1, the gate line Gate1 corresponding thereto does not output a scan signal.
  • the gate line Gate1 signal can be pulled high by the first driving transistor T1 at the output stage of the shift register unit SR1,
  • the gate line Gate1 performs scanning; in the non-output stage, the gate line Gate1 signal is pulled low through the second driving transistor T2, thereby preventing the shift register unit from erroneously outputting the scan signal in the non-output stage, ensuring that the gate driving circuit has a high Stability and reliability.
  • the second driving transistor T2 is used to input a low level to the gate lines (Gate1, Gate2...Gaten).
  • the size of the second driving transistor T2 is small with respect to the first driving transistor T1, and is generally about 100 ⁇ m. However, it is still larger than the general logic TFT (size is 10 ⁇ m) for implementing logic operations. Therefore, by disposing the first driving transistor T1 and the second driving transistor T2 having the above-described large size in the display region 100, the wiring space of the non-display region 101 can be reduced, thereby facilitating the design of the narrow bezel of the display panel.
  • the driving module (for example, D1) may include at least two driving sub-modules 200, and the driving sub-module 200 may include a first driving sub-transistor T1s and a sub-capacitor Cs.
  • the first sub-driving transistor T1s has a gate connected to a first control signal output signal Signal_A of the logic module (for example, L1), a first electrode is connected to the first driving signal input terminal CLK, and a second electrode is connected to the gate line (for example, Gate1). .
  • the sub-capacitor Cs has one end connected to the gate of the first sub-driving transistor T1s and the other end connected to the second pole of the first sub-driving transistor T1s.
  • the signal input by the first drive signal input terminal CLK can be output as a scan signal to
  • the shift register unit SR1 corresponds to the gate line Gate1 such that the gate line Gate1 will open a row of pixel cells 102 connected thereto; when the data line (Data1, Data2...Datan) inputs a data signal, a row connected to the gate line Gate1
  • the pixel unit 102 can perform screen display.
  • the plurality of first sub-driving transistors T1s are used to input scan signals to the gate lines (Gate1, Gate2...Gaten).
  • the sum of the sizes of the plurality of first sub-driving transistors T1s may be equal to the size of one first driving transistor T1, that is, the plurality of first sub-driving transistors T1s may be a first driving transistor T1 in parallel.
  • the size of the first driving transistor T1 is 1000 ⁇ m.
  • the driving module for example, D1 may include at least ten driving sub-modules 200
  • the size of the first sub-driving transistor T1s in each driving sub-module 200 may be 100 ⁇ m.
  • the sub-capacitor Cs is arranged in the same manner as described above.
  • the shift register unit SR1 for driving the first row gate line Gate1 includes a logic module L1 located in a non-display area and a first driving transistor T1 located in the first pixel unit 102.
  • the size of the first driving transistor T1 is represented by a circle. It can be seen that since the size of the first driving transistor T1 is large, it occupies most of the area of the pixel unit 102, and thus the aperture ratio of the pixel unit 102 provided with the first driving transistor T1 is low.
  • the shift register unit SR2 for driving the second row gate line Gate2 includes a logic module L2 located in the non-display area and a plurality of first sub-drive transistors T1s located in the different pixel units 102, respectively.
  • the first sub-driving transistor T1s is represented by a circle, and the sum of the sizes of the plurality of first sub-driving transistors T1s is equal to the size of the first driving transistor T1.
  • First sub-drive crystal The size of the body tube T1s is small relative to the size of the first driving transistor T1. Therefore, the area of the first sub-driving transistor T1s occupying the pixel unit 102 is also small, and thus the aperture ratio of the pixel unit 102 connected to the second row gate line Gate2 is large.
  • the driving submodule 200 may further include: a second sub driving transistor T2s.
  • the second sub-driving transistor T2s has a gate connected to a second control signal output signal Signal_B of the logic module (for example, L1), a first pole connecting gate line (for example, Gate1), and a second pole and a second driving signal input.
  • the terminal VSS is connected.
  • the shift register unit (for example, SR1) can not only turn on the plurality of first sub-drive transistors T1s through the control signal output from the first control signal output signal Signal_A through the logic module L1 in the output stage, A signal input from the drive signal input terminal CLK can be output as a scan signal to the gate line Gate1 corresponding to the shift register unit SR1.
  • the plurality of second sub-drive transistors T2s can be turned on by the logic module L1 from the control signal outputted by the second control signal output terminal Signal_B, and the signal input from the second drive signal input terminal VSS is output to the shift.
  • the gate line Gate1 corresponding to the bit register unit SR1 since the second driving signal input terminal VSS inputs a low level, the gate line Gate1 corresponding thereto does not output a scan signal in the non-output stage of the shift register unit SR1.
  • a plurality of first sub-drivings can be performed in the output stage of the shift register unit SR1.
  • the transistor T1s pulls the gate line Gate1 signal high to scan the gate line Gate1; in the non-output stage, the gate line Gate1 signal is pulled low through the plurality of second sub-drive transistors T2s, thereby preventing the shift register unit from being output.
  • the phase error output scan signal ensures high stability and reliability of the gate drive circuit.
  • the plurality of second sub-driving transistors T2s are used to input a low level to the gate lines (Gate1, Gate2...Gaten).
  • the sum of the sizes of the plurality of second sub-driving transistors T2s may be equal to the size of one second driving transistor T2, that is, the plurality of second sub-driving transistors T2s may be a second driving transistor T2 in parallel.
  • the size of the first driving transistor T2 is 100 ⁇ m.
  • the driving module for example, D1 may include at least ten driving sub-modules 200
  • the size of the second sub-driving transistor T2s in each driving sub-module 200 may be 10 ⁇ m.
  • a larger drive module (for example, D1) is disposed in the display area. 100, the wiring space of the non-display area 101 can be reduced.
  • the driving module (for example, D1) includes a plurality of driving sub-modules 200, when each driving sub-module 200 is separately disposed in a different pixel unit 102, a driving module (for example, D1) is disposed relative to When the area of the pixel unit 102 is occupied by one pixel unit 102, the area occupied by the driving sub-module 200 occupies the pixel unit 102 is greatly reduced, so that the influence on the aperture ratio of the display panel can be reduced. Therefore, the above embodiment can not only realize a narrow bezel design, but also ensure that the display panel has a high aperture ratio.
  • one of the driving sub-modules 200 may be disposed in each of the pixel units 102 of the display area 100. In this way, the size of the first driver sub-transistor T1s and the sub-capacitor Cs in the driving sub-module 200 can be further reduced. Thereby the influence on the aperture ratio of the display panel is further reduced.
  • the distribution of the plurality of first driver sub-transistors T1s and the plurality of second driver sub-transistors T2s in the display region will be exemplified below by way of a specific embodiment.
  • each of the driving sub-modules of each stage of the shift register unit includes a first sub-driving transistor T1s and a second sub-driving transistor T2s respectively located in two adjacent pixel units 102 in the same row.
  • FIG. 5 is a simplified schematic diagram, and thus the specific wiring of the above-mentioned driving transistor and logic modules (L1, L2, . . . Ln) is not shown.
  • the first sub-drive transistor T1s and the second sub-drive transistor T2s in each stage of the shift register unit can be disposed in different pixel units 102. Therefore, the above solution can further reduce the occupation of the area of the pixel unit 102 with respect to the scheme of disposing the driving submodule 200 in one pixel unit 102, so that the aperture ratio of the display panel can be improved.
  • the size of the pixel unit 102 is small. Therefore, in order to satisfy the design of the narrow bezel, the first logical sub-module 201 or the second logical sub-module 202 may be disposed at a position close to the edge region 41 on both sides of the display region 100.
  • the logic modules may include a first logic sub-module 201 and a second logic sub-module 202 respectively located on both sides of the display area 100.
  • the first logic sub-module 201 is connected to the gate of the first sub-drive transistor T1s.
  • the second logic sub-module 202 is coupled to the gate of the second sub-drive transistor T2s.
  • the first sub-driving transistor T1s and the second sub-driving transistor T2s are respectively located in the edge regions 41 on both sides of the central region 40 of the display region.
  • the edge region 41 described above includes at least one column of pixel units 102.
  • the number of columns of the central unit 40 pixel unit 102 is larger than the number of columns of the pixel unit of the edge area 41.
  • the first edge region 41 may refer to a plurality of columns of pixel units 102 located at two sides of the display panel near the frame of the display panel, and the central region 40 is the edge region 41 of the display panel except the two sides. Area. Also, the number of columns of the central region 40 pixel unit 102 is much larger than the number of columns of the pixel unit 102 of the edge region 41.
  • FIG. 6a is a simplified schematic diagram, and thus the specific connection structure of the above-described driving transistor and logic modules (L1, L2, . . . Ln) is not shown.
  • the first sub-drive transistor T1s and the second sub-drive transistor T2s are disposed in the near edge region 41. Therefore, for a high PPI display panel having a very small pixel unit 102 size, the drive transistor occupies only a small portion of the effective display area. Therefore, it is possible to reduce the influence on the aperture ratio of the display panel while achieving a narrow bezel design.
  • the first sub-drive transistors T1s of the different shift register units are disposed in the edge region 41 on the left side of the display panel, and the second sub-drive transistors T2s of the shift register unit are both It is disposed in the edge area 41 on the right side of the display panel. Since the size of the first sub-driving transistor T1s is larger than the size of the second sub-driving transistor T2s. As a result, the aperture ratios of the left edge region 41 and the right edge region 41 of the display panel are greatly different, so that the display brightness of the screen is not uniform, which reduces the display effect.
  • each pixel unit 102 of one row corresponds to one first sub-driving transistor T1s, and the other row
  • Each pixel unit 102 corresponds to a second sub-drive transistor T2s.
  • FIG. 6c a specific wiring diagram of a scheme in which the first sub-drive transistor T1s and the second sub-drive transistor T2s in the adjacent shift register unit are cross-arranged is as shown in FIG. 6c. It can be seen that due to The first sub-drive transistor T1s and the second sub-drive transistor T2s in the adjacent shift register unit are cross-arranged. Therefore, the positions of the first logical sub-module 201 and the second logical sub-module 202 of the different rows are also different.
  • the first logical sub-module 201 (L1) is located in the edge region 41 on the left side of FIG. 6c
  • the second logical sub-module 202 (L1') is located on the right side of FIG. 6c.
  • the edge area 41 In the edge area 41.
  • the positions of the first sub-drive transistor T1s and the second sub-drive transistor T2s of the shift register unit SR2 are interchanged, so the second logic sub-module 202 (L2) is located In the edge region 41 on the left side of Fig. 6c
  • the first logical sub-module 201 (L2') is located in the edge region 41 on the right side of Fig. 6c.
  • the drawings of the embodiments of the present invention are described by taking the display area of the array of the driving module as an example, but the embodiment of the present invention is not limited thereto.
  • the first driving transistor in each of the shift register units of each stage may be disposed in the display area, and the second driving transistor may be disposed in the non-display area.
  • Embodiments of the present invention provide a display device including any of the array substrates described above. It has the same structure and advantageous effects as the array substrate provided by the foregoing embodiments. Since the structure and beneficial effects of the array substrate have been described in detail in the foregoing embodiments, they are not described herein again.
  • the display device may specifically include a liquid crystal display device or an OLED display device, etc.
  • the display device may be a liquid crystal panel, a liquid crystal display, a liquid crystal television, an OLED panel, an electronic paper, a digital photo frame, a mobile phone, or a tablet computer. Any product or part that has a display function.
  • the foregoing program may be stored in a computer readable storage medium, and the program is executed when executed.
  • the foregoing steps include the steps of the foregoing method embodiments; and the foregoing storage medium includes: a medium that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.

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Abstract

公开了一种阵列基板及显示装置。该阵列基板（01）包括栅极驱动电路（10），栅极驱动电路（10）包括至少两级移位寄存器单元（SR1-SRn），每一级移位寄存器单元（SR1-SRn）与一行栅线（Gate1-Gaten）相连接。移位寄存器单元（SR1-SRn）包括驱动模块（D1-Dn）以及逻辑模块（L1-Ln）；驱动模块（D1-Dn）位于阵列基板的显示区域（100）的部分。该阵列基板能够解决由于ＧＯＡ电路中驱动ＴＦＴ的尺寸较大，不利于显示面板窄边框的设计趋势的问题

Description

阵列基板及显示装置 技术领域
本发明实施例涉及一种阵列基板及显示装置。
背景技术
薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)包括由水平和垂直两个方向的栅线和数据线交叉定义的像素矩阵。例如，当TFT-LCD进行显示时，通过栅线(Gate Line)上的栅极驱动电路依次从上到下对每一像素行输入一定宽度的方波进行选通，再通过数据线上的源极(Source)驱动电路将每一行像素所需的信号依次从上往下输出。当分辨率较高时，显示器的栅极驱动电路和源极驱动电路的输出均较多，驱动电路的长度也将增大，这将不利于模组驱动电路的绑定(Bonding)工艺。
为了解决上述问题，显示器的制造常采用GOA(Gate Driver on Array，阵列基板行驱动)电路的设计，将TFT(Thin Film Transistor，薄膜场效应晶体管)栅极开关电路集成在显示面板的阵列基板上以形成对显示面板的扫描驱动，从而可以省掉栅极驱动电路的邦定(Bonding)区域以及***布线空间。
发明内容
本发明的实施例提供一种阵列基板及显示装置，能够解决由于GOA电路中驱动TFT的尺寸较大，不利于显示面板窄边框的设计趋势的问题。
本发明实施例的一方面，提供一种阵列基板，其包括栅极驱动电路，所述栅极驱动电路包括至少两级移位寄存器单元，每一级所述移位寄存器单元与一行栅线相连接，所述移位寄存器单元包括驱动模块以及逻辑模块；所述驱动模块包括位于所述阵列基板的显示区域的部分；每个所述驱动模块分别连接所述逻辑模块、所述栅线以及第一驱动信号输入端，并且在所述逻辑模块输出信号的控制下，将所述第一驱动信号输入端输入的信号传输至所述栅线。
本发明实施例的另一方面，提供一种显示装置，其包括如上所述的阵列 基板。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1a为本发明实施例提供的一种阵列基板的结构示意图；
图1b为本发明实施例提供的一种栅极驱动电路的结构示意图；
图2为本发明实施例提供的一种移位寄存器单元的结构示意图；
图3a为本发明实施例提供的另一种移位寄存器单元的结构示意图；
图3b为本发明实施例提供的一种移位寄存器单元中各个部件的连接结构示意图；
图4a为本发明实施例提供的又一种移位寄存器单元的结构示意图；
图4b为本发明实施例提供的一种移位寄存器单元中的驱动晶体管尺寸设计对比图；
图5为本发明实施例提供的一种移位寄存器单元中的驱动晶体管的分布图；
图6a为本发明实施例提供的另一种移位寄存器单元中的驱动晶体管的分布图；
图6b为本发明实施例提供的又一种移位寄存器单元中的驱动晶体管的分布图；
图6c为本发明实施例提供的一种移位寄存器单元中各个驱动晶体管的连接结构图。
附图标记：
(D1、D2…Dn)-驱动模块；(L1、L2…Ln)-逻辑模块；Signal_A-第一控制信号输出端；Signal_B-第二控制信号输出端；(Gate1、Gate2…Gaten)-栅线；(Data1、Data2…Datan)-数据线；01-阵列基板；10-栅极驱动电路；Input-第一信号输入端；Reset-第二信号输入端；Output-本级信号输出端；STV-起始信号；RST-复位信号；(SR1、SR2…SRn)-移位寄存器单元；CLK-第一驱动信号输入端；VSS-第二驱动信号输入端；T1-第一驱动晶体管；T2-第 二驱动晶体管；C-电容；200-驱动子模块；T1s-第一驱动子晶体管；Cs-子电容；T2s-第二子驱动晶体管；100-显示区域；101-非显示区域；102-像素单元；30-半导体有源层；31-过孔；40-中心区域；41-边缘区域；201-第一逻辑子模块；202-第二逻辑子模块。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
在研究中，本申请的发明人注意到，GOA电路中包括多个TFT，一些TFT通过导通和截止两种状态，控制GOA电路中部分线路的通断，从而实现信号的逻辑输出，因此上述TFT称为逻辑TFT；而一些TFT在导通状态下，能够向栅线输入扫描信号，以使得扫描信号能够通过栅线将显示区域中的像素单元开启，因此，上述TFT称为驱动TFT。由于输入栅线的扫描信号，能够控制位于同一行的多个像素单元的开启和关闭，所以栅线的负载较大。这样一来，就需要增大驱动TFT的尺寸。
上述驱动TFT的尺寸一般远大于所述逻辑TFT的尺寸。然而，由于GOA电路设置于阵列基板的非显示区域，而所述非显示区域对应显示面板的边框位置。因此当上述驱动TFT的尺寸较大时，会占据大量的版图空间，这不利于显示面板窄边框的设计趋势。
本发明实施例提供一种阵列基板01，如图1a所示，可以包括栅极驱动电路10。所述栅极驱动电路10如图1b所示，可以包括至少两级移位寄存器单元(SR1、SR2…SRn)，每一级移位寄存器单元(例如SRn)与一行栅线(例如Gaten)相连接。每个所述移位寄存器单元(例如SRn)可以包括驱动模块(例如Dn)以及逻辑模块(例如Ln)。其中，n≥2且为整数。
例如，驱动模块(D1、D2…Dn)包括位于阵列基板01的显示区域100的部分。
例如，逻辑模块(L1、L2…Ln)可以位于阵列基板01的非显示区域101。 或者，在一些实施例中，逻辑模块也可以位于阵列基板01的显示区域100内。
每个驱动模块(例如D1)分别连接逻辑模块(例如L1)、栅线(例如Gate1)以及第一驱动信号输入端CLK；在逻辑模块(例如L1)输出信号的控制下，将第一驱动信号输入端CLK输入的信号传输至栅线(例如Gate1)。
需要说明的是，第一、本发明实施例中的逻辑模块(L1、L2…Ln)可以包括多个用于实现逻辑运算的薄膜晶体管(图中未示出，以下简称逻辑TFT)。通过上述逻辑TFT可以实现部分电路的通断，从而实现可以对控制信号的输出进行逻辑运算，以实现移位输出。由于逻辑TFT输出端的负载较小，因此所述逻辑TFT的尺寸较小，一般可以为10μm。所以即使将由多个逻辑TFT构成的逻辑模块(L1、L2…Ln)设置于非显示区域101，也不会占用太大的布线空间。
第二、显示区域100内的多条横纵交叉的栅线(Gate1、Gate2…Gaten)与数据线(Data1、Data2…Datan)交叉界定出多个呈矩阵形式排列的像素单元102。上述驱动模块(D1、D2…Dn)可以包括设置于至少一个上述像素单元102内的部分，例如驱动模块可以设置于像素单元102内。本发明实施例对驱动模块(D1、D2…Dn)在显示区域100内的具***置不做限定，例如不同行的驱动模块可以均设置在第一列像素单元102中。也可以如图1a所示，不同行的驱动模块位于不同列的像素单元102中。
第三、如图1b所示，上述栅极驱动电路10中，除第一级移位寄存器单元SR1外，其余每一级移位寄存器单元的第一信号输入端Input与其相邻的上一级移位寄存器单元的本级信号输出端Output相连接。例如，第一级移位寄存器单元SR1的第一信号输入端Input接收起始信号STV或者输入复位信号RST。
除最后一级移位寄存器单元SRn外，其余每一级移位寄存器单元的第二信号输入端Reset与其相邻的下一级移位寄存器单元的本级信号输出端Output相连接。例如，最后一级移位寄存器单元SRn的第二信号输入端Reset可以输入复位信号RST或者接收起始信号SVT。
第四，移位寄存器单元的数量与显示区域的栅线Gate的数量相等。即每一级移位寄存器单元的本级信号输出端Output与显示区域的一行栅线Gate 相连接，从而通过多级移位寄存器对输入的扫描信号进行移位，来实现对各行栅线的逐行扫描。
以如图1b所示的栅极驱动电路10为例，还可以根据起始信号STV输入位置的不同实现不同方向的扫描。
例如，当上述栅极驱动电路的各级移位寄存器单元(SR1、SR2…SRn)中的第一级移位寄存器单元SR1的第一信号输入端Input接收起始信号STV，最后一级移位寄存器单元SRn的第二信号输入端Reset输入复位信号RST时，各级移位寄存器(SR1、SR2…SRn)的本级信号输出端Output按正向(从上至下)顺序地将扫描信号输出到与其相对应的栅线(Gate1、Gate2…Gaten)上。
当上述栅极驱动电路的各级移位寄存器单元(SR1、SR2…SRn)中的最后一级移位寄存器单元SRn的第二信号输入端Reset接收起始信号STV，第一级移位寄存器单元SR1的第一信号输入端Input输入复位信号RST时，各级的本级信号输出端Output按反向(从下至上)顺序地将扫描信号输出到与其相对应的栅线(Gaten、Gaten-1…Gate1)上。
当然上述描述仅仅是以如图1b所示的栅极驱动电路10为例进行的说明。其他结构的栅极驱动电路在此不再赘述，但均属于本发明的保护范围。
本发明实施例提供一种阵列基板，包括栅极驱动电路，栅极驱动电路包括至少两级移位寄存器单元，每一级移位寄存器单元与一行栅线相连接。从而可以依次向栅线输入扫描信号，以实现栅线的逐行扫描。为了实现移位输出的功能，所述移位寄存器单元包括用于向栅线输入扫描信号的驱动模块以及用于通过逻辑输出以实现移位功能的逻辑模块。例如，驱动模块位于阵列基板的显示区域；逻辑模块位于阵列基板的非显示区域。驱动模块分别连接逻辑模块、栅线以及第一驱动信号输入端；在逻辑模块输出信号的控制下，将第一驱动信号输入端输入的信号传输至栅线。由于栅线的负载较大，因此驱动模块相对于逻辑模块而言，其尺寸较大。所以当将尺寸较大的驱动模块设置于显示区域后，可以大大减小非显示区域的布线空间，从而实现窄边框的设计。
以下通过具体的实施例，对上述驱动模块(D1、D2…Dn)以及逻辑模块(L1、L2…Ln)进行举例说明。
实施例一
如图2所示，驱动模块(例如D1)可以包括:第一驱动晶体管T1和电容C。
第一驱动晶体管T1，其栅极连接逻辑模块(例如L1)的第一控制信号输出端Signal_A，第一极连接第一驱动信号输入端CLK，第二极与栅线(例如Gate1)相连接。
所述电容C的一端与第一驱动晶体管T1的栅极相连接，另一端连接第一驱动晶体管T1的第二极。
这样一来，当逻辑模块L1从第一控制信号输出端Signal_A输出的控制信号将第一驱动晶体管T1导通时，第一驱动信号输入端CLK输入的信号可以作为扫描信号输出至与移位寄存器单元SR1相对应的栅线Gate1上，以使得栅线Gate1将与其相连的一行像素单元102打开；当数据线(Data1、Data2…Datan)输入数据信号时，与栅线Gate1相连的一行像素单元102可以进行画面显示。
上述实施例中，第一驱动晶体管T1用于向栅线(Gate1、Gate2…Gaten)输入扫描信号，由于栅线(Gate1、Gate2…Gaten)的负载较大，因此第一驱动晶体管T1的尺寸较大，大概在1000μm左右，远大于一般用于实现逻辑运算的逻辑TFT(尺寸在10μm)。因此，将上述尺寸较大的第一驱动晶体管T1设置于显示区域100中，能够减小非显示区域101的布线空间，从而有利于显示面板窄边框的设计。
实施例二
如图3a所示，在实施例一的基础上，上述驱动模块(例如D1)还可以包括：第二驱动晶体管T2。
所述第二驱动晶体管T2的栅极连接逻辑模块(例如L1)的第二控制信号输出端Signal_B，第一极连接栅线(例如Gate1)，第二极与第二驱动信号输入端VSS相连接。
本发明实施例中，是以第二驱动信号输入端VSS输入低电平，或者接地为例进行的说明。
图3b所示为第一驱动晶体管T1和第二驱动晶体管T2的接线连接图。第一驱动晶体管T1的第二极通过过孔31与栅线Gate相连接。第二驱动晶体 管T2的第二极通过过孔31与第二驱动信号输入端VSS相连接。并且，构成第一驱动晶体管T1和第二驱动晶体管T2的半导体有源层30的材料可以是氧化物半导体有源层，例如氧化铟锡、氧化铟锌；或者可以由低温多晶硅构成；或者还可以由非晶硅构成。本发明实施例对此不作限制。
此外，构成第一驱动晶体管T1的第一极和第二极(源极和漏极)、第二驱动晶体管T2的第一极和第二极(源极和漏极)，以及第一驱动信号输入端CLK的连接线可以由制备数据线的数据金属层构成。而第一控制信号输出端Signal_A的连接线、第二控制信号输出端Signal_B的连接线以及第二驱动信号输入端VSS的连接线可以由制备栅线Gate的栅极金属层构成。
综上所述，上述移位寄存器单元(例如SR1)，不仅可以在输出阶段，通过逻辑模块(例如L1)从第一控制信号输出端Signal_A输出的控制信号将第一驱动晶体管T1导通，以可以将第一驱动信号输入端CLK输入的信号作为扫描信号输出至与移位寄存器单元SR1相对应的栅线Gate1上，而且在非输出阶段，还可以通过逻辑模块L1从第二控制信号输出端Signal_B输出的控制信号将第二驱动晶体管T2导通，将第二驱动信号输入端VSS输入的信号输出至移位寄存器单元SR1相对应的栅线Gate1上，由于第二驱动信号输入端VSS输入低电平，因此在移位寄存器单元SR1的非输出阶段，与其相对应的栅线Gate1不会输出扫描信号。
因此，通过在移位寄存器单元SR1中设置第一驱动晶体管T1以及第二驱动晶体管T2，可以在移位寄存器单元SR1的输出阶段，通过第一驱动晶体管T1将栅线Gate1信号拉高，以对栅线Gate1进行扫描；在非输出阶段，通过第二驱动晶体管T2将栅线Gate1信号拉低，从而可以防止移位寄存器单元在非输出阶段误输出扫描信号，确保栅极驱动电路具有较高的稳定性和可信赖性。
上述实施例中，第二驱动晶体管T2用于向栅线(Gate1、Gate2…Gaten)输入低电平。第二驱动晶体管T2的尺寸相对于第一驱动晶体管T1而言较小，一般为100μm左右。但是还是大于一般的用于实现逻辑运算的逻辑TFT(尺寸在10μm)。因此，将上述尺寸较大的第一驱动晶体管T1以及第二驱动晶体管T2设置于显示区域100中，能够减小非显示区域101的布线空间，从而有利于显示面板窄边框的设计。
实施例三
如图4a所示，所述驱动模块(例如D1)可以包括至少两个驱动子模块200，驱动子模块200可以包括第一驱动子晶体管T1s和子电容Cs。
第一子驱动晶体管T1s，其栅极连接逻辑模块(例如L1)的第一控制信号输出端Signal_A，第一极连接第一驱动信号输入端CLK，第二极与栅线(例如Gate1)相连接。
所述子电容Cs，其一端与第一子驱动晶体管T1s的栅极相连接，另一端连接第一子驱动晶体管T1s的第二极。
这样一来，当逻辑模块L1从第一控制信号输出端Signal_A输出的控制信号将多个第一子驱动晶体管T1s导通时，第一驱动信号输入端CLK输入的信号可以作为扫描信号输出至与移位寄存器单元SR1相对应的栅线Gate1上，以使得栅线Gate1将与其相连的一行像素单元102打开；当数据线(Data1、Data2…Datan)输入数据信号时，与栅线Gate1相连的一行像素单元102可以进行画面显示。
上述实施例中，多个第一子驱动晶体管T1s用于向栅线(Gate1、Gate2…Gaten)输入扫描信号。这样一来，多个第一子驱动晶体管T1s的尺寸之和可以等于一个第一驱动晶体管T1的尺寸，即多个第一子驱动晶体管T1s并联后可以为一个第一驱动晶体管T1。例如，第一驱动晶体管T1的尺寸为1000μm。当所述驱动模块(例如D1)可以包括至少十个驱动子模块200时，每个驱动子模块200中的第一子驱动晶体管T1s的尺寸可以为100μm。此外，子电容Cs的设置方式同上所述。
例如，如图4b所示，用于驱动第一行栅线Gate1的移位寄存器单元SR1包括位于非显示区域的逻辑模块L1和位于第一个像素单元102中的第一驱动晶体管T1。第一驱动晶体管T1的尺寸采用圆形表示。可以看出由于第一驱动晶体管T1的尺寸较大，因此占据了像素单元102的大部分面积，因此设置有第一驱动晶体管T1的像素单元102的开口率低。
然而，用于驱动第二行栅线Gate2的移位寄存器单元SR2包括位于非显示区域的逻辑模块L2和多个分别位于不同像素单元102中的多个第一子驱动晶体管T1s。第一子驱动晶体管T1s采用圆形表示，并且多个第一子驱动晶体管T1s的尺寸之和等于第一驱动晶体管T1的尺寸。由于第一子驱动晶 体管T1s的尺寸相对于第一驱动晶体管T1的尺寸而言较小。因此第一子驱动晶体管T1s占用像素单元102的面积也较小，因此与第二行栅线Gate2相连的像素单元102的开口率较大。
在上述方案的基础上，驱动子模块200还可以包括：第二子驱动晶体管T2s。
例如，所述第二子驱动晶体管T2s，其栅极连接逻辑模块(例如L1)的第二控制信号输出端Signal_B，第一极连接栅线(例如Gate1)，第二极与第二驱动信号输入端VSS相连接。
这样一来，上述移位寄存器单元(例如SR1)，不仅可以在输出阶段，通过逻辑模块L1从第一控制信号输出端Signal_A输出的控制信号将多个第一子驱动晶体管T1s导通，将第一驱动信号输入端CLK输入的信号可以作为扫描信号输出至与移位寄存器单元SR1相对应的栅线Gate1上。而且在非输出阶段，还可以通过逻辑模块L1从第二控制信号输出端Signal_B输出的控制信号将多个第二子驱动晶体管T2s导通，将第二驱动信号输入端VSS输入的信号输出至移位寄存器单元SR1相对应的栅线Gate1上，由于第二驱动信号输入端VSS输入低电平，因此在移位寄存器单元SR1的非输出阶段，与其相对应的栅线Gate1不会输出扫描信号。
综上所述，通过在移位寄存器单元SR1中设置多个第一子驱动晶体管T1s以及多个第二子驱动晶体管T2s，可以在移位寄存器单元SR1的输出阶段，通过多个第一子驱动晶体管T1s将栅线Gate1信号拉高，以对栅线Gate1进行扫描；在非输出阶段，通过多个第二子驱动晶体管T2s将栅线Gate1信号拉低，从而可以防止移位寄存器单元在非输出阶段误输出扫描信号，确保栅极驱动电路的具有较高的稳定性和可信赖性。
上述实施例中，多个第二子驱动晶体管T2s用于向栅线(Gate1、Gate2…Gaten)输入低电平。这样一来，多个第二子驱动晶体管T2s的尺寸之和可以等于一个第二驱动晶体管T2的尺寸，即多个第二子驱动晶体管T2s并联后可以为一个第二驱动晶体管T2。例如，第一驱动晶体管T2的尺寸为100μm。当所述驱动模块(例如D1)可以包括至少十个驱动子模块200时，每个驱动子模块200中的第二子驱动晶体管T2s的尺寸可以为10μm。
这样一来，一方面，尺寸较大的驱动模块(例如D1)设置于显示区域 100，可以减小非显示区域101的布线空间。另一方面，由于驱动模块(例如D1)中包括多个驱动子模块200，当将每个驱动子模块200分别设置于不同的像素单元102时，相对于将一个驱动模块(例如D1)设置于一个像素单元102时占用像素单元102的面积而言，驱动子模块200占用像素单元102的面积大大减小，从而可以减小对显示面板开口率的影响。因此上述实施例不仅可以实现窄边框设计，而且可以确保显示面板具有较高的开口率。
例如，所述显示区域100的每个像素单元102中可以设置有一个所述驱动子模块200。这样一来，可以进一步减小驱动子模块200中第一驱动子晶体管T1s和子电容Cs的尺寸。从而进一步减小对显示面板开口率的影响。
以下通过具体的实施例对多个第一驱动子晶体管T1s以及多个第二驱动子晶体管T2s在显示区域中的分布情况进行举例说明。
实施例四
如图5所示，每一级移位寄存器单元中每个驱动子模块包括的第一子驱动晶体管T1s与第二子驱动晶体管T2s分别位于同一行的两个相邻的像素单元102中。需要说明的是，图5为简化示意图，因此上述驱动晶体管以及逻辑模块(L1、L2…Ln)的具体连线未示出。
通过上述设置方法，可以将每一级移位寄存器单元中的第一子驱动晶体管T1s与第二子驱动晶体管T2s设置于不同的像素单元102中。因此相对于将驱动子模块200设置于一个像素单元102的方案而言，上述方案能够更进一步的减小对像素单元102面积的占用，从而可以提高显示面板的开口率。
实施例五
对于高PPI(Pixels Per Inch，每英寸所拥有的像素数目)显示面板而言，由于像素单元102的尺寸较小。因此为了满足窄边框的设计，可以在靠近显示区域100两侧的边缘区域41的位置处设置第一逻辑子模块201或第二逻辑子模块202。
例如，如图6a所示，逻辑模块(L1、L2…Ln)可以包括分别位于所述显示区域100两侧的第一逻辑子模块201和第二逻辑子模块202。
每一级移位寄存器单元中，第一逻辑子模块201连接第一子驱动晶体管T1s的栅极。
第二逻辑子模块202连接第二子驱动晶体管T2s的栅极。
第一子驱动晶体管T1s与第二子驱动晶体管T2s分别位于显示区域的中心区域40两侧的边缘区域41。
上述边缘区域41包括至少一列像素单元102。
所述中心区域40像素单元102的列数大于所述边缘区域41像素单元的列数。
需要说明的是，第一、上述边缘区域41可以是指位于显示面板两侧的靠近显示面板边框处的几列像素单元102，而中心区域40为显示面板上除了上述两侧的边缘区域41以外的区域。并且，中心区域40像素单元102的列数远大于边缘区域41像素单元102的列数。
第二、图6a为简化示意图，因此上述驱动晶体管以及逻辑模块(L1、L2…Ln)的具体连接结构未示出。
上述方案中，由于近在边缘区域41设置第一子驱动晶体管T1s与第二子驱动晶体管T2s。因此对于像素单元102尺寸非常小的高PPI显示面板而言，驱动晶体管只占用了一小部分有效显示区域的面积。因此，可以在实现窄边框设计的同时，减小对显示面板开口率的影响。
然而，如图6a所示的设置方式中，不同移位寄存器单元的第一子驱动晶体管T1s均设置于显示面板左侧的边缘区域41中，而移位寄存器单元的第二子驱动晶体管T2s均设置于显示面板右侧的边缘区域41中。由于第一子驱动晶体管T1s的尺寸大于第二子驱动晶体管T2s的尺寸。这样一来将会导致，显示面板左侧边缘区域41与右侧边缘区域41的开口率相差很大，使得画面的显示亮度不均匀，降低了显示效果。
因此，为了解决上述问题，如图6b所示，在位于同一侧边缘区域41的相邻两行所述像素单元102中，一行的每个像素单元102对应一个第一子驱动晶体管T1s，另一行的每个像素单元102对应一个第二子驱动晶体管T2s。通过对相邻移位寄存器单元中的第一子驱动晶体管T1s和第二子驱动晶体管T2s进行交叉设置，使得两侧的边缘区域41被上述驱动晶体管占用的面积相当，从而使得上述驱动晶体管对两侧的边缘区域41开口率的影响程度相当。进而能够提高显示画面的亮度均匀性，提升显示效果。
例如，相邻移位寄存器单元中的第一子驱动晶体管T1s和第二子驱动晶体管T2s进行交叉设置的方案的具体接线图如图6c所示。可以看出，由于对 相邻移位寄存器单元中的第一子驱动晶体管T1s和第二子驱动晶体管T2s进行了交叉设置。因此，不同行的上述第一逻辑子模块201和第二逻辑子模块202的位置也不同。
例如，对于第一行像素单元102而言，第一逻辑子模块201(L1)位于图6c的左侧的边缘区域41中，第二逻辑子模块202(L1’)位于图6c的右侧的边缘区域41中。然而，对于第二行像素单元102而言，对移位寄存器单元SR2的第一子驱动晶体管T1s和第二子驱动晶体管T2s的位置进行了互换，因此第二逻辑子模块202(L2)位于图6c的左侧的边缘区域41中，第一逻辑子模块201(L2’)位于图6c的右侧的边缘区域41中。
本发明实施例的附图仅以驱动模块设置于阵列基板的显示区域为例进行说明，但本发明实施例不限于此。例如，各级移位寄存单元中的第一驱动晶体管可以设置于显示区域中，且第二驱动晶体管可以设置于非显示区域中。
本发明实施例提供一种显示装置，包括如上所述的任意一种阵列基板。具有与前述实施例提供的阵列基板相同的结构和有益效果。由于前述实施例中已经将阵列基板的结构和有益效果进行了详细的描述，此处不再赘述。
在本发明实施例中，显示装置具体可以包括液晶显示装置或OLED显示装置等，例如该显示装置可以为液晶面板、液晶显示器、液晶电视、OLED面板、电子纸、数码相框、手机或平板电脑等任何具有显示功能的产品或者部件。
本领域普通技术人员可以理解：实现上述方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成，前述的程序可以存储于一计算机可读取存储介质中，该程序在执行时，执行包括上述方法实施例的步骤；而前述的存储介质包括：ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2015年1月4日递交的中国专利申请第201510001826.4号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (12)

  1. 一种阵列基板，包括栅极驱动电路，其中，所述栅极驱动电路包括至少两级移位寄存器单元，每一级所述移位寄存器单元与一行栅线相连接，所述移位寄存器单元包括驱动模块以及逻辑模块；
    所述驱动模块包括位于所述阵列基板的显示区域的部分；
    每个所述驱动模块分别连接所述逻辑模块、所述栅线以及第一驱动信号输入端，并且在所述逻辑模块输出信号的控制下，将所述第一驱动信号输入端输入的信号传输至所述栅线。
  2. 根据权利要求1所述的阵列基板，其中，所述逻辑模块位于所述阵列基板的非显示区域或显示区域。
  3. 根据权利要求1或2所述的阵列基板，还包括：设置于所述显示区域内的多个像素单元，其中，所述驱动模块包括位于至少一个所述像素单元内的部分。
  4. 根据权利要求1～3任一项所述的阵列基板，其中，所述驱动模块包括：第一驱动晶体管和电容；
    所述第一驱动晶体管，其栅极连接所述逻辑模块的第一控制信号输出端，第一极连接所述第一驱动信号输入端，第二极与所述栅线相连接；
    所述电容，其一端与所述第一驱动晶体管的栅极相连接，另一端连接所述第一驱动晶体管的第二极。
  5. 根据权利要求4所述的阵列基板，其中，所述驱动模块还包括：第二驱动晶体管；
    所述第二驱动晶体管，其栅极连接所述逻辑模块的第二控制信号输出端，第一极连接所述栅线，第二极与第二驱动信号输入端相连接。
  6. 根据权利要求1～3任一项所述的阵列基板，其中，所述驱动模块包括至少两个驱动子模块，所述驱动子模块包括第一驱动子晶体管和子电容；
    所述第一子驱动晶体管，其栅极连接所述逻辑模块的第一控制信号输出端，第一极连接所述第一驱动信号输入端，第二极与所述栅线相连接；
    所述子电容，其一端与所述第一子驱动晶体管的栅极相连接，另一端连接所述第一子驱动晶体管的第二极。
  7. 根据权利要求6所述的阵列基板，其中，所述驱动子模块还包括：第二子驱动晶体管；
    所述第二子驱动晶体管，其栅极连接所述逻辑模块的第二控制信号输出端，第一极连接所述栅线，第二极与第二驱动信号输入端相连接。
  8. 根据权利要求6或7所述的阵列基板，还包括：设置于所述显示区域的多个像素单元，其中，所述显示区域的每个像素单元中设置有一个所述驱动子模块。
  9. 根据权利要求7所述的阵列基板，其中，每一级所述移位寄存器单元中的所述第一子驱动晶体管与所述第二子驱动晶体管分别位于同一行的两个相邻的所述像素单元中。
  10. 根据权利要求7所述的阵列基板，其中，
    所述逻辑模块包括分别位于所述显示区域两侧的第一逻辑子模块和第二逻辑子模块；
    其中，每一级所述移位寄存器单元的所述第一逻辑子模块连接所述第一子驱动晶体管的栅极；
    所述第二逻辑子模块连接所述第二子驱动晶体管的栅极；
    所述第一子驱动晶体管与所述第二子驱动晶体管分别位于所述显示区域的中心区域两侧的边缘区域；
    其中，所述边缘区域包括至少一列像素单元；
    所述中心区域像素单元的列数大于所述边缘区域像素单元的列数。
  11. 根据权利要求10所述的阵列基板，其中，位于同一侧所述边缘区域的相邻两行所述像素单元中，一行的每个所述像素单元对应一个所述第一子驱动晶体管，另一行的每个所述像素单元对应一个所述第二子驱动晶体管。
  12. 一种显示装置，包括权利要求1-11任一项所述的阵列基板。
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