WO2016101792A1 - Clock device and method for maintaining clock - Google Patents
Clock device and method for maintaining clock Download PDFInfo
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- WO2016101792A1 WO2016101792A1 PCT/CN2015/097014 CN2015097014W WO2016101792A1 WO 2016101792 A1 WO2016101792 A1 WO 2016101792A1 CN 2015097014 W CN2015097014 W CN 2015097014W WO 2016101792 A1 WO2016101792 A1 WO 2016101792A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
Definitions
- This application relates to, but is not limited to, the field of communication technology.
- Ethernet-based clock transmission technology has been more and more widely used, and its output clock performance can basically meet the ITU-T for ITU Telecommunication Standardization Sector.
- the specified clock characteristics due to the variety of application scenarios, the application methods are also various, and the clock performance needs to be improved in some application scenarios. For example, when an upstream clock device transmits a clock to a downstream clock device through Ethernet, if the link is suddenly broken or the clock suddenly disappears, the ITU-T standard requires the downstream clock device to enter the hold mode, that is, the clock hold state, and maintain the accuracy. Meet the performance requirements specified by the standard.
- a common method of the related art is that after detecting that the clock in the link is out of lock, the downstream clock interface device sends the unavailable clock quality level information DNU to the downstream clock processing device. After receiving the DNU information, the downstream clock processing device needs to The DNU information is parsed, and the analysis mode is completed before entering the hold mode. In this way, when the downstream clock interface device detects that the clock in the link is out of lock until the downstream clock processing device enters the hold mode, the DNU information needs to be forwarded and parsed, and the locking source of the downstream clock processing device is The original link clock becomes a local crystal oscillator, causing the output clock to jump and the system clock to jump.
- the present invention provides a clock device and method for maintaining a clock to solve the technical problem that the system clock hopping in the related art clock device takes too long.
- a clock device for holding a clock includes: a clock interface module and a clock processing module, wherein
- the clock interface module is configured to: monitor a received clock link signal, and when it is determined that the clock link signal is abnormal, turn off a clock output of the clock interface module;
- the clock processing module is configured to: when detecting that the clock output of the clock interface module is in a closed state, enter a clock hold state and output a system clock.
- the clock interface module includes: a detecting unit and a clock driving unit, where
- the detecting unit is configured to: receive and detect a clock link signal sent by the upstream clock device, and when determining that the state of the clock link signal is abnormal, send a switch control signal to the clock driving unit;
- the clock driving unit is configured to turn off a clock output of the clock interface module according to the switch control signal.
- the clock interface module includes a detecting unit, a filtering unit, and a clock driving unit, where:
- the detecting unit is configured to: receive and detect a clock link signal sent by the upstream clock device, and notify the filtering unit when determining that the state of the clock link signal is abnormal;
- the filtering unit is configured to perform noise filtering processing on the clock link signal that is determined to be abnormal by the detecting unit, and detect the clock link signal after the noise filtering process, when determining the When the state of the clock link signal after the noise filtering process is abnormal, sending a switch control signal to the clock driving unit;
- the clock driving unit is configured to turn off a clock output of the clock interface module according to the switch control signal.
- the clock processing module is configured to:
- phase locked loop circuit When the phase locked loop circuit detects that the clock interface module has no clock output within a preset time When it enters the clock hold state, it outputs the system clock.
- the clock link signal is an Ethernet signal or a second pulse signal.
- a clock holding method of a clock device includes: a clock interface module and a clock processing module, and the method includes:
- the clock interface module monitors the received clock link signal, and when it is determined that the clock link signal is abnormal, the clock output of the clock interface module is turned off;
- the clock processing module enters a clock hold state and outputs a system clock when detecting that the clock output of the clock interface module is in a closed state.
- the clock interface module monitors the received clock link signal, and when determining that the clock link signal is abnormal, the step of turning off the clock output of the clock interface module includes:
- the clock interface module receives and detects a clock link signal sent by the upstream clock device, and when it is determined that the state of the clock link signal is abnormal, generates a switch control signal, and closes the clock interface module according to the switch control signal. Clock output.
- the clock interface module monitors the received clock link signal, and when determining that the clock link signal is abnormal, the step of turning off the clock output of the clock interface module includes:
- the clock interface module receives and detects a clock link signal sent by the upstream clock device, performs noise filtering processing on the clock link signal that is determined to be abnormal, and detects the clock link signal after the noise filtering process. And determining that a state of the clock link signal after the noise filtering process is abnormal, generating a switch control signal, and turning off a clock output of the clock interface module according to the switch control signal.
- the clock processing module enters a clock hold state when detecting that the clock output of the clock interface module is in an off state, and the step of outputting the system clock includes:
- phase-locked loop circuit When the phase-locked loop circuit detects that the clock interface module has no clock output within a preset time, it enters a clock hold state and outputs a system clock.
- the clock link signal is an Ethernet signal or a second pulse signal.
- a computer readable storage medium storing computer executable instructions, the computer being executable
- the line instructions are used to perform the method of any of the above.
- the clock device and method for maintaining a clock when the clock interface module in the clock device detects that an abnormality occurs in the clock link signal sent by the upstream clock device, the clock output of the clock interface module is turned off;
- the clock processing module in the clock device detects that the clock output of the clock interface module is in the off state, it can know that the clock link signal is abnormal, and immediately enters the clock hold state and outputs the system clock without the clock interface module being
- the DNU information is sent to the clock processing module, and the clock processing module parses the DNU information to enter the clock hold state, thereby reducing the cumbersome operation of forwarding and parsing the DNU information, so that the clock device is in the clock device.
- the clock processing module can quickly enter the clock hold state, which minimizes the time from the clock interface module detecting the clock link signal abnormality to the clock processing module entering the clock hold state, thereby greatly reducing the clock processing module output system clock. Frequency jump and control Within 1ppb, clock device to satisfy the performance retention should have.
- FIG. 1 is a schematic diagram of functional modules of a first embodiment of a clock device for holding a clock according to an embodiment of the present invention
- FIG. 2 is a schematic diagram of a refinement function module of the clock interface module 01 of FIG. 1;
- FIG. 3 is a schematic diagram of a refinement function module of a clock interface module 01 in a second embodiment of a clock device for holding a clock according to the present invention
- FIG. 4 is a schematic flow chart of an embodiment of a clock holding method of a clock device according to the present invention.
- Embodiments of the present invention provide a clock device that holds a clock.
- FIG. 1 is a schematic diagram of functional modules of a first embodiment of a clock device for holding a clock according to the present invention.
- the clock device includes: a clock interface module 01 and a clock processing module 02, where
- the clock interface module 01 is configured to: monitor the received clock link signal, and when it is determined that the clock link signal is abnormal, turn off the clock output of the clock interface module 01;
- the clock processing module 02 is configured to enter a clock hold state and output a system clock when detecting that the clock output of the clock interface module 01 is in a closed state.
- the clock processing module 02 in the clock device detects When the clock output of the clock interface module 01 is in the off state, the clock link signal is abnormal, and the clock hold state is immediately entered, and the system clock is output, without the clock interface module 01 detecting the abnormality of the clock link signal.
- the DNU information is sent to the clock processing module 02, and the clock processing module 02 can parse the DNU information to enter the clock hold state, thereby reducing the cumbersome operation of forwarding and parsing the DNU information, so that the clock processing module 02 in the clock device can Quickly enter the clock hold state, which minimizes the time from when the clock interface module 01 detects the clock link signal abnormality to when the clock processing module 02 enters the clock hold state, thereby greatly reducing the frequency hop of the clock processing module 02 outputting the system clock. Change and control within 1 ppb to meet the clock device It has maintained performance.
- the clock interface module 01 includes: a detecting unit 03 and a clock driving unit 04, where
- the detecting unit 03 is configured to: receive and detect a clock link signal sent by the upstream clock device, and when it is determined that the state of the clock link signal is abnormal, send a switch control signal to the clock driving unit 04;
- the clock driving unit 04 is configured to turn off the clock output of the clock interface module 01 according to the switch control signal.
- the detecting unit 03 monitors the clock link signal sent by the upstream clock device in real time, and detects the state of the received clock link signal.
- the state of the clock link signal is abnormal, the description is If the data link is disconnected or the clock link signal is lost, the clock interface module 01 loses the clock source input from the upstream clock device, and cannot recover the clock in the clock link signal, that is, it automatically locks on the local crystal oscillator, but this The clock interface module 01 does not output the local crystal oscillator locked at this time, that is, the local oscillator clock, but the detection unit 03 sends a switch control signal to the clock drive unit 04; the clock drive unit 04 controls the switch according to the detection unit 03.
- the signal is used to control the clock output of the clock interface module 01.
- the switch control signal is sent to the clock driving unit 04, and the clock driving unit 04 can be turned off according to the switch control signal.
- the clock output of the clock interface module 01 is such that the output clock of the clock interface module 01 becomes a high impedance state.
- the above clock processing module 02 is set to:
- phase-locked loop circuit When the phase-locked loop circuit detects that the clock interface module 01 has no clock output within a preset time, it enters a clock hold state and outputs a system clock.
- the clock processing module 02 can perform detection by using a phase locked loop circuit.
- the clock processing module 02 uses a phase-locked loop circuit to lock the clock of the normal clock link signal recovery or enters the clock hold state, and the phase-locked loop circuit enters the clock hold state, except that the configuration command can be issued. It can also automatically enter the clock hold state when the phase-locked loop circuit detects the loss of the clock source. This is a basic function that most phase-locked loop chips have, and is used in the clock device of the synchronous digital system. Phase-locked loop circuits must have this capability.
- the clock processing module 02 of the clock device in this embodiment can use the phase-locked loop circuit to detect the clock output state of the clock interface module 01, and the phase-locked loop circuit in the clock processing module 02 detects the preset time.
- the clock interface module 01 has no clock output, it can be known that the clock link signal is abnormal, and the clock source is lost, the clock processing module 02 immediately enters the clock hold state and outputs the system clock.
- the preset time may be set, and the preset time may be set lower according to requirements.
- the clock processing module 02 can immediately enter the clock hold state, thereby reducing the detection cost. Time to make the clock Processing module 02 enters the clock hold state more quickly, thereby reducing the frequency hopping of the output system clock.
- the clock processing module 02 uses the hardware of the phase-locked loop circuit to detect the clock output state of the clock interface module 01 within a preset time, and when detecting that the clock interface module 01 has no clock output, Automatically enters the clock hold state, outputs the system clock, and shortens the time when the clock processing module 02 enters the clock hold state as much as possible, without the clock interface module 01 sending the DNU information to the clock processing module 02 when detecting that the clock link signal is abnormal.
- the clock processing module 02 After the clock processing module 02 parses the DNU information, it can enter the clock hold state, which reduces the cumbersome operation of forwarding and parsing the DNU information, so that the clock processing module 02 in the clock device can quickly enter the clock hold state, maximizing The time from when the clock interface module 01 detects the abnormality of the clock link signal to the time when the clock processing module 02 enters the clock hold state is shortened, thereby greatly reducing the frequency jump of the output system clock of the clock processing module 02, and controlling it within 1 ppb, Meet the retention performance that clock devices should have.
- a second embodiment of the present invention provides a clock device for holding a clock.
- the clock interface module 01 includes a detecting unit 03, a filtering unit 05, and a clock driving unit 04. ,among them:
- the detecting unit 03 is configured to: receive and detect a clock link signal sent by the upstream clock device, and when it is determined that the state of the clock link signal is abnormal, notify the filtering unit 05;
- the filtering unit 05 is configured to: perform noise filtering processing on the clock link signal that is determined to be abnormal by the detecting unit 03, and detect the clock link signal after the noise filtering process, when determining the When the state of the clock link signal after the noise filtering process is abnormal, send a switch control signal to the clock drive unit 04;
- the clock driving unit 04 is configured to turn off the clock output of the clock interface module 01 according to the switch control signal.
- the filtering unit 05 when the detecting unit 03 detects that the state of the clock link signal is abnormal, the filtering unit 05 first performs noise filtering processing on the clock link signal that is determined to be abnormal by the detecting unit 03, and continues to perform the noise filtering process.
- the clock link signal processed by the noise filtering is detected, if Still detecting the abnormal state of the clock link signal, the switch control signal is sent to the clock drive unit 04, so that the clock drive unit 04 turns off the clock output of the clock interface module 01 according to the switch control signal.
- the switch control signal is sent to the clock driving unit 04, effectively avoiding the upstream
- the short-term instability or environmental interference of the clock transmission link of the clock device may cause the detection unit 03 to misjudge the situation, and the state of the clock link signal sent by the upstream clock device may be more accurately determined, thereby confirming the clock link.
- the clock driving unit 04 turns off the clock output of the clock interface module 01, which reduces the possibility that the clock processing module 02 enters the clock holding state due to misjudgment, and enhances the clock device. stability.
- the clock link signal sent by the upstream clock device may be an Ethernet signal or a second pulse (1PPS) signal.
- the interface type of the Ethernet-based clock transmission is Ethernet optical port and Ethernet electrical port.
- the clock interface module 01 receives the synchronous Ethernet signal transmitted by the upstream clock device through the optical fiber, the optical module itself can generate signal loss.
- the LOS indicator signal, and the noise filtering process is performed inside the optical module, that is, the optical module itself performs noise filtering, loss detection, and the like on the signal loss. Therefore, in the actual application, if the detecting unit 03 of the clock interface module 01 acquires the synchronization ether
- the switch control signal is sent to the clock drive according to the LOS indication signal in the synchronous Ethernet signal.
- the unit 04 is configured to cause the clock driving unit 04 to turn off the clock output of the clock interface module 01 according to the switch control signal.
- the synchronous Ethernet physical layer chip When the clock interface module 01 receives the synchronous Ethernet signal transmitted by the upstream clock device through the network cable, the synchronous Ethernet physical layer chip will generate a signal loss interrupt, and the interrupt will also generate noise inside the synchronous Ethernet physical layer chip. Filtering processing, therefore, in the actual application, if the detecting unit 03 of the clock interface module 01 acquires the signal loss interrupt in the synchronous Ethernet signal, the state of the clock link signal is directly known to be abnormal, and no further noise filtering processing is required. And transmitting a switch control signal to the clock driving unit 04 according to a signal loss in the synchronous Ethernet signal, so that the clock driving unit 04 turns off the clock according to the switch control signal Clock output of interface module 01.
- the detecting unit 03 of the clock interface module 01 detects the state of the received 1PPS signal in real time, and detects that the state of the 1PPS signal is abnormal.
- the 1PPS signal is sent to the filtering unit 05, and the filtering unit 05 performs noise filtering processing on the 1PPS signal, and continues to detect the 1PPS signal after the noise filtering process. If the state of the 1PPS signal is still abnormal, the signal is sent.
- the control signal is switched to the clock driving unit 04 to cause the clock driving unit 04 to turn off the clock output of the clock interface module 01 according to the switching control signal. Further, when the phase locked loop circuit in the clock processing module 02 detects that the clock interface module 01 has no clock output within a preset time, it can immediately enter the clock hold state and output the system clock.
- Embodiments of the present invention provide a clock holding method of a clock device.
- the clock device includes: a clock interface module and a clock processing module.
- FIG. 4 is a schematic flowchart diagram of an embodiment of a clock holding method of a clock device according to the present invention.
- the clock keeping method of the clock device includes:
- Step S10 the clock interface module monitors the received clock link signal, and when it is determined that the clock link signal is abnormal, the clock output of the clock interface module is turned off;
- Step S20 the clock processing module enters a clock hold state and outputs a system clock when detecting that the clock output of the clock interface module is in a closed state.
- the clock processing module in the clock device detects the When the clock output of the clock interface module is off, you can know that the clock link signal is abnormal, and immediately enter the clock hold state and output the system clock.
- the clock processing module is sent to the clock processing module.
- the clock processing module parses the DNU information to enter the clock hold state, which reduces the cumbersome operation of forwarding and parsing the DNU information, so that the clock processing module in the clock device can quickly enter the clock hold state, and the maximum Limiting the slave clock interface module
- the time when the clock link signal is abnormal until the clock processing module enters the clock hold state is detected, thereby greatly reducing the frequency jump of the clock processing module output system clock, and controlling it within 1 ppb to meet the retention performance that the clock device should have.
- the step S10 may include: the clock interface module receives and detects a clock link signal sent by the upstream clock device, and when determining that the state of the clock link signal is abnormal, generates a switch control signal, and according to The switch control signal turns off the clock output of the clock interface module.
- the clock interface module monitors the clock link signal sent by the upstream clock device in real time, and detects the state of the received clock link signal.
- the state of the clock link signal is abnormal, the data link is disconnected or If the clock link signal is lost, the clock interface module loses the clock source input from the upstream clock device and cannot recover the clock in the clock link signal, that is, it is automatically locked on the local crystal oscillator. However, the clock interface module does not output.
- the local crystal oscillator locked at this time is the local oscillator clock, but generates a switch control signal, and controls the clock output of the clock interface module according to the generated switch control signal.
- the clock output of the clock interface module is turned off according to the generated switch control signal, so that the output clock of the clock interface module becomes a high impedance state.
- step S20 may include:
- phase-locked loop circuit When the phase-locked loop circuit detects that the clock interface module has no clock output within a preset time, it enters a clock hold state and outputs a system clock.
- the clock processing module may use a phase locked loop circuit for detecting. Because the clock processing module uses a phase-locked loop circuit to lock the clock of the normal clock link signal recovery or enters the clock hold state, and the phase-locked loop circuit enters the clock hold state, in addition to the way of issuing the configuration command, When the phase-locked loop circuit detects that the clock source is lost, it automatically enters the clock hold state, which is a basic function of most phase-locked loop chips, and the lock used in the clock device of the synchronous digital system. Phase loop circuits must have this capability.
- the clock processing module of the clock device in this embodiment may use a phase locked loop circuit to detect a clock output state of the clock interface module, and the phase locked loop circuit in the clock processing module detects the clock interface module within a preset time.
- the clock link signal is abnormal. If the clock source is lost, the clock processing module immediately enters the clock hold state and outputs the system clock.
- the preset time may be set, and the preset time may be set to be lower as needed.
- the clock processing module can immediately enter the clock hold state, reducing the time taken for the detection, This enables the clock processing module to enter the clock hold state more quickly, thereby reducing the frequency hopping of the output system clock.
- the clock processing module uses the hardware means of the phase-locked loop circuit to detect the clock output state of the clock interface module within a preset time, and automatically enters the clock when detecting that the clock interface module has no clock output. Maintaining the state, outputting the system clock, shortening the time that the clock processing module enters the clock hold state as much as possible, without the clock interface module sending DNU information to the clock processing module when the clock link signal is abnormal, and the clock processing module is again After the DNU information is parsed, it can enter the clock hold state, which reduces the cumbersome operation of DNU information forwarding and parsing, so that the clock processing module in the clock device can quickly enter the clock hold state, and the slave clock interface module detection is minimized.
- the time until the clock link signal is abnormal until the clock processing module enters the clock hold state thereby greatly reducing the frequency jump of the clock processing module output system clock, and controlling it within 1 ppb to meet the retention performance that the clock device should have.
- the second embodiment of the present invention provides a clock holding method for a clock device. Based on the foregoing first embodiment, the foregoing step S10 includes:
- the clock interface module receives and detects a clock link signal sent by the upstream clock device, performs noise filtering processing on the clock link signal that is determined to be abnormal, and detects the clock link signal after the noise filtering process. And determining that a state of the clock link signal after the noise filtering process is abnormal, generating a switch control signal, and turning off a clock output of the clock interface module according to the switch control signal.
- the clock interface module when the clock interface module detects that the state of the clock link signal is abnormal, Performing noise filtering processing on the clock link signal that is determined to be abnormal, and continuing to detect the clock link signal after the noise filtering process, and if the state of the clock link signal is still abnormal, And switching a control signal to turn off a clock output of the clock interface module according to the switch control signal.
- the switch control signal is generated only when the state of the clock link signal is abnormally detected, which effectively avoids the short-term instability that may exist due to the clock transmission link of the upstream clock device.
- the state of the clock link signal sent by the upstream clock device can be more accurately judged, and then the clock interface signal is turned off when the clock link signal is in an abnormal state such as a signal loss.
- the clock output reduces the possibility of the clock processing module entering the clock hold state due to misjudgment, and enhances the stability of the clock device.
- the clock link signal sent by the upstream clock device may be an Ethernet signal or a second pulse (1PPS) signal.
- Ethernet interface-based clock transmission commonly used as Ethernet optical port and Ethernet electrical port.
- the clock interface module receives the synchronous Ethernet signal transmitted by the upstream clock device through the optical fiber, the optical module itself can generate signal loss LOS.
- the signal is indicated, and noise filtering is performed inside the optical module, that is, the optical module itself performs noise filtering and loss detection on the signal loss. Therefore, in practical applications, if the clock interface module acquires the LOS in the synchronous Ethernet signal.
- the indication signal can directly know that the state of the clock link signal is abnormal, and no further noise filtering processing is needed, and a switch control signal is generated according to the LOS indication signal in the synchronous Ethernet signal to turn off the switch according to the switch control signal. Clock output of the clock interface module.
- the synchronous Ethernet physical layer chip When the clock interface module receives the synchronous Ethernet signal transmitted by the upstream clock device through the network cable, the synchronous Ethernet physical layer chip generates a signal loss interrupt, and the interrupt is generated by noise filtering inside the synchronous Ethernet physical layer chip. Processing, therefore, in the actual application, if the clock interface module acquires the signal loss interrupt in the synchronous Ethernet signal, it can directly know that the state of the clock link signal is abnormal, and no further noise filtering processing is required, and according to the synchronous Ethernet A signal loss interrupt in the signal generates a switch control signal to turn off the clock output of the clock interface module in accordance with the switch control signal.
- the clock interface module When the clock interface module receives the second pulse transmitted by the upstream clock device through the 1PPS interface
- the clock interface module detects the state of the received 1PPS signal in real time.
- the state of the 1PPS signal is abnormal, the noise filtering process is performed on the 1PPS signal, and the 1PPS signal after the noise filtering process is continued.
- the detection is performed, and if the state of the 1PPS signal is still abnormal, the switch control signal is generated to turn off the clock output of the clock interface module according to the switch control signal.
- the phase locked loop circuit in the clock processing module detects that the clock interface module has no clock output within a preset time, it can immediately enter the clock hold state and output the system clock.
- all or part of the steps of the above embodiments may also be implemented by using an integrated circuit. These steps may be separately fabricated into individual integrated circuit modules, or multiple modules or steps may be fabricated into a single integrated circuit module. achieve.
- the devices/function modules/functional units in the above embodiments may be implemented by a general-purpose computing device, which may be centralized on a single computing device or distributed over a network of multiple computing devices.
- the device/function module/functional unit in the above embodiment When the device/function module/functional unit in the above embodiment is implemented in the form of a software function module and sold or used as a stand-alone product, it can be stored in a computer readable storage medium.
- the above mentioned computer readable storage medium may be a read only memory, a magnetic disk or an optical disk or the like.
- the clock device and method for maintaining a clock when the clock interface module in the clock device detects that an abnormality occurs in the clock link signal sent by the upstream clock device, the clock output of the clock interface module is turned off;
- the clock processing module in the clock device can know the clock link signal when detecting that the clock output of the clock interface module is in the off state. Normally, the clock state is immediately entered and the system clock is output, and the clock interface module does not need to send DNU information to the clock processing module when the clock link signal is abnormal.
- the clock processing module parses the DNU information before entering the clock.
- Maintaining the state reduces the cumbersome operation of DNU information forwarding and parsing, so that the clock processing module in the clock device can quickly enter the clock hold state, which minimizes the detection of the clock link signal abnormality from the clock interface module to the clock processing.
- the time that the module enters the clock hold state greatly reduces the frequency jump of the clock processing module output system clock and controls it within 1 ppb to meet the retention performance of the clock device.
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Abstract
Disclosed in the present invention are a clock device and method for maintaining clock, the clock device comprising: a clock interface module and a clock processing module, the clock interface module being configured to monitor a received clock link signal, when the clock link signal is detected to be abnormal, turning off a clock output of the clock interface module; the clock processing module is configured to enter a clock maintaining state and output a system clock when the clock output of the clock interface module is detected to be a turned-off state.
Description
本申请涉及但不限于通信技术领域。This application relates to, but is not limited to, the field of communication technology.
目前在同步数字体系时钟传送方面,基于以太网的时钟传送技术已得到越来越广泛的应用,其输出时钟性能已基本能满足国际电信联盟远程通信标准化组织(ITU-T for ITU Telecommunication Standardization Sector)所规定的时钟特性。但由于应用场景变化多端,应用方式也各式各样,在一些应用情景下时钟性能还有待改善。比如,当上游时钟设备通过以太网传递时钟给下游时钟设备时,如果链路突然断掉或时钟突然消失,ITU-T标准要求下游时钟设备能进入到保持模式即时钟保持状态,且保持精度要满足标准规定的性能要求。At present, in the synchronous digital system clock transmission, Ethernet-based clock transmission technology has been more and more widely used, and its output clock performance can basically meet the ITU-T for ITU Telecommunication Standardization Sector. The specified clock characteristics. However, due to the variety of application scenarios, the application methods are also various, and the clock performance needs to be improved in some application scenarios. For example, when an upstream clock device transmits a clock to a downstream clock device through Ethernet, if the link is suddenly broken or the clock suddenly disappears, the ITU-T standard requires the downstream clock device to enter the hold mode, that is, the clock hold state, and maintain the accuracy. Meet the performance requirements specified by the standard.
发明内容Summary of the invention
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。The following is an overview of the topics detailed in this document. This Summary is not intended to limit the scope of the claims.
相关技术的常用的方式是下游时钟接口设备一旦检测到链路中的时钟失锁后,则发送不可用时钟质量等级信息DNU给下游时钟处理设备,下游时钟处理设备接收到该DNU信息后,需要对该DNU信息进行解析,解析完成后才能进入到保持模式。这样,在下游时钟接口设备检测到链路中的时钟失锁直到下游时钟处理设备进入到保持模式的过程中需要经过DNU信息的转发及解析等操作流程,同时,下游时钟处理设备的锁定源由原来的链路时钟变为本地晶振,使得输出时钟发生跳变,***时钟也随之跳变。经测试发现,在下游时钟接口设备检测到链路中的时钟失锁,经过DNU信息的转发及解析操作直到下游时钟处理设备进入到保持模式的过程需要花费的时间为ms(毫秒)级,使得***时钟产生ppm级的频率跳变,无法满足ITU-T标准
要求的下游时钟设备应具备的保持性能。A common method of the related art is that after detecting that the clock in the link is out of lock, the downstream clock interface device sends the unavailable clock quality level information DNU to the downstream clock processing device. After receiving the DNU information, the downstream clock processing device needs to The DNU information is parsed, and the analysis mode is completed before entering the hold mode. In this way, when the downstream clock interface device detects that the clock in the link is out of lock until the downstream clock processing device enters the hold mode, the DNU information needs to be forwarded and parsed, and the locking source of the downstream clock processing device is The original link clock becomes a local crystal oscillator, causing the output clock to jump and the system clock to jump. It has been found that the time that the downstream clock interface device detects that the clock in the link is out of lock, after the DNU information is forwarded and parsed until the downstream clock processing device enters the hold mode takes ms (milliseconds). The system clock generates a frequency jump of ppm level and cannot meet the ITU-T standard.
The required downstream clock device should have the retention performance.
本文提供一种保持时钟的时钟设备及方法,以解决相关技术的时钟设备中***时钟跳变花费时间过长的技术问题。The present invention provides a clock device and method for maintaining a clock to solve the technical problem that the system clock hopping in the related art clock device takes too long.
一种保持时钟的时钟设备,所述时钟设备包括:时钟接口模块及时钟处理模块,其中,A clock device for holding a clock, the clock device includes: a clock interface module and a clock processing module, wherein
所述时钟接口模块,设置为:监测接收的时钟链路信号,当判断所述时钟链路信号异常时,关闭所述时钟接口模块的时钟输出;The clock interface module is configured to: monitor a received clock link signal, and when it is determined that the clock link signal is abnormal, turn off a clock output of the clock interface module;
所述时钟处理模块,设置为:当检测到所述时钟接口模块的时钟输出处于关闭状态时,进入时钟保持状态,输出***时钟。The clock processing module is configured to: when detecting that the clock output of the clock interface module is in a closed state, enter a clock hold state and output a system clock.
可选地,所述时钟接口模块包括:检测单元和时钟驱动单元,其中,Optionally, the clock interface module includes: a detecting unit and a clock driving unit, where
所述检测单元,设置为:接收并检测上游时钟设备发送的时钟链路信号,当判断所述时钟链路信号的状态异常时,发送开关控制信号至所述时钟驱动单元;The detecting unit is configured to: receive and detect a clock link signal sent by the upstream clock device, and when determining that the state of the clock link signal is abnormal, send a switch control signal to the clock driving unit;
所述时钟驱动单元,设置为:根据所述开关控制信号关闭所述时钟接口模块的时钟输出。The clock driving unit is configured to turn off a clock output of the clock interface module according to the switch control signal.
可选地,所述时钟接口模块包括检测单元、滤波单元和时钟驱动单元,其中:Optionally, the clock interface module includes a detecting unit, a filtering unit, and a clock driving unit, where:
所述检测单元,设置为:接收并检测上游时钟设备发送的时钟链路信号,当判断所述时钟链路信号的状态异常时,通知滤波单元;The detecting unit is configured to: receive and detect a clock link signal sent by the upstream clock device, and notify the filtering unit when determining that the state of the clock link signal is abnormal;
所述滤波单元,设置为:对经所述检测单元判断为异常的所述时钟链路信号进行噪声滤波处理,并对经噪声滤波处理后的所述时钟链路信号进行检测,当判断所述经噪声滤波处理后的时钟链路信号的状态异常时,发送开关控制信号至所述时钟驱动单元;The filtering unit is configured to perform noise filtering processing on the clock link signal that is determined to be abnormal by the detecting unit, and detect the clock link signal after the noise filtering process, when determining the When the state of the clock link signal after the noise filtering process is abnormal, sending a switch control signal to the clock driving unit;
所述时钟驱动单元,设置为:根据所述开关控制信号关闭所述时钟接口模块的时钟输出。The clock driving unit is configured to turn off a clock output of the clock interface module according to the switch control signal.
可选地,所述时钟处理模块是设置为:Optionally, the clock processing module is configured to:
当利用锁相环电路检测到在预设时间内所述时钟接口模块无时钟输出
时,进入时钟保持状态,输出***时钟。When the phase locked loop circuit detects that the clock interface module has no clock output within a preset time
When it enters the clock hold state, it outputs the system clock.
可选地,所述时钟链路信号为以太网信号或秒脉冲信号。Optionally, the clock link signal is an Ethernet signal or a second pulse signal.
一种时钟设备的时钟保持方法,所述时钟设备包括:时钟接口模块及时钟处理模块,所述方法包括:A clock holding method of a clock device, the clock device includes: a clock interface module and a clock processing module, and the method includes:
所述时钟接口模块监测接收的时钟链路信号,当判断所述时钟链路信号异常时,关闭所述时钟接口模块的时钟输出;The clock interface module monitors the received clock link signal, and when it is determined that the clock link signal is abnormal, the clock output of the clock interface module is turned off;
所述时钟处理模块当检测到所述时钟接口模块的时钟输出处于关闭状态时,进入时钟保持状态,输出***时钟。The clock processing module enters a clock hold state and outputs a system clock when detecting that the clock output of the clock interface module is in a closed state.
可选地,所述时钟接口模块监测接收的时钟链路信号,当判断所述时钟链路信号异常时,关闭所述时钟接口模块的时钟输出的步骤包括:Optionally, the clock interface module monitors the received clock link signal, and when determining that the clock link signal is abnormal, the step of turning off the clock output of the clock interface module includes:
所述时钟接口模块接收并检测上游时钟设备发送的时钟链路信号,当判断所述时钟链路信号的状态异常时,生成开关控制信号,并根据所述开关控制信号关闭所述时钟接口模块的时钟输出。The clock interface module receives and detects a clock link signal sent by the upstream clock device, and when it is determined that the state of the clock link signal is abnormal, generates a switch control signal, and closes the clock interface module according to the switch control signal. Clock output.
可选地,所述时钟接口模块监测接收的时钟链路信号,当判断所述时钟链路信号异常时,关闭所述时钟接口模块的时钟输出的步骤包括:Optionally, the clock interface module monitors the received clock link signal, and when determining that the clock link signal is abnormal, the step of turning off the clock output of the clock interface module includes:
所述时钟接口模块接收并检测上游时钟设备发送的时钟链路信号,对判断为异常的所述时钟链路信号进行噪声滤波处理,并对经噪声滤波处理后的所述时钟链路信号进行检测,当判断所述经噪声滤波处理后的时钟链路信号的状态异常时,生成开关控制信号,并根据所述开关控制信号关闭所述时钟接口模块的时钟输出。The clock interface module receives and detects a clock link signal sent by the upstream clock device, performs noise filtering processing on the clock link signal that is determined to be abnormal, and detects the clock link signal after the noise filtering process. And determining that a state of the clock link signal after the noise filtering process is abnormal, generating a switch control signal, and turning off a clock output of the clock interface module according to the switch control signal.
可选地,所述时钟处理模块当检测到所述时钟接口模块的时钟输出处于关闭状态时,进入时钟保持状态,输出***时钟的步骤包括:Optionally, the clock processing module enters a clock hold state when detecting that the clock output of the clock interface module is in an off state, and the step of outputting the system clock includes:
当利用锁相环电路检测到在预设时间内所述时钟接口模块无时钟输出时,进入时钟保持状态,输出***时钟。When the phase-locked loop circuit detects that the clock interface module has no clock output within a preset time, it enters a clock hold state and outputs a system clock.
可选地,所述时钟链路信号为以太网信号或秒脉冲信号。Optionally, the clock link signal is an Ethernet signal or a second pulse signal.
一种计算机可读存储介质,存储有计算机可执行指令,所述计算机可执
行指令用于执行上述任一项的方法。A computer readable storage medium storing computer executable instructions, the computer being executable
The line instructions are used to perform the method of any of the above.
本发明实施例提出的一种保持时钟的时钟设备及方法,通过时钟设备中的时钟接口模块检测到上游时钟设备发送的时钟链路信号出现异常时,关闭所述时钟接口模块的时钟输出;这样,时钟设备中的时钟处理模块在检测到所述时钟接口模块的时钟输出处于关闭状态时,即可获知时钟链路信号异常,则立刻进入时钟保持状态,输出***时钟,而无需时钟接口模块在检测到时钟链路信号异常时,向时钟处理模块发送DNU信息,时钟处理模块再对DNU信息进行解析之后才能进入到时钟保持状态,减少了DNU信息的转发及解析等繁琐操作,使得时钟设备中的时钟处理模块能迅速进入到时钟保持状态,最大限度的缩短了从时钟接口模块检测到时钟链路信号异常到时钟处理模块进入时钟保持状态的时间,从而大大减少了时钟处理模块输出***时钟的频率跳变,并控制在1ppb以内,以满足时钟设备应具备的保持性能。The clock device and method for maintaining a clock according to the embodiment of the present invention, when the clock interface module in the clock device detects that an abnormality occurs in the clock link signal sent by the upstream clock device, the clock output of the clock interface module is turned off; When the clock processing module in the clock device detects that the clock output of the clock interface module is in the off state, it can know that the clock link signal is abnormal, and immediately enters the clock hold state and outputs the system clock without the clock interface module being When the clock link signal is abnormal, the DNU information is sent to the clock processing module, and the clock processing module parses the DNU information to enter the clock hold state, thereby reducing the cumbersome operation of forwarding and parsing the DNU information, so that the clock device is in the clock device. The clock processing module can quickly enter the clock hold state, which minimizes the time from the clock interface module detecting the clock link signal abnormality to the clock processing module entering the clock hold state, thereby greatly reducing the clock processing module output system clock. Frequency jump and control Within 1ppb, clock device to satisfy the performance retention should have.
在阅读并理解了附图和详细描述后,可以明白其他方面。Other aspects will be apparent upon reading and understanding the drawings and detailed description.
附图概述BRIEF abstract
图1为本发明实施例保持时钟的时钟设备第一实施例的功能模块示意图;1 is a schematic diagram of functional modules of a first embodiment of a clock device for holding a clock according to an embodiment of the present invention;
图2为图1中时钟接口模块01的细化功能模块示意图;2 is a schematic diagram of a refinement function module of the clock interface module 01 of FIG. 1;
图3为本发明保持时钟的时钟设备第二实施例中时钟接口模块01的细化功能模块示意图;3 is a schematic diagram of a refinement function module of a clock interface module 01 in a second embodiment of a clock device for holding a clock according to the present invention;
图4为本发明时钟设备的时钟保持方法一实施例的流程示意图。4 is a schematic flow chart of an embodiment of a clock holding method of a clock device according to the present invention.
本发明实施例提供一种保持时钟的时钟设备。Embodiments of the present invention provide a clock device that holds a clock.
参照图1,图1为本发明保持时钟的时钟设备第一实施例的功能模块示意图。
Referring to FIG. 1, FIG. 1 is a schematic diagram of functional modules of a first embodiment of a clock device for holding a clock according to the present invention.
在第一实施例中,该时钟设备包括:时钟接口模块01及时钟处理模块02,其中,In the first embodiment, the clock device includes: a clock interface module 01 and a clock processing module 02, where
所述时钟接口模块01,设置为:监测接收的时钟链路信号,当判断所述时钟链路信号异常时,关闭所述时钟接口模块01的时钟输出;The clock interface module 01 is configured to: monitor the received clock link signal, and when it is determined that the clock link signal is abnormal, turn off the clock output of the clock interface module 01;
所述时钟处理模块02,设置为:当检测到所述时钟接口模块01的时钟输出处于关闭状态时,进入时钟保持状态,输出***时钟。The clock processing module 02 is configured to enter a clock hold state and output a system clock when detecting that the clock output of the clock interface module 01 is in a closed state.
本实施例通过时钟设备中的时钟接口模块01检测到上游时钟设备发送的时钟链路信号出现异常时,关闭所述时钟接口模块01的时钟输出;这样,时钟设备中的时钟处理模块02在检测到所述时钟接口模块01的时钟输出处于关闭状态时,即可获知时钟链路信号异常,则立刻进入时钟保持状态,输出***时钟,而无需时钟接口模块01在检测到时钟链路信号异常时,向时钟处理模块02发送DNU信息,时钟处理模块02再对DNU信息进行解析之后才能进入到时钟保持状态,减少了DNU信息的转发及解析等繁琐操作,使得时钟设备中的时钟处理模块02能迅速进入到时钟保持状态,最大限度的缩短了从时钟接口模块01检测到时钟链路信号异常到时钟处理模块02进入时钟保持状态的时间,从而大大减少了时钟处理模块02输出***时钟的频率跳变,并控制在1ppb以内,以满足时钟设备应具备的保持性能。In this embodiment, when the clock interface module 01 in the clock device detects that the clock link signal sent by the upstream clock device is abnormal, the clock output of the clock interface module 01 is turned off; thus, the clock processing module 02 in the clock device detects When the clock output of the clock interface module 01 is in the off state, the clock link signal is abnormal, and the clock hold state is immediately entered, and the system clock is output, without the clock interface module 01 detecting the abnormality of the clock link signal. The DNU information is sent to the clock processing module 02, and the clock processing module 02 can parse the DNU information to enter the clock hold state, thereby reducing the cumbersome operation of forwarding and parsing the DNU information, so that the clock processing module 02 in the clock device can Quickly enter the clock hold state, which minimizes the time from when the clock interface module 01 detects the clock link signal abnormality to when the clock processing module 02 enters the clock hold state, thereby greatly reducing the frequency hop of the clock processing module 02 outputting the system clock. Change and control within 1 ppb to meet the clock device It has maintained performance.
如图2所示,上述时钟接口模块01包括:检测单元03、时钟驱动单元04,其中,As shown in FIG. 2, the clock interface module 01 includes: a detecting unit 03 and a clock driving unit 04, where
所述检测单元03,设置为:接收并检测上游时钟设备发送的时钟链路信号,当判断所述时钟链路信号的状态异常时,发送开关控制信号至所述时钟驱动单元04;The detecting unit 03 is configured to: receive and detect a clock link signal sent by the upstream clock device, and when it is determined that the state of the clock link signal is abnormal, send a switch control signal to the clock driving unit 04;
所述时钟驱动单元04,设置为:根据所述开关控制信号关闭所述时钟接口模块01的时钟输出。The clock driving unit 04 is configured to turn off the clock output of the clock interface module 01 according to the switch control signal.
检测单元03实时监测上游时钟设备发送的时钟链路信号,并对接收的时钟链路信号的状态进行检测,当检测到时钟链路信号的状态异常时,说明
数据链路出现断开或时钟链路信号丢失等情况,则时钟接口模块01失去上游时钟设备输入的时钟源,无法恢复出时钟链路信号中的时钟,即自动锁定在本地晶振上,但此时时钟接口模块01并不会输出此时锁定的本地晶振即本振时钟,而是由检测单元03发送开关控制信号至所述时钟驱动单元04;时钟驱动单元04根据检测单元03发送的开关控制信号来控制所述时钟接口模块01的时钟输出,当检测单元03检测到时钟链路信号的状态异常时,向时钟驱动单元04发送开关控制信号,时钟驱动单元04即可根据该开关控制信号关闭所述时钟接口模块01的时钟输出,这样,所述时钟接口模块01的输出时钟即变为高阻状态。The detecting unit 03 monitors the clock link signal sent by the upstream clock device in real time, and detects the state of the received clock link signal. When the state of the clock link signal is abnormal, the description is
If the data link is disconnected or the clock link signal is lost, the clock interface module 01 loses the clock source input from the upstream clock device, and cannot recover the clock in the clock link signal, that is, it automatically locks on the local crystal oscillator, but this The clock interface module 01 does not output the local crystal oscillator locked at this time, that is, the local oscillator clock, but the detection unit 03 sends a switch control signal to the clock drive unit 04; the clock drive unit 04 controls the switch according to the detection unit 03. The signal is used to control the clock output of the clock interface module 01. When the detecting unit 03 detects that the state of the clock link signal is abnormal, the switch control signal is sent to the clock driving unit 04, and the clock driving unit 04 can be turned off according to the switch control signal. The clock output of the clock interface module 01 is such that the output clock of the clock interface module 01 becomes a high impedance state.
上述时钟处理模块02是设置为:The above clock processing module 02 is set to:
当利用锁相环电路检测到在预设时间内所述时钟接口模块01无时钟输出时,进入时钟保持状态,输出***时钟。When the phase-locked loop circuit detects that the clock interface module 01 has no clock output within a preset time, it enters a clock hold state and outputs a system clock.
当所述时钟接口模块01的时钟输出处于关闭状态,也即所述时钟接口模块01的输出时钟变为高阻状态时,时钟处理模块02可采用锁相环电路来进行检测。由于时钟处理模块02采用的是锁相环电路来锁定正常的时钟链路信号恢复的时钟或进入时钟保持状态,而锁相环电路进入时钟保持状态时除了可以通过下发配置命令的方式外,还可在当锁相环电路检测到时钟源丢失时,自动进入到时钟保持状态,这是绝大多数锁相环芯片都具备的一种基本功能,而在同步数字体系的时钟设备中采用的锁相环电路是必须具备这一功能的。因此,本实施例中时钟设备的时钟处理模块02可采用锁相环电路来对时钟接口模块01的时钟输出状态进行检测,当时钟处理模块02中的锁相环电路检测到在预设时间内所述时钟接口模块01无时钟输出时,即可获知时钟链路信号出现异常,时钟源丢失,则时钟处理模块02立刻进入时钟保持状态,输出***时钟。需要说明的是,当利用锁相环电路在预设时间内检测所述时钟接口模块01的时钟输出状态之前,可对该预设时间进行设置,可根据需要将该预设时间设置得较低如1至2个周期,这样,利用锁相环电路在1至2个周期内检测到所述时钟接口模块01无时钟输出时,时钟处理模块02即可立即进入时钟保持状态,减少了检测花费的时间,能使时钟
处理模块02更快的进入时钟保持状态,从而减小输出***时钟的频率跳变。When the clock output of the clock interface module 01 is in the off state, that is, the output clock of the clock interface module 01 becomes a high impedance state, the clock processing module 02 can perform detection by using a phase locked loop circuit. The clock processing module 02 uses a phase-locked loop circuit to lock the clock of the normal clock link signal recovery or enters the clock hold state, and the phase-locked loop circuit enters the clock hold state, except that the configuration command can be issued. It can also automatically enter the clock hold state when the phase-locked loop circuit detects the loss of the clock source. This is a basic function that most phase-locked loop chips have, and is used in the clock device of the synchronous digital system. Phase-locked loop circuits must have this capability. Therefore, the clock processing module 02 of the clock device in this embodiment can use the phase-locked loop circuit to detect the clock output state of the clock interface module 01, and the phase-locked loop circuit in the clock processing module 02 detects the preset time. When the clock interface module 01 has no clock output, it can be known that the clock link signal is abnormal, and the clock source is lost, the clock processing module 02 immediately enters the clock hold state and outputs the system clock. It should be noted that, before using the phase-locked loop circuit to detect the clock output state of the clock interface module 01 within a preset time, the preset time may be set, and the preset time may be set lower according to requirements. For example, 1 to 2 cycles, in this way, when the clock interface module 01 is detected to have no clock output in 1 to 2 cycles by using the phase-locked loop circuit, the clock processing module 02 can immediately enter the clock hold state, thereby reducing the detection cost. Time to make the clock
Processing module 02 enters the clock hold state more quickly, thereby reducing the frequency hopping of the output system clock.
本实施例中时钟处理模块02利用锁相环电路这一硬件手段来检测在预设时间内所述时钟接口模块01的时钟输出状态,并在检测到所述时钟接口模块01无时钟输出时,自动进入时钟保持状态,输出***时钟,尽可能的缩短了时钟处理模块02进入时钟保持状态的时间,而无需时钟接口模块01在检测到时钟链路信号异常时,向时钟处理模块02发送DNU信息,时钟处理模块02再对DNU信息进行解析之后才能进入到时钟保持状态,减少了DNU信息的转发及解析等繁琐操作,使得时钟设备中的时钟处理模块02能迅速进入到时钟保持状态,最大限度的缩短了从时钟接口模块01检测到时钟链路信号异常到时钟处理模块02进入时钟保持状态的时间,从而大大减少了时钟处理模块02输出***时钟的频率跳变,并控制在1ppb以内,以满足时钟设备应具备的保持性能。In the embodiment, the clock processing module 02 uses the hardware of the phase-locked loop circuit to detect the clock output state of the clock interface module 01 within a preset time, and when detecting that the clock interface module 01 has no clock output, Automatically enters the clock hold state, outputs the system clock, and shortens the time when the clock processing module 02 enters the clock hold state as much as possible, without the clock interface module 01 sending the DNU information to the clock processing module 02 when detecting that the clock link signal is abnormal. After the clock processing module 02 parses the DNU information, it can enter the clock hold state, which reduces the cumbersome operation of forwarding and parsing the DNU information, so that the clock processing module 02 in the clock device can quickly enter the clock hold state, maximizing The time from when the clock interface module 01 detects the abnormality of the clock link signal to the time when the clock processing module 02 enters the clock hold state is shortened, thereby greatly reducing the frequency jump of the output system clock of the clock processing module 02, and controlling it within 1 ppb, Meet the retention performance that clock devices should have.
如图3所示,本发明第二实施例提出一种保持时钟的时钟设备,在上述第一实施例的基础上,所述时钟接口模块01包括检测单元03、滤波单元05和时钟驱动单元04,其中:As shown in FIG. 3, a second embodiment of the present invention provides a clock device for holding a clock. Based on the foregoing first embodiment, the clock interface module 01 includes a detecting unit 03, a filtering unit 05, and a clock driving unit 04. ,among them:
所述检测单元03,设置为:接收并检测上游时钟设备发送的时钟链路信号,当判断所述时钟链路信号的状态异常时,通知滤波单元05;The detecting unit 03 is configured to: receive and detect a clock link signal sent by the upstream clock device, and when it is determined that the state of the clock link signal is abnormal, notify the filtering unit 05;
滤波单元05,设置为:对经所述检测单元03判断为异常的所述时钟链路信号进行噪声滤波处理,并对经噪声滤波处理后的所述时钟链路信号进行检测,当判断所述经噪声滤波处理后的时钟链路信号的状态异常时,发送开关控制信号至所述时钟驱动单元04;The filtering unit 05 is configured to: perform noise filtering processing on the clock link signal that is determined to be abnormal by the detecting unit 03, and detect the clock link signal after the noise filtering process, when determining the When the state of the clock link signal after the noise filtering process is abnormal, send a switch control signal to the clock drive unit 04;
所述时钟驱动单元04,设置为:根据所述开关控制信号关闭所述时钟接口模块01的时钟输出。The clock driving unit 04 is configured to turn off the clock output of the clock interface module 01 according to the switch control signal.
本实施例中,在检测单元03检测到时钟链路信号的状态异常时,先通过滤波单元05对经所述检测单元03判断为异常的所述时钟链路信号进行噪声滤波处理,并继续对经噪声滤波处理后的所述时钟链路信号进行检测,若
仍然检测所述时钟链路信号的状态异常,才发送开关控制信号至所述时钟驱动单元04,以使时钟驱动单元04根据所述开关控制信号关闭所述时钟接口模块01的时钟输出。这样,本实施例中只有在经检测单元03及滤波单元05都检测到所述时钟链路信号的状态异常时,才会发送开关控制信号至所述时钟驱动单元04,有效地避免了因上游时钟设备的时钟传输链路可能存在的短时不稳定或环境干扰造成检测单元03误判的情况,能更加准确的对上游时钟设备发送的时钟链路信号状态进行判断,进而在确认时钟链路信号为信号丢失等异常状态时,才使时钟驱动单元04关闭所述时钟接口模块01的时钟输出,减小了因误判造成时钟处理模块02进入时钟保持状态的可能性,增强了时钟设备的稳定性。In this embodiment, when the detecting unit 03 detects that the state of the clock link signal is abnormal, the filtering unit 05 first performs noise filtering processing on the clock link signal that is determined to be abnormal by the detecting unit 03, and continues to perform the noise filtering process. The clock link signal processed by the noise filtering is detected, if
Still detecting the abnormal state of the clock link signal, the switch control signal is sent to the clock drive unit 04, so that the clock drive unit 04 turns off the clock output of the clock interface module 01 according to the switch control signal. Thus, in this embodiment, only when the detection unit 03 and the filtering unit 05 detect that the state of the clock link signal is abnormal, the switch control signal is sent to the clock driving unit 04, effectively avoiding the upstream The short-term instability or environmental interference of the clock transmission link of the clock device may cause the detection unit 03 to misjudge the situation, and the state of the clock link signal sent by the upstream clock device may be more accurately determined, thereby confirming the clock link. When the signal is an abnormal state such as a signal loss, the clock driving unit 04 turns off the clock output of the clock interface module 01, which reduces the possibility that the clock processing module 02 enters the clock holding state due to misjudgment, and enhances the clock device. stability.
上游时钟设备发送的时钟链路信号可以是以太网信号或秒脉冲(1PPS)信号。The clock link signal sent by the upstream clock device may be an Ethernet signal or a second pulse (1PPS) signal.
基于以太网的时钟传递普遍采用的接口类型为以太网光口和以太网电口,当时钟接口模块01接收到上游时钟设备通过光纤传递的同步以太网信号时,由于光模块本身可以产生信号丢失LOS指示信号,且在光模块内部会进行噪声滤波处理,即光模块本身会对信号丢失进行噪声滤波、丢失检测等处理,因此,在实际应用中若时钟接口模块01的检测单元03获取同步以太网信号中的LOS指示信号时,则可直接获知时钟链路信号的状态异常,且无需进一步的进行噪声滤波处理,并根据同步以太网信号中的LOS指示信号发送开关控制信号至所述时钟驱动单元04,以使时钟驱动单元04根据所述开关控制信号关闭所述时钟接口模块01的时钟输出。The interface type of the Ethernet-based clock transmission is Ethernet optical port and Ethernet electrical port. When the clock interface module 01 receives the synchronous Ethernet signal transmitted by the upstream clock device through the optical fiber, the optical module itself can generate signal loss. The LOS indicator signal, and the noise filtering process is performed inside the optical module, that is, the optical module itself performs noise filtering, loss detection, and the like on the signal loss. Therefore, in the actual application, if the detecting unit 03 of the clock interface module 01 acquires the synchronization ether When the LOS indication signal in the network signal is directly informed that the state of the clock link signal is abnormal, and no further noise filtering processing is required, and the switch control signal is sent to the clock drive according to the LOS indication signal in the synchronous Ethernet signal. The unit 04 is configured to cause the clock driving unit 04 to turn off the clock output of the clock interface module 01 according to the switch control signal.
当时钟接口模块01接收到上游时钟设备通过网线传递的同步以太网信号时,由于同步以太网物理层芯片会产生信号丢失中断,并且该中断的产生也会在同步以太网物理层芯片内部经过噪声滤波处理,因此,在实际应用中若时钟接口模块01的检测单元03获取同步以太网信号中的信号丢失中断时,则可直接获知时钟链路信号的状态异常,且无需进一步的进行噪声滤波处理,并根据同步以太网信号中的信号丢失中断发送开关控制信号至所述时钟驱动单元04,以使时钟驱动单元04根据所述开关控制信号关闭所述时钟
接口模块01的时钟输出。When the clock interface module 01 receives the synchronous Ethernet signal transmitted by the upstream clock device through the network cable, the synchronous Ethernet physical layer chip will generate a signal loss interrupt, and the interrupt will also generate noise inside the synchronous Ethernet physical layer chip. Filtering processing, therefore, in the actual application, if the detecting unit 03 of the clock interface module 01 acquires the signal loss interrupt in the synchronous Ethernet signal, the state of the clock link signal is directly known to be abnormal, and no further noise filtering processing is required. And transmitting a switch control signal to the clock driving unit 04 according to a signal loss in the synchronous Ethernet signal, so that the clock driving unit 04 turns off the clock according to the switch control signal
Clock output of interface module 01.
当时钟接口模块01接收到上游时钟设备通过1PPS接口传递的秒脉冲(1PPS)信号时,时钟接口模块01的检测单元03对接收的1PPS信号的状态进行实时检测,当检测到1PPS信号的状态异常时,将该1PPS信号发送至滤波单元05,由滤波单元05对该1PPS信号进行噪声滤波处理,并继续对经噪声滤波处理后的1PPS信号进行检测,若仍然检测1PPS信号的状态异常,才发送开关控制信号至所述时钟驱动单元04,以使时钟驱动单元04根据所述开关控制信号关闭所述时钟接口模块01的时钟输出。进而,当时钟处理模块02中的锁相环电路检测到在预设时间内所述时钟接口模块01无时钟输出时,能立刻进入时钟保持状态,输出***时钟。When the clock interface module 01 receives the second pulse (1PPS) signal transmitted by the upstream clock device through the 1PPS interface, the detecting unit 03 of the clock interface module 01 detects the state of the received 1PPS signal in real time, and detects that the state of the 1PPS signal is abnormal. The 1PPS signal is sent to the filtering unit 05, and the filtering unit 05 performs noise filtering processing on the 1PPS signal, and continues to detect the 1PPS signal after the noise filtering process. If the state of the 1PPS signal is still abnormal, the signal is sent. The control signal is switched to the clock driving unit 04 to cause the clock driving unit 04 to turn off the clock output of the clock interface module 01 according to the switching control signal. Further, when the phase locked loop circuit in the clock processing module 02 detects that the clock interface module 01 has no clock output within a preset time, it can immediately enter the clock hold state and output the system clock.
本发明实施例提供一种时钟设备的时钟保持方法。所述时钟设备包括:时钟接口模块及时钟处理模块。Embodiments of the present invention provide a clock holding method of a clock device. The clock device includes: a clock interface module and a clock processing module.
参照图4,图4为本发明时钟设备的时钟保持方法一实施例的流程示意图。Referring to FIG. 4, FIG. 4 is a schematic flowchart diagram of an embodiment of a clock holding method of a clock device according to the present invention.
在一实施例中,该时钟设备的时钟保持方法包括:In an embodiment, the clock keeping method of the clock device includes:
步骤S10,所述时钟接口模块监测接收的时钟链路信号,当判断所述时钟链路信号异常时,关闭所述时钟接口模块的时钟输出;Step S10, the clock interface module monitors the received clock link signal, and when it is determined that the clock link signal is abnormal, the clock output of the clock interface module is turned off;
步骤S20,所述时钟处理模块当检测到所述时钟接口模块的时钟输出处于关闭状态时,进入时钟保持状态,输出***时钟。Step S20, the clock processing module enters a clock hold state and outputs a system clock when detecting that the clock output of the clock interface module is in a closed state.
本实施例通过时钟设备中的时钟接口模块检测到上游时钟设备发送的时钟链路信号出现异常时,关闭所述时钟接口模块的时钟输出;这样,时钟设备中的时钟处理模块在检测到所述时钟接口模块的时钟输出处于关闭状态时,即可获知时钟链路信号异常,则立刻进入时钟保持状态,输出***时钟,而无需时钟接口模块在检测到时钟链路信号异常时,向时钟处理模块发送DNU信息,时钟处理模块再对DNU信息进行解析之后才能进入到时钟保持状态,减少了DNU信息的转发及解析等繁琐操作,使得时钟设备中的时钟处理模块能迅速进入到时钟保持状态,最大限度的缩短了从时钟接口模块
检测到时钟链路信号异常到时钟处理模块进入时钟保持状态的时间,从而大大减少了时钟处理模块输出***时钟的频率跳变,并控制在1ppb以内,以满足时钟设备应具备的保持性能。In this embodiment, when the clock interface module in the clock device detects that the clock link signal sent by the upstream clock device is abnormal, the clock output of the clock interface module is turned off; thus, the clock processing module in the clock device detects the When the clock output of the clock interface module is off, you can know that the clock link signal is abnormal, and immediately enter the clock hold state and output the system clock. When the clock interface module detects that the clock link signal is abnormal, the clock processing module is sent to the clock processing module. After the DNU information is sent, the clock processing module parses the DNU information to enter the clock hold state, which reduces the cumbersome operation of forwarding and parsing the DNU information, so that the clock processing module in the clock device can quickly enter the clock hold state, and the maximum Limiting the slave clock interface module
The time when the clock link signal is abnormal until the clock processing module enters the clock hold state is detected, thereby greatly reducing the frequency jump of the clock processing module output system clock, and controlling it within 1 ppb to meet the retention performance that the clock device should have.
在其他实施例中,上述步骤S10可以包括:所述时钟接口模块接收并检测上游时钟设备发送的时钟链路信号,当判断所述时钟链路信号的状态异常时,生成开关控制信号,并根据所述开关控制信号关闭所述时钟接口模块的时钟输出。In other embodiments, the step S10 may include: the clock interface module receives and detects a clock link signal sent by the upstream clock device, and when determining that the state of the clock link signal is abnormal, generates a switch control signal, and according to The switch control signal turns off the clock output of the clock interface module.
所述时钟接口模块实时监测上游时钟设备发送的时钟链路信号,并对接收的时钟链路信号的状态进行检测,当检测到时钟链路信号的状态异常时,说明数据链路出现断开或时钟链路信号丢失等情况,则时钟接口模块失去上游时钟设备输入的时钟源,无法恢复出时钟链路信号中的时钟,即自动锁定在本地晶振上,但此时时钟接口模块并不会输出此时锁定的本地晶振即本振时钟,而是生成开关控制信号,并根据生成的开关控制信号来控制所述时钟接口模块的时钟输出,当检测到时钟链路信号的状态异常时,即可根据生成的开关控制信号关闭所述时钟接口模块的时钟输出,这样,所述时钟接口模块的输出时钟即变为高阻状态。The clock interface module monitors the clock link signal sent by the upstream clock device in real time, and detects the state of the received clock link signal. When the state of the clock link signal is abnormal, the data link is disconnected or If the clock link signal is lost, the clock interface module loses the clock source input from the upstream clock device and cannot recover the clock in the clock link signal, that is, it is automatically locked on the local crystal oscillator. However, the clock interface module does not output. The local crystal oscillator locked at this time is the local oscillator clock, but generates a switch control signal, and controls the clock output of the clock interface module according to the generated switch control signal. When the state of the clock link signal is abnormal, The clock output of the clock interface module is turned off according to the generated switch control signal, so that the output clock of the clock interface module becomes a high impedance state.
在其他实施例中,上述步骤S20可以包括:In other embodiments, the foregoing step S20 may include:
当利用锁相环电路检测到在预设时间内所述时钟接口模块无时钟输出时,进入时钟保持状态,输出***时钟。When the phase-locked loop circuit detects that the clock interface module has no clock output within a preset time, it enters a clock hold state and outputs a system clock.
当所述时钟接口模块的时钟输出处于关闭状态,也即所述时钟接口模块的输出时钟变为高阻状态时,时钟处理模块可采用锁相环电路来进行检测。由于时钟处理模块采用的是锁相环电路来锁定正常的时钟链路信号恢复的时钟或进入时钟保持状态,而锁相环电路进入时钟保持状态时除了可以通过下发配置命令的方式外,还可在当锁相环电路检测到时钟源丢失时,自动进入到时钟保持状态,这是绝大多数锁相环芯片都具备的一种基本功能,而在同步数字体系的时钟设备中采用的锁相环电路是必须具备这一功能的。因此,
本实施例中时钟设备的时钟处理模块可采用锁相环电路来对时钟接口模块的时钟输出状态进行检测,当时钟处理模块中的锁相环电路检测到在预设时间内所述时钟接口模块无时钟输出时,即可获知时钟链路信号出现异常,时钟源丢失,则时钟处理模块立刻进入时钟保持状态,输出***时钟。需要说明的是,当利用锁相环电路在预设时间内检测所述时钟接口模块的时钟输出状态之前,可对该预设时间进行设置,可根据需要将该预设时间设置得较低如1至2个周期,这样,利用锁相环电路在1至2个周期内检测到所述时钟接口模块无时钟输出时,时钟处理模块即可立即进入时钟保持状态,减少了检测花费的时间,能使时钟处理模块更快的进入时钟保持状态,从而减小输出***时钟的频率跳变。When the clock output of the clock interface module is in the off state, that is, the output clock of the clock interface module becomes a high impedance state, the clock processing module may use a phase locked loop circuit for detecting. Because the clock processing module uses a phase-locked loop circuit to lock the clock of the normal clock link signal recovery or enters the clock hold state, and the phase-locked loop circuit enters the clock hold state, in addition to the way of issuing the configuration command, When the phase-locked loop circuit detects that the clock source is lost, it automatically enters the clock hold state, which is a basic function of most phase-locked loop chips, and the lock used in the clock device of the synchronous digital system. Phase loop circuits must have this capability. Therefore,
The clock processing module of the clock device in this embodiment may use a phase locked loop circuit to detect a clock output state of the clock interface module, and the phase locked loop circuit in the clock processing module detects the clock interface module within a preset time. When there is no clock output, the clock link signal is abnormal. If the clock source is lost, the clock processing module immediately enters the clock hold state and outputs the system clock. It should be noted that, before using the phase-locked loop circuit to detect the clock output state of the clock interface module within a preset time, the preset time may be set, and the preset time may be set to be lower as needed. 1 to 2 cycles, so that when the clock interface module detects no clock output in 1 to 2 cycles by using the phase-locked loop circuit, the clock processing module can immediately enter the clock hold state, reducing the time taken for the detection, This enables the clock processing module to enter the clock hold state more quickly, thereby reducing the frequency hopping of the output system clock.
本实施例中时钟处理模块利用锁相环电路这一硬件手段来检测在预设时间内所述时钟接口模块的时钟输出状态,并在检测到所述时钟接口模块无时钟输出时,自动进入时钟保持状态,输出***时钟,尽可能的缩短了时钟处理模块进入时钟保持状态的时间,而无需时钟接口模块在检测到时钟链路信号异常时,向时钟处理模块发送DNU信息,时钟处理模块再对DNU信息进行解析之后才能进入到时钟保持状态,减少了DNU信息的转发及解析等繁琐操作,使得时钟设备中的时钟处理模块能迅速进入到时钟保持状态,最大限度的缩短了从时钟接口模块检测到时钟链路信号异常到时钟处理模块进入时钟保持状态的时间,从而大大减少了时钟处理模块输出***时钟的频率跳变,并控制在1ppb以内,以满足时钟设备应具备的保持性能。In this embodiment, the clock processing module uses the hardware means of the phase-locked loop circuit to detect the clock output state of the clock interface module within a preset time, and automatically enters the clock when detecting that the clock interface module has no clock output. Maintaining the state, outputting the system clock, shortening the time that the clock processing module enters the clock hold state as much as possible, without the clock interface module sending DNU information to the clock processing module when the clock link signal is abnormal, and the clock processing module is again After the DNU information is parsed, it can enter the clock hold state, which reduces the cumbersome operation of DNU information forwarding and parsing, so that the clock processing module in the clock device can quickly enter the clock hold state, and the slave clock interface module detection is minimized. The time until the clock link signal is abnormal until the clock processing module enters the clock hold state, thereby greatly reducing the frequency jump of the clock processing module output system clock, and controlling it within 1 ppb to meet the retention performance that the clock device should have.
本发明第二实施例提出一种时钟设备的时钟保持方法,在上述第一实施例的基础上,上述步骤S10包括:The second embodiment of the present invention provides a clock holding method for a clock device. Based on the foregoing first embodiment, the foregoing step S10 includes:
所述时钟接口模块接收并检测上游时钟设备发送的时钟链路信号,对判断为异常的所述时钟链路信号进行噪声滤波处理,并对经噪声滤波处理后的所述时钟链路信号进行检测,当判断所述经噪声滤波处理后的时钟链路信号的状态异常时,生成开关控制信号,并根据所述开关控制信号关闭所述时钟接口模块的时钟输出。The clock interface module receives and detects a clock link signal sent by the upstream clock device, performs noise filtering processing on the clock link signal that is determined to be abnormal, and detects the clock link signal after the noise filtering process. And determining that a state of the clock link signal after the noise filtering process is abnormal, generating a switch control signal, and turning off a clock output of the clock interface module according to the switch control signal.
本实施例中,在所述时钟接口模块检测到时钟链路信号的状态异常时,
先对判断为异常的所述时钟链路信号进行噪声滤波处理,并继续对经噪声滤波处理后的所述时钟链路信号进行检测,若仍然检测所述时钟链路信号的状态异常,才生成开关控制信号,以根据所述开关控制信号关闭所述时钟接口模块的时钟输出。这样,本实施例中只有在经双重检测所述时钟链路信号的状态异常时,才会生成开关控制信号,有效地避免了因上游时钟设备的时钟传输链路可能存在的短时不稳定或环境干扰造成检测误判的情况,能更加准确的对上游时钟设备发送的时钟链路信号状态进行判断,进而在确认时钟链路信号为信号丢失等异常状态时,才关闭所述时钟接口模块的时钟输出,减小了因误判造成时钟处理模块进入时钟保持状态的可能性,增强了时钟设备的稳定性。In this embodiment, when the clock interface module detects that the state of the clock link signal is abnormal,
Performing noise filtering processing on the clock link signal that is determined to be abnormal, and continuing to detect the clock link signal after the noise filtering process, and if the state of the clock link signal is still abnormal, And switching a control signal to turn off a clock output of the clock interface module according to the switch control signal. In this way, in this embodiment, the switch control signal is generated only when the state of the clock link signal is abnormally detected, which effectively avoids the short-term instability that may exist due to the clock transmission link of the upstream clock device. When the environmental interference causes the misjudgment of the detection, the state of the clock link signal sent by the upstream clock device can be more accurately judged, and then the clock interface signal is turned off when the clock link signal is in an abnormal state such as a signal loss. The clock output reduces the possibility of the clock processing module entering the clock hold state due to misjudgment, and enhances the stability of the clock device.
上游时钟设备发送的时钟链路信号可以是以太网信号或秒脉冲(1PPS)信号。The clock link signal sent by the upstream clock device may be an Ethernet signal or a second pulse (1PPS) signal.
基于以太网的时钟传递普遍采用的接口类型为以太网光口和以太网电口,当时钟接口模块接收到上游时钟设备通过光纤传递的同步以太网信号时,由于光模块本身可以产生信号丢失LOS指示信号,且在光模块内部会进行噪声滤波处理,即光模块本身会对信号丢失进行噪声滤波、丢失检测等处理,因此,在实际应用中若时钟接口模块获取到同步以太网信号中的LOS指示信号,则可直接获知时钟链路信号的状态异常,且无需进一步的进行噪声滤波处理,并根据同步以太网信号中的LOS指示信号生成开关控制信号,以根据所述开关控制信号关闭所述时钟接口模块的时钟输出。Ethernet interface-based clock transmission commonly used as Ethernet optical port and Ethernet electrical port. When the clock interface module receives the synchronous Ethernet signal transmitted by the upstream clock device through the optical fiber, the optical module itself can generate signal loss LOS. The signal is indicated, and noise filtering is performed inside the optical module, that is, the optical module itself performs noise filtering and loss detection on the signal loss. Therefore, in practical applications, if the clock interface module acquires the LOS in the synchronous Ethernet signal. The indication signal can directly know that the state of the clock link signal is abnormal, and no further noise filtering processing is needed, and a switch control signal is generated according to the LOS indication signal in the synchronous Ethernet signal to turn off the switch according to the switch control signal. Clock output of the clock interface module.
当时钟接口模块接收到上游时钟设备通过网线传递的同步以太网信号时,由于同步以太网物理层芯片会产生信号丢失中断,并且该中断的产生也会在同步以太网物理层芯片内部经过噪声滤波处理,因此,在实际应用中若时钟接口模块获取到同步以太网信号中的信号丢失中断,则可直接获知时钟链路信号的状态异常,且无需进一步的进行噪声滤波处理,并根据同步以太网信号中的信号丢失中断生成开关控制信号,以根据所述开关控制信号关闭所述时钟接口模块的时钟输出。When the clock interface module receives the synchronous Ethernet signal transmitted by the upstream clock device through the network cable, the synchronous Ethernet physical layer chip generates a signal loss interrupt, and the interrupt is generated by noise filtering inside the synchronous Ethernet physical layer chip. Processing, therefore, in the actual application, if the clock interface module acquires the signal loss interrupt in the synchronous Ethernet signal, it can directly know that the state of the clock link signal is abnormal, and no further noise filtering processing is required, and according to the synchronous Ethernet A signal loss interrupt in the signal generates a switch control signal to turn off the clock output of the clock interface module in accordance with the switch control signal.
当时钟接口模块接收到上游时钟设备通过1PPS接口传递的秒脉冲
(1PPS)信号时,时钟接口模块对接收的1PPS信号的状态进行实时检测,当检测到1PPS信号的状态异常时,对该1PPS信号进行噪声滤波处理,并继续对经噪声滤波处理后的1PPS信号进行检测,若仍然检测1PPS信号的状态异常,才生成开关控制信号,以根据所述开关控制信号关闭所述时钟接口模块的时钟输出。进而,当时钟处理模块中的锁相环电路检测到在预设时间内所述时钟接口模块无时钟输出时,能立刻进入时钟保持状态,输出***时钟。When the clock interface module receives the second pulse transmitted by the upstream clock device through the 1PPS interface
When the (1PPS) signal is used, the clock interface module detects the state of the received 1PPS signal in real time. When the state of the 1PPS signal is abnormal, the noise filtering process is performed on the 1PPS signal, and the 1PPS signal after the noise filtering process is continued. The detection is performed, and if the state of the 1PPS signal is still abnormal, the switch control signal is generated to turn off the clock output of the clock interface module according to the switch control signal. Furthermore, when the phase locked loop circuit in the clock processing module detects that the clock interface module has no clock output within a preset time, it can immediately enter the clock hold state and output the system clock.
本领域普通技术人员可以理解上述实施例的全部或部分步骤可以使用计算机程序流程来实现,所述计算机程序可以存储于一计算机可读存储介质中,所述计算机程序在相应的硬件平台上(如***、设备、装置、器件等)执行,在执行时,包括方法实施例的步骤之一或其组合。One of ordinary skill in the art will appreciate that all or a portion of the steps of the above-described embodiments can be implemented using a computer program flow, which can be stored in a computer readable storage medium, such as on a corresponding hardware platform (eg, The system, device, device, device, etc. are executed, and when executed, include one or a combination of the steps of the method embodiments.
可选地,上述实施例的全部或部分步骤也可以使用集成电路来实现,这些步骤可以被分别制作成一个个集成电路模块,或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。Alternatively, all or part of the steps of the above embodiments may also be implemented by using an integrated circuit. These steps may be separately fabricated into individual integrated circuit modules, or multiple modules or steps may be fabricated into a single integrated circuit module. achieve.
上述实施例中的装置/功能模块/功能单元可以采用通用的计算装置来实现,它们可以集中在单个的计算装置上,也可以分布在多个计算装置所组成的网络上。The devices/function modules/functional units in the above embodiments may be implemented by a general-purpose computing device, which may be centralized on a single computing device or distributed over a network of multiple computing devices.
上述实施例中的装置/功能模块/功能单元以软件功能模块的形式实现并作为独立的产品销售或使用时,可以存储在一个计算机可读取存储介质中。上述提到的计算机可读取存储介质可以是只读存储器,磁盘或光盘等。When the device/function module/functional unit in the above embodiment is implemented in the form of a software function module and sold or used as a stand-alone product, it can be stored in a computer readable storage medium. The above mentioned computer readable storage medium may be a read only memory, a magnetic disk or an optical disk or the like.
本发明实施例提出的一种保持时钟的时钟设备及方法,通过时钟设备中的时钟接口模块检测到上游时钟设备发送的时钟链路信号出现异常时,关闭所述时钟接口模块的时钟输出;这样,时钟设备中的时钟处理模块在检测到所述时钟接口模块的时钟输出处于关闭状态时,即可获知时钟链路信号异
常,则立刻进入时钟保持状态,输出***时钟,而无需时钟接口模块在检测到时钟链路信号异常时,向时钟处理模块发送DNU信息,时钟处理模块再对DNU信息进行解析之后才能进入到时钟保持状态,减少了DNU信息的转发及解析等繁琐操作,使得时钟设备中的时钟处理模块能迅速进入到时钟保持状态,最大限度的缩短了从时钟接口模块检测到时钟链路信号异常到时钟处理模块进入时钟保持状态的时间,从而大大减少了时钟处理模块输出***时钟的频率跳变,并控制在1ppb以内,以满足时钟设备应具备的保持性能。
The clock device and method for maintaining a clock according to the embodiment of the present invention, when the clock interface module in the clock device detects that an abnormality occurs in the clock link signal sent by the upstream clock device, the clock output of the clock interface module is turned off; The clock processing module in the clock device can know the clock link signal when detecting that the clock output of the clock interface module is in the off state.
Normally, the clock state is immediately entered and the system clock is output, and the clock interface module does not need to send DNU information to the clock processing module when the clock link signal is abnormal. The clock processing module parses the DNU information before entering the clock. Maintaining the state reduces the cumbersome operation of DNU information forwarding and parsing, so that the clock processing module in the clock device can quickly enter the clock hold state, which minimizes the detection of the clock link signal abnormality from the clock interface module to the clock processing. The time that the module enters the clock hold state greatly reduces the frequency jump of the clock processing module output system clock and controls it within 1 ppb to meet the retention performance of the clock device.
Claims (11)
- 一种保持时钟的时钟设备,所述时钟设备包括:时钟接口模块及时钟处理模块,其中,A clock device for holding a clock, the clock device includes: a clock interface module and a clock processing module, wherein所述时钟接口模块,设置为:监测接收的时钟链路信号,当判断所述时钟链路信号异常时,关闭所述时钟接口模块的时钟输出;The clock interface module is configured to: monitor a received clock link signal, and when it is determined that the clock link signal is abnormal, turn off a clock output of the clock interface module;所述时钟处理模块,设置为:当检测到所述时钟接口模块的时钟输出处于关闭状态时,进入时钟保持状态,输出***时钟。The clock processing module is configured to: when detecting that the clock output of the clock interface module is in a closed state, enter a clock hold state and output a system clock.
- 如权利要求1所述的时钟设备,其中,所述时钟接口模块包括:检测单元和时钟驱动单元,其中,The clock device according to claim 1, wherein the clock interface module comprises: a detecting unit and a clock driving unit, wherein所述检测单元,设置为:接收并检测上游时钟设备发送的时钟链路信号,当判断所述时钟链路信号的状态异常时,发送开关控制信号至所述时钟驱动单元;The detecting unit is configured to: receive and detect a clock link signal sent by the upstream clock device, and when determining that the state of the clock link signal is abnormal, send a switch control signal to the clock driving unit;所述时钟驱动单元,设置为:根据所述开关控制信号关闭所述时钟接口模块的时钟输出。The clock driving unit is configured to turn off a clock output of the clock interface module according to the switch control signal.
- 如权利要求1所述的时钟设备,其中,所述时钟接口模块包括检测单元、滤波单元和时钟驱动单元,其中:The clock device according to claim 1, wherein said clock interface module comprises a detecting unit, a filtering unit, and a clock driving unit, wherein:所述检测单元,设置为:接收并检测上游时钟设备发送的时钟链路信号,当判断所述时钟链路信号的状态异常时,通知滤波单元;The detecting unit is configured to: receive and detect a clock link signal sent by the upstream clock device, and notify the filtering unit when determining that the state of the clock link signal is abnormal;所述滤波单元,设置为:对经所述检测单元判断为异常的所述时钟链路信号进行噪声滤波处理,并对经噪声滤波处理后的所述时钟链路信号进行检测,当判断所述经噪声滤波处理后的时钟链路信号的状态异常时,发送开关控制信号至所述时钟驱动单元;The filtering unit is configured to perform noise filtering processing on the clock link signal that is determined to be abnormal by the detecting unit, and detect the clock link signal after the noise filtering process, when determining the When the state of the clock link signal after the noise filtering process is abnormal, sending a switch control signal to the clock driving unit;所述时钟驱动单元,设置为:根据所述开关控制信号关闭所述时钟接口模块的时钟输出。The clock driving unit is configured to turn off a clock output of the clock interface module according to the switch control signal.
- 如权利要求1至3中任意一项所述的时钟设备,其中,所述时钟处理模块是设置为:The clock device according to any one of claims 1 to 3, wherein the clock processing module is configured to:当利用锁相环电路检测到在预设时间内所述时钟接口模块无时钟输出 时,进入时钟保持状态,输出***时钟。When the phase locked loop circuit detects that the clock interface module has no clock output within a preset time When it enters the clock hold state, it outputs the system clock.
- 如权利要求4所述的时钟设备,其中,所述时钟链路信号为以太网信号或秒脉冲信号。The clock device of claim 4, wherein the clock link signal is an Ethernet signal or a second pulse signal.
- 一种时钟设备的时钟保持方法,所述时钟设备包括:时钟接口模块及时钟处理模块,所述方法包括:A clock holding method of a clock device, the clock device includes: a clock interface module and a clock processing module, and the method includes:所述时钟接口模块监测接收的时钟链路信号,当判断所述时钟链路信号异常时,关闭所述时钟接口模块的时钟输出;The clock interface module monitors the received clock link signal, and when it is determined that the clock link signal is abnormal, the clock output of the clock interface module is turned off;所述时钟处理模块当检测到所述时钟接口模块的时钟输出处于关闭状态时,进入时钟保持状态,输出***时钟。The clock processing module enters a clock hold state and outputs a system clock when detecting that the clock output of the clock interface module is in a closed state.
- 如权利要求6所述的时钟设备的时钟保持方法,其中,所述时钟接口模块监测接收的时钟链路信号,当判断所述时钟链路信号异常时,关闭所述时钟接口模块的时钟输出的步骤包括:The clock keeping method of a clock device according to claim 6, wherein the clock interface module monitors the received clock link signal, and when the clock link signal is abnormal, the clock output of the clock interface module is turned off. The steps include:所述时钟接口模块接收并检测上游时钟设备发送的时钟链路信号,当判断所述时钟链路信号的状态异常时,生成开关控制信号,并根据所述开关控制信号关闭所述时钟接口模块的时钟输出。The clock interface module receives and detects a clock link signal sent by the upstream clock device, and when it is determined that the state of the clock link signal is abnormal, generates a switch control signal, and closes the clock interface module according to the switch control signal. Clock output.
- 如权利要求6所述的时钟设备的时钟保持方法,其中,所述时钟接口模块监测接收的时钟链路信号,当判断所述时钟链路信号异常时,关闭所述时钟接口模块的时钟输出的步骤包括:The clock keeping method of a clock device according to claim 6, wherein the clock interface module monitors the received clock link signal, and when the clock link signal is abnormal, the clock output of the clock interface module is turned off. The steps include:所述时钟接口模块接收并检测上游时钟设备发送的时钟链路信号,对判断为异常的所述时钟链路信号进行噪声滤波处理,并对经噪声滤波处理后的所述时钟链路信号进行检测,当判断所述经噪声滤波处理后的时钟链路信号的状态异常时,生成开关控制信号,并根据所述开关控制信号关闭所述时钟接口模块的时钟输出。The clock interface module receives and detects a clock link signal sent by the upstream clock device, performs noise filtering processing on the clock link signal that is determined to be abnormal, and detects the clock link signal after the noise filtering process. And determining that a state of the clock link signal after the noise filtering process is abnormal, generating a switch control signal, and turning off a clock output of the clock interface module according to the switch control signal.
- 如权利要求6至8中任意一项所述的时钟设备的时钟保持方法,其中,所述时钟处理模块当检测到所述时钟接口模块的时钟输出处于关闭状态时,进入时钟保持状态,输出***时钟的步骤包括:The clock holding method of a clock device according to any one of claims 6 to 8, wherein the clock processing module enters a clock hold state when detecting that the clock output of the clock interface module is in an off state, and outputs the system The steps of the clock include:当利用锁相环电路检测到在预设时间内所述时钟接口模块无时钟输出时,进入时钟保持状态,输出***时钟。 When the phase-locked loop circuit detects that the clock interface module has no clock output within a preset time, it enters a clock hold state and outputs a system clock.
- 如权利要求9所述的时钟设备的时钟保持方法,其中,所述时钟链路信号为以太网信号或秒脉冲信号。A clock holding method of a clock device according to claim 9, wherein said clock link signal is an Ethernet signal or a second pulse signal.
- 一种计算机可读存储介质,存储有计算机可执行指令,所述计算机可执行指令用于执行权利要求6-10任一项的方法。 A computer readable storage medium storing computer executable instructions for performing the method of any of claims 6-10.
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