WO2016101555A1 - 一种交叉调度方法及其装置、存储介质 - Google Patents

一种交叉调度方法及其装置、存储介质 Download PDF

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Publication number
WO2016101555A1
WO2016101555A1 PCT/CN2015/081402 CN2015081402W WO2016101555A1 WO 2016101555 A1 WO2016101555 A1 WO 2016101555A1 CN 2015081402 W CN2015081402 W CN 2015081402W WO 2016101555 A1 WO2016101555 A1 WO 2016101555A1
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frame
slot
intermediate frame
ith
service information
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PCT/CN2015/081402
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English (en)
French (fr)
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赖伟
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深圳市中兴微电子技术有限公司
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Publication of WO2016101555A1 publication Critical patent/WO2016101555A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems

Definitions

  • the present invention relates to an optical transport network (OTN) technology, and in particular, to a cross scheduling method, a device thereof, and a storage medium.
  • OTN optical transport network
  • OTN optical transport network
  • OTN is required to have a clustered crossover function to provide a large amount of bandwidth to adapt to the continuous growth of services; however, the clustered crossover function requires adding a cross chip in the OTN to enable framing processing in the OTN (Framer)
  • the chip and the cross chip cooperate, but when the cross chip is added to the OTN, the rack of the node including the cross chip and the framer chip is large, and the energy consumption of the node is increased, thereby increasing the cost of the node. Therefore, increasing the clustering crossover function of the cross chip is only applicable to the backbone nodes;
  • the OTN can have a small capacity cross function; however, in the prior art, the above requirements are not met, and therefore, a new type of cross scheduling method is needed to meet the above requirements.
  • the embodiments of the present invention provide a cross scheduling method, a device thereof, and a storage medium, which can achieve cross-scheduling without using a cross chip.
  • the technical solution of the embodiment of the present invention is implemented as follows:
  • the embodiment of the present invention provides a cross scheduling method, which is applied to a source chip; the method includes:
  • the first indication position is capable of indicating a destination chip address corresponding to the first time slot frame in the first intermediate frame;
  • the destination end chip is the destination end chip corresponding to the service information.
  • N first time slot frames are mapped in the first intermediate frame
  • the first first time slot frame and the second first time slot in the N first time slot frames The first time slot position corresponding to each of the Nth first time slot frame is corresponding to the first intermediate frame; the first first time slot frame and the second of the N first time slot frames
  • the destination chip addresses corresponding to the first slot frame to the Nth slot frame are the same; wherein N is a positive integer greater than or equal to 2.
  • the K is a positive integer greater than or equal to 2; the method further includes:
  • the ith indication location is capable of indicating an ith destination chip address corresponding to an ith slot frame in the ith intermediate frame
  • the ith target chip is a destination chip corresponding to the ith service information of the K service information.
  • the sending the i-th intermediate frame includes:
  • the first header information is unified in the first intermediate frame, the second intermediate frame, and the ith intermediate frame to the Kth intermediate frame Frame header information;
  • the transmission frame header information is the ith intermediate frame of the first frame header information.
  • the embodiment of the invention further provides a cross scheduling method, which is applied to a destination chip; the method includes:
  • the embodiment of the invention further provides a cross scheduling device, the device comprising:
  • a first receiving unit configured to receive service information
  • a first mapping unit configured to map or demap data corresponding to the service information to the first slot frame
  • a second mapping unit configured to map the first slot frame to a first intermediate frame based on a first slot position of the first slot frame; the first slot position capable of indicating the first Corresponding relationship between the slot frame and the first intermediate frame;
  • the first sending unit is configured to send the first intermediate frame according to the first indication position of the first intermediate frame, where the first indication position can indicate that the first time slot frame in the first intermediate frame corresponds to The destination chip address; the destination chip is the destination chip corresponding to the service information.
  • N first time slot frames are mapped in the first intermediate frame
  • the N The first first slot frame in the first slot frame, the first slot position corresponding to each of the second first slot frame to the Nth first slot frame, and the first intermediate frame Corresponding; the destination address of the first first time slot frame, the second first time slot frame, and the Nth first time slot frame of the N first time slot frames are the same; N is a positive integer greater than or equal to 2.
  • the K is a positive integer greater than or equal to 2; correspondingly,
  • the first receiving unit is further configured to receive K service information
  • the first mapping unit is further configured to map or demap the data corresponding to the K service information to the first slot frame, the second slot frame, the ith slot frame to the Kth slot frame respectively; Said i is a positive integer greater than or equal to 1 and less than or equal to K;
  • the second mapping unit is further configured to map the ith slot frame to an ith intermediate frame based on an ith slot position of the ith slot frame; the ith slot position can indicate Corresponding relationship between the i-th slot frame and the i-th intermediate frame;
  • the first sending unit is further configured to: send the i th intermediate frame based on an ith indication position of the i th intermediate frame; the i th indication position can indicate an i th slot in the i th intermediate frame
  • the i-th destination chip address corresponding to the frame; the i-th destination end chip is a destination end chip corresponding to the i-th service information of the K service information.
  • the first sending unit is further configured to replace the header information in the i-th intermediate frame with the first frame header information;
  • the first frame header information is a first intermediate frame, a second intermediate Uniform frame header information in the frame, the ith intermediate frame to the Kth intermediate frame;
  • the embodiment of the invention further provides a cross scheduling device, the device comprising:
  • a second receiving unit configured to receive the first intermediate frame
  • a first demapping unit configured to demap the first intermediate frame to a first slot frame
  • a second demapping unit configured to be based on a first slot position of the first slot frame
  • the first time slot frame is mapped or demapped to the service information;
  • the first time slot position can indicate a correspondence between the first time slot frame and the service information;
  • the second sending unit is configured to send the service information.
  • the cross scheduling method and the device and the storage medium provided by the embodiments of the present invention are capable of mapping or demapping data corresponding to the received service information to a first time slot frame; and based on the first frame of the first time slot frame a slot position, mapping the first slot frame to a first intermediate frame; and further transmitting the first intermediate frame to a destination corresponding to the service information based on the first indication position of the first intermediate frame
  • the end chip in this way, achieves the purpose of cross scheduling.
  • the embodiment of the present invention can achieve the purpose of cross-scheduling without using a cross chip. Therefore, the embodiment of the present invention can reduce scheduling costs and reduce power consumption.
  • FIG. 1 is a schematic flowchart 1 of an implementation flow of a cross scheduling method according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram 1 of a cross-scheduling device according to an embodiment of the present invention
  • FIG. 3 is a schematic flowchart 2 of an implementation process of a cross-scheduling method according to an embodiment of the present invention
  • FIG. 4 is a schematic structural diagram 2 of a cross-scheduling device according to an embodiment of the present invention.
  • FIG. 5 is a schematic flowchart 1 of a specific implementation of a cross-scheduling method according to an embodiment of the present invention
  • FIG. 6 is a second schematic flowchart of a specific implementation of a cross-scheduling method according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of mapping relationship between a slot frame and an intermediate frame in a source-end Framer chip according to an embodiment of the present invention.
  • FIG. 1 is a schematic flowchart 1 of an implementation process of a cross-scheduling method according to an embodiment of the present invention; the method is applied to a source chip, and the method includes:
  • Step 101 Receive service information.
  • the source chip can use a Framer chip, that is, a source framer chip; further, the source framer chip can receive various types of service information on its client side, for example, OTN service information, Ethernet Network business information, etc.
  • Step 102 Map or demap data corresponding to the service information to the first slot frame.
  • the source-side Framer chip maps or demaps the data corresponding to the service information to the optical channel data unit ( In the ODUK), the data corresponding to the service information mapped or demapping to the ODUK is further mapped or demapped into the ODUK slot frame according to the requirements of the slot frame, that is, in the first slot frame described in this embodiment.
  • the service rate corresponding to the service information is different. Therefore, when the data corresponding to the service information is mapped or demapped into the ODUK slot frame, that is, in the first slot frame, A different number of padding regions are set according to the structure of the ODUK slot frame.
  • Step 103 Map the first slot frame to a first intermediate frame based on a first slot position of the first slot frame; the first slot position can indicate the first slot frame and Corresponding relationship of the first intermediate frame;
  • the source-side Framer chip performs cross-scheduling on the transmitting side of the backplane to the ODUK slot frame, that is, the first slot frame by slot position, that is, the source-side Framer chip is on its back.
  • the transmitting side of the board maps the first slot frame to the first intermediate frame according to the first slot position corresponding to the first slot frame; and the first slot position and the first intermediate Corresponding to the frame, and since the first intermediate frame corresponds to the destination chip address corresponding to the service information, the first time slot frame can be sent to the first time slot by using the first intermediate frame.
  • frame The corresponding destination chip is sent to the destination chip corresponding to the service information.
  • the structure of the first intermediate frame is similar to the OTN frame structure class, and is a container for carrying ODUK time slot frames; therefore, the source framer chip can divide different ODUK time slot frames.
  • the time slots are mixed into the intermediate frame structure.
  • N first time slot frames are mapped in the first intermediate frame
  • the first first time slot frame and the second first time slot in the N first time slot frames The first time slot position corresponding to each of the Nth first time slot frame is corresponding to the first intermediate frame; the first first time slot frame and the second of the N first time slot frames
  • the destination chip addresses corresponding to the first slot frame to the Nth slot frame are the same; wherein N is a positive integer greater than or equal to 2.
  • the source-side Framer chip can receive N service information of different service types at the same time or in sequence, and the source-side Framer chip can map or demap the data corresponding to the N service information to N In the first slot frame, when the first slot position corresponding to each first slot frame in the N first slot frames is corresponding to the first intermediate frame, the N first The slot frames are all mapped into the first intermediate frame;
  • the first intermediate frame can include N first time slot frames, and the first time slot position corresponding to each first time slot frame of the N first time slot frames points to the a first intermediate frame, that is, a first time slot position corresponding to each of the N first time slot frames corresponds to the first intermediate frame, and therefore, the source framer The chip maps the N first slot frames to the first intermediate frame.
  • the source-side Framer chip can also receive K service information of different service types, that is, the first service information, the second service information, and the i-th service information to the K-th service information.
  • the source-side Framer chip respectively maps or demaps the data corresponding to the K service information into the first slot frame, the second slot frame, the i-slot frame to the K-slot frame.
  • the K is a positive integer greater than or equal to 2
  • the i is a positive integer greater than or equal to 1 and less than or equal to K;
  • the corresponding ith slot position corresponds to the ith slot position, and the ith slot position can indicate the correspondence between the ith slot frame and the intermediate frame;
  • the first time slot position corresponds to the first intermediate frame
  • the second time slot position corresponds to the second intermediate frame
  • the ith time slot position corresponds to the ith intermediate frame
  • the Kth time slot position corresponds to the Kth intermediate frame
  • the source-side Framer chip is further capable of using the first slot frame, the second slot frame, and the ith time based on the first slot position, the second slot position, the i-th slot position to the K-th slot position
  • the slot frame to the Kth slot frame are correspondingly mapped into the first intermediate frame, the second intermediate frame, the ith intermediate frame to the Kth intermediate frame.
  • Step 104 Send the first intermediate frame according to the first indication position of the first intermediate frame, where the first indication position can indicate a destination end chip corresponding to the first time slot frame in the first intermediate frame.
  • the destination chip is the destination chip corresponding to the service information.
  • the source framer chip on the transmitting side of the backplane, can send the first intermediate frame to and the first indicated location based on the first indicated position of the first intermediate frame.
  • the source framer chip transmits the first intermediate frame carrying the first slot frame to the first slot position and the first indication position.
  • the destination chip corresponding to the first slot frame the purpose of cross scheduling is implemented.
  • the source framer chip is unified on the transmitting side of the backplane, and the intermediate frame structure to be sent is unified into the intermediate frame of the first frame header information after the frame header information is aligned and transmitted;
  • the backplane SerDes interface is interconnected with the destination chip corresponding to the intermediate frame to be sent, that is, the source framer chip can be associated with the intermediate frame to be sent through the backplane SerDes interface of the source framer chip.
  • the destination end chip is interconnected to form an MESH structure. Therefore, the source framer chip can send the intermediate frame to the destination end chip, thereby laying a foundation for implementing cross scheduling.
  • the K is a positive integer greater than or equal to 2; the method further includes:
  • the i is a positive integer greater than or equal to 1 and less than or equal to K;
  • the ith indication location is capable of indicating an ith destination chip address corresponding to an ith slot frame in the ith intermediate frame
  • the ith target chip is a destination chip corresponding to the ith service information of the K service information.
  • the method further includes:
  • the i is a positive integer greater than or equal to 1 and less than K;
  • the first time slot position can indicate a correspondence between the first time slot frame and the first intermediate frame;
  • the second time slot position can indicate the second time slot frame and the second intermediate position Corresponding relationship of the frame;
  • the ith slot position can indicate a correspondence between the ith slot frame and the ith intermediate frame;
  • the Kth slot position can indicate the Kth slot frame and location Corresponding relationship of the Kth intermediate frame;
  • the first indication position can And indicating a first destination chip address corresponding to the first slot frame in the first intermediate frame, where the second indication location is capable of indicating a second destination end corresponding to the second slot frame in the second intermediate frame a chip address;
  • the ith indication position is capable of indicating an ith destination chip address corresponding to an ith slot frame in the ith intermediate frame;
  • the Kth indication location is capable of indicating a Kth in the Kth intermediate frame a K-th destination chip address corresponding to the time slot frame;
  • the first destination end chip is a destination end chip corresponding to the first service information; and the second destination end chip is a destination corresponding to the second service information
  • the end chip; the ith destination chip is the destination chip
  • the sending the i-th intermediate frame includes:
  • the first header information is unified in the first intermediate frame, the second intermediate frame, and the ith intermediate frame to the Kth intermediate frame Frame header information;
  • the transmission frame header information is the ith intermediate frame of the first frame header information.
  • the sending the first intermediate frame, the second intermediate frame, the i-th intermediate frame to the K-th intermediate frame including:
  • the frame header information of all the intermediate frames sent by the source-end Framer chip is a unified frame header information, that is, the first frame header information; further, the source-end Framer chip will send the intermediate frame to be sent. After the frame header information is unified into the first frame header information, the frame header information is sequentially sent to be the intermediate frame of the first frame header information;
  • the frame header information of the intermediate frame to be transmitted by the source framer chip is the first frame header information
  • the frame header information is directly sent as the intermediate frame of the first frame header information
  • the frame header information of the intermediate frame to be sent by the source framer chip is not the first frame header information
  • the frame header information of the intermediate frame to be sent is replaced with the first frame header information, and then, the frame header is used.
  • the information is transmitted for the intermediate frame of the first frame header information.
  • the embodiment of the invention further provides a first computer readable storage medium, the storage medium comprising a set of instructions, the instructions being used in the cross scheduling method according to the first embodiment.
  • an embodiment of the present invention further provides a cross scheduling device. As shown in FIG. 2, the device includes:
  • the first receiving unit 21 is configured to receive service information.
  • the first mapping unit 22 is configured to map or demap data corresponding to the service information to the first slot frame
  • the second mapping unit 23 is configured to map the first slot frame to a first intermediate frame based on a first slot position of the first slot frame; the first slot position can indicate the first a correspondence between a slot frame and the first intermediate frame;
  • the first sending unit 24 is configured to send the first intermediate frame according to the first indicated position of the first intermediate frame, where the first indicated position can indicate the first time slot frame in the first intermediate frame Corresponding destination chip address; the destination chip is a destination chip corresponding to the service information.
  • N first time slot frames are mapped in the first intermediate frame
  • the first first time slot frame and the second first time slot in the N first time slot frames The first time slot position corresponding to each of the Nth first time slot frame is corresponding to the first intermediate frame; the first first time slot frame and the second of the N first time slot frames
  • the destination chip addresses corresponding to the first slot frame to the Nth slot frame are the same; wherein N is a positive integer greater than or equal to 2.
  • the K is a positive integer greater than or equal to 2; correspondingly,
  • the first receiving unit 21 is further configured to receive K service information.
  • the first mapping unit 22 is further configured to map or demap data corresponding to the K service information to the first slot frame, the second slot frame, the i th slot frame to the Kth slot frame, respectively;
  • the i is a positive integer greater than or equal to 1 and less than or equal to K;
  • the second mapping unit 23 is further configured to map the ith slot frame to an ith intermediate frame based on an ith slot position of the ith slot frame; the ith slot position can indicate Corresponding relationship between the ith slot frame and the ith intermediate frame;
  • the first transmitting unit 24 is further configured to: send the ith intermediate frame based on an ith indication position of the ith intermediate frame; and the ith indication position can indicate an ith time in the ith intermediate frame
  • the ith destination chip address corresponding to the slot frame; the ith destination chip is the destination chip corresponding to the ith service information of the K service information.
  • the first sending unit 24 is further configured to replace the header information in the i-th intermediate frame with the first frame header information;
  • the first frame header information is a first intermediate frame, and the second Uniform frame header information in the intermediate frame, the ith intermediate frame to the Kth intermediate frame;
  • the first receiving unit 21, the first mapping unit 22, the second mapping unit 23, and the first sending unit 24 may all run in a source chip, and may be a central processor located in the source chip ( CPU), or microprocessor (MPU), or digital signal processor (DSP), or programmable gate array (FPGA) implementation.
  • CPU source chip
  • MPU microprocessor
  • DSP digital signal processor
  • FPGA programmable gate array
  • the cross-scheduling method and the device and the storage medium according to the embodiments of the present invention can realize the low-cost ODUK small-capacity cross-distribution purpose of the Framer chip interconnection through the ODUK cross-scheduling method of the MESH structure.
  • the embodiment of the present invention The cross-scheduling method and device thereof are different from the cluster cross-scheduling method and system. That is to say, the embodiment of the present invention does not require a special cross chip, and only needs to interconnect the source framer chip and the destination end framer chip.
  • the cross-scheduling process is implemented. Therefore, the embodiment of the present invention can reduce scheduling costs and reduce energy consumption.
  • the embodiment of the present invention since the embodiment of the present invention has low cost and low power consumption, it can also be applied to edge connection. Into the process of cross-scheduling of the sink node.
  • FIG. 3 is a schematic flowchart 2 of an implementation process of a cross-scheduling method according to an embodiment of the present invention; the method is applied to a destination end chip; as shown in FIG. 3, the method includes:
  • Step 301 Receive a first intermediate frame.
  • the destination end chip may be a Framer chip, that is, a destination end Framer chip; further, the destination end Framer chip is connected to the first intermediate frame on its backplane receiving side.
  • Step 302 Demap the first intermediate frame to a first slot frame.
  • the destination end Framer chip is in accordance with the source end Framer chip corresponding to the first intermediate frame.
  • the first intermediate frame performs a distinguishing process, and after the distinguishing process, the first intermediate frame is demapped to ODUK, and further demapped to a first time slot frame, that is, a first ODUK time slot frame.
  • the destination-end Framer chip when the destination-end Framer chip receives a plurality of intermediate frames from a plurality of source-side Framer chips on its backplane side, specifically,
  • the destination end Framer chip After the destination end Framer chip receives the first intermediate frame, the second intermediate frame, the jth intermediate frame and the Mth intermediate frame on the backplane side thereof, the destination end Framer chip follows the first intermediate frame and the second frame.
  • the source framer chip corresponding to the intermediate frame, the jth intermediate frame, and the Mth intermediate frame respectively distinguishes the first intermediate frame, the second intermediate frame, the jth intermediate frame to the Mth intermediate frame, and the frame header information alignment processing, After the alignment and the frame header information are aligned, the first intermediate frame, the second intermediate frame, the jth intermediate frame to the Mth intermediate frame, which are aligned with the header information, are respectively mapped to the first time slot frame and the second frame, respectively.
  • Step 303 Map or demap the first slot frame to service information based on a first slot position of the first slot frame; the first slot position can indicate the first slot frame And Corresponding relationship of business information;
  • the destination end Framer chip when the destination end Framer chip receives M intermediate frames from multiple source Framer chips on its backplane side, and the destination End Framer chip will be the first of the M intermediate frames.
  • the intermediate frame, the second intermediate frame, the jth intermediate frame to the Mth intermediate frame are respectively mapped to the first slot frame, the second slot frame, the jth slot frame to the Mth slot frame,
  • the destination end Framer chip is based on a first slot position of the first slot frame, a second slot position of the second slot frame, and a jth slot position of the jth slot frame to Mapping or de-mapping the first slot frame, the second slot frame, the j-th slot frame to the M-th slot frame to the first service information, and the M-th slot position of the M-th slot frame Second, business information, jth business information to Mth business information;
  • the first slot position can indicate a correspondence between the first slot frame and the first service information;
  • the second slot position can indicate the second slot frame and the second slot Corresponding relationship of the service information;
  • the jth slot position can indicate a correspondence between the jth slot frame and the jth service information;
  • the Mth slot position can indicate the Mth slot frame and Corresponding relationship of the Mth service information; in this manner, the destination end Framer chip demaps the received M intermediate frames from the multiple source Framer chips to the M service information.
  • Step 304 Send the service information.
  • the destination end Framer chip sends the service information on its client sending side.
  • the service information may be OTN service information, or Ethernet service information, and the like.
  • the destination end Framer chip when the destination end Framer chip receives M intermediate frames from multiple source Framer chips on its backplane side, and the destination End Framer chip demaps the M intermediate frames to M. After the service information, the destination end Framer chip sends the M service information.
  • the destination end Framer chip schedules, on the backplane receiving side, the demapped ODUK slot frame, that is, the first slot frame by slot position, specifically, when the destination The end Framer chip demaps the M intermediate frames from the multiple source Framer chips to the M time slot frames on the receiving side of the backplane, that is, the first time slot frame, the second time slot frame, and the jth time slot.
  • the destination end Framer chip can be based on the first time slot position of the first time slot frame and the second time slot position of the second time slot frame on its backplane receiving side.
  • the client side of the framer chip corresponds to the transmitting side, that is, the time slot position can indicate the corresponding relationship between the time slot frame and the service information, so that the destination framer chip can send the time slot frame based on the time slot position.
  • the destination end Framer chip can be based on a first slot position of the first slot frame, a second slot position of the second slot frame, and a jth time of the jth slot frame. And transmitting, by the slot location to the Mth slot position of the Mth slot frame, the first service information, the second service information, and the jth service information to the Mth service information.
  • the embodiment of the present invention further provides a second computer readable storage medium, where the storage medium includes a set of instructions, and the instructions are used in the cross scheduling method described in Embodiment 2.
  • the embodiment of the present invention further provides a cross scheduling device. As shown in FIG. 4, the device includes:
  • the second receiving unit 41 is configured to receive the first intermediate frame
  • a first demapping unit 42 configured to demap the first intermediate frame to a first slot frame
  • the second demapping unit 43 is configured to map or demap the first slot frame to service information based on a first slot position of the first slot frame; the first slot position can indicate Corresponding relationship between the first slot frame and the service information;
  • the second sending unit 44 is configured to send the service information.
  • the second receiving unit 41, the first demapping unit 42, the second demapping unit 43, and the second sending unit 44 may all run in the destination chip, and may be located at the destination.
  • CPU central processing unit
  • MPU microprocessor
  • DSP digital signal processor
  • FPGA programmable gate array
  • FIG. 5 is a schematic flowchart 1 of a specific implementation of a cross-scheduling method according to an embodiment of the present invention; the method is applied to a source-side Framer chip; as shown in FIG. 5, the method includes:
  • Step 501 The source framer chip receives K service information on its client side, and maps or demaps the data corresponding to the K service information to K ODUK time slot frames, that is, the first time slot frame and the second frame.
  • K is a positive integer greater than or equal to 2
  • the i is a positive integer greater than or equal to 1 and less than or equal to K;
  • the service information received by the source-side Framer chip on its client side is OTN service information and/or Ethernet service information;
  • the source-side Framer chip When the source-side Framer chip receives the OTN service information on its client side, the source-side Framer chip demaps the data corresponding to the OTN service information to the ODUK time slot frame;
  • the source-side Framer chip When the source-side Framer chip receives the Ethernet service information on its client side, the source-side Framer chip passes the bit synchronization mapping (BMP), the asynchronous mapping (AMP), or according to the rate level of the Ethernet service information. a mechanism such as a universal mapping (GMP), mapping data corresponding to the Ethernet service information to a corresponding ODUK time slot frame;
  • BMP bit synchronization mapping
  • AMP asynchronous mapping
  • GMP universal mapping
  • the data corresponding to the Ethernet service information is directly mapped to the ODUK slot frame corresponding to the rate by using the BMP method.
  • the data corresponding to the Ethernet service information is usually adopted by the AMP method. Mapping into an ODUK slot frame; when mapping, selectively padding data bytes or adjusting bytes in the NJO field and the PJO field of the ODUk slot frame;
  • a GMP method When mapping low-rate Ethernet service information to a high-rate ODUK slot frame, a GMP method is generally adopted, and the GMP method adopts a sigma/delta rule, and thus, the mapping party and the mapped party are adopted by the sigma/delta rule. Rate matching, so that the service signal corresponding to the Ethernet information is evenly distributed in the payload of the ODUK slot frame.
  • a high-speed ODUK slot frame structure may occupy multiple ODUKs.
  • a time slot the data corresponding to each ODUK time slot can be converted to a unified time slot by a bit width, for example, converted into an 8-bit time slot; then, the buses of the plurality of ODUK time slots are aggregated into an ODUK space-division bus, Each bit of the ODUK space-division bus is one unit, that is, an ODUK time slot; here, the service information with higher rate can occupy multiple 8-bit units.
  • Step 502 The source framer chip is on the transmitting side of the backplane, based on the first slot position of the first slot frame, the second slot position of the second slot frame, and the i-th slot frame. Mapping the first slot frame, the second slot frame, the ith slot frame to the Kth slot frame to the first intermediate position from the i slot position to the Kth slot position of the Kth slot frame a frame, a second intermediate frame, an i-th intermediate frame to a K-th intermediate frame;
  • the first slot position can indicate a correspondence between the first slot frame and the first intermediate frame;
  • the second slot position can indicate the second slot frame and the second slot Corresponding relationship of the intermediate frame;
  • the ith slot position can indicate a correspondence between the ith slot frame and the ith intermediate frame;
  • the Kth slot position can indicate the Kth slot frame and Corresponding relationship of the Kth intermediate frame; as described in FIG. 7, the first time slot frame, based on the first time slot position, the second time slot position, the i th slot position to the Kth slot position, The second slot frame, the i th slot frame to the Kth slot frame are correspondingly mapped to the first intermediate frame, the second intermediate frame, the i th intermediate frame to the Kth intermediate frame.
  • the source-side Framer chip maps the ODUK slot frame to the intermediate frame structure according to the location on the transmitting side of the backplane; that is, the source-side Framer chip is on the transmitting side of the backplane,
  • the first time slot position of the first time slot frame, the second time slot position of the second time slot frame, the ith time slot position of the ith time slot frame, and the Kth time slot position of the Kth time slot frame
  • the first slot frame, the second slot frame, the i th slot frame to the Kth slot frame are correspondingly mapped to the first intermediate frame, the second intermediate frame, the i th intermediate frame to the Kth intermediate frame; Transmitting, according to the ith indication position of the i th intermediate frame, the i th intermediate frame; and the source end framer chip capable of simultaneously selecting the K intermediate frames according to the K intermediate frames
  • the indicated location is sent out. Therefore, the transmitting side of the backplane of the source Framer chip can perform cross scheduling on the OTUK slot frame by slot
  • the intermediate frame structure is similar to the OTU frame structure defined in the G.709 protocol, and is a container for carrying ODUK slot frames.
  • the present embodiment can use the GMP mechanism to mix different time slot frames into time slots into an intermediate frame structure.
  • Step 503 Send the first indication position based on the first indication position of the first intermediate frame, the second indication position of the second intermediate frame, the ith indication position of the i-th intermediate frame, and the Kth indication position of the Kth intermediate frame.
  • the first indication location can indicate a first destination chip address corresponding to the first slot frame in the first intermediate frame; the second indication location can indicate a second time in the second intermediate frame a second destination chip address corresponding to the slot frame; the ith indication position can indicate an ith destination chip address corresponding to the ith slot frame in the i th intermediate frame; the Kth indication position can indicate a Kth destination chip address corresponding to the Kth time slot frame in the Kth intermediate frame; the first destination end chip is a destination end chip corresponding to the first service information; and the second destination end chip is The destination chip corresponding to the second service information; the ith destination chip is a destination chip corresponding to the ith service information; and the Kth destination chip is a destination corresponding to the Kth service information chip.
  • the source framer chip unifies the frame header information in the first intermediate frame, the second intermediate frame, the i-th intermediate frame, and the K-th intermediate frame into the first frame header information on the transmitting side of the backplane, And aligning the header information to send the first intermediate frame, the second intermediate frame, the i-th intermediate frame to the K-th intermediate frame;
  • unified frame header information is used in the structure of each intermediate frame, and the frame header information is aligned and sent; since the backplane SerDes of the source framer chip is interconnected with the Framer chip of the destination end, therefore, Embodiments are capable of transmitting each intermediate frame to a destination-side Framer chip.
  • the number of Framer chips is limited by the number of SerDes links on the backplane side; for example, it is necessary to ensure that one Framer chip has a SerDes link to each of the other Framer chips; and the intersection between the two Framer chips
  • the bandwidth is determined by the number and rate of SerDes between them.
  • FIG. 6 is a schematic flowchart 2 of a specific implementation of a cross-scheduling method according to an embodiment of the present invention; the method is applied to a target-end Framer chip; as shown in FIG. 6, the method includes:
  • Step 601 The destination side Framer chip receives M intermediate frames from multiple source Framer chips on its receiving side of the backplane;
  • the destination end Framer chip distinguishes the M intermediate frames according to the source framer chip, and aligns the frame header information in each intermediate frame structure from the same source Framer chip;
  • Step 602 The destination end Framer chip demaps the M intermediate frames on its receiving side of the backplane, and demaps to M ODUK slot frames, that is, the first slot frame and the second slot frame. , the jth slot frame to the Mth slot frame;
  • the destination end Framer chip converts the data corresponding to each ODUK time slot of the demlocated M ODUK time slot frames to a uniform size, for example, into 8 bits, on the receiving side of the backplane. Subsequently, the buses of multiple ODUK time slots are aggregated into ODUK space The sub-bus divides the slot position in units of 8 bits, so that the slot position can correspond to the slot information and the service information, and further corresponds to the client transmitting side of the destination framer.
  • Step 603 The destination end Framer chip maps or demaps the first slot frame, the second slot frame, the jth slot frame to the Mth slot frame to various M service information on its client transmitting side. And sending the M service information from the client sending side.
  • the service information includes OTN service information, or Ethernet service information, and the like.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • the embodiment of the present invention can map or demap the data corresponding to the received service information to the first slot frame; and map the first slot frame based on the first slot position of the first slot frame. And the first intermediate frame is sent to the destination end chip corresponding to the service information, so that the purpose of cross scheduling is achieved.
  • the embodiment of the present invention can achieve the purpose of cross-scheduling without using a cross chip. Therefore, the embodiment of the present invention can reduce scheduling costs and reduce power consumption.

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Abstract

本发明实施例公开了一种交叉调度方法，包括：接收业务信息；将业务信息对应的数据映射或解映射至第一时隙帧；基于所述第一时隙帧的第一时隙位置，将所述第一时隙帧映射至第一中间帧；所述第一时隙位置能够指示所述第一时隙帧与所述第一中间帧的对应关系；基于所述第一中间帧的第一指示位置，发送所述第一中间帧；所述第一指示位置能够指示所述第一中间帧中第一时隙帧所对应的目的端芯片地址；所述目的端芯片为所述业务信息对应的目的端芯片。本发明实施例还公开了一种交叉调度装置及存储介质。

Description

一种交叉调度方法及其装置、存储介质 技术领域
本发明涉及光传送网络(OTN，Optical Transport Network)技术，尤其涉及一种交叉调度方法及其装置、存储介质。
背景技术
随着网络业务的飞速增长，特别是宽带、交互式网络电视(IPTV)、视频等业务的飞速发展，对光传送网络(OTN)技术提出了新的要求。例如，
一方面，要求OTN能够具有集群式交叉功能，以提供海量带宽，适应业务的不断增长；但是，所述集群式交叉功能，需要在OTN中增加交叉芯片，以使OTN中的成帧处理(Framer)芯片和所述交叉芯片配合，但是，当所述OTN中加入交叉芯片后，会包含有交叉芯片和Framer芯片的节点的机架庞大，且使该节点能耗增加，进而增加该节点成本，因此，增加交叉芯片的集群式交叉功能只适用于骨干节点；
另一方面，还需要OTN能够具备小容量的交叉功能；但是，现有技术中，并不能满足上述需求，因此，亟需一种新型的交叉调度方法，以满足上述需求。
发明内容
为解决现有存在的技术问题，本发明实施例提供了一种交叉调度方法及其装置、存储介质，能够在不使用交叉芯片的条件下，实现交叉调度的目的。
本发明实施例的技术方案是这样实现的：本发明实施例提供了一种交叉调度方法，应用于源端芯片；所述方法包括：
接收业务信息；
将业务信息对应的数据映射或解映射至第一时隙帧；
基于所述第一时隙帧的第一时隙位置，将所述第一时隙帧映射至第一中间帧；所述第一时隙位置能够指示所述第一时隙帧与所述第一中间帧的对应关系；
基于所述第一中间帧的第一指示位置，发送所述第一中间帧；所述第一指示位置能够指示所述第一中间帧中第一时隙帧所对应的目的端芯片地址；所述目的端芯片为所述业务信息对应的目的端芯片。
上述方案中，当所述第一中间帧中映射有N个第一时隙帧时，所述N个第一时隙帧中的第一个第一时隙帧、第二个第一时隙帧至第N个第一时隙帧各自对应的第一时隙位置均与所述第一中间帧对应；所述N个第一时隙帧中的第一个第一时隙帧、第二个第一时隙帧至第N个第一时隙帧对应的目的端芯片地址相同；其中，所述N为大于等于2的正整数。
上述方案中，当接收到的业务信息为K个时，所述K为大于等于2的正整数；所述方法还包括：
将K个业务信息对应的数据分别映射或解映射至第一时隙帧、第二时隙帧、第i时隙帧至第K个时隙帧；所述i为大于等于1小于等于K的正整数；
基于所述第i时隙帧的第i时隙位置，将所述第i时隙帧映射至第i中间帧；所述第i时隙位置能够指示所述第i时隙帧与所述第i中间帧的对应关系；
基于所述第i中间帧的第i指示位置，发送所述第i中间帧；所述第i指示位置能够指示所述第i中间帧中第i时隙帧所对应的第i目的端芯片地址；所述第i目的端芯片为所述K个业务信息中的第i业务信息对应的目的端芯片。
上述方案中，所述发送所述第i中间帧，包括：
将所述第i中间帧中的帧头信息替换成第一帧头信息；所述第一帧头信息为第一中间帧、第二中间帧、第i中间帧至第K中间帧中统一的帧头信息；
发送帧头信息为第一帧头信息的所述第i中间帧。
本发明实施例还提供了一种交叉调度方法，所述方法应用于目的端芯片；所述方法包括：
接收第一中间帧；
将所述第一中间帧解映射至第一时隙帧；
基于所述第一时隙帧的第一时隙位置，将所述第一时隙帧映射或解映射至业务信息；所述第一时隙位置能够指示所述第一时隙帧与所述业务信息的对应关系；
发送所述业务信息。
本发明实施例还提供了一种交叉调度装置，所述装置包括：
第一接收单元，配置为接收业务信息；
第一映射单元，配置为将业务信息对应的数据映射或解映射至第一时隙帧；
第二映射单元，配置为基于所述第一时隙帧的第一时隙位置，将所述第一时隙帧映射至第一中间帧；所述第一时隙位置能够指示所述第一时隙帧与所述第一中间帧的对应关系；
第一发送单元，配置为基于所述第一中间帧的第一指示位置，发送所述第一中间帧；所述第一指示位置能够指示所述第一中间帧中第一时隙帧所对应的目的端芯片地址；所述目的端芯片为所述业务信息对应的目的端芯片。
上述方案中，当所述第一中间帧中映射有N个第一时隙帧时，所述N 个第一时隙帧中的第一个第一时隙帧、第二个第一时隙帧至第N个第一时隙帧各自对应的第一时隙位置均与所述第一中间帧对应；所述N个第一时隙帧中的第一个第一时隙帧、第二个第一时隙帧至第N个第一时隙帧对应的目的端芯片地址相同；其中，所述N为大于等于2的正整数。
上述方案中，当接收到的业务信息为K个时，所述K为大于等于2的正整数；对应地，
所述第一接收单元，还配置为接收K个业务信息；
所述第一映射单元，还配置为将K个业务信息对应的数据分别映射或解映射至第一时隙帧、第二时隙帧、第i时隙帧至第K个时隙帧；所述i为大于等于1小于等于K的正整数；
所述第二映射单元，还配置为基于所述第i时隙帧的第i时隙位置，将所述第i时隙帧映射至第i中间帧；所述第i时隙位置能够指示所述第i时隙帧与所述第i中间帧的对应关系；
所述第一发送单元，还配置为基于所述第i中间帧的第i指示位置，发送所述第i中间帧；所述第i指示位置能够指示所述第i中间帧中第i时隙帧所对应的第i目的端芯片地址；所述第i目的端芯片为所述K个业务信息中的第i业务信息对应的目的端芯片。
上述方案中，所述第一发送单元，还配置为将所述第i中间帧中的帧头信息替换成第一帧头信息；所述第一帧头信息为第一中间帧、第二中间帧、第i中间帧至第K中间帧中统一的帧头信息；
还配置为发送帧头信息为第一帧头信息的所述第i中间帧。
本发明实施例还提供了一种交叉调度装置，所述装置包括：
第二接收单元，配置为接收第一中间帧；
第一解映射单元，配置为将所述第一中间帧解映射至第一时隙帧；
第二解映射单元，配置为基于所述第一时隙帧的第一时隙位置，将所 述第一时隙帧映射或解映射至业务信息；所述第一时隙位置能够指示所述第一时隙帧与所述业务信息的对应关系；
第二发送单元，配置为发送所述业务信息。
本发明实施例所提供的交叉调度方法及其装置、存储介质，能够将接收到的业务信息对应的数据映射或解映射至第一时隙帧；并基于所述第一时隙帧的第一时隙位置，将所述第一时隙帧映射至第一中间帧；进而基于所述第一中间帧的第一指示位置，将所述第一中间帧发送至与所述业务信息对应的目的端芯片，如此，实现交叉调度的目的。
另外，由于本发明实施例无需使用交叉芯片，就能实现交叉调度的目的，因此，本发明实施例能够降低调度成本、降低能耗。
附图说明
图1为本发明实施例交叉调度方法的实现流程示意图一；
图2为本发明实施例交叉调度装置的结构示意图一；
图3为本发明实施例交叉调度方法的实现流程示意图二；
图4为本发明实施例交叉调度装置的结构示意图二；
图5为本发明实施例交叉调度方法的具体实现的流程示意图一；
图6为本发明实施例交叉调度方法的具体实现的流程示意图二；
图7为本发明实施例源端Framer芯片中时隙帧与中间帧的映射关系示意图。
具体实施方式
为了能够更加详尽地了解本发明实施例的特点与技术内容，下面结合附图对本发明实施例的实现进行详细阐述，所附附图仅供参考说明之用，并非用来限定本发明。
实施例一
图1为本发明实施例交叉调度方法的实现流程示意图一；所述方法应用于源端芯片，所述方法包括：
步骤101：接收业务信息；
本实施例中，所述源端芯片可以采用Framer芯片，即源端Framer芯片；进一步地，所述源端Framer芯片在其客户侧能够接收各种类型的业务信息，例如，OTN业务信息、以太网业务信息等。
步骤102：将业务信息对应的数据映射或解映射至第一时隙帧；
本实施例中，当所述源端Framer芯片在其客户侧接收到各种类型的业务信息后，所述源端Framer芯片将所述业务信息对应的数据映射或解映射至光通道数据单元(ODUK)中，并进一步将映射或解映射至ODUK的业务信息对应的数据按照时隙帧的要求映射或解映射至ODUK时隙帧中，即本实施例所述的第一时隙帧中。
这里，由于业务信息的业务类型不同，使得业务信息对应的业务速率不同，因此，在将业务信息对应的数据映射或解映射至ODUK时隙帧中，也即第一时隙帧中时，要根据所述ODUK时隙帧的结构设置不同数量的填充区域。
步骤103：基于所述第一时隙帧的第一时隙位置，将所述第一时隙帧映射至第一中间帧；所述第一时隙位置能够指示所述第一时隙帧与所述第一中间帧的对应关系；
本实施例中，所述源端Framer芯片在其背板发送侧对ODUK时隙帧，也即第一时隙帧按时隙位置进行交叉调度，也就是说，所述源端Framer芯片在其背板发送侧，依据所述第一时隙帧对应的第一时隙位置，将所述第一时隙帧映射至第一中间帧中；由于所述第一时隙位置与所述第一中间帧对应，又由于所述第一中间帧与所述业务信息对应的目的端芯片地址对应，所以，所述第一时隙帧能够通过所述第一中间帧发送至与所述第一时隙帧 对应的目的端芯片，也即发送至于所述业务信息对应的目的端芯片。
本实施例中，所述第一中间帧的结构与OTN帧结构类相似，是一种用来承载ODUK时隙帧的容器；所以，所述源端Framer芯片能够将不同的ODUK时隙帧分时隙混装入中间帧结构中。
上述方案中，当所述第一中间帧中映射有N个第一时隙帧时，所述N个第一时隙帧中的第一个第一时隙帧、第二个第一时隙帧至第N个第一时隙帧各自对应的第一时隙位置均与所述第一中间帧对应；所述N个第一时隙帧中的第一个第一时隙帧、第二个第一时隙帧至第N个第一时隙帧对应的目的端芯片地址相同；其中，所述N为大于等于2的正整数。
本实施例中，所述源端Framer芯片能够同时或依次接收到不同业务类型的N个业务信息，所述源端Framer芯片能够将所述N个业务信息对应的数据映射或解映射至N个第一时隙帧中，当所述N个第一时隙帧中的每一第一时隙帧对应的第一时隙位置均与所述第一中间帧对应时，所述N个第一时隙帧均映射至第一中间帧中；
也就是说，所述第一中间帧中能够包含有N个第一时隙帧，所述N个第一时隙帧中每一第一时隙帧对应的第一时隙位置均指向所述第一中间帧，也即，所述N个第一时隙帧中的每一第一时隙帧对应的第一时隙位置均与所述第一中间帧对应，因此，所述源端Framer芯片将所述N个第一时隙帧均映射至第一中间帧中。
另外，本实施例中，所述源端Framer芯片还能够同时或依次接收到不同业务类型的K个业务信息，也即第一业务信息、第二业务信息、第i业务信息至第K业务信息；此时，所述源端Framer芯片分别将所述K个业务信息对应的数据映射或解映射至第一时隙帧、第二时隙帧、第i时隙帧至第K时隙帧中；其中，所述K为大于等于2的正整数；所述i为大于等于1小于等于K的正整数；
由于每一时隙帧对应一时隙位置，即第i时隙帧对应第i时隙位置；而且，所述第i时隙位置能够指示所述第i时隙帧与中间帧的对应关系；具体地，所述第一时隙位置对应第一中间帧，第二时隙位置对应第二中间帧，第i时隙位置对应第i中间帧，第K时隙位置对应第K中间帧，所以，所述源端Framer芯片还能够基于第一时隙位置、第二时隙位置、第i时隙位置至第K时隙位置，将所述第一时隙帧、第二时隙帧、第i时隙帧至第K时隙帧对应映射至第一中间帧、第二中间帧、第i中间帧至第K中间帧中。
步骤104：基于所述第一中间帧的第一指示位置，发送所述第一中间帧；所述第一指示位置能够指示所述第一中间帧中第一时隙帧所对应的目的端芯片地址；所述目的端芯片为所述业务信息对应的目的端芯片。
本实施例中，所述源端Framer芯片，在其背板发送侧，能够基于所述第一中间帧的第一指示位置，将所述第一中间帧发送至、与所述第一指示位置对应的目的端芯片中，如此，所述源端Framer芯片，通过所述第一时隙位置、第一指示位置，将携带有所述第一时隙帧的所述第一中间帧发送至于所述第一时隙帧对应的目的端芯片中，实现交叉调度的目的。
本实施例中，所述源端Framer芯片在其背板发送侧，将待发送的中间帧结构统一为帧头信息为第一帧头信息的中间帧后对齐发送；由于所述源端Framer芯片的背板SerDes接口与待发送的中间帧对应的目的端芯片互连，也就是说，通过所述源端Framer芯片的背板SerDes接口，能够将源端Framer芯片与待发送的中间帧对应的目的端芯片互连，进而形成MESH结构，因此，所述源端Framer芯片能够将中间帧发送至目的端芯片，进而为实现交叉调度奠定了基础。
上述方案中，当接收到的业务信息为K个时，所述K为大于等于2的正整数；所述方法还包括：
将K个业务信息对应的数据分别映射或解映射至第一时隙帧、第二时 隙帧、第i时隙帧至第K个时隙帧；所述i为大于等于1小于等于K的正整数；
基于所述第i时隙帧的第i时隙位置，将所述第i时隙帧映射至第i中间帧；所述第i时隙位置能够指示所述第i时隙帧与所述第i中间帧的对应关系；
基于所述第i中间帧的第i指示位置，发送所述第i中间帧；所述第i指示位置能够指示所述第i中间帧中第i时隙帧所对应的第i目的端芯片地址；所述第i目的端芯片为所述K个业务信息中的第i业务信息对应的目的端芯片。
具体地，当接收到的业务信息为K个时，所述K为大于等于2的正整数；所述方法还包括：
将K个业务信息中的第一业务信息、第二业务信息、第i业务信息至第K业务信息对应的数据分别映射或解映射至第一时隙帧、第二时隙帧、第i时隙帧至第K个时隙帧；所述i为大于等于1小于K的正整数；
基于所述第一时隙帧的第一时隙位置、第二时隙帧的第二时隙位置、第i时隙帧的第i时隙位置至第K时隙帧的第K时隙位置，将所述第一时隙帧、第二时隙帧、第i时隙帧至第K个时隙帧对应映射至第一中间帧、第二中间帧、第i中间帧至第K中间帧；所述第一时隙位置能够指示所述第一时隙帧与所述第一中间帧的对应关系；所述第二时隙位置能够指示所述第二时隙帧与所述第二中间帧的对应关系；所述第i时隙位置能够指示所述第i时隙帧与所述第i中间帧的对应关系；所述第K时隙位置能够指示所述第K时隙帧与所述第K中间帧的对应关系；
基于所述第一中间帧的第一指示位置、第二中间帧的第二指示位置、第i中间帧的第i指示位置至第K中间帧的第K指示位置，发送所述第一中间帧、第二中间帧、第i中间帧至第K中间帧；所述第一指示位置能够 指示所述第一中间帧中第一时隙帧所对应的第一目的端芯片地址；所述第二指示位置能够指示所述第二中间帧中第二时隙帧所对应的第二目的端芯片地址；所述第i指示位置能够指示所述第i中间帧中第i时隙帧所对应的第i目的端芯片地址；所述第K指示位置能够指示所述第K中间帧中第K时隙帧所对应的第K目的端芯片地址；所述第一目的端芯片为所述第一业务信息对应的目的端芯片；所述第二目的端芯片为所述第二业务信息对应的目的端芯片；所述第i目的端芯片为所述第i业务信息对应的目的端芯片；所述第K目的端芯片为所述第K业务信息对应的目的端芯片。
上述方案中，所述发送所述第i中间帧，包括：
将所述第i中间帧中的帧头信息替换成第一帧头信息；所述第一帧头信息为第一中间帧、第二中间帧、第i中间帧至第K中间帧中统一的帧头信息；
发送帧头信息为第一帧头信息的所述第i中间帧。
上述方案中，所述发送所述第一中间帧、第二中间帧、第i中间帧至第K中间帧，包括：
将第一中间帧、第二中间帧、第i中间帧至第K中间帧中的帧头信息统一成第一帧头信息；
发送帧头信息统一后的所述第一中间帧、第二中间帧、第i中间帧至第K中间帧。
本实施例中，所述源端Framer芯片发送的所有中间帧的帧头信息为一统一的帧头信息，即第一帧头信息；进一步地，所述源端Framer芯片将待发送的中间帧的帧头信息全部统一为第一帧头信息后，依次发送帧头信息统一为第一帧头信息的中间帧；
这里，当所述源端Framer芯片待发送的中间帧的帧头信息为第一帧头信息时，直接发送帧头信息为第一帧头信息的中间帧；
当所述源端Framer芯片待发送的中间帧的帧头信息不为第一帧头信息时，将待发送的中间帧的帧头信息替换为所述第一帧头信息，随后，将帧头信息为所述第一帧头信息的中间帧发送。
本发明实施例还提出一种第一计算机可读存储介质，该存储介质包括一组指令，所述指令用于实施例一所述的交叉调度方法。
为实现上述方法，本发明实施例还提供了一种交叉调度装置，如图2所示，所述装置包括：
第一接收单元21，配置为接收业务信息；
第一映射单元22，配置为将业务信息对应的数据映射或解映射至第一时隙帧；
第二映射单元23，配置为基于所述第一时隙帧的第一时隙位置，将所述第一时隙帧映射至第一中间帧；所述第一时隙位置能够指示所述第一时隙帧与所述第一中间帧的对应关系；
第一发送单元24，配置为基于所述第一中间帧的第一指示位置，发送所述第一中间帧；所述第一指示位置能够指示所述第一中间帧中第一时隙帧所对应的目的端芯片地址；所述目的端芯片为所述业务信息对应的目的端芯片。
上述方案中，当所述第一中间帧中映射有N个第一时隙帧时，所述N个第一时隙帧中的第一个第一时隙帧、第二个第一时隙帧至第N个第一时隙帧各自对应的第一时隙位置均与所述第一中间帧对应；所述N个第一时隙帧中的第一个第一时隙帧、第二个第一时隙帧至第N个第一时隙帧对应的目的端芯片地址相同；其中，所述N为大于等于2的正整数。
上述方案中，当接收到的业务信息为K个时，所述K为大于等于2的正整数；对应地，
所述第一接收单元21，还配置为接收K个业务信息；
所述第一映射单元22，还配置为将K个业务信息对应的数据分别映射或解映射至第一时隙帧、第二时隙帧、第i时隙帧至第K个时隙帧；所述i为大于等于1小于等于K的正整数；
所述第二映射单元23，还配置为基于所述第i时隙帧的第i时隙位置，将所述第i时隙帧映射至第i中间帧；所述第i时隙位置能够指示所述第i时隙帧与所述第i中间帧的对应关系；
所述第一发送单元24，还配置为基于所述第i中间帧的第i指示位置，发送所述第i中间帧；所述第i指示位置能够指示所述第i中间帧中第i时隙帧所对应的第i目的端芯片地址；所述第i目的端芯片为所述K个业务信息中的第i业务信息对应的目的端芯片。
上述方案中，所述第一发送单元24，还配置为将所述第i中间帧中的帧头信息替换成第一帧头信息；所述第一帧头信息为第一中间帧、第二中间帧、第i中间帧至第K中间帧中统一的帧头信息；
还配置为发送帧头信息为第一帧头信息的所述第i中间帧。
本实施例中，所述第一接收单元21、第一映射单元22、第二映射单元23以及第一发送单元24均可以运行于源端芯片中，可由位于源端芯片中的中央处理器(CPU)、或微处理器(MPU)、或数字信号处理器(DSP)、或可编程门阵列(FPGA)实现。
本发明实施例所述的交叉调度方法及其装置、存储介质，能够通过MESH结构的ODUK交叉调度方法，实现Framer芯片互连的、低成本ODUK小容量交叉调度目的；而且，本发明实施例所述的交叉调度方法及其装置，不同于集群式交叉调度方法及***，也就是说，本发明实施例无需专门的交叉芯片，只需源端Framer芯片与目的端Framer芯片的互连，就能实现交叉调度过程，因此，本发明实施例能够降低调度成本、降低能耗；
另外，由于本发明实施例低成本，低能耗，因此，还能应用于边缘接 入汇聚节点的交叉调度的过程中。
实施例二
图3为本发明实施例交叉调度方法的实现流程示意图二；所述方法应用于目的端芯片；如图3所示，所述方法包括：
步骤301：接收第一中间帧；
本实施例中，所述目的端芯片可以采用Framer芯片，即目的端Framer芯片；进一步地，所述目的端Framer芯片，在其背板接收侧接第一中间帧。
步骤302：将所述第一中间帧解映射至第一时隙帧；
本实施例中，当所述目的端Framer芯片，在其背板接收侧接到所述第一中间帧后，所述目的端Framer芯片按照所述第一中间帧对应的源端Framer芯片对所述第一中间帧进行区分处理，待区分处理后将所述第一中间帧解映射至ODUK，并进一步解映射至第一时隙帧，也即第一ODUK时隙帧。
另外，本实施例中，当所述目的端Framer芯片在其背板侧接收到来自多个源端Framer芯片的多个中间帧时，具体地，
所述目的端Framer芯片在其背板侧接收到第一中间帧、第二中间帧、第j中间帧至第M中间帧后，所述目的端Framer芯片按照所述第一中间帧、第二中间帧、第j中间帧至第M中间帧各自对应的源端Framer芯片对所述第一中间帧、第二中间帧、第j中间帧至第M中间帧进行区分和帧头信息对齐处理，待区分和帧头信息对齐处理后，将帧头信息对齐后的所述第一中间帧、第二中间帧、第j中间帧至第M中间帧分别解映射至第一时隙帧、第二时隙帧、第j时隙帧至第M时隙帧；所述j为大于等于1小于等于M的正整数；所述M为大于等于2的正整数。
步骤303：基于所述第一时隙帧的第一时隙位置，将所述第一时隙帧映射或解映射至业务信息；所述第一时隙位置能够指示所述第一时隙帧与所 述业务信息的对应关系；
本实施例中，当所述目的端Framer芯片在其背板侧接收到来自多个源端Framer芯片的M个中间帧，且所述目的端Framer芯片将所述M个中间帧中的第一中间帧、第二中间帧、第j中间帧至第M中间帧分别解映射至第一时隙帧、第二时隙帧、第j时隙帧至第M时隙帧后，
所述目的端Framer芯片基于所述第一时隙帧的第一时隙位置、所述第二时隙帧的第二时隙位置、所述第j时隙帧的第j时隙位置至所述第M时隙帧的第M时隙位置，将所述第一时隙帧、第二时隙帧、第j时隙帧至第M时隙帧映射或解映射至第一业务信息、第二业务信息、第j业务信息至第M业务信息；
其中，所述第一时隙位置能够指示所述第一时隙帧与所述第一业务信息的对应关系；所述第二时隙位置能够指示所述第二时隙帧与所述第二业务信息的对应关系；所述第j时隙位置能够指示所述第j时隙帧与所述第j业务信息的对应关系；所述第M时隙位置能够指示所述第M时隙帧与所述第M业务信息的对应关系；如此，所述目的端Framer芯片将接收到的来自多个源端Framer芯片的M个中间帧解映射至M个业务信息。
步骤304：发送所述业务信息。
本实施例中，所述目的端Framer芯片在其客户发送侧将所述业务信息发送出去。所述业务信息可以为OTN业务信息、或者以太网业务信息等。
本实施例中，当所述目的端Framer芯片在其背板侧接收到来自多个源端Framer芯片的M个中间帧，且所述目的端Framer芯片将所述M个中间帧解映射至M个业务信息后，所述目的端Framer芯片发送所述M个业务信息。
本实施例中，所述目的端Framer芯片，在其背板接收侧对解映射后的ODUK时隙帧也即第一时隙帧按时隙位置进行调度，具体地，当所述目的 端Framer芯片在其背板接收侧将接收到来自多个源端Framer芯片的M个中间帧解映射至M个时隙帧，即第一时隙帧、第二时隙帧、第j时隙帧至第M时隙帧后，所述目的端Framer芯片在其背板接收侧能够基于所述第一时隙帧的第一时隙位置、所述第二时隙帧的第二时隙位置、所述第j时隙帧的第j时隙位置至所述第M时隙帧的第M时隙位置对所述M个时隙帧进行调度；进一步地，时隙位置与所述目的端Framer芯片的客户发送侧相对应，也就是说，该时隙位置能够指示时隙帧、与业务信息的对应关系，如此，所述目的端Framer芯片能够基于该时隙位置，将时隙帧发送至与该时隙位置对应的客户侧；
具体地，所述目的端Framer芯片能够基于所述第一时隙帧的第一时隙位置、所述第二时隙帧的第二时隙位置、所述第j时隙帧的第j时隙位置至所述第M时隙帧的第M时隙位置，发送所述第一业务信息、第二业务信息、第j业务信息至第M业务信息。
本发明实施例还提出一种第二计算机可读存储介质，该存储介质包括一组指令，所述指令用于实施例二所述的交叉调度方法。
为实现以上所述的方法，本发明实施例还提供了一种交叉调度装置，如图4所示，所述装置包括：
第二接收单元41，配置为接收第一中间帧；
第一解映射单元42，配置为将所述第一中间帧解映射至第一时隙帧；
第二解映射单元43，配置为基于所述第一时隙帧的第一时隙位置，将所述第一时隙帧映射或解映射至业务信息；所述第一时隙位置能够指示所述第一时隙帧与所述业务信息的对应关系；
第二发送单元44，配置为发送所述业务信息。
本实施例中，所述第二接收单元41、第一解映射单元42、第二解映射单元43以及第二发送单元44均可以运行于目的端芯片中，可由位于目的 端芯片中的中央处理器(CPU)、或微处理器(MPU)、或数字信号处理器(DSP)、或可编程门阵列(FPGA)实现。
实施例三
图5为本发明实施例交叉调度方法的具体实现的流程示意图一；所述方法应用于源端Framer芯片；如图5所示，所述方法包括：
步骤501：源端Framer芯片在其客户侧接收K个业务信息，对所述K个业务信息对应的数据进行映射或解映射至K个ODUK时隙帧，也即第一时隙帧、第二时隙帧、第i时隙帧至第K时隙帧；所述K为大于等于2的正整数；所述i为大于等于1小于等于K的正整数；
本实施例中，所述源端Framer芯片在其客户侧接收的业务信息为OTN业务信息和/或以太网业务信息等；
当所述源端Framer芯片在其客户侧接收到OTN业务信息时，所述源端Framer芯片将所述OTN业务信息对应的数据解映射至ODUK时隙帧；
当所述源端Framer芯片在其客户侧接收到以太网业务信息时，所述源端Framer芯片根据所述以太网业务信息的速率等级，通过比特同步映射(BMP)、异步映射(AMP)或通用映射(GMP)等机制，将所述以太网业务信息对应的数据映射至相应的ODUK时隙帧；
本实施例中，对于速率恒定的以太网业务信息，通常采用BMP方法直接将所述以太网业务信息对应的数据直接映射至于与其速率对应的ODUK时隙帧中；
对于速率与ODUK的速率不对应的以太网业务信息，也即所述以太网业务信息的速率相对于ODUK的速率有一定余量的业务，通常采用AMP方法将所述以太网业务信息对应的数据映射至ODUK时隙帧中；映射时，在ODUk时隙帧的NJO字段和PJO字段中选择性的填充数据字节或调整字节；
对于低速率的以太网业务信息向高速率的ODUK时隙帧映射时，通常采用GMP方法，所述GMP方法采用sigma/delta法则，如此，通过所述sigma/delta法则将映射方与被映射方的速率匹配，使所述以太网信息对应的业务信号均匀分布在ODUK时隙帧的净荷中。
本实施例中，所述源端Framer芯片在其客户侧接收到业务信息后，经过映射或解映射至ODUK时隙帧中；这里，一个高速的ODUK时隙帧的结构中可以占有多个ODUK时隙；各个ODUK时隙对应的数据经过位宽能够转换至大小统一的时隙，例如转换成8bit的时隙；然后，多个ODUK时隙的总线汇聚成至ODUK空分总线，在所述ODUK空分总线上每8bit为一单位，也即为一ODUK时隙；这里，速率较高的业务信息可以占用多个8bit的单位。
步骤502：所述源端Framer芯片在其背板发送侧，基于所述第一时隙帧的第一时隙位置、第二时隙帧的第二时隙位置、第i时隙帧的第i时隙位置至第K时隙帧的第K时隙位置，将所述第一时隙帧、第二时隙帧、第i时隙帧至第K个时隙帧对应映射至第一中间帧、第二中间帧、第i中间帧至第K中间帧；
其中，所述第一时隙位置能够指示所述第一时隙帧与所述第一中间帧的对应关系；所述第二时隙位置能够指示所述第二时隙帧与所述第二中间帧的对应关系；所述第i时隙位置能够指示所述第i时隙帧与所述第i中间帧的对应关系；所述第K时隙位置能够指示所述第K时隙帧与所述第K中间帧的对应关系；如图7所述，基于第一时隙位置、第二时隙位置、第i时隙位置至第K时隙位置，将所述第一时隙帧、第二时隙帧、第i时隙帧至第K个时隙帧对应映射至第一中间帧、第二中间帧、第i中间帧至第K中间帧。
本实施例中，所述源端Framer芯片在其背板发送侧将ODUK时隙帧按位置区分映射到中间帧结构中；也即，所述源端Framer芯片在其背板发送侧，基于所述第一时隙帧的第一时隙位置、第二时隙帧的第二时隙位置、第i时隙帧的第i时隙位置至第K时隙帧的第K时隙位置，将所述第一时隙帧、第二时隙帧、第i时隙帧至第K个时隙帧对应映射至第一中间帧、第二中间帧、第i中间帧至第K中间帧；进而，根据所述第i中间帧的第i指示位置，将所述第i中间帧发送出去；由于所述源端Framer芯片能够同时将所述K个中间帧，基于所述K个中间帧各自对应的指示位置发送出去，因此，所述源端Framer芯片的背板发送侧能够对ODUK时隙帧按时隙位置进行交叉调度。
这里，中间帧结构与G.709协议中定义的OTU帧结构相似，是一种用来承载ODUK时隙帧的容器。而且，本发实施例能够采用GMP机制，将不同的时隙帧分时隙混装入一个中间帧结构中。
步骤503：基于所述第一中间帧的第一指示位置、第二中间帧的第二指示位置、第i中间帧的第i指示位置至第K中间帧的第K指示位置，发送所述第一中间帧、第二中间帧、第i中间帧至第K中间帧；
其中，所述第一指示位置能够指示所述第一中间帧中第一时隙帧所对应的第一目的端芯片地址；所述第二指示位置能够指示所述第二中间帧中第二时隙帧所对应的第二目的端芯片地址；所述第i指示位置能够指示所述第i中间帧中第i时隙帧所对应的第i目的端芯片地址；所述第K指示位置能够指示所述第K中间帧中第K时隙帧所对应的第K目的端芯片地址；所述第一目的端芯片为所述第一业务信息对应的目的端芯片；所述第二目的端芯片为所述第二业务信息对应的目的端芯片；所述第i目的端芯片为所述第i业务信息对应的目的端芯片；所述第K目的端芯片为所述第K业务信息对应的目的端芯片。
本实施例中，所述源端Framer芯片在其背板发送侧将第一中间帧、第二中间帧、第i中间帧至第K中间帧中的帧头信息统一成第一帧头信息，并将帧头信息对齐后发送所述第一中间帧、第二中间帧、第i中间帧至第K中间帧；
本发明实施例中，各中间帧的结构中使用统一的帧头信息，并将帧头信息对齐后发送；由于所述源端Framer芯片其背板SerDes与目的端的Framer芯片互连，因此，本实施例能够将各中间帧发送至目的端Framer芯片。
这里，在MESH组网结构下，Framer芯片的个数受其背板侧SerDes链路数约束；例如，需要保证一个Framer芯片对其它各个Framer芯片都有SerDes链接；两个Framer芯片之间的交叉带宽由它们之间互边的SerDes的数量和速率确定。
图6为本发明实施例交叉调度方法的具体实现的流程示意图二；所述方法应用于目的端Framer芯片；如图6所示，所述方法包括：
步骤601：目的端Framer芯片在其背板接收侧接收来自多个源端Framer芯片的M个中间帧；
本实施例中，所述目的端Framer芯片按源端Framer芯片对所述M个中间帧进行区分，并将来自同一个源端Framer芯片的各路中间帧结构中的帧头信息对齐；
步骤602：所述目的端Framer芯片在其背板接收侧对所述M个中间帧进行解映射，并解映射至M个ODUK时隙帧，也即第一时隙帧、第二时隙帧、第j时隙帧至第M时隙帧；
本实施例中，所述目的端Framer芯片在其背板接收侧将解映射后的M个ODUK时隙帧中每一个ODUK时隙对应的数据经过位宽转换至统一大小，例如转换成8bit，随后，将多个ODUK时隙的总线汇聚成至ODUK空 分总线，以8bit为单位区分时隙位置，使所述时隙位置能够时隙帧与业务信息的对应关系，进而与目的端Framer的客户发送侧相对应。
步骤603：所述目的端Framer芯片在其客户发送侧将第一时隙帧、第二时隙帧、第j时隙帧至第M时隙帧对应映射或解映射至各种M个业务信息，并从客户发送侧将发送所述M个业务信息。
这里，业务信息包括OTN业务信息，或以太网业务信息等。
本领域内的技术人员应明白，本发明的实施例可提供为方法、***、或计算机程序产品。因此，本发明可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(***)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机 实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
以上所述仅是本发明实施例的实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明实施例原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本发明实施例的保护范围。
工业实用性
本发明实施例能够将接收到的业务信息对应的数据映射或解映射至第一时隙帧；并基于所述第一时隙帧的第一时隙位置，将所述第一时隙帧映射至第一中间帧；进而基于所述第一中间帧的第一指示位置，将所述第一中间帧发送至与所述业务信息对应的目的端芯片，如此，实现交叉调度的目的。另外，由于本发明实施例无需使用交叉芯片，就能实现交叉调度的目的，因此，本发明实施例能够降低调度成本、降低能耗。

Claims (12)

  1. 一种交叉调度方法，应用于源端芯片；所述方法包括：
    接收业务信息；
    将业务信息对应的数据映射或解映射至第一时隙帧；
    基于所述第一时隙帧的第一时隙位置，将所述第一时隙帧映射至第一中间帧；所述第一时隙位置能够指示所述第一时隙帧与所述第一中间帧的对应关系；
    基于所述第一中间帧的第一指示位置，发送所述第一中间帧；所述第一指示位置能够指示所述第一中间帧中第一时隙帧所对应的目的端芯片地址；所述目的端芯片为所述业务信息对应的目的端芯片。
  2. 根据权利要求1所述的方法，其中，当所述第一中间帧中映射有N个第一时隙帧时，所述N个第一时隙帧中的第一个第一时隙帧、第二个第一时隙帧至第N个第一时隙帧各自对应的第一时隙位置均与所述第一中间帧对应；所述N个第一时隙帧中的第一个第一时隙帧、第二个第一时隙帧至第N个第一时隙帧对应的目的端芯片地址相同；其中，所述N为大于等于2的正整数。
  3. 根据权利要求1所述的方法，其中，当接收到的业务信息为K个时，所述K为大于等于2的正整数；所述方法还包括：
    将K个业务信息对应的数据分别映射或解映射至第一时隙帧、第二时隙帧、第i时隙帧至第K个时隙帧；所述i为大于等于1小于等于K的正整数；
    基于所述第i时隙帧的第i时隙位置，将所述第i时隙帧映射至第i中间帧；所述第i时隙位置能够指示所述第i时隙帧与所述第i中间帧的对应关系；
    基于所述第i中间帧的第i指示位置，发送所述第i中间帧；所述第i指示位置能够指示所述第i中间帧中第i时隙帧所对应的第i目的端芯片地址；所述第i目的端芯片为所述K个业务信息中的第i业务信息对应的目的端芯片。
  4. 根据权利要求3所述的方法，其中，所述发送所述第i中间帧，包括：
    将所述第i中间帧中的帧头信息替换成第一帧头信息；所述第一帧头信息为第一中间帧、第二中间帧、第i中间帧至第K中间帧中统一的帧头信息；
    发送帧头信息为第一帧头信息的所述第i中间帧。
  5. 一种交叉调度方法，所述方法应用于目的端芯片；所述方法包括：
    接收第一中间帧；
    将所述第一中间帧解映射至第一时隙帧；
    基于所述第一时隙帧的第一时隙位置，将所述第一时隙帧映射或解映射至业务信息；所述第一时隙位置能够指示所述第一时隙帧与所述业务信息的对应关系；
    发送所述业务信息。
  6. 一种交叉调度装置，所述装置包括：
    第一接收单元，配置为接收业务信息；
    第一映射单元，配置为将业务信息对应的数据映射或解映射至第一时隙帧；
    第二映射单元，配置为基于所述第一时隙帧的第一时隙位置，将所述第一时隙帧映射至第一中间帧；所述第一时隙位置能够指示所述第一时隙帧与所述第一中间帧的对应关系；
    第一发送单元，配置为基于所述第一中间帧的第一指示位置，发送所 述第一中间帧；所述第一指示位置能够指示所述第一中间帧中第一时隙帧所对应的目的端芯片地址；所述目的端芯片为所述业务信息对应的目的端芯片。
  7. 根据权利要求6所述的装置，其中，当所述第一中间帧中映射有N个第一时隙帧时，所述N个第一时隙帧中的第一个第一时隙帧、第二个第一时隙帧至第N个第一时隙帧各自对应的第一时隙位置均与所述第一中间帧对应；所述N个第一时隙帧中的第一个第一时隙帧、第二个第一时隙帧至第N个第一时隙帧对应的目的端芯片地址相同；其中，所述N为大于等于2的正整数。
  8. 根据权利要求1所述的装置，其中，当接收到的业务信息为K个时，所述K为大于等于2的正整数；对应地，
    所述第一接收单元，还配置为接收K个业务信息；
    所述第一映射单元，还配置为将K个业务信息对应的数据分别映射或解映射至第一时隙帧、第二时隙帧、第i时隙帧至第K个时隙帧；所述i为大于等于1小于等于K的正整数；
    所述第二映射单元，还配置为基于所述第i时隙帧的第i时隙位置，将所述第i时隙帧映射至第i中间帧；所述第i时隙位置能够指示所述第i时隙帧与所述第i中间帧的对应关系；
    所述第一发送单元，还配置为基于所述第i中间帧的第i指示位置，发送所述第i中间帧；所述第i指示位置能够指示所述第i中间帧中第i时隙帧所对应的第i目的端芯片地址；所述第i目的端芯片为所述K个业务信息中的第i业务信息对应的目的端芯片。
  9. 根据权利要求8所述的装置，其中，所述第一发送单元，还配置为将所述第i中间帧中的帧头信息替换成第一帧头信息；所述第一帧头信息为第一中间帧、第二中间帧、第i中间帧至第K中间帧中统一的帧头信息；
    还配置为发送帧头信息为第一帧头信息的所述第i中间帧。
  10. 一种交叉调度装置，所述装置包括：
    第二接收单元，配置为接收第一中间帧；
    第一解映射单元，配置为将所述第一中间帧解映射至第一时隙帧；
    第二解映射单元，配置为基于所述第一时隙帧的第一时隙位置，将所述第一时隙帧映射或解映射至业务信息；所述第一时隙位置能够指示所述第一时隙帧与所述业务信息的对应关系；
    第二发送单元，配置为发送所述业务信息。
  11. 一种第一计算机可读存储介质，该存储介质包括一组指令，所述指令用于执行权利要求1至4任一项所述的交叉调度方法。
  12. 一种第二计算机可读存储介质，该存储介质包括一组指令，所述指令用于执行权利要求5所述的交叉调度方法。
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