WO2016101299A1 - 一种液晶显示面板的源极驱动电路及液晶显示器 - Google Patents

一种液晶显示面板的源极驱动电路及液晶显示器 Download PDF

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Publication number
WO2016101299A1
WO2016101299A1 PCT/CN2014/095476 CN2014095476W WO2016101299A1 WO 2016101299 A1 WO2016101299 A1 WO 2016101299A1 CN 2014095476 W CN2014095476 W CN 2014095476W WO 2016101299 A1 WO2016101299 A1 WO 2016101299A1
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Prior art keywords
data line
switching element
buffer amplifier
analog buffer
liquid crystal
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PCT/CN2014/095476
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English (en)
French (fr)
Inventor
秦杰辉
国春朋
卢宇程
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深圳市华星光电技术有限公司
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Publication of WO2016101299A1 publication Critical patent/WO2016101299A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present invention relates to the field of displays, and in particular to a source driving circuit and a liquid crystal display of a liquid crystal display panel.
  • the liquid crystal display panel includes an array substrate, as described in FIG. 1, wherein the array substrate includes a data line 12, a scan line 11, and a plurality of pixel units 13 defined by the data line 12 and the scan line 11;
  • the source driving circuit in the display panel comprises a plurality of analog-to-digital converters 14, a plurality of analog buffer amplifiers 15, each of which is provided with an analog-to-digital converter 14 and an analog buffer amplifier 15, and the analog-to-digital converter 14 signals
  • the analog input signal of the source input is converted into a digital signal; after the digital signal is amplified by the analog buffer amplifier 15, the digital signal after the amplification operation is transmitted to the corresponding data line to drive the pixel array of the liquid crystal display panel.
  • the pixel array requires a large range of charging voltage (i.e., pixel voltage), and black indicates that the pixel unit voltage is positive, gray. It means that the voltage of the pixel unit is negative, which causes the power consumption of the source driving circuit to be large, which causes the heat of the analog buffer amplifier to be severe and the loss to increase.
  • Embodiments of the present invention provide a source driving circuit of a liquid crystal display panel, wherein the liquid crystal display panel includes an array substrate, the array substrate includes a data line, a scan line, and a defined by the data line and the scan line Multiple pixel units;
  • the source driving circuit includes a plurality of source driving units, and each of the data lines is correspondingly provided with the source driving unit;
  • the source driving unit includes:
  • An analog to digital converter for converting an analog signal input from a signal source into a digital signal
  • An analog buffer amplifier group including a first analog buffer amplifier and a second analog buffer amplifier; the analog buffer amplifier group for amplifying a digital signal of the analog to digital converter and amplifying the data after the operation Signal transmission to the corresponding data line;
  • the selection signal Controlling, by the selection signal, the first analog buffer amplifier and the second analog buffer amplifier to alternately drive a plurality of rows of pixel units on the data line in units of rows; the selection signal is generated according to a clock signal;
  • the source driving unit further includes: a first switching element and a second switching element;
  • the first analog buffer amplifier is connected to the data line through the first switching element, and the second analog buffer amplifier is connected to the data line through a second switching element;
  • the selection signal controls whether the first analog buffer element and the second switching element are connected to the data line to control the first analog buffer amplifier and the second analog buffer amplifier to alternately drive in units of rows A plurality of rows of pixel units on the data line.
  • the first switching element when the selection signal is at a high level, the first switching element is connected to the data line, and the second switching element is disconnected from the data line .
  • the first switching element when the selection signal is at a low level, the first switching element is disconnected from the data line, and the second switching element is connected to the data line .
  • the first switching element is an N-type metal oxide semiconductor field effect transistor
  • the second switching element is a P-type metal oxide semiconductor field effect transistor
  • the first switching element includes a first gate, a first source, and a first drain;
  • the second switching element includes a second gate, a second source, and a second drain;
  • the first gate and the second gate are connected to the selection signal, the first source is connected to the data line, and the first drain is connected to an output end of the first analog buffer amplifier;
  • the second source is coupled to the data line, and the second drain is coupled to an output of the second analog buffer amplifier.
  • Embodiments of the present invention provide a source driving circuit of a liquid crystal display panel, wherein the liquid crystal display panel includes an array substrate, the array substrate includes a data line, a scan line, and a defined by the data line and the scan line Multiple pixel units;
  • the source driving circuit includes a plurality of source driving units, and each of the data lines is correspondingly provided with the source driving unit;
  • the source driving unit includes:
  • An analog to digital converter for converting an analog signal input by a signal source into a digital signal
  • An analog buffer amplifier group including a first analog buffer amplifier and a second analog buffer amplifier; the analog buffer amplifier group for amplifying a digital signal of the analog to digital converter and amplifying the data after the operation Signal transmission to the corresponding data line;
  • the first analog buffer amplifier and the second analog buffer amplifier are controlled to alternately drive a plurality of rows of pixel units on the data line in units of rows according to a selection signal.
  • the source driving unit further includes: a first switching element and a second switching element;
  • the first analog buffer amplifier is connected to the data line through the first switching element, and the second analog buffer amplifier is connected to the data line through a second switching element;
  • the selection signal controls whether the first analog buffer element and the second switching element are connected to the data line to control the first analog buffer amplifier and the second analog buffer amplifier to alternately drive in units of rows A plurality of rows of pixel units on the data line.
  • the first switching element when the selection signal is at a high level, the first switching element is connected to the data line, and the second switching element is disconnected from the data line .
  • the first switching element when the selection signal is at a low level, the first switching element is disconnected from the data line, and the second switching element is connected to the data line .
  • the first switching element is an N-type metal oxide semiconductor field effect transistor
  • the second switching element is a P-type metal oxide semiconductor field effect transistor
  • the first switching element includes a first gate, a first source, and a first drain;
  • the second switching element includes a second gate, a second source, and a second drain;
  • the first gate and the second gate are connected to the selection signal, the first source is connected to the data line, and the first drain is connected to an output end of the first analog buffer amplifier;
  • the second source is coupled to the data line, and the second drain is coupled to an output of the second analog buffer amplifier.
  • the selection signal is generated based on a clock signal.
  • An embodiment of the present invention further provides a liquid crystal display, including: a liquid crystal display panel, the liquid crystal display panel includes an array substrate, the array substrate includes a data line, a scan line, and is defined by the data line and the scan line Multiple pixel units;
  • the source driving circuit includes a plurality of source driving units, and each of the data lines is correspondingly provided with the source driving unit;
  • the source driving unit includes:
  • An analog to digital converter for converting an analog signal input by a signal source into a digital signal
  • An analog buffer amplifier group including a first analog buffer amplifier and a second analog buffer amplifier, the analog buffer amplifier group for amplifying a digital signal of the analog to digital converter, and amplifying the data after the operation Signal transmission to the corresponding data line;
  • the first analog buffer amplifier and the second analog buffer amplifier are controlled to alternately drive a plurality of rows of pixel units on the data line in units of rows according to a selection signal.
  • the source driving unit further includes: a first switching element and a second switching element;
  • the first analog buffer amplifier is connected to the data line through the first switching element, and the second analog buffer amplifier is connected to the data line through a second switching element;
  • the selection signal controls whether the first analog buffer element and the second switching element are connected to the data line to control the first analog buffer amplifier and the second analog buffer amplifier to alternately drive in units of rows A plurality of rows of pixel units on the data line.
  • the first switching element when the selection signal is at a high level, the first switching element is connected to the data line, and the second switching element is disconnected from the data line;
  • the first switching element When the selection signal is low, the first switching element is disconnected from the data line, and the second switching element is connected to the data line.
  • the first switching element is an N-type metal oxide semiconductor field effect transistor
  • the second switching element is a P-type metal oxide semiconductor field effect transistor
  • the first switching element includes a first gate, a first source, and a first drain;
  • the second switching element includes a second gate, a second source, and a second drain;
  • the first gate and the second gate are connected to the selection signal, the first source is connected to the data line, and the first drain is connected to an output end of the first analog buffer amplifier;
  • the second source is coupled to the data line, and the second drain is coupled to an output of the second analog buffer amplifier.
  • the selection signal is generated based on a clock signal.
  • the source driving circuit and the liquid crystal display of the liquid crystal display panel of the present invention reduce the power consumption of a single analog buffer amplifier by adding an analog buffer amplifier to each data line, thereby reducing power consumption.
  • FIG. 1 is a schematic structural view of a first array substrate of the prior art
  • FIG. 2 is a schematic structural view of a second array substrate of the prior art
  • FIG. 3 is a schematic structural view of a first array substrate of the present invention.
  • FIG. 4 is a schematic enlarged view of the source driving unit of FIG. 3;
  • FIG. 5 is a schematic structural view of a second array substrate of the present invention.
  • Figure 6 is a timing diagram of the selection signal of the present invention.
  • FIG. 3 is a schematic structural diagram of a first array substrate of the present invention.
  • the liquid crystal display panel of the present invention comprises: a color film substrate, an array substrate, and a liquid crystal layer between the color film substrate and the array substrate, wherein the array substrate comprises a data line 22, as described in FIG. a scan line 21, and a plurality of pixel units 23 defined by the data line 22 and the scan line 21; the array substrate further includes a source drive circuit 24;
  • the source driving circuit 24 includes a plurality of source driving units 25, each of the data lines corresponding to the source driving unit 25;
  • the source driving unit 25 includes: an analog-to-digital converter 26 and an analog buffer amplifier group 27.
  • the signal source inputs a video signal to the liquid crystal display panel, the video signal is an analog signal, and the analog-to-digital converter Converting a video signal input by the signal source into a digital signal; then the analog buffer amplifier group 27 amplifies the digital signal obtained by the analog-to-digital converter (such as a load driving capability of amplifying the digital signal, Driving the pixel array load on the data line, and transmitting the data signal after the amplification operation to the corresponding data line;
  • the analog buffer amplifier group 27 amplifies the digital signal obtained by the analog-to-digital converter (such as a load driving capability of amplifying the digital signal, Driving the pixel array load on the data line, and transmitting the data signal after the amplification operation to the corresponding data line;
  • the analog buffer amplifier group 27 includes a first analog buffer amplifier 28 and a second analog buffer amplifier 29;
  • the array substrate is further provided with a selection signal input line 30 for providing a selection signal, and the source driving circuit of the present invention can control the first analog buffer amplifier 28 according to the selection signal input by the selection signal input line 30.
  • the second analog buffer amplifier 29 alternately drives a plurality of rows of pixel units on the data line in units of rows.
  • the first analog buffer amplifier is separately operated, that is, the digital signal corresponding to the first row of pixel units on the first data line is processed to The first row of pixel units on the data line is driven to display the pixel unit, and then the second analog buffer amplifier is separately operated, that is, the digital signal corresponding to the second row of pixel units on the first data line.
  • the source driving unit 25 further includes: a first switching element 31 and a second switching element 32; the first analog buffer amplifier 28 can be connected to the data line through the first switching element 31, The second analog buffer amplifier 29 can be connected to the data line through the second switching element 32;
  • the selection signal controls whether the first analog buffer element and the second switching element are connected to the data line to control the first analog buffer amplifier and the second analog buffer amplifier to alternately drive in units of rows A plurality of rows of pixel units on the data line. Specifically, when the selection signal is at a high level, the first switching element 31 is connected to the data line, the second switching element 32 is disconnected from the data line; when the selection signal is low level The first switching element 31 is disconnected from the data line, and the second switching element 32 is connected to the data line.
  • the first switching element 31 may be an N-type MOS transistor (metal oxide semiconductor field effect transistor), the second switching element 32 may be a P-type MOS transistor, and the first switching element 31 includes a first gate, a first source, a first drain; the second switching element 32 includes a second gate, a second source, and a second drain;
  • N-type MOS transistor metal oxide semiconductor field effect transistor
  • P-type MOS transistor metal oxide semiconductor field effect transistor
  • the first gate and the second gate are connected to the selection signal, the first source is connected to the data line, and the first drain is connected to an output end of the first analog buffer amplifier 28;
  • the second source is connected to the data line, and the second drain is connected to an output of the second analog buffer amplifier 29.
  • the selection signal is generated based on a clock signal.
  • the selection signal can be provided by a timing controller on the liquid crystal display panel, and the waveform thereof is as shown in FIG. 6.
  • the timing controller provides a clock signal, and the timing chart of the clock signal Clock is shown in FIG. 6, and the scan signal input on the scan line is also based on A clock signal is generated, the selection signal Select being generated with reference to the clock signal, preferably generated from the scan signal.
  • the selection signal is high, such that the first switch is closed, the second switch is off, the first analog buffer amplifier is operating, and the second analog buffer is The amplifier does not operate, the first analog buffer amplifier transmits the data signal after the amplification operation to the first row of pixel units on the data line corresponding thereto; between time t2-t3, the selection signal is low Leveling, causing the second switch to be closed, the first switch to be turned off, the second analog buffer amplifier to operate, the first analog buffer amplifier not operating, ie, the second analog buffer amplifier to be amplified
  • the subsequent data signal is transmitted to the second row of pixel units on the data line corresponding thereto, and between time t3-t4, the selection signal is at a high level, so that the first switch is closed, the second The switch is turned off, the first analog buffer amplifier operates, the second analog buffer amplifier does not operate, and the first analog buffer amplifier transmits the data signal after the amplification operation to the corresponding a third row of pixel units on the data line; between times t1-t2, the
  • the input signal on the data line of the present invention is alternately output by two buffer amplifiers, that is, alternately outputted alternately, which lowers the temperature of each amplifier and reduces power consumption in the case of line inversion and dot inversion. .
  • FIG. 3 shows a schematic diagram of row inversion of the pixel array
  • FIG. 5 shows a schematic diagram of dot inversion of the pixel array.
  • the present invention ensures the normal operation of the liquid crystal display panel, and In the prior art, only one analog buffer amplifier comparison is set, and the operating time of the analog buffer amplifier is reduced by half, so that the temperature of each analog buffer amplifier is greatly reduced, and the power consumption is reduced.
  • the source driving circuit of the liquid crystal display panel of the present invention reduces the power consumption of a single analog buffer amplifier by adding an analog buffer amplifier to each data line, thereby reducing power consumption.
  • the present invention also provides a liquid crystal display comprising a liquid crystal display panel and a backlight module, the liquid crystal display panel comprising an array substrate, the array substrate comprising a data line, a scan line, and a defined by the data line and the scan line Multiple pixel units;
  • the source driving circuit includes a plurality of source driving units, and each of the data lines is correspondingly provided with the source driving unit;
  • the source driving unit includes:
  • An analog to digital converter for converting an analog signal input by a signal source into a digital signal
  • An analog buffer amplifier group including a first analog buffer amplifier and a second analog buffer amplifier, the analog buffer amplifier group for amplifying a digital signal of the analog to digital converter, and amplifying the data after the operation Signal transmission to the corresponding data line;
  • the first analog buffer amplifier and the second analog buffer amplifier are controlled to alternately drive a plurality of rows of pixel units on the data line in units of rows according to a selection signal.
  • the source driving unit further includes: a first switching element and a second switching element;
  • the first analog buffer amplifier is connected to the data line through the first switching element, and the second analog buffer amplifier is connected to the data line through a second switching element;
  • the selection signal controls whether the first analog buffer element and the second switching element are connected to the data line to control the first analog buffer amplifier and the second analog buffer amplifier to alternately drive in units of rows A plurality of rows of pixel units on the data line.
  • the first switching element When the selection signal is high level, the first switching element is connected to the data line, and the second switching element is disconnected from the data line;
  • the first switching element When the selection signal is low, the first switching element is disconnected from the data line, and the second switching element is connected to the data line.
  • the first switching element is an N-type MOS transistor, and the second switching element is a P-type MOS transistor;
  • the first switching element includes a first gate, a first source, and a first drain;
  • the second switching element includes a second gate, a second source, and a second drain;
  • the first gate and the second gate are connected to the selection signal, the first source is connected to the data line, and the first drain is connected to an output end of the first analog buffer amplifier;
  • the second source is coupled to the data line, and the second drain is coupled to an output of the second analog buffer amplifier.
  • the selection signal is generated based on a clock signal.
  • the liquid crystal display of the present invention can employ any of the above-described source driving circuits, and since the source driving circuit has been described above, it will not be described in detail herein.
  • the liquid crystal display of the present invention reduces the power consumption of a single analog buffer amplifier by adding an analog buffer amplifier to each data line, thereby reducing power consumption.

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  • Computer Hardware Design (AREA)
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Abstract

一种液晶显示面板的源极驱动电路（24）及液晶显示器，源极驱动电路（24）包括多个与数据线（22）对应的源极驱动单元（25）；源极驱动单元（25）包括：模数转换器（26）；包括第一模拟缓冲放大器（28）和第二模拟缓冲放大器（29）的模拟缓冲放大器组（27）；根据选择信号控制第一模拟缓冲放大器（28）和第二模拟缓冲放大器（29）以行为单位交替驱动数据线（22）上的多行像素单元（23）。

Description

一种液晶显示面板的源极驱动电路及液晶显示器 技术领域
本发明涉及显示器领域，特别是涉及一种液晶显示面板的源极驱动电路及液晶显示器。
 背景技术
为了避免产生极化电场，液晶显示器常采用行反转或者点反转的方式驱动。液晶显示面板包括阵列基板，如图1所述，其中阵列基板包括数据线12、扫描线11、以及由所述数据线12和所述扫描线11限定的多个像素单元13；现有的液晶显示面板中的源极驱动电路，包括多个模数转换器14、多个模拟缓冲放大器15，每条数据对应设置有一模数转换器14和一模拟缓冲放大器15，模数转换器14将信号源输入的模拟信号转换为数字信号；再利用模拟缓冲放大器15对数字信号进行放大操作后，将放大操作后的数字信号传输至相应的数据线，以驱动液晶显示面板的像素阵列。
但是，由于行反转（如图1）或者点反转（如图2）过程中，像素阵列需要的充电电压（也即像素电压）的范围很大，黑色表示像素单元的电压为正，灰色表示像素单元的电压为负，造成源极驱动电路功消耗很大，导致模拟缓冲放大器的发热很严重、损耗增大。
故，有必要提供一种液晶显示面板的源极驱动电路及液晶显示器，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种液晶显示面板的源极驱动电路及液晶显示器，以解决现有源极驱动电路中的模拟缓冲放大器发热严重的技术问题，从而增加了功耗。
技术解决方案
本发明实施例提供一种液晶显示面板的源极驱动电路，其中所述液晶显示面板包括阵列基板，所述阵列基板包括数据线、扫描线、以及由所述数据线和所述扫描线限定的多个像素单元；
所述源极驱动电路包括多个源极驱动单元，每条所述数据线对应设置有所述源极驱动单元；
所述源极驱动单元包括：
模数转换器，用于将信号源输入的模拟信号转换为数字信号；以及
模拟缓冲放大器组，包括第一模拟缓冲放大器和第二模拟缓冲放大器；所述模拟缓冲放大器组，用于对所述模数转换器的数字信号进行放大操作，并将放大操作后的所述数据信号传输至相应的数据线；
根据选择信号控制所述第一模拟缓冲放大器和所述第二模拟缓冲放大器以行为单位交替驱动所述数据线上的多行像素单元；所述选择信号根据时钟信号生成；
所述源极驱动单元还包括：第一开关元件、第二开关元件；
所述第一模拟缓冲放大器通过所述第一开关元件连接至所述数据线，所述第二模拟缓冲放大器通过第二开关元件连接至所述数据线；
所述选择信号通过控制所述第一开关元件和所述第二开关元件是否与所述数据线连接，以控制所述第一模拟缓冲放大器和所述第二模拟缓冲放大器以行为单位交替驱动所述数据线上的多行像素单元。
在本发明的液晶显示面板的源极驱动电路中，当所述选择信号为高电平时，所述第一开关元件与所述数据线连接，所述第二开关元件与所述数据线断开。
在本发明的液晶显示面板的源极驱动电路中，当所述选择信号为低电平时，所述第一开关元件与所述数据线断开，所述第二开关元件与所述数据线连接。
在本发明的液晶显示面板的源极驱动电路中，所述第一开关元件为N型金属氧化物半导体场效应晶体管、所述第二开关元件为P型金属氧化物半导体场效应晶体管；
所述第一开关元件包括第一栅极、第一源极、第一漏极；
所述第二开关元件包括第二栅极、第二源极、第二漏极；
所述第一栅极和所述第二栅极连接所述选择信号，所述第一源极连接所述数据线，所述第一漏极连接所述第一模拟缓冲放大器的输出端；
所述第二源极连接所述数据线，所述第二漏极连接所述第二模拟缓冲放大器的输出端。
本发明实施例提供一种液晶显示面板的源极驱动电路，其中所述液晶显示面板包括阵列基板，所述阵列基板包括数据线、扫描线、以及由所述数据线和所述扫描线限定的多个像素单元；
所述源极驱动电路包括多个源极驱动单元，每条所述数据线对应设置有所述源极驱动单元；
所述源极驱动单元包括：
模数转换器，用于将信号源输入的模拟信号转换为数字信号；
模拟缓冲放大器组，包括第一模拟缓冲放大器和第二模拟缓冲放大器；所述模拟缓冲放大器组，用于对所述模数转换器的数字信号进行放大操作，并将放大操作后的所述数据信号传输至相应的数据线；
根据选择信号控制所述第一模拟缓冲放大器和所述第二模拟缓冲放大器以行为单位交替驱动所述数据线上的多行像素单元。
在本发明的液晶显示面板的源极驱动电路中，所述源极驱动单元还包括：第一开关元件、第二开关元件；
所述第一模拟缓冲放大器通过所述第一开关元件连接至所述数据线，所述第二模拟缓冲放大器通过第二开关元件连接至所述数据线；
所述选择信号通过控制所述第一开关元件和所述第二开关元件是否与所述数据线连接，以控制所述第一模拟缓冲放大器和所述第二模拟缓冲放大器以行为单位交替驱动所述数据线上的多行像素单元。
在本发明的液晶显示面板的源极驱动电路中，当所述选择信号为高电平时，所述第一开关元件与所述数据线连接，所述第二开关元件与所述数据线断开。
在本发明的液晶显示面板的源极驱动电路中，当所述选择信号为低电平时，所述第一开关元件与所述数据线断开，所述第二开关元件与所述数据线连接。
在本发明的液晶显示面板的源极驱动电路中，所述第一开关元件为N型金属氧化物半导体场效应晶体管、所述第二开关元件为P型金属氧化物半导体场效应晶体管；
所述第一开关元件包括第一栅极、第一源极、第一漏极；
所述第二开关元件包括第二栅极、第二源极、第二漏极；
所述第一栅极和所述第二栅极连接所述选择信号，所述第一源极连接所述数据线，所述第一漏极连接所述第一模拟缓冲放大器的输出端；
所述第二源极连接所述数据线，所述第二漏极连接所述第二模拟缓冲放大器的输出端。
在本发明的液晶显示面板的源极驱动电路中，所述选择信号根据时钟信号生成。
本发明实施例还提供一种液晶显示器，其包括：液晶显示面板，所述液晶显示面板包括阵列基板，所述阵列基板包括数据线、扫描线、以及由所述数据线和所述扫描线限定的多个像素单元；
所述源极驱动电路包括多个源极驱动单元，每条所述数据线对应设置有所述源极驱动单元；
所述源极驱动单元包括：
模数转换器，用于将信号源输入的模拟信号转换为数字信号；
模拟缓冲放大器组，包括第一模拟缓冲放大器和第二模拟缓冲放大器，所述模拟缓冲放大器组，用于对所述模数转换器的数字信号进行放大操作，并将放大操作后的所述数据信号传输至相应的数据线；
根据选择信号控制所述第一模拟缓冲放大器和所述第二模拟缓冲放大器以行为单位交替驱动所述数据线上的多行像素单元。
在本发明的液晶显示器中，所述源极驱动单元还包括：第一开关元件、第二开关元件；
所述第一模拟缓冲放大器通过所述第一开关元件连接至所述数据线，所述第二模拟缓冲放大器通过第二开关元件连接至所述数据线；
所述选择信号通过控制所述第一开关元件和所述第二开关元件是否与所述数据线连接，以控制所述第一模拟缓冲放大器和所述第二模拟缓冲放大器以行为单位交替驱动所述数据线上的多行像素单元。
在本发明的液晶显示器中，当所述选择信号为高电平时，所述第一开关元件与所述数据线连接，所述第二开关元件与所述数据线断开；
当所述选择信号为低电平时，所述第一开关元件与所述数据线断开，所述第二开关元件与所述数据线连接。
在本发明的液晶显示器中，所述第一开关元件为N型金属氧化物半导体场效应晶体管、所述第二开关元件为P型金属氧化物半导体场效应晶体管；
所述第一开关元件包括第一栅极、第一源极、第一漏极；
所述第二开关元件包括第二栅极、第二源极、第二漏极；
所述第一栅极和所述第二栅极连接所述选择信号，所述第一源极连接所述数据线，所述第一漏极连接所述第一模拟缓冲放大器的输出端；
所述第二源极连接所述数据线，所述第二漏极连接所述第二模拟缓冲放大器的输出端。
在本发明的液晶显示器中，所述选择信号根据时钟信号生成。
 有益效果
本发明的液晶显示面板的源极驱动电路及液晶显示器，通过给每条数据线增加一个模拟缓冲放大器，从而降低了单个模拟缓冲放大器的温度，从而降低了功耗。
 附图说明
图1为现有技术的第一种阵列基板的结构示意图；
图2为现有技术的第二种阵列基板的结构示意图；
图3为本发明的第一种阵列基板的结构示意图；
图4为图3中源极驱动单元的放大结构示意图；
图5为本发明的第二种阵列基板的结构示意图；
图6为本发明的选择信号的时序图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
请参照图3，图3为本发明的第一种阵列基板的结构示意图。
本发明的液晶显示面板包括：彩膜基板、阵列基板、以及位于所述彩膜基板和所述阵列基板之间的液晶层，其中所述阵列基板如图3所述，其包括数据线22、扫描线21、以及由所述数据线22和所述扫描线21限定的多个像素单元23；所述阵列基板还包括源极驱动电路24；
所述源极驱动电路24包括多个源极驱动单元25，每条所述数据线对应设置有所述源极驱动单元25；
结合图4，所述源极驱动单元25包括：模数转换器26、模拟缓冲放大器组27，当信号源向液晶显示面板输入视频信号时，该视频信号为模拟信号，所述模数转换器26将信号源输入的视频信号转换为数字信号；接着所述模拟缓冲放大器组27对所述模数转换器获取到的数字信号进行放大操作（所述放大操作譬如放大数字信号的负载驱动能力，以驱动数据线上的像素阵列负载），并将放大操作后的所述数据信号传输至相应的数据线；
所述模拟缓冲放大器组27，包括第一模拟缓冲放大器28和第二模拟缓冲放大器29；
所述阵列基板上还设置有选择信号输入线30，用于提供选择信号，本发明的源极驱动电路能够根据所述选择信号输入线30输入的选择信号控制所述第一模拟缓冲放大器28和所述第二模拟缓冲放大器29以行为单位交替驱动所述数据线上的多行像素单元。
以左侧第一条数据线为例，譬如先使所述第一模拟缓冲放大器单独工作，即对第一条数据线上的第一行像素单元对应的数字信号进行处理，以对第一条数据线上的第一行像素单元进行驱动，使该像素单元进行显示，接着再使所述第二模拟缓冲放大器单独工作，即对第一条数据线上的第二行像素单元对应的数字信号进行处理，以对第一条数据线上的第二行像素单元进行驱动，再使所述第一模拟缓冲放大器单独工作，即对第一条数据线上的第三行像素单元对应的数字信号进行处理，以对第一条数据线上的第三行像素单元进行驱动，以及使所述第二模拟缓冲放大器单独工作，即对第一条数据线上的第四行像素单元对应的数字信号进行处理，以对第一条数据线上的第四行像素单元进行驱动。
优选地，所述源极驱动单元25还包括：第一开关元件31和第二开关元件32；所述第一模拟缓冲放大器28可通过所述第一开关元件31连接至所述数据线，所述第二模拟缓冲放大器29可通过第二开关元件32连接至所述数据线；
所述选择信号通过控制所述第一开关元件和所述第二开关元件是否与所述数据线连接，以控制所述第一模拟缓冲放大器和所述第二模拟缓冲放大器以行为单位交替驱动所述数据线上的多行像素单元。具体为当所述选择信号为高电平时，所述第一开关元件31与所述数据线连接，所述第二开关元件32与所述数据线断开；当所述选择信号为低电平时，所述第一开关元件31与所述数据线断开，所述第二开关元件32与所述数据线连接。
所述第一开关元件31可为N型MOS管（金属氧化物半导体场效应晶体管），所述第二开关元件可32为P型MOS管，所述第一开关元件31包括第一栅极、第一源极、第一漏极；所述第二开关元件32包括第二栅极、第二源极、第二漏极；
所述第一栅极和所述第二栅极连接所述选择信号，所述第一源极连接所述数据线，所述第一漏极连接所述第一模拟缓冲放大器28的输出端；
所述第二源极连接所述数据线，所述第二漏极连接所述第二模拟缓冲放大器29的输出端。
优选地，所述选择信号根据时钟信号生成。其中选择信号可由液晶显示面板上的时序控制器提供，其波形如图6所示，时序控制器提供时钟信号，时钟信号Clock的时序图如图6所示，扫描线上输入的扫描信号也根据时钟信号产生，所述选择信号Select参照所述时钟信号生成，优选地根据所述扫描信号生成。
譬如，在时间t1-t2之间，所述选择信号为高电平，使得所述第一开关闭合，所述第二开关断开，所述第一模拟缓冲放大器工作，所述第二模拟缓冲放大器不工作，所述第一模拟缓冲放大器将经过放大操作后的数据信号传输至与其对应的所述数据线上的第一行像素单元；在时间t2-t3之间，所述选择信号为低电平，使得所述第二开关闭合，所述第一开关断开，所述第二模拟缓冲放大器工作，所述第一模拟缓冲放大器不工作，即所述第二模拟缓冲放大器将经过放大操作后的数据信号传输至与其对应的所述数据线上的第二行像素单元，在时间t3-t4之间，所述选择信号为高电平，使得所述第一开关闭合，所述第二开关断开，所述第一模拟缓冲放大器工作，所述第二模拟缓冲放大器不工作，所述第一模拟缓冲放大器将经过放大操作后的数据信号传输至与其对应的所述数据线上的第三行像素单元；在时间t4-t5之间，所述选择信号为低电平，使得所述第二开关闭合，所述第一开关断开，所述第二模拟缓冲放大器工作，所述第一模拟缓冲放大器不工作，即所述第二模拟缓冲放大器将经过放大操作后的数据信号传输至与其对应的所述数据线上的第四行像素单元。
可见，本发明的数据线上的输入信号是由两个缓冲放大器交替输出，即隔行交替输出，这样降低了每个放大器的温度，而且在行反转和点反转的情况下降低了功耗。
由于每条数据线增加一个模拟缓冲放大器，即每条数据线有两个模拟缓冲放大器，并通过开关控制这两个模拟缓冲放大器输出与关闭，能够使得两个缓冲放大器交替工作，特别是在像素单元进行行反转或者点反转的情况，图3给出像素阵列行反转的示意图，图5给出像素阵列点反转的示意图，本发明在保证液晶显示面板正常工作的条件下，与现有技术仅设置一个模拟缓冲放大器比较，模拟缓冲放大器的工作时间减少一半，使得每个模拟缓冲放大器的温度大大降低，降低了功耗。
本发明的液晶显示面板的源极驱动电路，通过给每条数据线增加一个模拟缓冲放大器，从而降低了单个模拟缓冲放大器的温度，从而降低了功耗。
本发明还提供一种液晶显示器，包括液晶显示面板及背光模块，所述液晶显示面板包括阵列基板，所述阵列基板包括数据线、扫描线、以及由所述数据线和所述扫描线限定的多个像素单元；
所述源极驱动电路包括多个源极驱动单元，每条所述数据线对应设置有所述源极驱动单元；
所述源极驱动单元包括：
模数转换器，用于将信号源输入的模拟信号转换为数字信号；
模拟缓冲放大器组，包括第一模拟缓冲放大器和第二模拟缓冲放大器，所述模拟缓冲放大器组，用于对所述模数转换器的数字信号进行放大操作，并将放大操作后的所述数据信号传输至相应的数据线；
根据选择信号控制所述第一模拟缓冲放大器和所述第二模拟缓冲放大器以行为单位交替驱动所述数据线上的多行像素单元。
优选地，所述源极驱动单元还包括：第一开关元件、第二开关元件；
所述第一模拟缓冲放大器通过所述第一开关元件连接至所述数据线，所述第二模拟缓冲放大器通过第二开关元件连接至所述数据线；
所述选择信号通过控制所述第一开关元件和所述第二开关元件是否与所述数据线连接，以控制所述第一模拟缓冲放大器和所述第二模拟缓冲放大器以行为单位交替驱动所述数据线上的多行像素单元。
当所述选择信号为高电平时，所述第一开关元件与所述数据线连接，所述第二开关元件与所述数据线断开；
当所述选择信号为低电平时，所述第一开关元件与所述数据线断开，所述第二开关元件与所述数据线连接。
所述第一开关元件为N型MOS管、所述第二开关元件为P型MOS管；
所述第一开关元件包括第一栅极、第一源极、第一漏极；
所述第二开关元件包括第二栅极、第二源极、第二漏极；
所述第一栅极和所述第二栅极连接所述选择信号，所述第一源极连接所述数据线，所述第一漏极连接所述第一模拟缓冲放大器的输出端；
所述第二源极连接所述数据线，所述第二漏极连接所述第二模拟缓冲放大器的输出端。
所述选择信号根据时钟信号生成。
本发明的液晶显示器可以采用上述任何一种源极驱动电路，鉴于源极驱动电路已在上文描述，在此不再详述。
本发明的液晶显示器，通过给每条数据线增加一个模拟缓冲放大器，从而降低了单个模拟缓冲放大器的温度，从而降低了功耗。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (15)

  1. 一种液晶显示面板的源极驱动电路，其中
    所述液晶显示面板包括阵列基板，所述阵列基板包括数据线、扫描线、以及由所述数据线和所述扫描线限定的多个像素单元；
    所述源极驱动电路包括多个源极驱动单元，每条所述数据线对应设置有所述源极驱动单元；
    所述源极驱动单元包括：
    模数转换器，用于将信号源输入的模拟信号转换为数字信号；以及
    模拟缓冲放大器组，包括第一模拟缓冲放大器和第二模拟缓冲放大器；所述模拟缓冲放大器组，用于对所述模数转换器的数字信号进行放大操作，并将放大操作后的所述数据信号传输至相应的数据线；
    根据选择信号控制所述第一模拟缓冲放大器和所述第二模拟缓冲放大器以行为单位交替驱动所述数据线上的多行像素单元；所述选择信号根据时钟信号生成；
    所述源极驱动单元还包括：第一开关元件、第二开关元件；
    所述第一模拟缓冲放大器通过所述第一开关元件连接至所述数据线，所述第二模拟缓冲放大器通过第二开关元件连接至所述数据线；
    所述选择信号通过控制所述第一开关元件和所述第二开关元件是否与所述数据线连接，以控制所述第一模拟缓冲放大器和所述第二模拟缓冲放大器以行为单位交替驱动所述数据线上的多行像素单元。
  2. 根据权利要求1所述的液晶显示面板的源极驱动电路，其中
    当所述选择信号为高电平时，所述第一开关元件与所述数据线连接，所述第二开关元件与所述数据线断开。
  3. 根据权利要求1所述的液晶显示面板的源极驱动电路，其中
    当所述选择信号为低电平时，所述第一开关元件与所述数据线断开，所述第二开关元件与所述数据线连接。
  4. 根据权利要求1所述的液晶显示面板的源极驱动电路，其中所述第一开关元件为N型金属氧化物半导体场效应晶体管、所述第二开关元件为P型金属氧化物半导体场效应晶体管；
    所述第一开关元件包括第一栅极、第一源极、第一漏极；
    所述第二开关元件包括第二栅极、第二源极、第二漏极；
    所述第一栅极和所述第二栅极连接所述选择信号，所述第一源极连接所述数据线，所述第一漏极连接所述第一模拟缓冲放大器的输出端；
    所述第二源极连接所述数据线，所述第二漏极连接所述第二模拟缓冲放大器的输出端。
  5. 一种液晶显示面板的源极驱动电路，其中
    所述液晶显示面板包括阵列基板，所述阵列基板包括数据线、扫描线、以及由所述数据线和所述扫描线限定的多个像素单元；
    所述源极驱动电路包括多个源极驱动单元，每条所述数据线对应设置有所述源极驱动单元；
    所述源极驱动单元包括：
    模数转换器，用于将信号源输入的模拟信号转换为数字信号；
    模拟缓冲放大器组，包括第一模拟缓冲放大器和第二模拟缓冲放大器；所述模拟缓冲放大器组，用于对所述模数转换器的数字信号进行放大操作，并将放大操作后的所述数据信号传输至相应的数据线；
    根据选择信号控制所述第一模拟缓冲放大器和所述第二模拟缓冲放大器以行为单位交替驱动所述数据线上的多行像素单元。
  6. 根据权利要求5所述的液晶显示面板的源极驱动电路，其中所述源极驱动单元还包括：第一开关元件、第二开关元件；
    所述第一模拟缓冲放大器通过所述第一开关元件连接至所述数据线，所述第二模拟缓冲放大器通过第二开关元件连接至所述数据线；
    所述选择信号通过控制所述第一开关元件和所述第二开关元件是否与所述数据线连接，以控制所述第一模拟缓冲放大器和所述第二模拟缓冲放大器以行为单位交替驱动所述数据线上的多行像素单元。
  7. 根据权利要求6所述的液晶显示面板的源极驱动电路，其中
    当所述选择信号为高电平时，所述第一开关元件与所述数据线连接，所述第二开关元件与所述数据线断开；
  8. 根据权利要求6所述的液晶显示面板的源极驱动电路，其中
    当所述选择信号为低电平时，所述第一开关元件与所述数据线断开，所述第二开关元件与所述数据线连接。
  9. 根据权利要求6所述的液晶显示面板的源极驱动电路，其中所述第一开关元件为N型金属氧化物半导体场效应晶体管、所述第二开关元件为P型金属氧化物半导体场效应晶体管；
    所述第一开关元件包括第一栅极、第一源极、第一漏极；
    所述第二开关元件包括第二栅极、第二源极、第二漏极；
    所述第一栅极和所述第二栅极连接所述选择信号，所述第一源极连接所述数据线，所述第一漏极连接所述第一模拟缓冲放大器的输出端；
    所述第二源极连接所述数据线，所述第二漏极连接所述第二模拟缓冲放大器的输出端。
  10. 根据权利要求5所述的液晶显示面板的源极驱动电路，其中
    所述选择信号根据时钟信号生成。
  11. 一种液晶显示器，其包括液晶显示面板，所述液晶显示面板包括阵列基板，所述阵列基板包括数据线、扫描线、以及由所述数据线和所述扫描线限定的多个像素单元；
    所述源极驱动电路包括多个源极驱动单元，每条所述数据线对应设置有所述源极驱动单元；
    所述源极驱动单元包括：
    模数转换器，用于将信号源输入的模拟信号转换为数字信号；
    模拟缓冲放大器组，包括第一模拟缓冲放大器和第二模拟缓冲放大器，所述模拟缓冲放大器组，用于对所述模数转换器的数字信号进行放大操作，并将放大操作后的所述数据信号传输至相应的数据线；
    根据选择信号控制所述第一模拟缓冲放大器和所述第二模拟缓冲放大器以行为单位交替驱动所述数据线上的多行像素单元。
  12. 根据权利要求11所述的液晶显示器，其中
    所述源极驱动单元还包括：第一开关元件、第二开关元件；
    所述第一模拟缓冲放大器通过所述第一开关元件连接至所述数据线，所述第二模拟缓冲放大器通过第二开关元件连接至所述数据线；
    所述选择信号通过控制所述第一开关元件和所述第二开关元件是否与所述数据线连接，以控制所述第一模拟缓冲放大器和所述第二模拟缓冲放大器以行为单位交替驱动所述数据线上的多行像素单元。
  13. 根据权利要求12所述的液晶显示器，其中
    当所述选择信号为高电平时，所述第一开关元件与所述数据线连接，所述第二开关元件与所述数据线断开；
    当所述选择信号为低电平时，所述第一开关元件与所述数据线断开，所述第二开关元件与所述数据线连接。
  14. 根据权利要求12所述的液晶显示器，其中
    所述第一开关元件为N型金属氧化物半导体场效应晶体管、所述第二开关元件为P型金属氧化物半导体场效应晶体管；
    所述第一开关元件包括第一栅极、第一源极、第一漏极；
    所述第二开关元件包括第二栅极、第二源极、第二漏极；
    所述第一栅极和所述第二栅极连接所述选择信号，所述第一源极连接所述数据线，所述第一漏极连接所述第一模拟缓冲放大器的输出端；
    所述第二源极连接所述数据线，所述第二漏极连接所述第二模拟缓冲放大器的输出端。
  15. 根据权利要求11所述的液晶显示器，其中
    所述选择信号根据时钟信号生成。
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