WO2016098249A1 - Information processing device and fpga configuration method - Google Patents

Information processing device and fpga configuration method Download PDF

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Publication number
WO2016098249A1
WO2016098249A1 PCT/JP2014/083722 JP2014083722W WO2016098249A1 WO 2016098249 A1 WO2016098249 A1 WO 2016098249A1 JP 2014083722 W JP2014083722 W JP 2014083722W WO 2016098249 A1 WO2016098249 A1 WO 2016098249A1
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fpgas
fpga
configuration data
configuration
data bus
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PCT/JP2014/083722
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French (fr)
Japanese (ja)
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孝彰 杉田
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三菱電機株式会社
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Priority to JP2016564550A priority Critical patent/JP6381673B2/en
Priority to PCT/JP2014/083722 priority patent/WO2016098249A1/en
Publication of WO2016098249A1 publication Critical patent/WO2016098249A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components

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  • the present invention relates to an information processing apparatus and an FPGA configuration method for configuring an FPGA (Field Programmable Gate Array).
  • the FPGA uses a volatile memory as a memory for writing data for determining a logical structure, the data is lost when the power is turned off. Therefore, every time the FPGA is activated, it is necessary to write data into the memory, that is, to perform configuration.
  • a mode called slave parallel mode in which a configuration clock is supplied from the CPU (Central Processing Unit) to the FPGA, and configuration data is written on the parallel bus according to the clock (for example, (See Patent Documents 1 and 2).
  • the invention according to Patent Document 2 employs a configuration in which configuration time is shortened by simultaneously writing configuration data to a plurality of FPGAs.
  • this configuration since one set of flash ROM and a download control circuit is required for each FPGA, there is a problem that the hardware scale increases.
  • the present invention has been made to solve the above-described problems, and aims to shorten the configuration time for a plurality of FPGAs without increasing the hardware scale.
  • An information processing apparatus includes a plurality of FPGAs, a memory that stores a plurality of configuration data for configuring the plurality of FPGAs, and a processor that writes the plurality of configuration data stored in the memories to the plurality of FPGAs.
  • a data bus branched from the processor side and connected to a plurality of FPGAs, the data buses being connected to a plurality of FPGAs for each configuration data bus width of the FPGA, and a memory for each of the plurality of FPGAs.
  • the configuration data for the FPGA is stored in the address corresponding to the data bus for each width of the configuration data bus connected to the processor, and the processor stores the duplicate data stored in each address corresponding to the data bus connected to the plurality of FPGAs.
  • the configuration data and simultaneously write to a plurality of FPGA through a data bus.
  • the hardware scale does not increase.
  • a memory in which configuration data for the FPGA is stored at an address corresponding to the data bus for each configuration data bus width connected to the FPGA is used. Configuration data can be written, and configuration time can be shortened.
  • FIG. 3 is a diagram showing a flow of configuration data in the information processing apparatus according to Embodiment 1.
  • FIG. 3 is a diagram showing a memory map of configuration data in the flash ROM according to the first embodiment.
  • FIG. It is a figure which shows the memory map of the configuration data in the conventional flash ROM.
  • 3 is a flowchart illustrating an FPGA configuration method by the information processing apparatus according to the first embodiment.
  • 7 is a block diagram illustrating a modification of the information processing apparatus according to Embodiment 1.
  • FIG. It is a figure which shows the memory map of the configuration data in the flash ROM of FIG. 7 is a block diagram illustrating a modification of the information processing apparatus according to Embodiment 1.
  • FIG. It is a figure which shows the memory map of the configuration data in the flash ROM of FIG.
  • FIG. 1 is a block diagram illustrating a configuration example of the information processing apparatus 1 according to the first embodiment.
  • n (n ⁇ 2) FPGAs 11 and 12 are connected to the CPU 2 via the CPU bus 3.
  • a flash ROM 4 is also connected to the CPU bus 3.
  • a DRAM (Dynamic Random Access Memory) 5 is connected to the CPU 2 via a dedicated memory bus 6.
  • Embodiment 1 only one flash ROM 4 is used regardless of the number of FPGAs. Further, a download control circuit for writing configuration data from the flash ROM 4 to the FPGA is not required other than the CPU 2.
  • FIG. 2 is a diagram showing a configuration flow in the information processing apparatus 1 according to the first embodiment.
  • the flow of configuration data is indicated by a broken line.
  • the CPU bus 3 is a parallel bus, and is branched halfway from the side connected to the CPU 2 and connected to the FPGAs 11 and 12.
  • a CPU bus 3 having a data bus width of 32 bits is used.
  • a lower 16-bit configuration data bus denoted as “DAT ⁇ 15.0>” is connected to the FPGA 11, and an upper 16-bit configuration denoted as “DAT ⁇ 31.16>”.
  • DAT ⁇ 15.0> is connected to the FPGA 11
  • an upper 16-bit configuration denoted as “DAT ⁇ 31.16>”.
  • CS * chip select control bus
  • the CPU 2 switches the signal value of the control bus for chip selection to make the FPGAs 11 and 12 ready for reading and writing.
  • the CPU 2 can write configuration data to the FPGA 11 through the lower 16 bits of the configuration data bus in the CPU bus 3 and simultaneously write configuration data to the FPGA 12 through the upper 16 bits.
  • control bus for supplying the configuration clock is not shown.
  • a configuration clock is supplied from the CPU 2 to the FPGAs 11 and 12, and configuration data is written to the FPGAs 11 and 12 in accordance with this clock.
  • FIG. 3 is a diagram showing a memory map of configuration data in the flash ROM 4 of the first embodiment.
  • the configuration data 21 of the FPGA 11 and the configuration data 22 of the FPGA 12 are stored in the flash ROM 4.
  • the configuration data 21 of the FPGA 11 is stored at an address corresponding to the lower 16 bits (0 to 15 bits) of the configuration data bus
  • the FPGA 12 is stored at an address corresponding to the upper 16 bits (16 to 31 bits) of the configuration data bus.
  • the configuration data 22 is stored and combined.
  • the base address indicates a start address when the configuration data 21 and 22 of the FPGAs 11 and 12 are stored.
  • the point is to store the configuration data for the FPGA at an address corresponding to the data bus for each width of the configuration data bus connected to the FPGA.
  • the configuration data 21 is output to the FPGA 11 through the data bus denoted as “DAT ⁇ 15.0>” in FIG.
  • the configuration data 22 is output to the FPGA 12 through a data bus denoted as “DAT ⁇ 31..16>”.
  • FIG. 4 shows a configuration in which configuration data is sequentially written from one flash ROM to two FPGAs as in Patent Document 1 described above. Since each of the FPGAs 11 and 12 has a configuration data bus width of 16 bits, the configuration data 21 and 22 of the FPGAs 11 and 12 are sequentially stored in the addresses corresponding to the configuration data buses 0 to 15 bits in the flash ROM 4. Has been.
  • the configuration data 21 is output to the FPGA 11 through a configuration data bus having a 16-bit width.
  • the configuration data 22 is output to the FPGA 12 through a configuration data bus having a 16-bit width.
  • the storage address is doubled in FIG. 4 compared to FIG. The time will be longer.
  • FIG. 5 is a flowchart showing the FPGA configuration method by the information processing apparatus 1 according to the first embodiment.
  • the CPU 2 reads the configuration data 21 and 22 from the flash ROM 4 through the CPU bus 3 (step ST1), and expands it to the DRAM 5 through the memory bus 6 (step ST2). Then, the CPU 2 reads the configuration data 21 and 22 expanded in the DRAM 5 through the memory bus 6 and simultaneously writes them into the FPGAs 11 and 12 through the CPU bus 3.
  • This sequence is all software processing performed by the CPU 2, and no hardware other than the CPU 2 is required.
  • the configuration data since configuration data is simultaneously written to a plurality of FPGAs, the configuration data may be written only once.
  • a total of 8 bits of data buses of 0 to 7 bits counted from the lower side are connected to the FPGA 11, and a total of 8 bits of 8 to 15 bits are connected to the FPGA 12.
  • the configuration data 21 of the FPGA 11 is stored in the address corresponding to 0 to 7 bits counted from the lower side in the flash ROM 4, and the FPGA 12 is stored in the address corresponding to 8 to 15 bits.
  • the configuration data 22 is stored, the configuration data 23 of the FPGA 13 is stored at addresses corresponding to 16 bits to 23 bits, and the configuration data 24 of the FPGA 14 is stored at addresses corresponding to 24 to 31 bits.
  • FPGAs having different data bus widths may be mixed. Examples of this are shown in FIGS. As shown in FIG. 8, among the data bus width 32 bits of the CPU bus 3, a total of 16 bits of data buses of 0 to 15 bits counted from the lower side are connected to the FPGA 11, and a total of 8 bits of data buses of 16 to 23 bits are connected to the FPGA 12. Connect a 24-bit to 8-bit data bus to the FPGA 13 in total.
  • the configuration data 21 of the FPGA 11 is stored in an address corresponding to 0 to 15 bits counted from the lower side in the flash ROM 4, and the FPGA 12 is stored in an address corresponding to 16 to 23 bits.
  • the configuration data 22 is stored, and the configuration data 23 of the FPGA 13 is stored at an address corresponding to 24 to 31 bits and combined.
  • the FPGA configuration data bus width is less than or equal to the data bus width of the CPU bus 3.
  • the FPGA configuration data bus width And the number can be changed freely.
  • the data bus width of the CPU bus 3 is 32 bits, two FPGAs (two FPGAs having a 16-bit data bus width, or two FPGAs having a 8-bit data bus width), three FPGAs (one FPGA having a 16-bit data bus width and 8-bit data)
  • a combination of two FPGAs having a bus width and four FPGAs is possible.
  • the configuration data bus width and the number of FPGAs can be freely changed as described above.
  • the configuration data bus width and the number of FPGAs can be freely changed as described above.
  • the flash ROM is used as the memory for storing the configuration data, but other memories may be used.
  • a non-volatile memory in which data is not lost even when the power is turned off, and a memory having a data bus width equal to or larger than the CPU bus is desirable.
  • the CPU is used as the processor for controlling the writing of the configuration data, other processors may be used.
  • the information processing apparatus 1 includes the plurality of FPGAs 11 and 12 and the flash ROM 4 that stores the plurality of configuration data 21 and 22 for configuring the plurality of FPGAs 11 and 12.
  • a CPU 2 for writing a plurality of configuration data 21 and 22 stored in the flash ROM 4 to the plurality of FPGAs 11 and 12 and a CPU bus 3 branched from the CPU 2 side and connected to the plurality of FPGAs 11 and 12 are provided.
  • the CPU bus 3 is connected to a plurality of FPGAs 11 and 12 for each FPGA configuration data bus width
  • the flash ROM 4 is a data bus for each configuration data bus width connected to the FPGA for each of the plurality of FPGAs 11 and 12.
  • the configuration data for the FPGA is stored in the address corresponding to the CPU bus, and the CPU 2 stores the plurality of configuration data 21 and 22 stored in each address corresponding to the data bus connected to the plurality of FPGAs 11 and 12 in the CPU bus. 3, a plurality of FPGAs 11 and 12 are simultaneously written. Since only one CPU and flash ROM are required regardless of the number of FPGAs, the hardware scale does not increase. In addition, since it is possible to simultaneously write to a plurality of FPGAs, the configuration time can be shortened.
  • any component of the embodiment can be modified or any component of the embodiment can be omitted within the scope of the invention.
  • the information processing apparatus shortens the FPGA configuration time, it is suitable for use in a car navigation apparatus equipped with a plurality of FPGAs.

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Abstract

This information processing device 1 is provided with: a plurality of FPGAs 11, 12; a flash ROM 4; a CPU 2; and a CPU bus 3 that branches from the CPU 2 side and is connected to the plurality of FPGAs 11, 12. The CPU bus 3 is respectively connected to the plurality of FPGAs 11, 12 at each data bus width for FPGA configuration. The flash ROM 4 stores, for each of the plurality of FPGAs 11, 12, configuration data for the relevant FPGA, in an address corresponding to the data bus at each configuration data bus width connected to the FPGA. The CPU 2 simultaneously writes, to the plurality of FPGAs 11, 12 via the CPU bus 3, a plurality of configuration data 21, 22 stored in the addresses corresponding to the data buses connected to the plurality of FPGAs 11, 12.

Description

情報処理装置およびＦＰＧＡコンフィギュレーション方法Information processing apparatus and FPGA configuration method
　この発明は、ＦＰＧＡ（Ｆｉｅｌｄ　Ｐｒｏｇｒａｍｍａｂｌｅ　Ｇａｔｅ　Ａｒｒａｙ）のコンフィギュレーションを行う情報処理装置およびＦＰＧＡコンフィギュレーション方法に関するものである。 The present invention relates to an information processing apparatus and an FPGA configuration method for configuring an FPGA (Field Programmable Gate Array).
　ＦＰＧＡは、論理構造を決定するデータを書き込むメモリとして揮発性メモリを用いるため、電源を切るとデータが消失する。そのため、ＦＰＧＡを起動する都度、データをメモリに書き込む、つまりコンフィギュレーションを行う必要がある。ＦＰＧＡのコンフィギュレーションには、スレーブパラレルモードと呼ばれる、ＣＰＵ（Ｃｅｎｔｒａｌ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）からＦＰＧＡへコンフィギュレーションクロックを供給し、クロックに合わせてコンフィギュレーションデータをパラレルバスで書き込むモードが用意されている（例えば、特許文献１，２参照）。 Since the FPGA uses a volatile memory as a memory for writing data for determining a logical structure, the data is lost when the power is turned off. Therefore, every time the FPGA is activated, it is necessary to write data into the memory, that is, to perform configuration. For FPGA configuration, there is a mode called slave parallel mode, in which a configuration clock is supplied from the CPU (Central Processing Unit) to the FPGA, and configuration data is written on the parallel bus according to the clock (for example, (See Patent Documents 1 and 2).
特開２００９－１９３３２１号公報JP 2009-193321 A 特開２０１０－１７７８９７号公報JP 2010-177897 A
　上記特許文献１に係る発明では、複数のＦＰＧＡに対するコンフィギュレーションに要する時間を短縮するために、フラッシュＲＯＭ（Ｒｅａｄ　Ｏｎｌｙ　Ｍｅｍｏｒｙ）およびダウンロード制御回路を１組だけ搭載し、ダウンロード制御回路がフラッシュＲＯＭからコンフィギュレーションデータを読み出し、複数のＦＰＧＡに対して順次書き込む構成が採用されている。しかし、複数のＦＰＧＡに順番にデータを書き込んでいくシーケンスであるため、ＦＰＧＡの数が増えるほどコンフィギュレーション時間が長くなるという課題があった。 In the invention according to Patent Document 1, only one set of flash ROM (Read Only Memory) and a download control circuit is mounted in order to reduce the time required for configuration of a plurality of FPGAs, and the download control circuit is configured from the flash ROM. A configuration is employed in which the operation data is read and sequentially written to a plurality of FPGAs. However, since this sequence sequentially writes data to a plurality of FPGAs, there is a problem that the configuration time increases as the number of FPGAs increases.
　他方、上記特許文献２に係る発明では、複数のＦＰＧＡに対して同時にコンフィギュレーションデータを書き込むことによって、コンフィギュレーション時間を短縮する構成が採用されている。この構成の場合、１個のＦＰＧＡにつき１組のフラッシュＲＯＭおよびダウンロード制御回路が必要なため、ハードウエア規模が増大するという課題があった。 On the other hand, the invention according to Patent Document 2 employs a configuration in which configuration time is shortened by simultaneously writing configuration data to a plurality of FPGAs. In the case of this configuration, since one set of flash ROM and a download control circuit is required for each FPGA, there is a problem that the hardware scale increases.
　この発明は、上記のような課題を解決するためになされたもので、ハードウエア規模を増大することなく、複数のＦＰＧＡに対するコンフィギュレーション時間を短縮することを目的とする。 The present invention has been made to solve the above-described problems, and aims to shorten the configuration time for a plurality of FPGAs without increasing the hardware scale.
　この発明に係る情報処理装置は、複数のＦＰＧＡと、複数のＦＰＧＡをコンフィギュレーションする複数のコンフィギュレーションデータを格納したメモリと、メモリに格納された複数のコンフィギュレーションデータを複数のＦＰＧＡに書き込むプロセッサと、プロセッサ側から分岐して複数のＦＰＧＡに接続するデータバスとを備え、データバスは、ＦＰＧＡのコンフィギュレーション用データバス幅ごとに複数のＦＰＧＡに接続され、メモリは、複数のＦＰＧＡそれぞれについて、ＦＰＧＡと接続したコンフィギュレーション用データバス幅ごとのデータバスに対応するアドレスに当該ＦＰＧＡ用のコンフィギュレーションデータを格納し、プロセッサは、複数のＦＰＧＡと接続したデータバスに対応する各アドレスに格納された複数のコンフィギュレーションデータを、データバスを通じて複数のＦＰＧＡに同時に書き込むものである。 An information processing apparatus according to the present invention includes a plurality of FPGAs, a memory that stores a plurality of configuration data for configuring the plurality of FPGAs, and a processor that writes the plurality of configuration data stored in the memories to the plurality of FPGAs. A data bus branched from the processor side and connected to a plurality of FPGAs, the data buses being connected to a plurality of FPGAs for each configuration data bus width of the FPGA, and a memory for each of the plurality of FPGAs. The configuration data for the FPGA is stored in the address corresponding to the data bus for each width of the configuration data bus connected to the processor, and the processor stores the duplicate data stored in each address corresponding to the data bus connected to the plurality of FPGAs. The configuration data, and simultaneously write to a plurality of FPGA through a data bus.
　この発明によれば、１組のメモリおよびプロセッサを用いて複数のＦＰＧＡをコンフィギュレーションするようにしたので、ハードウエア規模は増大しない。また、複数のＦＰＧＡそれぞれについて、ＦＰＧＡと接続したコンフィギュレーション用データバス幅ごとのデータバスに対応するアドレスに当該ＦＰＧＡ用のコンフィギュレーションデータを格納したメモリを採用したので、複数のＦＰＧＡに対して同時にコンフィギュレーションデータを書き込むことができるようになり、コンフィギュレーション時間を短縮できる。 According to the present invention, since a plurality of FPGAs are configured using one set of memory and processor, the hardware scale does not increase. In addition, for each of the plurality of FPGAs, a memory in which configuration data for the FPGA is stored at an address corresponding to the data bus for each configuration data bus width connected to the FPGA is used. Configuration data can be written, and configuration time can be shortened.
この発明の実施の形態１に係る情報処理装置の構成例を示すブロック図である。It is a block diagram which shows the structural example of the information processing apparatus which concerns on Embodiment 1 of this invention. 実施の形態１に係る情報処理装置におけるコンフィギュレーションデータの流れを示す図である。3 is a diagram showing a flow of configuration data in the information processing apparatus according to Embodiment 1. FIG. 実施の形態１のフラッシュＲＯＭにおけるコンフィギュレーションデータのメモリマップを示す図である。3 is a diagram showing a memory map of configuration data in the flash ROM according to the first embodiment. FIG. 従来のフラッシュＲＯＭにおけるコンフィギュレーションデータのメモリマップを示す図である。It is a figure which shows the memory map of the configuration data in the conventional flash ROM. 実施の形態１に係る情報処理装置によるＦＰＧＡコンフィギュレーション方法を示すフローチャートである。3 is a flowchart illustrating an FPGA configuration method by the information processing apparatus according to the first embodiment. 実施の形態１に係る情報処理装置の変形例を示すブロック図である。7 is a block diagram illustrating a modification of the information processing apparatus according to Embodiment 1. FIG. 図６のフラッシュＲＯＭにおけるコンフィギュレーションデータのメモリマップを示す図である。It is a figure which shows the memory map of the configuration data in the flash ROM of FIG. 実施の形態１に係る情報処理装置の変形例を示すブロック図である。7 is a block diagram illustrating a modification of the information processing apparatus according to Embodiment 1. FIG. 図８のフラッシュＲＯＭにおけるコンフィギュレーションデータのメモリマップを示す図である。It is a figure which shows the memory map of the configuration data in the flash ROM of FIG.
　以下、この発明をより詳細に説明するために、この発明を実施するための形態について、添付の図面に従って説明する。
実施の形態１．
　図１は、実施の形態１に係る情報処理装置１の構成例を示すブロック図である。図１に示すように、ｎ個（ｎ≧２）のＦＰＧＡ１１，１２は、ＣＰＵバス３経由でＣＰＵ２に接続されている。また、ＣＰＵバス３には、フラッシュＲＯＭ４も接続されている。ＤＲＡＭ（Ｄｙｎａｍｉｃ　Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）５は、専用のメモリバス６経由でＣＰＵ２に接続されている。 Hereinafter, in order to explain the present invention in more detail, modes for carrying out the present invention will be described with reference to the accompanying drawings.
Embodiment 1 FIG.
FIG. 1 is a block diagram illustrating a configuration example of the information processing apparatus 1 according to the first embodiment. As shown in FIG. 1, n (n ≧ 2) FPGAs 11 and 12 are connected to the CPU 2 via the CPU bus 3. A flash ROM 4 is also connected to the CPU bus 3. A DRAM (Dynamic Random Access Memory) 5 is connected to the CPU 2 via a dedicated memory bus 6.
　実施の形態１では、ＦＰＧＡの個数によらず、フラッシュＲＯＭ４を１個だけ使用する。また、フラッシュＲＯＭ４からＦＰＧＡへコンフィギュレーションデータを書き込むダウンロード制御回路は、ＣＰＵ２以外に必要ない。 In Embodiment 1, only one flash ROM 4 is used regardless of the number of FPGAs. Further, a download control circuit for writing configuration data from the flash ROM 4 to the FPGA is not required other than the CPU 2.
　以下では、２個のＦＰＧＡ１１，１２が搭載された情報処理装置１を例に用いて、実施の形態１を説明する。 Hereinafter, the first embodiment will be described using the information processing apparatus 1 on which two FPGAs 11 and 12 are mounted as an example.
　図２は、実施の形態１に係る情報処理装置１におけるコンフィギュレーションの流れを示す図である。コンフィギュレーションデータの流れは、破線で示す。ＣＰＵバス３はパラレルバスであり、ＣＰＵ２に接続された側から途中で分岐してＦＰＧＡ１１，１２に接続されている。 FIG. 2 is a diagram showing a configuration flow in the information processing apparatus 1 according to the first embodiment. The flow of configuration data is indicated by a broken line. The CPU bus 3 is a parallel bus, and is branched halfway from the side connected to the CPU 2 and connected to the FPGAs 11 and 12.
　図２では、データバス幅３２ｂｉｔのＣＰＵバス３を使用する。ＣＰＵバス３のうち、「ＤＡＴ＜１５．．０＞」と表記した下位１６ｂｉｔのコンフィギュレーション用データバスをＦＰＧＡ１１に接続し、「ＤＡＴ＜３１．．１６＞」と表記した上位１６ｂｉｔのコンフィギュレーション用データバスをＦＰＧＡ１２に接続する。また、「ＣＳ＊」と表記したチップセレクト用の制御バスを、２個のＦＰＧＡ１１，１２に共通で接続する。ＣＰＵ２は、チップセレクト用の制御バスの信号値を切り替えて、ＦＰＧＡ１１，１２を読み書き可能状態にする。
　この構成により、ＣＰＵ２は、ＣＰＵバス３のうち、コンフィギュレーション用データバスの下位１６ｂｉｔを通じてＦＰＧＡ１１へコンフィギュレーションデータを書き込むと同時に、上位１６ｂｉｔを通じてＦＰＧＡ１２へコンフィギュレーションデータを書き込むことが可能である。 In FIG. 2, a CPU bus 3 having a data bus width of 32 bits is used. Of the CPU bus 3, a lower 16-bit configuration data bus denoted as “DAT <15.0>” is connected to the FPGA 11, and an upper 16-bit configuration denoted as “DAT <31.16>”. Connect the data bus to the FPGA 12. Further, a chip select control bus denoted as “CS *” is commonly connected to the two FPGAs 11 and 12. The CPU 2 switches the signal value of the control bus for chip selection to make the FPGAs 11 and 12 ready for reading and writing.
With this configuration, the CPU 2 can write configuration data to the FPGA 11 through the lower 16 bits of the configuration data bus in the CPU bus 3 and simultaneously write configuration data to the FPGA 12 through the upper 16 bits.
　なお、図２ではコンフィギュレーションクロック供給用の制御バスは図示を省略している。スレーブパラレルモードの場合、ＣＰＵ２からＦＰＧＡ１１，１２へコンフィギュレーションクロックを供給し、このクロックに合わせてＦＰＧＡ１１，１２へのコンフィギュレーションデータの書き込みが行われる。 In FIG. 2, the control bus for supplying the configuration clock is not shown. In the slave parallel mode, a configuration clock is supplied from the CPU 2 to the FPGAs 11 and 12, and configuration data is written to the FPGAs 11 and 12 in accordance with this clock.
　図３は、実施の形態１のフラッシュＲＯＭ４におけるコンフィギュレーションデータのメモリマップを示す図である。ＦＰＧＡ１１のコンフィギュレーションデータ２１と、ＦＰＧＡ１２のコンフィギュレーションデータ２２は、フラッシュＲＯＭ４に格納されている。
　フラッシュＲＯＭ４のうち、コンフィギュレーション用データバス下位１６ｂｉｔ（０～１５ｂｉｔ）に対応するアドレスにＦＰＧＡ１１のコンフィギュレーションデータ２１を格納し、コンフィギュレーション用データバス上位１６ｂｉｔ（１６～３１ｂｉｔ）に対応するアドレスにＦＰＧＡ１２のコンフィギュレーションデータ２２を格納し、結合しておく。ベースアドレスは、ＦＰＧＡ１１，１２のコンフィギュレーションデータ２１，２２を格納する際の開始アドレスを示す。複数のＦＰＧＡそれぞれについて、ＦＰＧＡと接続されたコンフィギュレーション用データバス幅ごとのデータバスに対応するアドレスに、当該ＦＰＧＡ用のコンフィギュレーションデータを格納しておくことがポイントである。 FIG. 3 is a diagram showing a memory map of configuration data in the flash ROM 4 of the first embodiment. The configuration data 21 of the FPGA 11 and the configuration data 22 of the FPGA 12 are stored in the flash ROM 4.
In the flash ROM 4, the configuration data 21 of the FPGA 11 is stored at an address corresponding to the lower 16 bits (0 to 15 bits) of the configuration data bus, and the FPGA 12 is stored at an address corresponding to the upper 16 bits (16 to 31 bits) of the configuration data bus. The configuration data 22 is stored and combined. The base address indicates a start address when the configuration data 21 and 22 of the FPGAs 11 and 12 are stored. For each of the plurality of FPGAs, the point is to store the configuration data for the FPGA at an address corresponding to the data bus for each width of the configuration data bus connected to the FPGA.
　図３の例の場合、コンフィギュレーションデータ２１は、図２に「ＤＡＴ＜１５．．０＞」と表記したデータバスを通じてＦＰＧＡ１１へ出力される。並行して、コンフィギュレーションデータ２２が、「ＤＡＴ＜３１．．１６＞」と表記したデータバスを通じてＦＰＧＡ１２へ出力される。 In the case of the example in FIG. 3, the configuration data 21 is output to the FPGA 11 through the data bus denoted as “DAT <15.0>” in FIG. In parallel, the configuration data 22 is output to the FPGA 12 through a data bus denoted as “DAT <31..16>”.
　これに対し、上記特許文献１のように、１個のフラッシュＲＯＭから２個のＦＰＧＡへ順次コンフィギュレーションデータを書き込む構成の場合を、図４に示す。ＦＰＧＡ１１，１２のそれぞれはコンフィギュレーション用データバス幅が１６ｂｉｔであるため、フラッシュＲＯＭ４のうち、コンフィギュレーション用データバス０～１５ｂｉｔに対応するアドレスにＦＰＧＡ１１，１２のコンフィギュレーションデータ２１，２２が順番に格納されている。
　図４の例の場合、まず、コンフィギュレーションデータ２１が、１６ｂｉｔ幅のコンフィギュレーション用データバスを通じてＦＰＧＡ１１へ出力される。その後、コンフィギュレーションデータ２２が、１６ｂｉｔ幅のコンフィギュレーション用データバスを通じてＦＰＧＡ１２へ出力される。その結果、図３と図４とでコンフィギュレーションデータ２１，２２の合計データ量が同じでも、図３に比べ図４では格納アドレスが２倍になるため、書き込み回数も２倍になり、コンフィギュレーション時間が長くなる。 On the other hand, FIG. 4 shows a configuration in which configuration data is sequentially written from one flash ROM to two FPGAs as in Patent Document 1 described above. Since each of the FPGAs 11 and 12 has a configuration data bus width of 16 bits, the configuration data 21 and 22 of the FPGAs 11 and 12 are sequentially stored in the addresses corresponding to the configuration data buses 0 to 15 bits in the flash ROM 4. Has been.
In the case of the example of FIG. 4, first, the configuration data 21 is output to the FPGA 11 through a configuration data bus having a 16-bit width. Thereafter, the configuration data 22 is output to the FPGA 12 through a configuration data bus having a 16-bit width. As a result, even if the total data amount of the configuration data 21 and 22 is the same in FIG. 3 and FIG. 4, the storage address is doubled in FIG. 4 compared to FIG. The time will be longer.
　図５は、実施の形態１に係る情報処理装置１によるＦＰＧＡコンフィギュレーション方法を示すフローチャートである。ＣＰＵ２は、ＣＰＵバス３を通じてフラッシュＲＯＭ４からコンフィギュレーションデータ２１，２２を読み出し（ステップＳＴ１）、メモリバス６を通じてＤＲＡＭ５へ展開する（ステップＳＴ２）。そして、ＣＰＵ２は、ＤＲＡＭ５へ展開したコンフィギュレーションデータ２１，２２を、メモリバス６を通じて読み出し、ＣＰＵバス３を通じてＦＰＧＡ１１，１２に同時に書き込む。このシーケンスは、すべてＣＰＵ２が行うソフトウエアの処理であり、このＣＰＵ２以外にハードウエアを必要としない。また、複数のＦＰＧＡに対してコンフィギュレーションデータを同時に書き込むため、コンフィギュレーションデータ書き込みは１回でよい。 FIG. 5 is a flowchart showing the FPGA configuration method by the information processing apparatus 1 according to the first embodiment. The CPU 2 reads the configuration data 21 and 22 from the flash ROM 4 through the CPU bus 3 (step ST1), and expands it to the DRAM 5 through the memory bus 6 (step ST2). Then, the CPU 2 reads the configuration data 21 and 22 expanded in the DRAM 5 through the memory bus 6 and simultaneously writes them into the FPGAs 11 and 12 through the CPU bus 3. This sequence is all software processing performed by the CPU 2, and no hardware other than the CPU 2 is required. In addition, since configuration data is simultaneously written to a plurality of FPGAs, the configuration data may be written only once.
　以上の説明では、２個のＦＰＧＡを使用する場合を例にしたが、ＣＰＵバス３のＦＰＧＡに接続するコンフィギュレーション用データバス幅を変更することで、３個以上のＦＰＧＡにも対応可能である。
　一般には、ＦＰＧＡのコンフィギュレーション用データバス幅は１６ｂｉｔまたは８ｂｉｔが多い。ＣＰＵバス３のデータバス幅を３２ｂｉｔにした場合、コンフィギュレーション用データバス幅８ｂｉｔのＦＰＧＡを最大４個、同時にコンフィギュレーションすることが可能である。この例を図６と図７に示す。 In the above description, the case where two FPGAs are used is taken as an example. However, by changing the configuration data bus width connected to the FPGA of the CPU bus 3, it is possible to support three or more FPGAs. .
In general, there are many 16-bit or 8-bit data bus widths for FPGA configuration. When the data bus width of the CPU bus 3 is 32 bits, it is possible to simultaneously configure up to four FPGAs having a configuration data bus width of 8 bits. Examples of this are shown in FIGS.
　図６に示すように、ＣＰＵバス３のデータバス幅３２ｂｉｔのうち、下位側から数えて０～７ｂｉｔの計８ｂｉｔのデータバスをＦＰＧＡ１１に接続し、８～１５ｂｉｔの計８ｂｉｔのデータバスをＦＰＧＡ１２に接続し、１６～２３ｂｉｔの計８ｂｉｔのデータバスをＦＰＧＡ１３に接続し、２３～３１ｂｉｔの計８ｂｉｔのデータバスをＦＰＧＡ１４に接続する。この構成の場合、図７に示すように、フラッシュＲＯＭ４のうち、下位側から数えて０～７ｂｉｔに対応するアドレスへＦＰＧＡ１１のコンフィギュレーションデータ２１を格納し、８～１５ｂｉｔに対応するアドレスへＦＰＧＡ１２のコンフィギュレーションデータ２２を格納し、１６ｂｉｔ～２３ｂｉｔに対応するアドレスへＦＰＧＡ１３のコンフィギュレーションデータ２３を格納し、２４～３１ｂｉｔに対応するアドレスへＦＰＧＡ１４のコンフィギュレーションデータ２４を格納し、結合しておく。 As shown in FIG. 6, among the data bus width 32 bits of the CPU bus 3, a total of 8 bits of data buses of 0 to 7 bits counted from the lower side are connected to the FPGA 11, and a total of 8 bits of 8 to 15 bits are connected to the FPGA 12. Connect a total of 8 bits of data bus of 16 to 23 bits to the FPGA 13 and connect a total of 8 bits of data bus of 23 to 31 bits to the FPGA 14. In the case of this configuration, as shown in FIG. 7, the configuration data 21 of the FPGA 11 is stored in the address corresponding to 0 to 7 bits counted from the lower side in the flash ROM 4, and the FPGA 12 is stored in the address corresponding to 8 to 15 bits. The configuration data 22 is stored, the configuration data 23 of the FPGA 13 is stored at addresses corresponding to 16 bits to 23 bits, and the configuration data 24 of the FPGA 14 is stored at addresses corresponding to 24 to 31 bits.
　また、データバス幅が異なるＦＰＧＡが混在しても構わない。この例を図８と図９に示す。
　図８に示すように、ＣＰＵバス３のデータバス幅３２ｂｉｔのうち、下位側から数えて０～１５ｂｉｔの計１６ｂｉｔのデータバスをＦＰＧＡ１１に接続し、１６～２３ｂｉｔの計８ｂｉｔのデータバスをＦＰＧＡ１２に接続し、２４～３１ｂｉｔの計８ｂｉｔのデータバスをＦＰＧＡ１３に接続する。この構成の場合、図９に示すように、フラッシュＲＯＭ４のうち、下位側から数えて０～１５ｂｉｔに対応するアドレスへＦＰＧＡ１１のコンフィギュレーションデータ２１を格納し、１６～２３ｂｉｔに対応するアドレスへＦＰＧＡ１２のコンフィギュレーションデータ２２を格納し、２４～３１ｂｉｔに対応するアドレスへＦＰＧＡ１３のコンフィギュレーションデータ２３を格納し、結合しておく。 Also, FPGAs having different data bus widths may be mixed. Examples of this are shown in FIGS.
As shown in FIG. 8, among the data bus width 32 bits of the CPU bus 3, a total of 16 bits of data buses of 0 to 15 bits counted from the lower side are connected to the FPGA 11, and a total of 8 bits of data buses of 16 to 23 bits are connected to the FPGA 12. Connect a 24-bit to 8-bit data bus to the FPGA 13 in total. In the case of this configuration, as shown in FIG. 9, the configuration data 21 of the FPGA 11 is stored in an address corresponding to 0 to 15 bits counted from the lower side in the flash ROM 4, and the FPGA 12 is stored in an address corresponding to 16 to 23 bits. The configuration data 22 is stored, and the configuration data 23 of the FPGA 13 is stored at an address corresponding to 24 to 31 bits and combined.
　図６と図７の構成、または図８と図９の構成において、ＦＰＧＡのコンフィギュレーション用データバス幅の合計値がＣＰＵバス３のデータバス幅以下であるなら、ＦＰＧＡのコンフィギュレーション用データバス幅および個数を自由に変更可能である。ＣＰＵバス３のデータバス幅が３２ｂｉｔの場合、２個のＦＰＧＡ（１６ｂｉｔデータバス幅のＦＰＧＡ２個、または８ｂｉｔデータバス幅のＦＰＧＡ２個）、３個のＦＰＧＡ（１６ｂｉｔデータバス幅のＦＰＧＡ１個と８ｂｉｔデータバス幅のＦＰＧＡ２個）、４個のＦＰＧＡ（８ｂｉｔデータバス幅のＦＰＧＡ４個）といった組み合わせが可能である。
　さらに、データバス幅６４ｂｉｔ、１６ｂｉｔなどのＣＰＵバス３を使用する場合にも、上記同様、ＦＰＧＡのコンフィギュレーション用データバス幅および個数を自由に変更可能である。
　なお、ＦＰＧＡのコンフィギュレーション用のデータバス幅は様々あるが、コンフィギュレーション時間を短縮するには、より大きなデータバス幅を採用することが望ましい。 6 and 7, or in the configurations of FIGS. 8 and 9, if the total value of the FPGA configuration data bus width is less than or equal to the data bus width of the CPU bus 3, the FPGA configuration data bus width And the number can be changed freely. When the data bus width of the CPU bus 3 is 32 bits, two FPGAs (two FPGAs having a 16-bit data bus width, or two FPGAs having a 8-bit data bus width), three FPGAs (one FPGA having a 16-bit data bus width and 8-bit data) A combination of two FPGAs having a bus width and four FPGAs (four FPGAs having an 8-bit data bus width) is possible.
Further, when the CPU bus 3 having a data bus width of 64 bits or 16 bits is used, the configuration data bus width and the number of FPGAs can be freely changed as described above.
Although there are various data bus widths for FPGA configuration, it is desirable to employ a larger data bus width in order to shorten the configuration time.
　図１～図９の説明では、コンフィギュレーションデータを格納するメモリとしてフラッシュＲＯＭを用いたが、その他のメモリであってもよい。電源を切ってもデータが消失しない不揮発性メモリであって、データバス幅がＣＰＵバスと同じかそれ以上のメモリが望ましい。また、コンフィギュレーションデータの書き込みを制御するプロセッサとしてＣＰＵを用いたが、その他のプロセッサであってもよい。 In the description of FIGS. 1 to 9, the flash ROM is used as the memory for storing the configuration data, but other memories may be used. A non-volatile memory in which data is not lost even when the power is turned off, and a memory having a data bus width equal to or larger than the CPU bus is desirable. Further, although the CPU is used as the processor for controlling the writing of the configuration data, other processors may be used.
　以上より、実施の形態１によれば、情報処理装置１は、複数のＦＰＧＡ１１，１２と、複数のＦＰＧＡ１１，１２をコンフィギュレーションするための複数のコンフィギュレーションデータ２１，２２を格納したフラッシュＲＯＭ４と、フラッシュＲＯＭ４に格納された複数のコンフィギュレーションデータ２１，２２を複数のＦＰＧＡ１１，１２に書き込むＣＰＵ２と、ＣＰＵ２側から分岐して複数のＦＰＧＡ１１，１２に接続するＣＰＵバス３とを備える。ＣＰＵバス３は、ＦＰＧＡのコンフィギュレーション用データバス幅ごとに複数のＦＰＧＡ１１，１２に接続され、フラッシュＲＯＭ４は、複数のＦＰＧＡ１１，１２それぞれについて、ＦＰＧＡと接続したコンフィギュレーション用データバス幅ごとのデータバスに対応するアドレスに当該ＦＰＧＡ用のコンフィギュレーションデータを格納し、ＣＰＵ２は、複数のＦＰＧＡ１１，１２と接続したデータバスに対応する各アドレスに格納された複数のコンフィギュレーションデータ２１，２２を、ＣＰＵバス３を通じて複数のＦＰＧＡ１１，１２に同時に書き込む構成にした。ＦＰＧＡの個数によらずＣＰＵとフラッシュＲＯＭが１組あればよいので、ハードウエア規模が増大しない。また、複数のＦＰＧＡに対して同時に書き込むことができるので、コンフィギュレーション時間を短縮できる。 As described above, according to the first embodiment, the information processing apparatus 1 includes the plurality of FPGAs 11 and 12 and the flash ROM 4 that stores the plurality of configuration data 21 and 22 for configuring the plurality of FPGAs 11 and 12. A CPU 2 for writing a plurality of configuration data 21 and 22 stored in the flash ROM 4 to the plurality of FPGAs 11 and 12 and a CPU bus 3 branched from the CPU 2 side and connected to the plurality of FPGAs 11 and 12 are provided. The CPU bus 3 is connected to a plurality of FPGAs 11 and 12 for each FPGA configuration data bus width, and the flash ROM 4 is a data bus for each configuration data bus width connected to the FPGA for each of the plurality of FPGAs 11 and 12. The configuration data for the FPGA is stored in the address corresponding to the CPU bus, and the CPU 2 stores the plurality of configuration data 21 and 22 stored in each address corresponding to the data bus connected to the plurality of FPGAs 11 and 12 in the CPU bus. 3, a plurality of FPGAs 11 and 12 are simultaneously written. Since only one CPU and flash ROM are required regardless of the number of FPGAs, the hardware scale does not increase. In addition, since it is possible to simultaneously write to a plurality of FPGAs, the configuration time can be shortened.
　なお、本発明はその発明の範囲内において、実施の形態の任意の構成要素の変形、または実施の形態の任意の構成要素の省略が可能である。 In the present invention, any component of the embodiment can be modified or any component of the embodiment can be omitted within the scope of the invention.
　この発明に係る情報処理装置は、ＦＰＧＡのコンフィギュレーション時間を短縮するようにしたので、複数のＦＰＧＡが搭載されたカーナビゲーション装置などに用いるのに適している。 Since the information processing apparatus according to the present invention shortens the FPGA configuration time, it is suitable for use in a car navigation apparatus equipped with a plurality of FPGAs.
　１　情報処理装置、２　ＣＰＵ（プロセッサ）、３　ＣＰＵバス（データバス）、４　フラッシュＲＯＭ（メモリ）、５　ＤＲＡＭ、６　メモリバス、１１～１４　ＦＰＧＡ、２１～２４　コンフィギュレーションデータ。 1 Information processing device, 2 CPU (processor), 3 CPU bus (data bus), 4 Flash ROM (memory), 5 DRAM, 6 memory bus, 11-14 FPGA, 21-24 configuration data.

Claims (2)

  1. 　複数のＦＰＧＡと、
    　前記複数のＦＰＧＡをコンフィギュレーションする複数のコンフィギュレーションデータを格納したメモリと、
    　前記メモリに格納された前記複数のコンフィギュレーションデータを前記複数のＦＰＧＡに書き込むプロセッサと、
    　前記プロセッサ側から分岐して前記複数のＦＰＧＡに接続するデータバスとを備え、
    　前記データバスは、ＦＰＧＡのコンフィギュレーション用データバス幅ごとに前記複数のＦＰＧＡに接続され、
    　前記メモリは、前記複数のＦＰＧＡそれぞれについて、ＦＰＧＡと接続した前記コンフィギュレーション用データバス幅ごとのデータバスに対応するアドレスに当該ＦＰＧＡ用のコンフィギュレーションデータを格納し、
    　前記プロセッサは、前記複数のＦＰＧＡと接続したデータバスに対応する各アドレスに格納された前記複数のコンフィギュレーションデータを、前記データバスを通じて前記複数のＦＰＧＡに同時に書き込むことを特徴とする情報処理装置。     Multiple FPGAs;
    A memory storing a plurality of configuration data for configuring the plurality of FPGAs;
    A processor that writes the plurality of configuration data stored in the memory to the plurality of FPGAs;
    A data bus branched from the processor side and connected to the plurality of FPGAs,
    The data bus is connected to the plurality of FPGAs for each configuration data bus width of the FPGA.
    For each of the plurality of FPGAs, the memory stores configuration data for the FPGA at an address corresponding to a data bus for each width of the configuration data bus connected to the FPGA.
    The information processing apparatus, wherein the processor simultaneously writes the plurality of configuration data stored at each address corresponding to a data bus connected to the plurality of FPGAs to the plurality of FPGAs through the data bus.
  2. 　分岐したデータバスを介して複数のＦＰＧＡと接続されているプロセッサが、メモリに格納されている複数のコンフィギュレーションデータを、前記複数のＦＰＧＡに書き込むＦＰＧＡコンフィギュレーション方法であって、
    　前記データバスは、ＦＰＧＡのコンフィギュレーション用データバス幅ごとに前記複数のＦＰＧＡに接続され、前記メモリには、前記複数のＦＰＧＡそれぞれについて、ＦＰＧＡと接続した前記コンフィギュレーション用データバス幅ごとのデータバスに対応するアドレスに当該ＦＰＧＡ用のコンフィギュレーションデータが格納されており、前記プロセッサは、前記複数のＦＰＧＡと接続したデータバスに対応する各アドレスに格納された前記複数のコンフィギュレーションデータを、前記データバスを通じて前記複数のＦＰＧＡに同時に書き込むことを特徴とするＦＰＧＡコンフィギュレーション方法。     A FPGA configuration method in which a processor connected to a plurality of FPGAs via branched data buses writes a plurality of configuration data stored in a memory to the plurality of FPGAs.
    The data bus is connected to the plurality of FPGAs for each configuration data bus width of the FPGA, and the memory includes a data bus for each of the configuration data bus widths connected to the FPGA for each of the plurality of FPGAs. Configuration data for the FPGA is stored at an address corresponding to the processor, and the processor converts the configuration data stored at each address corresponding to a data bus connected to the plurality of FPGAs to the data. An FPGA configuration method, wherein the plurality of FPGAs are simultaneously written through a bus.
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US20040093488A1 (en) * 2002-11-07 2004-05-13 Joseph Horanzy Method and apparatus for configuring a programmable logic device
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