WO2016096263A1

WO2016096263A1 - Semiconductor device

Info

Publication number: WO2016096263A1
Application number: PCT/EP2015/076351
Authority: WO
Inventors: Jaroslav HOMOLA; Jiri Podzemsky; Tomas LOUZECKY
Original assignee: Abb Technology Ag
Priority date: 2014-12-19
Filing date: 2015-11-11
Publication date: 2016-06-23

Abstract

The invention relates to a semiconductor device (1) for a high power circuit breaker being shaped as a truncated cone comprising a first circular surface side (4) and an opposed, parallel second circular surface side (5), whereby the semiconductor device (1) comprising a plurality of wafers (8, 12) of semiconductor material, arranged with their circular sides parallel to the first circular surface side (4) and the second circular surface side (5), and connected firmly together by alloying, and whereby at least two of the wafers (8) comprise an internal layer (9) of basic semiconductor material arranged between two side layers (10, 11), the first side layer (10) comprising the same electrical conductivity than the internal layer (9) and the second side layer (11) comprising the opposite type of electrical conductivity than the internal layer (9) thus forming with the internal layer (9) a p-n junction.

Description

Semiconductor device

Technical Field

The invention relates to a semiconductor device adapted for use in a high power circuit breaker and being shaped as a truncated cone comprising a first circular surface side and an opposed, parallel second circular surface side. The invention further relates to a high power circuit breaker for interrupting a current comprising the semiconductor device. The invention furthermore relates to a method for manufacturing the semiconductor device.

Background Art

In certain electrical circuits there is a need to interrupt currents with a magnitude of 10⁴ A, while a reverse recovery voltage may have a magnitude of 10⁴ V. A typical example of such circuit breaker application involves peak surge currents of 36 kA and peak reverse recovery voltages of 18 kV. Conventional circuit breakers work with mechanical arc interruption of current with SFe or vacuum insulation. Due to the high currents and voltages, the circuit breakers often suffer with contact burn off and limited endurance. Thus, semiconductor based circuit breakers with arc free interruption of currents have been used in order to overcome such problems. In particular, diode based circuit breakers are used comprising a diode connected in parallel to a first mechanical switch and a second mechanical switch. In a circuit breaker operation, the first mechanical switch directs the current through the diode, and next the second mechanical switch interrupts the circuit at a time when there is only comparatively small reverse recovery current flowing through the diode.

However, especially when switching before mentioned surge currents of 36 kA or more followed by a reverse voltage of 18 kV such diode based circuit breakers are very difficult to design. In particular, the thickness of the semiconductor material of the diode must increase and thus the current capability and surge current capability is decreasing. For solving said problem, a proper number of diodes with a lower voltage and required surge current capability can be connected in series. Unfortunately, the cost of such solution is too high compared with the target cost for a feasible replacement of conventional mechanical circuit breakers by a semiconductor based circuit breaker. JP 2002 374618 A discloses a semiconductor circuit breaker comprising switches connected in series and a semiconductor device adapted for leading current and enabling a switch to interrupt the current. DE 29 50 073 A1 discloses a stacked assembly of diodes connected in series.

Disclosure of Invention

Therefore, it is an object of the invention to provide semiconductor device for a high power circuit breaker that solves before mentioned problem. In particular, it is an object of the invention to provide a semiconductor device for a high power circuit breaker that provides at a competitive cost and size a possibility for switching surge currents of 36 kA or more.

The object of the invention is solved by the features of the independent claims. Pre- ferred embodiments are detailed in the dependent claims.

Thus, the object is solved by a semiconductor device for a high power circuit breaker being shaped as a truncated cone comprising a first circular surface side and an opposed, parallel second circular surface side, whereby the semiconductor device comprising a plurality of wafers of semiconductor material, arranged with their circular sides parallel to the first circular surface side and the second circular surface side, and connected firmly together by alloying, and whereby at least two of the wafers comprise an internal layer of basic semiconductor material arranged between two side layers, the first side layer comprising the same electrical conductivity than the internal layer and the second side layer comprising the opposite type of electrical conductivity than the internal layer thus forming with the internal layer a p-n junction.

It is therefore a key point of the invention to provide a semiconductor device in the shape of truncated cone having a positive bevel to the p-n junctions in all wafers. Such semiconductor device can be manufactured at low cost, as no expensive materials such as Mo electrodes are required and as the manufacturing process is comparatively simple compared to prior art diode based circuit breakers comprising several high voltage diodes or diode chips connected in series. The semiconductor device can be capsulated in a standard ceramic capsule housing, while no coolers or supporting equipment are required for its proper performance in a high power circuit breaker application. The term "for a high power circuit breaker" means that the semiconductor device is dimensioned for handling currents and voltages that are present in high power applications, such as, for example, currents in an order 10⁴ A and reverse recovery voltage in an order 10⁴ V, in particular before mentioned surge currents of 36 kA or more followed by a reverse voltage of 18 kV.

Generally, the first side layers may comprise a p-type electrical conductivity, such that the internal layers also comprise a p-type electrical conductivity, while the second side layers comprise an n-type electrical conductivity. However, according to an especially preferred embodiment, the first side layers comprise an n-type electrical conductivity and the wafers are oriented with their first side layers towards the first circular surface side. Preferably all first side layers comprise an n-type electrical conductivity, while all internal layers comprise an n-type electrical conductivity and all second side layers comprise an p-type electrical conductivity. According to another preferred embodiment the diameter of the first circular surface side is smaller than the diameter of the second circular surface side. Preferably, the diameter of the p-type electrical conductivity layers, e.g. of the second side layers, is larger than the diameter of the n-type electrical conductivity layers, e.g. of the first side layers. The shape of the truncated cone advantageously provides for a positive beveling of the p-n junctions. The beveling advantageously decreases the intensity of the electrical field at the surface of the wafer. The beveling can, for example, be made mechanically by sandblasting or grinding.

In a further preferred embodiment the first circular surface side and/or the second circu- lar surface side comprise a diameter≥ 2 inch, preferably≥ 2,5 inch and most preferably ≥ 3 inch. Alternatively, the diameter can be≥ 70 mm, preferably≥ 75 mm and most preferably≥ 80 mm. Such way currents in an order 10⁴ A and reverse recovery voltage in an order 10⁴ V can be handled by the semiconductor device without destroying the semiconductor device in a circuit breaker operation e.g. when interrupting a faulty current.

According to another preferred embodiment the concentration of active dopants in all side layers of n-type electrical conductivity is higher than 10¹⁹ cm ³. This improves the voltage-ampere characteristics of the semiconductor device in a surge current mode, e.g. when switching a surge current, and advantageously prevents additional voltage drops at the alloyed surface of the n-type electrical conductivity layers. According to another preferred embodiment at least one of the wafers comprises only one layer of highly doped semiconductor material. Preferably, said wafer, also referred to as passive component in the following, comprises a low resistivity, compared to the other wafers. Such way losses generated in said wafer by the surge current are very small compared to the losses generated in the other wafers. Thus, such wafer only comprising one layer of highly doped semiconductor material advantageously provides an additional volume to the volume of the adjacent wafers and therefore increases the heat capacity of the semiconductor device. In other words, such wafer only comprising one layer of highly doped semiconductor material provides for keeping the temperature increase in the semiconductor device due to surge currents under control such that the temperature in the other wafers does not exceed a maximum operating temperature not destroying the wafers. In this regard the layer of highly doped semiconductor material preferably comprises an n-type electrical conductivity with a concentration of active dopants higher than 10¹⁹ cm ³. More preferably, the semiconductor device comprises, in an alternating order, a wafer only comprising one layer of highly doped semiconductor material followed by a wafer having two side layers and an internal layer.

According to another preferred embodiment the semiconductor device comprises a first contact layer and a second contact layer for electrically contacting the semiconductor device, the first contact layer is arranged at the first circular surface side and the second contact layer is arranged at the second circular surface side. Preferably, the first contact layer and/or the second contact layer is provided as an electrode for electrically contacting the semiconductor device, preferably as a cathode contact respectively as a anode contact.

According to another preferred embodiment all wafers comprise the same semiconductor material, preferably Silicon. In such case, the problem of bending after an alloying operation due to differences in the thermal expansion coefficients can be advantageously avoided. Further advantageously, no high clamp pressure is needed, as required for prior art solution, for making the contact layers flat. In an alternative embodiment, other semiconductor materials can be used as well.

The object of the invention is further solved by a high power circuit breaker for interrupting a current comprising the semiconductor device according to any of the previous claims, a first mechanical switch and a second mechanical switch, whereby the first mechanical switch is connected parallel to the semiconductor device and the second me- chanical switch is connected in series to the first mechanical switch and the semiconductor device being connected in parallel, and the semiconductor device is adapted for leading the current for enabling the second mechanical switch to interrupt the current in a in reverse recovery phase of the semiconductor device. When disconnecting the first mechanical switch in a circuit breaker operation, the current is directed through the semiconductor device. When the current is comparably small in the reverse recovery phase of the semiconductor device, a circuit connected to the circuit breaker can be disconnected by the second mechanical switch without stressing and thus without damaging the mechanical switches.

The object of the invention is furthermore solved by a method for manufacturing a semiconductor device for a high power circuit breaker, the method comprising the steps:

Providing multiple circular wafers of semiconductor material having all the same diameter and being arranged parallel to each other with their circular sides,

Alloying the wafers firmly together forming a column having a first circular surface side and an opposed, parallel second circular surface side,

Mechanically and/or chemically processing the column for shaping a truncated cone. Preferably, contact layers on the first circular surface side and on the second circular surface side are formed for electrically contacting the semiconductor device. Furthermore, for the truncated cone the diameter of the first circular surface side is smaller than the diameter of the second circular surface side. Moreover, the mechanically and/or chemically processed surface of the truncated cone is preferably covered by a layer of passivation material.

Preferably, all components of the semiconductor device, e.g. the wafers, are connected together in one single operation by the step of alloying. More preferably, all active and passive components of the semiconductor device, e.g. the p-n junctions, are provided from the same semiconductor material, such as Silicon. Such way, the problem of bending after an alloying operation due to difference thermal expansion coefficient is advantageously avoided. The passivation material is preferably an isolation material, such as for example silicon rubber. According to another preferred embodiment the step of alloying is conducted with a temperature of ≤ 700 ° C, preferably≤ 650 °C and/or whereby the step of mechanically and/or chemically processing comprises grinding the column. Alternatively, the column can be sandblasted for reaching the shape of a truncated cone.

According to another preferred embodiment at least two of the wafers comprise an in- ternal layer of basic semiconductor material arranged between two side layers, the first side layer comprising the same electrical conductivity than the internal layer and the second side layer comprising the opposite type of electrical conductivity than the internal layer thus forming with the internal layer a p-n junction. According to another preferred embodiment the first side layers comprise an n-type electrical conductivity, the wafers are oriented with their first side layers towards the first circular surface side and the concentration of active dopants in all side layers of n-type electrical conductivity is higher than 10¹⁹ cm ³. Preferably, the n-type electrical conductivity layers are coated by a metal layer prior to the step of alloying.

According to another preferred embodiment at least one of the wafers comprises only one layer of highly doped semiconductor material comprising an n-type electrical conductivity with a concentration of active dopants higher than 10¹⁹ cm ³. The layer of highly doped semiconductor material is preferably cut from a highly doped semiconductor crys- tal and advantageously absorbs energy losses generated by high current in the p-n junctions in order to keep the temperature below a critical value. Thus, the semiconductor device can be operated without providing a cooler or the like, as all energy is absorbed by the truncated cone. Other aspects, embodiments and/or advantages for the method are derivable for the man skilled in the art from before described semiconductor device.

These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.

Brief Description of Drawings

In the drawings:

Fig. 1 shows a part of a high power circuit breaker with a semiconductor device ac- cording to a preferred embodiment in a schematic view, Fig. 2 shows the semiconductor device of Fig. 1 in a schematic view, and

Fig. 3 shows semiconductor device of Fig. 1 in a further preferred embodiment in a schematics view.

5

Detailed Description of the Invention

Fig. 1 shows a part of a high power circuit breaker comprising a semiconductor device 1 l o according to a preferred embodiment in a schematic view for demonstrating the adapted use of the semiconductor device 1. A first mechanical switch 2 is connected parallel to the semiconductor device 1 , whereby a second mechanical switch 3 is connected in series to the first mechanical switch 2 and the semiconductor device 1 is connected in parallel. In a circuit breaker operation, e.g. if a faulty current flows, the second mechanical 15 switch 3 can interrupt the current in a in reverse recovery phase of the semiconductor device 1 i.e. when the current is small, as shown in the diagram in Fig. 1 .

Prior art diode based circuit breakers face the problem that with an increasing voltage of the diode the thickness of the semiconductor material of the diode has to increase, 20 which in turn means that the current capability and surge current capability decreases.

The semiconductor device 1 as described below solves said problem, as being capable of handling surge currents of 36 kA followed by reverse voltages 18 kV. With the proposed semiconductor device 1 the mechanical switches 2, 3 are not stressed and thus not damaged by disconnecting a current.

25

In particular, as shown in Fig. 2, the semiconductor device 1 according to the preferred embodiment of the invention is shaped as a truncated cone and comprises a first circular surface side 4 and an opposed, parallel second circular surface side 5. For electrically contacting the semiconductor device 1 a first contact layer 6 as electrode is arranged 30 at the first circular surface side 4 and a second contact layer 7 as electrode is arranged at the second circular surface side 5. The semiconductor device 1 comprises, arranged in-between the first contact layer 6 and the second contact layer 7, five wafers 8 of the same semiconductor material i.e. Silicon in the current embodiment.

35 As can be further seen from Fig. 2, the wafers 8 are each arranged with their circular sides parallel to the first circular surface side 4 and the second circular surface side 5. The wafers 8 are firmly alloyed together at a temperature of around 650 °C and thereafter grinded for forming the shape of the truncated cone, whereby the diameter of the first circular surface side 4 is smaller than the diameter of the second circular surface side 5. Alternatively, the wafers 8 can be mechanically and/or chemically processed by other means known from prior art for forming the truncated cone.

All wafers 8 as shown in Fig. 2 comprise an internal layer 9 of basic semiconductor material each arranged in-between each two side layers 10, 1 1 . The first side layer 10 comprises the same electrical conductivity than the internal layer 9, while the second side layer 1 1 comprises the opposite type of electrical conductivity than the internal layer 9. Thereby, the second side layer 1 1 forms with the internal layer 9 a p-n junction. In the preferred embodiment as shown in Fig. 2, all first side layers 10 and all internal layers 9 comprise an n-type electrical conductivity, whereby all second side layers 1 1 comprise a p-type electrical conductivity. Furthermore, the concentration of active dopants in first side layers 1 1 is higher than 10¹⁹ cm ³. As can be seen further, all wafers 8 are oriented with their respective first side layers 10 towards the first circular surface side 4.

In normal circumstances, no current flows through the semiconductor device 1 and the semiconductor device 1 is at ambient temperature. At a first step of a circuit breaker op- eration, for example if a faulty current is detected, the first mechanical switch 2 opens and a surge current flows through the semiconductor device 1. The current generates losses in the wafers 8 of the semiconductor device 1. Due to the losses the temperature of the wafers 8 increases. The higher the reverse voltage VR, of a wafer 8, the higher the thickness of the wafer 8 and the higher are the losses generated by the surge cur- rent.

Taking into consideration the specific weight and specific heat capacity of the semiconductor material of the wafers 8, the wafers 8 are designed the way that the losses generated by the surge current in each wafer 8 do not increase the temperature of the wafer 8 above a maximum temperature T_jmax and thus each wafer 8 can hold the reverse recovery voltage VR, in the second step of a circuit breaker operation. No external cooling is thus necessary for a proper function of the semiconductor device 1. It is thereby assumed that the wafers 8 are designed such that each of them can block a maximum reverse voltage VR, at the maximum temperature Tjmax. The sum of the VR, of all wafers 8 must be higher than the required reverse voltage VR_max for the semiconductor device 1 . Fig. 3 shows a semiconductor device 1 in a further preferred embodiment in a schematic view. The semiconductor device 1 comprises three wafers 8, which each comprise an internal layer 9 of basic semiconductor material arranged in-between two side layers 10, 1 1 as shown in Fig. 2. In-between each two wafers 8 a further wafer 12 is provided, which only comprises one layer of highly doped semiconductor material having an n- type electrical conductivity with a concentration of active dopants higher than 10¹⁹ cm ³. This way, a passive component in form of the further wafer 12 is provided between each two of the further wafer 8. The function of the semiconductor device 1 as shown in Fig. 2 is similar to the embodiment described before in regard to Fig. 1. The passive components in form of the further wafer 12 are made of highly doped semiconductor material with low resistivity, so that the losses generated in the passive components by the surge current are very small compare to the losses generated in the active components of the wafers 8 i.e. in the p-j junctions. The advantageous feature of the passive component 12 lies in providing an additional volume to the volume of adjacent active components and thus increasing heat capacity of the semiconductor device 1. Passive components 12 of a proper thickness thus enable to keep the increase the temperature in the semiconductor device 1 by surge current under control such that the temperature in active components does not exceed I jmax-

The concentration of active dopants of higher than 10¹⁹ cm ³ in the first side layer 10 and in the further wafer 12 improves the voltage-ampere characteristics of the semiconductor device 1 in the surge current mode and does not create additional voltage drops at the alloyed surface of n-type. The shape of truncated cone advantageously forms a positive beveling at the surface of p-n junctions of all the active components in the semiconductor device 1 such that the diameter of the p-type side layers is larger than the diameter of the n-type side layer in each active component i.e. in each wafer 8. Reference sign list

Semiconductor device 1

First mechanical switch 2 Second mechanical switch 3

First circular surface side 4

Second circular surface side 5

First contact layer 6

Second contact layer 7 Wafer 8

Internal layer 9

First side layer 10

Second side layer 1 1

Further wafer 12

Claims

1. Semiconductor device (1 ) for a high power circuit breaker being shaped as a truncated cone comprising a first circular surface side (4) and an opposed, parallel second circular surface side (5), whereby

the semiconductor device (1 ) comprising a plurality of wafers (8, 12) of semiconductor material, arranged with their circular sides parallel to the first circular surface side (4) and the second circular surface side (5), and connected firmly together by alloying, and whereby

at least two of the wafers (8) comprise an internal layer (9) of basic semiconductor material arranged between two side layers (10, 1 1 ), the first side layer (10) comprising the same electrical conductivity than the internal layer (9) and the second side layer (1 1 ) comprising the opposite type of electrical conductivity than the internal layer (9) thus forming with the internal layer (9) a p-n junction.

2. Semiconductor device (1 ) according the previous claim, whereby the first side layers (10) comprise an n-type electrical conductivity and the wafers (8) are oriented with their first side layers (10) towards the first circular surface side (4).

3. Semiconductor device (1 ) according to any of the previous claims, whereby the diameter of the first circular surface side (4) is smaller than the diameter of the second circular surface side (5).

4. Semiconductor device (1 ) according to any of the previous claims, whereby the first circular surface side (4) and/or the second circular surface side (5) comprise a diameter≥ 2 inch, preferably≥ 2,5 inch and most preferably≥ 3 inch.

5. Semiconductor device (1 ) according to claim 2, whereby the concentration of active dopants in all side layers (10) of n-type electrical conductivity is higher than 10¹⁹ cm ³.

6. Semiconductor device (1 ) according to any of the previous claims, whereby at least one of the wafers (12) comprises only one layer of highly doped semiconductor material.

7. Semiconductor device (1 ) according the previous claim, whereby the layer of highly doped semiconductor material comprises an n-type electrical conductivity with a concentration of active dopants higher than 10¹⁹ cm ³.

8. Semiconductor device (1 ) according to any of the previous claims, whereby the semiconductor device (1 ) comprises a first contact layer (6) and a second contact layer (7) for electrically contacting the semiconductor device (1 ), the first contact layer (6) is arranged at the first circular surface side (4) and the second contact layer (7) is arranged at the second circular surface side (5).

9. Semiconductor device (1 ) according to any of the previous claims, whereby all wafers (8) comprise the same semiconductor material, preferably Silicon.

10. High power circuit breaker for interrupting a current comprising the semiconductor device (1 ) according to any of the previous claims, a first mechanical switch (2) and a second mechanical switch (3), whereby

the first mechanical switch (2) is connected parallel to the semiconductor device (1 ) and the second mechanical switch (3) is connected in series to the first mechanical switch (2) and the semiconductor device (1 ) being connected in parallel, and

the semiconductor device (1 ) is adapted for leading the current for enabling the second mechanical switch (3) to interrupt the current in a in reverse recovery phase of the semiconductor device (1 ).

1 1. Method for manufacturing a semiconductor device (1 ) for a high power circuit breaker, the method comprising the steps:

Providing multiple circular wafers (8, 12) of semiconductor material having all the same diameter and being arranged parallel to each other with their circular sides, Alloying the wafers (8, 12) firmly together forming a column having a first circular surface side (4) and an opposed, parallel second circular surface side (5), Mechanically and/or chemically processing the column for shaping a truncated cone.

12. Method according to the previous method claim, whereby contact layers (6, 7) on the first circular surface side (4) and on the second circular surface side (5) are formed for electrically contacting the semiconductor device (1 ), whereby for the truncated cone the diameter of the first circular surface side (4) is smaller than the diameter of the second circular surface side (5), and whereby the mechanically and/or chemically processed surface of the truncated cone is covered by a layer of passivation material.

13. Method according to the previous method claim, whereby the step of alloying is conducted with a temperature of≤ 700 °C, preferably≤ 650 °C and/or whereby the step of mechanically and/or chemically processing comprises grinding the column.

14. Method according to any of the previous method claims, whereby at least two of the wafers (8) comprise an internal layer (9) of basic semiconductor material arranged between two side layers (10. 1 1 ), the first side layer (10) comprising the same electrical conductivity than the internal layer (9) and the second side layer (1 1 ) comprising the opposite type of electrical conductivity than the internal layer (9) thus forming with the internal layer (9) a p-n junction.

15. Method according to the previous method claim, whereby the first side layers (10) comprise an n-type electrical conductivity, the wafers (8) are oriented with their first side layers (10) towards the first circular surface side (4) and the concentration of active dopants in all side layers (10) of n-type electrical conductivity is higher than 10¹⁹ cm ³.

16. Method according to any of the previous method claims, whereby at least one of the wafers (12) comprises only one layer of highly doped semiconductor material comprising an n-type electrical conductivity with a concentration of active dopants higher than 10¹⁹ cm ³.