WO2016078248A1 - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

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Publication number
WO2016078248A1
WO2016078248A1 PCT/CN2015/073340 CN2015073340W WO2016078248A1 WO 2016078248 A1 WO2016078248 A1 WO 2016078248A1 CN 2015073340 W CN2015073340 W CN 2015073340W WO 2016078248 A1 WO2016078248 A1 WO 2016078248A1
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Prior art keywords
via hole
electrode
aperture
array substrate
thin film
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PCT/CN2015/073340
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English (en)
French (fr)
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方金钢
辛龙宝
孙宏达
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京东方科技集团股份有限公司
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Priority to US14/785,830 priority Critical patent/US10090368B2/en
Priority to EP15793663.4A priority patent/EP3223315B1/en
Publication of WO2016078248A1 publication Critical patent/WO2016078248A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present invention relates to the field of display, and in particular, to an array substrate, a preparation method thereof, and a display device.
  • An AMOLED (Active Matrix Organic Light Emitting Diode) display device is an important structural form of an OLED display device.
  • the AMOLED display device includes an array substrate and a package substrate, wherein a plurality of display units are formed on the array substrate. .
  • the display unit includes a switching thin film transistor 3, a driving thin film transistor 4, and an OLED.
  • the gate G of the switching thin film transistor 3 is electrically connected to the gate line 1
  • the drain D is electrically connected to the data line 2
  • the source S is electrically connected to the gate G of the driving thin film transistor 4, and the drain D of the driving thin film transistor 4 is driven.
  • the source S is electrically connected to the V dd line (power signal line), and the source S is electrically connected to the anode or cathode of the OLED.
  • the gate line 1, the data line 2, and the V dd line are simultaneously loaded with an electrical signal, the source S of the driving thin film transistor 4 drives the OLED to emit light.
  • the active layer 13 is generally formed of IGZO (Indium Gallium Zinc Oxide) having a higher electron mobility, and is generally formed on the active layer 13.
  • the barrier layer 14 is etched to prevent erosion of the active layer 13 by the drain 17 and the source 18 when wetted by the acid solution.
  • the drain 17 and the source 18 of the switching thin film transistor 3 are electrically connected to the active layer 13 through the first via 15, and the source 18 of the switching thin film transistor 3 passes through the second via 16 and
  • the first electrode 20 is electrically connected, and the first electrode 20 is electrically connected to the gate 11 of the driving thin film transistor 4.
  • the first via 15 and the second via 16 are simultaneously etched by using a mask. Since the first via 15 is formed, only one layer, that is, the etch barrier layer 14, is etched to realize the source and the source.
  • the second via 16 requires etching two layers, that is, the etch barrier layer 14 and the gate insulating layer 12, and then forming a second via hole during etching
  • the first via 15 is overetched, that is, the first via 15 penetrates through the etch barrier layer 14 and the gate insulating layer 12, so that both the source 18 and the drain 17 are electrically connected to the gate 11, resulting in a switch.
  • the thin film transistor failed.
  • the conventional fabrication process employs two mask processes or a halftone mask and a gray tone mask to form the first via and the second via.
  • the use of two masking processes increases the complexity of the process and increases the production cost; while using a halftone mask and a gray mask, although only one masking process is used, the halftone mask and the gray mask are used. Expensive, also increases production costs.
  • Embodiments of the present invention provide an array substrate, a preparation method thereof, and a display device, which solve the problem that a first via hole and a second via hole are formed by simultaneously etching a mask while using a mask in a conventional fabrication process. Over-etching, the problem of failure of the thin film transistor.
  • an array substrate including: a substrate and a switching thin film transistor and a first electrode formed on the substrate, the switching thin film transistor including a gate, a gate insulating layer, an active layer, and etching a barrier layer and a source and a drain, wherein the etch barrier layer is formed with a first via hole, and the source and the drain are electrically connected to the active layer through the first via hole;
  • the etch barrier layer and the gate insulating layer cover the first electrode, and the etch barrier layer and the gate insulating layer are formed with a second via hole at a position corresponding to the first electrode, the switch film A source of the transistor is electrically connected to the first electrode through the second via, and a maximum aperture of the first via is not greater than a minimum aperture of the second via.
  • a method for fabricating an array substrate including: forming a switching thin film transistor and a first electrode on a substrate; wherein forming the switching thin film transistor and the first electrode specifically includes: forming a gate on the substrate, a first electrode, a gate insulating layer, an active layer, and an etch barrier layer, wherein the etch barrier layer and the gate insulating layer cover the first electrode; forming a first via and a second via, wherein The first via is formed at a bit corresponding to the active layer Placed through the etch barrier layer; the second via is formed at a position corresponding to the first electrode, penetrates the etch barrier layer and the gate insulating layer; forms a source and a drain, wherein the source and the drain a pole is electrically connected to the active layer through the first via, a source of the switching thin film transistor is electrically connected to the first electrode through the second via; a maximum aperture of the first via Not larger than the minimum aperture of the second via.
  • a display device comprising: the array substrate of any of the above.
  • Embodiments of the present invention provide an array substrate, a method for fabricating the same, and a display device.
  • the embodiment of the present invention provides a second via by setting a maximum aperture of a first via and a minimum aperture of a second via.
  • the aperture is larger than the first via hole
  • the first via hole and the second via hole are simultaneously etched by using one mask, since the first via hole has a small aperture, the ultraviolet light is irradiated to the first via hole during the exposure process. If the diffracting is easy to cause the exposure energy to decrease, the exposure degree of the first via hole is smaller than that of the second via hole in the same time; then, the development processing is performed, and since the first via hole has a small aperture, the development of the reaction in the first via hole is performed.
  • the liquid is less, resulting in incomplete reaction.
  • a small amount of photoresist remains in the hole after the first via hole is developed, and the second via hole has a larger aperture and is subjected to development processing.
  • the etch stop layer is completely exposed; then etching the etch stop layer exposed by the second via hole, and then performing ashing treatment to remove the residual photoresist in the first via hole, and simultaneously etching
  • the etch stop layer of the via hole and the gate insulating layer of the second via hole thereby avoiding the simultaneous etching of the first via hole and the second via hole by using one mask, thereby causing the first via hole to be overetched for a long time, so that the film The problem of transistor failure.
  • FIG. 1 is a schematic diagram of a driving circuit of a conventional AMOLED light emitting device
  • FIG. 2 is a schematic structural view of a conventional AMOLED array substrate
  • FIG. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 4 is a flow chart of a method for preparing an array substrate according to an embodiment of the present invention Schematic diagram
  • FIG. 5 is a schematic structural view of an array substrate formed in step S01 of FIG. 4;
  • FIG. 6 is a schematic structural view of an array substrate formed in step S02 of FIG. 4;
  • FIG. 7 is a schematic structural view of an array substrate formed in step S03 of FIG. 4;
  • FIG. 8 is a schematic structural view of an array substrate formed in step S04 of FIG. 4;
  • FIG. 9 is a schematic structural view of an array substrate formed in step S05 of FIG. 4;
  • FIG. 10 is a schematic structural view of an array substrate formed in step S06 of FIG. 4;
  • FIG. 11 is a schematic structural view of an array substrate formed in step S07 of FIG. 4;
  • step S05 of FIG. 4 is a schematic flow chart of the preparation method of step S05 of FIG. 4;
  • FIG. 13 is a schematic structural view of an array substrate formed in step S051 of FIG. 12;
  • FIG. 14 is a schematic structural view of an array substrate formed in step S052 of FIG. 12;
  • 15 is a schematic structural view of an array substrate formed in step S053 of FIG. 12;
  • FIG. 16 is a schematic structural view of the array substrate formed in step S054 of FIG.
  • An embodiment of the present invention provides an array substrate, as shown in FIG. 3, comprising: a substrate 10 and a first thin film transistor 30 and a first electrode 20 formed on the substrate 10,
  • the first thin film transistor 30 includes a gate electrode 11 , a gate insulating layer 12 , an active layer 13 , an etch stop layer 14 , a source electrode 18 , and a drain electrode 17 .
  • the first via hole 15 is formed on the etch barrier layer 14 .
  • the source 18 and the drain 17 are electrically connected to the active layer 13 through the first via 15; the etch stop layer 14 and the gate insulating layer 12 cover the first electrode 20, and the etch barrier layer 14 and the gate insulating layer 12 correspond to A second via 16 is formed at a position of the electrode 20, and the maximum aperture of the first via 15 is not greater than the minimum aperture of the second via 16.
  • the difference between the minimum aperture of the second via hole 16 and the maximum aperture of the first via hole is not less than 2 ⁇ m;
  • the ratio of the minimum aperture of the second via 16 to the maximum aperture of the first via is not less than 1.3.
  • the theoretically formed via hole is a cylinder, that is, the cross section along the axial direction of the via hole is a rectangle, and in practice, due to the limitation of the process and the like, the formed via hole may be a step, that is, along the via hole.
  • the cross section in the axial direction is trapezoidal, or other irregular shape, and the via hole diameter actually formed has a maximum value and a minimum value.
  • the specific locations of the first via holes and the second via holes in the array substrate are not specifically limited in the embodiment of the present invention.
  • the first via and the second via may be located in the same pixel unit, or the first via may be located in the pixel unit, the second via may be located at an edge position of the array substrate, or the like.
  • the maximum aperture of the first via hole is not greater than the minimum aperture of the second via hole, and the minimum aperture of the second via hole and the first via hole in the case where the maximum aperture of the first via hole is less than or equal to 8 ⁇ m.
  • the difference between the maximum apertures is not less than 2 ⁇ m.
  • the maximum aperture of the first via is 3 ⁇ m, and the minimum aperture of the second via is greater than or equal to 5 ⁇ m; the maximum aperture of the first via is 8 ⁇ m, and the second The minimum aperture of the via is greater than or equal to 10 ⁇ m.
  • the ratio of the minimum aperture of the second via hole to the maximum aperture of the first via hole is not less than 1.3, specifically, for example, the maximum aperture of the first via hole When it is 10 ⁇ m, the minimum aperture of the second via hole is greater than or equal to 13 ⁇ m.
  • the aperture ranges of the first via hole and the second via hole are specific The appropriate amount can be adjusted according to the sensitivity, the exposure amount, the development time, and the like of the photoresist material, as long as the above range is satisfied, and is not specifically limited herein.
  • the array substrate may be an array substrate of a liquid crystal display device, and the first electrode may be a gate line lead.
  • the source and the drain are electrically connected to the active layer through the first via.
  • the gate line lead at the second via position may be electrically connected to the signal line through a metal electrode layer formed at the second via position.
  • the first via hole is located in the pixel unit, and the second via hole may be located at an edge position of the array substrate or the like.
  • the array substrate further includes a second thin film transistor, wherein the first thin film transistor may be a switching thin film transistor, the second thin film transistor may be a driving thin film transistor, and the first electrode is a gate of the second thin film transistor, and the first thin film transistor
  • the source may be electrically connected to the gate of the second thin film transistor, so that the first thin film transistor controls the gate voltage of the second thin film transistor, and the formed array substrate can be applied to the AMOLED light emitting device, and the AMOLED light emitting device has a reaction speed. Fast, high contrast, power saving and so on.
  • the first electrode is a connection electrode
  • the source of the first thin film transistor is electrically connected to the gate of the second thin film transistor through the first electrode
  • the embodiment and the drawing of the present invention are described in detail as an example.
  • the first via and the second via may be located in the same pixel unit.
  • an array substrate provided by the embodiment of the present invention has a larger aperture of the first via hole 15 and a minimum aperture of the second via hole 16 so that the aperture of the second via hole 16 is larger than the first hole.
  • the via hole 15 is formed by simultaneously etching a first via hole 15 and a second via hole 16 by using a mask. Since the first via hole 15 has a small aperture, ultraviolet rays are irradiated to the first via hole 15 during exposure.
  • the exposure energy is reduced, and the exposure of the first via 15 is smaller than that of the second via 16 in the same time; then, the development processing is performed, and since the aperture of the first via 15 is small, the first via 15 is The developing solution participating in the reaction is less, resulting in incomplete reaction.
  • a small amount of photoresist remains in the hole after the first via hole 15 is subjected to development processing, and the second via hole 16 has a smaller aperture.
  • the etch stop layer 14 in the hole is completely exposed; then the etch stop layer 14 exposed by the second via hole 16 is etched, and then ashing is performed to remove the residual light in the hole of the first via hole 15 Engraved, Etching the etch stop layer 14 of the first via 15 and the gate insulating layer 12 of the second via 16, thereby avoiding the simultaneous etching of the first via 15 and the second via 16 using a mask
  • the first via 15 is over-etched for a long time, causing the first thin film transistor 30 to fail.
  • the first via hole 15 and the second via hole 16 are simultaneously etched by using one mask, the first via hole can also be precisely controlled by precisely controlling the exposure time of the first via hole 15 and the second via hole 16
  • the exposure degree of 15 is smaller than that of the second via hole 16; then, the development time of the first via hole 15 and the second via hole 16 can be precisely controlled, so that the first via hole 15 is not fully developed, and the second via hole 16 is completely developed;
  • a small amount of photoresist remains in the hole of the first via hole 15, and the photoresist in the hole of the second via hole 16 is further removed and the etch barrier layer 14 in the hole is completely exposed. come out.
  • the maximum aperture of the first via may range from 3-8 ⁇ m.
  • the minimum aperture of the second via hole is 5 ⁇ m; in the case where the maximum aperture of the first via hole is 8 ⁇ m, the second via hole The minimum aperture is 10 ⁇ m.
  • the material of the active layer of the array substrate may be an oxide, and specifically, may be an oxide of a single element such as In (indium), Ga (gallium), Zn (zinc), or Sn (tin), or Any combination of these elements, such as IGZO (indium gallium zinc oxide), ITZO (indium tin zinc oxide); may also be nitrogen oxides, specifically, may be In, Ga, Zn, Sn, etc.
  • the single element oxynitride may also be an oxynitride of any combination of these elements, such as ZnON (zinc oxynitride); or may be a phosphide such as InP (indium phosphide) or GaP (gallium phosphide). ) or IGZP (indium gallium zinc phosphide).
  • An embodiment of the present invention provides a method for fabricating an array substrate, comprising: forming a first thin film transistor and a first electrode on a substrate; wherein forming the first thin film transistor and the first electrode specifically includes: forming a gate on the substrate a first electrode, a gate insulating layer, an active layer, and an etch barrier layer, wherein the etch barrier layer and the gate insulating layer cover the first electrode; forming a first via hole and a second via hole, wherein the first via hole Formed in correspondence a source layer is disposed through the etch barrier layer, a second via hole is formed at a position corresponding to the first electrode, penetrates the etch barrier layer and the gate insulating layer, and a source and a drain are formed, wherein the source and the drain are formed
  • the first via is electrically connected to the active layer; wherein the maximum aperture of the first via is not greater than the smallest aperture of the second via.
  • a difference between a minimum aperture of the second via hole and a maximum aperture of the first via hole is not less than 2 ⁇ m; in the first via hole
  • the ratio of the minimum aperture of the second via to the maximum aperture of the first via is not less than 1.3.
  • Embodiments of the present invention provide a method for fabricating an array substrate.
  • the embodiment of the present invention provides a larger aperture of the first via hole and a smaller aperture of the second via hole, so that the aperture of the second via hole is larger than the first Through-holes, when a first via hole and a second via hole are simultaneously etched by using one mask, since the first via hole has a small aperture, diffraction is likely to occur when ultraviolet rays are irradiated to the first via hole during exposure.
  • the exposure energy is reduced, the exposure degree of the first via hole is smaller than that of the second via hole in the same time; then, the development processing is performed, and since the first via hole has a small aperture, the developer participating in the reaction in the first via hole is less. The reaction is incomplete.
  • the exposure time of the first via hole and the second via hole can be precisely controlled, so that the exposure degree of the first via hole is less than a second via hole; then, by precisely controlling the development time of the first via hole and the second via hole, the first via hole is not fully developed, and the second via hole is completely developed; thus, after the above two-step process, A small amount of photoresist remains in one via hole, and the photoresist in the second via hole is further removed and The etch stop layer in the hole is completely exposed.
  • the maximum aperture of the first via may range from 3-8 ⁇ m.
  • the minimum aperture of the second via hole is 5 ⁇ m; in the case where the maximum aperture of the first via hole is 8 ⁇ m, the second via hole The minimum aperture is 10 ⁇ m.
  • the etch barrier layer and the gate insulating layer cover the first electrode, and the gate electrode and the first electrode may be formed in the same layer, may be simultaneously formed in the same layer by one patterning process, or formed by different patterning processes. On the same floor. In the embodiment of the invention, the gate and the first electrode are simultaneously formed in the same layer by one patterning process as an example.
  • the first thin film transistor is used as the switching thin film transistor, and the first electrode is electrically connected to the source of the first thin film transistor as an example.
  • the method for preparing the display panel is as shown in FIG. 4 , and the method includes:
  • Step S01 as shown in FIG. 5, the gate electrode 11 and the first electrode 20 are formed on the substrate 10 by one patterning process.
  • the substrate 10 can be made of materials such as Corning, Asahi Glass, and quartz glass, and has a thickness of 50-1000 ⁇ m.
  • the gate electrode 11 and the first electrode 20 may be made of a metal such as Al (aluminum), Mo (molybdenum), Cr (chromium), Cu (copper), or Ti (titanium), and have a thickness of 200 to 1000 nm.
  • a gate insulating layer 12 is formed on the substrate 10 by a CVD (Chemical Vapor Deposition) method, wherein the gate insulating layer 12 may be a single layer or a multilayer film of SiOx or SiNx. The thickness is 100-500 nm. And the gate insulating layer 12 covers the gate electrode 11 and the first electrode 20.
  • CVD Chemical Vapor Deposition
  • an active layer 13 is formed, wherein the active layer 13 may be an oxide film such as IGZO, ITZO or ZnON, an amorphous semiconductor film having a thickness of 5-150 nm, and a mobility higher than 10 m. 2 /vs.
  • oxide film such as IGZO, ITZO or ZnON
  • amorphous semiconductor film having a thickness of 5-150 nm, and a mobility higher than 10 m. 2 /vs.
  • Step S04 as shown in FIG. 8, an etch stop layer 14 is formed, wherein the etch stop layer 14 may be a SiOx film having a thickness of 50-200 nm.
  • the etch barrier layer 14 covers the gate electrode 11 and the first electrode 20.
  • Step S05 as shown in FIG. 9, forming a first via hole 15 and a second via hole 16, which
  • the first via hole 15 is formed at a position corresponding to the active layer 13 and penetrates through the etch barrier layer 14.
  • the second via hole 16 is formed at a position corresponding to the first electrode 20, penetrating the etch barrier layer 14 and the gate insulating layer.
  • Step S06 as shown in FIG. 10, a source 18 and a drain 17 are formed.
  • the source 18 and the drain 17 are electrically connected to the active layer 13 through the first via 15, and the source 18 passes through the second via 16 and
  • An electrode 20 is electrically connected, wherein the source 18 and the drain 17 may be made of metal such as Al (aluminum), Mo (molybdenum), Cr (chromium), Cu (copper), Ti (titanium), etc., and have a thickness of 5- 250nm.
  • a passivation layer 23 covering the source electrode 18 and the drain electrode 17 is formed.
  • the passivation layer 23 may be made of an insulating material such as silicon oxide, silicon nitride or an organic material.
  • the preparation method of the above step S05 is as shown in FIG. 12, and the method includes:
  • Step S051 as shown in FIG. 13, a photoresist 21 covering the etch barrier layer 14 is formed, and the photoresist 21 is exposed and developed by the mask 22, and a photoresist removal region and a photoresist are formed after development.
  • a resistive region and a photoresist portion remaining region wherein the photoresist removing region correspondingly forms the second via hole 16, the photoresist portion remaining region correspondingly forms the first via hole 15, and the photoresist 21 may have a thickness of 1.5-3 ⁇ m High sensitivity organic film.
  • the width of the transparent region of the mask 22 at the position corresponding to the second via 16 may be about 10 ⁇ m, and the width of the transparent region of the mask 22 at the position corresponding to the first via 15 may be about 8 ⁇ m.
  • the total exposure amount of the first via hole 15 is smaller than that of the second via hole 16.
  • Step S052 as shown in FIG. 14, etching the etch stop layer 14 at the second via location.
  • the etching time is precisely controlled, and as shown in FIG. 11, the gate insulating layer 12 at the second via hole position can be slightly inscribed.
  • Step S053 as shown in FIG. 15, the photoresist 21 is subjected to ashing treatment to remove
  • the photoresist 21 at the location of the first via 15 precisely controls the ashing time, completely exposing the etch stop layer 14 at the first via location.
  • Step S054 as shown in FIG. 16, etching the etch barrier layer 14 at the position of the first via hole 15 and the gate insulating layer 12 at the position of the second via hole 16.
  • step S055 as shown in FIG. 9, the photoresist 21 is peeled off.
  • a first via 15 and a second via 16 are formed on the substrate 10.
  • An embodiment of the present invention provides a display device including the array substrate of any of the above.
  • the display device may be a display device such as a liquid crystal display, an electronic paper, an OLED display, or any display product or component such as a television, a digital camera, a mobile phone, a tablet computer or the like including the display device.
  • the display device may include a substrate substrate, a package substrate, and a support between the substrate substrate and the package substrate, wherein the substrate substrate includes a thin film transistor, an OLED, and a package substrate sequentially formed on the substrate.
  • a black matrix (BM) and a color filter are sequentially formed on a transparent substrate to prevent light leakage between adjacent pixels.
  • the display device belongs to a top emission structure, that is, OLED light is emitted from the package substrate.
  • the display device may further include a base substrate and a package substrate, and the base substrate and the package substrate do not need to be joined, and are directly bonded by a sealant.
  • the base substrate comprises a thin film transistor sequentially formed on the substrate, a low temperature color filter using a special process and material, and an OLED, and a filler may be added on the OLED to block diffusion of water and oxygen.
  • the display device belongs to a bottom emission structure, that is, OLED light is emitted from the substrate substrate.

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Abstract

一种阵列基板及其制备方法、显示装置，涉及显示领域，该阵列基板包括形成在衬底（10）上的第一薄膜晶体管（30）和第一电极（20），第一薄膜晶体管（30）包括栅极（11）、栅绝缘层（12）、有源层（13）、刻蚀阻挡层（14），刻蚀阻挡层（14）上形成第一过孔（15），刻蚀阻挡层（14）和栅绝缘层（12）在对应第一电极（20）的位置形成第二过孔（16），第一过孔（15）的最大孔径不大于第二过孔（16）的最小孔径。

Description

阵列基板及其制备方法、显示装置 技术领域
本发明涉及显示领域，尤其涉及一种阵列基板及其制备方法、显示装置。
背景技术
AMOLED(Active Matrix Organic Light Emitting Diode，有源矩阵有机发光二极管)显示装置是OLED显示装置的一种重要结构形式，AMOLED显示装置包括阵列基板和封装基板，其中，阵列基板上形成有多个显示单元。如图1所示，显示单元包括开关薄膜晶体管3、驱动薄膜晶体管4以及OLED。其中，开关薄膜晶体管3的栅极G与栅线1电连接，漏极D与数据线2电连接，源极S与驱动薄膜晶体管4的栅极G电连接；驱动薄膜晶体管4的漏极D与Vdd线(电源信号线)电连接，源极S与OLED的阳极或阴极电连接。当栅线1、数据线2以及Vdd线同时加载电信号，驱动薄膜晶体管4的源极S驱动OLED发光。
在上述AMOLED显示装置中，如图2所示，有源层13一般采用电子迁移率更高的IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)形成，则一般还在有源层13上形成刻蚀阻挡层14，以阻止漏极17和源极18在被酸液湿刻时对有源层13的侵蚀。
具体的，如图2所示，开关薄膜晶体管3的漏极17和源极18通过第一过孔15与有源层13电连接，开关薄膜晶体管3的源极18通过第二过孔16与第一电极20电连接，第一电极20与驱动薄膜晶体管4的栅极11电连接。在制备过程中，第一过孔15和第二过孔16采用一道掩膜同时刻蚀形成，由于形成第一过孔15只需刻蚀一层即刻蚀阻挡层14，即可实现源极和漏极与有源层的电连接；形成第二过孔16需要刻蚀两层即刻蚀阻挡层14和栅极绝缘层12，则在刻蚀形成第二过孔 16时，第一过孔15会出现过刻，即第一过孔15贯穿刻蚀阻挡层14以及栅绝缘层12，从而使得源极18和漏极17均与栅极11电连接，导致开关薄膜晶体管失效。
为了避免上述问题，传统的制作工艺中采用两道掩膜工序或者采用半色调掩膜和灰色调掩膜形成第一过孔和第二过孔。但采用两道掩膜工序增加了工艺的复杂性，提高了生产成本；采用半色调掩膜和灰色调掩膜虽然仅用了一道掩膜工序，但半色调掩膜板和灰色调掩膜板昂贵，同样提高了生产成本。
发明内容
本发明的实施例提供一种阵列基板及其制备方法、显示装置，解决了传统的制作工艺中采用一道掩膜同时刻蚀形成第一过孔和第二过孔而导致第一过孔长时间过刻，使得薄膜晶体管失效的问题。
为达到上述目的，本发明的实施例采用如下技术方案：
一方面，提供了一种阵列基板，包括：衬底以及形成在所述衬底上的开关薄膜晶体管和第一电极，所述开关薄膜晶体管包括栅极、栅绝缘层、有源层、刻蚀阻挡层以及源极和漏极，其中，所述刻蚀阻挡层上形成有第一过孔，所述源极和所述漏极通过所述第一过孔与所述有源层电连接；所述刻蚀阻挡层和所述栅绝缘层覆盖所述第一电极，所述刻蚀阻挡层和所述栅绝缘层在对应第一电极的位置处形成有第二过孔，所述开关薄膜晶体管的源极通过所述第二过孔与所述第一电极电连接，所述第一过孔的最大孔径不大于所述第二过孔的最小孔径。另一方面，提供了一种阵列基板的制备方法，包括：在衬底上形成开关薄膜晶体管和第一电极；其中，形成开关薄膜晶体管和第一电极具体包括：在衬底上形成栅极、第一电极、栅绝缘层、有源层以及刻蚀阻挡层，其中，所述刻蚀阻挡层和所述栅绝缘层覆盖所述第一电极；形成第一过孔和第二过孔，其中，所述第一过孔形成在对应有源层的位 置处，贯穿刻蚀阻挡层；第二过孔形成在对应第一电极的位置处，贯穿刻蚀阻挡层和栅绝缘层；形成源极和漏极，其中，所述源极和所述漏极通过所述第一过孔与所述有源层电连接，所述开关薄膜晶体管的源极通过所述第二过孔与所述第一电极电连接；所述第一过孔的最大孔径不大于所述第二过孔的最小孔径。
再一方面，提供了一种显示装置，包括：上述任一项所述的阵列基板。
本发明的实施例提供了一种阵列基板及其制备方法、显示装置，本发明实施例通过设置第一过孔的最大孔径和第二过孔的最小孔径的尺寸关系，使得第二过孔的孔径大于第一过孔，则在采用一道掩膜同时刻蚀形成第一过孔和第二过孔时，由于第一过孔孔径较小，在曝光过程中，紫外线照射到第一过孔时容易发生衍射导致曝光能量减少，则相同时间内第一过孔的曝光程度小于第二过孔；接着进行显影处理，由于第一过孔孔径较小，则在第一过孔内参与反应的显影液较少，导致反应不完全，这样，由于上述两方面原因，使得第一过孔经过显影处理后孔内会残余少量光刻胶，而第二过孔由于孔径较大，经过显影处理后孔内的刻蚀阻挡层完全暴露出来；接着刻蚀第二过孔暴露的刻蚀阻挡层，然后进行灰化处理去除第一过孔孔内残余的光刻胶，再同时刻蚀第一过孔的刻蚀阻挡层和第二过孔的栅绝缘层，从而避免了采用一道掩膜同时刻蚀形成第一过孔和第二过孔而导致第一过孔长时间过刻，使得薄膜晶体管失效的问题。
附图说明
图1为传统的AMOLED发光器件的驱动电路原理图；
图2为传统的AMOLED阵列基板的结构示意图；
图3为本发明实施例提供的一种阵列基板的结构示意图；
图4为本发明实施例提供的一种阵列基板制备方法的流 程示意图；
图5为图4步骤S01形成的阵列基板的结构示意图；
图6为图4步骤S02形成的阵列基板的结构示意图；
图7为图4步骤S03形成的阵列基板的结构示意图；
图8为图4步骤S04形成的阵列基板的结构示意图；
图9为图4步骤S05形成的阵列基板的结构示意图；
图10为图4步骤S06形成的阵列基板的结构示意图；
图11为图4步骤S07形成的阵列基板的结构示意图；
图12为图4步骤S05的制备方法的流程示意图；
图13为图12步骤S051形成的阵列基板的结构示意图；
图14为图12步骤S052形成的阵列基板的结构示意图；
图15为图12步骤S053形成的阵列基板的结构示意图；
图16为图12步骤S054形成的阵列基板的结构示意图。
附图标记：
1-栅线；2-数据线；3-开关薄膜晶体管；4-驱动薄膜晶体管；10-衬底；11-栅极；12-栅极绝缘层；13-有源层；14-刻蚀阻挡层；15-第一过孔；16-第二过孔；17-漏极；18-源极；19-驱动薄膜晶体管栅极；20-第一电极；21-光刻胶；22-掩膜板；23-钝化层；30-第一薄膜晶体管。
具体实施方式
下面结合附图和实施例，对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明，但不用来限制本发明的范围。
本发明实施例提供了一种阵列基板，如图3所示，包括：衬底10以及形成在衬底10上的第一薄膜晶体管30和第一电极20， 第一薄膜晶体管30包括栅极11、栅绝缘层12、有源层13、刻蚀阻挡层14、源极18和漏极17，其中，刻蚀阻挡层14上形成有第一过孔15，源极18和漏极17通过第一过孔15与有源层13电连接；刻蚀阻挡层14和栅绝缘层12覆盖第一电极20，刻蚀阻挡层14和栅绝缘层12在对应第一电极20位置处形成有第二过孔16，第一过孔15的最大孔径不大于第二过孔16的最小孔径。
根据本发明的一些实施例，在第一过孔15的最大孔径小于等于8μm的情况下，第二过孔16的最小孔径与第一过孔的最大孔径的差不小于2μm；在第一过孔15的最大孔径大于8μm且小于等于14μm的情况下，第二过孔16的最小孔径与第一过孔的最大孔径的比值不小于1.3。
需要说明的是，理论上形成的过孔是圆柱体，即沿过孔的轴线方向的截面是矩形，而在实际中由于工艺等条件限制，形成的过孔可以是梯台，即沿过孔的轴线方向的截面是梯形，或者是其他不规则形状，则实际中形成的过孔孔径存在最大值与最小值。另外，第一过孔和第二过孔在阵列基板的具***置本发明实施例不作具体限定。例如，第一过孔和第二过孔可以是位于同一像素单元内，或者，第一过孔可以是位于像素单元内，第二过孔可以是位于阵列基板的边缘位置处等。
本发明实施例中，第一过孔的最大孔径不大于第二过孔的最小孔径，在第一过孔的最大孔径小于等于8μm的情况下，第二过孔的最小孔径与第一过孔的最大孔径的差不小于2μm，具体的，例如，第一过孔的最大孔径为3μm，则第二过孔的最小孔径大于或等于5μm；第一过孔的最大孔径为8μm，则第二过孔的最小孔径大于或等于10μm。
在第一过孔的最大孔径大于8μm且小于等于14μm的情况下，第二过孔的最小孔径与第一过孔的最大孔径的比值不小于1.3，具体的，例如第一过孔的最大孔径为10μm，则第二过孔的最小孔径大于或等于13μm。
进一步需要说明的是，第一过孔和第二过孔的孔径范围具体 可以根据光刻胶材料的感度、曝光量、显影时间等进行适量调整，只要满足上述范围要求即可，这里不作具体限定。
上述阵列基板可以是液晶显示装置的阵列基板，则第一电极可以是栅线引线，在形成源极和漏极的过程中，源极和漏极通过第一过孔与有源层电连接，第二过孔位置处的栅线引线可以通过形成在第二过孔位置处的金属电极层与信号线电连接。此时，第一过孔位于像素单元内，第二过孔可以是位于阵列基板的边缘位置处等。
或者，阵列基板还包括第二薄膜晶体管，其中，第一薄膜晶体管可以是开关薄膜晶体管，第二薄膜晶体管可以是驱动薄膜晶体管，则第一电极为第二薄膜晶体管的栅极，第一薄膜晶体管的源极可以是与第二薄膜晶体管的栅极电连接，从而实现第一薄膜晶体管控制第二薄膜晶体管的栅极电压，这样形成的阵列基板可应用于AMOLED发光器件，AMOLED发光器件具有反应速度快、对比度高、省电等特点。或者，第一电极为连接电极，第一薄膜晶体管的源极通过第一电极与第二薄膜晶体管的栅极电连接，且本发明实施例及附图以此为例进行详细说明。且在以上情况中，第一过孔和第二过孔可以是位于同一像素单元内。
如图3所示，本发明实施例提供的一种阵列基板通过设置第一过孔15的最大孔径和第二过孔16的最小孔径的尺寸关系，使得第二过孔16的孔径大于第一过孔15，则在采用一道掩膜同时刻蚀形成第一过孔15和第二过孔16时，由于第一过孔15孔径较小，在曝光过程中，紫外线照射到第一过孔15时容易发生衍射导致曝光能量减少，则相同时间内第一过孔15的曝光程度小于第二过孔16；接着进行显影处理，由于第一过孔15孔径较小，则在第一过孔15内参与反应的显影液较少，导致反应不完全，这样，由于上述两方面原因，使得第一过孔15经过显影处理后孔内会残余少量光刻胶，而第二过孔16由于孔径较大，经过显影处理后孔内的刻蚀阻挡层14完全暴露出来；接着刻蚀第二过孔16暴露的刻蚀阻挡层14，然后进行灰化处理去除第一过孔15孔内残余的光刻胶， 再刻蚀第一过孔15的刻蚀阻挡层14和第二过孔16的栅绝缘层12，从而避免了采用一道掩膜同时刻蚀形成第一过孔15和第二过孔16而导致第一过孔15长时间过刻，使得第一薄膜晶体管30失效的问题。
进一步的，在采用一道掩膜同时刻蚀形成第一过孔15和第二过孔16时，还可以通过精确控制第一过孔15和第二过孔16的曝光时间，使得第一过孔15的曝光程度小于第二过孔16；接着还可以通过精确控制第一过孔15和第二过孔16的显影时间，使得第一过孔15不完全显影，第二过孔16完全显影；这样经过上述两步工艺处理后，第一过孔15孔内会残余少量光刻胶，第二过孔16孔内的光刻胶更进一步清除干净并使得孔内的刻蚀阻挡层14完全暴露出来。
可选的，考虑到实际需要和成本问题，第一过孔的最大孔径的取值范围可为3-8μm。根据本发明的一些实施例，在第一过孔的最大孔径为3μm的情况下，第二过孔的最小孔径为5μm；在第一过孔的最大孔径为8μm的情况下，第二过孔的最小孔径为10μm。
可选的，阵列基板的有源层的材料可以是氧化物，具体的，可以是In(铟)、Ga(镓)、Zn(锌)、Sn(锡)等单一元素的氧化物，也可以是这几种元素任意组合的氧化物，例如IGZO(铟镓锌氧化物)、ITZO(铟锡锌氧化物)；还可以是氮氧化物，具体的，可以是In、Ga、Zn、Sn等单一元素的氮氧化物，也可以是这几种元素任意组合的氮氧化物，例如ZnON(氮氧化锌)；还可以是磷化物，例如可以是InP(磷化铟)、GaP(磷化镓)或IGZP(铟镓锌磷化物)。
本发明实施例提供了一种阵列基板的制备方法，包括在衬底上形成第一薄膜晶体管和第一电极；其中，形成第一薄膜晶体管和第一电极具体包括：在衬底上形成栅极、第一电极、栅绝缘层、有源层以及刻蚀阻挡层，其中，刻蚀阻挡层和栅绝缘层覆盖第一电极；形成第一过孔和第二过孔，其中，第一过孔形成在对应有 源层的位置处，贯穿刻蚀阻挡层，第二过孔形成在对应第一电极的位置处，贯穿刻蚀阻挡层和栅绝缘层；形成源极和漏极，其中，源极和漏极通过第一过孔与有源层电连接；其中，第一过孔的最大孔径不大于第二过孔的最小孔径。
根据本发明的一些实施例，在第一过孔的最大孔径小于等于8μm的情况下，第二过孔的最小孔径与第一过孔的最大孔径的差不小于2μm；在第一过孔的最大孔径大于8μm且小于等于14μm的情况下，第二过孔的最小孔径与第一过孔的最大孔径的比值不小于1.3。
本发明的实施例提供了一种阵列基板的制备方法，本发明实施例通过设置第一过孔的最大孔径和第二过孔的最小孔径的尺寸关系，使得第二过孔的孔径大于第一过孔，则在采用一道掩膜同时刻蚀形成第一过孔和第二过孔时，由于第一过孔孔径较小，在曝光过程中，紫外线照射到第一过孔时容易发生衍射导致曝光能量减少，则相同时间内第一过孔的曝光程度小于第二过孔；接着进行显影处理，由于第一过孔孔径较小，则在第一过孔内参与反应的显影液较少，导致反应不完全，这样，由于上述两方面原因，使得第一过孔经过显影处理后孔内会残余少量光刻胶，而第二过孔由于孔径较大，经过显影处理后孔内的刻蚀阻挡层完全暴露出来；接着刻蚀第二过孔暴露的刻蚀阻挡层，然后进行灰化处理去除第一过孔孔内残余的光刻胶，再同时刻蚀第一过孔的刻蚀阻挡层和第二过孔的栅绝缘层，从而避免了采用一道掩膜同时刻蚀形成第一过孔和第二过孔而导致第一过孔长时间过刻，使得薄膜晶体管失效的问题。
进一步的，在采用一道掩膜同时刻蚀形成第一过孔和第二过孔时，还可以通过精确控制第一过孔和第二过孔的曝光时间，使得第一过孔的曝光程度小于第二过孔；接着还可以通过精确控制第一过孔和第二过孔的显影时间，使得第一过孔不完全显影，第二过孔完全显影；这样经过上述两步工艺处理后，第一过孔孔内会残余少量光刻胶，第二过孔孔内的光刻胶更进一步清除干净并 使得孔内的刻蚀阻挡层完全暴露出来。
可选的，考虑到实际需要和成本问题，第一过孔的最大孔径的取值范围可为3-8μm。根据本发明的一些实施例，在第一过孔的最大孔径为3μm的情况下，第二过孔的最小孔径为5μm；在第一过孔的最大孔径为8μm的情况下，第二过孔的最小孔径为10μm。本发明实施例中，刻蚀阻挡层和栅绝缘层覆盖第一电极，可以是栅极与第一电极形成在同一层，可以是通过一次构图工艺同时形成在同一层，或者通过不同构图工艺形成在同一层。本发明实施例以栅极与第一电极通过一次构图工艺同时形成在同一层为例进行说明。
下面，以第一薄膜晶体管作为开关薄膜晶体管、第一电极作为连接电极与第一薄膜晶体管的源极电连接为例具体说明该显示面板的制备方法如图4所示，所述方法包括：
步骤S01、如图5所示，通过一次构图工艺在衬底10上形成栅极11和第一电极20。其中，衬底10可以由康宁、旭硝子玻璃、石英玻璃等材质制成，厚度为50-1000μm。栅极11和第一电极20可以由Al(铝)、Mo(钼)、Cr(铬)、Cu(铜)、Ti(钛)等金属制成，厚度为200-1000nm。
步骤S02、如图6所示，采用CVD(Chemical Vapor Deposition，化学气相沉积)法在衬底10上形成栅绝缘层12，其中，栅绝缘层12可以是SiOx、SiNx的单层或多层薄膜，厚度为100-500nm。且栅绝缘层12覆盖栅极11和第一电极20。
步骤S03、如图7所示，形成有源层13，其中，有源层13可以是IGZO、ITZO或ZnON等氧化物薄膜，厚度为5-150nm的非晶态半导体薄膜，迁移率高于10m2/vs。
步骤S04、如图8所示，形成刻蚀阻挡层14，其中，刻蚀阻挡层14可以是SiOx薄膜，厚度为50-200nm。刻蚀阻挡层14覆盖栅极11和第一电极20。
步骤S05、如图9所示，形成第一过孔15和第二过孔16，其 中，第一过孔15形成在对应有源层13的位置处，贯穿刻蚀阻挡层14，第二过孔16形成在对应第一电极20的位置处，贯穿刻蚀阻挡层14和栅绝缘层12。
步骤S06、如图10所示，形成源极18和漏极17，源极18和漏极17通过第一过孔15与有源层13电连接，源极18通过第二过孔16与第一电极20电连接，其中，源极18和漏极17可以由Al(铝)、Mo(钼)、Cr(铬)、Cu(铜)、Ti(钛)等金属制成，厚度为5-250nm。
步骤S07、如图11所示，形成覆盖源极18和漏极17的钝化层23，其中，钝化层23可采用氧化硅、氮化硅及有机材料等绝缘材料制成。
进一步的，上述步骤S05制备方法如图12所示，所述方法包括：
步骤S051、如图13所示，形成覆盖刻蚀阻挡层14的光刻胶21，利用掩膜板22对光刻胶21进行曝光并进行显影，显影后形成光刻胶去除区域、光刻胶保留区域和光刻胶部分保留区域，其中，光刻胶去除区域对应形成第二过孔16，光刻胶部分保留区域对应形成第一过孔15，光刻胶21可以是厚度为1.5-3μm的高感度有机膜。
此时，掩膜板22在对应第二过孔16位置处的透光区的宽度大约可以是10μm，掩膜板22在对应第一过孔15位置处的透光区的宽度大约可以是8μm，相同时间内第一过孔15总的曝光量小于第二过孔16，经过显影处理后，第一过孔15孔内会残余光刻胶形成光刻胶部分保留，而第二过孔16孔内的刻蚀阻挡层14完全暴露经显影后被完全去除。
步骤S052、如图14所示，刻蚀第二过孔位置处的刻蚀阻挡层14。此时，精确控制刻蚀时间，如图11所示，还可以对第二过孔位置处的栅绝缘层12进行少量过刻。
步骤S053、如图15所示，对光刻胶21进行灰化处理，去除 第一过孔15位置处的光刻胶21，精确控制灰化时间，完全暴露第一过孔位置处的刻蚀阻挡层14。
步骤S054、如图16所示，刻蚀第一过孔15位置处的刻蚀阻挡层14以及第二过孔16位置处的栅绝缘层12。
步骤S055、如图9所示，剥离光刻胶21。在衬底10上形成第一过孔15和第二过孔16。
本发明的实施例提供了一种显示装置，该显示装置包括上述任一所述的阵列基板。所述显示装置可以为液晶显示器、电子纸、OLED显示器等显示器件以及包括这些显示器件的电视、数码相机、手机、平板电脑等任何具有显示功能的产品或者部件。
具体的，该显示装置可以是包括衬底基板、封装基板和位于衬底基板和封装基板之间的支撑物，其中，该衬底基板包括依次形成在衬底上的薄膜晶体管、OLED，封装基板包括依次形成在透明衬底上用来防止相邻像素间漏光的黑色矩阵(Black Matrix，BM)和彩色滤光片。该显示装置属于顶发射结构，即OLED光线从封装基板向外发射。
该显示装置还可以是包括衬底基板和封装基板，衬底基板和封装基板不需要对合，直接通过封框胶粘合。其中，该衬底基板包括依次形成在衬底上的薄膜晶体管、采用特殊工艺和材料的低温彩色滤光片、以及OLED，该OLED上还可加入填充物以阻隔水氧的扩散。该显示装置属于底发射结构，即OLED光线从衬底基板向外发射。
以上实施方式仅用于说明本发明，而并非对本发明的限制，有关技术领域的普通技术人员，在不脱离本发明的精神和范围的情况下，还可以做出各种变化和变型，因此所有等同的技术方案也属于本发明的范畴，本发明的专利保护范围应由权利要求限定。

Claims (13)

  1. 一种阵列基板，包括：衬底以及形成在所述衬底上的第一薄膜晶体管和第一电极，所述第一薄膜晶体管包括栅极、栅绝缘层、有源层、刻蚀阻挡层、源极和漏极，其中，所述刻蚀阻挡层上形成有第一过孔，所述源极和所述漏极通过所述第一过孔与所述有源层电连接；所述刻蚀阻挡层和所述栅绝缘层覆盖所述第一电极，所述刻蚀阻挡层和所述栅绝缘层在对应第一电极的位置处形成有第二过孔，所述第一过孔的最大孔径不大于所述第二过孔的最小孔径。
  2. 根据权利要求1所述的阵列基板，其中，
    在所述第一过孔的最大孔径小于等于8μm的情况下，所述第二过孔的最小孔径与所述第一过孔的最大孔径的差不小于2μm；
    在所述第一过孔的最大孔径大于8μm且小于等于14μm的情况下，所述第二过孔的最小孔径与所述第一过孔的最大孔径的比值不小于1.3。
  3. 根据权利要求1或2所述的阵列基板，其中，所述第一过孔的最大孔径的取值范围为3-8μm。
  4. 根据权利要求3所述的阵列基板，其中，在所述第一过孔的最大孔径为3μm的情况下，所述第二过孔的最小孔径为5μm；
    在所述第一过孔的最大孔径为8μm的情况下，所述第二过孔的最小孔径为10μm。
  5. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括第二薄膜晶体管，所述第一电极为所述第二薄膜晶体管的栅极，所述第一薄膜晶体管的源极通过所述第二过孔与所述第一电极电连接。
  6. 根据权利要求1所述的阵列基板，其中，所述有源层由氧化物、氮氧化物或者磷化物制成。
  7. 一种阵列基板的制备方法，其中，包括：在衬底上形 成第一薄膜晶体管和第一电极；
    其中，形成第一薄膜晶体管和第一电极包括：
    在衬底上形成栅极、第一电极、栅绝缘层、有源层以及刻蚀阻挡层，其中，所述刻蚀阻挡层和所述栅绝缘层覆盖所述第一电极；
    形成第一过孔和第二过孔，其中，所述第一过孔形成在对应所述有源层的位置处，贯穿所述刻蚀阻挡层；所述第二过孔形成在对应所述第一电极的位置处，贯穿所述刻蚀阻挡层和所述栅绝缘层；
    形成源极和漏极，其中，所述源极和所述漏极通过所述第一过孔与所述有源层电连接；
    所述第一过孔的最大孔径不大于所述第二过孔的最小孔径。
  8. 根据权利要求7所述的制备方法，其中，在所述第一过孔的最大孔径小于等于8μm的情况下，所述第二过孔的最小孔径与所述第一过孔的最大孔径的差不小于2μm；
    在所述第一过孔的最大孔径大于8μm且小于等于14μm的情况下，所述第二过孔的最小孔径与所述第一过孔的最大孔径的比值不小于1.3。
  9. 根据权利要求7所述的制备方法，其中，所述形成第一过孔和第二过孔包括：
    形成覆盖刻蚀阻挡层的光刻胶；
    利用掩膜板对所述光刻胶进行曝光和显影，显影后形成光刻胶去除区域、光刻胶保留区域和光刻胶部分保留区域，其中，光刻胶去除区域对应形成第二过孔，光刻胶部分保留区域对应形成第一过孔；
    刻蚀第二过孔位置处的刻蚀阻挡层；
    对所述光刻胶进行灰化处理，去除第一过孔位置处的光刻胶；
    刻蚀第一过孔位置处的刻蚀阻挡层以及第二过孔位置处的栅绝缘层；
    剥离光刻胶。
  10. 根据权利要求7所述的制备方法，其中，所述源极通过所述第二过孔与所述第一电极电连接。
  11. 根据权利要求7所述的制备方法，其中，所述第一过孔的最大孔径的取值范围为3-8μm。
  12. 根据权利要求11所述的制备方法，其中，在所述第一过孔的最大孔径为3μm的情况下，所述第二过孔的最小孔径为5μm；
    在所述第一过孔的最大孔径为8μm的情况下，所述第二过孔的最小孔径为10μm。
  13. 一种显示装置，包括：权利要求1-6任一项所述的阵列基板。
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US20160358991A1 (en) 2016-12-08
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