WO2016076300A1 - Photoelectric conversion element - Google Patents

Photoelectric conversion element Download PDF

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Publication number
WO2016076300A1
WO2016076300A1 PCT/JP2015/081562 JP2015081562W WO2016076300A1 WO 2016076300 A1 WO2016076300 A1 WO 2016076300A1 JP 2015081562 W JP2015081562 W JP 2015081562W WO 2016076300 A1 WO2016076300 A1 WO 2016076300A1
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Prior art keywords
amorphous semiconductor
semiconductor layer
type amorphous
region
photoelectric conversion
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PCT/JP2015/081562
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French (fr)
Japanese (ja)
Inventor
督章 國吉
神川　剛
真臣 原田
敏彦 酒井
柳民 鄒
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シャープ株式会社
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Publication of WO2016076300A1 publication Critical patent/WO2016076300A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT® solar cells; solar cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present disclosure relates to a photoelectric conversion element.
  • JP-T-2010-503222 discloses an example of a back junction solar cell in which a passivation layer and a back contact layer are formed on the back surface of a semiconductor substrate.
  • a passivation layer is formed on the entire back surface of the semiconductor substrate, an opening is formed in the passivation layer by etching using hydrogen plasma.
  • the back contact layer is formed in the opening of the passivation layer.
  • JP-T-2010-503222 an opening penetrating in the thickness direction is formed in the passivation layer by etching the passivation layer until it reaches the back surface of the semiconductor substrate. As a result, the interface portion between the semiconductor substrate and the passivation layer is damaged, so that the passivation property is deteriorated and the contact resistance may be increased.
  • the present disclosure aims to provide a photoelectric conversion element that can ensure good passivation and reduce contact resistance.
  • the photoelectric conversion element according to the present disclosure is formed on a semiconductor substrate, one surface of the semiconductor substrate, and has at least one concave portion on the surface, and is formed on a passivation layer made of an intrinsic amorphous semiconductor, and on the passivation layer.
  • FIG. 1 is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element according to the first embodiment.
  • FIG. 2A is a diagram showing a first step in the method of manufacturing the photoelectric conversion element shown in FIG.
  • FIG. 2B is a diagram showing a second step in the method of manufacturing the photoelectric conversion element shown in FIG.
  • FIG. 2C is a diagram showing a third step in the method of manufacturing the photoelectric conversion element shown in FIG.
  • FIG. 2D is a diagram showing a fourth step in the method of manufacturing the photoelectric conversion element shown in FIG.
  • FIG. 2E is a diagram showing a fifth step in the method for manufacturing the photoelectric conversion element shown in FIG. 1.
  • 2F is a diagram showing a sixth step in the method of manufacturing the photoelectric conversion element shown in FIG. FIG.
  • FIG. 2G is a diagram showing a seventh step in the method of manufacturing the photoelectric conversion element shown in FIG.
  • FIG. 2H is a diagram showing an eighth step in the method of manufacturing the photoelectric conversion element shown in FIG.
  • FIG. 2I is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element completed through the first to eighth steps.
  • FIG. 3 is a diagram showing the shape of the recess formed in the fourth step.
  • FIG. 4A is a diagram showing the shape of the n-type amorphous semiconductor layer formed in the fifth step.
  • FIG. 4B is a diagram showing another shape of the n-type amorphous semiconductor layer formed in the fifth step.
  • FIG. 5 is a diagram showing the lifetime of the photoelectric conversion element for each thickness of the passivation layer.
  • FIG. 5 is a diagram showing the lifetime of the photoelectric conversion element for each thickness of the passivation layer.
  • FIG. 6A is a diagram showing contact resistance for each thickness of a portion where an n-type amorphous semiconductor layer is disposed in the passivation layer.
  • FIG. 6B is a diagram showing contact resistance for each thickness of a portion where the p-type amorphous semiconductor layer is disposed in the passivation layer.
  • FIG. 7 is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element according to the second embodiment.
  • FIG. 8A is a diagram showing one step in the method of manufacturing the photoelectric conversion element shown in FIG.
  • FIG. 8B is a diagram illustrating a step in the method for manufacturing the photoelectric conversion element illustrated in FIG. 7.
  • FIG. 8C is a diagram showing one step in the method for manufacturing the photoelectric conversion element shown in FIG. 7.
  • FIG. 8A is a diagram showing contact resistance for each thickness of a portion where an n-type amorphous semiconductor layer is disposed in the passivation layer.
  • FIG. 6B is a diagram showing contact resistance for
  • FIG. 8D is a cross-sectional view showing a schematic configuration of the photoelectric conversion element completed through the steps shown in FIGS. 8A to 8C.
  • FIG. 9 is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element according to the third embodiment.
  • FIG. 10 is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element according to the fourth embodiment.
  • FIG. 11A is a diagram illustrating a step in the method of manufacturing the photoelectric conversion element illustrated in FIG. 10.
  • FIG. 11B is a diagram illustrating a step in the method for manufacturing the photoelectric conversion element illustrated in FIG. 10.
  • FIG. 11C is a diagram illustrating a step in the method of manufacturing the photoelectric conversion element illustrated in FIG. 10.
  • FIG. 11A is a diagram illustrating a step in the method of manufacturing the photoelectric conversion element illustrated in FIG. 10.
  • FIG. 11B is a diagram illustrating a step in the method for manufacturing the photoelectric conversion element illustrated in FIG. 10.
  • FIG. 11D is a diagram illustrating a step in the method of manufacturing the photoelectric conversion element illustrated in FIG. 10.
  • FIG. 11E is a cross-sectional view showing a schematic configuration of the photoelectric conversion element completed through the steps shown in FIGS. 11A to 11D.
  • FIG. 12 is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element according to the fifth embodiment.
  • FIG. 13 is a schematic diagram illustrating a configuration example of a photoelectric conversion module according to the sixth embodiment.
  • FIG. 14 is a schematic diagram illustrating a configuration example of the solar power generation system according to the seventh embodiment.
  • FIG. 15 is a schematic diagram illustrating a configuration example of the photoelectric conversion module array illustrated in FIG. 14.
  • FIG. 16 is a schematic diagram illustrating another configuration example of the solar power generation system according to the seventh embodiment.
  • FIG. 17 is a schematic diagram illustrating a configuration example of the solar power generation system according to the eighth embodiment.
  • FIG. 18 is a schematic diagram illustrating another configuration example of the solar power generation system according to the eighth embodiment.
  • the photoelectric conversion element according to the embodiment is formed on a semiconductor substrate, one surface of the semiconductor substrate, and has at least one concave portion on the surface, and is formed on a passivation layer made of an intrinsic amorphous semiconductor, and on the passivation layer.
  • the passivation layer is interposed between the first and second amorphous semiconductor layers and the semiconductor substrate, the semiconductor is formed when the first and second amorphous semiconductor layers are formed.
  • the interface portion between the substrate and the passivation layer is not easily damaged. For this reason, favorable passivation property can be ensured.
  • At least one of the first and second amorphous semiconductor layers is disposed in the recess provided on the surface of the passivation layer. That is, in the passivation layer, the thickness of at least one of the portion where the first amorphous semiconductor layer is disposed and the portion where the second amorphous semiconductor layer is disposed is smaller than the thickness of the other portion. For this reason, the contact resistance between the semiconductor substrate and the passivation layer can be reduced.
  • Both the first amorphous semiconductor layer and the second amorphous semiconductor layer may be disposed in the recess (second configuration).
  • the thickness of both the portion where the first amorphous semiconductor layer is disposed and the portion where the second amorphous semiconductor layer is disposed is smaller than the thickness of the other portion. Become. For this reason, the contact resistance between the passivation layer and the semiconductor substrate can be further reduced.
  • the thickness of the passivation layer in the region where the first amorphous semiconductor layer is in contact may be different from the thickness in the region where the second amorphous semiconductor layer is in contact (third configuration).
  • the thickness of the region in contact with the first amorphous semiconductor layer and the thickness of the region in contact with the second amorphous semiconductor layer can be determined according to the characteristics of the photoelectric conversion element. For this reason, passivation property can be improved efficiently.
  • the first amorphous semiconductor layer may have an n-type conductivity
  • the second amorphous semiconductor layer may have a p-type conductivity.
  • the thickness in the region in contact with the second amorphous semiconductor layer may be larger than the thickness in the region in contact with the first amorphous semiconductor layer (fourth configuration).
  • the passivation layer is formed so that the thickness of the region in contact with the second amorphous semiconductor layer having the p-type conductivity is relatively large.
  • the passivation layer may have a thickness of 5 nm to 20 nm in a portion where no recess is provided (fifth configuration).
  • the portion of the passivation layer where the first and second amorphous semiconductor layers are not disposed has a sufficient thickness to protect the semiconductor substrate. Therefore, recombination of carriers (electrons and holes) can be suppressed in a region corresponding to the first and second amorphous semiconductor layers in the semiconductor substrate, and good passivation can be realized. .
  • FIG. 1 is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element according to the first embodiment.
  • the photoelectric conversion element 10 includes a semiconductor substrate 1, an antireflection film 2, a passivation layer 3, an n-type amorphous semiconductor layer 4, a p-type amorphous semiconductor layer 5, an electrode. 6 and 7.
  • the semiconductor substrate 1 is, for example, an n-type single crystal silicon substrate.
  • the semiconductor substrate 1 has a thickness of 100 to 150 ⁇ m, for example.
  • a texture structure is formed on one surface of the semiconductor substrate 1.
  • the surface on which the texture structure is formed is referred to as a light receiving surface, and the surface opposite to the light receiving surface is referred to as a back surface.
  • the antireflection film 2 is formed on the light receiving surface of the semiconductor substrate 1.
  • the antireflection film 2 is made of, for example, a silicon nitride film.
  • the antireflection film 2 has a film thickness of 60 nm, for example.
  • the passivation layer 3 is formed on the back surface of the semiconductor substrate 1.
  • the passivation layer 3 has a plurality of recesses 34a and 34b on the surface.
  • the recesses 34a and 34b are formed in the passivation layer 3 by, for example, etching using hydrogen plasma.
  • the upper surface in the thickness direction of the passivation layer 3 includes a first region 31 in contact with the n-type amorphous semiconductor layer 4 and a second region 32 in contact with the p-type amorphous semiconductor layer 5.
  • the upper surface in the thickness direction of the passivation layer 3 further includes a third region 33 where neither the n-type amorphous semiconductor layer 4 nor the p-type amorphous semiconductor layer 5 is in contact.
  • region 31 is an area
  • the bottom surface of the recess 34 a does not reach the interface between the semiconductor substrate 1 and the passivation layer 3.
  • the bottom surface of the recess 34 a is positioned above the interface between the semiconductor substrate 1 and the passivation layer 3 in the thickness direction.
  • the thickness T31 of the passivation layer 3 in the first region 31 is smaller than the thickness T33 of the passivation layer 3 in the third region 33.
  • the thickness T31 can be appropriately determined within a range of 2 to 10 nm, for example.
  • region 32 is an area
  • the bottom surface of the recess 34 b does not reach the interface between the semiconductor substrate 1 and the passivation layer 3. That is, the bottom surface of the recess 34 b is positioned above the interface between the semiconductor substrate 1 and the passivation layer 3 in the thickness direction.
  • the thickness T32 of the passivation layer 3 in the second region 32 is smaller than the thickness T33 of the passivation layer 3 in the third region 33.
  • the thickness T32 can be appropriately determined within a range of 2 to 10 nm, for example.
  • the thickness T32 in the second region 32 is different from the thickness T31 in the first region 31.
  • the thickness T32 is larger than the thickness T31.
  • the thickness T32 may be smaller than the thickness T31 or may be equal to the thickness T31.
  • the recesses 34a and 34b are provided so as not to overlap each other. That is, the first region 31 and the second region 32 are spaced apart in the in-plane direction of the semiconductor substrate 1. A third region 33 is interposed between the first region 31 and the second region 32 in the in-plane direction of the semiconductor substrate 1.
  • the distance G between the first region 31 and the second region 32 in the in-plane direction of the semiconductor substrate 1 is preferably 250 ⁇ m or less.
  • the interval G is the shortest distance between the edge of the first region 31 and the edge of the second region 32 in the in-plane direction of the semiconductor substrate 1.
  • region 33 is an area
  • the thickness T33 in the third region 33 can be set in the range of 5 nm to 20 nm.
  • the n-type amorphous semiconductor layer 4 is formed on the passivation layer 3. More specifically, the n-type amorphous semiconductor layer 4 is formed in the recess 34a. Therefore, the n-type amorphous semiconductor layer 4 is in contact with the bottom surface of the recess 34 a that is the first region 31.
  • the thickness of the n-type amorphous semiconductor layer 4 is, for example, 3 to 50 nm.
  • the n-type amorphous semiconductor layer 4 is an amorphous semiconductor layer having n-type conductivity and containing hydrogen.
  • the n-type amorphous semiconductor layer 4 contains, for example, phosphorus (P) as an n-type dopant.
  • the n-type amorphous semiconductor layer 4 includes, for example, n-type amorphous silicon, n-type amorphous silicon germanium, n-type amorphous germanium, n-type amorphous silicon carbide, and n-type amorphous silicon nitride. N-type amorphous silicon oxide, n-type amorphous silicon oxynitride, n-type amorphous silicon carbon oxide, or the like.
  • the p-type amorphous semiconductor layer 5 is formed on the passivation layer 3. More specifically, the p-type amorphous semiconductor layer 5 is formed in the recess 34b. Therefore, the p-type amorphous semiconductor layer 5 is in contact with the bottom surface of the recess 34 b that is the second region 32.
  • the thickness of the p-type amorphous semiconductor layer 5 is, for example, 5 to 50 nm.
  • the p-type amorphous semiconductor layer 5 is an amorphous semiconductor layer having p-type conductivity and containing hydrogen.
  • the p-type amorphous semiconductor layer 5 includes, for example, boron (B) as a p-type dopant.
  • the p-type amorphous semiconductor layer 5 includes, for example, p-type amorphous silicon, p-type amorphous silicon germanium, p-type amorphous germanium, p-type amorphous silicon carbide, and p-type amorphous silicon nitride. , P-type amorphous silicon oxide, p-type amorphous silicon oxynitride, p-type amorphous silicon carbon oxide, or the like.
  • the second region 32 is arranged away from the first region 31 in the in-plane direction of the semiconductor substrate 1. Therefore, on the surface of the passivation layer 3, the p-type amorphous semiconductor layer 5 provided on the second region 32 is disposed away from the n-type amorphous semiconductor layer 4 provided on the first region 31. .
  • a plurality of n-type amorphous semiconductor layers 4 and a plurality of p-type amorphous semiconductor layers 5 are alternately arranged in the in-plane direction of the semiconductor substrate 1 on the passivation layer 3. .
  • the electrode 6 is formed on the n-type amorphous semiconductor layer 4.
  • the electrode 7 is formed on the p-type amorphous semiconductor layer 5.
  • each electrode 6 and 7 may have a laminated structure.
  • each electrode 6 and 7 may include a transparent conductive layer and a metal layer.
  • the thickness of the transparent conductive layer of each electrode 6 and 7 can be 3 to 100 nm, for example.
  • the thickness of the metal layer of each electrode 6 and 7 is preferably 50 nm or more.
  • the transparent conductive layer of the electrode 6 is preferably made of a material having high adhesion to the n-type amorphous semiconductor layer 4.
  • the transparent conductive layer of the electrode 7 is preferably made of a material having high adhesion to the p-type amorphous semiconductor layer 5.
  • the metal layers of the electrodes 6 and 7 are preferably made of a metal having high conductivity.
  • the transparent conductive layers of the electrodes 6 and 7 can be made of, for example, ITO (Indium Tin Oxide), ZnO, or IWO (Indium Tungsten Oxide).
  • the metal layers of the electrodes 6 and 7 are, for example, silver (Ag), nickel (Ni), aluminum (Al), copper (Cu), tin (Sn), platinum (Pt), gold (Au), chromium (Cr ), Tungsten (W), cobalt (Co), titanium (Ti), alloys thereof, or laminated films thereof.
  • the electrodes 6 and 7 may not include the above-described transparent conductive layer or metal layer.
  • the metal layer of each electrode 6, 7 is made of Ti, Ni, Al, Cr, etc., and has an adhesion layer having a thickness of about 1 to 10 nm, Al, It can have a laminated structure with a light reflecting metal layer mainly composed of Ag or the like.
  • FIG. 1 Manufacturing method of photoelectric conversion element
  • the semiconductor substrate 1 shown in FIG. 2A is prepared (first step).
  • a wafer having a thickness of 100 to 300 ⁇ m is cut out from bulk silicon, and etching for removing a damaged layer on the wafer surface and etching for adjusting the thickness are performed.
  • a protective film is formed on one surface of the etched wafer.
  • silicon oxide, silicon nitride, or the like is used for the protective film.
  • wet etching is performed on the wafer on which the protective film is formed using an alkaline solution such as NaOH or KOH (for example, an aqueous solution of KOH: 1 to 5 wt%, isopropyl alcohol: 1 to 10 wt%).
  • an alkaline solution such as NaOH or KOH
  • KOH for example, an aqueous solution of KOH: 1 to 5 wt%, isopropyl alcohol: 1 to 10 wt%.
  • the antireflection film 2 is formed on the light receiving surface of the semiconductor substrate 1, that is, the surface on which the texture structure is formed (second step).
  • the antireflection film 2 can be formed, for example, by sequentially stacking a silicon oxide film and a silicon nitride film on the light receiving surface of the semiconductor substrate 1.
  • the silicon oxide film can be formed by subjecting the light receiving surface of the semiconductor substrate 1 to thermal oxidation or wet treatment.
  • the thermal oxidation treatment for example, the semiconductor substrate 1 is heated to 900 to 1000 ° C. in an atmosphere of oxygen or water vapor.
  • wet processing for example, the semiconductor substrate 1 is immersed in hydrogen peroxide, nitric acid, ozone water, or the like, and then heated to 800 to 1000 ° C. in a dry atmosphere.
  • the silicon nitride film can be formed by, for example, a plasma CVD (Plasma Chemical Vapor Deposition) method.
  • An i-type amorphous semiconductor layer and an n-type amorphous semiconductor layer can be sequentially formed between the silicon nitride film and the semiconductor substrate 1 instead of the silicon oxide film.
  • the i-type amorphous semiconductor layer and the n-type amorphous semiconductor layer can be formed by, for example, a plasma CVD method.
  • an i-type amorphous semiconductor layer 300 is formed on the back surface of the semiconductor substrate 1 (third step).
  • i-type amorphous semiconductor layer 300 is formed by depositing i-type amorphous silicon on the entire back surface of semiconductor substrate 1 by plasma CVD.
  • the i-type amorphous silicon is deposited to a thickness sufficient to ensure good passivation, for example, 5 to 20 nm.
  • the i-type amorphous semiconductor layer 300 is formed to have a thickness T300 equal to the thickness T33 (FIG. 1) in the third region 33 of the passivation layer 3.
  • the reaction gas introduced into the reaction chamber provided in the plasma CVD apparatus is, for example, hydrogen gas and silane gas.
  • the processing conditions at this time are, for example, the temperature of the semiconductor substrate 1: 130 to 210 ° C., the hydrogen gas flow rate: 0 to 100 sccm, the silane gas (SiH 4 ) flow rate: about 40 sccm, the pressure in the reaction chamber: 40 to 120 Pa, and the frequency: 13 .56 MHz, power density: 5 to 15 mW / cm 2 .
  • the recess 34a is formed in the i-type amorphous semiconductor layer 300 (fourth step).
  • a shadow mask 200 is disposed on the i-type amorphous semiconductor layer 300.
  • the i-type amorphous semiconductor layer 300 is etched by, for example, hydrogen plasma through the opening 200 a of the shadow mask 200.
  • etching of a depth smaller than the thickness T300 of the i-type amorphous semiconductor layer 300 is performed so that the semiconductor substrate 1 is not exposed from the i-type amorphous semiconductor layer 300.
  • the recess 34 a is formed in the i-type amorphous semiconductor layer 300.
  • Etching with hydrogen plasma can be performed using a plasma CVD apparatus.
  • the processing conditions at this time are, for example, the temperature of the semiconductor substrate 1: 130 to 210 ° C., an atmosphere of 100% hydrogen gas, the pressure in the reaction chamber: 40 to 300 Pa, the frequency: 13.56 MHz, and the power density: 10 to 100 mW / cm 2 , treatment time: 10 to 300 seconds.
  • etch back of several nm can be performed without penetrating the i-type amorphous semiconductor layer 300, and the interface between the semiconductor substrate 1 and the i-type amorphous semiconductor layer 300 is damaged by etching. Can be prevented.
  • FIG. 3 is a diagram showing the relationship between the etching depth and the width of the opening 200a (the length of the opening 200a in the in-plane direction of the semiconductor substrate 1).
  • FIG. 3 shows the etching depth when etching is performed in the same time when the width of the opening 200a of the shadow mask 200 is 200 ⁇ m, 400 ⁇ m, 600 ⁇ m, 800 ⁇ m, and 1000 ⁇ m.
  • FIG. 3 shows that the larger the width of the opening 200a, the smaller the etching depth and the slower the etching rate. That is, if the width of the opening 200a is large, a wide and shallow concave portion 34a is formed, and if the width of the opening 200a is small, a narrow and deep concave portion 34a is formed.
  • the recesses 34a having various shapes can be formed.
  • the n-type amorphous semiconductor layer 4 is formed in the recess 34a (fifth step).
  • an n-type amorphous material is formed in the recess 34a through the opening 200a by plasma CVD. Deposit quality silicon. Thereby, the n-type amorphous semiconductor layer 4 is formed in the recess 34a.
  • the reaction gas introduced into the reaction chamber provided in the plasma CVD apparatus is, for example, silane gas, hydrogen gas, and phosphine gas diluted with hydrogen gas (phosphine concentration is 1%, for example) ).
  • the processing conditions at this time are, for example, a temperature of the semiconductor substrate 1 of about 170 ° C., a hydrogen gas flow rate of 0 to 100 sccm, a silane gas flow rate of about 40 sccm, a phosphine gas flow rate of about 40 sccm, a pressure in the reaction chamber of about 40 Pa, and a high frequency power. Density: about 8.33 mW / cm 2 .
  • FIG. 4A shows a result of measuring the film thickness of the n-type amorphous semiconductor layer 4 by scanning the n-type amorphous semiconductor layer 4 in the in-plane direction of the semiconductor substrate 1 with a stylus profilometer.
  • the n-type amorphous semiconductor layer 4 formed through the opening 200a of the shadow mask 200 includes a flat region L, a film thickness reduction region T, and a tapered region R, as shown in FIG. 4A.
  • the thickness of the n-type amorphous semiconductor layer 4 normalized by setting the thickness of the flat region L to 1.0 is plotted on the vertical axis.
  • the n-type amorphous semiconductor layer 4 has the maximum film thickness at a point C that is substantially the center in the in-plane direction of the semiconductor substrate 1.
  • the flat region L is a region where the film thickness hardly changes from the maximum film thickness. In the example of FIG. 4A, the region between the lengths in the scanning direction between 280 ⁇ m and 380 ⁇ m is the flat region L.
  • the length of the flat region L depends on the width of the opening 200a, but the deposition (deposition rate) does not depend on the width of the opening 200a.
  • the film thickness gradually decreases in the region from one end K10 to the point K11 of the flat region L and the region from the other end K20 to the point K12 of the flat region L.
  • the film thickness sharply decreases in the region from the point K11 to the point K21 and the region from the point K12 to the point K22. That is, rather than the reduction rate (first reduction rate) of each film thickness in the region from one end K10 to the point K11 of the flat region L and the region from the other end K20 to the point K12 of the flat region L, The decreasing rate (second decreasing rate) of each film thickness in the region from the point K11 to the point K21 and the region from the point K12 to the point K22 is large.
  • the film thickness reduction region T is a region in which the film thickness reduction rate gradually changes in the n-type amorphous semiconductor layer 4, and includes a region from the end K10 to the point K11 of the flat region L and an end of the flat region L. This is an area from the portion K20 to the point K12. That is, the film thickness reduction region T has a first point at which the film thickness of the thin film is maximized in one thin film formed on the semiconductor substrate 1, and the film thickness decreases in the in-plane direction of the thin film. When the point at which the rate of decrease changes from the first rate of decrease to the second rate of decrease is taken as the second point, this is the region from the first point to the second point in the in-plane direction of the thin film.
  • the tapered region R is a region formed in a tapered shape, and is a region from the points K21 and K22 to the lower ends K31 and K32 of the n-type amorphous semiconductor layer 4, respectively.
  • the tapered region R is a region formed around the opening 200 a, that is, around the shadow mask 200.
  • the width of the tapered region R varies depending on the film forming conditions of the n-type amorphous semiconductor layer 4 and is, for example, 400 ⁇ m or less, preferably 100 ⁇ m or less.
  • the amount of film thickness reduction in the film thickness reduction region T is preferably 5% or more of the film thickness of the flat region L, and more preferably 10% or more. That is, in FIG. 4A, the amount of decrease in the film thickness from the ends K10, K20 of the flat region L to the points K11, K21 is preferably 5% or more of the film thickness of the flat region L, and is preferably 10% or more. It is more preferable. In the example of FIG. 4A, the film thickness reduction region T is reduced by 20% or more than the film thickness of the flat region L, which is a preferable state.
  • the width of the film thickness reduction region T is preferably 20 ⁇ m or more, and more preferably 100 ⁇ m or more.
  • FIG. 4B is a diagram showing another shape of the n-type amorphous semiconductor layer 4.
  • the n-type amorphous semiconductor layer 4 does not have the flat region L, but the film thickness of the region from the point C to the point K10 that is the approximate center of the n-type amorphous semiconductor layer 4 is increased.
  • the decreasing rate is smaller than the decreasing rate of the film thickness in the region from the point K10 to the point K20.
  • Each region T1 from the point C10 to the point K10 is a film thickness decreasing region of the n-type amorphous semiconductor layer 4 having the shape shown in FIG. 4B.
  • the film thickness outside the point K20 is substantially constant, and the tapered region R is not formed.
  • the tapered region R can be formed by adjusting the film forming pressure, the distance between the shadow mask 200 and the passivation layer 3, or the like.
  • the n-type amorphous semiconductor layer 4 may have a film thickness at a point C that is substantially the center in the in-plane direction of the semiconductor substrate 1 smaller than the film thickness at both ends. That is, the n-type amorphous semiconductor layer 4 may be formed in a shape in which the central portion is recessed from both end portions.
  • the n-type amorphous semiconductor layer 4 has the first point at which the film thickness is maximum, and the reduction rate of the film thickness in the in-plane direction of the n-type amorphous semiconductor layer 4 is The region from the first point to the second point in the in-plane direction of the n-type amorphous semiconductor layer 4 when the point where the first decrease rate changes to the second decrease rate is the second point.
  • a film thickness reduction region can be provided.
  • a recess 34b is formed in the i-type amorphous semiconductor layer 300 (sixth step).
  • a shadow mask 201 is disposed on the i-type amorphous semiconductor layer 300. Then, the i-type amorphous semiconductor layer 300 is etched by, for example, hydrogen plasma through the opening 201 a of the shadow mask 201. At this time, etching with a depth smaller than the thickness of the i-type amorphous semiconductor layer 300 is performed so that the semiconductor substrate 1 is not exposed from the i-type amorphous semiconductor layer 300. Thereby, the recess 34b is formed in the i-type amorphous semiconductor layer 300, and the passivation layer 3 is completed.
  • Etching with hydrogen plasma can be performed using a plasma CVD apparatus under the same processing conditions as in the fourth step. Therefore, even when the recess 34b is formed, etch back of several nm can be performed without penetrating the i-type amorphous semiconductor layer 300, and the interface between the semiconductor substrate 1 and the i-type amorphous semiconductor layer 300 is etched. Can prevent damage.
  • the etching depth when forming the recess 34b is different from the etching depth when forming the recess 34a.
  • the etching depth D34b when forming the recess 34b is smaller than the etching depth D34a when forming the recess 34a.
  • the recess 34b can be formed in various shapes depending on the width of the opening 201a of the shadow mask 201.
  • the concave portion 34b shallower than the concave portion 34a may be formed by making the width of the opening 201a larger than the opening 200a of the shadow mask 200 used for forming the concave portion 34a.
  • the shape of the recess 34b may be adjusted by changing the processing conditions such as the etching time when forming the recess 34a.
  • the p-type amorphous semiconductor layer 5 is formed in the recess 34b (seventh step).
  • a p-type is formed in the recess 34b through the opening 201a by the plasma CVD method.
  • Amorphous silicon is deposited.
  • the p-type amorphous semiconductor layer 5 is formed in the recess 34b.
  • the reaction gas introduced into the reaction chamber provided in the plasma CVD apparatus is, for example, silane gas, hydrogen gas, and diborane gas diluted with hydrogen (diborane concentration is about 2%, for example). is there.
  • the processing conditions at this time are, for example, the temperature of the semiconductor substrate 1: 150 to 210 ° C., hydrogen gas flow rate: 0 to 100 sccm, silane gas flow rate: about 40 sccm, diborane gas flow rate: about 40 sccm, pressure in the reaction chamber: 40 to 120 Pa, high frequency Power density: 5 to 15 mW / cm 2 .
  • the p-type amorphous semiconductor layer 5 formed through the opening 201a of the shadow mask 201 has the same shape as the n-type amorphous semiconductor layer 4 shown in FIG. That is, similarly to the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5 includes a flat region L, a film thickness reduction region T, and a tapered region R.
  • electrodes 6 and 7 are formed on the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, respectively (eighth step).
  • a mask 202 is disposed on the back surface of the semiconductor substrate 1 on which the passivation layer 3, the n-type amorphous semiconductor layer 4, and the p-type amorphous semiconductor layer 5 are formed. Then, electrodes 6 and 7 are formed on the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 through the openings 202a of the mask 202, for example, by vapor deposition or sputtering.
  • the photoelectric conversion element 10 shown in FIG. 2I is manufactured.
  • each mask 200, 201, 202 used in each of the above steps is, for example, a metal made of a metal such as stainless steel, copper, nickel, an alloy containing nickel (for example, 42 alloy or Invar material), molybdenum or the like. It is a mask.
  • Each mask 200 to 204 may be made of glass, ceramic, organic film or the like.
  • the passivation layer 3 is interposed between the semiconductor substrate 1 and the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5. Yes.
  • the interface portion between the semiconductor substrate 1 and the passivation layer 3 is not easily damaged. Therefore, good passivation properties can be ensured.
  • the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are disposed in the recesses 34a and 34b of the passivation layer 3, respectively. That is, in the passivation layer 3, the thickness T31 in the first region 31 that is in contact with the n-type amorphous semiconductor layer 4 and the thickness T32 in the second region 32 that is in contact with the p-type amorphous semiconductor layer 5 are n-type amorphous. It is smaller than the thickness T33 in the third region 33 where the semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are not in contact. For this reason, the contact resistance between the semiconductor substrate 1 and the passivation layer 3 can be reduced in the n-side region and the p-side region.
  • the thickness T32 of the second region 32 in contact with the p-type amorphous semiconductor layer 5 is larger than the thickness T31 of the first region 31 in contact with the n-type amorphous semiconductor layer 4.
  • the recesses 34 a and 34 b are formed without exposing the semiconductor substrate 1 from the i-type amorphous semiconductor layer 300. For this reason, when forming the recesses 34a and 34b, the interface portion between the semiconductor substrate 1 and the i-type amorphous semiconductor layer 300 (passivation layer 3) is not damaged, and the passivation property can be improved.
  • the semiconductor substrate 1 has a texture structure on the light receiving surface. For this reason, it is possible to prevent light from being reflected from the light receiving surface of the semiconductor substrate 1, and to ensure a large amount of light incident on the photoelectric conversion element 10.
  • the thickness T33 of the third region 33 where the n-type and p-type amorphous semiconductor layers 4 and 5 are not in contact with each other is, for example, 5 nm to 20 nm.
  • the thicknesses T31 and T32 of the first region 31 in contact with the n-type amorphous semiconductor layer 4 and the second region 32 in contact with the p-type amorphous semiconductor layer 5 are, for example, 2 nm to 10 nm. .
  • the thickness of the portion where the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are disposed is sufficiently small, and the contact resistance in the n-side and p-side regions is more reliably ensured. Can be reduced.
  • the distance G between the first region 31 and the second region 32 in the in-plane direction of the semiconductor substrate 1 is, for example, 250 ⁇ m or less. Thereby, a large area of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 disposed on the passivation layer 3 can be secured, and the collection efficiency of carriers (electrons and holes) is improved. Can be made.
  • the passivation layer 3 is formed by forming the i-type amorphous semiconductor layer 300 on the back surface of the semiconductor substrate 1 and then providing the recesses 34 a and 34 b in the i-type amorphous semiconductor layer 300.
  • the back surface of the semiconductor substrate 1 is not exposed from the i-type amorphous semiconductor layer 300. That is, the passivation layer 3 is formed without going through a step of exposing a part of the back surface of the semiconductor substrate 1. For this reason, the interface portion between the semiconductor substrate 1 and the passivation layer 3 is not damaged, and good passivation can be realized.
  • the formation of the recess 34 a of the passivation layer 3 and the formation of the n-type amorphous semiconductor layer 4 are performed continuously using the same shadow mask 200.
  • the formation of the recess 34 b of the passivation layer 3 and the formation of the p-type amorphous semiconductor layer 5 are performed continuously using the same shadow mask 201. For this reason, it can suppress that an impurity mixes into the passivation layer 3, and can ensure favorable passivation property.
  • FIG. 5 is a diagram illustrating the lifetime of the photoelectric conversion element 10 for each thickness of the passivation layer 3.
  • FIG. 6A is a diagram illustrating the contact resistance in the n-side region for each thickness of the first region 31.
  • FIG. 6B is a diagram showing the contact resistance in the p-side region for each thickness of the second region 32.
  • the film thickness of 1.75 times, the film thickness of 1.5 times, and the film thickness of 1.25 times are 1.75 times that the passivation layer 3 has a predetermined thickness (standard film thickness). It means having double thickness, 1.5 times thickness, and 1.25 times thickness.
  • the lifetime of the photoelectric conversion element 10 exhibiting passivation properties increases as the thickness of the passivation layer 3 increases.
  • the thickness of the passivation layer 3 increases, deterioration with time is alleviated. From this, it can be seen that if the thickness of the passivation layer 3 is increased, good passivation properties can be secured.
  • the contact resistance in the p-side region significantly increases as the thickness T32 of the second region 32 increases. Therefore, it can be seen that the contact resistance can be effectively reduced by making the thickness T32 of the second region 32 smaller than the thicknesses T31 and T33 of the other regions in the passivation layer 3.
  • the contact resistance in the n-side region does not increase significantly according to the thickness T31 of the first region 31, but in addition to the thickness T32 of the second region 32, If the thickness T31 is made smaller than the thickness T33 of other regions, the contact resistance can be further reduced.
  • the thickness T33 of the third region 33 where the n-type and p-type amorphous semiconductor layers 4 and 5 are not in contact is sufficiently ensured.
  • the thickness T31 of the first region 31 in contact with the n-type amorphous semiconductor layer 4 and the thickness T32 of the second region 32 in contact with the p-type amorphous semiconductor layer 5 are the third region. It is smaller than the thickness T33 of 33. Therefore, it is possible to reduce contact resistance while ensuring good passivation.
  • FIG. 7 is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element according to the second embodiment.
  • the photoelectric conversion element 102 is first in that a part of the n-type amorphous semiconductor layer 4 and a part of the p-type amorphous semiconductor layer 5 overlap on the passivation layer 320. Different from the embodiment.
  • a recess 324 having a stepped bottom surface is formed in the passivation layer 320.
  • the lower surface of the bottom surface of the recess 324 is a first region 321 in contact with the n-type amorphous semiconductor layer 4.
  • the upper surface of the bottom surface of the recess 324 is a second region 322 that is in contact with the p-type amorphous semiconductor layer 5.
  • the thickness T321 in the first region 321 is smaller than the thickness T322 in the second region 322, as in the first embodiment.
  • the thickness T323 of the third region 303 where the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are not in contact is larger than the thickness T321 in the first region 321 and the thickness T322 in the second region 322. .
  • the entire bottom surface of the n-type amorphous semiconductor layer 4 is in contact with the first region 321 of the passivation layer 3.
  • the p-type amorphous semiconductor layer 5 has most of the bottom surface in contact with the second region 322 of the passivation layer 3, but part of the bottom surface is in contact with the top surface in the thickness direction of the n-type amorphous semiconductor layer 4. Yes. That is, the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are disposed on the passivation layer 3 so as to partially overlap.
  • the p-type amorphous semiconductor layer 5 partially overlaps the n-type amorphous semiconductor layer 4, but the n-type amorphous semiconductor layer is formed on the p-type amorphous semiconductor layer 5.
  • a part of 4 may overlap.
  • the thickness T321 of the first region 321 in which the n-type amorphous semiconductor layer 4 is disposed is set to a p-type amorphous.
  • the thickness T322 of the second region 322 where the quality semiconductor layer 5 is disposed may be smaller.
  • a texture structure is formed on the light receiving surface of the semiconductor substrate 1, and the antireflection film 2 is formed.
  • an i-type amorphous semiconductor layer 302 is formed on the back surface of the semiconductor substrate 1 in the same manner as in the third step of the first embodiment.
  • the recess 400a is formed on the i-type amorphous semiconductor layer 302, and the n-type amorphous semiconductor layer 4 is formed in the recess 400a.
  • the concave portion 400 b is formed in the i-type amorphous semiconductor layer 302.
  • the recess 400b can be formed by the same method and conditions as in the sixth step of the first embodiment. However, the recess 400b is different from the recess 34b formed in the sixth step of the first embodiment in that the recess 400b is formed in contact with the recess 400a. That is, the recess 400 b is formed adjacent to the recess 400 a so as not to be separated from the recess 400 a in the in-plane direction of the semiconductor substrate 1.
  • the i-type amorphous semiconductor layer 302 is etched by, for example, hydrogen plasma through the opening 203a of the shadow mask 200 to form the recess 400b.
  • etching with a depth smaller than the thickness of the i-type amorphous semiconductor layer 302 is performed so that the semiconductor substrate 1 is not exposed from the i-type amorphous semiconductor layer 302.
  • the etching depth for forming the recess 400b is smaller than the etching depth for forming the recess 400a.
  • a recess 324 having a stepped bottom surface is formed by the recesses 400a and 400b.
  • the p-type amorphous semiconductor layer 5 is formed in the recess 400b.
  • the p-type amorphous semiconductor layer 5 can be formed using, for example, a plasma CVD method under the same processing conditions as in the seventh step of the first embodiment. Specifically, as shown in FIG. 8C, the p-type amorphous semiconductor layer 5 is formed in the recess 400b through the opening 204a of the shadow mask 204. At this time, the recess 400b and a part of the n-type amorphous semiconductor layer 4 are exposed from the opening 204a. Therefore, a part of the p-type amorphous semiconductor layer 5 is formed on the n-type amorphous semiconductor layer 4 and the other part is formed in the recess 400b.
  • a plasma CVD method under the same processing conditions as in the seventh step of the first embodiment. Specifically, as shown in FIG. 8C, the p-type amorphous semiconductor layer 5 is formed in the recess 400b through the opening 204a of the shadow mask 204. At this time, the recess 400b and a part of the
  • electrodes 6 and 7 are formed on the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, respectively, in the same manner as in the eighth step of the first embodiment.
  • FIG. 9 is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element according to the third embodiment.
  • the n-type amorphous semiconductor layer 4 is disposed in the recess 334, and the p-type amorphous semiconductor layer 5 is disposed in the recess.
  • the first embodiment There is no difference from the first embodiment.
  • the bottom surface of the recess 334 formed in the passivation layer 330 is a first region 331 in contact with the n-type amorphous semiconductor layer 4.
  • the thickness T331 in the first region 331 is smaller than the thickness in other regions. That is, the thickness T331 is smaller than the thickness T332 of the second region 332 in contact with the p-type amorphous semiconductor layer 5, and the third region in which the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are not in contact. It is smaller than the thickness T333 of 333.
  • the p-type amorphous semiconductor layer 5 is not disposed in the recess of the passivation layer 330. Accordingly, in the passivation layer 330, the thickness T332 of the second region 332 in contact with the p-type amorphous semiconductor layer 5 is equal to the third region 333 in which the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are not in contact. Is substantially equal to the thickness T333.
  • the photoelectric conversion element 103 can be manufactured by the same method as the photoelectric conversion element 10 according to the first embodiment. However, in the photoelectric conversion element 103, since the p-type amorphous semiconductor layer 5 is not disposed in the recess of the passivation layer 330, the sixth step of forming the recess 34b for disposing the p-type amorphous semiconductor layer 5 is performed. It is unnecessary. That is, the photoelectric conversion element 103 can be manufactured through the first to fifth steps, the seventh step, and the eighth step of Embodiment 1.
  • the n-type amorphous semiconductor layer 4 is disposed in the recess 334 of the passivation layer 330.
  • the thickness T331 of the first region 331 with which the n-type amorphous semiconductor layer 4 is in contact is smaller than the thickness of other regions, so that the contact resistance can be reduced.
  • the thicknesses T332 and T333 of regions other than the first region 331 are relatively large, so that good passivation properties can be ensured.
  • the thickness T332 of the second region 332 in contact with the p-type amorphous semiconductor layer 5 is larger than the thickness T331 of the first region 331 in contact with the n-type amorphous semiconductor layer 4. For this reason, in the p-side region where the passivation property is likely to deteriorate, it is possible to suppress the deterioration of the passivation property.
  • FIG. 10 is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element according to the fourth embodiment.
  • the photoelectric conversion element 104 in the passivation layer 340, the p-type amorphous semiconductor layer 5 is disposed in the recess 344, and the n-type amorphous semiconductor layer 44 is disposed in the recess.
  • the photoelectric conversion element 104 is also different from the first embodiment in that the n-type amorphous semiconductor layer 44 has a separation portion 441.
  • the bottom surface of the recess 344 formed in the passivation layer 340 is a second region 342 in contact with the p-type amorphous semiconductor layer 5.
  • the thickness T342 in the second region 342 is smaller than the thickness in other regions. That is, the thickness T342 is smaller than the thickness T341 of the first region 341 in contact with the n-type amorphous semiconductor layer 44.
  • the n-type amorphous semiconductor layer 44 is separated into a plurality of parts by the separation part 441 in the in-plane direction of the semiconductor substrate 1. That is, the separation part 441 penetrates the n-type amorphous semiconductor layer 44 in the thickness direction and divides it in the in-plane direction of the semiconductor substrate 1.
  • a p-type amorphous semiconductor layer 5 is disposed in the separation portion 441.
  • a texture structure is formed on the light receiving surface of the semiconductor substrate 1, and the antireflection film 2 is formed.
  • an i-type amorphous semiconductor layer 304 is formed on the back surface of the semiconductor substrate 1 in the same manner as in the third step of the first embodiment.
  • an n-type amorphous semiconductor film 500 is formed on the i-type amorphous semiconductor layer 304.
  • the n-type amorphous semiconductor film 500 can be formed by a plasma CVD method in the same manner as the fifth step of the first embodiment. However, in the fourth embodiment, the n-type amorphous semiconductor film 500 is formed on the entire surface of the i-type amorphous semiconductor layer 304. For this reason, the shadow mask 200 used in the fifth step of the first embodiment is not disposed on the i-type amorphous semiconductor layer 304, and n-type amorphous silicon is deposited by plasma CVD.
  • a separation portion 441 is formed in the n-type amorphous semiconductor film 500 and a recess 344 is formed in the i-type amorphous semiconductor layer 304.
  • the n-type amorphous semiconductor film 500 and the i-type amorphous semiconductor layer 304 are etched using, for example, hydrogen plasma through the opening 205a of the shadow mask 205.
  • Do. Etching can be performed under the same conditions as in the fourth step of the first embodiment. The etching is performed at a depth that penetrates the n-type amorphous semiconductor film 500 and does not reach the interface between the i-type amorphous semiconductor layer 304 and the semiconductor substrate 1.
  • the passivation layer 340 having the recess 344 and the n-type amorphous semiconductor layer 44 separated in the in-plane direction of the semiconductor substrate 1 by the separation portion 441 are completed.
  • the p-type amorphous semiconductor layer 5 is formed in the recess 344 of the passivation layer 340 and the separation part 441 of the n-type amorphous semiconductor layer 44.
  • the p-type amorphous semiconductor layer 5 is formed by plasma CVD or the like through the opening 205a while the shadow mask 205 is disposed on the n-type amorphous semiconductor layer 44.
  • the film formation conditions at this time can be the same as those in the seventh step of the first embodiment.
  • the p-type amorphous semiconductor layer 5 is formed in the recess 344 of the passivation layer 340 and the separation portion 441 of the n-type amorphous semiconductor layer 44.
  • electrodes 6 and 7 are formed on the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, respectively, in the same manner as in the eighth step of the first embodiment.
  • the p-type amorphous semiconductor layer 5 is disposed in the recess 344 of the passivation layer 340.
  • the thickness T342 of the second region 342 in contact with the p-type amorphous semiconductor layer 5 is smaller than other regions, so that the contact resistance can be reduced.
  • the thickness T341 of the first region 341 in contact with the n-type amorphous semiconductor layer 44 in the passivation layer 340 is relatively large, good passivation can be ensured.
  • FIG. 12 is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element according to the fifth embodiment.
  • the photoelectric conversion element 105 is different from the first embodiment in that the thickness T351 of the first region 351 and the thickness T352 of the second region 352 are equal in the passivation layer 350.
  • the passivation layer 350 has recesses 354a and 354b.
  • the n-type amorphous semiconductor layer 4 is disposed in the recess 354a.
  • the p-type amorphous semiconductor layer 5 is disposed in the recess 354b.
  • the bottom surfaces of the recesses 354a and 354b are a first region 351 in contact with the n-type amorphous semiconductor layer 4 and a second region 352 in contact with the p-type amorphous semiconductor layer 5, respectively.
  • the depths of the recesses 354a and 354b are substantially equal. That is, in the thickness direction of the passivation layer 350, the position of the bottom surface of the recess 354a is substantially equal to the position of the bottom surface of the recess 354b. Therefore, in the passivation layer 350, the thickness T351 of the first region 351 and the thickness T352 of the second region 352 are substantially equal. The thickness T351 of the first region 351 and the thickness T352 of the second region 352 are smaller than the thickness T353 of the third region 353 where the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 do not contact.
  • the photoelectric conversion element 105 can be manufactured by the same method as in the first embodiment.
  • the first embodiment since the depths of the recesses 34a and 34b are different from each other, it is necessary to form the recesses 34a and 34b by changing the processing conditions such as the opening width of the shadow mask and the etching time.
  • the fifth embodiment since the depths of the recesses 354a and 354b are the same, the recesses 354a and 354b can be formed with the same opening width of the shadow mask and other processing conditions.
  • the photoelectric conversion element 105 also has the thickness T351 of the first region 351 in contact with the n-type amorphous semiconductor layer 4 and the p-type in the passivation layer 330, as in the first embodiment.
  • Both the thickness T352 of the second region 352 that the amorphous semiconductor layer 5 is in contact with are smaller than the thickness T353 of the third region 353 that the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are not in contact with. For this reason, favorable passivation property can be ensured and contact resistance can be reduced.
  • FIG. 13 is a schematic diagram illustrating a configuration of a photoelectric conversion module according to the sixth embodiment.
  • the photoelectric conversion module 1000 includes a plurality of photoelectric conversion elements 1001, a cover 1002, and output terminals 1003 and 1004.
  • At least one of the plurality of photoelectric conversion elements 1001 is any one of the photoelectric conversion elements 10 and 102 to 105 according to the first to fifth embodiments.
  • the plurality of photoelectric conversion elements 1001 are, for example, arranged in an array and connected in series. Instead of connecting in series, parallel connection or a combination of series and parallel may be performed.
  • the cover 1002 is made of a weather resistant cover and covers the plurality of photoelectric conversion elements 1001.
  • the cover 1002 includes, for example, a transparent base material (for example, glass) provided on the light receiving surface side of the photoelectric conversion element 1001 and a back surface base material (on the reverse side opposite to the light receiving surface side of the photoelectric conversion element 1001).
  • a transparent base material for example, glass
  • a back surface base material on the reverse side opposite to the light receiving surface side of the photoelectric conversion element 1001
  • glass, a resin sheet, etc. and the sealing material (for example, EVA etc.) which fills the clearance gap between the said transparent base material and the said resin base material are included.
  • the output terminal 1003 is connected to a photoelectric conversion element 1001 with a wiring sheet disposed at one end of a plurality of photoelectric conversion elements 1001 connected in series.
  • the output terminal 1004 is connected to the photoelectric conversion element 1001 disposed at the other end of the plurality of photoelectric conversion elements 1001 connected in series.
  • the photoelectric conversion elements 10 and 102 to 105 have a high open circuit voltage (Voc) and improved element characteristics. Therefore, the performance of the photoelectric conversion module 1000 can be improved.
  • Voc open circuit voltage
  • the photoelectric conversion module according to the present embodiment is not limited to the configuration shown in FIG. 13, but any configuration as long as any one of the photoelectric conversion elements 10 and 102 to 105 according to the first to fifth embodiments is used. May be.
  • FIG. 14 is a schematic diagram illustrating a configuration of a photovoltaic power generation system according to the seventh embodiment.
  • the photovoltaic power generation system 1100 includes a photoelectric conversion module array 1101, a connection box 1102, a power conditioner 1103, a distribution board 1104, and a power meter 1105.
  • Functions such as “Home Energy Management System (HEMS)” and “Building Energy Management System (BEMS)” are added to the photovoltaic power generation system 1100. Can do.
  • HEMS Home Energy Management System
  • BEMS Building Energy Management System
  • connection box 1102 is connected to the photoelectric conversion module array 1101.
  • the power conditioner 1103 is connected to the connection box 1102.
  • Distribution board 1104 is connected to power conditioner 1103 and electrical equipment 1110.
  • the power meter 1105 is connected to the distribution board 1104 and system linkage.
  • the photoelectric conversion module array 1101 converts sunlight into electricity to generate DC power, and supplies the generated DC power to the connection box 1102.
  • connection box 1102 receives the DC power generated by the photoelectric conversion module array 1101 and supplies the received DC power to the power conditioner 1103.
  • the power conditioner 1103 converts the DC power received from the connection box 1102 into AC power, and supplies the converted AC power to the distribution board 1104.
  • Distribution board 1104 supplies AC power received from power conditioner 1103 and / or commercial power received via power meter 1105 to electrical equipment 1110. Further, when the AC power received from the power conditioner 1103 is larger than the power consumption of the electrical equipment 1110, the distribution board 1104 supplies the surplus AC power to the system linkage via the power meter 1105.
  • the power meter 1105 measures the power in the direction from the grid connection to the distribution board 1104 and measures the power in the direction from the distribution board 1104 to the grid cooperation.
  • FIG. 15 is a schematic diagram showing the configuration of the photoelectric conversion module array 1101 shown in FIG.
  • photoelectric conversion module array 1101 includes a plurality of photoelectric conversion modules 1120 and output terminals 1121 and 1122.
  • the plurality of photoelectric conversion modules 1120 are arranged in an array and connected in series. Each of the plurality of photoelectric conversion modules 1120 includes a photoelectric conversion module 1000 shown in FIG.
  • the output terminal 1121 is connected to a photoelectric conversion module 1120 located at one end of a plurality of photoelectric conversion modules 1120 connected in series.
  • the output terminal 1122 is connected to the photoelectric conversion module 1120 located at the other end of the plurality of photoelectric conversion modules 1120 connected in series.
  • the photoelectric conversion module array 1101 generates sunlight by converting sunlight into electricity, and supplies the generated DC power to the power conditioner 1103 via the connection box 1102.
  • the power conditioner 1103 converts the DC power received from the photoelectric conversion module array 1101 into AC power, and supplies the converted AC power to the distribution board 1104.
  • the distribution board 1104 supplies the AC power received from the power conditioner 1103 to the electrical device 1110 when the AC power received from the power conditioner 1103 is greater than or equal to the power consumption of the electrical device 1110. Then, the distribution board 1104 supplies surplus AC power to the system linkage via the power meter 1105.
  • Distribution board 1104 supplies AC power received from system cooperation and AC power received from power conditioner 1103 to electric device 1110 when the AC power received from power conditioner 1103 is less than the power consumption of electric device 1110. To do.
  • the photovoltaic power generation system 1100 includes any of the photoelectric conversion elements according to the first to fifth embodiments having improved element characteristics. Therefore, the performance of the photovoltaic power generation system 1100 can be improved.
  • the photovoltaic power generation system according to the present embodiment is not limited to the configuration shown in FIGS. 14 and 15, and may have any configuration as long as any of the photoelectric conversion elements according to the first to fifth embodiments is used. Also good.
  • a storage battery 1106 may be connected to the power conditioner 1103. In this case, output fluctuation due to fluctuations in the amount of sunlight can be suppressed, and power stored in the storage battery 1106 can be supplied even in a time zone without sunlight.
  • the storage battery 1106 may be built in the power conditioner 1103.
  • FIG. 17 is a schematic diagram illustrating a configuration of a photovoltaic power generation system according to the eighth embodiment.
  • the photovoltaic power generation system 1200 includes subsystems 1201 to 120n (n is an integer of 2 or more), power conditioners 1211 to 121n, and a transformer 1221.
  • the photovoltaic power generation system 1200 is a photovoltaic power generation system having a larger scale than the photovoltaic power generation system 1100 shown in FIGS.
  • the power conditioners 1211 to 121n are connected to the subsystems 1201 to 120n, respectively.
  • the transformer 1221 is connected to the power conditioners 1211 to 121n and the system linkage.
  • Each of the subsystems 1201 to 120n includes module systems 1231 to 123j (j is an integer of 2 or more).
  • Each of the module systems 1231 to 123j includes photoelectric conversion module arrays 1301 to 130i (i is an integer of 2 or more), connection boxes 1311 to 131i, and a current collection box 1321.
  • Each of the photoelectric conversion module arrays 1301 to 130i has the same configuration as the photoelectric conversion module array 1101 shown in FIG.
  • connection boxes 1311 to 131i are connected to the photoelectric conversion module arrays 1301 to 130i, respectively.
  • the current collection box 1321 is connected to the connection boxes 1311 to 131i. Also, j current collection boxes 1321 of the subsystem 1201 are connected to the power conditioner 1211. The j current collection boxes 1321 of the subsystem 1202 are connected to the power conditioner 1212. Hereinafter, similarly, j current collection boxes 1321 of the subsystem 120n are connected to the power conditioner 121n.
  • the i photoelectric conversion module arrays 1301 to 130i of the module system 1231 generate sunlight by converting sunlight into electricity, and the generated DC power is collected through the connection boxes 1311 to 131i, respectively.
  • the i photoelectric conversion module arrays 1301 to 130i of the module system 1232 generate sunlight by converting sunlight into electricity, and the generated DC power is collected through the connection boxes 1311 to 131i, respectively.
  • the i photoelectric conversion module arrays 1301 to 130i of the module system 123j convert sunlight into electricity to generate DC power, and the generated DC power is connected to the connection boxes 1311 to 131i, respectively. To the current collection box 1321.
  • the j current collection boxes 1321 of the subsystem 1201 supply DC power to the power conditioner 1211.
  • the j current collection boxes 1321 of the subsystem 1202 supply DC power to the power conditioner 1212 in the same manner.
  • the j current collecting boxes 1321 of the subsystem 120n supply DC power to the power conditioner 121n.
  • the power conditioners 1211 to 121n convert the DC power received from the subsystems 1201 to 120n into AC power, and supply the converted AC power to the transformer 1221.
  • the transformer 1221 receives AC power from the power conditioners 1211 to 121n, converts the voltage level of the received AC power, and supplies it to the system linkage.
  • the photovoltaic power generation system 1200 includes any of the photoelectric conversion elements according to the first to fifth embodiments having improved element characteristics. Therefore, the performance of the photovoltaic power generation system 1200 can be improved.
  • the photovoltaic power generation system according to the eighth embodiment is not limited to the configuration shown in FIG. 17, and any configuration can be used as long as any of the photoelectric conversion elements according to the first to fifth embodiments is used. Good.
  • a storage battery 1213 may be connected to the power conditioners 1211 to 121n, or the storage battery 1213 may be built in the power conditioners 1211 to 121n.
  • the power conditioners 1211 to 121n can appropriately convert part or all of the DC power received from the current collection box 1321 and store it in the storage battery 1213.
  • the electric power stored in the storage battery 1213 is appropriately supplied to the power conditioners 1211 to 121n according to the power generation amount of the subsystems 1201 to 120n, and is appropriately converted into electric power and supplied to the transformer 1221.
  • the texture structure is formed only on the light receiving surface of the semiconductor substrate.
  • the texture structure can be formed on the back surface of the semiconductor substrate.
  • the adhesion between the n-type amorphous semiconductor layer and the p-type amorphous semiconductor layer and each electrode is improved, and as a result, the yield and reliability of the photoelectric conversion element can be improved.
  • the contact area between the n-type amorphous semiconductor layer and the p-type amorphous semiconductor layer and each electrode is larger than when the back surface of the semiconductor substrate is flat, the contact resistance can also be reduced. .
  • the semiconductor substrate is an n-type single crystal silicon substrate.
  • the semiconductor substrate may be a p-type silicon substrate.
  • the antireflection film is formed on the light receiving surface of the semiconductor substrate, but the antireflection film may not be provided on the light receiving surface of the semiconductor substrate.
  • an n + layer in which a high concentration n-type dopant is diffused may be formed on the light receiving surface of the semiconductor substrate instead of the antireflection film.
  • an n + layer in which a high concentration n-type dopant is diffused may be formed between the light receiving surface of the semiconductor substrate and the antireflection film.
  • each amorphous semiconductor layer is formed using the plasma CVD method.
  • a CatCVD (Catalytic Chemical Vapor Deposition) method is used instead of the plasma CVD method. You can also.
  • the temperature of the semiconductor substrate is 100 to 300 ° C.
  • the deposition pressure is 10 to 500 Pa
  • the temperature of the thermal catalyst is 1500 to 2000 ° C.
  • RF power The film may be formed at a density of 0.01 to 1 W / cm 2 . By doing so, a high-quality amorphous semiconductor layer and a separation portion can be formed at a relatively low temperature and in a short time.

Abstract

Provided is a photoelectric conversion element in which excellent passivation can be obtained and contact resistance can be reduced. The photoelectric conversion element (10) is provided with: a semiconductor substrate (1); a passivation layer (3) formed on one surface of the semiconductor substrate (1), the passivation layer (3) having at least one recess (34a, 34b) on the surface and comprising an intrinsic amorphous semiconductor; a first amorphous semiconductor layer (4) formed on the passivation layer (3), the first amorphous semiconductor layer (4) having a first conductivity type; and a second amorphous semiconductor layer (5) formed on the passivation layer (3), the second amorphous semiconductor layer (5) having a second conductivity type that is opposite of the first conductivity type. At least one of the first amorphous semiconductor layer (4) and the second amorphous semiconductor layer (5) is disposed in the recess (34a, 34b).

Description

光電変換素子Photoelectric conversion element
　本開示は、光電変換素子に関する。 The present disclosure relates to a photoelectric conversion element.
　近年、光電変換素子としての太陽電池が注目されている。太陽電池の一例として、裏面接合型の太陽電池を挙げることができる。 In recent years, solar cells as photoelectric conversion elements have attracted attention. As an example of the solar cell, a back junction solar cell can be given.
　特表２０１０－５０３２２２号公報には、半導体基板の裏面に、パッシベーション層及びバックコンタクト層が形成された裏面接合型の太陽電池の例が開示されている。特表２０１０－５０３２２２号公報では、半導体基板の裏面全体にパッシベーション層が形成された後、水素プラズマを用いたエッチングによってパッシベーション層に開口が形成される。バックコンタクト層は、パッシベーション層の開口内に形成される。 JP-T-2010-503222 discloses an example of a back junction solar cell in which a passivation layer and a back contact layer are formed on the back surface of a semiconductor substrate. In JP-T-2010-503222, after a passivation layer is formed on the entire back surface of the semiconductor substrate, an opening is formed in the passivation layer by etching using hydrogen plasma. The back contact layer is formed in the opening of the passivation layer.
　特表２０１０－５０３２２２号公報では、半導体基板の裏面に到達するまでパッシベーション層をエッチングすることにより、厚み方向に貫通した開口をパッシベーション層に形成する。これにより、半導体基板とパッシベーション層との界面部分が損傷するため、パッシベーション性が悪化し、コンタクト抵抗が高くなる可能性がある。 In JP-T-2010-503222, an opening penetrating in the thickness direction is formed in the passivation layer by etching the passivation layer until it reaches the back surface of the semiconductor substrate. As a result, the interface portion between the semiconductor substrate and the passivation layer is damaged, so that the passivation property is deteriorated and the contact resistance may be increased.
　本開示は、良好なパッシベーション性を確保し、コンタクト抵抗を低減することができる光電変換素子を提供することを目的とする。 The present disclosure aims to provide a photoelectric conversion element that can ensure good passivation and reduce contact resistance.
　本開示に係る光電変換素子は、半導体基板と、半導体基板の一方面上に形成され、表面に少なくとも１つの凹部を有しており、真性非晶質半導体からなるパッシベーション層と、パッシベーション層上に形成され、第１導電型を有する第１非晶質半導体層と、パッシベーション層上に形成され、第１導電型と反対の第２導電型を有する第２非晶質半導体層と、を備え、第１非晶質半導体層及び第２非晶質半導体層の少なくとも一方は、凹部内に配置されている。 The photoelectric conversion element according to the present disclosure is formed on a semiconductor substrate, one surface of the semiconductor substrate, and has at least one concave portion on the surface, and is formed on a passivation layer made of an intrinsic amorphous semiconductor, and on the passivation layer. A first amorphous semiconductor layer formed and having a first conductivity type, and a second amorphous semiconductor layer formed on the passivation layer and having a second conductivity type opposite to the first conductivity type, At least one of the first amorphous semiconductor layer and the second amorphous semiconductor layer is disposed in the recess.
　本開示によれば、良好なパッシベーション性を確保し、コンタクト抵抗を低減することができる。 According to the present disclosure, it is possible to ensure good passivation and reduce contact resistance.
図１は、第１実施形態に係る光電変換素子の概略構成を示す断面図である。FIG. 1 is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element according to the first embodiment. 図２Ａは、図１に示す光電変換素子の製造方法における第１工程を示す図である。FIG. 2A is a diagram showing a first step in the method of manufacturing the photoelectric conversion element shown in FIG. 図２Ｂは、図１に示す光電変換素子の製造方法における第２工程を示す図である。FIG. 2B is a diagram showing a second step in the method of manufacturing the photoelectric conversion element shown in FIG. 図２Ｃは、図１に示す光電変換素子の製造方法における第３工程を示す図である。FIG. 2C is a diagram showing a third step in the method of manufacturing the photoelectric conversion element shown in FIG. 図２Ｄは、図１に示す光電変換素子の製造方法における第４工程を示す図である。FIG. 2D is a diagram showing a fourth step in the method of manufacturing the photoelectric conversion element shown in FIG. 図２Ｅは、図１に示す光電変換素子の製造方法における第５工程を示す図である。FIG. 2E is a diagram showing a fifth step in the method for manufacturing the photoelectric conversion element shown in FIG. 1. 図２Ｆは、図１に示す光電変換素子の製造方法における第６工程を示す図である。2F is a diagram showing a sixth step in the method of manufacturing the photoelectric conversion element shown in FIG. 図２Ｇは、図１に示す光電変換素子の製造方法における第７工程を示す図である。FIG. 2G is a diagram showing a seventh step in the method of manufacturing the photoelectric conversion element shown in FIG. 図２Ｈは、図１に示す光電変換素子の製造方法における第８工程を示す図である。FIG. 2H is a diagram showing an eighth step in the method of manufacturing the photoelectric conversion element shown in FIG. 図２Ｉは、第１～第８工程を経て完成した光電変換素子の概略構成を示す断面図である。FIG. 2I is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element completed through the first to eighth steps. 図３は、第４工程で形成する凹部の形状を示す図である。FIG. 3 is a diagram showing the shape of the recess formed in the fourth step. 図４Ａは、第５工程で形成するｎ型非晶質半導体層の形状を示す図である。FIG. 4A is a diagram showing the shape of the n-type amorphous semiconductor layer formed in the fifth step. 図４Ｂは、第５工程で形成するｎ型非晶質半導体層の別の形状を示す図である。FIG. 4B is a diagram showing another shape of the n-type amorphous semiconductor layer formed in the fifth step. 図５は、パッシベーション層の厚みごとに光電変換素子のライフタイムをした図である。FIG. 5 is a diagram showing the lifetime of the photoelectric conversion element for each thickness of the passivation layer. 図６Ａは、パッシベーション層のうちｎ型非晶質半導体層が配置される部分について、その厚みごとのコンタクト抵抗を示す図である。FIG. 6A is a diagram showing contact resistance for each thickness of a portion where an n-type amorphous semiconductor layer is disposed in the passivation layer. 図６Ｂは、パッシベーション層のうちｐ型非晶質半導体層が配置される部分について、その厚みごとのコンタクト抵抗を示す図である。FIG. 6B is a diagram showing contact resistance for each thickness of a portion where the p-type amorphous semiconductor layer is disposed in the passivation layer. 図７は、第２実施形態に係る光電変換素子の概略構成を示す断面図である。FIG. 7 is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element according to the second embodiment. 図８Ａは、図７に示す光電変換素子の製造方法における一工程を示す図である。FIG. 8A is a diagram showing one step in the method of manufacturing the photoelectric conversion element shown in FIG. 図８Ｂは、図７に示す光電変換素子の製造方法における一工程を示す図である。FIG. 8B is a diagram illustrating a step in the method for manufacturing the photoelectric conversion element illustrated in FIG. 7. 図８Ｃは、図７に示す光電変換素子の製造方法における一工程を示す図である。FIG. 8C is a diagram showing one step in the method for manufacturing the photoelectric conversion element shown in FIG. 7. 図８Ｄは、図８Ａ～図８Ｃに示す工程を経て完成した光電変換素子の概略構成を示す断面図である。FIG. 8D is a cross-sectional view showing a schematic configuration of the photoelectric conversion element completed through the steps shown in FIGS. 8A to 8C. 図９は、第３実施形態に係る光電変換素子の概略構成を示す断面図である。FIG. 9 is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element according to the third embodiment. 図１０は、第４実施形態に係る光電変換素子の概略構成を示す断面図である。FIG. 10 is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element according to the fourth embodiment. 図１１Ａは、図１０に示す光電変換素子の製造方法における一工程を示す図である。FIG. 11A is a diagram illustrating a step in the method of manufacturing the photoelectric conversion element illustrated in FIG. 10. 図１１Ｂは、図１０に示す光電変換素子の製造方法における一工程を示す図である。FIG. 11B is a diagram illustrating a step in the method for manufacturing the photoelectric conversion element illustrated in FIG. 10. 図１１Ｃは、図１０に示す光電変換素子の製造方法における一工程を示す図である。FIG. 11C is a diagram illustrating a step in the method of manufacturing the photoelectric conversion element illustrated in FIG. 10. 図１１Ｄは、図１０に示す光電変換素子の製造方法における一工程を示す図である。FIG. 11D is a diagram illustrating a step in the method of manufacturing the photoelectric conversion element illustrated in FIG. 10. 図１１Ｅは、図１１Ａ～図１１Ｄに示す工程を経て完成した光電変換素子の概略構成を示す断面図である。FIG. 11E is a cross-sectional view showing a schematic configuration of the photoelectric conversion element completed through the steps shown in FIGS. 11A to 11D. 図１２は、第５実施形態に係る光電変換素子の概略構成を示す断面図である。FIG. 12 is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element according to the fifth embodiment. 図１３は、第６実施形態に係る光電変換モジュールの構成例を示す概略図である。FIG. 13 is a schematic diagram illustrating a configuration example of a photoelectric conversion module according to the sixth embodiment. 図１４は、第７実施形態に係る太陽光発電システムの構成例を示す概略図である。FIG. 14 is a schematic diagram illustrating a configuration example of the solar power generation system according to the seventh embodiment. 図１５は、図１４に示す光電変換モジュールアレイの構成例を示す概略図である。FIG. 15 is a schematic diagram illustrating a configuration example of the photoelectric conversion module array illustrated in FIG. 14. 図１６は、第７実施形態に係る太陽光発電システムの他の構成例を示す概略図である。FIG. 16 is a schematic diagram illustrating another configuration example of the solar power generation system according to the seventh embodiment. 図１７は、第８実施形態に係る太陽光発電システムの構成例を示す概略図である。FIG. 17 is a schematic diagram illustrating a configuration example of the solar power generation system according to the eighth embodiment. 図１８は、第８実施形態に係る太陽光発電システムの他の構成例を示す概略図である。FIG. 18 is a schematic diagram illustrating another configuration example of the solar power generation system according to the eighth embodiment.
　実施形態に係る光電変換素子は、半導体基板と、半導体基板の一方面上に形成され、表面に少なくとも１つの凹部を有しており、真性非晶質半導体からなるパッシベーション層と、パッシベーション層上に形成され、第１導電型を有する第１非晶質半導体層と、パッシベーション層上に形成され、第１導電型と反対の第２導電型を有する第２非晶質半導体層と、を備え、第１非晶質半導体層及び第２非晶質半導体層の少なくとも一方は、凹部内に配置されている（第１の構成）。 The photoelectric conversion element according to the embodiment is formed on a semiconductor substrate, one surface of the semiconductor substrate, and has at least one concave portion on the surface, and is formed on a passivation layer made of an intrinsic amorphous semiconductor, and on the passivation layer. A first amorphous semiconductor layer formed and having a first conductivity type, and a second amorphous semiconductor layer formed on the passivation layer and having a second conductivity type opposite to the first conductivity type, At least one of the first amorphous semiconductor layer and the second amorphous semiconductor layer is disposed in the recess (first configuration).
　第１の構成によれば、第１及び第２非晶質半導体層と半導体基板との間にはパッシベーション層が介在しているため、第１及び第２非晶質半導体層の形成に際し、半導体基板とパッシベーション層との界面部分が損傷を受けにくい。このため、良好なパッシベーション性を確保することができる。 According to the first configuration, since the passivation layer is interposed between the first and second amorphous semiconductor layers and the semiconductor substrate, the semiconductor is formed when the first and second amorphous semiconductor layers are formed. The interface portion between the substrate and the passivation layer is not easily damaged. For this reason, favorable passivation property can be ensured.
　第１の構成によれば、パッシベーション層の表面に設けられた凹部内に、第１及び第２非晶質半導体層の少なくとも一方が配置されている。すなわち、パッシベーション層において、第１非晶質半導体層が配置される部分及び第２非晶質半導体層が配置される部分の少なくとも一方の厚みが、その他の部分の厚みよりも小さくなる。このため、半導体基板とパッシベーション層とのコンタクト抵抗を低減することができる。 According to the first configuration, at least one of the first and second amorphous semiconductor layers is disposed in the recess provided on the surface of the passivation layer. That is, in the passivation layer, the thickness of at least one of the portion where the first amorphous semiconductor layer is disposed and the portion where the second amorphous semiconductor layer is disposed is smaller than the thickness of the other portion. For this reason, the contact resistance between the semiconductor substrate and the passivation layer can be reduced.
　上記第１非晶質半導体層及び第２非晶質半導体層は、いずれも凹部内に配置してもよい（第２の構成）。 Both the first amorphous semiconductor layer and the second amorphous semiconductor layer may be disposed in the recess (second configuration).
　第２の構成によれば、パッシベーション層において、第１非晶質半導体層が配置される部分及び第２非晶質半導体層が配置される部分の双方の厚みがその他の部分の厚みよりも小さくなる。このため、パッシベーション層と半導体基板とのコンタクト抵抗をより低減することができる。 According to the second configuration, in the passivation layer, the thickness of both the portion where the first amorphous semiconductor layer is disposed and the portion where the second amorphous semiconductor layer is disposed is smaller than the thickness of the other portion. Become. For this reason, the contact resistance between the passivation layer and the semiconductor substrate can be further reduced.
　上記パッシベーション層は、第１非晶質半導体層が接する領域における厚みと、第２非晶質半導体層が接する領域における厚みとが異なっていてもよい（第３の構成）。 The thickness of the passivation layer in the region where the first amorphous semiconductor layer is in contact may be different from the thickness in the region where the second amorphous semiconductor layer is in contact (third configuration).
　第３の構成によれば、光電変換素子の特性に応じて、第１非晶質半導体層が接する領域における厚み及び第２非晶質半導体層が接する領域の厚み各々を決定することができる。このため、パッシベーション性を効率的に向上させることができる。 According to the third configuration, the thickness of the region in contact with the first amorphous semiconductor layer and the thickness of the region in contact with the second amorphous semiconductor layer can be determined according to the characteristics of the photoelectric conversion element. For this reason, passivation property can be improved efficiently.
　上記第１非晶質半導体層は、ｎ型の導電型を有し、第２非晶質半導体層は、ｐ型の導電型を有していてもよい。この場合、パッシベーション層において、第２非晶質半導体層が接する領域における厚みは、第１非晶質半導体層が接する領域における厚みよりも大きくてもよい（第４の構成）。 The first amorphous semiconductor layer may have an n-type conductivity, and the second amorphous semiconductor layer may have a p-type conductivity. In this case, in the passivation layer, the thickness in the region in contact with the second amorphous semiconductor layer may be larger than the thickness in the region in contact with the first amorphous semiconductor layer (fourth configuration).
　第４の構成によれば、パッシベーション層は、ｐ型の導電型を有する第２非晶質半導体層が接する領域の厚みが比較的大きくなるように形成される。このように構成することで、パッシベーション性が低下しやすいｐ側領域において、パッシベーション性の低下を抑制することができる。 According to the fourth configuration, the passivation layer is formed so that the thickness of the region in contact with the second amorphous semiconductor layer having the p-type conductivity is relatively large. By comprising in this way, the fall of passivation property can be suppressed in the p side area | region where passivation property tends to fall.
　上記パッシベーション層は、凹部が設けられていない部分の厚みが５ｎｍ～２０ｎｍであってもよい（第５の構成）。 The passivation layer may have a thickness of 5 nm to 20 nm in a portion where no recess is provided (fifth configuration).
　第５の構成によれば、パッシベーション層のうち、第１及び第２非晶質半導体層が配置されていない部分は、半導体基板を保護するのに十分な厚みを有する。このため、半導体基板内の第１及び第２非晶質半導体層間に相当する領域において、キャリア（電子及び正孔）の再結合を抑制することができ、良好なパッシベーション性を実現することができる。 According to the fifth configuration, the portion of the passivation layer where the first and second amorphous semiconductor layers are not disposed has a sufficient thickness to protect the semiconductor substrate. Therefore, recombination of carriers (electrons and holes) can be suppressed in a region corresponding to the first and second amorphous semiconductor layers in the semiconductor substrate, and good passivation can be realized. .
　以下、実施の形態について図面を参照しつつ説明する。図中同一又は相当する構成については同一の符号を付し、同じ説明を繰り返さない。 Hereinafter, embodiments will be described with reference to the drawings. In the drawings, the same or corresponding components are denoted by the same reference numerals, and the same description is not repeated.
　［第１実施形態］
　（光電変換素子の構成）
　図１は、第１実施形態に係る光電変換素子の概略構成を示す断面図である。図１に示すように、光電変換素子１０は、半導体基板１と、反射防止膜２と、パッシベーション層３と、ｎ型非晶質半導体層４と、ｐ型非晶質半導体層５と、電極６，７とを備える。 [First Embodiment]
(Configuration of photoelectric conversion element)
FIG. 1 is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element according to the first embodiment. As shown in FIG. 1, the photoelectric conversion element 10 includes a semiconductor substrate 1, an antireflection film 2, a passivation layer 3, an n-type amorphous semiconductor layer 4, a p-type amorphous semiconductor layer 5, an electrode. 6 and 7.
　半導体基板１は、例えば、ｎ型単結晶シリコン基板である。半導体基板１は、例えば、１００～１５０μｍの厚みを有する。 The semiconductor substrate 1 is, for example, an n-type single crystal silicon substrate. The semiconductor substrate 1 has a thickness of 100 to 150 μm, for example.
　半導体基板１の一方の面には、テクスチャ構造が形成されている。以下、半導体基板１において、テクスチャ構造が形成されている面を受光面と称し、受光面と反対の面を裏面と称する。 A texture structure is formed on one surface of the semiconductor substrate 1. Hereinafter, in the semiconductor substrate 1, the surface on which the texture structure is formed is referred to as a light receiving surface, and the surface opposite to the light receiving surface is referred to as a back surface.
　反射防止膜２は、半導体基板１の受光面上に形成されている。反射防止膜２は、例えば、窒化シリコン膜で構成される。反射防止膜２は、例えば、６０ｎｍの膜厚を有する。 The antireflection film 2 is formed on the light receiving surface of the semiconductor substrate 1. The antireflection film 2 is made of, for example, a silicon nitride film. The antireflection film 2 has a film thickness of 60 nm, for example.
　パッシベーション層３は、半導体基板１の裏面上に形成されている。パッシベーション層３は、表面に複数の凹部３４ａ，３４ｂを有する。凹部３４ａ，３４ｂは、例えば、水素プラズマを用いたエッチングによってパッシベーション層３に形成される。 The passivation layer 3 is formed on the back surface of the semiconductor substrate 1. The passivation layer 3 has a plurality of recesses 34a and 34b on the surface. The recesses 34a and 34b are formed in the passivation layer 3 by, for example, etching using hydrogen plasma.
　パッシベーション層３の厚み方向における上面は、ｎ型非晶質半導体層４が接する第１領域３１と、ｐ型非晶質半導体層５が接する第２領域３２とを含む。パッシベーション層３の厚み方向の上面は、さらに、ｎ型非晶質半導体層４及びｐ型非晶質半導体層５のいずれもが接していない第３領域３３を含む。 The upper surface in the thickness direction of the passivation layer 3 includes a first region 31 in contact with the n-type amorphous semiconductor layer 4 and a second region 32 in contact with the p-type amorphous semiconductor layer 5. The upper surface in the thickness direction of the passivation layer 3 further includes a third region 33 where neither the n-type amorphous semiconductor layer 4 nor the p-type amorphous semiconductor layer 5 is in contact.
　第１領域３１は、凹部３４ａの底面で構成される領域である。凹部３４ａの底面は、半導体基板１とパッシベーション層３との界面までは到達していない。凹部３４ａの底面は、厚み方向において、半導体基板１とパッシベーション層３との界面よりも上方に位置付けられている。 1st area | region 31 is an area | region comprised by the bottom face of the recessed part 34a. The bottom surface of the recess 34 a does not reach the interface between the semiconductor substrate 1 and the passivation layer 3. The bottom surface of the recess 34 a is positioned above the interface between the semiconductor substrate 1 and the passivation layer 3 in the thickness direction.
　第１領域３１におけるパッシベーション層３の厚みＴ３１は、第３領域３３におけるパッシベーション層３の厚みＴ３３よりも小さい。厚みＴ３１は、例えば、２～１０ｎｍの範囲で適宜決定することができる。 The thickness T31 of the passivation layer 3 in the first region 31 is smaller than the thickness T33 of the passivation layer 3 in the third region 33. The thickness T31 can be appropriately determined within a range of 2 to 10 nm, for example.
　第２領域３２は、凹部３４ｂの底面で構成される領域である。凹部３４ｂの底面は、半導体基板１とパッシベーション層３との界面までは到達していない。すなわち、凹部３４ｂの底面は、厚み方向において、半導体基板１とパッシベーション層３との界面よりも上方に位置付けられている。 2nd area | region 32 is an area | region comprised by the bottom face of the recessed part 34b. The bottom surface of the recess 34 b does not reach the interface between the semiconductor substrate 1 and the passivation layer 3. That is, the bottom surface of the recess 34 b is positioned above the interface between the semiconductor substrate 1 and the passivation layer 3 in the thickness direction.
　第２領域３２におけるパッシベーション層３の厚みＴ３２は、第３領域３３におけるパッシベーション層３の厚みＴ３３よりも小さい。厚みＴ３２は、例えば、２～１０ｎｍの範囲で適宜決定することができる。 The thickness T32 of the passivation layer 3 in the second region 32 is smaller than the thickness T33 of the passivation layer 3 in the third region 33. The thickness T32 can be appropriately determined within a range of 2 to 10 nm, for example.
　第２領域３２における厚みＴ３２は、第１領域３１における厚みＴ３１とは異なる。図１の例では、厚みＴ３２の方が厚みＴ３１よりも大きい。しかしながら、厚みＴ３２は、厚みＴ３１よりも小さくてもよく、厚みＴ３１と等しくてもよい。 The thickness T32 in the second region 32 is different from the thickness T31 in the first region 31. In the example of FIG. 1, the thickness T32 is larger than the thickness T31. However, the thickness T32 may be smaller than the thickness T31 or may be equal to the thickness T31.
　パッシベーション層３の厚み方向の上面において、凹部３４ａ，３４ｂは、互いに重なり合わないように設けられている。すなわち、第１領域３１及び第２領域３２は、半導体基板１の面内方向において離間して配置されている。半導体基板１の面内方向において、第１領域３１と第２領域３２との間には第３領域３３が介在している。 On the upper surface in the thickness direction of the passivation layer 3, the recesses 34a and 34b are provided so as not to overlap each other. That is, the first region 31 and the second region 32 are spaced apart in the in-plane direction of the semiconductor substrate 1. A third region 33 is interposed between the first region 31 and the second region 32 in the in-plane direction of the semiconductor substrate 1.
　半導体基板１の面内方向において、第１領域３１と第２領域３２との間隔Ｇは、２５０μｍ以下とすることが好ましい。間隔Ｇは、半導体基板１の面内方向において、第１領域３１のエッジと第２領域３２のエッジとの最短距離である。 The distance G between the first region 31 and the second region 32 in the in-plane direction of the semiconductor substrate 1 is preferably 250 μm or less. The interval G is the shortest distance between the edge of the first region 31 and the edge of the second region 32 in the in-plane direction of the semiconductor substrate 1.
　第３領域３３は、厚み方向において、パッシベーション層３の上面の全領域の中で最も上方に位置する領域である。パッシベーション層３は、第３領域３３において、良好なパッシベーション性を確保することが可能な程度の厚みを有することが好ましい。例えば、第３領域３３における厚みＴ３３は、５ｎｍ～２０ｎｍの範囲で設定することができる。 3rd area | region 33 is an area | region located in the uppermost among all the area | regions of the upper surface of the passivation layer 3 in the thickness direction. It is preferable that the passivation layer 3 has a thickness enough to ensure good passivation properties in the third region 33. For example, the thickness T33 in the third region 33 can be set in the range of 5 nm to 20 nm.
　ｎ型非晶質半導体層４は、パッシベーション層３上に形成されている。より具体的には、ｎ型非晶質半導体層４は、凹部３４ａ内に形成されている。したがって、ｎ型非晶質半導体層４は、第１領域３１である凹部３４ａの底面に接している。ｎ型非晶質半導体層４の厚みは、例えば、３～５０ｎｍである。 The n-type amorphous semiconductor layer 4 is formed on the passivation layer 3. More specifically, the n-type amorphous semiconductor layer 4 is formed in the recess 34a. Therefore, the n-type amorphous semiconductor layer 4 is in contact with the bottom surface of the recess 34 a that is the first region 31. The thickness of the n-type amorphous semiconductor layer 4 is, for example, 3 to 50 nm.
　ｎ型非晶質半導体層４は、ｎ型の導電型を有し、水素を含有する非晶質半導体層である。ｎ型非晶質半導体層４は、例えば、ｎ型ドーパントとしてリン（Ｐ）を含有する。ｎ型非晶質半導体層４は、例えば、ｎ型非晶質シリコン、ｎ型非晶質シリコンゲルマニウム、ｎ型非晶質ゲルマニウム、ｎ型非晶質シリコンカーバイド、ｎ型非晶質シリコンナイトライド、ｎ型非晶質シリコンオキサイド、ｎ型非晶質シリコンオキシナイトライド、又はｎ型非晶質シリコンカーボンオキサイド等で構成することができる。 The n-type amorphous semiconductor layer 4 is an amorphous semiconductor layer having n-type conductivity and containing hydrogen. The n-type amorphous semiconductor layer 4 contains, for example, phosphorus (P) as an n-type dopant. The n-type amorphous semiconductor layer 4 includes, for example, n-type amorphous silicon, n-type amorphous silicon germanium, n-type amorphous germanium, n-type amorphous silicon carbide, and n-type amorphous silicon nitride. N-type amorphous silicon oxide, n-type amorphous silicon oxynitride, n-type amorphous silicon carbon oxide, or the like.
　ｐ型非晶質半導体層５は、パッシベーション層３上に形成されている。より具体的には、ｐ型非晶質半導体層５は、凹部３４ｂ内に形成されている。したがって、ｐ型非晶質半導体層５は、第２領域３２である凹部３４ｂの底面に接している。ｐ型非晶質半導体層５の厚みは、例えば、５～５０ｎｍである。 The p-type amorphous semiconductor layer 5 is formed on the passivation layer 3. More specifically, the p-type amorphous semiconductor layer 5 is formed in the recess 34b. Therefore, the p-type amorphous semiconductor layer 5 is in contact with the bottom surface of the recess 34 b that is the second region 32. The thickness of the p-type amorphous semiconductor layer 5 is, for example, 5 to 50 nm.
　ｐ型非晶質半導体層５は、ｐ型の導電型を有し、水素を含有する非晶質半導体層である。ｐ型非晶質半導体層５は、例えば、ｐ型ドーパントとしてボロン（Ｂ）を含む。ｐ型非晶質半導体層５は、例えば、ｐ型非晶質シリコン、ｐ型非晶質シリコンゲルマニウム、ｐ型非晶質ゲルマニウム、ｐ型非晶質シリコンカーバイド、ｐ型非晶質シリコンナイトライド、ｐ型非晶質シリコンオキサイド、ｐ型非晶質シリコンオキシナイトライド、又はｐ型非晶質シリコンカーボンオキサイド等で構成することができる。 The p-type amorphous semiconductor layer 5 is an amorphous semiconductor layer having p-type conductivity and containing hydrogen. The p-type amorphous semiconductor layer 5 includes, for example, boron (B) as a p-type dopant. The p-type amorphous semiconductor layer 5 includes, for example, p-type amorphous silicon, p-type amorphous silicon germanium, p-type amorphous germanium, p-type amorphous silicon carbide, and p-type amorphous silicon nitride. , P-type amorphous silicon oxide, p-type amorphous silicon oxynitride, p-type amorphous silicon carbon oxide, or the like.
　上述した通り、第２領域３２は、半導体基板１の面内方向において、第１領域３１から離間して配置されている。よって、パッシベーション層３の表面において、第２領域３２上に設けられるｐ型非晶質半導体層５は、第１領域３１上に設けられるｎ型非晶質半導体層４から離間して配置される。 As described above, the second region 32 is arranged away from the first region 31 in the in-plane direction of the semiconductor substrate 1. Therefore, on the surface of the passivation layer 3, the p-type amorphous semiconductor layer 5 provided on the second region 32 is disposed away from the n-type amorphous semiconductor layer 4 provided on the first region 31. .
　図示は省略するが、パッシベーション層３上には、複数のｎ型非晶質半導体層４及び複数のｐ型非晶質半導体層５が、半導体基板１の面内方向において交互に配置されている。 Although not shown, a plurality of n-type amorphous semiconductor layers 4 and a plurality of p-type amorphous semiconductor layers 5 are alternately arranged in the in-plane direction of the semiconductor substrate 1 on the passivation layer 3. .
　電極６は、ｎ型非晶質半導体層４上に形成される。電極７は、ｐ型非晶質半導体層５上に形成される。 The electrode 6 is formed on the n-type amorphous semiconductor layer 4. The electrode 7 is formed on the p-type amorphous semiconductor layer 5.
　各電極６，７は、積層構造を有していてもよい。例えば、各電極６，７は、透明導電層と、金属層とを含んでいてもよい。各電極６，７の透明導電層の厚みは、例えば、３～１００ｎｍとすることができる。各電極６，７の金属層の厚みは、５０ｎｍ以上であることが好ましい。 The electrodes 6 and 7 may have a laminated structure. For example, each electrode 6 and 7 may include a transparent conductive layer and a metal layer. The thickness of the transparent conductive layer of each electrode 6 and 7 can be 3 to 100 nm, for example. The thickness of the metal layer of each electrode 6 and 7 is preferably 50 nm or more.
　電極６の透明導電層は、ｎ型非晶質半導体層４と密着性が高い材料で構成されることが好ましい。電極７の透明導電層は、ｐ型非晶質半導体層５と密着性が高い材料で構成されることが好ましい。各電極６，７の金属層は、導電率が高い金属で構成されることが好ましい。 The transparent conductive layer of the electrode 6 is preferably made of a material having high adhesion to the n-type amorphous semiconductor layer 4. The transparent conductive layer of the electrode 7 is preferably made of a material having high adhesion to the p-type amorphous semiconductor layer 5. The metal layers of the electrodes 6 and 7 are preferably made of a metal having high conductivity.
　各電極６，７の透明導電層は、例えば、ＩＴＯ（Ｉｎｄｉｕｍ　Ｔｉｎ　Ｏｘｉｄｅ）、ＺｎＯ、又はＩＷＯ（Ｉｎｄｉｕｍ　Ｔｕｎｇｓｔｅｎ　Ｏｘｉｄｅ）で構成することができる。各電極６，７の金属層は、例えば、銀（Ａｇ）、ニッケル（Ｎｉ）、アルミニウム（Ａｌ）、銅（Ｃｕ）、錫（Ｓｎ）、白金（Ｐｔ）、金（Ａｕ）、クロム（Ｃｒ）、タングステン（Ｗ）、コバルト（Ｃｏ）、もしくはチタン（Ｔｉ）、これらの合金、又はこれらの積層膜で構成することができる。 The transparent conductive layers of the electrodes 6 and 7 can be made of, for example, ITO (Indium Tin Oxide), ZnO, or IWO (Indium Tungsten Oxide). The metal layers of the electrodes 6 and 7 are, for example, silver (Ag), nickel (Ni), aluminum (Al), copper (Cu), tin (Sn), platinum (Pt), gold (Au), chromium (Cr ), Tungsten (W), cobalt (Co), titanium (Ti), alloys thereof, or laminated films thereof.
　各電極６，７は、上述の透明導電層又は金属層を含んでいなくてもよい。各電極６，７が透明導電層を含まない場合、各電極６，７の金属層は、Ｔｉ，Ｎｉ，Ａｌ，Ｃｒ等からなり、且つ１～１０ｎｍ程度の厚みを有する密着層と、Ａｌ，Ａｇ等を主成分とする光反射金属層との積層構造を有することができる。 The electrodes 6 and 7 may not include the above-described transparent conductive layer or metal layer. When each electrode 6, 7 does not include a transparent conductive layer, the metal layer of each electrode 6, 7 is made of Ti, Ni, Al, Cr, etc., and has an adhesion layer having a thickness of about 1 to 10 nm, Al, It can have a laminated structure with a light reflecting metal layer mainly composed of Ag or the like.
　（光電変換素子の製造方法）
　以下、上述のように構成された光電変換素子１０の製造方法について説明する。図２Ａ～図２Ｉは、光電変換素子１０の製造方法における各工程を示す図である。 (Manufacturing method of photoelectric conversion element)
Hereinafter, the manufacturing method of the photoelectric conversion element 10 comprised as mentioned above is demonstrated. 2A to 2I are diagrams showing each step in the method for manufacturing the photoelectric conversion element 10. FIG.
　まず、図２Ａに示す半導体基板１を準備する（第１工程）。 First, the semiconductor substrate 1 shown in FIG. 2A is prepared (first step).
　具体的には、バルクのシリコンから１００～３００μｍの厚さのウェハを切り出し、ウェハ表面のダメージ層を除去するためのエッチングと、厚さを調整するためのエッチングとを行う。これらのエッチングがなされたウェハの片面に保護膜を形成する。保護膜には、例えば、酸化シリコン、窒化シリコン等が用いられる。 Specifically, a wafer having a thickness of 100 to 300 μm is cut out from bulk silicon, and etching for removing a damaged layer on the wafer surface and etching for adjusting the thickness are performed. A protective film is formed on one surface of the etched wafer. For example, silicon oxide, silicon nitride, or the like is used for the protective film.
　保護膜が形成されたウェハに対し、ＮａＯＨ、ＫＯＨ等のアルカリ溶液（例えば、ＫＯＨ：１～５ｗｔ％、イソプロピルアルコール：１～１０ｗｔ％の水溶液）を用いてウェットエッチングを行う。これにより、保護膜が形成されていない面が異方性エッチングされ、当該面に複数のピラミッド形状を含むテクスチャ構造が形成される。その後、ウェハから保護膜を除去することにより、図２Ａに示す半導体基板１が得られる。 Wet etching is performed on the wafer on which the protective film is formed using an alkaline solution such as NaOH or KOH (for example, an aqueous solution of KOH: 1 to 5 wt%, isopropyl alcohol: 1 to 10 wt%). Thereby, the surface where the protective film is not formed is anisotropically etched, and a texture structure including a plurality of pyramid shapes is formed on the surface. Then, the semiconductor substrate 1 shown in FIG. 2A is obtained by removing the protective film from the wafer.
　次に、図２Ｂに示すように、半導体基板１の受光面、つまりテクスチャ構造が形成された面に反射防止膜２を形成する（第２工程）。 Next, as shown in FIG. 2B, the antireflection film 2 is formed on the light receiving surface of the semiconductor substrate 1, that is, the surface on which the texture structure is formed (second step).
　反射防止膜２は、例えば、酸化シリコン膜と、窒化シリコン膜とを半導体基板１の受光面上に順に積層することによって形成することができる。酸化シリコン膜は、半導体基板１の受光面を熱酸化又はウェット処理することによって形成することができる。熱酸化処理の場合、例えば、半導体基板１を酸素又は水蒸気の雰囲気中で９００～１０００℃に加熱する。ウェット処理の場合、例えば、半導体基板１を過酸化水素、硝酸、又はオゾン水等に浸漬し、その後、ドライ雰囲気中で８００～１０００℃に加熱する。窒化シリコン膜は、例えば、プラズマＣＶＤ（Ｐｌａｓｍａ　Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法によって形成することができる。 The antireflection film 2 can be formed, for example, by sequentially stacking a silicon oxide film and a silicon nitride film on the light receiving surface of the semiconductor substrate 1. The silicon oxide film can be formed by subjecting the light receiving surface of the semiconductor substrate 1 to thermal oxidation or wet treatment. In the case of the thermal oxidation treatment, for example, the semiconductor substrate 1 is heated to 900 to 1000 ° C. in an atmosphere of oxygen or water vapor. In the case of wet processing, for example, the semiconductor substrate 1 is immersed in hydrogen peroxide, nitric acid, ozone water, or the like, and then heated to 800 to 1000 ° C. in a dry atmosphere. The silicon nitride film can be formed by, for example, a plasma CVD (Plasma Chemical Vapor Deposition) method.
　窒化シリコン膜と半導体基板１との間には、酸化シリコン膜に代えて、ｉ型非晶質半導体層及びｎ型非晶質半導体層を順次形成することができる。ｉ型非晶質半導体層及びｎ型非晶質半導体層は、例えば、プラズマＣＶＤ法によって形成することができる。 An i-type amorphous semiconductor layer and an n-type amorphous semiconductor layer can be sequentially formed between the silicon nitride film and the semiconductor substrate 1 instead of the silicon oxide film. The i-type amorphous semiconductor layer and the n-type amorphous semiconductor layer can be formed by, for example, a plasma CVD method.
　次に、図２Ｃに示すように、半導体基板１の裏面にｉ型非晶質半導体層３００を形成する（第３工程）。 Next, as shown in FIG. 2C, an i-type amorphous semiconductor layer 300 is formed on the back surface of the semiconductor substrate 1 (third step).
　例えば、プラズマＣＶＤ法によって半導体基板１の裏面全体にｉ型非晶質シリコンを堆積することにより、ｉ型非晶質半導体層３００が形成される。ｉ型非晶質シリコンは、良好なパッシベーション性を確保するために十分な厚さ、例えば、５～２０ｎｍの厚さになるまで堆積される。ｉ型非晶質半導体層３００は、パッシベーション層３の第３領域３３における厚みＴ３３（図１）と等しい厚みＴ３００を有するように形成される。 For example, i-type amorphous semiconductor layer 300 is formed by depositing i-type amorphous silicon on the entire back surface of semiconductor substrate 1 by plasma CVD. The i-type amorphous silicon is deposited to a thickness sufficient to ensure good passivation, for example, 5 to 20 nm. The i-type amorphous semiconductor layer 300 is formed to have a thickness T300 equal to the thickness T33 (FIG. 1) in the third region 33 of the passivation layer 3.
　ｉ型非晶質半導体層３００の形成に際し、プラズマＣＶＤ装置が備える反応室に導入される反応ガスは、例えば、水素ガス及びシランガスである。このときの処理条件は、例えば、半導体基板１の温度：１３０～２１０℃、水素ガス流量：０～１００ｓｃｃｍ、シランガス（ＳｉＨ４）流量：約４０ｓｃｃｍ、反応室内の圧力：４０～１２０Ｐａ、周波数：１３．５６ＭＨｚ、電力密度：５～１５ｍＷ／ｃｍ２とすることができる。 When forming the i-type amorphous semiconductor layer 300, the reaction gas introduced into the reaction chamber provided in the plasma CVD apparatus is, for example, hydrogen gas and silane gas. The processing conditions at this time are, for example, the temperature of the semiconductor substrate 1: 130 to 210 ° C., the hydrogen gas flow rate: 0 to 100 sccm, the silane gas (SiH 4 ) flow rate: about 40 sccm, the pressure in the reaction chamber: 40 to 120 Pa, and the frequency: 13 .56 MHz, power density: 5 to 15 mW / cm 2 .
　次に、凹部３４ａをｉ型非晶質半導体層３００に形成する（第４工程）。 Next, the recess 34a is formed in the i-type amorphous semiconductor layer 300 (fourth step).
　具体的には、図２Ｄに示すように、ｉ型非晶質半導体層３００上にシャドーマスク２００を配置する。そして、ｉ型非晶質半導体層３００に対し、シャドーマスク２００の開口２００ａを介して、例えば、水素プラズマによるエッチングを行う。このとき、ｉ型非晶質半導体層３００から半導体基板１が露出しないよう、ｉ型非晶質半導体層３００の厚みＴ３００よりも小さい深さのエッチングが行われる。これにより、凹部３４ａがｉ型非晶質半導体層３００に形成される。 Specifically, as shown in FIG. 2D, a shadow mask 200 is disposed on the i-type amorphous semiconductor layer 300. Then, the i-type amorphous semiconductor layer 300 is etched by, for example, hydrogen plasma through the opening 200 a of the shadow mask 200. At this time, etching of a depth smaller than the thickness T300 of the i-type amorphous semiconductor layer 300 is performed so that the semiconductor substrate 1 is not exposed from the i-type amorphous semiconductor layer 300. As a result, the recess 34 a is formed in the i-type amorphous semiconductor layer 300.
　水素プラズマによるエッチングは、プラズマＣＶＤ装置を用いて行うことができる。このときの処理条件は、例えば、半導体基板１の温度：１３０～２１０℃、水素ガス１００％の雰囲気中、反応室内の圧力：４０～３００Ｐａ、周波数：１３．５６ＭＨｚ、電力密度：１０～１００ｍＷ／ｃｍ２、処理時間：１０～３００秒とすることができる。このような処理条件により、ｉ型非晶質半導体層３００を貫通させることなく数ｎｍのエッチバックを行うことができ、半導体基板１とｉ型非晶質半導体層３００との界面がエッチングによって損傷するのを防止することができる。 Etching with hydrogen plasma can be performed using a plasma CVD apparatus. The processing conditions at this time are, for example, the temperature of the semiconductor substrate 1: 130 to 210 ° C., an atmosphere of 100% hydrogen gas, the pressure in the reaction chamber: 40 to 300 Pa, the frequency: 13.56 MHz, and the power density: 10 to 100 mW / cm 2 , treatment time: 10 to 300 seconds. Under such processing conditions, etch back of several nm can be performed without penetrating the i-type amorphous semiconductor layer 300, and the interface between the semiconductor substrate 1 and the i-type amorphous semiconductor layer 300 is damaged by etching. Can be prevented.
　ここで、第４工程で形成された凹部３４ａの形状とシャドーマスク２００の開口２００ａとの関係について説明する。図３は、エッチング深さと、開口２００ａの幅（半導体基板１の面内方向における開口２００ａの長さ）との関係を示す図である。 Here, the relationship between the shape of the recess 34a formed in the fourth step and the opening 200a of the shadow mask 200 will be described. FIG. 3 is a diagram showing the relationship between the etching depth and the width of the opening 200a (the length of the opening 200a in the in-plane direction of the semiconductor substrate 1).
　図３には、シャドーマスク２００の開口２００ａの幅が２００μｍ，４００μｍ，６００μｍ，８００μｍ，１０００μｍである場合について、同一時間でエッチングを行ったときのエッチング深さが示されている。図３から、開口２００ａの幅が大きくなるほどエッチング深さが小さく、エッチング速度が遅くなることがわかる。すなわち、開口２００ａの幅が大きければ広くて浅い凹部３４ａが形成され、開口２００ａの幅が小さければ狭くて深い凹部３４ａが形成される。このように、シャドーマスク２００の開口２００ａの幅を変更することにより、様々な形状の凹部３４ａを形成することができる。 FIG. 3 shows the etching depth when etching is performed in the same time when the width of the opening 200a of the shadow mask 200 is 200 μm, 400 μm, 600 μm, 800 μm, and 1000 μm. FIG. 3 shows that the larger the width of the opening 200a, the smaller the etching depth and the slower the etching rate. That is, if the width of the opening 200a is large, a wide and shallow concave portion 34a is formed, and if the width of the opening 200a is small, a narrow and deep concave portion 34a is formed. As described above, by changing the width of the opening 200a of the shadow mask 200, the recesses 34a having various shapes can be formed.
　ｉ型非晶質半導体層３００に凹部３４ａを形成した後、図２Ｅに示すように、凹部３４ａ内にｎ型非晶質半導体層４を形成する（第５工程）。 After forming the recess 34a in the i-type amorphous semiconductor layer 300, as shown in FIG. 2E, the n-type amorphous semiconductor layer 4 is formed in the recess 34a (fifth step).
　具体的には、第４工程で用いたシャドーマスク２００をｉ型非晶質半導体層３００上に配置したまま、例えば、プラズマＣＶＤ法により、開口２００ａを介して凹部３４ａ内にｎ型の非晶質シリコンを堆積する。これにより凹部３４ａ内にｎ型非晶質半導体層４が形成される。 Specifically, with the shadow mask 200 used in the fourth step disposed on the i-type amorphous semiconductor layer 300, for example, an n-type amorphous material is formed in the recess 34a through the opening 200a by plasma CVD. Deposit quality silicon. Thereby, the n-type amorphous semiconductor layer 4 is formed in the recess 34a.
　ｎ型非晶質半導体層４の形成に際し、プラズマＣＶＤ装置が備える反応室に導入される反応ガスは、例えば、シランガス、水素ガス、及び水素ガスで希釈されたホスフィンガス（ホスフィン濃度は例えば１％）である。このときの処理条件は、例えば、半導体基板１の温度：約１７０℃、水素ガス流量：０～１００ｓｃｃｍ、シランガス流量：約４０ｓｃｃｍ、ホスフィンガス流量：約４０ｓｃｃｍ、反応室内の圧力：約４０Ｐａ、高周波電力密度：約８．３３ｍＷ／ｃｍ２とすることができる。 When forming the n-type amorphous semiconductor layer 4, the reaction gas introduced into the reaction chamber provided in the plasma CVD apparatus is, for example, silane gas, hydrogen gas, and phosphine gas diluted with hydrogen gas (phosphine concentration is 1%, for example) ). The processing conditions at this time are, for example, a temperature of the semiconductor substrate 1 of about 170 ° C., a hydrogen gas flow rate of 0 to 100 sccm, a silane gas flow rate of about 40 sccm, a phosphine gas flow rate of about 40 sccm, a pressure in the reaction chamber of about 40 Pa, and a high frequency power. Density: about 8.33 mW / cm 2 .
　ここで、第５工程で形成されるｎ型非晶質半導体層４の形状について説明する。図４Ａは、触針段差計にてｎ型非晶質半導体層４を半導体基板１の面内方向にスキャンし、ｎ型非晶質半導体層４の膜厚を測定した結果を示している。 Here, the shape of the n-type amorphous semiconductor layer 4 formed in the fifth step will be described. FIG. 4A shows a result of measuring the film thickness of the n-type amorphous semiconductor layer 4 by scanning the n-type amorphous semiconductor layer 4 in the in-plane direction of the semiconductor substrate 1 with a stylus profilometer.
　シャドーマスク２００の開口２００ａを介して形成されたｎ型非晶質半導体層４は、図４Ａに示すように、フラット領域Ｌと、膜厚減少領域Ｔと、テーパー形状領域Ｒとを含む。図４Ａでは、フラット領域Ｌの膜厚を１．０として規格化したｎ型非晶質半導体層４の膜厚を縦軸にとっている。 The n-type amorphous semiconductor layer 4 formed through the opening 200a of the shadow mask 200 includes a flat region L, a film thickness reduction region T, and a tapered region R, as shown in FIG. 4A. In FIG. 4A, the thickness of the n-type amorphous semiconductor layer 4 normalized by setting the thickness of the flat region L to 1.0 is plotted on the vertical axis.
　ｎ型非晶質半導体層４は、半導体基板１の面内方向における略中心である点Ｃにおいて最大の膜厚を有する。フラット領域Ｌは、最大の膜厚から膜厚がほとんど変化しない領域をいう。図４Ａの例では、スキャン方向の長さが２８０μｍ～３８０μｍの間の領域がフラット領域Ｌである。フラット領域Ｌの長さは開口２００ａの幅に依存するが、デポレート（堆積速度）は開口２００ａの幅に依存しない。 The n-type amorphous semiconductor layer 4 has the maximum film thickness at a point C that is substantially the center in the in-plane direction of the semiconductor substrate 1. The flat region L is a region where the film thickness hardly changes from the maximum film thickness. In the example of FIG. 4A, the region between the lengths in the scanning direction between 280 μm and 380 μm is the flat region L. The length of the flat region L depends on the width of the opening 200a, but the deposition (deposition rate) does not depend on the width of the opening 200a.
　図４Ａに示すように、フラット領域Ｌの一方の端部Ｋ１０から点Ｋ１１までの領域と、フラット領域Ｌの他方の端部Ｋ２０から点Ｋ１２までの領域は、膜厚が緩やかに減少している。これに対し、点Ｋ１１から点Ｋ２１までの領域及び点Ｋ１２から点Ｋ２２までの領域は、膜厚が急峻に減少している。つまり、フラット領域Ｌの一方の端部Ｋ１０から点Ｋ１１までの領域、及びフラット領域Ｌの他方の端部Ｋ２０から点Ｋ１２までの領域における各膜厚の減少率（第１減少率）よりも、点Ｋ１１から点Ｋ２１までの領域及び点Ｋ１２から点Ｋ２２までの領域における各膜厚の減少率（第２減少率）が大きくなっている。 As shown in FIG. 4A, the film thickness gradually decreases in the region from one end K10 to the point K11 of the flat region L and the region from the other end K20 to the point K12 of the flat region L. . On the other hand, the film thickness sharply decreases in the region from the point K11 to the point K21 and the region from the point K12 to the point K22. That is, rather than the reduction rate (first reduction rate) of each film thickness in the region from one end K10 to the point K11 of the flat region L and the region from the other end K20 to the point K12 of the flat region L, The decreasing rate (second decreasing rate) of each film thickness in the region from the point K11 to the point K21 and the region from the point K12 to the point K22 is large.
　膜厚減少領域Ｔは、ｎ型非晶質半導体層４において膜厚の減少率が緩やかに変化する領域であり、フラット領域Ｌの端部Ｋ１０から点Ｋ１１までの領域、及びフラット領域Ｌの端部Ｋ２０から点Ｋ１２までの領域である。すなわち、膜厚減少領域Ｔは、半導体基板１上に成膜される一の薄膜において、当該薄膜の膜厚が最大となる点を第１の点とし、当該薄膜の面内方向において膜厚の減少率が第１減少率から第２減少率に変化する点を第２の点とした場合、当該薄膜の面内方向における第１の点から第２の点までの領域である。 The film thickness reduction region T is a region in which the film thickness reduction rate gradually changes in the n-type amorphous semiconductor layer 4, and includes a region from the end K10 to the point K11 of the flat region L and an end of the flat region L. This is an area from the portion K20 to the point K12. That is, the film thickness reduction region T has a first point at which the film thickness of the thin film is maximized in one thin film formed on the semiconductor substrate 1, and the film thickness decreases in the in-plane direction of the thin film. When the point at which the rate of decrease changes from the first rate of decrease to the second rate of decrease is taken as the second point, this is the region from the first point to the second point in the in-plane direction of the thin film.
　テーパー形状領域Ｒは、テーパー状に成膜された領域であり、点Ｋ２１，Ｋ２２それぞれからｎ型非晶質半導体層４の下方端Ｋ３１，Ｋ３２までの領域である。テーパー形状領域Ｒは、開口２００ａの外側、つまりシャドーマスク２００の下方に回り込んで成膜された領域である。テーパー形状領域Ｒの幅は、ｎ型非晶質半導体層４の成膜条件等によって変動するが、例えば４００μｍ以下であり、好ましくは１００μｍ以下である。 The tapered region R is a region formed in a tapered shape, and is a region from the points K21 and K22 to the lower ends K31 and K32 of the n-type amorphous semiconductor layer 4, respectively. The tapered region R is a region formed around the opening 200 a, that is, around the shadow mask 200. The width of the tapered region R varies depending on the film forming conditions of the n-type amorphous semiconductor layer 4 and is, for example, 400 μm or less, preferably 100 μm or less.
　膜厚減少領域Ｔにおける膜厚の減少量は、フラット領域Ｌの膜厚の５％以上であることが好ましく、１０％以上であることがより好ましい。つまり、図４Ａにおいて、フラット領域Ｌの端部Ｋ１０，Ｋ２０から点Ｋ１１，Ｋ２１までの膜厚の減少量が、フラット領域Ｌの膜厚の５％以上であることが好ましく、１０％以上であることがより好ましい。図４Ａの例では、膜厚減少領域Ｔは、フラット領域Ｌの膜厚よりも２０％以上減少しており、好ましい状態である。膜厚減少領域Ｔの幅は、２０μｍ以上が好ましく、１００μｍ以上がより好ましい。 The amount of film thickness reduction in the film thickness reduction region T is preferably 5% or more of the film thickness of the flat region L, and more preferably 10% or more. That is, in FIG. 4A, the amount of decrease in the film thickness from the ends K10, K20 of the flat region L to the points K11, K21 is preferably 5% or more of the film thickness of the flat region L, and is preferably 10% or more. It is more preferable. In the example of FIG. 4A, the film thickness reduction region T is reduced by 20% or more than the film thickness of the flat region L, which is a preferable state. The width of the film thickness reduction region T is preferably 20 μm or more, and more preferably 100 μm or more.
　図４Ｂは、ｎ型非晶質半導体層４の別の形状を示す図である。図４Ｂの例では、ｎ型非晶質半導体層４がフラット領域Ｌを有していないが、ｎ型非晶質半導体層４の略中心である点Ｃから点Ｋ１０までの領域の膜厚の減少率は、点Ｋ１０から点Ｋ２０までの領域の膜厚の減少率よりも小さい。点Ｃ１０から点Ｋ１０までの各領域Ｔ１は、図４Ｂに示す形状を有するｎ型非晶質半導体層４の膜厚減少領域である。 FIG. 4B is a diagram showing another shape of the n-type amorphous semiconductor layer 4. In the example of FIG. 4B, the n-type amorphous semiconductor layer 4 does not have the flat region L, but the film thickness of the region from the point C to the point K10 that is the approximate center of the n-type amorphous semiconductor layer 4 is increased. The decreasing rate is smaller than the decreasing rate of the film thickness in the region from the point K10 to the point K20. Each region T1 from the point C10 to the point K10 is a film thickness decreasing region of the n-type amorphous semiconductor layer 4 having the shape shown in FIG. 4B.
　図４Ｂの例では、点Ｋ２０の外側の膜厚はほぼ一定であり、テーパー形状領域Ｒが形成されていない。しかしながら、例えば、成膜圧力や、シャドーマスク２００とパッシベーション層３との距離等を調整することにより、テーパー形状領域Ｒを形成することもできる。 4B, the film thickness outside the point K20 is substantially constant, and the tapered region R is not formed. However, for example, the tapered region R can be formed by adjusting the film forming pressure, the distance between the shadow mask 200 and the passivation layer 3, or the like.
　図示は省略するが、ｎ型非晶質半導体層４は、半導体基板１の面内方向における略中心である点Ｃの膜厚が両端部の膜厚よりも小さいものであってもよい。すなわち、ｎ型非晶質半導体層４は、両端部よりも中心部が窪んだ形状に形成されていてもよい。この場合であっても、ｎ型非晶質半導体層４は、膜厚が最大となる点を第１の点とし、ｎ型非晶質半導体層４の面内方向における膜厚の減少率が第１減少率から第２減少率に変化する点を第２の点としたときに、ｎ型非晶質半導体層４の面内方向における第１の点から第２の点までの領域である膜厚減少領域を有することができる。 Although not shown, the n-type amorphous semiconductor layer 4 may have a film thickness at a point C that is substantially the center in the in-plane direction of the semiconductor substrate 1 smaller than the film thickness at both ends. That is, the n-type amorphous semiconductor layer 4 may be formed in a shape in which the central portion is recessed from both end portions. Even in this case, the n-type amorphous semiconductor layer 4 has the first point at which the film thickness is maximum, and the reduction rate of the film thickness in the in-plane direction of the n-type amorphous semiconductor layer 4 is The region from the first point to the second point in the in-plane direction of the n-type amorphous semiconductor layer 4 when the point where the first decrease rate changes to the second decrease rate is the second point. A film thickness reduction region can be provided.
　ｎ型非晶質半導体層４の形成後、図２Ｆに示すように、凹部３４ｂをｉ型非晶質半導体層３００に形成する（第６工程）。 After the n-type amorphous semiconductor layer 4 is formed, as shown in FIG. 2F, a recess 34b is formed in the i-type amorphous semiconductor layer 300 (sixth step).
　具体的には、ｉ型非晶質半導体層３００上にシャドーマスク２０１を配置する。そして、ｉ型非晶質半導体層３００に対し、シャドーマスク２０１の開口２０１ａを介して、例えば、水素プラズマによるエッチングを行う。このとき、ｉ型非晶質半導体層３００から半導体基板１が露出しないよう、ｉ型非晶質半導体層３００の厚みよりも小さい深さのエッチングが行われる。これにより、凹部３４ｂがｉ型非晶質半導体層３００に形成され、パッシベーション層３が完成する。 Specifically, a shadow mask 201 is disposed on the i-type amorphous semiconductor layer 300. Then, the i-type amorphous semiconductor layer 300 is etched by, for example, hydrogen plasma through the opening 201 a of the shadow mask 201. At this time, etching with a depth smaller than the thickness of the i-type amorphous semiconductor layer 300 is performed so that the semiconductor substrate 1 is not exposed from the i-type amorphous semiconductor layer 300. Thereby, the recess 34b is formed in the i-type amorphous semiconductor layer 300, and the passivation layer 3 is completed.
　水素プラズマによるエッチングは、第４工程と同様の処理条件で、プラズマＣＶＤ装置を用いて行うことができる。よって、凹部３４ｂの形成においても、ｉ型非晶質半導体層３００を貫通させることなく数ｎｍのエッチバックを行うことができ、半導体基板１とｉ型非晶質半導体層３００との界面がエッチングによって損傷するのを防止することができる。 Etching with hydrogen plasma can be performed using a plasma CVD apparatus under the same processing conditions as in the fourth step. Therefore, even when the recess 34b is formed, etch back of several nm can be performed without penetrating the i-type amorphous semiconductor layer 300, and the interface between the semiconductor substrate 1 and the i-type amorphous semiconductor layer 300 is etched. Can prevent damage.
　ただし、凹部３４ｂの形成の際のエッチング深さは、凹部３４ａの形成の際のエッチング深さと異なる。図２Ｆに示す例では、凹部３４ｂの形成の際のエッチング深さＤ３４ｂは、凹部３４ａの形成の際のエッチング深さＤ３４ａよりも小さい。 However, the etching depth when forming the recess 34b is different from the etching depth when forming the recess 34a. In the example shown in FIG. 2F, the etching depth D34b when forming the recess 34b is smaller than the etching depth D34a when forming the recess 34a.
　凹部３４ａと同様に、凹部３４ｂは、シャドーマスク２０１の開口２０１ａの幅に応じて様々な形状に形成することができる。例えば、凹部３４ａの形成に用いたシャドーマスク２００の開口２００ａよりも開口２０１ａの幅を大きくすることにより、凹部３４ａよりも浅い凹部３４ｂを形成してもよい。また、エッチング時間等の処理条件を凹部３４ａの形成時と変更することによって、凹部３４ｂの形状を調整してもよい。 Similar to the recess 34a, the recess 34b can be formed in various shapes depending on the width of the opening 201a of the shadow mask 201. For example, the concave portion 34b shallower than the concave portion 34a may be formed by making the width of the opening 201a larger than the opening 200a of the shadow mask 200 used for forming the concave portion 34a. Further, the shape of the recess 34b may be adjusted by changing the processing conditions such as the etching time when forming the recess 34a.
　次に、凹部３４ｂ内上にｐ型非晶質半導体層５を形成する（第７工程）。 Next, the p-type amorphous semiconductor layer 5 is formed in the recess 34b (seventh step).
　具体的には、図２Ｇに示すように、第６工程で用いたシャドーマスク２０１をパッシベーション層３上に配置したまま、例えば、プラズマＣＶＤ法により、開口２０１ａを介して凹部３４ｂ内にｐ型の非晶質シリコンを堆積する。これにより、凹部３４ｂ内にｐ型非晶質半導体層５が形成される。 Specifically, as shown in FIG. 2G, while the shadow mask 201 used in the sixth step is placed on the passivation layer 3, for example, a p-type is formed in the recess 34b through the opening 201a by the plasma CVD method. Amorphous silicon is deposited. Thereby, the p-type amorphous semiconductor layer 5 is formed in the recess 34b.
　ｐ型非晶質半導体層５の形成に際し、プラズマＣＶＤ装置が備える反応室に導入される反応ガスは、例えば、シランガス、水素ガス、及び水素希釈されたジボランガス（ジボラン濃度は例えば約２％）である。このときの処理条件は、例えば、半導体基板１の温度：１５０～２１０℃、水素ガス流量：０～１００ｓｃｃｍ、シランガス流量：約４０ｓｃｃｍ、ジボランガス流量：約４０ｓｃｃｍ、反応室内の圧力：４０～１２０Ｐａ、高周波電力密度：５～１５ｍＷ／ｃｍ２とすることができる。 When forming the p-type amorphous semiconductor layer 5, the reaction gas introduced into the reaction chamber provided in the plasma CVD apparatus is, for example, silane gas, hydrogen gas, and diborane gas diluted with hydrogen (diborane concentration is about 2%, for example). is there. The processing conditions at this time are, for example, the temperature of the semiconductor substrate 1: 150 to 210 ° C., hydrogen gas flow rate: 0 to 100 sccm, silane gas flow rate: about 40 sccm, diborane gas flow rate: about 40 sccm, pressure in the reaction chamber: 40 to 120 Pa, high frequency Power density: 5 to 15 mW / cm 2 .
　図示は省略するが、シャドーマスク２０１の開口２０１ａを介して形成されたｐ型非晶質半導体層５は、図４に示すｎ型非晶質半導体層４と同様の形状を有する。すなわち、ｐ型非晶質半導体層５は、ｎ型非晶質半導体層４と同様に、フラット領域Ｌと、膜厚減少領域Ｔと、テーパー形状領域Ｒとを含んでいる。 Although not shown, the p-type amorphous semiconductor layer 5 formed through the opening 201a of the shadow mask 201 has the same shape as the n-type amorphous semiconductor layer 4 shown in FIG. That is, similarly to the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5 includes a flat region L, a film thickness reduction region T, and a tapered region R.
　次に、ｎ型非晶質半導体層４及びｐ型非晶質半導体層５上にそれぞれ電極６，７を形成する（第８工程）。 Next, electrodes 6 and 7 are formed on the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, respectively (eighth step).
　具体的には、図２Ｈに示すように、パッシベーション層３、ｎ型非晶質半導体層４及びｐ型非晶質半導体層５が形成された半導体基板１の裏面にマスク２０２を配置する。そして、例えば、蒸着法やスパッタ法等により、マスク２０２の開口２０２ａを介して、ｎ型非晶質半導体層４及びｐ型非晶質半導体層５上にそれぞれ電極６，７を形成する。 Specifically, as shown in FIG. 2H, a mask 202 is disposed on the back surface of the semiconductor substrate 1 on which the passivation layer 3, the n-type amorphous semiconductor layer 4, and the p-type amorphous semiconductor layer 5 are formed. Then, electrodes 6 and 7 are formed on the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 through the openings 202a of the mask 202, for example, by vapor deposition or sputtering.
　以上の各工程により、図２Ｉに示す光電変換素子１０が製造される。 Through the above steps, the photoelectric conversion element 10 shown in FIG. 2I is manufactured.
　なお、上記各工程において使用される各マスク２００，２０１，２０２は、例えば、ステンレス鋼、銅、ニッケル、ニッケルを含む合金（例えば、４２アロイ、又はインバー材等）、モリブデン等の金属からなるメタルマスクである。各マスク２００～２０４は、ガラス、セラミック、有機フィルム等で構成されていてもよい。 In addition, each mask 200, 201, 202 used in each of the above steps is, for example, a metal made of a metal such as stainless steel, copper, nickel, an alloy containing nickel (for example, 42 alloy or Invar material), molybdenum or the like. It is a mask. Each mask 200 to 204 may be made of glass, ceramic, organic film or the like.
　（効果）
　以上のように、第１実施形態に係る光電変換素子１０では、半導体基板１と、ｎ型非晶質半導体層４及びｐ型非晶質半導体層５との間にパッシベーション層３が介在している。このため、ｎ型非晶質半導体層４及びｐ型非晶質半導体層５を形成する際、半導体基板１とパッシベーション層３との界面部分が損傷を受けにくい。よって、良好なパッシベーション性を確保することができる。 (effect)
As described above, in the photoelectric conversion element 10 according to the first embodiment, the passivation layer 3 is interposed between the semiconductor substrate 1 and the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5. Yes. For this reason, when the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are formed, the interface portion between the semiconductor substrate 1 and the passivation layer 3 is not easily damaged. Therefore, good passivation properties can be ensured.
　ｎ型非晶質半導体層４及びｐ型非晶質半導体層５は、それぞれパッシベーション層３の凹部３４ａ，３４ｂ内に配置されている。すなわち、パッシベーション層３において、ｎ型非晶質半導体層４が接する第１領域３１における厚みＴ３１、及びｐ型非晶質半導体層５が接する第２領域３２における厚みＴ３２は、ｎ型非晶質半導体層４及びｐ型非晶質半導体層５が接していない第３領域３３における厚みＴ３３よりも小さい。このため、ｎ側領域及びｐ側領域において、半導体基板１とパッシベーション層３とのコンタクト抵抗を低減することができる。 The n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are disposed in the recesses 34a and 34b of the passivation layer 3, respectively. That is, in the passivation layer 3, the thickness T31 in the first region 31 that is in contact with the n-type amorphous semiconductor layer 4 and the thickness T32 in the second region 32 that is in contact with the p-type amorphous semiconductor layer 5 are n-type amorphous. It is smaller than the thickness T33 in the third region 33 where the semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are not in contact. For this reason, the contact resistance between the semiconductor substrate 1 and the passivation layer 3 can be reduced in the n-side region and the p-side region.
　パッシベーション層３において、ｐ型非晶質半導体層５が接する第２領域３２の厚みＴ３２は、ｎ型非晶質半導体層４が接する第１領域３１の厚みＴ３１よりも大きい。このようにすることで、半導体基板１がｎ型単結晶シリコン基板の場合、パッシベーション層３において第２領域３２に相当する部分と半導体基板１との界面における少数キャリア（正孔）の再結合が抑制され、パッシベーション層３全体としてのパッシベーション性を高めることができる。 In the passivation layer 3, the thickness T32 of the second region 32 in contact with the p-type amorphous semiconductor layer 5 is larger than the thickness T31 of the first region 31 in contact with the n-type amorphous semiconductor layer 4. Thus, when the semiconductor substrate 1 is an n-type single crystal silicon substrate, minority carriers (holes) are recombined at the interface between the portion corresponding to the second region 32 and the semiconductor substrate 1 in the passivation layer 3. It is suppressed and the passivation property as the whole passivation layer 3 can be improved.
　凹部３４ａ，３４ｂは、半導体基板１をｉ型非晶質半導体層３００から露出させることなく形成される。このため、凹部３４ａ，３４ｂの形成に際し、半導体基板１とｉ型非晶質半導体層３００（パッシベーション層３）との界面部分が損傷を受けず、パッシベーション性を高めることができる。 The recesses 34 a and 34 b are formed without exposing the semiconductor substrate 1 from the i-type amorphous semiconductor layer 300. For this reason, when forming the recesses 34a and 34b, the interface portion between the semiconductor substrate 1 and the i-type amorphous semiconductor layer 300 (passivation layer 3) is not damaged, and the passivation property can be improved.
　光電変換素子１０において、半導体基板１は受光面にテクスチャ構造を有している。このため、半導体基板１の受光面で光が反射するのを防止することができ、光電変換素子１０に対する光入射量を大きく確保することができる。 In the photoelectric conversion element 10, the semiconductor substrate 1 has a texture structure on the light receiving surface. For this reason, it is possible to prevent light from being reflected from the light receiving surface of the semiconductor substrate 1, and to ensure a large amount of light incident on the photoelectric conversion element 10.
　パッシベーション層３において、ｎ型及びｐ型非晶質半導体層４，５が接しない第３領域３３の厚みＴ３３は、例えば、５ｎｍ～２０ｎｍとされる。これにより、半導体基板１をパッシベーション層３によって十分に保護することができ、パッシベーション性をより向上させることができる。 In the passivation layer 3, the thickness T33 of the third region 33 where the n-type and p-type amorphous semiconductor layers 4 and 5 are not in contact with each other is, for example, 5 nm to 20 nm. Thereby, the semiconductor substrate 1 can be sufficiently protected by the passivation layer 3, and the passivation property can be further improved.
　パッシベーション層３において、ｎ型非晶質半導体層４が接する第１領域３１及びｐ型非晶質半導体層５が接する第２領域３２の各厚みＴ３１，Ｔ３２は、例えば、２ｎｍ～１０ｎｍとされる。これにより、パッシベーション層３において、ｎ型非晶質半導体層４及びｐ型非晶質半導体層５が配置される部分の厚みが十分に小さくなり、ｎ側及びｐ側領域におけるコンタクト抵抗をより確実に低減することができる。 In the passivation layer 3, the thicknesses T31 and T32 of the first region 31 in contact with the n-type amorphous semiconductor layer 4 and the second region 32 in contact with the p-type amorphous semiconductor layer 5 are, for example, 2 nm to 10 nm. . As a result, in the passivation layer 3, the thickness of the portion where the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are disposed is sufficiently small, and the contact resistance in the n-side and p-side regions is more reliably ensured. Can be reduced.
　半導体基板１の面内方向において、第１領域３１と第２領域３２との間隔Ｇは、例えば、２５０μｍ以下とされる。これにより、パッシベーション層３上に配置されるｎ型非晶質半導体層４及びｐ型非晶質半導体層５の面積を大きく確保することができ、キャリア（電子及び正孔）の収集効率を向上させることができる。 The distance G between the first region 31 and the second region 32 in the in-plane direction of the semiconductor substrate 1 is, for example, 250 μm or less. Thereby, a large area of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 disposed on the passivation layer 3 can be secured, and the collection efficiency of carriers (electrons and holes) is improved. Can be made.
　パッシベーション層３は、半導体基板１の裏面にｉ型非晶質半導体層３００を形成した後、ｉ型非晶質半導体層３００に凹部３４ａ，３４ｂを設けることで形成される。ｉ型非晶質半導体層３００に凹部３４ａ，３４ｂを設ける工程において、半導体基板１の裏面がｉ型非晶質半導体層３００から露出することはない。つまり、パッシベーション層３は、半導体基板１の裏面の一部を露出させる工程を経ることなく形成される。このため、半導体基板１とパッシベーション層３との界面部分が損傷を受けることがなく、良好なパッシベーション性を実現することができる。 The passivation layer 3 is formed by forming the i-type amorphous semiconductor layer 300 on the back surface of the semiconductor substrate 1 and then providing the recesses 34 a and 34 b in the i-type amorphous semiconductor layer 300. In the step of providing the recesses 34 a and 34 b in the i-type amorphous semiconductor layer 300, the back surface of the semiconductor substrate 1 is not exposed from the i-type amorphous semiconductor layer 300. That is, the passivation layer 3 is formed without going through a step of exposing a part of the back surface of the semiconductor substrate 1. For this reason, the interface portion between the semiconductor substrate 1 and the passivation layer 3 is not damaged, and good passivation can be realized.
　第１実施形態では、パッシベーション層３の凹部３４ａの形成及びｎ型非晶質半導体層４の形成は、同一のシャドーマスク２００を使用し、連続して行われる。また、パッシベーション層３の凹部３４ｂの形成及びｐ型非晶質半導体層５の形成は、同一のシャドーマスク２０１を使用し、連続して行われる。このため、パッシベーション層３に不純物が混入するのを抑制することができ、良好なパッシベーション性を確保することができる。 In the first embodiment, the formation of the recess 34 a of the passivation layer 3 and the formation of the n-type amorphous semiconductor layer 4 are performed continuously using the same shadow mask 200. In addition, the formation of the recess 34 b of the passivation layer 3 and the formation of the p-type amorphous semiconductor layer 5 are performed continuously using the same shadow mask 201. For this reason, it can suppress that an impurity mixes into the passivation layer 3, and can ensure favorable passivation property.
　ここで、第１実施形態に係る光電変換素子１０によって得られる効果をより具体的に説明する。図５は、光電変換素子１０のライフタイムをパッシベーション層３の厚みごとに示す図である。図６Ａは、ｎ側領域のコンタクト抵抗を第１領域３１の厚みごとに示す図である。図６Ｂは、ｐ側領域のコンタクト抵抗を第２領域３２の厚みごとに示す図である。 Here, the effect obtained by the photoelectric conversion element 10 according to the first embodiment will be described more specifically. FIG. 5 is a diagram illustrating the lifetime of the photoelectric conversion element 10 for each thickness of the passivation layer 3. FIG. 6A is a diagram illustrating the contact resistance in the n-side region for each thickness of the first region 31. FIG. 6B is a diagram showing the contact resistance in the p-side region for each thickness of the second region 32.
　図５において、１．７５倍の膜厚、１．５倍の膜厚、及び１．２５倍の膜厚とは、それぞれ、パッシベーション層３が、所定の厚み（標準膜厚）の１．７５倍の厚み、１．５倍の厚み、及び１．２５倍の厚みを有することを意味する。図５に示すように、パッシベーション性を示す光電変換素子１０のライフタイムは、パッシベーション層３の厚みが大きいほど大きい。また、パッシベーション層３の厚みが大きいほど、経時劣化が緩和されている。このことから、パッシベーション層３の厚みを大きくすれば、良好なパッシベーション性を確保できることがわかる。 In FIG. 5, the film thickness of 1.75 times, the film thickness of 1.5 times, and the film thickness of 1.25 times are 1.75 times that the passivation layer 3 has a predetermined thickness (standard film thickness). It means having double thickness, 1.5 times thickness, and 1.25 times thickness. As shown in FIG. 5, the lifetime of the photoelectric conversion element 10 exhibiting passivation properties increases as the thickness of the passivation layer 3 increases. In addition, as the thickness of the passivation layer 3 increases, deterioration with time is alleviated. From this, it can be seen that if the thickness of the passivation layer 3 is increased, good passivation properties can be secured.
　ただし、図６Ｂに示すように、ｐ側領域におけるコンタクト抵抗は、第２領域３２の厚みＴ３２が大きくなると顕著に増加する。よって、パッシベーション層３において、第２領域３２の厚みＴ３２を他の領域の厚みＴ３１，Ｔ３３よりも小さくすることで、コンタクト抵抗を効果的に低減できることがわかる。一方、図６Ａに示すように、ｎ側領域におけるコンタクト抵抗は、第１領域３１の厚みＴ３１に応じて顕著に増加するものではないが、第２領域３２の厚みＴ３２に加え、第１領域３１の厚みＴ３１を他の領域の厚みＴ３３よりも小さくすれば、コンタクト抵抗のさらなる低減を図ることができる。 However, as shown in FIG. 6B, the contact resistance in the p-side region significantly increases as the thickness T32 of the second region 32 increases. Therefore, it can be seen that the contact resistance can be effectively reduced by making the thickness T32 of the second region 32 smaller than the thicknesses T31 and T33 of the other regions in the passivation layer 3. On the other hand, as shown in FIG. 6A, the contact resistance in the n-side region does not increase significantly according to the thickness T31 of the first region 31, but in addition to the thickness T32 of the second region 32, If the thickness T31 is made smaller than the thickness T33 of other regions, the contact resistance can be further reduced.
　第１実施形態に係る光電変換素子１０では、パッシベーション層３において、ｎ型及びｐ型非晶質半導体層４，５が接しない第３領域３３の厚みＴ３３が十分に確保されている。その一方で、パッシベーション層３において、ｎ型非晶質半導体層４が接する第１領域３１の厚みＴ３１、及びｐ型非晶質半導体層５が接する第２領域３２の厚みＴ３２は、第３領域３３の厚みＴ３３よりも小さくなっている。したがって、良好なパッシベーション性を確保しつつ、コンタクト抵抗を低減することができる。 In the photoelectric conversion element 10 according to the first embodiment, in the passivation layer 3, the thickness T33 of the third region 33 where the n-type and p-type amorphous semiconductor layers 4 and 5 are not in contact is sufficiently ensured. On the other hand, in the passivation layer 3, the thickness T31 of the first region 31 in contact with the n-type amorphous semiconductor layer 4 and the thickness T32 of the second region 32 in contact with the p-type amorphous semiconductor layer 5 are the third region. It is smaller than the thickness T33 of 33. Therefore, it is possible to reduce contact resistance while ensuring good passivation.
　［第２実施形態］
　（光電変換素子の構成）
　図７は、第２実施形態に係る光電変換素子の概略構成を示す断面図である。図７に示すように、光電変換素子１０２は、パッシベーション層３２０上でｎ型非晶質半導体層４の一部とｐ型非晶質半導体層５の一部とが重なり合っている点で第１実施形態と異なる。 [Second Embodiment]
(Configuration of photoelectric conversion element)
FIG. 7 is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element according to the second embodiment. As shown in FIG. 7, the photoelectric conversion element 102 is first in that a part of the n-type amorphous semiconductor layer 4 and a part of the p-type amorphous semiconductor layer 5 overlap on the passivation layer 320. Different from the embodiment.
　パッシベーション層３２０には、階段状の底面を有する凹部３２４が形成されている。凹部３２４の底面のうち下段面は、ｎ型非晶質半導体層４が接する第１領域３２１である。凹部３２４の底面のうち上段面は、ｐ型非晶質半導体層５が接する第２領域３２２である。 In the passivation layer 320, a recess 324 having a stepped bottom surface is formed. The lower surface of the bottom surface of the recess 324 is a first region 321 in contact with the n-type amorphous semiconductor layer 4. The upper surface of the bottom surface of the recess 324 is a second region 322 that is in contact with the p-type amorphous semiconductor layer 5.
　パッシベーション層３２０でも、第１実施形態と同様、第１領域３２１における厚みＴ３２１が第２領域３２２における厚みＴ３２２よりも小さい。また、ｎ型非晶質半導体層４及びｐ型非晶質半導体層５が接していない第３領域３０３の厚みＴ３２３は、第１領域３２１における厚みＴ３２１及び第２領域３２２における厚みＴ３２２よりも大きい。 Also in the passivation layer 320, the thickness T321 in the first region 321 is smaller than the thickness T322 in the second region 322, as in the first embodiment. The thickness T323 of the third region 303 where the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are not in contact is larger than the thickness T321 in the first region 321 and the thickness T322 in the second region 322. .
　ｎ型非晶質半導体層４は、底面全体がパッシベーション層３の第１領域３２１に接している。ｐ型非晶質半導体層５は、底面の大部分がパッシベーション層３の第２領域３２２に接しているが、底面の一部がｎ型非晶質半導体層４の厚み方向の上面に接している。すなわち、ｎ型非晶質半導体層４及びｐ型非晶質半導体層５は、一部が重なり合うようにパッシベーション層３上に配置されている。 The entire bottom surface of the n-type amorphous semiconductor layer 4 is in contact with the first region 321 of the passivation layer 3. The p-type amorphous semiconductor layer 5 has most of the bottom surface in contact with the second region 322 of the passivation layer 3, but part of the bottom surface is in contact with the top surface in the thickness direction of the n-type amorphous semiconductor layer 4. Yes. That is, the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are disposed on the passivation layer 3 so as to partially overlap.
　図７の例では、ｎ型非晶質半導体層４上にｐ型非晶質半導体層５の一部が重なっているが、ｐ型非晶質半導体層５上にｎ型非晶質半導体層４の一部が重なっていてもよい。ｐ型非晶質半導体層５上にｎ型非晶質半導体層４の一部を重ねる場合、ｎ型非晶質半導体層４が配置される第１領域３２１の厚みＴ３２１を、ｐ型非晶質半導体層５が配置される第２領域３２２の厚みＴ３２２よりも小さくしてもよい。 In the example of FIG. 7, the p-type amorphous semiconductor layer 5 partially overlaps the n-type amorphous semiconductor layer 4, but the n-type amorphous semiconductor layer is formed on the p-type amorphous semiconductor layer 5. A part of 4 may overlap. When a part of the n-type amorphous semiconductor layer 4 is stacked on the p-type amorphous semiconductor layer 5, the thickness T321 of the first region 321 in which the n-type amorphous semiconductor layer 4 is disposed is set to a p-type amorphous. The thickness T322 of the second region 322 where the quality semiconductor layer 5 is disposed may be smaller.
　（光電変換素子の製造方法）
　以下、光電変換素子１０２の製造方法について説明する。 (Manufacturing method of photoelectric conversion element)
Hereinafter, a method for manufacturing the photoelectric conversion element 102 will be described.
　図８Ａに示すように、まず、第１実施形態の第１及び第２工程と同様にして、半導体基板１の受光面にテクスチャ構造を形成し、反射防止膜２を形成する。続いて、第１実施形態の第３工程と同様にして、半導体基板１の裏面にｉ型非晶質半導体層３０２を形成する。さらに、第１実施形態の第４及び第５工程と同様にして、ｉ型非晶質半導体層３０２上に凹部４００ａを形成し、凹部４００ａ内にｎ型非晶質半導体層４を形成する。 As shown in FIG. 8A, first, in the same manner as in the first and second steps of the first embodiment, a texture structure is formed on the light receiving surface of the semiconductor substrate 1, and the antireflection film 2 is formed. Subsequently, an i-type amorphous semiconductor layer 302 is formed on the back surface of the semiconductor substrate 1 in the same manner as in the third step of the first embodiment. Further, in the same manner as the fourth and fifth steps of the first embodiment, the recess 400a is formed on the i-type amorphous semiconductor layer 302, and the n-type amorphous semiconductor layer 4 is formed in the recess 400a.
　次に、凹部４００ｂをｉ型非晶質半導体層３０２に形成する。 Next, the concave portion 400 b is formed in the i-type amorphous semiconductor layer 302.
　凹部４００ｂは、第１実施形態の第６工程と同様の方法及び条件で形成することができる。しかしながら、凹部４００ｂは、凹部４００ａと接するように形成される点で、第１実施形態の第６工程で形成した凹部３４ｂとは異なる。すなわち、凹部４００ｂは、半導体基板１の面内方向において凹部４００ａから離間しないよう、凹部４００ａに隣接して形成される。 The recess 400b can be formed by the same method and conditions as in the sixth step of the first embodiment. However, the recess 400b is different from the recess 34b formed in the sixth step of the first embodiment in that the recess 400b is formed in contact with the recess 400a. That is, the recess 400 b is formed adjacent to the recess 400 a so as not to be separated from the recess 400 a in the in-plane direction of the semiconductor substrate 1.
　具体的には、図８Ｂに示すように、シャドーマスク２００の開口２０３ａを介して、例えば、水素プラズマによるエッチングをｉ型非晶質半導体層３０２に施し、凹部４００ｂを形成する。このとき、ｉ型非晶質半導体層３０２から半導体基板１が露出しないよう、ｉ型非晶質半導体層３０２の厚みよりも小さい深さのエッチングが行われる。ただし、凹部４００ｂの形成に際するエッチング深さは、凹部４００ａの形成に際するエッチング深さよりも小さい。凹部４００ａ，４００ｂにより、階段状の底面を有する凹部３２４が構成される。 Specifically, as shown in FIG. 8B, the i-type amorphous semiconductor layer 302 is etched by, for example, hydrogen plasma through the opening 203a of the shadow mask 200 to form the recess 400b. At this time, etching with a depth smaller than the thickness of the i-type amorphous semiconductor layer 302 is performed so that the semiconductor substrate 1 is not exposed from the i-type amorphous semiconductor layer 302. However, the etching depth for forming the recess 400b is smaller than the etching depth for forming the recess 400a. A recess 324 having a stepped bottom surface is formed by the recesses 400a and 400b.
　次に、凹部４００ｂ内にｐ型非晶質半導体層５を形成する。 Next, the p-type amorphous semiconductor layer 5 is formed in the recess 400b.
　ｐ型非晶質半導体層５は、例えば、プラズマＣＶＤ法を用い、第１実施形態の第７工程と同様の処理条件で形成することができる。具体的には、図８Ｃに示すように、シャドーマスク２０４の開口２０４ａを介し、凹部４００ｂ内にｐ型非晶質半導体層５を形成する。このとき、凹部４００ｂ及びｎ型非晶質半導体層４の一部が開口２０４ａから露出している。したがって、ｐ型非晶質半導体層５は、一部がｎ型非晶質半導体層４上に形成され、その他の部分が凹部４００ｂ内に形成される。 The p-type amorphous semiconductor layer 5 can be formed using, for example, a plasma CVD method under the same processing conditions as in the seventh step of the first embodiment. Specifically, as shown in FIG. 8C, the p-type amorphous semiconductor layer 5 is formed in the recess 400b through the opening 204a of the shadow mask 204. At this time, the recess 400b and a part of the n-type amorphous semiconductor layer 4 are exposed from the opening 204a. Therefore, a part of the p-type amorphous semiconductor layer 5 is formed on the n-type amorphous semiconductor layer 4 and the other part is formed in the recess 400b.
　その後、図８Ｄに示すように、第１実施形態の第８工程と同様にして、ｎ型非晶質半導体層４及びｐ型非晶質半導体層５上にそれぞれ電極６，７を形成する。 Thereafter, as shown in FIG. 8D, electrodes 6 and 7 are formed on the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, respectively, in the same manner as in the eighth step of the first embodiment.
　（効果）
　以上のように、第２実施形態に係る光電変換素子１０２では、パッシベーション層３上において、ｎ型非晶質半導体層４の一部とｐ型非晶質半導体層５の一部とが重なり合っている。すなわち、パッシベーション層３において、ｎ型非晶質半導体層４が接する第１領域３２１と、ｐ型非晶質半導体層５が接する第２領域３２２とが互いに接している。これにより、パッシベーション層３上におけるｎ型非晶質半導体層４及びｐ型非晶質半導体層５の面積を大きくすることができ、キャリア（電子及び正孔）の収集効率を向上させることができる。 (effect)
As described above, in the photoelectric conversion element 102 according to the second embodiment, a part of the n-type amorphous semiconductor layer 4 and a part of the p-type amorphous semiconductor layer 5 are overlapped on the passivation layer 3. Yes. That is, in the passivation layer 3, the first region 321 in contact with the n-type amorphous semiconductor layer 4 and the second region 322 in contact with the p-type amorphous semiconductor layer 5 are in contact with each other. Thereby, the areas of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 on the passivation layer 3 can be increased, and the collection efficiency of carriers (electrons and holes) can be improved. .
　［第３実施形態］
　（光電変換素子の構成及び製造方法）
　図９は、第３実施形態に係る光電変換素子の概略構成を示す断面図である。図９に示すように、光電変換素子１０３は、パッシベーション層３３０において、ｎ型非晶質半導体層４が凹部３３４内に配置され、ｐ型非晶質半導体層５が凹部内には配置されていない点で第１実施形態と異なる。 [Third Embodiment]
(Configuration and manufacturing method of photoelectric conversion element)
FIG. 9 is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element according to the third embodiment. As shown in FIG. 9, in the photoelectric conversion element 103, in the passivation layer 330, the n-type amorphous semiconductor layer 4 is disposed in the recess 334, and the p-type amorphous semiconductor layer 5 is disposed in the recess. There is no difference from the first embodiment.
　パッシベーション層３３０に形成されている凹部３３４の底面は、ｎ型非晶質半導体層４が接する第１領域３３１である。パッシベーション層３３０のうち、第１領域３３１における厚みＴ３３１は、その他の領域における厚みよりも小さい。すなわち、厚みＴ３３１は、ｐ型非晶質半導体層５が接する第２領域３３２の厚みＴ３３２よりも小さく、ｎ型非晶質半導体層４及びｐ型非晶質半導体層５が接しない第３領域３３３の厚みＴ３３３よりも小さい。 The bottom surface of the recess 334 formed in the passivation layer 330 is a first region 331 in contact with the n-type amorphous semiconductor layer 4. Of the passivation layer 330, the thickness T331 in the first region 331 is smaller than the thickness in other regions. That is, the thickness T331 is smaller than the thickness T332 of the second region 332 in contact with the p-type amorphous semiconductor layer 5, and the third region in which the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are not in contact. It is smaller than the thickness T333 of 333.
　上述したように、ｐ型非晶質半導体層５は、パッシベーション層３３０の凹部内に配置されていない。したがって、パッシベーション層３３０において、ｐ型非晶質半導体層５が接する第２領域３３２の厚みＴ３３２は、ｎ型非晶質半導体層４及びｐ型非晶質半導体層５が接しない第３領域３３３の厚みＴ３３３と実質的に等しい。 As described above, the p-type amorphous semiconductor layer 5 is not disposed in the recess of the passivation layer 330. Accordingly, in the passivation layer 330, the thickness T332 of the second region 332 in contact with the p-type amorphous semiconductor layer 5 is equal to the third region 333 in which the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are not in contact. Is substantially equal to the thickness T333.
　光電変換素子１０３は、第１実施形態に係る光電変換素子１０と同様の方法で製造することができる。ただし、光電変換素子１０３では、ｐ型非晶質半導体層５がパッシベーション層３３０の凹部内に配置されないため、ｐ型非晶質半導体層５を配置するための凹部３４ｂを形成する第６工程は不要である。すなわち、光電変換素子１０３は、実施形態１の第１～第５工程、第７工程、及び第８工程を経て製造することができる。 The photoelectric conversion element 103 can be manufactured by the same method as the photoelectric conversion element 10 according to the first embodiment. However, in the photoelectric conversion element 103, since the p-type amorphous semiconductor layer 5 is not disposed in the recess of the passivation layer 330, the sixth step of forming the recess 34b for disposing the p-type amorphous semiconductor layer 5 is performed. It is unnecessary. That is, the photoelectric conversion element 103 can be manufactured through the first to fifth steps, the seventh step, and the eighth step of Embodiment 1.
　（効果）
　以上のように、第３実施形態に係る光電変換素子１０３では、ｎ型非晶質半導体層４がパッシベーション層３３０の凹部３３４内に配置されている。この場合、パッシベーション層３３０において、ｎ型非晶質半導体層４が接する第１領域３３１の厚みＴ３３１が他の領域の厚みよりも小さくなるため、コンタクト抵抗を低減することができる。また、パッシベーション層３３０において、第１領域３３１以外の領域の厚みＴ３３２，Ｔ３３３は比較的大きいため、良好なパッシベーション性を確保することもできる。 (effect)
As described above, in the photoelectric conversion element 103 according to the third embodiment, the n-type amorphous semiconductor layer 4 is disposed in the recess 334 of the passivation layer 330. In this case, in the passivation layer 330, the thickness T331 of the first region 331 with which the n-type amorphous semiconductor layer 4 is in contact is smaller than the thickness of other regions, so that the contact resistance can be reduced. In addition, in the passivation layer 330, the thicknesses T332 and T333 of regions other than the first region 331 are relatively large, so that good passivation properties can be ensured.
　また、パッシベーション層３３０において、ｐ型非晶質半導体層５が接する第２領域３３２の厚みＴ３３２は、ｎ型非晶質半導体層４が接する第１領域３３１の厚みＴ３３１よりも大きい。このため、パッシベーション性が低下しやすいｐ側領域において、パッシベーション性の低下を抑制することができる。 Further, in the passivation layer 330, the thickness T332 of the second region 332 in contact with the p-type amorphous semiconductor layer 5 is larger than the thickness T331 of the first region 331 in contact with the n-type amorphous semiconductor layer 4. For this reason, in the p-side region where the passivation property is likely to deteriorate, it is possible to suppress the deterioration of the passivation property.
　［第４実施形態］
　（光電変換素子の構成）
　図１０は、第４実施形態に係る光電変換素子の概略構成を示す断面図である。図１０に示すように、光電変換素子１０４は、パッシベーション層３４０において、ｐ型非晶質半導体層５が凹部３４４内に配置され、ｎ型非晶質半導体層４４が凹部内には配置されていない点で第１実施形態と異なる。また、光電変換素子１０４は、ｎ型非晶質半導体層４４が分離部４４１を有する点でも第１実施形態と異なる。 [Fourth Embodiment]
(Configuration of photoelectric conversion element)
FIG. 10 is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element according to the fourth embodiment. As shown in FIG. 10, in the photoelectric conversion element 104, in the passivation layer 340, the p-type amorphous semiconductor layer 5 is disposed in the recess 344, and the n-type amorphous semiconductor layer 44 is disposed in the recess. There is no difference from the first embodiment. The photoelectric conversion element 104 is also different from the first embodiment in that the n-type amorphous semiconductor layer 44 has a separation portion 441.
　パッシベーション層３４０に形成されている凹部３４４の底面は、ｐ型非晶質半導体層５が接する第２領域３４２である。パッシベーション層３３０のうち、第２領域３４２における厚みＴ３４２は、その他の領域における厚みよりも小さい。すなわち、厚みＴ３４２は、ｎ型非晶質半導体層４４が接する第１領域３４１の厚みＴ３４１よりも小さい。 The bottom surface of the recess 344 formed in the passivation layer 340 is a second region 342 in contact with the p-type amorphous semiconductor layer 5. In the passivation layer 330, the thickness T342 in the second region 342 is smaller than the thickness in other regions. That is, the thickness T342 is smaller than the thickness T341 of the first region 341 in contact with the n-type amorphous semiconductor layer 44.
　ｎ型非晶質半導体層４４は、半導体基板１の面内方向において、分離部４４１によって複数部分に分離される。すなわち、分離部４４１は、ｎ型非晶質半導体層４４を厚み方向に貫通し、且つ半導体基板１の面内方向に分断する。分離部４４１内には、ｐ型非晶質半導体層５が配置されている。 The n-type amorphous semiconductor layer 44 is separated into a plurality of parts by the separation part 441 in the in-plane direction of the semiconductor substrate 1. That is, the separation part 441 penetrates the n-type amorphous semiconductor layer 44 in the thickness direction and divides it in the in-plane direction of the semiconductor substrate 1. A p-type amorphous semiconductor layer 5 is disposed in the separation portion 441.
　（光電変換素子の製造方法）
　以下、光電変換素子１０４の製造方法について説明する。 (Manufacturing method of photoelectric conversion element)
Hereinafter, a method for manufacturing the photoelectric conversion element 104 will be described.
　図１１Ａに示すように、まず、第１実施形態の第１及び第２工程と同様にして、半導体基板１の受光面にテクスチャ構造を形成し、反射防止膜２を形成する。続いて、第１実施形態の第３工程と同様にして、半導体基板１の裏面にｉ型非晶質半導体層３０４を形成する。 As shown in FIG. 11A, first, in the same manner as in the first and second steps of the first embodiment, a texture structure is formed on the light receiving surface of the semiconductor substrate 1, and the antireflection film 2 is formed. Subsequently, an i-type amorphous semiconductor layer 304 is formed on the back surface of the semiconductor substrate 1 in the same manner as in the third step of the first embodiment.
　次に、図１１Ｂに示すように、ｉ型非晶質半導体層３０４上にｎ型非晶質半導体膜５００を形成する。 Next, as shown in FIG. 11B, an n-type amorphous semiconductor film 500 is formed on the i-type amorphous semiconductor layer 304.
　ｎ型非晶質半導体膜５００は、第１実施形態の第５工程と同様にして、プラズマＣＶＤ法により形成することができる。ただし、第４実施形態では、ｉ型非晶質半導体層３０４の表面全体にｎ型非晶質半導体膜５００を形成する。このため、第１実施形態の第５工程で使用したシャドーマスク２００をｉ型非晶質半導体層３０４上に配置せず、プラズマＣＶＤ法によるｎ型の非晶質シリコンの堆積を行う。 The n-type amorphous semiconductor film 500 can be formed by a plasma CVD method in the same manner as the fifth step of the first embodiment. However, in the fourth embodiment, the n-type amorphous semiconductor film 500 is formed on the entire surface of the i-type amorphous semiconductor layer 304. For this reason, the shadow mask 200 used in the fifth step of the first embodiment is not disposed on the i-type amorphous semiconductor layer 304, and n-type amorphous silicon is deposited by plasma CVD.
　次に、ｎ型非晶質半導体膜５００に分離部４４１を形成するとともに、ｉ型非晶質半導体層３０４に凹部３４４を形成する。 Next, a separation portion 441 is formed in the n-type amorphous semiconductor film 500 and a recess 344 is formed in the i-type amorphous semiconductor layer 304.
　具体的には、図１１Ｃに示すように、ｎ型非晶質半導体膜５００及びｉ型非晶質半導体層３０４に対し、例えば、シャドーマスク２０５の開口２０５ａを介して水素プラズマを用いたエッチングを行う。エッチングは、第１実施形態の第４工程と同様の条件で行うことができる。エッチングは、ｎ型非晶質半導体膜５００を貫通し、且つｉ型非晶質半導体層３０４と半導体基板１の界面まで到達しない深さで行われる。これにより、凹部３４４を有するパッシベーション層３４０、及び分離部４４１によって半導体基板１の面内方向に分離されたｎ型非晶質半導体層４４が完成する。 Specifically, as shown in FIG. 11C, the n-type amorphous semiconductor film 500 and the i-type amorphous semiconductor layer 304 are etched using, for example, hydrogen plasma through the opening 205a of the shadow mask 205. Do. Etching can be performed under the same conditions as in the fourth step of the first embodiment. The etching is performed at a depth that penetrates the n-type amorphous semiconductor film 500 and does not reach the interface between the i-type amorphous semiconductor layer 304 and the semiconductor substrate 1. As a result, the passivation layer 340 having the recess 344 and the n-type amorphous semiconductor layer 44 separated in the in-plane direction of the semiconductor substrate 1 by the separation portion 441 are completed.
　次に、パッシベーション層３４０の凹部３４４及びｎ型非晶質半導体層４４の分離部４４１内にｐ型非晶質半導体層５を形成する。 Next, the p-type amorphous semiconductor layer 5 is formed in the recess 344 of the passivation layer 340 and the separation part 441 of the n-type amorphous semiconductor layer 44.
　具体的には、図１１Ｄに示すように、シャドーマスク２０５をｎ型非晶質半導体層４４上に配置したまま、開口２０５ａを介し、プラズマＣＶＤ法等によって、ｐ型非晶質半導体層５を形成する。このときの成膜条件は、第１実施形態の第７工程と同様のものとすることができる。これにより、パッシベーション層３４０の凹部３４４及びｎ型非晶質半導体層４４の分離部４４１内にｐ型非晶質半導体層５が形成される。 Specifically, as shown in FIG. 11D, the p-type amorphous semiconductor layer 5 is formed by plasma CVD or the like through the opening 205a while the shadow mask 205 is disposed on the n-type amorphous semiconductor layer 44. Form. The film formation conditions at this time can be the same as those in the seventh step of the first embodiment. As a result, the p-type amorphous semiconductor layer 5 is formed in the recess 344 of the passivation layer 340 and the separation portion 441 of the n-type amorphous semiconductor layer 44.
　その後、図１１Ｅに示すように、第１実施形態の第８工程と同様にして、ｎ型非晶質半導体層４及びｐ型非晶質半導体層５上にそれぞれ電極６，７を形成する。 Thereafter, as shown in FIG. 11E, electrodes 6 and 7 are formed on the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, respectively, in the same manner as in the eighth step of the first embodiment.
　（効果）
　以上のように、第４実施形態に係る光電変換素子１０４では、ｐ型非晶質半導体層５がパッシベーション層３４０の凹部３４４内に配置されている。この場合、パッシベーション層３４０において、ｐ型非晶質半導体層５が接する第２領域３４２の厚みＴ３４２が他の領域よりも小さくなるため、コンタクト抵抗を低減することができる。また、パッシベーション層３４０において、ｎ型非晶質半導体層４４が接する第１領域３４１の厚みＴ３４１は比較的大きいため、良好なパッシベーション性を確保することもできる。 (effect)
As described above, in the photoelectric conversion element 104 according to the fourth embodiment, the p-type amorphous semiconductor layer 5 is disposed in the recess 344 of the passivation layer 340. In this case, in the passivation layer 340, the thickness T342 of the second region 342 in contact with the p-type amorphous semiconductor layer 5 is smaller than other regions, so that the contact resistance can be reduced. In addition, since the thickness T341 of the first region 341 in contact with the n-type amorphous semiconductor layer 44 in the passivation layer 340 is relatively large, good passivation can be ensured.
　［第５実施形態］
　（光電変換素子の構成及び製造方法）
　図１２は、第５実施形態に係る光電変換素子の概略構成を示す断面図である。図１２に示すように、光電変換素子１０５は、パッシベーション層３５０において、第１領域３５１の厚みＴ３５１と、第２領域３５２の厚みＴ３５２とが等しい点で第１実施形態と異なる。 [Fifth Embodiment]
(Configuration and manufacturing method of photoelectric conversion element)
FIG. 12 is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element according to the fifth embodiment. As shown in FIG. 12, the photoelectric conversion element 105 is different from the first embodiment in that the thickness T351 of the first region 351 and the thickness T352 of the second region 352 are equal in the passivation layer 350.
　パッシベーション層３５０は、凹部３５４ａ，３５４ｂを有する。凹部３５４ａ内には、ｎ型非晶質半導体層４が配置される。凹部３５４ｂ内には、ｐ型非晶質半導体層５が配置される。凹部３５４ａ，３５４ｂの底面は、それぞれ、ｎ型非晶質半導体層４が接する第１領域３５１及びｐ型非晶質半導体層５が接する第２領域３５２である。 The passivation layer 350 has recesses 354a and 354b. The n-type amorphous semiconductor layer 4 is disposed in the recess 354a. The p-type amorphous semiconductor layer 5 is disposed in the recess 354b. The bottom surfaces of the recesses 354a and 354b are a first region 351 in contact with the n-type amorphous semiconductor layer 4 and a second region 352 in contact with the p-type amorphous semiconductor layer 5, respectively.
　凹部３５４ａ，３５４ｂの深さは実質的に等しい。すなわち、パッシベーション層３５０の厚み方向において、凹部３５４ａの底面の位置は、凹部３５４ｂの底面の位置と実質的に等しい。したがって、パッシベーション層３５０において、第１領域３５１の厚みＴ３５１と、第２領域３５２の厚みＴ３５２とは実質的に等しい。第１領域３５１の厚みＴ３５１及び第２領域３５２の厚みＴ３５２は、ｎ型非晶質半導体層４及びｐ型非晶質半導体層５が接しない第３領域３５３の厚みＴ３５３よりも小さい The depths of the recesses 354a and 354b are substantially equal. That is, in the thickness direction of the passivation layer 350, the position of the bottom surface of the recess 354a is substantially equal to the position of the bottom surface of the recess 354b. Therefore, in the passivation layer 350, the thickness T351 of the first region 351 and the thickness T352 of the second region 352 are substantially equal. The thickness T351 of the first region 351 and the thickness T352 of the second region 352 are smaller than the thickness T353 of the third region 353 where the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 do not contact.
　光電変換素子１０５は、第１実施形態と同様の方法で製造することができる。なお、第１実施形態では、凹部３４ａ，３４ｂの深さが互いに異なるため、シャドーマスクの開口幅や、エッチング時間等の処理条件を変更して凹部３４ａ，３４ｂを形成する必要がある。一方、第５実施形態では、凹部３５４ａ，３５４ｂの深さが同じであるため、シャドーマスクの開口幅及びその他の処理条件を同一にして、凹部３５４ａ，３５４ｂの形成を行うことができる。 The photoelectric conversion element 105 can be manufactured by the same method as in the first embodiment. In the first embodiment, since the depths of the recesses 34a and 34b are different from each other, it is necessary to form the recesses 34a and 34b by changing the processing conditions such as the opening width of the shadow mask and the etching time. On the other hand, in the fifth embodiment, since the depths of the recesses 354a and 354b are the same, the recesses 354a and 354b can be formed with the same opening width of the shadow mask and other processing conditions.
　（効果）
　以上のように、第５実施形態に係る光電変換素子１０５も、第１実施形態と同様、パッシベーション層３３０において、ｎ型非晶質半導体層４が接する第１領域３５１の厚みＴ３５１、及びｐ型非晶質半導体層５が接する第２領域３５２の厚みＴ３５２の双方が、ｎ型非晶質半導体層４及びｐ型非晶質半導体層５が接しない第３領域３５３の厚みＴ３５３よりも小さい。このため、良好なパッシベーション性を確保し、且つコンタクト抵抗を低減することができる。 (effect)
As described above, the photoelectric conversion element 105 according to the fifth embodiment also has the thickness T351 of the first region 351 in contact with the n-type amorphous semiconductor layer 4 and the p-type in the passivation layer 330, as in the first embodiment. Both the thickness T352 of the second region 352 that the amorphous semiconductor layer 5 is in contact with are smaller than the thickness T353 of the third region 353 that the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are not in contact with. For this reason, favorable passivation property can be ensured and contact resistance can be reduced.
　［第６実施形態］
　本実施形態では、上述した第１～第５実施形態の少なくとも１つの光電変換素子を備えた光電変換モジュールについて説明する。図１３は、第６実施形態に係る光電変換モジュールの構成を示す概略図である。光電変換モジュール１０００は、複数の光電変換素子１００１と、カバー１００２と、出力端子１００３，１００４とを備える。 [Sixth Embodiment]
In the present embodiment, a photoelectric conversion module including at least one photoelectric conversion element of the first to fifth embodiments described above will be described. FIG. 13 is a schematic diagram illustrating a configuration of a photoelectric conversion module according to the sixth embodiment. The photoelectric conversion module 1000 includes a plurality of photoelectric conversion elements 1001, a cover 1002, and output terminals 1003 and 1004.
　複数の光電変換素子１００１の少なくとも１つは、第１～第５実施形態に係る光電変換素子１０，１０２～１０５のいずれかである。複数の光電変換素子１００１は、例えば、アレイ状に配置され、直列に接続されている。直列に接続する代わりに、並列接続、又は、直列と並列を組み合わせた接続を行ってもよい。 At least one of the plurality of photoelectric conversion elements 1001 is any one of the photoelectric conversion elements 10 and 102 to 105 according to the first to fifth embodiments. The plurality of photoelectric conversion elements 1001 are, for example, arranged in an array and connected in series. Instead of connecting in series, parallel connection or a combination of series and parallel may be performed.
　カバー１００２は、耐候性のカバーからなり、複数の光電変換素子１００１を覆う。カバー１００２は、例えば、光電変換素子１００１の受光面側に設けられた透明基材（例えばガラス等）と、光電変換素子１００１の受光面側とは反対の裏面側に設けられた裏面基材（例えば、ガラス、樹脂シート等）と、前記透明基材と前記樹脂基材との間の隙間を埋める封止材（例えばＥＶＡ等）とを含む。 The cover 1002 is made of a weather resistant cover and covers the plurality of photoelectric conversion elements 1001. The cover 1002 includes, for example, a transparent base material (for example, glass) provided on the light receiving surface side of the photoelectric conversion element 1001 and a back surface base material (on the reverse side opposite to the light receiving surface side of the photoelectric conversion element 1001). For example, glass, a resin sheet, etc.) and the sealing material (for example, EVA etc.) which fills the clearance gap between the said transparent base material and the said resin base material are included.
　出力端子１００３は、直列に接続された複数の光電変換素子１００１の一方端に配置される配線シート付き光電変換素子１００１に接続される。 The output terminal 1003 is connected to a photoelectric conversion element 1001 with a wiring sheet disposed at one end of a plurality of photoelectric conversion elements 1001 connected in series.
　出力端子１００４は、直列に接続された複数の光電変換素子１００１の他方端に配置される光電変換素子１００１に接続される。 The output terminal 1004 is connected to the photoelectric conversion element 1001 disposed at the other end of the plurality of photoelectric conversion elements 1001 connected in series.
　上述したように、第１～第５実施形態に係る光電変換素子１０、１０２～１０５は、開放電圧（Ｖｏｃ）を高く、素子特性が向上している。したがって、光電変換モジュール１０００の性能を向上させることができる。 As described above, the photoelectric conversion elements 10 and 102 to 105 according to the first to fifth embodiments have a high open circuit voltage (Voc) and improved element characteristics. Therefore, the performance of the photoelectric conversion module 1000 can be improved.
　なお、本実施形態による光電変換モジュールは、図１３に示す構成に限らず、第１～第５実施形態に係る光電変換素子１０、１０２～１０５のいずれかを用いる限り、どのような構成であってもよい。 Note that the photoelectric conversion module according to the present embodiment is not limited to the configuration shown in FIG. 13, but any configuration as long as any one of the photoelectric conversion elements 10 and 102 to 105 according to the first to fifth embodiments is used. May be.
　［第７実施形態］
　図１４は、第７実施形態に係る太陽光発電システムの構成を示す概略図である。太陽光発電システム１１００は、光電変換モジュールアレイ１１０１と、接続箱１１０２と、パワーコンディショナー１１０３と、分電盤１１０４と、電力メーター１１０５とを備える。太陽光発電システム１１００には、「ホーム・エネルギー・マネジメント・システム（ＨＥＭＳ：Ｈｏｍｅ　Ｅｎｅｒｇｙ　Ｍａｎａｇｅｍｅｎｔ　Ｓｙｓｔｅｍ）」、「ビルディング・エネルギー・マネジメント・システム（ＢＥＭＳ：Ｂｕｉｌｄｉｎｇ　Ｅｎｅｒｇｙ　Ｍａｎａｇｅｍｅｎｔ　Ｓｙｓｔｅｍ）」等の機能を付加することができる。これにより、太陽光発電システム１１００の発電量の監視、太陽光発電システム１１００に接続される各電気機器類の消費電力量の監視・制御等を行うことができ、エネルギー消費量を削減することができる。 [Seventh Embodiment]
FIG. 14 is a schematic diagram illustrating a configuration of a photovoltaic power generation system according to the seventh embodiment. The photovoltaic power generation system 1100 includes a photoelectric conversion module array 1101, a connection box 1102, a power conditioner 1103, a distribution board 1104, and a power meter 1105. Functions such as “Home Energy Management System (HEMS)” and “Building Energy Management System (BEMS)” are added to the photovoltaic power generation system 1100. Can do. Thereby, the power generation amount of the solar power generation system 1100 can be monitored, the power consumption amount of each electrical device connected to the solar power generation system 1100 can be monitored and controlled, and the energy consumption can be reduced. it can.
　接続箱１１０２は、光電変換モジュールアレイ１１０１に接続される。パワーコンディショナー１１０３は、接続箱１１０２に接続される。分電盤１１０４は、パワーコンディショナー１１０３及び電気機器１１１０に接続される。電力メーター１１０５は、分電盤１１０４及び系統連携に接続される。 The connection box 1102 is connected to the photoelectric conversion module array 1101. The power conditioner 1103 is connected to the connection box 1102. Distribution board 1104 is connected to power conditioner 1103 and electrical equipment 1110. The power meter 1105 is connected to the distribution board 1104 and system linkage.
　光電変換モジュールアレイ１１０１は、太陽光を電気に変換して直流電力を発電し、その発電した直流電力を接続箱１１０２に供給する。 The photoelectric conversion module array 1101 converts sunlight into electricity to generate DC power, and supplies the generated DC power to the connection box 1102.
　接続箱１１０２は、光電変換モジュールアレイ１１０１が発電した直流電力を受け、その受けた直流電力をパワーコンディショナー１１０３へ供給する。 The connection box 1102 receives the DC power generated by the photoelectric conversion module array 1101 and supplies the received DC power to the power conditioner 1103.
　パワーコンディショナー１１０３は、接続箱１１０２から受けた直流電力を交流電力に変換し、その変換した交流電力を分電盤１１０４に供給する。 The power conditioner 1103 converts the DC power received from the connection box 1102 into AC power, and supplies the converted AC power to the distribution board 1104.
　分電盤１１０４は、パワーコンディショナー１１０３から受けた交流電力及び／又は電力メーター１１０５を介して受けた商用電力を電気機器１１１０へ供給する。また、分電盤１１０４は、パワーコンディショナー１１０３から受けた交流電力が電気機器１１１０の消費電力よりも多いとき、余った交流電力を、電力メーター１１０５を介して、系統連携へ供給する。 Distribution board 1104 supplies AC power received from power conditioner 1103 and / or commercial power received via power meter 1105 to electrical equipment 1110. Further, when the AC power received from the power conditioner 1103 is larger than the power consumption of the electrical equipment 1110, the distribution board 1104 supplies the surplus AC power to the system linkage via the power meter 1105.
　電力メーター１１０５は、系統連携から分電盤１１０４へ向かう方向の電力を計測するとともに、分電盤１１０４から系統連携へ向かう方向の電力を計測する。 The power meter 1105 measures the power in the direction from the grid connection to the distribution board 1104 and measures the power in the direction from the distribution board 1104 to the grid cooperation.
　図１５は、図１４に示す光電変換モジュールアレイ１１０１の構成を示す概略図である。図１５を参照して、光電変換モジュールアレイ１１０１は、複数の光電変換モジュール１１２０と、出力端子１１２１，１１２２とを含む。 FIG. 15 is a schematic diagram showing the configuration of the photoelectric conversion module array 1101 shown in FIG. Referring to FIG. 15, photoelectric conversion module array 1101 includes a plurality of photoelectric conversion modules 1120 and output terminals 1121 and 1122.
　複数の光電変換モジュール１１２０は、アレイ状に配列され、直列に接続される。複数の光電変換モジュール１１２０の各々は、図１３に示す光電変換モジュール１０００からなる。 The plurality of photoelectric conversion modules 1120 are arranged in an array and connected in series. Each of the plurality of photoelectric conversion modules 1120 includes a photoelectric conversion module 1000 shown in FIG.
　出力端子１１２１は、直列に接続された複数の光電変換モジュール１１２０の一方端に位置する光電変換モジュール１１２０に接続される。 The output terminal 1121 is connected to a photoelectric conversion module 1120 located at one end of a plurality of photoelectric conversion modules 1120 connected in series.
　出力端子１１２２は、直列に接続された複数の光電変換モジュール１１２０の他方端に位置する光電変換モジュール１１２０に接続される。 The output terminal 1122 is connected to the photoelectric conversion module 1120 located at the other end of the plurality of photoelectric conversion modules 1120 connected in series.
　太陽光発電システム１１００における動作を説明する。光電変換モジュールアレイ１１０１は、太陽光を電気に変換して直流電力を発電し、その発電した直流電力を、接続箱１１０２を介してパワーコンディショナー１１０３へ供給する。 Operation in the solar power generation system 1100 will be described. The photoelectric conversion module array 1101 generates sunlight by converting sunlight into electricity, and supplies the generated DC power to the power conditioner 1103 via the connection box 1102.
　パワーコンディショナー１１０３は、光電変換モジュールアレイ１１０１から受けた直流電力を交流電力に変換し、その変換した交流電力を分電盤１１０４へ供給する。 The power conditioner 1103 converts the DC power received from the photoelectric conversion module array 1101 into AC power, and supplies the converted AC power to the distribution board 1104.
　分電盤１１０４は、パワーコンディショナー１１０３から受けた交流電力が電気機器１１１０の消費電力以上であるとき、パワーコンディショナー１１０３から受けた交流電力を電気機器１１１０に供給する。そして、分電盤１１０４は、余った交流電力を、電力メーター１１０５を介して系統連携へ供給する。 The distribution board 1104 supplies the AC power received from the power conditioner 1103 to the electrical device 1110 when the AC power received from the power conditioner 1103 is greater than or equal to the power consumption of the electrical device 1110. Then, the distribution board 1104 supplies surplus AC power to the system linkage via the power meter 1105.
　また、分電盤１１０４は、パワーコンディショナー１１０３から受けた交流電力が電気機器１１１０の消費電力よりも少ないとき、系統連携から受けた交流電力及びパワーコンディショナー１１０３から受けた交流電力を電気機器１１１０へ供給する。 Distribution board 1104 supplies AC power received from system cooperation and AC power received from power conditioner 1103 to electric device 1110 when the AC power received from power conditioner 1103 is less than the power consumption of electric device 1110. To do.
　太陽光発電システム１１００は、上述したように、素子特性が向上している第１～第５実施形態に係る光電変換素子のいずれかを備えている。したがって、太陽光発電システム１１００の性能を向上させることができる。 As described above, the photovoltaic power generation system 1100 includes any of the photoelectric conversion elements according to the first to fifth embodiments having improved element characteristics. Therefore, the performance of the photovoltaic power generation system 1100 can be improved.
　なお、本実施形態による太陽光発電システムは、図１４及び図１５に示す構成に限らず、第１～第５実施形態に係る光電変換素子のいずれかを用いる限り、どのような構成であってもよい。また、図１６に示すようにパワーコンディショナー１１０３には蓄電池１１０６が接続されていてもよい。この場合、日照量の変動による出力変動を抑制することができるとともに、日照のない時間帯であっても蓄電池１１０６に蓄電された電力を供給することができる。蓄電池１１０６はパワーコンディショナー１１０３に内蔵されていてもよい。 Note that the photovoltaic power generation system according to the present embodiment is not limited to the configuration shown in FIGS. 14 and 15, and may have any configuration as long as any of the photoelectric conversion elements according to the first to fifth embodiments is used. Also good. In addition, as shown in FIG. 16, a storage battery 1106 may be connected to the power conditioner 1103. In this case, output fluctuation due to fluctuations in the amount of sunlight can be suppressed, and power stored in the storage battery 1106 can be supplied even in a time zone without sunlight. The storage battery 1106 may be built in the power conditioner 1103.
　［第８実施形態］
　図１７は、第８実施形態に係る太陽光発電システムの構成を示す概略図である。太陽光発電システム１２００は、サブシステム１２０１～１２０ｎ（ｎは２以上の整数）と、パワーコンディショナー１２１１～１２１ｎと、変圧器１２２１とを備える。太陽光発電システム１２００は、図１４、１８Ｂに示す太陽光発電システム１１００よりも規模が大きい太陽光発電システムである。 [Eighth Embodiment]
FIG. 17 is a schematic diagram illustrating a configuration of a photovoltaic power generation system according to the eighth embodiment. The photovoltaic power generation system 1200 includes subsystems 1201 to 120n (n is an integer of 2 or more), power conditioners 1211 to 121n, and a transformer 1221. The photovoltaic power generation system 1200 is a photovoltaic power generation system having a larger scale than the photovoltaic power generation system 1100 shown in FIGS.
　パワーコンディショナー１２１１～１２１ｎは、それぞれ、サブシステム１２０１～１２０ｎに接続される。 The power conditioners 1211 to 121n are connected to the subsystems 1201 to 120n, respectively.
　変圧器１２２１は、パワーコンディショナー１２１１～１２１ｎ及び系統連携に接続される。 The transformer 1221 is connected to the power conditioners 1211 to 121n and the system linkage.
　サブシステム１２０１～１２０ｎの各々は、モジュールシステム１２３１～１２３ｊ（ｊは２以上の整数）からなる。 Each of the subsystems 1201 to 120n includes module systems 1231 to 123j (j is an integer of 2 or more).
　モジュールシステム１２３１～１２３ｊの各々は、光電変換モジュールアレイ１３０１～１３０ｉ（ｉは２以上の整数）と、接続箱１３１１～１３１ｉと、集電箱１３２１とを含む。 Each of the module systems 1231 to 123j includes photoelectric conversion module arrays 1301 to 130i (i is an integer of 2 or more), connection boxes 1311 to 131i, and a current collection box 1321.
　光電変換モジュールアレイ１３０１～１３０ｉの各々は、図１８に示す光電変換モジュールアレイ１１０１と同じ構成からなる。 Each of the photoelectric conversion module arrays 1301 to 130i has the same configuration as the photoelectric conversion module array 1101 shown in FIG.
　接続箱１３１１～１３１ｉは、それぞれ、光電変換モジュールアレイ１３０１～１３０ｉに接続される。 The connection boxes 1311 to 131i are connected to the photoelectric conversion module arrays 1301 to 130i, respectively.
　集電箱１３２１は、接続箱１３１１～１３１ｉに接続される。また、サブシステム１２０１のｊ個の集電箱１３２１は、パワーコンディショナー１２１１に接続される。サブシステム１２０２のｊ個の集電箱１３２１は、パワーコンディショナー１２１２に接続される。以下、同様にして、サブシステム１２０ｎのｊ個の集電箱１３２１は、パワーコンディショナー１２１ｎに接続される。 The current collection box 1321 is connected to the connection boxes 1311 to 131i. Also, j current collection boxes 1321 of the subsystem 1201 are connected to the power conditioner 1211. The j current collection boxes 1321 of the subsystem 1202 are connected to the power conditioner 1212. Hereinafter, similarly, j current collection boxes 1321 of the subsystem 120n are connected to the power conditioner 121n.
　モジュールシステム１２３１のｉ個の光電変換モジュールアレイ１３０１～１３０ｉは、太陽光を電気に変換して直流電力を発電し、その発電した直流電力を、それぞれ接続箱１３１１～１３１ｉを介して集電箱１３２１へ供給する。モジュールシステム１２３２のｉ個の光電変換モジュールアレイ１３０１～１３０ｉは、太陽光を電気に変換して直流電力を発電し、その発電した直流電力をそれぞれ、接続箱１３１１～１３１ｉを介して集電箱１３２１へ供給する。以下、同様にして、モジュールシステム１２３ｊのｉ個の光電変換モジュールアレイ１３０１～１３０ｉは、太陽光を電気に変換して直流電力を発電し、その発電した直流電力をそれぞれ、接続箱１３１１～１３１ｉを介して集電箱１３２１へ供給する。 The i photoelectric conversion module arrays 1301 to 130i of the module system 1231 generate sunlight by converting sunlight into electricity, and the generated DC power is collected through the connection boxes 1311 to 131i, respectively. To supply. The i photoelectric conversion module arrays 1301 to 130i of the module system 1232 generate sunlight by converting sunlight into electricity, and the generated DC power is collected through the connection boxes 1311 to 131i, respectively. To supply. Similarly, the i photoelectric conversion module arrays 1301 to 130i of the module system 123j convert sunlight into electricity to generate DC power, and the generated DC power is connected to the connection boxes 1311 to 131i, respectively. To the current collection box 1321.
　そして、サブシステム１２０１のｊ個の集電箱１３２１は、直流電力をパワーコンディショナー１２１１へ供給する。 And the j current collection boxes 1321 of the subsystem 1201 supply DC power to the power conditioner 1211.
　サブシステム１２０２のｊ個の集電箱１３２１は、同様にして直流電力をパワーコンディショナー１２１２へ供給する。 The j current collection boxes 1321 of the subsystem 1202 supply DC power to the power conditioner 1212 in the same manner.
　以下、同様にして、サブシステム１２０ｎのｊ個の集電箱１３２１は、直流電力をパワーコンディショナー１２１ｎへ供給する。 Hereinafter, similarly, the j current collecting boxes 1321 of the subsystem 120n supply DC power to the power conditioner 121n.
　パワーコンディショナー１２１１～１２１ｎは、それぞれ、サブシステム１２０１～１２０ｎから受けた直流電力を交流電力に変換し、その変換した交流電力を変圧器１２２１へ供給する。 The power conditioners 1211 to 121n convert the DC power received from the subsystems 1201 to 120n into AC power, and supply the converted AC power to the transformer 1221.
　変圧器１２２１は、パワーコンディショナー１２１１～１２１ｎから交流電力を受け、その受けた交流電力の電圧レベルを変換して系統連携へ供給する。 The transformer 1221 receives AC power from the power conditioners 1211 to 121n, converts the voltage level of the received AC power, and supplies it to the system linkage.
　太陽光発電システム１２００は、上述したように、素子特性が向上している第１～第５実施形態に係る光電変換素子のいずれかを備えている。したがって、太陽光発電システム１２００の性能を向上させることができる。 As described above, the photovoltaic power generation system 1200 includes any of the photoelectric conversion elements according to the first to fifth embodiments having improved element characteristics. Therefore, the performance of the photovoltaic power generation system 1200 can be improved.
　なお、第８実施形態に係る太陽光発電システムは、図１７に示す構成に限らず、第１～第５実施形態に係る光電変換素子のいずれかを用いる限り、どのような構成であってもよい。 Note that the photovoltaic power generation system according to the eighth embodiment is not limited to the configuration shown in FIG. 17, and any configuration can be used as long as any of the photoelectric conversion elements according to the first to fifth embodiments is used. Good.
　また、図１８に示すようにパワーコンディショナー１２１１～１２１ｎに蓄電池１２１３が接続されていてもよいし、蓄電池１２１３がパワーコンディショナー１２１１～１２１ｎに内蔵されていてもよい。この場合、パワーコンディショナー１２１１～１２１ｎは、集電箱１３２１から受けた直流電力の一部又は全部を適切に電力変換して、蓄電池１２１３に蓄電することができる。蓄電池１２１３に蓄電された電力は、サブシステム１２０１～１２０ｎの発電量に応じて適宜パワーコンディショナー１２１１～１２１ｎ側に供給され、適切に電力変換されて変圧器１２２１へ供給される。 Further, as shown in FIG. 18, a storage battery 1213 may be connected to the power conditioners 1211 to 121n, or the storage battery 1213 may be built in the power conditioners 1211 to 121n. In this case, the power conditioners 1211 to 121n can appropriately convert part or all of the DC power received from the current collection box 1321 and store it in the storage battery 1213. The electric power stored in the storage battery 1213 is appropriately supplied to the power conditioners 1211 to 121n according to the power generation amount of the subsystems 1201 to 120n, and is appropriately converted into electric power and supplied to the transformer 1221.
　［変形例］
　以上、実施形態について説明したが、本開示は上記実施形態に限定されるものではなく、その趣旨を逸脱しない限りにおいて種々の変更が可能である。 [Modification]
Although the embodiments have been described above, the present disclosure is not limited to the above-described embodiments, and various modifications can be made without departing from the gist thereof.
　上記第１～第５実施形態では、半導体基板の受光面にのみテクスチャ構造が形成される例を説明したが、半導体基板の裏面にもテクスチャ構造を形成することができる。この場合、ｎ型非晶質半導体層及びｐ型非晶質半導体層と各電極との密着性が向上し、結果として、光電変換素子の歩留まり及び信頼性を向上させることができる。また、半導体基板の裏面が平坦な場合と比較して、ｎ型非晶質半導体層及びｐ型非晶質半導体層と各電極との接触面積が大きくなるため、接触抵抗を低減することもできる。 In the first to fifth embodiments, the texture structure is formed only on the light receiving surface of the semiconductor substrate. However, the texture structure can be formed on the back surface of the semiconductor substrate. In this case, the adhesion between the n-type amorphous semiconductor layer and the p-type amorphous semiconductor layer and each electrode is improved, and as a result, the yield and reliability of the photoelectric conversion element can be improved. In addition, since the contact area between the n-type amorphous semiconductor layer and the p-type amorphous semiconductor layer and each electrode is larger than when the back surface of the semiconductor substrate is flat, the contact resistance can also be reduced. .
　上記第１～第５実施形態では、半導体基板がｎ型単結晶シリコン基板である例を説明したが、半導体基板は、ｐ型のシリコン基板であってもよい。 In the first to fifth embodiments, the example in which the semiconductor substrate is an n-type single crystal silicon substrate has been described. However, the semiconductor substrate may be a p-type silicon substrate.
　上記第１～第５実施形態では、半導体基板の受光面に反射防止膜が形成される例を説明したが、半導体基板の受光面には反射防止膜が設けられていなくてもよい。また、半導体基板の受光面には、反射防止膜に代えて、高濃度のｎ型ドーパントが拡散されたｎ＋層が形成されていてもよい。あるいは、半導体基板の受光面と反射防止膜との間に、高濃度のｎ型ドーパントが拡散されたｎ＋層が形成されていてもよい。 In the first to fifth embodiments, the example in which the antireflection film is formed on the light receiving surface of the semiconductor substrate has been described, but the antireflection film may not be provided on the light receiving surface of the semiconductor substrate. In addition, an n + layer in which a high concentration n-type dopant is diffused may be formed on the light receiving surface of the semiconductor substrate instead of the antireflection film. Alternatively, an n + layer in which a high concentration n-type dopant is diffused may be formed between the light receiving surface of the semiconductor substrate and the antireflection film.
　上記第１～第５実施形態では、プラズマＣＶＤ法を用いて、各非晶質半導体層を形成する例を説明したが、プラズマＣＶＤ法に代えて、ＣａｔＣＶＤ（Ｃａｔａｌｙｔｉｃ　Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法を用いることもできる。ＣａｔＣＶＤ法を用いる場合、例えば、半導体基板の温度を１００～３００℃、成膜圧力を１０～５００Ｐａ、熱触媒体としてタングステンを使用する際には熱触媒体の温度を１５００～２０００℃、ＲＦパワー密度を０．０１～１Ｗ／ｃｍ２として成膜を行ってもよい。このようにすることで、品質の高い非晶質半導体層及び分離部を比較的低温且つ短時間で形成することができる。 In the first to fifth embodiments, the example in which each amorphous semiconductor layer is formed using the plasma CVD method has been described. However, instead of the plasma CVD method, a CatCVD (Catalytic Chemical Vapor Deposition) method is used. You can also. When using the CatCVD method, for example, the temperature of the semiconductor substrate is 100 to 300 ° C., the deposition pressure is 10 to 500 Pa, and when using tungsten as the thermal catalyst, the temperature of the thermal catalyst is 1500 to 2000 ° C., RF power The film may be formed at a density of 0.01 to 1 W / cm 2 . By doing so, a high-quality amorphous semiconductor layer and a separation portion can be formed at a relatively low temperature and in a short time.

Claims (5)

  1. 　半導体基板と、
    　前記半導体基板の一方面上に形成され、表面に少なくとも１つの凹部を有しており、真性非晶質半導体からなるパッシベーション層と、
    　前記パッシベーション層上に形成され、第１導電型を有する第１非晶質半導体層と、
    　前記パッシベーション層上に形成され、前記第１導電型と反対の第２導電型を有する第２非晶質半導体層と、
    を備え、
    　前記第１非晶質半導体層及び前記第２非晶質半導体層の少なくとも一方は、前記凹部内に配置されている、光電変換素子。     A semiconductor substrate;
    A passivation layer formed on one surface of the semiconductor substrate, having at least one recess on the surface, and made of an intrinsic amorphous semiconductor;
    A first amorphous semiconductor layer formed on the passivation layer and having a first conductivity type;
    A second amorphous semiconductor layer formed on the passivation layer and having a second conductivity type opposite to the first conductivity type;
    With
    At least one of the first amorphous semiconductor layer and the second amorphous semiconductor layer is a photoelectric conversion element disposed in the recess.
  2. 　請求項１に記載の光電変換素子であって、
    　前記第１非晶質半導体層及び前記第２非晶質半導体層は、いずれも前記凹部内に配置されている、光電変換素子。     The photoelectric conversion device according to claim 1,
    The first amorphous semiconductor layer and the second amorphous semiconductor layer are both photoelectric conversion elements arranged in the recess.
  3. 　請求項１又は２に記載の光電変換素子であって、
    　前記パッシベーション層は、前記第１非晶質半導体層が接する領域における厚みと、前記第２非晶質半導体層が接する領域における厚みとが異なる、光電変換素子。     The photoelectric conversion element according to claim 1 or 2,
    The passivation layer is a photoelectric conversion element in which a thickness in a region in contact with the first amorphous semiconductor layer is different from a thickness in a region in contact with the second amorphous semiconductor layer.
  4. 　請求項３に記載の光電変換素子であって、
    　前記第１非晶質半導体層は、ｎ型の導電型を有し、
    　前記第２非晶質半導体層は、ｐ型の導電型を有しており、
    　前記パッシベーション層において、前記第２非晶質半導体層が接する領域における厚みは、前記第１非晶質半導体層が接する領域における厚みよりも大きい、光電変換素子。     The photoelectric conversion device according to claim 3,
    The first amorphous semiconductor layer has an n-type conductivity.
    The second amorphous semiconductor layer has a p-type conductivity,
    In the passivation layer, the thickness of the region in contact with the second amorphous semiconductor layer is larger than the thickness in the region in contact with the first amorphous semiconductor layer.
  5. 　請求項１から４のいずれか１項に記載の光電変換素子であって、
    　前記パッシベーション層は、前記凹部が設けられていない部分の厚みが５ｎｍ～２０ｎｍである、光電変換素子。     It is a photoelectric conversion element given in any 1 paragraph of Claims 1-4,
    The photoelectric conversion element, wherein the passivation layer has a thickness of 5 nm to 20 nm at a portion where the concave portion is not provided.
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JPWO2020217999A1 (en) * 2019-04-23 2021-11-25 株式会社カネカ Manufacturing method of solar cells and solar cells
JP7169440B2 (en) 2019-04-23 2022-11-10 株式会社カネカ SOLAR CELL MANUFACTURING METHOD AND SOLAR CELL

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