WO2016072415A1 - Photoelectric conversion element - Google Patents

Photoelectric conversion element Download PDF

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Publication number
WO2016072415A1
WO2016072415A1 PCT/JP2015/081026 JP2015081026W WO2016072415A1 WO 2016072415 A1 WO2016072415 A1 WO 2016072415A1 JP 2015081026 W JP2015081026 W JP 2015081026W WO 2016072415 A1 WO2016072415 A1 WO 2016072415A1
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Prior art keywords
semiconductor layer
film thickness
type
photoelectric conversion
film
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PCT/JP2015/081026
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French (fr)
Japanese (ja)
Inventor
神川　剛
真臣 原田
敏彦 酒井
督章 國吉
柳民 鄒
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シャープ株式会社
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Priority to JP2016557773A priority Critical patent/JP6639407B2/en
Publication of WO2016072415A1 publication Critical patent/WO2016072415A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT® solar cells; solar cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present invention relates to a photoelectric conversion element.
  • Japanese Laid-Open Patent Publication No. 2012-28718 discloses a back junction solar cell in which intrinsic (i-type) amorphous silicon is interposed between an n-type crystalline silicon substrate and a p-type amorphous silicon layer. Has been. By interposing the intrinsic amorphous silicon, the passivation property is improved, the recombination of carriers at the interface between the n-type crystalline silicon substrate and the p-type amorphous silicon layer is suppressed, and the photoelectric conversion efficiency is improved.
  • a passivation film such as intrinsic amorphous silicon can be provided between the n-type crystalline silicon substrate and the p-type amorphous silicon layer to improve the passivation property.
  • the series resistance component becomes high and the photoelectric conversion efficiency decreases.
  • An object of the present invention is to provide a photoelectric conversion element capable of reducing the series resistance component and improving the photoelectric conversion efficiency.
  • a photoelectric conversion element is formed on a semiconductor substrate, a first amorphous semiconductor layer having a first conductivity type formed on one surface of the semiconductor substrate, and one surface of the semiconductor substrate. And a second amorphous semiconductor layer formed adjacent to the first amorphous semiconductor layer in an in-plane direction of the semiconductor substrate and having a second conductivity type opposite to the first conductivity type; A first electrode formed on the first amorphous semiconductor layer; and a second electrode formed on the second amorphous semiconductor layer, the first electrode formed on the semiconductor substrate.
  • the point where the film thickness is maximum is the first point, and the reduction rate of the thickness of the thin film is larger than the first reduction rate from the first reduction rate in the in-plane direction of the one thin film.
  • the point of change of the second reduction rate, or the thickness of the one thin film in the in-plane direction of the one thin film is defined as the second point, and the region from the first point to the second point in the in-plane direction of the one thin film is defined as the film thickness reduction region.
  • the first amorphous semiconductor layer and the second amorphous semiconductor layer has the film thickness reduction region, at least one of the electrodes formed on the at least one semiconductor layer. The part is formed on the film thickness reduction region.
  • the series resistance component can be reduced and the photoelectric conversion efficiency can be improved.
  • FIG. 1 is a cross-sectional view schematically showing the photoelectric conversion element according to the first embodiment.
  • FIG. 2 is an enlarged schematic view of the electrode shown in FIG.
  • FIG. 3A is a diagram showing the results of measuring the film thickness of the n-type semiconductor layer shown in FIG.
  • FIG. 3B is a diagram showing a micrograph of the surface of the silicon substrate.
  • FIG. 3B (b) is a diagram showing the results of measuring the surface height of the silicon substrate shown in FIG. 3B (a).
  • (A) of FIG. 3C is the figure which illustrated the result of having measured the film thickness from the interface of the passivation film on a silicon substrate, and the silicon substrate surface to the semiconductor layer surface.
  • FIG. 3A is a cross-sectional view schematically showing the photoelectric conversion element according to the first embodiment.
  • FIG. 2 is an enlarged schematic view of the electrode shown in FIG.
  • FIG. 3A is a diagram showing the results of measuring the film thickness of the n-type semiconductor layer shown in FIG
  • FIG. 3C (b) is a diagram showing a result of re-plotting each film thickness shown in FIG. 3C (a).
  • FIG. 4 is a cross-sectional view showing a state where the thickness reduction regions of adjacent n-type semiconductor layers and p-type semiconductor layers overlap.
  • FIG. 5 is a cross-sectional view showing the configuration of the n-type electrode.
  • FIG. 6A is a diagram illustrating a manufacturing process of the photoelectric conversion element according to the first embodiment.
  • FIG. 6B is a diagram illustrating a manufacturing process of the photoelectric conversion element according to the first embodiment.
  • FIG. 6C is a diagram illustrating a manufacturing process of the photoelectric conversion element according to the first embodiment.
  • FIG. 6A is a diagram illustrating a manufacturing process of the photoelectric conversion element according to the first embodiment.
  • FIG. 6B is a diagram illustrating a manufacturing process of the photoelectric conversion element according to the first embodiment.
  • FIG. 6C is a diagram illustrating a manufacturing process of the
  • FIG. 6D is a diagram illustrating a manufacturing process of the photoelectric conversion element according to the first embodiment.
  • FIG. 7 is a diagram for explaining the relationship between the thickness and opening width of the metal mask, the film thickness reduction region, and the tapered region.
  • FIG. 8 is a cross-sectional view of four electrodes having different positions at both ends of the n-type electrode. It is a figure which shows the result of having measured the serial resistance component and open circuit voltage of each electrode shown in FIG.
  • FIG. 10 is a cross-sectional view of the electrode of the photoelectric conversion element according to the second embodiment.
  • FIG. 11 is a diagram showing the results of measuring the film thickness of the n-type semiconductor layer shown in FIG.
  • FIG. 12 is a cross-sectional view of the photoelectric conversion element according to the fourth embodiment.
  • FIG. 13 is an enlarged schematic view of a region where the electrode shown in FIG. 12 is formed.
  • FIG. 14 is a diagram illustrating the ratio of the thickness of the first passivation layer and the second passivation layer) and the measurement result of the photoelectric conversion efficiency.
  • FIG. 15 is a cross-sectional view of the photoelectric conversion element according to the fifth embodiment.
  • FIG. 16A is a cross-sectional view of the photoelectric conversion element according to the sixth embodiment.
  • FIG. 16B is an enlarged schematic view of a part of the wiring sheet in the sixth embodiment.
  • FIG. 17A is a cross-sectional view of the photoelectric conversion element according to the seventh embodiment.
  • FIG. 17B is a diagram showing a micrograph of the surface of the silicon substrate shown in FIG. 17A.
  • FIG. 18 is a schematic diagram illustrating a configuration of a photoelectric conversion module according to the eighth embodiment.
  • FIG. 19A is a schematic diagram illustrating a configuration of a photovoltaic power generation system including a photoelectric conversion element according to the ninth embodiment.
  • FIG. 19B is a schematic diagram illustrating another configuration example of the photovoltaic power generation system illustrated in FIG. 19A.
  • FIG. 20 is a schematic diagram illustrating a configuration of the photoelectric conversion module array illustrated in FIG. 19A.
  • FIG. 21A is a schematic diagram illustrating a configuration of a photovoltaic power generation system including a photoelectric conversion element according to the tenth embodiment.
  • FIG. 21B is a schematic diagram illustrating another configuration example of the photovoltaic power generation system illustrated in FIG. 21A.
  • a photoelectric conversion device includes a semiconductor substrate, a first amorphous semiconductor layer having a first conductivity type formed on one surface of the semiconductor substrate, and one of the semiconductor substrates.
  • a second amorphous semiconductor formed on a surface and adjacent to the first amorphous semiconductor layer in an in-plane direction of the semiconductor substrate and having a second conductivity type opposite to the first conductivity type A layer, a first electrode formed on the first amorphous semiconductor layer, and a second electrode formed on the second amorphous semiconductor layer, and formed on the semiconductor substrate
  • the point where the film thickness is maximum is taken as a first point, and the reduction rate of the film thickness in the in-plane direction of the one thin film is changed from the first reduction rate to the first decrease.
  • the region from the first point to the second point in the in-plane direction of the one thin film is the film thickness.
  • the region from the first point to the second point in the in-plane direction of the one thin film is the film thickness.
  • the first amorphous semiconductor layer and the second amorphous semiconductor layer has the reduced thickness region and is formed in the at least one semiconductor layer.
  • At least a part of the electrodes is formed on the film thickness reduction region (first configuration).
  • At least one of the first amorphous semiconductor layer and the second amorphous semiconductor layer has a thickness reduction region. At least a part of the electrode formed on the semiconductor layer having the film thickness reduction region is formed in contact with at least a part of the film thickness reduction region. Since the film thickness of the film thickness reduction region is smaller than the film thickness at the first point of the semiconductor layer, the series resistance component can be reduced as compared with the case where an amorphous semiconductor layer having a uniform film thickness is provided. .
  • the semiconductor layer having the film thickness reduction region may have the same conductivity type as the semiconductor substrate.
  • the film thickness reduction region is provided in the semiconductor layer having the same conductivity type as the semiconductor substrate, the series resistance component with respect to majority carriers can be further reduced.
  • each of the first amorphous semiconductor layer and the second amorphous semiconductor layer has the film thickness reduction region.
  • the film thickness reduction regions of the adjacent first amorphous semiconductor layer and the second amorphous semiconductor layer may be arranged apart from each other.
  • the film thickness in the film thickness reduction region is smaller than the case where the film thickness reduction region of the first amorphous semiconductor layer and the second amorphous semiconductor layer are arranged to overlap,
  • the series resistance component can be reduced.
  • the dopant concentration in the film thickness reduction region is the film thickness reduction. It is good also as higher than the dopant density
  • the dopant concentration in the film thickness reduction region is higher than the dopant concentration in the region where the film thickness is thicker than the film thickness reduction region. Therefore, the series resistance in the film thickness reduction region can be reduced, and the contact resistance between the semiconductor layer having the film thickness reduction region and the electrode formed on the semiconductor layer can be reduced.
  • the photoelectric conversion element according to the fifth configuration is any one of the first to fourth configurations, and further includes the semiconductor substrate, the first amorphous semiconductor layer, and the second amorphous semiconductor layer. It is good also as providing the 1st passivation film formed between these.
  • the series resistance component can be reduced and the passivation property of the semiconductor substrate can be improved.
  • the photoelectric conversion element according to the sixth configuration is further formed between the first passivation film and the first amorphous semiconductor layer and the second amorphous semiconductor layer in the fifth configuration.
  • a second passivation film may be provided, and the first passivation film and the second passivation film may be made of an intrinsic amorphous semiconductor.
  • the second passivation film may include the film thickness reduction region.
  • the seventh configuration since the thickness of the film thickness reduction region in the second passivation film is smaller than the film thickness of the first point in the second passivation film, the series resistance in the film thickness reduction region in the second passivation film. Components can be reduced.
  • the passivation property can be improved and the series resistance component can be reduced.
  • the first passivation film may be formed of an insulator capable of tunneling carriers. According to the ninth configuration, the semiconductor substrate can be passivated and the carrier can be easily taken out.
  • the insulator is any one of an oxide, a nitride, and an oxynitride of an amorphous semiconductor containing at least a Group 4 element. Alternatively, it may be made of polycrystalline silicon.
  • the silicon substrate 11 is, for example, an n-type single crystal silicon substrate.
  • the thickness of the silicon substrate 11 is, for example, 100 to 150 ⁇ m.
  • the silicon substrate 11 may be a p-type single crystal silicon substrate instead of the n-type single crystal silicon substrate.
  • a texture is formed on one surface (Z-axis negative direction side) of the silicon substrate 11.
  • the texture decreases the surface reflectance of the silicon substrate 11 and increases the short circuit current.
  • the surface on which the texture is formed is referred to as the light receiving surface of the silicon substrate 11, and the other surface (the Z-axis positive direction side) is referred to as the back surface.
  • a passivation layer 13 is formed on the back surface of the silicon substrate 11.
  • the passivation layer 13 is composed of a thermal oxide film of the silicon substrate 11.
  • the passivation layer 13 may be, for example, amorphous silicon, amorphous silicon oxide, nitride, oxynitride, polycrystalline silicon, or the like.
  • the thickness of the passivation layer 13 is preferably 1 to 20 nm, for example, and more preferably 1 to 3 nm. In the present embodiment, the thickness of the passivation layer 13 is 2 nm.
  • the n-type semiconductor layer 15n is an n-type amorphous semiconductor layer containing hydrogen.
  • the n-type semiconductor layer 15n includes, for example, phosphorus (P) as an impurity, n-type amorphous silicon, n-type amorphous silicon germanium, n-type amorphous germanium, n-type amorphous silicon carbide, n-type It may be amorphous silicon nitride, n-type amorphous silicon oxide, n-type amorphous silicon oxynitride, n-type amorphous silicon carbon oxide, or the like.
  • the thickness of the n-type semiconductor layer 15n is, for example, 3 to 50 nm.
  • the p-type semiconductor layer 15p is a p-type amorphous semiconductor layer containing hydrogen.
  • the p-type semiconductor layer 15p includes, for example, boron (B) as an impurity, p-type amorphous silicon, p-type amorphous silicon germanium, p-type amorphous germanium, p-type amorphous silicon carbide, p-type. It may be amorphous silicon nitride, p-type amorphous silicon oxide, p-type amorphous silicon oxynitride, p-type amorphous silicon carbon oxide, or the like.
  • the thickness of the p-type semiconductor layer 15p is, for example, 5 to 50 nm.
  • An n-type electrode 16n is formed on the n-type semiconductor layer 15n.
  • a p-type electrode 16p is formed on the p-type semiconductor layer 15p.
  • the n-type electrode 16n and the p-type electrode 16p are configured by laminating two conductive layers described later. The detailed structure of the n-type electrode 16n and the p-type electrode 16p will be described later.
  • FIG. 2 is an enlarged schematic view of a portion where the n-type semiconductor layer 15n shown in FIG. 1 is formed.
  • FIG. 3A shows the result of measuring the film thickness of the n-type semiconductor layer 15n by scanning the n-type semiconductor layer 15n in the in-plane direction (X-axis direction) with a stylus profilometer.
  • the film thickness of the n-type semiconductor layer 15n changes substantially between the length of 280 ⁇ m from the point C, which is substantially the center of the n-type semiconductor layer 15n, and between the point C and 380 ⁇ m.
  • the flat region L is a region where the film thickness hardly changes from the maximum film thickness.
  • the length in the scan direction is between 280 ⁇ m and 380 ⁇ m.
  • the film thickness of the region from one end K10 to K11 (K1) of the flat region L and the region from the other end K20 to K12 (K1) of the flat region L is moderate. is decreasing.
  • the film thickness of the region from K11 to K21 (K2) and the region from K12 to K22 (K2) are sharply decreased. That is, the region from K11 to K21 is smaller than the film thickness reduction rate (first reduction rate) in the region from one end K10 to K11 of the flat region L and the region from the other end K20 to K12 of the flat region L.
  • the film thickness reduction rate (second reduction rate) in the region from K12 to K22 is large.
  • the film thickness reduction region T is a region where the film thickness reduction rate gradually changes in the n-type semiconductor layer 15n.
  • the region from the end K10 to the point K11 of the flat region L and the flat region L This is the region from the end K20 to the point K12. That is, in the present embodiment, the film thickness reduction region is defined as a first point in the thin film formed on the silicon substrate 11, where the thin film has the maximum film thickness, and the in-plane direction of the thin film.
  • the second point is the point at which the film thickness decrease rate changes from the first decrease rate to the second decrease rate larger than the first decrease rate, the first point in the in-plane direction of the thin film To the second point.
  • the tapered region R is a region formed in a taper shape, and is a region from the point K2 (K21, K22) to the lower end K3 (K31, K32) of the n-type semiconductor layer 15n.
  • the width of the tapered region R varies depending on the film formation conditions of the semiconductor layer described later, but is, for example, 400 ⁇ m or less, and more preferably 100 ⁇ m or less.
  • the film thickness reduction amount d in the film thickness reduction region T of the n-type semiconductor layer 15n is preferably 5% or more of the film thickness h of the flat region L, and more preferably 10% or more. . That is, in FIG. 3A, the amount of decrease in the film thickness from the end K10, K20 of the flat region L to the point K11, K21 is preferably 5% or more of the film thickness of the flat region L, and is 10% or more. It is more preferable.
  • the vertical axis in FIG. 3A indicates the film thickness of the n-type semiconductor layer 15n normalized by setting the film thickness of the flat region L to 1.0. As shown in FIG.
  • the film thickness reduction region T is reduced by 20% or more than the film thickness of the flat region L, which is a preferable state. Further, the width of the film thickness reduction region T can be controlled by a film forming method described later, and is preferably 20 ⁇ m or more, and more preferably 100 ⁇ m or more.
  • FIG. 3B is a photomicrograph of the surface of the silicon substrate 11. Moreover, (b) of FIG. 3B is a figure which shows the result of having measured the height of the silicon substrate 11 surface.
  • the film thickness of the silicon substrate 11 shown in FIG. 3A is a film thickness excluding the unevenness of the silicon substrate 11.
  • the film thickness reduction region T in the n-type semiconductor layer 15n and the p-type semiconductor layer 15p when the silicon substrate 11 is uneven can be determined as follows.
  • FIG. 3C is a schematic diagram showing the result of measuring the film thickness h from the interface 11S between the passivation film 13 and the surface of the silicon substrate 11 to the surface of the n-type semiconductor layer 15n or the p-type semiconductor layer 15p. .
  • each film thickness h shown in FIG. 3C (a) can be expressed as shown in FIG. 3C (b). That is, as shown in FIG. 3A, the film thickness of the semiconductor layer (n-type semiconductor layer 15n, p-type semiconductor layer 15p) can be specified on the assumption that the surface of the silicon substrate 11 is substantially flat. Therefore, even if the surface of the silicon substrate 11 has a concavo-convex shape, each film thickness reduction region T in the n-type semiconductor layer 15n and the p-type semiconductor layer 15p is verified by using such a method. Is possible.
  • the film thickness reduction region T is determined by measuring and re-plotting the film thickness on the texture by the above method. Judgment can be made.
  • the width of the film thickness reduction region T of the n-type semiconductor layer 15n is larger than the width of the film thickness reduction region T of the p-type semiconductor layer 15p.
  • the width of the film thickness reduction region T of the p-type semiconductor layer 15p is opposite to that of the film thickness reduction region T of the n-type semiconductor layer 15n. It is preferable that it is larger than the width.
  • the reduction amount of the film thickness in the thickness reduction region T the reduction amount of the semiconductor layer having the same conductivity type as that of the silicon substrate 11 may be larger than the reduction amount of the film thickness of the other semiconductor layer. More preferred.
  • FIG. 4 shows a schematic diagram in the case where the film thickness reduction regions T of the adjacent n-type semiconductor layer 15n and p-type semiconductor layer 15p overlap.
  • the film thickness reduction region Tp of the p-type semiconductor layer 15p is formed on the film thickness reduction region Tn of the n-type semiconductor layer 15n, so that the passivation property is improved.
  • the series resistance component does not decrease, and the low resistance The effect of conversion will not be obtained.
  • the respective thickness reduction regions T in the adjacent semiconductor layers do not overlap. Furthermore, in consideration of the yield of productivity and the like, it is preferable that the distance between the K1 points that are the end portions of the respective film thickness reduction regions T in the adjacent semiconductor layers is 20 ⁇ m or more, and more preferably 100 ⁇ m or more.
  • FIG. 5 is an enlarged schematic view of a region where the n-type semiconductor layer 15n is disposed.
  • the n-type electrode 16n has a stacked structure in which a first conductive layer 161 and a second conductive layer 162 are stacked.
  • the p-type electrode 16p has a stacked structure in which the first conductive layer 161 and the second conductive layer 162 are stacked in the same manner as the n-type electrode 16n.
  • the first conductive layer 161 is made of a transparent conductive film such as ITO (Indium Tin Oxide), ZnO, or IWO (Indium Tungsten Oxide).
  • ITO Indium Tin Oxide
  • ZnO Zinc Oxide
  • IWO Indium Tungsten Oxide
  • the first conductive layer 161 is preferably made of a transparent conductive film having high adhesion to the n-type semiconductor layer 15n and the p-type semiconductor layer 15p.
  • the thickness of the first conductive layer 161 is preferably 3 to 100 nm, for example.
  • the second conductive layer 162 is preferably formed using a metal having higher conductivity than the first conductive layer 161.
  • the thickness of the second conductive layer 162 is preferably 50 nm or more.
  • the thickness of the second conductive layer 162 in this embodiment is, for example, about 0.8 ⁇ m.
  • the n-type electrode 16n and the p-type electrode 16p have a stacked structure in which the first conductive layer 161 and the second conductive layer 162 are stacked.
  • the first conductive layer 161 is not provided and the second conductive layer is not provided.
  • the layer 162 may be formed in contact with the n-type semiconductor layer 15n or the p-type semiconductor layer 15p.
  • the second conductive layer 162 is preferably made of a metal having high adhesion with the n-type semiconductor layer 15n and the p-type semiconductor layer 15p.
  • the second conductive layer 162 is made of, for example, any metal such as Ti (titanium), Ni (nickel), Al (aluminum), and Cr (chromium) having a thickness of about 1 to 10 nm, Al It is good also as having a laminated structure which laminated
  • the n-type electrode 16n is also formed on the film thickness reduction region T. Specifically, the n-type electrode 16n is formed such that both end portions Z1, Z2 in the X-axis direction of the n-type electrode 16n are located in the film thickness reduction region T.
  • the p-type electrode 16p is formed so that both ends in the X-axis direction of the p-type electrode 16p are located in the film thickness decreasing region T in the p-type semiconductor layer 15p, similarly to the n-type electrode 16n. ing.
  • a wafer having a thickness of 100 to 300 ⁇ m is cut out from bulk silicon, and etching for removing a damaged layer on the wafer surface and etching for adjusting the thickness are performed.
  • a protective film is formed on one side of these etched wafers.
  • silicon oxide, silicon nitride, or the like is used as the protective film.
  • the wafer on which the protective film is formed is subjected to wet etching using an alkaline solution such as NaOH or KOH (for example, an aqueous solution of KOH: 1 to 5 wt%, isopropyl alcohol: 1 to 10 wt%).
  • an alkaline solution such as NaOH or KOH
  • a texture structure is formed on the surface where the protective film is not formed by anisotropic etching.
  • the ARC 12 is formed on the light receiving surface of the silicon substrate 11, and the passivation layer 13 is formed on the back surface.
  • the ARC 12 has a stacked structure in which a silicon oxide film and a silicon nitride film are stacked, and the case where the passivation layer 13 is formed of a silicon oxide film will be described.
  • the surface of the silicon substrate 11 is thermally oxidized to form an oxide film on the light receiving surface and a passivation layer 13 on the back surface.
  • an ARC 12 is formed by forming a silicon nitride film on the oxide film on the light receiving surface.
  • a wet process or a thermal oxidation process may be used.
  • the silicon substrate 11 is immersed in hydrogen peroxide, nitric acid, ozone water, or the like, and then heated to 800 to 1000 ° C. in a dry atmosphere.
  • thermal oxidation treatment for example, the silicon substrate 11 is heated to 900 to 1000 ° C. in an atmosphere of oxygen or water vapor.
  • the silicon nitride film can be formed by sputtering, EB (Electron Beam) vapor deposition, TEOS (TetraEthoxySilane), or the like.
  • the passivation layer 13 is nitrided with nitrogen plasma using plasma CVD (Plasma Enhanced Chemical Vapor Deposition), and further annealed at 500 ° C. or higher to form a SiON film on the back surface of the silicon substrate 11.
  • plasma CVD Plasma Enhanced Chemical Vapor Deposition
  • the passivation layer 13 of SiON it is possible to suppress diffusion of impurities such as boron contained in the p-type semiconductor layer 15p formed on the passivation layer 13 into the silicon substrate 11. it can. Further, even when the passivation layer 13 having a thickness capable of flowing a tunnel current is formed, diffusion of impurities such as boron can be effectively suppressed.
  • the passivation of the surface of the silicon substrate 11 is one of the important points.
  • the passivation film 13 is formed with a substantially uniform film thickness on the entire surface of the silicon substrate 11 by a single film formation.
  • the purpose of forming the passivation film 13 by one film formation as in this embodiment is not the purpose of passivation the entire surface of the silicon substrate 11 by multiple film formation intentionally. More preferred.
  • the passivation film 13 may not have a completely uniform thickness.
  • the passivation film 13 is not limited to the entire surface of the silicon substrate 11, and the passivation film 13 may not be formed on a part of the surface of the silicon substrate 11 such as the periphery of the wafer or the alignment mark portion.
  • the passivation property of the silicon substrate 11 can be improved by forming the passivation film 13 substantially uniformly on the substantially entire surface of the silicon substrate 11.
  • a metal mask 110 is disposed on the passivation layer 13 to form an n-type semiconductor layer 15n.
  • the n-type semiconductor layer 15n is formed so that the width of the flat region L is about 100 ⁇ m and the width of the film thickness reduction region T is about 150 ⁇ m.
  • the metal mask 110 (110A) has an opening 110a in a portion where the n-type semiconductor layer 15n is formed on the silicon substrate 11.
  • the metal mask 110 has a thickness M of 200 ⁇ m and an opening width O of 400 ⁇ m.
  • the metal mask 110 may be made of a metal such as stainless steel, copper, nickel, an alloy containing nickel (for example, 42 alloy or Invar material), molybdenum or the like. Considering the thermal expansion coefficient of the silicon substrate 11 and the raw material cost, the metal mask 110 is more preferably 42 alloy. Regarding the thickness M of the metal mask 110, considering the manufacturing cost, it becomes a problem to dispose the metal mask 110 once.
  • the metal mask 110 Since the running cost of production can be suppressed by using the metal mask 110 many times, it is preferable to recycle the metal mask 110 and use it many times.
  • the film deposited on the metal mask 110 is removed using hydrofluoric acid or NaOH.
  • the thickness M of the metal mask 110 is preferably about 30 ⁇ m to 300 ⁇ m.
  • a metal mask is used instead of the metal mask.
  • a mask made of glass, ceramic, an organic film, or the like may be used instead of the metal mask.
  • the n-type semiconductor layer 15n is formed using, for example, plasma CVD.
  • the reaction gas introduced into the reaction chamber provided in the plasma CVD apparatus is silane gas, hydrogen gas, and phosphine gas diluted with hydrogen (phosphine concentration: 1%).
  • the hydrogen gas flow rate is 0 to 100 sccm
  • the silane gas flow rate is 40 sccm
  • the phosphine gas flow rate is 40 sccm.
  • the temperature of the silicon substrate 11 is 130 to 180 ° C., for example.
  • the pressure in the reaction chamber is 40 to 120 Pa, and the RF power density is 5 to 15 mW / cm 2 . Thereby, n-type amorphous silicon (n-type semiconductor layer 15n) doped with phosphorus is formed.
  • the width of the film thickness reduction region T and the film thickness reduction amount of the n-type semiconductor layer 15n can be controlled by changing the film formation pressure. It can also be controlled by the thickness M and opening width O of the metal mask 110A.
  • the thickness M of the metal mask 110 is increased, as shown in FIG. 7, the film formation in the region Sa in the vicinity of the opening 110a on the metal mask 110A becomes remarkable, and the width of the film thickness reduction region T is increased accordingly. .
  • this phenomenon appears remarkably by reducing the opening width O.
  • an appropriate film thickness reduction region T can be formed.
  • the metal mask 110A is removed, and a metal mask 110 (110B) having an opening 110b in a region where the n-type semiconductor layer 15n is not formed is disposed on the silicon substrate 11, and p A type semiconductor layer 15p is formed.
  • the p-type semiconductor layer 15p is formed using, for example, plasma CVD.
  • the reaction gas introduced into the reaction chamber provided in the plasma CVD apparatus is silane gas, hydrogen gas, and diborane gas diluted with hydrogen (diborane concentration: 2%).
  • the hydrogen gas flow rate is 0 to 100 sccm
  • the silane gas flow rate is 40 sccm
  • the diborane gas flow rate is 40 sccm.
  • the temperature of the silicon substrate 11 is 130 to 180 ° C.
  • the pressure in the reaction chamber is 40 to 120 Pa
  • the RF power density is 5 to 15 mW / cm 2 .
  • p-type amorphous silicon (p-type semiconductor layer 15p) doped with boron is formed.
  • the film thickness reduction region T of the p-type semiconductor layer 15p is controlled by adjusting the film formation pressure, the thickness of the metal mask 110B, and the opening width, similarly to the n-type semiconductor layer 15n. can do.
  • the n-type semiconductor layer 15n and the p-type semiconductor layer 15p are formed adjacent to each other on the passivation layer 13 by removing the metal mask 110B.
  • the space between the n-type semiconductor layer 15n and the p-type semiconductor layer 15n is covered with a metal mask 110 (110C), and the n-type semiconductor layer 15n and the p-type semiconductor layer 15n are overlaid on the n-type semiconductor layer 15n.
  • An electrode 16n and a p-type electrode 16p are formed.
  • the metal mask 110C is arranged so that the end of the opening 110c is positioned in the film thickness reduction region T of the adjacent n-type semiconductor layer 15n and p-type semiconductor layer 15p.
  • the n-type electrode 16n and the p-type electrode 16p have a stacked structure in which a first conductive layer 161 and a second conductive layer 162n are stacked.
  • the first conductive layer 161 and the second conductive layer 162 are formed by spraying a sputtering method, an EB vapor deposition method, an ion plating method, a thermal CVD method, a MOCVD (Metal-Organic-Chemical-Vapor-Deposition) method, a sol-gel method, or a liquid material. It can be formed using a heating method, an inkjet method, or the like.
  • the first conductive layer 161 is composed of any one of ITO, IWO, and ZnO.
  • the second conductive layer 162 is composed of a laminated film of a first metal and a second metal.
  • the first conductive layer 161 is formed using, for example, sputtering.
  • sputtering may be performed under the following film formation conditions.
  • an ITO target doped with 0.5 to 4 wt% of SnO 2 is used, and argon gas or a mixed gas of argon gas and oxygen gas is introduced.
  • the temperature of the silicon substrate 11 is 25 to 250 ° C.
  • the gas pressure is 0.1 to 1.5 Pa
  • the input power is 0.01 to 2 kW.
  • a ZnO target doped with 0.5 to 4 wt% Al is used instead of the ITO target.
  • the second conductive layer 162 may be formed by using, for example, an EB vapor deposition method, or the first conductive layer 161 may be used as a seed layer, and the second conductive layer 162 may be formed by a plating film forming method.
  • Ti is formed as the first metal of the second conductive layer 162
  • Al is formed as the second metal on the first metal, thereby forming a laminated film of Ti and Al (Ti / Al).
  • a second conductive layer 162 is formed.
  • Ti for example, Ni, W, Co, or the like may be used as the first metal.
  • an alloy of these metals may be used, or an alloy of these metals and P or B may be used.
  • Al for example, Cu, Sn, or the like may be used as the second metal.
  • FIG. 1 By arranging the metal mask 110C so that the end of the width of the opening 110c of the metal mask 110C is located in each of the film thickness reduction regions T of the n-type semiconductor layer 15n and the p-type semiconductor layer 15p, FIG. As shown, the n-type electrode 16n is formed such that both end portions Z1, Z2 of the n-type electrode 16n are located in the film thickness reduction region T of the n-type semiconductor layer 15n. Although not shown, the p-type electrode 16p is similarly formed so that both end portions Z1 and Z2 of the p-type electrode 16p are located in the film thickness reduction region T of the p-type semiconductor layer 15p.
  • the photoelectric conversion element 1 shown in FIG. 1 is formed by the manufacturing method described above.
  • the p-type semiconductor layer 15 p and the silicon substrate 11 form a pn junction through the passivation layer 13.
  • electrons and holes are generated. Electrons and holes are tunneled through the passivation layer 13 and moved to the n-type semiconductor layer 15n and the p-type semiconductor layer 15p, respectively, and are taken out as current through the n-type electrode 16n and the p-type electrode 16p.
  • the passivation layer 13 reduces defects at the interface between the silicon substrate 11 and the n-type semiconductor layer 15n and the interface between the silicon substrate 11 and the p-type semiconductor layer 15p.
  • the n-type electrode 16n and the p-type electrode 16p have been described as being formed such that both end portions Z1 and Z2 of each electrode are located in the film thickness reduction region T in the corresponding semiconductor layer.
  • the relationship between the positions of both ends Z1, Z2 of the n-type electrode 16n and the p-type electrode 16p, the series resistance component Rs of the photoelectric conversion element, and the open circuit voltage Voc will be described.
  • FIGS. 8A to 8D are schematic views showing four electrodes (161n, 16n, 162n, 163n) in which the positions of both end portions Z1, Z2 of the n-type electrode 16n are different, and FIG. FIG. 9 is a diagram showing the results of measuring a series resistance component Rs and an open circuit voltage Voc when each n-type electrode shown in FIGS. 8A to 8D is used.
  • the n-type semiconductor layer 15n under each n-type electrode has a flat region L, a film thickness reduction region T, and a tapered region R.
  • 8A shows that both end portions Z1 and Z2 of the n-type electrode 161n are located in the flat region L
  • FIG. 8B shows both end portions Z1 of the n-type electrode 16n as in the above-described embodiment.
  • Z2 are located in the film thickness reduction region T.
  • both end portions Z1, Z2 of the n-type electrode 162n are located in the tapered region R
  • FIG. 8D both end portions Z1, Z2 of the n-type electrode 163n are tapered. It is located outside the shape region R.
  • the n-type electrode 161n shown in FIG. 8A has substantially the same characteristics as when the film thickness reduction region T is not formed. Therefore, as shown in FIG. 9, the series resistance component Rs and the open circuit voltage Voc in the case of FIG. 8A are set to 1.0, which are used as references.
  • the series resistance component Rs is reduced to 88% as compared with the electrode 161n shown in FIG. The same as the case of the mold electrode 161n. That is, when the n-type electrode 16n shown in FIG. 8B is used, the resistance can be lowered while securing the passivation property as compared with the case where the n-type electrode 161n is used. Further, as shown in FIG. 9, when the n-type electrode 162n shown in FIG. 8C and the n-type electrode 163n shown in FIG. 8D are used, the n-type shown in FIG.
  • both end portions Z1 and Z2 of the n-type electrode 16n are arranged inside the tapered region R. In the case of being located on the outside, the resistance can be reduced.
  • FIG. 8B in which both end portions Z1 and Z2 of the n-type electrode 16n are located in the film thickness reduction region T, it is possible to achieve low resistance while ensuring passivation. It can be said that this is preferable to the case where the n-type electrodes 162n and 163n in FIGS. 8C and 8D are used.
  • the film thickness reduction region T is formed in each of the n-type semiconductor layer 15n and the p-type semiconductor layer 15p has been described, but the film thickness reduction region T is formed in any one of the semiconductor layers. Even if it is provided, an effect of low resistance can be obtained. Therefore, the film thickness reduction region T only needs to be provided in at least one of the n-type semiconductor layer 15n and the p-type semiconductor layer 15p.
  • the film thickness reduction region T in the n-type and p-type semiconductor layers 15n and 15p is thinner than the central portion of the n-type and p-type semiconductor layers 15n and 15p. Therefore, by forming at least part of the n-type electrode 16n or the p-type electrode 16p in the film thickness reduction region T, the series resistance can be reduced and the characteristics of the photoelectric conversion element can be improved.
  • the width of the opening of the metal mask 110, the thickness of the metal mask 110, or the film formation pressure is controlled to be flat.
  • the region L and the film thickness reduction region T are formed by one film formation. Compared with the flat region L, the film thickness reduction region T has a relatively slow film formation rate, so that the impurity concentration is relatively increased as compared with the flat region L. As a result, the series resistance component in the film thickness reduction region T can be reduced, and the contact resistance can be further reduced.
  • the metal mask 110 is used, and the first conductive layer 161 and the second conductive layer 162 having different conductivities are formed once on the n-type and p-type semiconductor layers 15n and 15p. Can be formed. Therefore, compared with the case where the 1st conductive layer 161 and the 2nd conductive layer 162 are formed using photolithography etc., the manufacturing process of the photoelectric conversion element 1 can be shortened, and manufacturing cost can be reduced.
  • an amorphous silicon film formed by thermal oxidation is formed on the entire back surface of the silicon substrate 11 as the passivation layer 13. Therefore, although the in-plane distribution is slightly generated, the back surface of the silicon substrate 11 can be covered with a substantially uniform film thickness and can be passivated.
  • the semiconductor layers (n-type semiconductor layer 15n and p-type semiconductor layer 15p) having the film thickness reduction region T are formed on the substantially uniform passivation film 13 so as to reduce the film thickness. Electrodes (n-type electrode 16n and p-type electrode 16p) are formed on region T. Such a configuration is more preferable because it can achieve both passivation properties and low resistance at the interface of the silicon substrate 11.
  • FIG. 10 is a cross-sectional view of the electrode of the photoelectric conversion element according to this embodiment.
  • the electrode 24n includes an n-type semiconductor layer 25n and an n-type electrode 26n.
  • the n-type semiconductor layer 25n and the n-type electrode 26n are each made of the same material as the n-type semiconductor layer 15n and the n-type electrode 16n in the first embodiment.
  • the n-type semiconductor layer 25n has a film thickness reduction region T1 and a tapered region R.
  • FIG. 11 shows the n-type semiconductor layer 25n when the opening width O of the metal mask 110 is 400 ⁇ m as in the first embodiment and the film formation pressure is higher than the film formation pressure of the first embodiment (for example, 150 Pa). The film thickness measurement results are shown.
  • the film thickness of the point C10 that is the center of the n-type semiconductor layer 25n shown in FIG. 11 is substantially the same as the film thickness of the center point C of the n-type semiconductor layer 15n in the first embodiment.
  • the reduction rate of the film thickness in the region from C10 to K10 of the n-type semiconductor layer 25n is smaller than the reduction rate of the film thickness in the region from K10 to K20.
  • each region T1 from C10 to K10 is a film thickness decreasing region in the n-type semiconductor layer 25n.
  • the film thickness is substantially the same from the point K20 toward the outside of the n-type semiconductor layer 25n, and the tapered region R is not formed.
  • the tapered region R can be formed.
  • the n-type electrode 26n is formed so that both end portions Z1 and Z2 of the n-type electrode 26n are located in the film thickness decreasing region T1 of the n-type semiconductor layer 25n as in the first embodiment. To do.
  • the series resistance component can be reduced as compared with the case of the n-type electrode 161n shown in FIG. Therefore, even when the flat region L is not formed in the n-type and p-type semiconductor layers 15n and 15p, at least a part of the n-type electrode 16n and the p-type electrode 16p is formed on the film thickness reduction region T1. If so, the resistance can be reduced.
  • the photoelectric conversion element in this embodiment is formed by the same manufacturing method as in the first embodiment described above. That is, the n-type semiconductor layer 25n and the p-type semiconductor layer (not shown) in the present embodiment use the metal masks 110A and 110B shown in FIGS. 6B and 6C, the film formation pressure, the thickness M of the metal mask 110, and the metal mask. It can be formed by appropriately adjusting the opening width O of 110 or the like.
  • the passivation layer 13 in FIG. 1 is formed of a thermal oxide film of silicon has been described.
  • an intrinsic (i-type) amorphous material containing hydrogen is used as the passivation layer 13.
  • An example in which a high-quality semiconductor layer is used will be described.
  • the i-type amorphous semiconductor layer includes, for example, i-type amorphous silicon, i-type amorphous silicon germanium, i-type amorphous germanium, i-type amorphous silicon carbide, i-type amorphous silicon nitride, i-type amorphous silicon oxynitride, i-type amorphous silicon oxide, i-type amorphous silicon carbon oxide, or the like may be used.
  • the thickness of the i-type amorphous semiconductor layer is, for example, 1 to 10 nm.
  • p formed on the i-type amorphous semiconductor layer is formed. Impurities such as boron contained in the type semiconductor layer 15p can be prevented from diffusing into the silicon substrate 11.
  • the i-type amorphous semiconductor layer can reduce defects at the interface between the silicon substrate 11 and the n-type semiconductor layer 15n and the interface between the silicon substrate 11 and the p-type semiconductor layer 15p.
  • an i-type amorphous silicon layer is formed as the passivation layer 13 in the first embodiment.
  • the i-type amorphous silicon layer may be formed before the ARC 12 is formed, or may be formed after the ARC 12 is formed.
  • the ARC 12 may have a three-layer structure in which an i-type amorphous silicon layer (for example, 5 nm), an n-type amorphous silicon layer (for example, 8 nm), and a silicon nitride film (for example, 60 nm) are stacked in this order.
  • an amorphous silicon semiconductor layer (i-type amorphous silicon layer and n-type amorphous silicon layer) is formed on the light receiving surface of the silicon substrate 11 by using, for example, plasma CVD.
  • ammonia gas is added as a reaction gas to form a silicon nitride film made of silicon nitride or oxynitride (SiN, SiON).
  • SiN, SiON silicon nitride film made of silicon nitride or oxynitride
  • the silicon substrate 11 is inverted in a vacuum state in the reaction chamber of the plasma CVD apparatus, and the i-type amorphous silicon layer is formed as the passivation layer 13 on the back surface of the silicon substrate 11.
  • the i-type amorphous silicon layer is formed on substantially the entire back surface of the silicon substrate 11 using plasma CVD.
  • the reaction gas introduced into the reaction chamber provided in the plasma CVD apparatus is silane gas and hydrogen gas.
  • the hydrogen gas flow rate is 0 to 100 sccm
  • the silane gas flow rate is 40 sccm.
  • the temperature of the silicon substrate 11 is 130 to 180 ° C.
  • the pressure in the reaction chamber is 40 to 120 Pa, and the RF power density is 5 to 15 mW / cm 2 .
  • the film thickness of the i-type amorphous silicon layer formed on substantially the entire back surface of the silicon substrate 11 is, for example, 8 nm.
  • the film thickness of the i-type amorphous silicon layer is preferably about 2 to 20 nm, more preferably about 3 to 12 nm.
  • the metal mask 110 is disposed at an appropriate position on the passivation layer 13 in a vacuum state in the reaction chamber of the plasma CVD apparatus. Then, the n-type and p-type semiconductor layers 15n and 15p and the n-type and p-type electrodes 16n and 16p are sequentially formed under the same film formation conditions as in the first embodiment. By doing in this way, a photoelectric conversion element can be produced in a vacuum atmosphere.
  • an i-type amorphous silicon layer can be formed as the passivation layer 13 on the substantially entire back surface of the silicon substrate 11 by a single film formation. Therefore, although the in-plane distribution is slightly generated, the back surface of the silicon substrate 11 can be covered with a substantially uniform film thickness and can be passivated.
  • the semiconductor layers (n-type semiconductor layer 15n and p-type semiconductor layer 15p) having the film thickness reduction region T are formed on the substantially uniform passivation film 13 so as to reduce the film thickness. Electrodes (n-type electrode 16n and p-type electrode 16p) are formed on region T. Such a configuration is more preferable because it can achieve both passivation properties and low resistance at the interface of the silicon substrate 11.
  • FIG. 12 is a schematic view showing a cross section of the photoelectric conversion element 100 according to this embodiment.
  • FIG. 13 is an enlarged schematic view of a region where the n-type semiconductor layer 15n shown in FIG. 12 is formed.
  • symbol same as 1st Embodiment is attached
  • a passivation layer 131 made of the same i-type amorphous silicon layer as the passivation layer 13 is formed on the passivation layer 13 at a position where the n-type semiconductor layer 15n and the p-type semiconductor layer 15p are formed.
  • the passivation layer 13 is referred to as a first passivation layer 13 and the passivation layer 131 is referred to as a second passivation layer 131.
  • the n-type semiconductor layer 15n has a film thickness reduction region T
  • the second passivation layer 131 formed under the n-type semiconductor layer 15n also has a film thickness reduction region t.
  • the p-type semiconductor layer 15p similarly has a film thickness reduction region T
  • the second passivation layer 131 formed under the p-type semiconductor layer 15p also has a film thickness reduction region t. .
  • the first passivation layer 13 made of an i-type amorphous silicon layer is formed on substantially the entire back surface of the silicon substrate 11 using plasma CVD.
  • the film thickness of the first passivation layer 13 is about 5 nm.
  • a metal mask 110 ⁇ / b> D (not shown) is disposed on the first passivation layer 13.
  • the metal mask 110D has an opening and is disposed on the first passivation layer 13 so that the opening is located in a portion where the n-type semiconductor layer 15n is formed.
  • a second passivation layer 131 made of an i-type amorphous silicon layer is formed, and then an n-type semiconductor layer 15n made of an n-type amorphous silicon layer is formed.
  • the metal mask 110D is removed, and a metal mask 110E (not shown) covering the n-type semiconductor layer 15n is disposed on the silicon substrate 11.
  • the metal mask 110E has an opening, and is arranged such that the opening is located in a portion where the p-type semiconductor layer 15p is formed.
  • a second passivation layer 131 made of an i-type amorphous silicon layer is formed, and then a p-type semiconductor layer 15p made of a p-type amorphous silicon layer is formed.
  • the width in the in-plane direction of the n-type semiconductor layer 15n is, for example, about 400 ⁇ m, and the width in the in-plane direction of the p-type semiconductor layer 15p is, for example, about 1200 ⁇ m.
  • the film thickness of the second passivation layer 131 formed under the n-type semiconductor layer 15n is, for example, about 1 nm, and the film thickness of the n-type semiconductor layer 15n is, for example, about 13 nm.
  • the film thickness of the second passivation layer 131 formed under the p-type semiconductor layer 15p is, for example, about 3 nm, and the film thickness of the p-type semiconductor layer 15p is, for example, about 15 nm.
  • the thickness of the first passivation layer 13 is about 5 nm.
  • the width of the film thickness reduction region T in the semiconductor layer and the amount of film thickness reduction vary depending on the opening width of the metal mask.
  • n-type amorphous silicon is used for the silicon substrate 11, it is important to reduce the resistance of the n-type semiconductor layer 15n. Therefore, it is preferable that the width of the film thickness reduction region T of the n-type semiconductor layer 15n is larger than the width of the film thickness reduction region T of the p-type semiconductor layer 15p.
  • the width of the thickness reduction region T of the p-type semiconductor layer 15p is larger than the width of the thickness reduction region T of the n-type semiconductor layer 15n. Is preferably large.
  • the second passivation layer 131 also has the film thickness reduction region t, the film thickness in the portion of the film thickness reduction region t becomes thinner compared to the case where the second passivation layer 131 does not have the film thickness reduction region t. Therefore, the resistance can be further reduced.
  • the thickness (about 1 nm) of the second passivation layer 131 formed below the n-type semiconductor layer 15n and the thickness of the p-type semiconductor layer 15p are larger than the thickness (about 5 nm) of the first passivation layer 13.
  • the film thickness (about 3 nm) of the second passivation layer 131 formed below is thinner.
  • the total film thickness of the first passivation layer 13 and the second passivation layer 131 is 10 nm, and the ratio (H1 / H2) of the film thickness H1 of the first passivation layer 13 to the film thickness H2 of the second passivation layer 131 is changed. Conversion efficiency was measured.
  • FIG. 14 is a diagram showing the ratio of film thicknesses (H1 / H2) between the first passivation layer 13 and the second passivation layer 131 and the measurement result of the photoelectric conversion efficiency.
  • the photoelectric conversion efficiency is 24.0% or more, and when the film thickness ratio is 0.25, the photoelectric conversion efficiency is 22.3%. It became low. Thereby, the photoelectric conversion efficiency is not determined by the total film thickness of the first passivation layer 13 and the second passivation layer 131, but the film thickness of the first passivation layer 13 is larger than the film thickness of the second passivation layer 131. It can be seen that the photoelectric conversion characteristics are improved.
  • the n-type semiconductor is used.
  • the thickness of the second passivation layer 131 is made larger than that of the first passivation layer 13. It is preferable to reduce the thickness.
  • a film thickness reduction region is also formed in the second passivation layer 131 formed under the n-type semiconductor layer 15n. From the viewpoint of reducing resistance, it is more preferable.
  • the film thickness reduction region T in at least one of the n-type semiconductor layer 15n and the p-type semiconductor layer 15p has a film thickness from the center of the semiconductor layer toward the outside.
  • region may be comprised as follows.
  • FIG. 15 is a schematic view showing a cross section of the photoelectric conversion element according to the present embodiment.
  • at least one of the n-type and p-type semiconductor layers 15 n and 15 p in the photoelectric conversion element 101 is a film thickness decreasing region from the point Cm at which the film thickness is maximum toward the inside of each semiconductor layer.
  • a region T2 where the film thickness decreases is provided.
  • the film thickness reduction region T2 is a point Cn (second point) at which the sign of the rate of change of film thickness changes from negative to positive in the in-plane direction of the semiconductor layer from the point Cm (first point) at which the film thickness becomes maximum. This is the area up to point).
  • the point where the film thickness is maximum in one thin film formed on the silicon substrate 11 is the first point, and the film thickness reduction rate is the first in the in-plane direction of the thin film.
  • the second point is that the rate of change from the rate of 1 changes to a second rate of decrease that is greater than the first rate of decrease or the sign of the rate of change of film thickness changes from negative to positive in the in-plane direction of the thin film. Is the region from the first point to the second point in the in-plane direction of the thin film.
  • the n-type semiconductor layer 15n and the p-type semiconductor layer 15p are covered so as to be separated from each other on the n-type electrode 16n and the p-type electrode 16p.
  • a film 17 is formed.
  • the insulating film 17 for example, an oxide film such as Si, Al, Ti, zirconia, an inorganic insulating film such as a nitride film of Si or Al, or an oxynitride film of Si or Al may be used.
  • the insulating film 17 may be an organic material such as an imide resin, an epoxy resin, a fluororesin, a polycarbonate, or a liquid crystal polymer.
  • the imide resin may be polyimide, for example.
  • the fluororesin for example, polytetrafluoroethylene (PTFE) may be used.
  • the insulating film 17 may be formed by forming a resist by screen printing, or using a silicon resin or the like.
  • FIG. 16B is an enlarged schematic view of a part of the wiring sheet in the present embodiment.
  • the wiring sheet 200 is configured by forming wiring members 202 a and 202 b on an insulating base material 201.
  • the insulating base material 201 may be any insulating material, and for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyphenylene sulfide (PPS), polyvinyl fluoride (PVF), polyimide, or the like may be used.
  • the thickness of the insulating substrate 201 is not particularly limited, but is preferably about 25 ⁇ m or more and 150 ⁇ m or less.
  • the insulating base 201 may have a single layer structure or a multilayer structure of two or more layers.
  • the wiring members 202a and 202b may be any conductive material, and may be any metal such as Cu, Al, or Ag, or an alloy containing any one of these metals as a main component. Good.
  • the film thickness of the wiring members 202a and 202b is not particularly limited, but is preferably 10 ⁇ m or more and 80 ⁇ m or less, for example. When the thickness of the wiring members 202a and 202b is 10 ⁇ m or less, the wiring resistance may increase. Moreover, when it becomes 80 micrometers or more, it is necessary to apply heat when bonding the wiring sheet 200 and the photoelectric conversion element 101 together.
  • the film thickness of the wiring materials 202a and 202b is more preferably 80 ⁇ m or less.
  • a conductive material such as nickel, gold, platinum, palladium, silver, tin, indium, or ITO may be formed on part of the surface of the wiring members 202a and 202b.
  • the wiring members 202a and 202b may have a single layer structure or a multilayer structure of two or more layers.
  • the shape of the wiring sheet 200 and the patterns of the wiring materials 202a and 202b are not limited to those shown in FIG. 16B.
  • the wiring members 202 a and 202 b of the wiring sheet 200 are joined to the n-type electrode 16 n and the p-type electrode 16 p formed on the back surface of the photoelectric conversion element 102.
  • the wiring material 202a in the broken line frame 200A shown in FIG. 16B is joined to the p-type electrode 16p of the photoelectric conversion element 101, and the wiring material 202b is joined to the n-type electrode 16n of the photoelectric conversion element 102.
  • the wiring material 202a in the broken line frame 200B is joined to the n-type electrode 16n of the photoelectric conversion element 101, and the wiring material 202b is joined to the p-type electrode 16p. That is, in FIG. 16B, each electrode of the same conductivity type of the photoelectric conversion element 102 adjacent in the Y-axis direction is joined to a different wiring material.
  • each photoelectric conversion element 102 is electrically connected in series. Thereby, the electric current generated by the incidence of sunlight on the photoelectric conversion element 102 can be output to the outside through the wiring members 202a and 202b in the wiring sheet 200.
  • the method of joining the n-type electrode 16n and the p-type electrode 16p of the photoelectric conversion element 102 and the wiring members 202a and 202b of the wiring sheet 200 is not particularly limited, but the following method can be used.
  • ACF Anisotropic Conductive Film
  • ACP Anisotropic Conductive Paste
  • NCP Non Inductive Paste
  • TCAP-5401-27 manufactured by Tamura Kaken Co., Ltd. may be used as the solder resin.
  • the insulating adhesive any of an epoxy resin, an acrylic resin, a urethane resin, or the like may be used, or a thermosetting or photocurable resin may be used.
  • the conductive adhesive may use solder particles containing at least one of tin and bismuth. More preferably, it is an alloy of tin and any of bismuth, indium, silver and the like. With this configuration, the melting point of solder can be suppressed, and an adhesion process at a low temperature becomes possible.
  • the photoelectric conversion element 102 is formed on the n-type semiconductor layer 15n and the p-type semiconductor layer 15p, which are amorphous semiconductor layers, and the n-type electrode 16n and the p-type electrode 16p.
  • An insulating film 17 is formed. That is, the insulating film 17 exists on the amorphous semiconductor layer and on the n-type electrode 16n and the p-type electrode 16p, and the base on which the insulating film 17 is formed is different.
  • the insulating film 17 having a different base may be peeled off due to a difference in thermal expansion coefficient of the base due to heat generated by the bonding process. Therefore, in particular, a bonding process at 200 ° C.
  • thermosetting silver paste a low-temperature effect type copper paste, an anisotropic conductive film, an anisotropic conductive paste, etc. that can be cured and electrically bonded at a low temperature. It is preferable to use it.
  • the conductive adhesives When applying the conductive adhesive on the n-type electrode 16n and the p-type electrode 16p, the conductive adhesives are spatially separated from each other so that adjacent conductive adhesives are not short-circuited. Insulate. At this time, the conductive adhesive is applied so as not to hinder conduction between the wiring sheet 200 and the photoelectric conversion element 102.
  • the conductive adhesive For patterning the conductive adhesive, screen printing or the like may be used. In the case of an anisotropic conductive film or anisotropic conductive paste, there is no need for patterning.
  • the adhesive force of the adhesive causes photoelectric conversion.
  • the conversion element 102 and the wiring sheet 200 are joined.
  • the temperature and heating time of the heat treatment vary depending on the type of the conductive adhesive, the n-type electrode 16n and the p-type electrode 16p, and the wiring materials 202a and 202b, but may be about 120 to 220 ° C.
  • the temperature of the heat treatment in this embodiment is 150 ° C., and the heating time is about several minutes to 1 hour.
  • the conductive adhesive is formed at least on the opening region F of the insulating film 17 in the photoelectric conversion element 102 (see FIG. 16A). In addition, since the electrical insulation is maintained by the insulating film 17, a conductive adhesive may be formed outside the opening region F.
  • the region covered with the insulating film 17 is wide. Insulation with respect to the width X in the in-plane direction of the n-type electrode 16n and the p-type electrode 16p (see FIG. 16A) More preferably, the sum of the widths J1 and J2 (see FIG. 16A) of the regions on both sides of the opening region F of the film 17 is 30% or more. In consideration of the likelihood of the manufacturing process, it is preferable that the opening region F of the insulating film 17 is provided in the vicinity of the approximate center of the n-type electrode 16n and the p-type electrode 16p.
  • the photoelectric conversion element with a wiring sheet in which the wiring sheet 200 and the photoelectric conversion element 102 are joined is composed of a glass substrate on which an ethylene vinyl acetate resin (EVA resin) is formed and a PET on which an EVA resin is formed. Arranged between the film. Then, the EVA resin on the glass substrate side is vacuum bonded to the photoelectric conversion element with a wiring sheet. In addition, the EVA resin on the PET film side is cured by heating to 125 ° C. in a state where it is vacuum-pressurized to the photoelectric conversion element with a wiring sheet. By doing in this way, the photoelectric conversion element with a wiring sheet is sealed in EVA resin hardened between a glass substrate and a PET film, and a solar cell module is produced.
  • EVA resin ethylene vinyl acetate resin
  • FIG. 17A is a cross-sectional view of a photoelectric conversion element 400 manufactured using a silicon substrate 401 having a texture structure formed on both sides.
  • the same reference numerals as those in the first embodiment are given to the same configurations as those in the first embodiment.
  • the photoelectric conversion element 400 is manufactured by the steps shown in FIGS. 6A to 6D described above using a wafer having a texture structure formed on both sides.
  • FIG. 17B is a view showing an SEM (Scanning Electron Microscopy) photograph of the surface of the silicon substrate 401.
  • FIG. 17B (a) shows an SEM photograph in the case where the length of the base of the pyramid constituting the texture structure is 2 ⁇ m or less
  • FIG. 17B (b) shows the length of the base of the pyramid is 10 ⁇ m or less.
  • the SEM photograph of the case is shown.
  • (c) of FIG. 17B has shown the SEM photograph in case the length of the base of a pyramid is about 15 micrometers.
  • a p-type semiconductor layer 15p and an n-type semiconductor layer 15n were formed on the back surface of the silicon substrate 401 on which both types of texture structures shown in FIGS. 17B (a), (b), and (c) were formed.
  • the p-type semiconductor layer 15p and the n-type semiconductor layer 15n have a film thickness reduction region T as in the above-described embodiment.
  • the silicon substrate 401 having a texture structure formed on both sides is used, the effect of passivation and low resistance can be obtained by having the film thickness reduction region T.
  • a p-type semiconductor layer 15p and / or an n-type semiconductor layer 15n having a film thickness reduction region T is formed on the back surface of the silicon substrate 401 having a texture structure, and TCO (Transparent Conductive Oxide) and / or Alternatively, when the electrode 16 is formed, an effect of improving the adhesion with the semiconductor layer is obtained by an anchor effect or the like due to the uneven shape. Therefore, in order to improve the long-term reliability of the solar cell, it is preferable that the texture is formed on both sides of the silicon substrate.
  • photoelectric conversion element 400 is modularized using the wiring sheet 200. Further, the silicon substrate used in the photoelectric conversion element according to the present embodiment may be used in the other embodiments described above.
  • FIG. 18 is a schematic diagram illustrating a configuration of a photoelectric conversion module according to the present embodiment.
  • the photoelectric conversion module 1000 includes a plurality of photoelectric conversion elements 1001, a cover 1002, and output terminals 1003 and 1004.
  • the plurality of photoelectric conversion elements 1001 are, for example, arranged in an array on the wiring sheet 200 according to the sixth embodiment and connected in series. Instead of connecting in series, parallel connection or a combination of series and parallel may be performed.
  • the cover 1002 is made of a weather resistant cover and covers the plurality of photoelectric conversion elements 1001.
  • the cover 1002 includes, for example, a transparent base material (for example, glass) provided on the light receiving surface side of the photoelectric conversion element 1001 and a back surface base material (on the reverse side opposite to the light receiving surface side of the photoelectric conversion element 1001).
  • a transparent base material for example, glass
  • a back surface base material on the reverse side opposite to the light receiving surface side of the photoelectric conversion element 1001
  • glass, a resin sheet, etc. and the sealing material (for example, EVA etc.) which fills the clearance gap between the said transparent base material and the said resin base material are included.
  • the output terminal 1003 is connected to a photoelectric conversion element 1001 with a wiring sheet disposed at one end of a plurality of photoelectric conversion elements 1001 connected in series.
  • the output terminal 1004 is connected to the photoelectric conversion element 1001 disposed at the other end of the plurality of photoelectric conversion elements 1001 connected in series.
  • the photoelectric conversion elements 1 and 100 to 102 according to the first to fifth embodiments described above and the photoelectric conversion element 400 according to the seventh embodiment have improved element characteristics. Therefore, the performance of the photoelectric conversion module 1000 can be improved.
  • the photoelectric conversion module according to the present embodiment is not limited to the configuration shown in FIG. 18, but any configuration as long as any one of the photoelectric conversion elements according to the first to fifth embodiments and the seventh embodiment is used. It may be.
  • FIG. 19A is a schematic diagram illustrating a configuration of a photovoltaic power generation system according to the present embodiment.
  • the photovoltaic power generation system 1100 includes a photoelectric conversion module array 1101, a connection box 1102, a power conditioner 1103, a distribution board 1104, and a power meter 1105.
  • Functions such as “Home Energy Management System (HEMS)” and “Building Energy Management System (BEMS)” are added to the photovoltaic power generation system 1100.
  • HEMS Home Energy Management System
  • BEMS Building Energy Management System
  • connection box 1102 is connected to the photoelectric conversion module array 1101.
  • the power conditioner 1103 is connected to the connection box 1102.
  • Distribution board 1104 is connected to power conditioner 1103 and electrical equipment 1110.
  • the power meter 1105 is connected to the distribution board 1104 and system linkage.
  • the photoelectric conversion module array 1101 converts sunlight into electricity to generate DC power, and supplies the generated DC power to the connection box 1102.
  • connection box 1102 receives the DC power generated by the photoelectric conversion module array 1101 and supplies the received DC power to the power conditioner 1103.
  • the power conditioner 1103 converts the DC power received from the connection box 1102 into AC power, and supplies the converted AC power to the distribution board 1104.
  • Distribution board 1104 supplies AC power received from power conditioner 1103 and / or commercial power received via power meter 1105 to electrical equipment 1110. Further, when the AC power received from the power conditioner 1103 is larger than the power consumption of the electrical equipment 1110, the distribution board 1104 supplies the surplus AC power to the system linkage via the power meter 1105.
  • the power meter 1105 measures the power in the direction from the grid connection to the distribution board 1104 and measures the power in the direction from the distribution board 1104 to the grid cooperation.
  • FIG. 20 is a schematic diagram showing the configuration of the photoelectric conversion module array 1101 shown in FIG. 19A.
  • photoelectric conversion module array 1101 includes a plurality of photoelectric conversion modules 1120 and output terminals 1121 and 1122.
  • the plurality of photoelectric conversion modules 1120 are arranged in an array and connected in series. Each of the plurality of photoelectric conversion modules 1120 includes a photoelectric conversion module 1000 shown in FIG.
  • the output terminal 1121 is connected to a photoelectric conversion module 1120 located at one end of a plurality of photoelectric conversion modules 1120 connected in series.
  • the output terminal 1122 is connected to the photoelectric conversion module 1120 located at the other end of the plurality of photoelectric conversion modules 1120 connected in series.
  • the photoelectric conversion module array 1101 generates sunlight by converting sunlight into electricity, and supplies the generated DC power to the power conditioner 1103 via the connection box 1102.
  • the power conditioner 1103 converts the DC power received from the photoelectric conversion module array 1101 into AC power, and supplies the converted AC power to the distribution board 1104.
  • the distribution board 1104 supplies the AC power received from the power conditioner 1103 to the electrical device 1110 when the AC power received from the power conditioner 1103 is greater than or equal to the power consumption of the electrical device 1110. Then, the distribution board 1104 supplies surplus AC power to the system linkage via the power meter 1105.
  • distribution board 1104 supplies AC power received from grid cooperation and AC power received from power conditioner 1103 to electrical equipment 1110 when the AC power received from power conditioner 1103 is less than the power consumption of electrical equipment 1110. To do.
  • the photovoltaic power generation system 1100 includes any one of the photoelectric conversion elements according to the first to fifth embodiments and the seventh embodiment in which element characteristics are improved. Therefore, the performance of the photovoltaic power generation system 1100 can be improved.
  • the photovoltaic power generation system according to the present embodiment is not limited to the configuration illustrated in FIGS. 19A and 20, and as long as any one of the photoelectric conversion elements according to the first to fifth embodiments and the seventh embodiment is used. Such a configuration may be adopted.
  • a storage battery 1106 may be connected to the power conditioner 1103. In this case, output fluctuation due to fluctuations in the amount of sunlight can be suppressed, and power stored in the storage battery 1106 can be supplied even in a time zone without sunlight.
  • the storage battery 1106 may be built in the power conditioner 1103.
  • FIG. 21A is a schematic diagram illustrating a configuration of a photovoltaic power generation system according to the present embodiment.
  • the photovoltaic power generation system 1200 includes subsystems 1201 to 120n (n is an integer of 2 or more), power conditioners 1211 to 121n, and a transformer 1221.
  • the photovoltaic power generation system 1200 is a photovoltaic power generation system having a larger scale than the photovoltaic power generation system 1100 shown in FIGS. 19A and 19B.
  • the power conditioners 1211 to 121n are connected to the subsystems 1201 to 120n, respectively.
  • the transformer 1221 is connected to the power conditioners 1211 to 121n and the system linkage.
  • Each of the subsystems 1201 to 120n includes module systems 1231 to 123j (j is an integer of 2 or more).
  • Each of the module systems 1231 to 123j includes photoelectric conversion module arrays 1301 to 130i (i is an integer of 2 or more), connection boxes 1311 to 131i, and a current collection box 1321.
  • Each of the photoelectric conversion module arrays 1301 to 130i has the same configuration as the photoelectric conversion module array 1101 shown in FIG.
  • connection boxes 1311 to 131i are connected to the photoelectric conversion module arrays 1301 to 130i, respectively.
  • the current collection box 1321 is connected to the connection boxes 1311 to 131i. Also, j current collection boxes 1321 of the subsystem 1201 are connected to the power conditioner 1211. The j current collection boxes 1321 of the subsystem 1202 are connected to the power conditioner 1212. Hereinafter, similarly, j current collection boxes 1321 of the subsystem 120n are connected to the power conditioner 121n.
  • the i photoelectric conversion module arrays 1301 to 130i of the module system 1231 generate sunlight by converting sunlight into electricity, and the generated DC power is collected through the connection boxes 1311 to 131i, respectively.
  • the i photoelectric conversion module arrays 1301 to 130i of the module system 1232 generate sunlight by converting sunlight into electricity, and the generated DC power is collected through the connection boxes 1311 to 131i, respectively.
  • the i photoelectric conversion module arrays 1301 to 130i of the module system 123j convert sunlight into electricity to generate DC power, and the generated DC power is connected to the connection boxes 1311 to 131i, respectively. To the current collection box 1321.
  • the j current collection boxes 1321 of the subsystem 1201 supply DC power to the power conditioner 1211.
  • the j current collection boxes 1321 of the subsystem 1202 supply DC power to the power conditioner 1212 in the same manner.
  • the j current collecting boxes 1321 of the subsystem 120n supply DC power to the power conditioner 121n.
  • the power conditioners 1211 to 121n convert the DC power received from the subsystems 1201 to 120n into AC power, and supply the converted AC power to the transformer 1221.
  • the transformer 1221 receives AC power from the power conditioners 1211 to 121n, converts the voltage level of the received AC power, and supplies it to the system linkage.
  • the photovoltaic power generation system 1200 includes any one of the photoelectric conversion elements according to the first to fifth embodiments having improved element characteristics. Therefore, the performance of the photovoltaic power generation system 1200 can be improved.
  • the photovoltaic power generation system according to this embodiment is not limited to the configuration illustrated in FIG. 21A, but any type of photoelectric conversion element according to the first to fifth embodiments and the seventh embodiment is used. It may be a configuration.
  • a storage battery 1213 may be connected to the power conditioners 1211 to 121n, or the storage battery 1213 may be built in the power conditioners 1211 to 121n.
  • the power conditioners 1211 to 121n can appropriately convert part or all of the direct-current power received from the current collection box 1321, and store it in the storage battery 1213.
  • the electric power stored in the storage battery 1213 is appropriately supplied to the power conditioners 1211 to 121n according to the power generation amount of the subsystems 1201 to 120n, and is appropriately converted into electric power and supplied to the transformer 1221.
  • the silicon substrates 11 and 401 may be made of n-type single crystal silicon or p-type single crystal silicon. Further, it may be made of n-type polycrystalline silicon or p-type polycrystalline silicon. When the silicon substrates 11 and 401 are made of n-type polycrystalline silicon or p-type polycrystalline silicon, the silicon substrates 11 and 401 have a light-receiving surface or a texture such as a honeycomb texture using dry etching on the light-receiving surface and the back surface. Processed into a structure.
  • the ARC 12 is formed on the light receiving surfaces of the silicon substrates 11 and 401 has been described, but the ARC 12 may not be formed. Further, instead of the ARC 12, an n + layer in which a high concentration n-type dopant is diffused may be formed. Alternatively, an n + layer in which a high concentration n-type dopant is diffused may be formed between the light receiving surface of the silicon substrate 11 and the ARC 12.
  • the amorphous semiconductor layer is formed using the plasma CVD method.
  • CatCVD Catalytic Chemical Vapor Deposition
  • An amorphous semiconductor layer may be formed using a method.
  • the film formation conditions are, for example, the temperature of the silicon substrate 11 of 100 to 300 ° C., the film formation pressure of 10 to 500 Pa, and the temperature of the thermal catalyst (when tungsten is used as the thermal catalyst) 1500.
  • the RF power density may be set to 0.01 to 1 W / cm 2 at ⁇ 2000 ° C.
  • a high-quality amorphous semiconductor layer can be formed at a relatively low temperature and in a short time.
  • the flat region L may not be formed in the n-type semiconductor layer 15n and the p-type semiconductor layer 15p.

Abstract

Provided is a photoelectric conversion element with which it is possible to reduce the number of series resistance components and improve photoelectric conversion efficiency. The photoelectric conversion element 1 is provided with: a semiconductor substrate 11; a first amorphous semiconductor layer 15n having a first conductor type formed on one surface of the semiconductor substrate 11; a second amorphous semiconductor layer 15p having a second conductor type and formed adjacent to the first amorphous semiconductor layer 15n in the in-plane direction of the semiconductor substrate 11; a first electrode 16n formed on the first amorphous semiconductor layer 15n; and a second electrode 16p formed on the second amorphous semiconductor layer 15p. At least one semiconductor layer among the first amorphous semiconductor layer 15n and the second amorphous semiconductor layer 15p has a film thickness reduction region, and at least one portion of an electrode formed on at least one of the semiconductor layers is formed contiguous to the film thickness reduction region. The film thickness reduction region extends from a first point to a second point in the in-plane direction of the semiconductor layer, where the first point is the point of the maximum film thickness, and the second point is either the point where the reduction rate of the film thickness in the in-plane direction of the semiconductor layer changes from a first reduction rate to a second reduction rate greater than the first reduction rate, or the point where the rate of change of the film thickness of the semiconductor layer in the in-plane direction of the semiconductor layer changes from negative to positive.

Description

光電変換素子Photoelectric conversion element
　本発明は、光電変換素子に関する。 The present invention relates to a photoelectric conversion element.
　近年、光電変換素子としての太陽電池が注目されている。特開２０１２－２８７１８号公報には、ｎ型の結晶シリコン基板とｐ型の非晶質シリコン層との間に、真性（ｉ型）非晶質シリコンを介在させた裏面接合型太陽電池が開示されている。真性非晶質シリコンを介在させることによって、パッシベーション性が向上し、ｎ型結晶シリコン基板とｐ型非晶質シリコン層の界面におけるキャリアの再結合が抑制され、光電変換効率が向上する。 In recent years, solar cells as photoelectric conversion elements have attracted attention. Japanese Laid-Open Patent Publication No. 2012-28718 discloses a back junction solar cell in which intrinsic (i-type) amorphous silicon is interposed between an n-type crystalline silicon substrate and a p-type amorphous silicon layer. Has been. By interposing the intrinsic amorphous silicon, the passivation property is improved, the recombination of carriers at the interface between the n-type crystalline silicon substrate and the p-type amorphous silicon layer is suppressed, and the photoelectric conversion efficiency is improved.
　特開２０１２－２８７１８号公報のように、ｎ型結晶シリコン基板とｐ型非晶質シリコン層との間に、真性非晶質シリコン等のパッシベーション膜を設けることによってパッシベーション性を向上させることができるが、一方で直列抵抗成分が高くなり、光電変換効率が低下する。 As disclosed in JP 2012-28718 A, a passivation film such as intrinsic amorphous silicon can be provided between the n-type crystalline silicon substrate and the p-type amorphous silicon layer to improve the passivation property. However, on the other hand, the series resistance component becomes high and the photoelectric conversion efficiency decreases.
　本発明の目的は、直列抵抗成分を低減し、光電変換効率を向上可能な光電変換素子を提供することを目的とする。 An object of the present invention is to provide a photoelectric conversion element capable of reducing the series resistance component and improving the photoelectric conversion efficiency.
　本発明に係る光電変換素子は、半導体基板と、前記半導体基板の一方の面上に形成された第１導電型を有する第１非晶質半導体層と、前記半導体基板の一方の面上に形成され、かつ前記半導体基板の面内方向において前記第１非晶質半導体層に隣接して形成され、前記第１導電型と反対の第２導電型を有する第２非晶質半導体層と、前記第１非晶質半導体層の上に形成された第１電極と、前記第２非晶質半導体層の上に形成された第２電極とを備え、前記半導体基板上に成膜された一の薄膜において、膜厚が最大である点を第１の点とし、当該一の薄膜の面内方向において当該薄膜の膜厚の減少率が第１の減少率から前記第１の減少率よりも大きい第２の減少率に変化する点、または当該一の薄膜の面内方向において当該一の薄膜の膜厚の変化率の符号が負から正に変化する点を第２の点とし、当該一の薄膜の面内方向において前記第１の点から前記第２の点までの領域を膜厚減少領域と定義したとき、前記第１非晶質半導体層及び前記第２非晶質半導体層の少なくとも一方の半導体層は、前記膜厚減少領域を有し、前記少なくとも一方の半導体層に形成された電極の少なくとも一部は、前記膜厚減少領域上に形成されている。 A photoelectric conversion element according to the present invention is formed on a semiconductor substrate, a first amorphous semiconductor layer having a first conductivity type formed on one surface of the semiconductor substrate, and one surface of the semiconductor substrate. And a second amorphous semiconductor layer formed adjacent to the first amorphous semiconductor layer in an in-plane direction of the semiconductor substrate and having a second conductivity type opposite to the first conductivity type; A first electrode formed on the first amorphous semiconductor layer; and a second electrode formed on the second amorphous semiconductor layer, the first electrode formed on the semiconductor substrate. In the thin film, the point where the film thickness is maximum is the first point, and the reduction rate of the thickness of the thin film is larger than the first reduction rate from the first reduction rate in the in-plane direction of the one thin film. The point of change of the second reduction rate, or the thickness of the one thin film in the in-plane direction of the one thin film The point where the sign of the conversion rate changes from negative to positive is defined as the second point, and the region from the first point to the second point in the in-plane direction of the one thin film is defined as the film thickness reduction region. When at least one of the first amorphous semiconductor layer and the second amorphous semiconductor layer has the film thickness reduction region, at least one of the electrodes formed on the at least one semiconductor layer. The part is formed on the film thickness reduction region.
　本発明によれば、直列抵抗成分を低減し、光電変換効率を向上させることができる。 According to the present invention, the series resistance component can be reduced and the photoelectric conversion efficiency can be improved.
図１は、第１実施形態に係る光電変換素子を模式的に示す断面図である。FIG. 1 is a cross-sectional view schematically showing the photoelectric conversion element according to the first embodiment. 図２は、図１に示す電極を拡大した模式図である。FIG. 2 is an enlarged schematic view of the electrode shown in FIG. 図３Ａは、図２に示すｎ型半導体層の膜厚を測定した結果を示す図である。FIG. 3A is a diagram showing the results of measuring the film thickness of the n-type semiconductor layer shown in FIG. 図３Ｂの（ａ）は、シリコン基板の表面の顕微鏡写真を示す図である。図３Ｂの（ｂ）は、図３Ｂの（ａ）に示すシリコン基板の表面の高さを測定した結果を示す図である。FIG. 3B is a diagram showing a micrograph of the surface of the silicon substrate. FIG. 3B (b) is a diagram showing the results of measuring the surface height of the silicon substrate shown in FIG. 3B (a). 図３Ｃの（ａ）は、シリコン基板上のパッシベーション膜とシリコン基板表面との界面から半導体層表面までの膜厚を測定した結果を例示した図である。図３Ｃの（ｂ）は、図３Ｃの（ａ）に示す各膜厚をプロットし直した結果を示す図である。(A) of FIG. 3C is the figure which illustrated the result of having measured the film thickness from the interface of the passivation film on a silicon substrate, and the silicon substrate surface to the semiconductor layer surface. FIG. 3C (b) is a diagram showing a result of re-plotting each film thickness shown in FIG. 3C (a). 図４は、隣接するｎ型半導体層とｐ型半導体層の膜厚減少領域が重なっている状態を示す断面図である。FIG. 4 is a cross-sectional view showing a state where the thickness reduction regions of adjacent n-type semiconductor layers and p-type semiconductor layers overlap. 図５は、ｎ型電極の構成を示す断面図である。FIG. 5 is a cross-sectional view showing the configuration of the n-type electrode. 図６Ａは、第１実施形態に係る光電変換素子の製造工程を説明する図である。FIG. 6A is a diagram illustrating a manufacturing process of the photoelectric conversion element according to the first embodiment. 図６Ｂは、第１実施形態に係る光電変換素子の製造工程を説明する図である。FIG. 6B is a diagram illustrating a manufacturing process of the photoelectric conversion element according to the first embodiment. 図６Ｃは、第１実施形態に係る光電変換素子の製造工程を説明する図である。FIG. 6C is a diagram illustrating a manufacturing process of the photoelectric conversion element according to the first embodiment. 図６Ｄは、第１実施形態に係る光電変換素子の製造工程を説明する図である。FIG. 6D is a diagram illustrating a manufacturing process of the photoelectric conversion element according to the first embodiment. 図７は、メタルマスクの厚さ及び開口幅と、膜厚減少領域及びテーパー形状領域との関係を説明する図である。FIG. 7 is a diagram for explaining the relationship between the thickness and opening width of the metal mask, the film thickness reduction region, and the tapered region. 図８は、ｎ型電極の両端部の位置が各々異なる４つの電極の断面図である。FIG. 8 is a cross-sectional view of four electrodes having different positions at both ends of the n-type electrode. 図８に示す各電極の直列抵抗成分と開放電圧とを測定した結果を示す図である。It is a figure which shows the result of having measured the serial resistance component and open circuit voltage of each electrode shown in FIG. 図１０は、第２実施形態に係る光電変換素子の電極の断面図である。FIG. 10 is a cross-sectional view of the electrode of the photoelectric conversion element according to the second embodiment. 図１１は、図１０に示すｎ型半導体層の膜厚を測定した結果を示す図である。FIG. 11 is a diagram showing the results of measuring the film thickness of the n-type semiconductor layer shown in FIG. 図１２は、第４実施形態に係る光電変換素子の断面図である。FIG. 12 is a cross-sectional view of the photoelectric conversion element according to the fourth embodiment. 図１３は、図１２に示す電極が形成された領域を拡大した模式図である。FIG. 13 is an enlarged schematic view of a region where the electrode shown in FIG. 12 is formed. 図１４は、第１パッシベーション層と第２パッシベーション層の膜厚の比率）とその光電変換効率の測定結果とを示す図である。FIG. 14 is a diagram illustrating the ratio of the thickness of the first passivation layer and the second passivation layer) and the measurement result of the photoelectric conversion efficiency. 図１５は、第５実施形態に係る光電変換素子の断面図である。FIG. 15 is a cross-sectional view of the photoelectric conversion element according to the fifth embodiment. 図１６Ａは、第６実施形態に係る光電変換素子の断面図である。FIG. 16A is a cross-sectional view of the photoelectric conversion element according to the sixth embodiment. 図１６Ｂは、第６実施形態における配線シートの一部を拡大した模式図である。FIG. 16B is an enlarged schematic view of a part of the wiring sheet in the sixth embodiment. 図１７Ａは、第７実施形態に係る光電変換素子の断面図である。FIG. 17A is a cross-sectional view of the photoelectric conversion element according to the seventh embodiment. 図１７Ｂは、図１７Ａに示すシリコン基板の表面の顕微鏡写真を示す図である。FIG. 17B is a diagram showing a micrograph of the surface of the silicon substrate shown in FIG. 17A. 図１８は、第８実施形態に係る光電変換モジュールの構成を示す概略図である。FIG. 18 is a schematic diagram illustrating a configuration of a photoelectric conversion module according to the eighth embodiment. 図１９Ａは、第９実施形態による光電変換素子を備える太陽光発電システムの構成を示す概略図である。FIG. 19A is a schematic diagram illustrating a configuration of a photovoltaic power generation system including a photoelectric conversion element according to the ninth embodiment. 図１９Ｂは、図１９Ａに示す太陽光発電システムの他の構成例を示す概略図である。FIG. 19B is a schematic diagram illustrating another configuration example of the photovoltaic power generation system illustrated in FIG. 19A. 図２０は、図１９Ａに示す光電変換モジュールアレイの構成を示す概略図である。FIG. 20 is a schematic diagram illustrating a configuration of the photoelectric conversion module array illustrated in FIG. 19A. 図２１Ａは、第１０実施形態による光電変換素子を備える太陽光発電システムの構成を示す概略図である。FIG. 21A is a schematic diagram illustrating a configuration of a photovoltaic power generation system including a photoelectric conversion element according to the tenth embodiment. 図２１Ｂは、図２１Ａに示す太陽光発電システムの他の構成例を示す概略図である。FIG. 21B is a schematic diagram illustrating another configuration example of the photovoltaic power generation system illustrated in FIG. 21A.
　本発明の一実施形態に係る光電変換素子は、半導体基板と、前記半導体基板の一方の面上に形成された第１導電型を有する第１非晶質半導体層と、前記半導体基板の一方の面上に形成され、かつ前記半導体基板の面内方向において前記第１非晶質半導体層に隣接して形成され、前記第１導電型と反対の第２導電型を有する第２非晶質半導体層と、前記第１非晶質半導体層の上に形成された第１電極と、前記第２非晶質半導体層の上に形成された第２電極とを備え、前記半導体基板上に成膜された一の薄膜において、膜厚が最大である点を第１の点とし、当該一の薄膜の面内方向において当該薄膜の膜厚の減少率が第１の減少率から前記第１の減少率よりも大きい第２の減少率に変化する点、または当該一の薄膜の面内方向において当該一の薄膜の膜厚の変化率の符号が負から正に変化する点を第２の点とし、当該一の薄膜の面内方向において前記第１の点から前記第２の点までの領域を膜厚減少領域と定義したとき、前記第１非晶質半導体層及び前記第２非晶質半導体層の少なくとも一方の半導体層は、前記膜厚減少領域を有し、前記少なくとも一方の半導体層に形成された電極の少なくとも一部は、前記膜厚減少領域上に形成されている（第１の構成）。 A photoelectric conversion device according to an embodiment of the present invention includes a semiconductor substrate, a first amorphous semiconductor layer having a first conductivity type formed on one surface of the semiconductor substrate, and one of the semiconductor substrates. A second amorphous semiconductor formed on a surface and adjacent to the first amorphous semiconductor layer in an in-plane direction of the semiconductor substrate and having a second conductivity type opposite to the first conductivity type A layer, a first electrode formed on the first amorphous semiconductor layer, and a second electrode formed on the second amorphous semiconductor layer, and formed on the semiconductor substrate In the one thin film, the point where the film thickness is maximum is taken as a first point, and the reduction rate of the film thickness in the in-plane direction of the one thin film is changed from the first reduction rate to the first decrease. In the in-plane direction of the one thin film at the point of changing to a second reduction rate greater than the rate The point from which the sign of the rate of change of the film thickness changes from negative to positive is the second point, and the region from the first point to the second point in the in-plane direction of the one thin film is the film thickness. When defined as a reduced region, at least one of the first amorphous semiconductor layer and the second amorphous semiconductor layer has the reduced thickness region and is formed in the at least one semiconductor layer. At least a part of the electrodes is formed on the film thickness reduction region (first configuration).
　第１の構成によれば、第１非晶質半導体層と第２非晶質半導体層の少なくとも一方の半導体層において、膜厚減少領域を有する。膜厚減少領域を有する半導体層上に形成された電極の少なくとも一部は、膜厚減少領域の少なくとも一部に接して形成されている。膜厚減少領域の膜厚は、当該半導体層の第１の点における膜厚よりも薄いため、膜厚が均一な非晶質半導体層を設ける場合と比べ、直列抵抗成分を低減させることができる。 According to the first configuration, at least one of the first amorphous semiconductor layer and the second amorphous semiconductor layer has a thickness reduction region. At least a part of the electrode formed on the semiconductor layer having the film thickness reduction region is formed in contact with at least a part of the film thickness reduction region. Since the film thickness of the film thickness reduction region is smaller than the film thickness at the first point of the semiconductor layer, the series resistance component can be reduced as compared with the case where an amorphous semiconductor layer having a uniform film thickness is provided. .
　また、第２の構成に係る光電変換素子は、第１の構成において、前記膜厚減少領域を有する前記半導体層は、前記半導体基板と同じ導電型を有することとしてもよい。 Further, in the photoelectric conversion element according to the second configuration, in the first configuration, the semiconductor layer having the film thickness reduction region may have the same conductivity type as the semiconductor substrate.
　第２の構成によれば、半導体基板と同じ導電型の半導体層に膜厚減少領域が設けられているため、多数キャリアに対する直列抵抗成分をより低減することができる。 According to the second configuration, since the film thickness reduction region is provided in the semiconductor layer having the same conductivity type as the semiconductor substrate, the series resistance component with respect to majority carriers can be further reduced.
　また、第３の構成に係る光電変換素子は、第１又は第２の構成において、前記第１非晶質半導体層及び前記第２非晶質半導体層の各々は、前記膜厚減少領域を有し、隣接する前記第１非晶質半導体層と前記第２非晶質半導体層の前記膜厚減少領域は、離間して配置されていることとしてもよい。 In the photoelectric conversion element according to the third configuration, in the first or second configuration, each of the first amorphous semiconductor layer and the second amorphous semiconductor layer has the film thickness reduction region. In addition, the film thickness reduction regions of the adjacent first amorphous semiconductor layer and the second amorphous semiconductor layer may be arranged apart from each other.
　第３の構成によれば、第１非晶質半導体層と第２非晶質半導体層の膜厚減少領域とが重なって配置される場合と比べ、膜厚減少領域における膜厚が薄いため、直列抵抗成分を低減することができる。 According to the third configuration, since the film thickness in the film thickness reduction region is smaller than the case where the film thickness reduction region of the first amorphous semiconductor layer and the second amorphous semiconductor layer are arranged to overlap, The series resistance component can be reduced.
　また、第４の構成に係る光電変換素子は、第１から第３のいずれかの構成の前記膜厚減少領域を有する前記半導体層において、前記膜厚減少領域におけるドーパント濃度は、前記膜厚減少領域よりも膜厚が厚い領域のドーパント濃度より高いこととしてもよい。 In the photoelectric conversion element according to the fourth configuration, in the semiconductor layer having the film thickness reduction region of any one of the first to third configurations, the dopant concentration in the film thickness reduction region is the film thickness reduction. It is good also as higher than the dopant density | concentration of the area | region where a film thickness is thicker than an area | region.
　第４の構成によれば、膜厚減少領域を有する半導体層において、膜厚減少領域におけるドーパント濃度は、膜厚減少領域よりも膜厚が厚い領域のドーパント濃度よりも高い。そのため、膜厚減少領域における直列抵抗を低減できるとともに、膜厚減少領域を有する半導体層と、当該半導体層上に形成される電極との間のコンタクト抵抗を低減することができる。 According to the fourth configuration, in the semiconductor layer having the film thickness reduction region, the dopant concentration in the film thickness reduction region is higher than the dopant concentration in the region where the film thickness is thicker than the film thickness reduction region. Therefore, the series resistance in the film thickness reduction region can be reduced, and the contact resistance between the semiconductor layer having the film thickness reduction region and the electrode formed on the semiconductor layer can be reduced.
　また、第５の構成に係る光電変換素子は、第１から第４のいずれかの構成において、さらに、前記半導体基板と、前記第１非晶質半導体層及び前記第２非晶質半導体層との間に形成された第１パッシベーション膜を備えることとしてもよい。 Further, the photoelectric conversion element according to the fifth configuration is any one of the first to fourth configurations, and further includes the semiconductor substrate, the first amorphous semiconductor layer, and the second amorphous semiconductor layer. It is good also as providing the 1st passivation film formed between these.
　第５の構成によれば、直列抵抗成分の低減を図るとともに、半導体基板のパッシベーション性を向上させることができる。 According to the fifth configuration, the series resistance component can be reduced and the passivation property of the semiconductor substrate can be improved.
　また、第６の構成に係る光電変換素子は、第５の構成において、さらに、前記第１パッシベーション膜と、前記第１非晶質半導体層及び前記第２非晶質半導体層との間に形成され、第２パッシベーション膜を備え、前記第１パッシベーション膜及び前記第２パッシベーション膜は、真性非晶質半導体からなることとしてもよい。 The photoelectric conversion element according to the sixth configuration is further formed between the first passivation film and the first amorphous semiconductor layer and the second amorphous semiconductor layer in the fifth configuration. In addition, a second passivation film may be provided, and the first passivation film and the second passivation film may be made of an intrinsic amorphous semiconductor.
　第６の構成によれば、さらに、第１非晶質半導体層及び第２非晶質半導体層と第１パッシベーション膜との界面におけるキャリアの再結合を抑制することができる。 According to the sixth configuration, recombination of carriers at the interface between the first amorphous semiconductor layer and the second amorphous semiconductor layer and the first passivation film can be further suppressed.
　また、第７の構成に係る光電変換素子は、第６の構成において、前記第２パッシベーション膜は、前記膜厚減少領域を有することとしてもよい。 Further, in the photoelectric conversion element according to the seventh configuration, in the sixth configuration, the second passivation film may include the film thickness reduction region.
　第７の構成によれば、第２パッシベーション膜における膜厚減少領域の膜厚は、第２パッシベーション膜における第１の点の膜厚より薄いため、第２パッシベーション膜における膜厚減少領域において直列抵抗成分を低減することができる。 According to the seventh configuration, since the thickness of the film thickness reduction region in the second passivation film is smaller than the film thickness of the first point in the second passivation film, the series resistance in the film thickness reduction region in the second passivation film. Components can be reduced.
　また、第８の構成に係る光電変換素子は、第６又は第７の構成において、前記第２パッシベーション膜は、前記第１パッシベーション膜よりも膜厚が薄いこととしてもよい。 Further, in the photoelectric conversion element according to the eighth configuration, in the sixth or seventh configuration, the second passivation film may be thinner than the first passivation film.
　第８の構成によれば、パッシベーション性の向上を図るとともに、直列抵抗成分を低減することができる。 According to the eighth configuration, the passivation property can be improved and the series resistance component can be reduced.
　また、第９の構成に係る光電変換素子は、第５の構成において、前記第１パッシベーション膜は、キャリアがトンネル可能な絶縁物で構成されていることとしてもよい。第９の構成によれば、半導体基板をパッシベーションするとともに、キャリアを容易に取り出すことができる。 Further, in the photoelectric conversion element according to the ninth configuration, in the fifth configuration, the first passivation film may be formed of an insulator capable of tunneling carriers. According to the ninth configuration, the semiconductor substrate can be passivated and the carrier can be easily taken out.
　また、第１０の構成に係る光電変換素子は、第９の構成において、前記絶縁物は、少なくとも第４族元素を含む非晶質半導体の酸化物、窒化物、及び酸窒化物のいずれか、又は多結晶シリコンからなることとしてもよい。 Further, in the photoelectric conversion element according to a tenth configuration, in the ninth configuration, the insulator is any one of an oxide, a nitride, and an oxynitride of an amorphous semiconductor containing at least a Group 4 element. Alternatively, it may be made of polycrystalline silicon.
　以下、図面を参照し、本発明の実施の形態を詳しく説明する。図中同一または相当部分には同一符号を付してその説明は繰り返さない。なお、説明を分かりやすくするために、以下で参照する図面においては、構成が簡略化または模式化して示されたり、一部の構成部材が省略されたりしている。また、各図に示された構成部材間の寸法比は、必ずしも実際の寸法比を示すものではない。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated. In addition, in order to make the explanation easy to understand, in the drawings referred to below, the configuration is shown in a simplified or schematic manner, or some components are omitted. Further, the dimensional ratio between the constituent members shown in each drawing does not necessarily indicate an actual dimensional ratio.
　＜第１実施形態＞
　図１は、本発明の第１実施形態に係る光電変換素子の構成を模式的に示す断面図である。光電変換素子１は、シリコン基板１１、ＡＲＣ（Ａｎｔｉ　Ｒｅｆｌｅｃｔｉｏｎ　Ｃｏａｔ）１２、パッシベーション層１３、ｎ型半導体層（第１非晶質半導体層）１５ｎ、ｐ型半導体層（第２非晶質半導体層）１５ｐ、ｎ型電極１６ｎ、及びｐ型電極１６ｐを備える。 <First Embodiment>
FIG. 1 is a cross-sectional view schematically showing the configuration of the photoelectric conversion element according to the first embodiment of the present invention. The photoelectric conversion element 1 includes a silicon substrate 11, an ARC (Anti Reflection Coat) 12, a passivation layer 13, an n-type semiconductor layer (first amorphous semiconductor layer) 15n, and a p-type semiconductor layer (second amorphous semiconductor layer). 15p, an n-type electrode 16n, and a p-type electrode 16p.
　シリコン基板１１は、例えば、ｎ型の単結晶シリコン基板である。シリコン基板１１の厚さは、例えば、１００～１５０μｍである。なお、シリコン基板１１は、ｎ型の単結晶シリコン基板に代えて、ｐ型の単結晶シリコン基板を用いてもよい。 The silicon substrate 11 is, for example, an n-type single crystal silicon substrate. The thickness of the silicon substrate 11 is, for example, 100 to 150 μm. Note that the silicon substrate 11 may be a p-type single crystal silicon substrate instead of the n-type single crystal silicon substrate.
　図１において、シリコン基板１１の一方（Ｚ軸負方向側）の面はテクスチャが形成されている。テクスチャは、シリコン基板１１の表面反射率を低下させ、短絡電流を増加させる。以下の説明において、テクスチャが形成されている面をシリコン基板１１の受光面と称し、他方（Ｚ軸正方向側）の面を裏面と称する。 In FIG. 1, a texture is formed on one surface (Z-axis negative direction side) of the silicon substrate 11. The texture decreases the surface reflectance of the silicon substrate 11 and increases the short circuit current. In the following description, the surface on which the texture is formed is referred to as the light receiving surface of the silicon substrate 11, and the other surface (the Z-axis positive direction side) is referred to as the back surface.
　シリコン基板１１の受光面を覆うように、ＡＲＣ１２が形成されている。ＡＲＣ１２は、例えば、厚さ６０ｎｍ程度の窒化シリコン膜を堆積して構成されている。ＡＲＣ１２は、シリコン基板１１の表面反射率を低下させ、短絡電流を増加させる。 An ARC 12 is formed so as to cover the light receiving surface of the silicon substrate 11. The ARC 12 is configured, for example, by depositing a silicon nitride film having a thickness of about 60 nm. The ARC 12 decreases the surface reflectance of the silicon substrate 11 and increases the short-circuit current.
　シリコン基板１１の裏面上には、パッシベーション層１３が形成されている。パッシベーション層１３は、シリコン基板１１の熱酸化膜で構成されている。なお、パッシベーション層１３としては、例えば、非晶質シリコン、又は非晶質シリコンの酸化物、窒化物、及び酸窒化物、又は多結晶シリコン等であってもよい。パッシベーション層１３の厚さは、例えば１～２０ｎｍが好ましく、１～３ｎｍがより好ましい。本実施形態において、パッシベーション層１３の厚さは２ｎｍである。 A passivation layer 13 is formed on the back surface of the silicon substrate 11. The passivation layer 13 is composed of a thermal oxide film of the silicon substrate 11. The passivation layer 13 may be, for example, amorphous silicon, amorphous silicon oxide, nitride, oxynitride, polycrystalline silicon, or the like. The thickness of the passivation layer 13 is preferably 1 to 20 nm, for example, and more preferably 1 to 3 nm. In the present embodiment, the thickness of the passivation layer 13 is 2 nm.
　図１に示すように、パッシベーション層１３の上には、面内方向（Ｘ軸方向）において、ｎ型半導体層（第１非晶質半導体層）１５ｎとｐ型半導体層（第２非晶質半導体層）１５ｐが交互に隣接して形成されている。隣接するｎ型半導体層１５ｎとｐ型半導体層１５ｎは、所定の距離（Ｇ）を隔てて配置されている。 As shown in FIG. 1, an n-type semiconductor layer (first amorphous semiconductor layer) 15n and a p-type semiconductor layer (second amorphous layer) are formed on the passivation layer 13 in the in-plane direction (X-axis direction). Semiconductor layers 15p are alternately formed adjacent to each other. The adjacent n-type semiconductor layer 15n and p-type semiconductor layer 15n are arranged with a predetermined distance (G) therebetween.
　ｎ型半導体層１５ｎは、水素を含有するｎ型の非晶質半導体層である。ｎ型半導体層１５ｎは、例えばリン（Ｐ）を不純物として含有する、ｎ型非晶質シリコン、ｎ型非晶質シリコンゲルマニウム、ｎ型非晶質ゲルマニウム、ｎ型非晶質シリコンカーバイド、ｎ型非晶質シリコンナイトライド、ｎ型非晶質シリコンオキサイド、ｎ型非晶質シリコンオキシナイトライド、ｎ型非晶質シリコンカーボンオキサイド等であってもよい。ｎ型半導体層１５ｎの厚さは、例えば、３～５０ｎｍである。 The n-type semiconductor layer 15n is an n-type amorphous semiconductor layer containing hydrogen. The n-type semiconductor layer 15n includes, for example, phosphorus (P) as an impurity, n-type amorphous silicon, n-type amorphous silicon germanium, n-type amorphous germanium, n-type amorphous silicon carbide, n-type It may be amorphous silicon nitride, n-type amorphous silicon oxide, n-type amorphous silicon oxynitride, n-type amorphous silicon carbon oxide, or the like. The thickness of the n-type semiconductor layer 15n is, for example, 3 to 50 nm.
　ｐ型半導体層１５ｐは、水素を含有するｐ型の非晶質半導体層である。ｐ型半導体層１５ｐは、例えばボロン（Ｂ）を不純物として含有する、ｐ型非晶質シリコン、ｐ型非晶質シリコンゲルマニウム、ｐ型非晶質ゲルマニウム、ｐ型非晶質シリコンカーバイド、ｐ型非晶質シリコンナイトライド、ｐ型非晶質シリコンオキサイド、ｐ型非晶質シリコンオキシナイトライド、ｐ型非晶質シリコンカーボンオキサイド等であってもよい。ｐ型半導体層１５ｐの厚さは、例えば、５～５０ｎｍである。 The p-type semiconductor layer 15p is a p-type amorphous semiconductor layer containing hydrogen. The p-type semiconductor layer 15p includes, for example, boron (B) as an impurity, p-type amorphous silicon, p-type amorphous silicon germanium, p-type amorphous germanium, p-type amorphous silicon carbide, p-type. It may be amorphous silicon nitride, p-type amorphous silicon oxide, p-type amorphous silicon oxynitride, p-type amorphous silicon carbon oxide, or the like. The thickness of the p-type semiconductor layer 15p is, for example, 5 to 50 nm.
　シリコン基板１１の面内方向（Ｘ軸方向）において、ｎ型半導体層１５ｎの幅は、ｐ型半導体層１５ｐの幅よりも小さい。ｎ型半導体層１５ｎの面積とｐ型半導体層１５ｐの面積の和に対するｐ型半導体層１５ｐの面積の割合が高いほど、光照射によって生成される少数キャリア（正孔）が、ｐ型半導体層１５ｐに到達するまでに移動する距離が減少する。その結果、ｐ型半導体層１５ｐに到達するまでに再結合する正孔の数が減少し、短絡電流が増加し、光電変換効率が向上する。 In the in-plane direction (X-axis direction) of the silicon substrate 11, the width of the n-type semiconductor layer 15n is smaller than the width of the p-type semiconductor layer 15p. The higher the ratio of the area of the p-type semiconductor layer 15p to the sum of the area of the n-type semiconductor layer 15n and the area of the p-type semiconductor layer 15p, the more minority carriers (holes) generated by light irradiation are. The distance traveled before reaching is reduced. As a result, the number of holes that recombine before reaching the p-type semiconductor layer 15p is reduced, the short-circuit current is increased, and the photoelectric conversion efficiency is improved.
　ｎ型半導体層１５ｎの上には、ｎ型電極１６ｎが形成されている。ｐ型半導体層１５ｐの上には、ｐ型電極１６ｐが形成されている。ｎ型電極１６ｎ及びｐ型電極１６ｐは、後述する２つの導電層を積層して構成されている。ｎ型電極１６ｎ及びｐ型電極１６ｐの詳細な構造の説明については後述する。 An n-type electrode 16n is formed on the n-type semiconductor layer 15n. A p-type electrode 16p is formed on the p-type semiconductor layer 15p. The n-type electrode 16n and the p-type electrode 16p are configured by laminating two conductive layers described later. The detailed structure of the n-type electrode 16n and the p-type electrode 16p will be described later.
　なお、本明細書において、ｎ型及びｐ型の非晶質半導体層には、微結晶相が含まれてもよい。また、微結晶相は、平均粒子径が１～５０ｎｍである結晶を含む。 Note that in this specification, the n-type and p-type amorphous semiconductor layers may include a microcrystalline phase. The microcrystalline phase includes crystals having an average particle diameter of 1 to 50 nm.
　ここで、ｎ型半導体層１５ｎ及びｐ型半導体層１５ｐの形状について説明する。図２は、図１に示すｎ型半導体層１５ｎが形成された部分を拡大した模式図である。また、図３Ａは、触針段差計にてｎ型半導体層１５ｎを面内方向（Ｘ軸方向）にスキャンし、ｎ型半導体層１５ｎの膜厚を測定した結果を示している。 Here, the shapes of the n-type semiconductor layer 15n and the p-type semiconductor layer 15p will be described. FIG. 2 is an enlarged schematic view of a portion where the n-type semiconductor layer 15n shown in FIG. 1 is formed. FIG. 3A shows the result of measuring the film thickness of the n-type semiconductor layer 15n by scanning the n-type semiconductor layer 15n in the in-plane direction (X-axis direction) with a stylus profilometer.
　図２に示すように、ｎ型半導体層１５ｎは、Ｌ、Ｔ、Ｒで示す３つの領域を有する。以下、領域Ｌをフラット領域Ｌ、領域Ｔを膜厚減少領域Ｔ、領域Ｒをテーパー形状領域Ｒと称する。なお、ｐ型半導体層１５ｐの構造の図示を省略するが、ｐ型半導体層１５ｐもｎ型半導体層１５ｎと同様に、フラット領域Ｌ、膜厚減少領域Ｔ、テーパー形状領域Ｒを有する。以下、各領域について具体的に説明する。 As shown in FIG. 2, the n-type semiconductor layer 15n has three regions indicated by L, T, and R. Hereinafter, the region L is referred to as a flat region L, the region T as a film thickness reduction region T, and the region R as a tapered region R. Although illustration of the structure of the p-type semiconductor layer 15p is omitted, the p-type semiconductor layer 15p also has a flat region L, a film thickness reduction region T, and a tapered region R like the n-type semiconductor layer 15n. Hereinafter, each region will be described in detail.
　図３Ａに示すように、ｎ型半導体層１５ｎは、ｎ型半導体層１５ｎの略中心となるＣ点からスキャン方向の長さが２８０μｍの間、及びＣ点から３８０μｍの間は膜厚が殆ど変化していない。フラット領域Ｌは、最大の膜厚から膜厚が殆ど変化しない領域であり、図３Ａの例では、スキャン方向の長さが２８０μｍ～３８０μｍの間の領域である。 As shown in FIG. 3A, the film thickness of the n-type semiconductor layer 15n changes substantially between the length of 280 μm from the point C, which is substantially the center of the n-type semiconductor layer 15n, and between the point C and 380 μm. Not done. The flat region L is a region where the film thickness hardly changes from the maximum film thickness. In the example of FIG. 3A, the length in the scan direction is between 280 μm and 380 μm.
　また、図３Ａに示すように、フラット領域Ｌの一方の端部Ｋ１０からＫ１１（Ｋ１）の領域と、フラット領域Ｌの他方の端部Ｋ２０からＫ１２（Ｋ１）の領域は、膜厚が緩やかに減少している。これに対し、Ｋ１１からＫ２１（Ｋ２）の領域及びＫ１２からＫ２２（Ｋ２）の領域は、膜厚が急峻に減少している。つまり、フラット領域Ｌの一方の端部Ｋ１０からＫ１１の領域、及びフラット領域Ｌの他方の端部Ｋ２０からＫ１２の領域における膜厚の減少率（第１減少率）よりも、Ｋ１１からＫ２１の領域及びＫ１２からＫ２２の領域における膜厚の減少率（第２減少率）が大きくなっている。 Further, as shown in FIG. 3A, the film thickness of the region from one end K10 to K11 (K1) of the flat region L and the region from the other end K20 to K12 (K1) of the flat region L is moderate. is decreasing. On the other hand, the film thickness of the region from K11 to K21 (K2) and the region from K12 to K22 (K2) are sharply decreased. That is, the region from K11 to K21 is smaller than the film thickness reduction rate (first reduction rate) in the region from one end K10 to K11 of the flat region L and the region from the other end K20 to K12 of the flat region L. In addition, the film thickness reduction rate (second reduction rate) in the region from K12 to K22 is large.
　膜厚減少領域Ｔは、ｎ型半導体層１５ｎにおいて膜厚の減少率が緩やかに変化する領域であり、図３Ａにおいて、フラット領域Ｌの端部Ｋ１０から点Ｋ１１までの領域と、フラット領域Ｌの端部Ｋ２０から点Ｋ１２までの領域である。すなわち、本実施形態において、膜厚減少領域は、シリコン基板１１上に成膜される一の薄膜において、当該薄膜の膜厚が最大となる点を第１の点とし、当該薄膜の面内方向において膜厚の減少率が第１の減少率から第１の減少率よりも大きい第２の減少率に変化する点を第２の点とした場合、当該薄膜の面内方向における第１の点から第２の点までの領域である。 The film thickness reduction region T is a region where the film thickness reduction rate gradually changes in the n-type semiconductor layer 15n. In FIG. 3A, the region from the end K10 to the point K11 of the flat region L and the flat region L This is the region from the end K20 to the point K12. That is, in the present embodiment, the film thickness reduction region is defined as a first point in the thin film formed on the silicon substrate 11, where the thin film has the maximum film thickness, and the in-plane direction of the thin film. When the second point is the point at which the film thickness decrease rate changes from the first decrease rate to the second decrease rate larger than the first decrease rate, the first point in the in-plane direction of the thin film To the second point.
　テーパー形状領域Ｒは、テーパー状に成膜された領域であり、点Ｋ２（Ｋ２１，Ｋ２２）からｎ型半導体層１５ｎの下方端Ｋ３（Ｋ３１，Ｋ３２）までの領域である。テーパー形状領域Ｒの幅は、後述する半導体層の成膜条件等によって変動するが、例えば４００μｍ以下であり、１００μｍ以下がより好ましい。 The tapered region R is a region formed in a taper shape, and is a region from the point K2 (K21, K22) to the lower end K3 (K31, K32) of the n-type semiconductor layer 15n. The width of the tapered region R varies depending on the film formation conditions of the semiconductor layer described later, but is, for example, 400 μm or less, and more preferably 100 μm or less.
　図２において、ｎ型半導体層１５ｎの膜厚減少領域Ｔにおける膜厚の減少量ｄが、フラット領域Ｌの膜厚ｈの５％以上であることが好ましく、１０％以上であることがより好ましい。つまり、図３Ａにおいて、フラット領域Ｌの端部Ｋ１０，Ｋ２０から点Ｋ１１，Ｋ２１までの膜厚の減少量が、フラット領域Ｌの膜厚の５％以上であることが好ましく、１０％以上であることがより好ましい。図３Ａの縦軸は、フラット領域Ｌの膜厚を１．０として規格化したｎ型半導体層１５ｎの膜厚を示している。図３Ａに示すように、膜厚減少領域Ｔは、フラット領域Ｌの膜厚よりも２０％以上減少しており、好ましい状態である。また、膜厚減少領域Ｔの幅は、後述する成膜方法によって制御可能であり、２０μｍ以上が好ましく、１００μｍ以上がより好ましい。 In FIG. 2, the film thickness reduction amount d in the film thickness reduction region T of the n-type semiconductor layer 15n is preferably 5% or more of the film thickness h of the flat region L, and more preferably 10% or more. . That is, in FIG. 3A, the amount of decrease in the film thickness from the end K10, K20 of the flat region L to the point K11, K21 is preferably 5% or more of the film thickness of the flat region L, and is 10% or more. It is more preferable. The vertical axis in FIG. 3A indicates the film thickness of the n-type semiconductor layer 15n normalized by setting the film thickness of the flat region L to 1.0. As shown in FIG. 3A, the film thickness reduction region T is reduced by 20% or more than the film thickness of the flat region L, which is a preferable state. Further, the width of the film thickness reduction region T can be controlled by a film forming method described later, and is preferably 20 μm or more, and more preferably 100 μm or more.
　なお、図１及び図２では、便宜上、シリコン基板１１の表面が平坦な例を図示したが、シリコン基板１１の表面は凹凸形状を有する場合がある。図３Ｂの（ａ）は、シリコン基板１１の表面の顕微鏡写真である。また、図３Ｂの（ｂ）は、シリコン基板１１表面の高さを測定した結果を示す図である。 1 and 2 show an example in which the surface of the silicon substrate 11 is flat for the sake of convenience, the surface of the silicon substrate 11 may have an uneven shape. FIG. 3B is a photomicrograph of the surface of the silicon substrate 11. Moreover, (b) of FIG. 3B is a figure which shows the result of having measured the height of the silicon substrate 11 surface.
　図３Ｂの（ａ）（ｂ）に示すように、シリコン基板１１におけるダメージ層を除去するためのエッチングによって、テクスチャが形成されていないシリコン基板１１の面にも１μｍ程度の凹凸が形成される場合がある。上記図３Ａに示すシリコン基板１１の膜厚は、シリコン基板１１の凹凸を除いた膜厚である。シリコン基板１１に凹凸がある場合のｎ型半導体層１５ｎ、ｐ型半導体層１５ｐにおける膜厚減少領域Ｔは、以下のようにして判断することができる。 As shown in (a) and (b) of FIG. 3B, when the unevenness of about 1 μm is formed also on the surface of the silicon substrate 11 where the texture is not formed by etching for removing the damaged layer in the silicon substrate 11. There is. The film thickness of the silicon substrate 11 shown in FIG. 3A is a film thickness excluding the unevenness of the silicon substrate 11. The film thickness reduction region T in the n-type semiconductor layer 15n and the p-type semiconductor layer 15p when the silicon substrate 11 is uneven can be determined as follows.
　例えば、シリコン基板１１の表面に凹凸が形成されている場合において、シリコン基板１１の表面にパッシベーション膜１３を形成し、パッシベーション膜１３の上にｎ型半導体層１５ｎ又はｐ型半導体層１５ｐを形成して、走査電子顕微鏡（ＳＥＭ）又は透過電子顕微鏡（ＴＥＭ）を用いて撮影する。撮影結果から、パッシベーション膜１３とシリコン基板１１の表面の界面を確認することができる。図３Ｃの（ａ）は、パッシベーション膜１３とシリコン基板１１の表面との界面１１Ｓからｎ型半導体層１５ｎ又はｐ型半導体層１５ｐの表面までの膜厚ｈを測定した結果を表す模式図である。図３Ｃの（ａ）に示す各膜厚ｈをプロットし直すことにより、図３Ｃの（ａ）に示す各膜厚ｈを、図３Ｃの（ｂ）に示すように表すことができる。つまり、図３Ａで示したように、シリコン基板１１の表面が略平坦なものとして半導体層（ｎ型半導体層１５ｎ、ｐ型半導体層１５ｐ）の膜厚を特定できる。よって、シリコン基板１１の表面が凹凸形状を有している場合であっても、ｎ型半導体層１５ｎ、ｐ型半導体層１５ｐにおける各膜厚減少領域Ｔを、このような方法を用いることで検証可能である。また後述するように、シリコン基板１１の両面にテクスチャが形成されている基板を用いた場合においても、上記の方法で、テクスチャ上の膜厚を測定しプロットしなおすことで膜厚減少領域Ｔを判断することができる。 For example, when unevenness is formed on the surface of the silicon substrate 11, a passivation film 13 is formed on the surface of the silicon substrate 11, and an n-type semiconductor layer 15 n or a p-type semiconductor layer 15 p is formed on the passivation film 13. Then, the image is taken using a scanning electron microscope (SEM) or a transmission electron microscope (TEM). From the imaging result, the interface between the passivation film 13 and the surface of the silicon substrate 11 can be confirmed. FIG. 3C is a schematic diagram showing the result of measuring the film thickness h from the interface 11S between the passivation film 13 and the surface of the silicon substrate 11 to the surface of the n-type semiconductor layer 15n or the p-type semiconductor layer 15p. . By re-plotting each film thickness h shown in FIG. 3C (a), each film thickness h shown in FIG. 3C (a) can be expressed as shown in FIG. 3C (b). That is, as shown in FIG. 3A, the film thickness of the semiconductor layer (n-type semiconductor layer 15n, p-type semiconductor layer 15p) can be specified on the assumption that the surface of the silicon substrate 11 is substantially flat. Therefore, even if the surface of the silicon substrate 11 has a concavo-convex shape, each film thickness reduction region T in the n-type semiconductor layer 15n and the p-type semiconductor layer 15p is verified by using such a method. Is possible. Further, as will be described later, even when a substrate having a texture formed on both sides of the silicon substrate 11 is used, the film thickness reduction region T is determined by measuring and re-plotting the film thickness on the texture by the above method. Judgment can be made.
　本実施形態では、シリコン基板１１としてｎ型の単結晶シリコン基板を用いるため、ｎ型半導体層１５ｎの低抵抗化が重要となる。そのため、ｐ型半導体層１５ｐの膜厚減少領域Ｔの幅より、ｎ型半導体層１５ｎの膜厚減少領域Ｔの幅が大きいことが好ましい。シリコン基板１１にｐ型の単結晶シリコン基板を用いる場合には、上記とは逆に、ｐ型半導体層１５ｐの膜厚減少領域Ｔの幅が、ｎ型半導体層１５ｎの膜厚減少領域Ｔの幅よりも大きいことが好ましい。また、膜厚減少領域Ｔの膜厚の減少量についても、シリコン基板１１と同じ導電型を有する半導体層の膜厚の減少量が、他方の半導体層の膜厚の減少量よりも大きいことがより好ましい。 In this embodiment, since an n-type single crystal silicon substrate is used as the silicon substrate 11, it is important to reduce the resistance of the n-type semiconductor layer 15n. Therefore, it is preferable that the width of the film thickness reduction region T of the n-type semiconductor layer 15n is larger than the width of the film thickness reduction region T of the p-type semiconductor layer 15p. When a p-type single crystal silicon substrate is used as the silicon substrate 11, the width of the film thickness reduction region T of the p-type semiconductor layer 15p is opposite to that of the film thickness reduction region T of the n-type semiconductor layer 15n. It is preferable that it is larger than the width. In addition, regarding the reduction amount of the film thickness in the thickness reduction region T, the reduction amount of the semiconductor layer having the same conductivity type as that of the silicon substrate 11 may be larger than the reduction amount of the film thickness of the other semiconductor layer. More preferred.
　ここで、隣接するｎ型半導体層１５ｎとｐ型半導体層１５ｐの膜厚減少領域Ｔが重なっている場合の模式図を図４に示す。図４に示すように、ｎ型半導体層１５ｎの膜厚減少領域Ｔｎ上に、ｐ型半導体層１５ｐの膜厚減少領域Ｔｐが形成されると、膜厚が厚くなるためパッシベーション性は向上する。しかしながら、ｎ型半導体層１５ｎとｐ型半導体層１５ｐにおける膜厚減少領域Ｔｎ、Ｔｐの上にｎ型電極１６ｎ、ｐ型電極１６ｐをそれぞれ形成しても、直列抵抗成分は減少せず、低抵抗化の効果は得られなくなる。そのため、低抵抗化を考慮した場合、隣接する半導体層における各膜厚減少領域Ｔが重ならないほうが好ましい。さらに、生産性の歩留まりなどを考慮すると、隣接する半導体層における各膜厚減少領域Ｔの端部となるＫ１点の間隔が、２０μｍ以上離れていることが好ましく、１００μｍ以上がより好ましい。 Here, FIG. 4 shows a schematic diagram in the case where the film thickness reduction regions T of the adjacent n-type semiconductor layer 15n and p-type semiconductor layer 15p overlap. As shown in FIG. 4, when the film thickness reduction region Tp of the p-type semiconductor layer 15p is formed on the film thickness reduction region Tn of the n-type semiconductor layer 15n, the film thickness is increased, so that the passivation property is improved. However, even if the n-type electrode 16n and the p-type electrode 16p are respectively formed on the film thickness reduction regions Tn and Tp in the n-type semiconductor layer 15n and the p-type semiconductor layer 15p, the series resistance component does not decrease, and the low resistance The effect of conversion will not be obtained. Therefore, when considering the reduction in resistance, it is preferable that the respective thickness reduction regions T in the adjacent semiconductor layers do not overlap. Furthermore, in consideration of the yield of productivity and the like, it is preferable that the distance between the K1 points that are the end portions of the respective film thickness reduction regions T in the adjacent semiconductor layers is 20 μm or more, and more preferably 100 μm or more.
　次に、図５を用いて、ｎ型電極１６ｎ及びｐ型電極１６ｐの構造について説明する。図５は、ｎ型半導体層１５ｎが配置されている領域を拡大した模式図である。図５に示すように、ｎ型電極１６ｎは、第１導電層１６１と第２導電層１６２とを積層した積層構造を有する。なお、図示を省略するが、ｐ型電極１６ｐもｎ型電極１６ｎと同様に、第１導電層１６１と第２導電層１６２とを積層した積層構造を有する。 Next, the structure of the n-type electrode 16n and the p-type electrode 16p will be described with reference to FIG. FIG. 5 is an enlarged schematic view of a region where the n-type semiconductor layer 15n is disposed. As shown in FIG. 5, the n-type electrode 16n has a stacked structure in which a first conductive layer 161 and a second conductive layer 162 are stacked. Although not shown, the p-type electrode 16p has a stacked structure in which the first conductive layer 161 and the second conductive layer 162 are stacked in the same manner as the n-type electrode 16n.
　第１導電層１６１は、例えば、ＩＴＯ（Ｉｎｄｉｕｍ　Ｔｉｎ　Ｏｘｉｄｅ）、ＺｎＯ、ＩＷＯ（Ｉｎｄｉｕｍ　Ｔｕｎｇｓｔｅｎ　Ｏｘｉｄｅ）等の透明導電膜で構成されている。 The first conductive layer 161 is made of a transparent conductive film such as ITO (Indium Tin Oxide), ZnO, or IWO (Indium Tungsten Oxide).
　第２導電層１６２は、例えば、Ａｇ（銀）、Ｎｉ（ニッケル）、Ａｌ（アルミニウム）、Ｃｕ（銅）、Ｓｎ（錫）、Ｐｔ（プラチナ）、Ａｕ（金）、Ｃｒ（クロム）、Ｗ（タングステン）、Ｃｏ（コバルト）等の金属、又はこれらの金属の合金、又はこれら金属の積層膜であってもよい。 The second conductive layer 162 is made of, for example, Ag (silver), Ni (nickel), Al (aluminum), Cu (copper), Sn (tin), Pt (platinum), Au (gold), Cr (chromium), W It may be a metal such as (tungsten) or Co (cobalt), an alloy of these metals, or a laminated film of these metals.
　第１導電層１６１は、ｎ型半導体層１５ｎ及びｐ型半導体層１５ｐと密着性の高い透明導電膜が用いられることが好ましい。第１導電層１６１の厚さは、例えば３～１００ｎｍが好ましい。また、第２導電層１６２は、第１導電層１６１よりも導電率の高い金属を用いることが好ましい。第２導電層１６２の厚さは、５０ｎｍ以上が好ましい。本実施形態における第２導電層１６２の厚さは、例えば０．８μｍ程度である。 The first conductive layer 161 is preferably made of a transparent conductive film having high adhesion to the n-type semiconductor layer 15n and the p-type semiconductor layer 15p. The thickness of the first conductive layer 161 is preferably 3 to 100 nm, for example. The second conductive layer 162 is preferably formed using a metal having higher conductivity than the first conductive layer 161. The thickness of the second conductive layer 162 is preferably 50 nm or more. The thickness of the second conductive layer 162 in this embodiment is, for example, about 0.8 μm.
　なお、この例では、ｎ型電極１６ｎ及びｐ型電極１６ｐは、第１導電層１６１と第２導電層１６２とを積層した積層構造を有するが、第１導電層１６１を設けず、第２導電層１６２を、ｎ型半導体層１５ｎ又はｐ型半導体層１５ｐに接するように形成してもよい。この場合には、第２導電層１６２は、ｎ型半導体層１５ｎ及びｐ型半導体層１５ｐと密着性の高い金属を用いることが好ましい。具体的には、第２導電層１６２は、例えば、１～１０ｎｍ程度の厚さのＴｉ（チタン）、Ｎｉ（ニッケル）、Ａｌ（アルミニウム）、Ｃｒ（クロム）等のいずれかの金属と、Ａｌ（アルミニウム）又はＡｇ（銀）等を主成分とする光を反射させる金属とを積層した積層構造を有することとしてもよい。 In this example, the n-type electrode 16n and the p-type electrode 16p have a stacked structure in which the first conductive layer 161 and the second conductive layer 162 are stacked. However, the first conductive layer 161 is not provided and the second conductive layer is not provided. The layer 162 may be formed in contact with the n-type semiconductor layer 15n or the p-type semiconductor layer 15p. In this case, the second conductive layer 162 is preferably made of a metal having high adhesion with the n-type semiconductor layer 15n and the p-type semiconductor layer 15p. Specifically, the second conductive layer 162 is made of, for example, any metal such as Ti (titanium), Ni (nickel), Al (aluminum), and Cr (chromium) having a thickness of about 1 to 10 nm, Al It is good also as having a laminated structure which laminated | stacked the metal which reflects light which has (aluminum) or Ag (silver) etc. as a main component.
　図５に示すように、ｎ型電極１６ｎは、膜厚減少領域Ｔの上にも形成されている。具体的には、ｎ型電極１６ｎのＸ軸方向の両端部Ｚ１，Ｚ２が、膜厚減少領域Ｔ内に位置するようにｎ型電極１６ｎは形成されている。図示を省略するが、ｐ型電極１６ｐもｎ型電極１６ｎと同様、ｐ型半導体層１５ｐにおける膜厚減少領域Ｔ内に、ｐ型電極１６ｐのＸ軸方向の両端部が位置するように形成されている。 As shown in FIG. 5, the n-type electrode 16n is also formed on the film thickness reduction region T. Specifically, the n-type electrode 16n is formed such that both end portions Z1, Z2 in the X-axis direction of the n-type electrode 16n are located in the film thickness reduction region T. Although not shown, the p-type electrode 16p is formed so that both ends in the X-axis direction of the p-type electrode 16p are located in the film thickness decreasing region T in the p-type semiconductor layer 15p, similarly to the n-type electrode 16n. ing.
　（光電変換素子１の製造方法）
　次に、図６Ａ～６Ｄを用い、光電変換素子１の製造方法について説明する。 (Method for producing photoelectric conversion element 1)
Next, a method for manufacturing the photoelectric conversion element 1 will be described with reference to FIGS. 6A to 6D.
　まず、バルクのシリコンから１００～３００μｍの厚さのウェハを切り出し、ウェハ表面のダメージ層を除去するためのエッチングと、厚さを調整するためのエッチングとを行う。これらのエッチングされたウェハの片面に保護膜を形成する。保護膜は、例えば、酸化シリコン、窒化シリコン等が用いられる。保護膜が形成されたウェハを、ＮａＯＨ、ＫＯＨ等のアルカリ溶液（例えば、ＫＯＨ：１～５ｗｔ％、イソプロピルアルコール：１～１０ｗｔ％の水溶液）を用いてウェットエッチングを行う。このとき、異方性エッチングによって、保護膜が形成されていない面にテクスチャ構造が形成される。エッチング後に保護膜を除去することにより、図６Ａに示すシリコン基板１１が生成される。 First, a wafer having a thickness of 100 to 300 μm is cut out from bulk silicon, and etching for removing a damaged layer on the wafer surface and etching for adjusting the thickness are performed. A protective film is formed on one side of these etched wafers. For example, silicon oxide, silicon nitride, or the like is used as the protective film. The wafer on which the protective film is formed is subjected to wet etching using an alkaline solution such as NaOH or KOH (for example, an aqueous solution of KOH: 1 to 5 wt%, isopropyl alcohol: 1 to 10 wt%). At this time, a texture structure is formed on the surface where the protective film is not formed by anisotropic etching. By removing the protective film after the etching, the silicon substrate 11 shown in FIG. 6A is generated.
　続いて、図６Ａに示すように、シリコン基板１１の受光面にＡＲＣ１２を形成し、裏面にパッシベーション層１３を形成する。以下、ＡＲＣ１２は、酸化シリコン膜と窒化シリコン膜とを積層した積層構造を有し、パッシベーション層１３は、酸化シリコン膜で構成されている場合について説明する。 Subsequently, as shown in FIG. 6A, the ARC 12 is formed on the light receiving surface of the silicon substrate 11, and the passivation layer 13 is formed on the back surface. Hereinafter, the ARC 12 has a stacked structure in which a silicon oxide film and a silicon nitride film are stacked, and the case where the passivation layer 13 is formed of a silicon oxide film will be described.
　この場合、まず、シリコン基板１１の表面を熱酸化させ、受光面の酸化膜と裏面のパッシベーション層１３とを形成する。その後、受光面の酸化膜の上に窒化シリコン膜を形成することによりＡＲＣ１２を形成する。シリコン基板１１の酸化は、ウェット処理および熱酸化処理のいずれを用いてもよい。ウェット処理の場合、例えば、シリコン基板１１を過酸化水素、硝酸、又はオゾン水等に浸漬し、その後、ドライ雰囲気で８００～１０００℃に加熱する。また、熱酸化処理の場合には、例えば、シリコン基板１１を酸素又は水蒸気の雰囲気で９００～１０００℃に加熱する。窒化シリコン膜の形成は、スパッタ法、ＥＢ（Ｅｌｅｃｔｒｏｎ　Ｂｅａｍ）蒸着法、ＴＥＯＳ（ＴｅｔｒａＥｔｈＯｘｙＳｉｌａｎｅ）法等によって行うことができる。 In this case, first, the surface of the silicon substrate 11 is thermally oxidized to form an oxide film on the light receiving surface and a passivation layer 13 on the back surface. Thereafter, an ARC 12 is formed by forming a silicon nitride film on the oxide film on the light receiving surface. For the oxidation of the silicon substrate 11, either a wet process or a thermal oxidation process may be used. In the case of wet processing, for example, the silicon substrate 11 is immersed in hydrogen peroxide, nitric acid, ozone water, or the like, and then heated to 800 to 1000 ° C. in a dry atmosphere. In the case of thermal oxidation treatment, for example, the silicon substrate 11 is heated to 900 to 1000 ° C. in an atmosphere of oxygen or water vapor. The silicon nitride film can be formed by sputtering, EB (Electron Beam) vapor deposition, TEOS (TetraEthoxySilane), or the like.
　熱酸化膜の形成後、プラズマＣＶＤ（Ｐｌａｓｍａ　Ｅｎｃｈａｎｃｅｄ　Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）を用い、パッシベーション層１３を窒素プラズマで窒化し、さらに５００℃以上でアニールすることにより、シリコン基板１１の裏面にＳｉＯＮ膜が形成される。このように、パッシベーション層１３をＳｉＯＮで形成することにより、パッシベーション層１３の上に形成されるｐ型半導体層１５ｐに含有されるボロン等の不純物がシリコン基板１１に拡散することを抑制することができる。また、トンネル電流を流すことができる膜厚のパッシベーション層１３を形成した場合であっても、有効にボロン等の不純物の拡散を抑制することができる。 After the thermal oxide film is formed, the passivation layer 13 is nitrided with nitrogen plasma using plasma CVD (Plasma Enhanced Chemical Vapor Deposition), and further annealed at 500 ° C. or higher to form a SiON film on the back surface of the silicon substrate 11. The In this manner, by forming the passivation layer 13 of SiON, it is possible to suppress diffusion of impurities such as boron contained in the p-type semiconductor layer 15p formed on the passivation layer 13 into the silicon substrate 11. it can. Further, even when the passivation layer 13 having a thickness capable of flowing a tunnel current is formed, diffusion of impurities such as boron can be effectively suppressed.
　太陽電池の作製において、シリコン基板１１の表面のパッシベーション性は重要なポイントの１つである。本実施形態では、１回の成膜によって、パッシベーション膜１３が、シリコン基板１１表面の全面に略均一な膜厚で形成される。意図的に複数回の成膜によって、シリコン基板１１の表面の全面をパッシベーションするのではなく、本実施形態のように、１回の成膜でパッシベーション膜１３を形成することは、製造プロセスの観点より好ましい。なお、パッシベーション膜１３は、完全に面内が均一な膜厚でなくてもよい。また、パッシベーション膜１３はシリコン基板１１の表面の全面に限らず、ウェハ周辺やアライメントマーク部分等、シリコン基板１１の表面の一部にパッシベーション膜１３が形成されていなくてもよい。このように、パッシベーション膜１３をシリコン基板１１の略全面において略均一に形成することにより、シリコン基板１１のパッシベーション性を向上させることができる。 In the production of solar cells, the passivation of the surface of the silicon substrate 11 is one of the important points. In this embodiment, the passivation film 13 is formed with a substantially uniform film thickness on the entire surface of the silicon substrate 11 by a single film formation. The purpose of forming the passivation film 13 by one film formation as in this embodiment is not the purpose of passivation the entire surface of the silicon substrate 11 by multiple film formation intentionally. More preferred. Note that the passivation film 13 may not have a completely uniform thickness. Further, the passivation film 13 is not limited to the entire surface of the silicon substrate 11, and the passivation film 13 may not be formed on a part of the surface of the silicon substrate 11 such as the periphery of the wafer or the alignment mark portion. Thus, the passivation property of the silicon substrate 11 can be improved by forming the passivation film 13 substantially uniformly on the substantially entire surface of the silicon substrate 11.
　次に、図６Ｂに示すように、パッシベーション層１３の上にメタルマスク１１０を配置し、ｎ型半導体層１５ｎを形成する。本実施形態では、フラット領域Ｌの幅が約１００μｍ、膜厚減少領域Ｔの幅が約１５０μｍとなるようにｎ型半導体層１５ｎが形成される。 Next, as shown in FIG. 6B, a metal mask 110 is disposed on the passivation layer 13 to form an n-type semiconductor layer 15n. In the present embodiment, the n-type semiconductor layer 15n is formed so that the width of the flat region L is about 100 μm and the width of the film thickness reduction region T is about 150 μm.
　メタルマスク１１０（１１０Ａ）は、シリコン基板１１上のｎ型半導体層１５ｎが形成される部分に開口１１０ａを有する。メタルマスク１１０の厚さＭは２００μｍであり、開口幅Ｏは４００μｍである。メタルマスク１１０は、ステンレス鋼、銅、ニッケル、ニッケルを含む合金（例えば、４２アロイ、又はインバー材等）、モリブデン等の金属で構成されていてもよい。シリコン基板１１の熱膨張係数と、原料コストとを考慮するとメタルマスク１１０は４２アロイがより好ましい。メタルマスク１１０の厚さＭに関し、製造コストを考慮すると、メタルマスク１１０を１回で使い捨てることは問題となる。メタルマスク１１０を何度も使用することによって生産のランニングコストを抑制することができるため、メタルマスク１１０を再生して多数回使用することが好ましい。この場合、メタルマスク１１０に付着する成膜物を、弗酸やＮａＯＨを用いて除去する。再生回数を考慮すると、メタルマスク１１０の厚さＭは、３０μｍ～３００μｍ程度が好ましい。 The metal mask 110 (110A) has an opening 110a in a portion where the n-type semiconductor layer 15n is formed on the silicon substrate 11. The metal mask 110 has a thickness M of 200 μm and an opening width O of 400 μm. The metal mask 110 may be made of a metal such as stainless steel, copper, nickel, an alloy containing nickel (for example, 42 alloy or Invar material), molybdenum or the like. Considering the thermal expansion coefficient of the silicon substrate 11 and the raw material cost, the metal mask 110 is more preferably 42 alloy. Regarding the thickness M of the metal mask 110, considering the manufacturing cost, it becomes a problem to dispose the metal mask 110 once. Since the running cost of production can be suppressed by using the metal mask 110 many times, it is preferable to recycle the metal mask 110 and use it many times. In this case, the film deposited on the metal mask 110 is removed using hydrofluoric acid or NaOH. Considering the number of times of reproduction, the thickness M of the metal mask 110 is preferably about 30 μm to 300 μm.
　なお、本実施形態では、メタルマスクを用いる例を説明するが、メタルマスクに代えて、ガラス、セラミック、有機フィルム等で構成されたマスクを用いてもよい。 In this embodiment, an example in which a metal mask is used will be described. However, a mask made of glass, ceramic, an organic film, or the like may be used instead of the metal mask.
　ｎ型半導体層１５ｎは、例えば、プラズマＣＶＤを用いて形成される。プラズマＣＶＤ装置が備える反応室に導入される反応ガスは、シランガス、水素ガス、及び水素希釈されたホスフィンガス（ホスフィン濃度：１％）である。この場合、水素ガス流量は０～１００ｓｃｃｍ、シランガス流量は４０ｓｃｃｍ、ホスフィンガス流量は４０ｓｃｃｍである。シリコン基板１１の温度は、例えば、１３０～１８０℃である。また、反応室内の圧力は、４０～１２０Ｐａであり、ＲＦパワー密度は５～１５ｍＷ／ｃｍ２である。これにより、リンがドープされたｎ型非晶質シリコン（ｎ型半導体層１５ｎ）が形成される。 The n-type semiconductor layer 15n is formed using, for example, plasma CVD. The reaction gas introduced into the reaction chamber provided in the plasma CVD apparatus is silane gas, hydrogen gas, and phosphine gas diluted with hydrogen (phosphine concentration: 1%). In this case, the hydrogen gas flow rate is 0 to 100 sccm, the silane gas flow rate is 40 sccm, and the phosphine gas flow rate is 40 sccm. The temperature of the silicon substrate 11 is 130 to 180 ° C., for example. The pressure in the reaction chamber is 40 to 120 Pa, and the RF power density is 5 to 15 mW / cm 2 . Thereby, n-type amorphous silicon (n-type semiconductor layer 15n) doped with phosphorus is formed.
　ｎ型半導体層１５ｎの膜厚減少領域Ｔの幅や膜厚減少量は、成膜圧力を変えることによって制御することができる。また、メタルマスク１１０Ａの厚さＭと開口幅Ｏによっても制御することができる。メタルマスク１１０の厚さＭを厚くすると、図７に示すように、メタルマスク１１０Ａ上の開口部１１０ａ近傍の領域Ｓａにおける成膜が顕著となり、それに伴って膜厚減少領域Ｔの幅も広くなる。また、開口幅Ｏを狭くすることによって、この現象は顕著に現れる。このように、メタルマスク１１０の厚さＭと開口幅Ｏ、成膜圧力などを制御することで、適切な膜厚減少領域Ｔを形成することができる。 The width of the film thickness reduction region T and the film thickness reduction amount of the n-type semiconductor layer 15n can be controlled by changing the film formation pressure. It can also be controlled by the thickness M and opening width O of the metal mask 110A. When the thickness M of the metal mask 110 is increased, as shown in FIG. 7, the film formation in the region Sa in the vicinity of the opening 110a on the metal mask 110A becomes remarkable, and the width of the film thickness reduction region T is increased accordingly. . In addition, this phenomenon appears remarkably by reducing the opening width O. Thus, by controlling the thickness M and opening width O of the metal mask 110, the film forming pressure, etc., an appropriate film thickness reduction region T can be formed.
　また、図７に示すように、プラズマＣＶＤなどの気相成膜法を用いて半導体層を成膜した場合、メタルマスク１１０Ａの下部、つまり、パッシベーション層１３とメタルマスク１１０Ａの隙間の領域Ｓｂに原料が回り込み、テーパー状に成膜される。反応室における圧力が高いほど原料の回り込みが大きくなり、テーパー形状領域Ｒの幅が大きくなる。テーパー形状領域Ｒの幅は、プラズマＣＶＤ装置の反応室における圧力や、メタルマスク１１０Ａとパッシベーション層１３の隙間の距離によって変動する。テーパー形状領域Ｒの幅は狭いことが好ましく、４００μｍ以下が好ましい。より好ましくは１００μｍ以下である。 Further, as shown in FIG. 7, when a semiconductor layer is formed using a vapor deposition method such as plasma CVD, in the lower part of the metal mask 110A, that is, in the region Sb between the passivation layer 13 and the metal mask 110A. The raw material wraps around and forms a taper. The higher the pressure in the reaction chamber, the greater the wraparound of the raw material and the greater the width of the tapered region R. The width of the tapered region R varies depending on the pressure in the reaction chamber of the plasma CVD apparatus and the distance between the metal mask 110 </ b> A and the passivation layer 13. The width of the tapered region R is preferably narrow, and is preferably 400 μm or less. More preferably, it is 100 μm or less.
　続いて、図６Ｃに示すように、メタルマスク１１０Ａを除去し、ｎ型半導体層１５ｎが形成されていない領域に開口部１１０ｂを有するメタルマスク１１０（１１０Ｂ）をシリコン基板１１上に配置し、ｐ型半導体層１５ｐを形成する。 Subsequently, as shown in FIG. 6C, the metal mask 110A is removed, and a metal mask 110 (110B) having an opening 110b in a region where the n-type semiconductor layer 15n is not formed is disposed on the silicon substrate 11, and p A type semiconductor layer 15p is formed.
　ｐ型半導体層１５ｐは、例えばプラズマＣＶＤを用いて形成される。プラズマＣＶＤ装置が備える反応室に導入される反応ガスは、シランガス、水素ガス、及び水素希釈されたジボランガス（ジボラン濃度：２％）である。この場合、水素ガス流量は０～１００ｓｃｃｍ、シランガス流量は４０ｓｃｃｍ、ジボランガス流量は４０ｓｃｃｍである。シリコン基板１１の温度は、１３０～１８０℃である。また、反応室内の圧力は、４０～１２０Ｐａであり、ＲＦパワー密度は５～１５ｍＷ／ｃｍ２である。これにより、ボロンがドープされたｐ型非晶質シリコン（ｐ型半導体層１５ｐ）が形成される。 The p-type semiconductor layer 15p is formed using, for example, plasma CVD. The reaction gas introduced into the reaction chamber provided in the plasma CVD apparatus is silane gas, hydrogen gas, and diborane gas diluted with hydrogen (diborane concentration: 2%). In this case, the hydrogen gas flow rate is 0 to 100 sccm, the silane gas flow rate is 40 sccm, and the diborane gas flow rate is 40 sccm. The temperature of the silicon substrate 11 is 130 to 180 ° C. The pressure in the reaction chamber is 40 to 120 Pa, and the RF power density is 5 to 15 mW / cm 2 . Thus, p-type amorphous silicon (p-type semiconductor layer 15p) doped with boron is formed.
　なお、ｐ型半導体層１５ｐにおいても、ｎ型半導体層１５ｎと同様に、成膜圧力、メタルマスク１１０Ｂの厚さと開口幅を調整することにより、ｐ型半導体層１５ｐの膜厚減少領域Ｔを制御することができる。 Also in the p-type semiconductor layer 15p, the film thickness reduction region T of the p-type semiconductor layer 15p is controlled by adjusting the film formation pressure, the thickness of the metal mask 110B, and the opening width, similarly to the n-type semiconductor layer 15n. can do.
　図６Ｃにおいて、メタルマスク１１０Ｂを除去することにより、パッシベーション層１３の上に、ｎ型半導体層１５ｎとｐ型半導体層１５ｐとが隣接して形成される。 6C, the n-type semiconductor layer 15n and the p-type semiconductor layer 15p are formed adjacent to each other on the passivation layer 13 by removing the metal mask 110B.
　続いて、図６Ｄに示すように、ｎ型半導体層１５ｎとｐ型半導体層１５ｎの間をメタルマスク１１０（１１０Ｃ）で覆い、ｎ型半導体層１５ｎとｐ型半導体層１５ｎの上に、ｎ型電極１６ｎ及びｐ型電極１６ｐを形成する。メタルマスク１１０Ｃは、開口部１１０ｃの端部が、隣接するｎ型半導体層１５ｎとｐ型半導体層１５ｐの膜厚減少領域Ｔ内に位置するように配置される。 Subsequently, as shown in FIG. 6D, the space between the n-type semiconductor layer 15n and the p-type semiconductor layer 15n is covered with a metal mask 110 (110C), and the n-type semiconductor layer 15n and the p-type semiconductor layer 15n are overlaid on the n-type semiconductor layer 15n. An electrode 16n and a p-type electrode 16p are formed. The metal mask 110C is arranged so that the end of the opening 110c is positioned in the film thickness reduction region T of the adjacent n-type semiconductor layer 15n and p-type semiconductor layer 15p.
　ｎ型電極１６ｎ及びｐ型電極１６ｐは、第１導電層１６１と第２導電層１６２ｎとを積層した積層構造を有する。第１導電層１６１及び第２導電層１６２は、スパッタ法、ＥＢ蒸着法、イオンプレーティング法、熱ＣＶＤ法、ＭＯＣＶＤ（Metal Organic Chemical Vapor Deposition）法、ゾルゲル法、液状にした原料を噴霧して加熱する方法、又はインクジェット法等を用いて形成することができる。本実施形態では、第１導電層１６１がＩＴＯ、ＩＷＯ、ＺｎＯのいずれかで構成されている。また、第２導電層１６２は、第１金属と第２金属の積層膜で構成されている。 The n-type electrode 16n and the p-type electrode 16p have a stacked structure in which a first conductive layer 161 and a second conductive layer 162n are stacked. The first conductive layer 161 and the second conductive layer 162 are formed by spraying a sputtering method, an EB vapor deposition method, an ion plating method, a thermal CVD method, a MOCVD (Metal-Organic-Chemical-Vapor-Deposition) method, a sol-gel method, or a liquid material. It can be formed using a heating method, an inkjet method, or the like. In the present embodiment, the first conductive layer 161 is composed of any one of ITO, IWO, and ZnO. The second conductive layer 162 is composed of a laminated film of a first metal and a second metal.
　第１導電層１６１は、例えばスパッタリングを用いて形成する。第１導電層１６１がＩＴＯの場合、以下の成膜条件でスパッタリングを行ってもよい。例えば、ＳｎＯ２を０．５～４ｗｔ％ドープしたＩＴＯターゲットを用い、アルゴンガス、又はアルゴンガスと酸素ガスとの混合ガスを導入する。シリコン基板１１の温度は２５～２５０℃であり、ガス圧力は０．１～１．５Ｐａ、投入電力は０．０１～２ｋＷである。また、第１導電層１６１がＺｎＯの場合は、上記ＩＴＯターゲットに代えて、Ａｌを０．５～４ｗｔ％ドープしたＺｎＯターゲットを用いる。 The first conductive layer 161 is formed using, for example, sputtering. When the first conductive layer 161 is ITO, sputtering may be performed under the following film formation conditions. For example, an ITO target doped with 0.5 to 4 wt% of SnO 2 is used, and argon gas or a mixed gas of argon gas and oxygen gas is introduced. The temperature of the silicon substrate 11 is 25 to 250 ° C., the gas pressure is 0.1 to 1.5 Pa, and the input power is 0.01 to 2 kW. When the first conductive layer 161 is ZnO, a ZnO target doped with 0.5 to 4 wt% Al is used instead of the ITO target.
　第２導電層１６２は、例えばＥＢ蒸着法を用いて形成してもよいし、第１導電層１６１をシード層とし、メッキ成膜法によって第２導電層１６２を形成してもよい。例えば、第２導電層１６２の第１金属としてＴｉを成膜し、第１金属の上に、第２金属としてＡｌを成膜することにより、ＴｉとＡｌの積層膜（Ｔｉ／Ａｌ）からなる第２導電層１６２が形成される。なお、第１金属としては、Ｔｉ以外に、例えば、Ｎｉ、Ｗ、Ｃｏ等を用いてもよい。又は、これら金属の合金を用いてもよいし、これらの金属とＰ又はＢとの合金を用いてもよい。また、第２金属として、Ａｌ以外に、例えばＣｕ、Ｓｎ等を用いてもよい。 The second conductive layer 162 may be formed by using, for example, an EB vapor deposition method, or the first conductive layer 161 may be used as a seed layer, and the second conductive layer 162 may be formed by a plating film forming method. For example, Ti is formed as the first metal of the second conductive layer 162, and Al is formed as the second metal on the first metal, thereby forming a laminated film of Ti and Al (Ti / Al). A second conductive layer 162 is formed. In addition to Ti, for example, Ni, W, Co, or the like may be used as the first metal. Alternatively, an alloy of these metals may be used, or an alloy of these metals and P or B may be used. In addition to Al, for example, Cu, Sn, or the like may be used as the second metal.
　メタルマスク１１０Ｃの開口部１１０ｃの幅の端部が、ｎ型半導体層１５ｎ及びｐ型半導体層１５ｐの各膜厚減少領域Ｔ内に位置するようにメタルマスク１１０Ｃを配置することにより、図５に示すように、ｎ型電極１６ｎの両端部Ｚ１，Ｚ２がｎ型半導体層１５ｎの膜厚減少領域Ｔ内に位置するようにｎ型電極１６ｎが形成される。また、図示を省略するが、ｐ型電極１６ｐも同様に、ｐ型電極１６ｐの両端部Ｚ１，Ｚ２がｐ型半導体層１５ｐの膜厚減少領域Ｔ内に位置するように形成される。 By arranging the metal mask 110C so that the end of the width of the opening 110c of the metal mask 110C is located in each of the film thickness reduction regions T of the n-type semiconductor layer 15n and the p-type semiconductor layer 15p, FIG. As shown, the n-type electrode 16n is formed such that both end portions Z1, Z2 of the n-type electrode 16n are located in the film thickness reduction region T of the n-type semiconductor layer 15n. Although not shown, the p-type electrode 16p is similarly formed so that both end portions Z1 and Z2 of the p-type electrode 16p are located in the film thickness reduction region T of the p-type semiconductor layer 15p.
　上記した製造方法により、図１に示す光電変換素子１が形成される。光電変換素子１において、ｐ型半導体層１５ｐとシリコン基板１１は、パッシベーション層１３を介してｐｎ接合を形成する。ｐｎ接合に光が入射すると、電子と正孔とが生成される。電子と正孔は、パッシベーション層１３をトンネリングして、ｎ型半導体層１５ｎとｐ型半導体層１５ｐにそれぞれ移動し、ｎ型電極１６ｎとｐ型電極１６ｐを通じて、電流として外部に取り出される。パッシベーション層１３によって、シリコン基板１１とｎ型半導体層１５ｎとの間の界面、及びシリコン基板１１とｐ型半導体層１５ｐとの間の界面の欠陥が低減される。 The photoelectric conversion element 1 shown in FIG. 1 is formed by the manufacturing method described above. In the photoelectric conversion element 1, the p-type semiconductor layer 15 p and the silicon substrate 11 form a pn junction through the passivation layer 13. When light enters the pn junction, electrons and holes are generated. Electrons and holes are tunneled through the passivation layer 13 and moved to the n-type semiconductor layer 15n and the p-type semiconductor layer 15p, respectively, and are taken out as current through the n-type electrode 16n and the p-type electrode 16p. The passivation layer 13 reduces defects at the interface between the silicon substrate 11 and the n-type semiconductor layer 15n and the interface between the silicon substrate 11 and the p-type semiconductor layer 15p.
　上述した実施形態では、ｎ型電極１６ｎ及びｐ型電極１６ｐは、各電極の両端部Ｚ１，Ｚ２が、対応する半導体層における膜厚減少領域Ｔ内に位置するように形成される例を説明した。ここで、ｎ型電極１６ｎ及びｐ型電極１６ｐの両端部Ｚ１，Ｚ２の位置と、光電変換素子の直列抵抗成分Ｒｓ及び開放電圧Ｖｏｃとの関係について説明する。 In the above-described embodiment, the n-type electrode 16n and the p-type electrode 16p have been described as being formed such that both end portions Z1 and Z2 of each electrode are located in the film thickness reduction region T in the corresponding semiconductor layer. . Here, the relationship between the positions of both ends Z1, Z2 of the n-type electrode 16n and the p-type electrode 16p, the series resistance component Rs of the photoelectric conversion element, and the open circuit voltage Voc will be described.
　図８の（ａ）～（ｄ）は、ｎ型電極１６ｎの両端部Ｚ１，Ｚ２の位置が各々異なる４つの電極（１６１ｎ、１６ｎ、１６２ｎ、１６３ｎ）を示す模式図であり、図９は、図８の（ａ）～（ｄ）に示す各ｎ型電極を用いた場合の直列抵抗成分Ｒｓと開放電圧Ｖｏｃとを測定した結果を示す図である。 FIGS. 8A to 8D are schematic views showing four electrodes (161n, 16n, 162n, 163n) in which the positions of both end portions Z1, Z2 of the n-type electrode 16n are different, and FIG. FIG. 9 is a diagram showing the results of measuring a series resistance component Rs and an open circuit voltage Voc when each n-type electrode shown in FIGS. 8A to 8D is used.
　図８の（ａ）～（ｄ）に示す各ｎ型電極の下のｎ型半導体層１５ｎは、フラット領域Ｌ、膜厚減少領域Ｔ、テーパー形状領域Ｒを有する。図８の（ａ）は、ｎ型電極１６１ｎの両端部Ｚ１，Ｚ２がフラット領域Ｌ内に位置し、図８の（ｂ）は、上述した実施形態と同様、ｎ型電極１６ｎの両端部Ｚ１，Ｚ２が膜厚減少領域Ｔ内に位置している。また、図８の（ｃ）は、ｎ型電極１６２ｎの両端部Ｚ１，Ｚ２がテーパー形状領域Ｒ内に位置し、図８の（ｄ）は、ｎ型電極１６３ｎの両端部Ｚ１，Ｚ２がテーパー形状領域Ｒの外側に位置している。 8A to 8D, the n-type semiconductor layer 15n under each n-type electrode has a flat region L, a film thickness reduction region T, and a tapered region R. 8A shows that both end portions Z1 and Z2 of the n-type electrode 161n are located in the flat region L, and FIG. 8B shows both end portions Z1 of the n-type electrode 16n as in the above-described embodiment. , Z2 are located in the film thickness reduction region T. 8C, both end portions Z1, Z2 of the n-type electrode 162n are located in the tapered region R, and FIG. 8D, both end portions Z1, Z2 of the n-type electrode 163n are tapered. It is located outside the shape region R.
　図８の（ａ）に示すｎ型電極１６１ｎの場合、膜厚減少領域Ｔを形成しない場合と略同様の特性を有する。そのため、図９に示すように、図８の（ａ）の場合の直列抵抗成分Ｒｓ及び開放電圧Ｖｏｃをそれぞれ１．０とし、これをレファレンスとする。 The n-type electrode 161n shown in FIG. 8A has substantially the same characteristics as when the film thickness reduction region T is not formed. Therefore, as shown in FIG. 9, the series resistance component Rs and the open circuit voltage Voc in the case of FIG. 8A are set to 1.0, which are used as references.
　図９に示すように、図８の（ｂ）に示すｎ型電極１６ｎの場合、図８の（ａ）に示す電極１６１ｎよりも直列抵抗成分Ｒｓが８８％まで低下し、開放電圧Ｖｏｃはｎ型電極１６１ｎの場合と同じである。つまり、図８の（ｂ）に示すｎ型電極１６ｎを用いた場合は、ｎ型電極１６１ｎを用いた場合と比べ、パッシベーション性を確保しつつ、低抵抗化を図ることができる。また、図９に示すように、図８の（ｃ）に示すｎ型電極１６２ｎ、及び図８の（ｄ）に示すｎ型電極１６３ｎを用いた場合、図８の（ｂ）に示すｎ型電極１６ｎを用いた場合に比べて直列抵抗成分Ｒｓが低下するが、開放電圧Ｖｏｃも若干低下する。よって、図８の（ｃ）に示すｎ型電極１６２ｎ、及び図８の（ｄ）に示すｎ型電極１６３ｎのように、ｎ型電極１６ｎの両端部Ｚ１，Ｚ２がテーパー形状領域Ｒの内側や外側に位置する場合には、低抵抗化を図ることができる。上記のとおり、ｎ型電極１６ｎの両端部Ｚ１，Ｚ２が膜厚減少領域Ｔ内に位置する図８の（ｂ）の場合、パッシベーション性を確保しつつ、低抵抗化を図ることができるため、図８の（ｃ）（ｄ）のｎ型電極１６２ｎ、１６３ｎを用いた場合よりも好ましいと言える。 As shown in FIG. 9, in the case of the n-type electrode 16n shown in FIG. 8B, the series resistance component Rs is reduced to 88% as compared with the electrode 161n shown in FIG. The same as the case of the mold electrode 161n. That is, when the n-type electrode 16n shown in FIG. 8B is used, the resistance can be lowered while securing the passivation property as compared with the case where the n-type electrode 161n is used. Further, as shown in FIG. 9, when the n-type electrode 162n shown in FIG. 8C and the n-type electrode 163n shown in FIG. 8D are used, the n-type shown in FIG. Although the series resistance component Rs is reduced as compared with the case where the electrode 16n is used, the open circuit voltage Voc is also slightly reduced. Therefore, like the n-type electrode 162n shown in FIG. 8C and the n-type electrode 163n shown in FIG. 8D, both end portions Z1 and Z2 of the n-type electrode 16n are arranged inside the tapered region R. In the case of being located on the outside, the resistance can be reduced. As described above, in the case of FIG. 8B in which both end portions Z1 and Z2 of the n-type electrode 16n are located in the film thickness reduction region T, it is possible to achieve low resistance while ensuring passivation. It can be said that this is preferable to the case where the n- type electrodes 162n and 163n in FIGS. 8C and 8D are used.
　なお、上記実施形態の例では、ｎ型半導体層１５ｎとｐ型半導体層１５ｐのそれぞれに膜厚減少領域Ｔを形成する例を説明したが、いずれか一方の半導体層に膜厚減少領域Ｔが設けられている場合であっても低抵抗の効果を得ることができる。よって、ｎ型半導体層１５ｎとｐ型半導体層１５ｐの少なくとも一方の半導体層において膜厚減少領域Ｔが設けられていればよい。 In the example of the above-described embodiment, the example in which the film thickness reduction region T is formed in each of the n-type semiconductor layer 15n and the p-type semiconductor layer 15p has been described, but the film thickness reduction region T is formed in any one of the semiconductor layers. Even if it is provided, an effect of low resistance can be obtained. Therefore, the film thickness reduction region T only needs to be provided in at least one of the n-type semiconductor layer 15n and the p-type semiconductor layer 15p.
　上述した実施形態では、ｎ型及びｐ型半導体層１５ｎ，１５ｐにおける膜厚減少領域Ｔは、ｎ型及びｐ型半導体層１５ｎ，１５ｐの中心部分よりも膜厚が薄い。そのため、膜厚減少領域Ｔにｎ型電極１６ｎ又はｐ型電極１６ｐの少なくとも一部を形成することにより、直列抵抗を減少させることができ、光電変換素子の特性を向上させることができる。 In the embodiment described above, the film thickness reduction region T in the n-type and p- type semiconductor layers 15n and 15p is thinner than the central portion of the n-type and p- type semiconductor layers 15n and 15p. Therefore, by forming at least part of the n-type electrode 16n or the p-type electrode 16p in the film thickness reduction region T, the series resistance can be reduced and the characteristics of the photoelectric conversion element can be improved.
　また、上述した実施形態では、ｎ型及びｐ型半導体層１５ｎ、１５ｐを形成する際、メタルマスク１１０の開口部の幅やメタルマスク１１０の厚さ、又は成膜圧力を制御することで、フラット領域Ｌと膜厚減少領域Ｔが１回の成膜で形成される。フラット領域Ｌに比べて膜厚減少領域Ｔは、相対的に成膜レートが遅くなるため、フラット領域Ｌよりも不純物濃度が相対的に増加する。その結果、膜厚減少領域Ｔにおける直列抵抗成分を低減し、さらにコンタクト抵抗を低減することができる。 In the above-described embodiment, when the n-type and p- type semiconductor layers 15n and 15p are formed, the width of the opening of the metal mask 110, the thickness of the metal mask 110, or the film formation pressure is controlled to be flat. The region L and the film thickness reduction region T are formed by one film formation. Compared with the flat region L, the film thickness reduction region T has a relatively slow film formation rate, so that the impurity concentration is relatively increased as compared with the flat region L. As a result, the series resistance component in the film thickness reduction region T can be reduced, and the contact resistance can be further reduced.
　また、上述した実施形態では、メタルマスク１１０を用い、ｎ型及びｐ型半導体層１５ｎ、１５ｐの上に、導電率の異なる第１導電層１６１及び第２導電層１６２を１回の成膜で形成することができる。そのため、フォトリソグラフィー等を用いて第１導電層１６１及び第２導電層１６２を形成する場合と比べ、光電変換素子１の製造工程を短縮し、製造コストを低減することができる。 In the above-described embodiment, the metal mask 110 is used, and the first conductive layer 161 and the second conductive layer 162 having different conductivities are formed once on the n-type and p- type semiconductor layers 15n and 15p. Can be formed. Therefore, compared with the case where the 1st conductive layer 161 and the 2nd conductive layer 162 are formed using photolithography etc., the manufacturing process of the photoelectric conversion element 1 can be shortened, and manufacturing cost can be reduced.
　また、上述した実施形態では、シリコン基板１１の裏面に、熱酸化処理によって形成されたシリコンの非晶質膜がパッシベーション層１３として全面に形成される。そのため、面内分布は若干生じるものの、略均一な膜厚でシリコン基板１１の裏面を覆い、パッシベーションすることができる。また、上述した実施形態では、略均一なパッシベーション膜１３の上に、膜厚減少領域Ｔを有する半導体層（ｎ型半導体層１５ｎ、ｐ型半導体層１５ｐ）が離間して形成され、膜厚減少領域Ｔの上に電極（ｎ型電極１６ｎ、ｐ型電極１６ｐ）が形成されている。このように構成することで、シリコン基板１１の界面におけるパッシベーション性と低抵抗化を両立することができるため、より好ましい。 In the embodiment described above, an amorphous silicon film formed by thermal oxidation is formed on the entire back surface of the silicon substrate 11 as the passivation layer 13. Therefore, although the in-plane distribution is slightly generated, the back surface of the silicon substrate 11 can be covered with a substantially uniform film thickness and can be passivated. In the above-described embodiment, the semiconductor layers (n-type semiconductor layer 15n and p-type semiconductor layer 15p) having the film thickness reduction region T are formed on the substantially uniform passivation film 13 so as to reduce the film thickness. Electrodes (n-type electrode 16n and p-type electrode 16p) are formed on region T. Such a configuration is more preferable because it can achieve both passivation properties and low resistance at the interface of the silicon substrate 11.
　＜第２実施形態＞
　上述した第１実施形態では、ｎ型半導体層１５ｎ及びｐ型半導体層１５ｐがフラット領域Ｌを有する構成について説明したが、本実施形態では、ｎ型半導体層１５ｎ及びｐ型半導体層１５ｐにフラット領域Ｌが形成されていない構成について説明する。 Second Embodiment
In the first embodiment described above, the configuration in which the n-type semiconductor layer 15n and the p-type semiconductor layer 15p have the flat region L has been described. However, in the present embodiment, the flat region is added to the n-type semiconductor layer 15n and the p-type semiconductor layer 15p. A configuration in which L is not formed will be described.
　図１０は、本実施形態に係る光電変換素子の電極の断面図である。図１０の例において、電極２４ｎは、ｎ型半導体層２５ｎとｎ型電極２６ｎとを含む。ｎ型半導体層２５ｎとｎ型電極２６ｎはそれぞれ、第１実施形態におけるｎ型半導体層１５ｎ及びｎ型電極１６ｎと同様の材料で構成されている。図１０に示すように、ｎ型半導体層２５ｎは、膜厚減少領域Ｔ１とテーパー形状領域Ｒとを有する。 FIG. 10 is a cross-sectional view of the electrode of the photoelectric conversion element according to this embodiment. In the example of FIG. 10, the electrode 24n includes an n-type semiconductor layer 25n and an n-type electrode 26n. The n-type semiconductor layer 25n and the n-type electrode 26n are each made of the same material as the n-type semiconductor layer 15n and the n-type electrode 16n in the first embodiment. As shown in FIG. 10, the n-type semiconductor layer 25n has a film thickness reduction region T1 and a tapered region R.
　ｎ型半導体層２５ｎは、上述した第１実施形態と同様に、メタルマスク１１０を用いて形成される。メタルマスク１１０の厚さ、開口部の幅、又は成膜圧力を制御することにより、膜厚減少領域Ｔ１とテーパー形状領域Ｒが形成される。 The n-type semiconductor layer 25n is formed using the metal mask 110 as in the first embodiment described above. By controlling the thickness of the metal mask 110, the width of the opening, or the film formation pressure, the film thickness reduction region T1 and the tapered region R are formed.
　図１１は、メタルマスク１１０の開口幅Ｏを、第１実施形態と同様に４００μｍとし、成膜圧力を第１実施形態の成膜圧力よりも高く（例えば１５０Ｐａ）した場合のｎ型半導体層２５ｎの膜厚の測定結果を示している。 FIG. 11 shows the n-type semiconductor layer 25n when the opening width O of the metal mask 110 is 400 μm as in the first embodiment and the film formation pressure is higher than the film formation pressure of the first embodiment (for example, 150 Pa). The film thickness measurement results are shown.
　図１１に示すｎ型半導体層２５ｎの中心となる点Ｃ１０の膜厚と、第１実施形態におけるｎ型半導体層１５ｎの中心点Ｃの膜厚とは略同じである。図１１に示すように、ｎ型半導体層２５ｎのＣ１０からＫ１０までの領域の膜厚の減少率は、Ｋ１０からＫ２０までの領域の膜厚の減少率よりも小さい。図１１において、Ｃ１０からＫ１０までの各領域Ｔ１がｎ型半導体層２５ｎにおける膜厚減少領域である。 The film thickness of the point C10 that is the center of the n-type semiconductor layer 25n shown in FIG. 11 is substantially the same as the film thickness of the center point C of the n-type semiconductor layer 15n in the first embodiment. As shown in FIG. 11, the reduction rate of the film thickness in the region from C10 to K10 of the n-type semiconductor layer 25n is smaller than the reduction rate of the film thickness in the region from K10 to K20. In FIG. 11, each region T1 from C10 to K10 is a film thickness decreasing region in the n-type semiconductor layer 25n.
　なお、図１１に示すように、上記成膜条件下では、点Ｋ２０からｎ型半導体層２５ｎの外側に向けて略同じ膜厚となっており、テーパー形状領域Ｒが形成されていないが、成膜圧力やメタルマスク１１０とパッシベーション層１３との間の隙間の距離を調整することにより、テーパー形状領域Ｒを形成することができる。 As shown in FIG. 11, under the above film formation conditions, the film thickness is substantially the same from the point K20 toward the outside of the n-type semiconductor layer 25n, and the tapered region R is not formed. By adjusting the film pressure and the distance of the gap between the metal mask 110 and the passivation layer 13, the tapered region R can be formed.
　また、図１０に示すように、第１実施形態と同様、ｎ型半導体層２５ｎの膜厚減少領域Ｔ１内にｎ型電極２６ｎの両端部Ｚ１、Ｚ２が位置するようにｎ型電極２６ｎを形成する。このように構成することにより、図８の（ａ）に示したｎ型電極１６１ｎの場合と比べ、直列抵抗成分を低減することができる。よって、ｎ型及びｐ型半導体層１５ｎ、１５ｐにおいて、フラット領域Ｌが形成されていない場合でも、膜厚減少領域Ｔ１の上に、ｎ型電極１６ｎ及びｐ型電極１６ｐの少なくとも一部が形成されていれば、低抵抗化を図ることができる。 Further, as shown in FIG. 10, the n-type electrode 26n is formed so that both end portions Z1 and Z2 of the n-type electrode 26n are located in the film thickness decreasing region T1 of the n-type semiconductor layer 25n as in the first embodiment. To do. By configuring in this way, the series resistance component can be reduced as compared with the case of the n-type electrode 161n shown in FIG. Therefore, even when the flat region L is not formed in the n-type and p- type semiconductor layers 15n and 15p, at least a part of the n-type electrode 16n and the p-type electrode 16p is formed on the film thickness reduction region T1. If so, the resistance can be reduced.
　（製造方法）
　本実施形態における光電変換素子は、上述した第１実施形態と同様の製造方法によって形成される。つまり、本実施形態におけるｎ型半導体層２５ｎ及びｐ型半導体層（図示略）は、図６Ｂ、６Ｃに示すメタルマスク１１０Ａ，１１０Ｂを用い、成膜圧力、メタルマスク１１０の厚さＭ、メタルマスク１１０の開口幅Ｏ等を適宜調整することにより形成することができる。 (Production method)
The photoelectric conversion element in this embodiment is formed by the same manufacturing method as in the first embodiment described above. That is, the n-type semiconductor layer 25n and the p-type semiconductor layer (not shown) in the present embodiment use the metal masks 110A and 110B shown in FIGS. 6B and 6C, the film formation pressure, the thickness M of the metal mask 110, and the metal mask. It can be formed by appropriately adjusting the opening width O of 110 or the like.
　＜第３実施形態＞
　上述した第１実施形態では、図１におけるパッシベーション層１３をシリコンの熱酸化膜で構成する例を説明したが、本実施形態では、パッシベーション層１３として、水素を含有する真性（ｉ型）非晶質半導体層で構成する例について説明する。 <Third Embodiment>
In the first embodiment described above, the example in which the passivation layer 13 in FIG. 1 is formed of a thermal oxide film of silicon has been described. However, in this embodiment, an intrinsic (i-type) amorphous material containing hydrogen is used as the passivation layer 13. An example in which a high-quality semiconductor layer is used will be described.
　ｉ型非晶質半導体層は、例えば、ｉ型非晶質シリコン、ｉ型非晶質シリコンゲルマニウム、ｉ型非晶質ゲルマニウム、ｉ型非晶質シリコンカーバイド、ｉ型非晶質シリコンナイトライド、ｉ型非晶質シリコンオキシナイトライド、ｉ型非晶質シリコンオキサイド、又はｉ型非晶質シリコンカーボンオキサイド等を用いてもよい。 The i-type amorphous semiconductor layer includes, for example, i-type amorphous silicon, i-type amorphous silicon germanium, i-type amorphous germanium, i-type amorphous silicon carbide, i-type amorphous silicon nitride, i-type amorphous silicon oxynitride, i-type amorphous silicon oxide, i-type amorphous silicon carbon oxide, or the like may be used.
　ｉ型非晶質半導体層の厚さは、例えば、１～１０ｎｍである。このように、ｉ型非晶質半導体層をｉ型非晶質シリコンオキシナイトライドや、ｉ型非晶質シリコンナイトライドで形成することにより、ｉ型非晶質半導体層上に形成されるｐ型半導体層１５ｐに含有されるボロン等の不純物がシリコン基板１１に拡散することを抑制することができる。また、ｉ型非晶質半導体層によって、シリコン基板１１とｎ型半導体層１５ｎとの間の界面、及びシリコン基板１１とｐ型半導体層１５ｐとの間の界面の欠陥を低減することができる。 The thickness of the i-type amorphous semiconductor layer is, for example, 1 to 10 nm. In this way, by forming the i-type amorphous semiconductor layer from i-type amorphous silicon oxynitride or i-type amorphous silicon nitride, p formed on the i-type amorphous semiconductor layer is formed. Impurities such as boron contained in the type semiconductor layer 15p can be prevented from diffusing into the silicon substrate 11. The i-type amorphous semiconductor layer can reduce defects at the interface between the silicon substrate 11 and the n-type semiconductor layer 15n and the interface between the silicon substrate 11 and the p-type semiconductor layer 15p.
　（光電変換素子の製造方法）
　本実施形態では、第１実施形態におけるパッシベーション層１３として、ｉ型非晶質シリコン層を形成する。ｉ型非晶質シリコン層は、ＡＲＣ１２を形成する前に形成してもよいし、ＡＲＣ１２を形成した後に形成してもよい。また、ＡＲＣ１２を、ｉ型非晶質シリコン層（例えば５ｎｍ）、ｎ型非晶質シリコン層（例えば８ｎｍ）、シリコンの窒化膜（例えば６０ｎｍ）をこの順に積層した３層構造としてもよい。 (Manufacturing method of photoelectric conversion element)
In this embodiment, an i-type amorphous silicon layer is formed as the passivation layer 13 in the first embodiment. The i-type amorphous silicon layer may be formed before the ARC 12 is formed, or may be formed after the ARC 12 is formed. The ARC 12 may have a three-layer structure in which an i-type amorphous silicon layer (for example, 5 nm), an n-type amorphous silicon layer (for example, 8 nm), and a silicon nitride film (for example, 60 nm) are stacked in this order.
　この場合、まず、シリコン基板１１の受光面に、例えば、プラズマＣＶＤを用いて、非晶質シリコン半導体層（ｉ型非晶質シリコン層とｎ型非晶質シリコン層）を形成する。続いて、同じプラズマＣＶＤ装置において、反応ガスとしてアンモニアガスを追加し、シリコンの窒化物又は酸窒化物（ＳｉＮ、ＳｉＯＮ）からなるシリコンの窒化膜を形成する。これにより、真空雰囲気で上記３層を連続で成膜することができる。 In this case, first, an amorphous silicon semiconductor layer (i-type amorphous silicon layer and n-type amorphous silicon layer) is formed on the light receiving surface of the silicon substrate 11 by using, for example, plasma CVD. Subsequently, in the same plasma CVD apparatus, ammonia gas is added as a reaction gas to form a silicon nitride film made of silicon nitride or oxynitride (SiN, SiON). Thereby, the three layers can be continuously formed in a vacuum atmosphere.
　さらに、プラズマＣＶＤ装置の反応室において真空状態でシリコン基板１１を反転し、シリコン基板１１の裏面にパッシベーション層１３として、上記ｉ型非晶質シリコン層を成膜する。ｉ型非晶質シリコン層は、プラズマＣＶＤを用いて、シリコン基板１１の裏面の略全面に形成される。プラズマＣＶＤ装置が備える反応室に導入される反応ガスは、シランガス及び水素ガスである。この場合、水素ガス流量は０～１００ｓｃｃｍ、シランガス流量は４０ｓｃｃｍである。シリコン基板１１の温度は、１３０～１８０℃である。また、反応室内の圧力は、４０～１２０Ｐａであり、ＲＦパワー密度は５～１５ｍＷ／ｃｍ２である。 Further, the silicon substrate 11 is inverted in a vacuum state in the reaction chamber of the plasma CVD apparatus, and the i-type amorphous silicon layer is formed as the passivation layer 13 on the back surface of the silicon substrate 11. The i-type amorphous silicon layer is formed on substantially the entire back surface of the silicon substrate 11 using plasma CVD. The reaction gas introduced into the reaction chamber provided in the plasma CVD apparatus is silane gas and hydrogen gas. In this case, the hydrogen gas flow rate is 0 to 100 sccm, and the silane gas flow rate is 40 sccm. The temperature of the silicon substrate 11 is 130 to 180 ° C. The pressure in the reaction chamber is 40 to 120 Pa, and the RF power density is 5 to 15 mW / cm 2 .
　シリコン基板１１の裏面の略全面に成膜されたｉ型非晶質シリコン層の膜厚は、例えば８ｎｍである。ｉ型非晶質シリコン層の膜厚は、２～２０ｎｍ程度が好ましく、より好ましくは３～１２ｎｍ程度である。 The film thickness of the i-type amorphous silicon layer formed on substantially the entire back surface of the silicon substrate 11 is, for example, 8 nm. The film thickness of the i-type amorphous silicon layer is preferably about 2 to 20 nm, more preferably about 3 to 12 nm.
　次に、プラズマＣＶＤ装置の反応室において真空状態で、パッシベーション層１３の上の適切な位置にメタルマスク１１０を配置する。そして、第１実施形態と同様の成膜条件の下、ｎ型及びｐ型半導体層１５ｎ、１５ｐと、ｎ型及びｐ型電極１６ｎ、１６ｐを順に成膜する。このようにすることにより、真空雰囲気内で光電変換素子を作製することができる。 Next, the metal mask 110 is disposed at an appropriate position on the passivation layer 13 in a vacuum state in the reaction chamber of the plasma CVD apparatus. Then, the n-type and p- type semiconductor layers 15n and 15p and the n-type and p- type electrodes 16n and 16p are sequentially formed under the same film formation conditions as in the first embodiment. By doing in this way, a photoelectric conversion element can be produced in a vacuum atmosphere.
　なお、シリコン基板１１の裏面にパッシベーション層１３を成膜する際の熱履歴によって受光面のパッシベーション性が低下する現象が生じる場合がある。シリコン基板１１の裏面を成膜する前に、受光面における非晶質シリコン半導体層上にシリコンの窒化膜を形成しておくことで、シリコンの窒化物膜によって上記パッシベーション性の低下を抑制することができる。 It should be noted that there may be a phenomenon in which the passivation property of the light receiving surface is deteriorated due to the thermal history when the passivation layer 13 is formed on the back surface of the silicon substrate 11. Before forming the back surface of the silicon substrate 11, a silicon nitride film is formed on the amorphous silicon semiconductor layer on the light receiving surface, thereby suppressing the above-described deterioration of the passivation property by the silicon nitride film. Can do.
　本実施形態では、パッシベーション層１３としてｉ型非晶質シリコン層をシリコン基板１１の裏面の略全面に１回の成膜で形成することができる。そのため、面内分布は若干生じるものの、略均一な膜厚でシリコン基板１１の裏面を覆い、パッシベーションすることができる。また、上述した実施形態では、略均一なパッシベーション膜１３の上に、膜厚減少領域Ｔを有する半導体層（ｎ型半導体層１５ｎ、ｐ型半導体層１５ｐ）が離間して形成され、膜厚減少領域Ｔの上に電極（ｎ型電極１６ｎ、ｐ型電極１６ｐ）が形成されている。このように構成することで、シリコン基板１１の界面におけるパッシベーション性と低抵抗化を両立することができるため、より好ましい。 In this embodiment, an i-type amorphous silicon layer can be formed as the passivation layer 13 on the substantially entire back surface of the silicon substrate 11 by a single film formation. Therefore, although the in-plane distribution is slightly generated, the back surface of the silicon substrate 11 can be covered with a substantially uniform film thickness and can be passivated. In the above-described embodiment, the semiconductor layers (n-type semiconductor layer 15n and p-type semiconductor layer 15p) having the film thickness reduction region T are formed on the substantially uniform passivation film 13 so as to reduce the film thickness. Electrodes (n-type electrode 16n and p-type electrode 16p) are formed on region T. Such a configuration is more preferable because it can achieve both passivation properties and low resistance at the interface of the silicon substrate 11.
　＜第４実施形態＞
　上述した第１実施形態から第３実施形態では、１層のパッシベーション層１３を形成する場合を例に説明したが、本実施形態では、２層のパッシベーション層１３を形成する場合を例に説明する。なお、本実施形態では、パッシベーション層１３として、上述した第３実施形態と同様にｉ型非晶質シリコン層を用いる。 <Fourth embodiment>
In the first to third embodiments described above, the case where the single passivation layer 13 is formed has been described as an example. However, in the present embodiment, the case where the two passivation layers 13 are formed is described as an example. . In the present embodiment, an i-type amorphous silicon layer is used as the passivation layer 13 as in the third embodiment described above.
　図１２は、本実施形態に係る光電変換素子１００の断面を示す模式図である。また、図１３は、図１２に示すｎ型半導体層１５ｎが形成された領域を拡大した模式図である。図１２及び図１３において、第１実施形態と同様の構成には、第１実施形態と同じ符号を付している。 FIG. 12 is a schematic view showing a cross section of the photoelectric conversion element 100 according to this embodiment. FIG. 13 is an enlarged schematic view of a region where the n-type semiconductor layer 15n shown in FIG. 12 is formed. In FIG.12 and FIG.13, the code | symbol same as 1st Embodiment is attached | subjected to the structure similar to 1st Embodiment.
　図１２に示すように、パッシベーション層１３の上において、ｎ型半導体層１５ｎ、ｐ型半導体層１５ｐが形成される位置にパッシベーション層１３と同じｉ型非晶質シリコン層からなるパッシベーション層１３１が形成されている。以下、パッシベーション層１３を第１パッシベーション層１３、パッシベーション層１３１を第２パッシベーション層１３１と称する。 As shown in FIG. 12, a passivation layer 131 made of the same i-type amorphous silicon layer as the passivation layer 13 is formed on the passivation layer 13 at a position where the n-type semiconductor layer 15n and the p-type semiconductor layer 15p are formed. Has been. Hereinafter, the passivation layer 13 is referred to as a first passivation layer 13 and the passivation layer 131 is referred to as a second passivation layer 131.
　図１３に示すように、ｎ型半導体層１５ｎは、膜厚減少領域Ｔを有し、ｎ型半導体層１５ｎの下に形成される第２パッシベーション層１３１も膜厚減少領域ｔを有する。また、図示を省略するが、ｐ型半導体層１５ｐも同様に、膜厚減少領域Ｔを有し、ｐ型半導体層１５ｐの下に形成される第２パッシベーション層１３１も膜厚減少領域ｔを有する。 As shown in FIG. 13, the n-type semiconductor layer 15n has a film thickness reduction region T, and the second passivation layer 131 formed under the n-type semiconductor layer 15n also has a film thickness reduction region t. Although not shown, the p-type semiconductor layer 15p similarly has a film thickness reduction region T, and the second passivation layer 131 formed under the p-type semiconductor layer 15p also has a film thickness reduction region t. .
　本実施形態では、プラズマＣＶＤを用いて、シリコン基板１１の裏面の略全面に、ｉ型非晶質シリコン層からなる第１パッシベーション層１３を成膜する。第１パッシベーション層１３の膜厚は約５ｎｍである。続いて、第１パッシベーション層１３の上にメタルマスク１１０Ｄ（図示略）を配置する。メタルマスク１１０Ｄは、開口部を有し、ｎ型半導体層１５ｎを形成する部分に開口部が位置するように、第１パッシベーション層１３の上に配置される。そして、ｉ型非晶質シリコン層からなる第２パッシベーション層１３１を成膜し、続けて、ｎ型非晶質シリコン層からなるｎ型半導体層１５ｎを成膜する。 In the present embodiment, the first passivation layer 13 made of an i-type amorphous silicon layer is formed on substantially the entire back surface of the silicon substrate 11 using plasma CVD. The film thickness of the first passivation layer 13 is about 5 nm. Subsequently, a metal mask 110 </ b> D (not shown) is disposed on the first passivation layer 13. The metal mask 110D has an opening and is disposed on the first passivation layer 13 so that the opening is located in a portion where the n-type semiconductor layer 15n is formed. Then, a second passivation layer 131 made of an i-type amorphous silicon layer is formed, and then an n-type semiconductor layer 15n made of an n-type amorphous silicon layer is formed.
　次に、メタルマスク１１０Ｄを除去し、シリコン基板１１上に、ｎ型半導体層１５ｎを覆うメタルマスク１１０Ｅ（図示略）を配置する。メタルマスク１１０Ｅは、開口部を有し、ｐ型半導体層１５ｐを形成する部分に開口部が位置するように配置される。そして、ｉ型非晶質シリコン層からなる第２パッシベーション層１３１を成膜し、続けて、ｐ型非晶質シリコン層からなるｐ型半導体層１５ｐを成膜する。 Next, the metal mask 110D is removed, and a metal mask 110E (not shown) covering the n-type semiconductor layer 15n is disposed on the silicon substrate 11. The metal mask 110E has an opening, and is arranged such that the opening is located in a portion where the p-type semiconductor layer 15p is formed. Then, a second passivation layer 131 made of an i-type amorphous silicon layer is formed, and then a p-type semiconductor layer 15p made of a p-type amorphous silicon layer is formed.
　なお、ｎ型半導体層１５ｎの面内方向の幅は例えば約４００μｍであり、ｐ型半導体層１５ｐの面内方向の幅は例えば約１２００μｍである。また、ｎ型半導体層１５ｎの下に形成される第２パッシベーション層１３１の膜厚は例えば約１ｎｍであり、ｎ型半導体層１５ｎの膜厚は例えば約１３ｎｍである。ｐ型半導体層１５ｐの下に形成される第２パッシベーション層１３１の膜厚は例えば約３ｎｍであり、ｐ型半導体層１５ｐの膜厚は例えば約１５ｎｍである。また、この例において、第１パッシベーション層１３の膜厚は、約５ｎｍである。 The width in the in-plane direction of the n-type semiconductor layer 15n is, for example, about 400 μm, and the width in the in-plane direction of the p-type semiconductor layer 15p is, for example, about 1200 μm. The film thickness of the second passivation layer 131 formed under the n-type semiconductor layer 15n is, for example, about 1 nm, and the film thickness of the n-type semiconductor layer 15n is, for example, about 13 nm. The film thickness of the second passivation layer 131 formed under the p-type semiconductor layer 15p is, for example, about 3 nm, and the film thickness of the p-type semiconductor layer 15p is, for example, about 15 nm. In this example, the thickness of the first passivation layer 13 is about 5 nm.
　メタルマスクの開口幅によって半導体層における膜厚減少領域Ｔの幅や膜厚の減少量が変動する。シリコン基板１１にｎ型の非晶質シリコンを用いている場合は、ｎ型半導体層１５ｎの低抵抗化が重要となる。そのため、ｐ型半導体層１５ｐの膜厚減少領域Ｔの幅よりｎ型半導体層１５ｎの膜厚減少領域Ｔの幅が大きいことが好ましい。ｐ型の非晶質シリコンをシリコン基板１１として用いる場合には、上記とは逆に、ｎ型半導体層１５ｎの膜厚減少領域Ｔの幅よりｐ型半導体層１５ｐの膜厚減少領域Ｔの幅が大きいことが好ましい。また、第２パッシベーション層１３１も膜厚減少領域ｔを有することで、第２パッシベーション層１３１に膜厚減少領域ｔを有しない場合と比べ、膜厚減少領域ｔの部分における膜厚が薄くなるため、より低抵抗化することができる。 The width of the film thickness reduction region T in the semiconductor layer and the amount of film thickness reduction vary depending on the opening width of the metal mask. When n-type amorphous silicon is used for the silicon substrate 11, it is important to reduce the resistance of the n-type semiconductor layer 15n. Therefore, it is preferable that the width of the film thickness reduction region T of the n-type semiconductor layer 15n is larger than the width of the film thickness reduction region T of the p-type semiconductor layer 15p. When p-type amorphous silicon is used as the silicon substrate 11, contrary to the above, the width of the thickness reduction region T of the p-type semiconductor layer 15p is larger than the width of the thickness reduction region T of the n-type semiconductor layer 15n. Is preferably large. In addition, since the second passivation layer 131 also has the film thickness reduction region t, the film thickness in the portion of the film thickness reduction region t becomes thinner compared to the case where the second passivation layer 131 does not have the film thickness reduction region t. Therefore, the resistance can be further reduced.
　本実施形態では、第１パッシベーション層１３の膜厚（約５ｎｍ）よりも、ｎ型半導体層１５ｎの下に形成される第２パッシベーション層１３１の膜厚（約１ｎｍ）とｐ型半導体層１５ｐの下に形成される第２パッシベーション層１３１の膜厚（約３ｎｍ）の方が薄い。第１パッシベーション層１３と第２パッシベーション層１３１の合計膜厚を１０ｎｍとして、第１パッシベーション層１３の膜厚Ｈ１と第２パッシベーション層１３１の膜厚Ｈ２の比率（Ｈ１／Ｈ２）を変化させて光電変換効率を測定した。図１４は、第１パッシベーション層１３と第２パッシベーション層１３１の膜厚の比率（Ｈ１／Ｈ２）とその光電変換効率の測定結果とを示す図である。 In the present embodiment, the thickness (about 1 nm) of the second passivation layer 131 formed below the n-type semiconductor layer 15n and the thickness of the p-type semiconductor layer 15p are larger than the thickness (about 5 nm) of the first passivation layer 13. The film thickness (about 3 nm) of the second passivation layer 131 formed below is thinner. The total film thickness of the first passivation layer 13 and the second passivation layer 131 is 10 nm, and the ratio (H1 / H2) of the film thickness H1 of the first passivation layer 13 to the film thickness H2 of the second passivation layer 131 is changed. Conversion efficiency was measured. FIG. 14 is a diagram showing the ratio of film thicknesses (H1 / H2) between the first passivation layer 13 and the second passivation layer 131 and the measurement result of the photoelectric conversion efficiency.
　図１４に示すように、膜厚比率が１．０以上において光電変換効率が２４．０％以上となっており、膜厚比率が０．２５のときに光電変換効率が２２．３％と最も低くなった。これにより、第１パッシベーション層１３と第２パッシベーション層１３１の合計膜厚で光電変換効率が決まるのではなく、第１パッシベーション層１３の膜厚が、第２パッシベーション層１３１の膜厚より厚い方が、光電変換特性が良くなることが分かる。 As shown in FIG. 14, when the film thickness ratio is 1.0 or more, the photoelectric conversion efficiency is 24.0% or more, and when the film thickness ratio is 0.25, the photoelectric conversion efficiency is 22.3%. It became low. Thereby, the photoelectric conversion efficiency is not determined by the total film thickness of the first passivation layer 13 and the second passivation layer 131, but the film thickness of the first passivation layer 13 is larger than the film thickness of the second passivation layer 131. It can be seen that the photoelectric conversion characteristics are improved.
　よって、本実施形態のように、第１パッシベーション層１３がシリコン基板１１の略全面に形成され、第１パッシベーション層１３上の一部に第２パッシベーション層１３１を形成する場合には、ｎ型半導体層１５ｎ及びｐ型半導体層１５ｐの少なくとも一方の半導体層の下に形成される第２パッシベーション層１３１の膜厚を、第１パッシベーション層１３の膜厚よりも薄くすることにより、光電変換素子の特性を向上させることができる。 Therefore, when the first passivation layer 13 is formed on substantially the entire surface of the silicon substrate 11 and the second passivation layer 131 is formed on a part of the first passivation layer 13 as in this embodiment, the n-type semiconductor is used. By making the film thickness of the second passivation layer 131 formed below at least one of the semiconductor layer 15n and the p-type semiconductor layer 15p smaller than the film thickness of the first passivation layer 13, the characteristics of the photoelectric conversion element Can be improved.
　つまり、シリコン基板１１の略全面に形成された第１パッシベーション層１３の上の一部に第２パッシベーション層１３１を形成する場合には、第２パッシベーション層１３１の膜厚を第１パッシベーション層１３よりも薄くすることが好ましい。また、本施形態のように、２層のパッシベーション層を形成する場合には、ｎ型半導体層１５ｎの下に形成される第２パッシベーション層１３１においても膜厚減少領域が形成されていることが、低抵抗化の観点からより好ましい。 That is, in the case where the second passivation layer 131 is formed on a part of the first passivation layer 13 formed on the substantially entire surface of the silicon substrate 11, the thickness of the second passivation layer 131 is made larger than that of the first passivation layer 13. It is preferable to reduce the thickness. In addition, when two passivation layers are formed as in this embodiment, a film thickness reduction region is also formed in the second passivation layer 131 formed under the n-type semiconductor layer 15n. From the viewpoint of reducing resistance, it is more preferable.
　＜第５実施形態＞
　上述した第１実施形態～第４実施形態では、ｎ型半導体層１５ｎとｐ型半導体層１５ｐの少なくとも一方の半導体層における膜厚減少領域Ｔは、当該半導体層の中心から外側に向かって膜厚が減少する領域の例を説明したが、膜厚減少領域は以下のように構成されていてもよい。 <Fifth Embodiment>
In the first to fourth embodiments described above, the film thickness reduction region T in at least one of the n-type semiconductor layer 15n and the p-type semiconductor layer 15p has a film thickness from the center of the semiconductor layer toward the outside. Although the example of the area | region where this reduces is demonstrated, the film thickness reduction area | region may be comprised as follows.
　図１５は、本実施形態に係る光電変換素子の断面を示す模式図である。図１５に示すように、光電変換素子１０１におけるｎ型及びｐ型半導体層１５ｎ、１５ｐの少なくとも一方は、膜厚減少領域として、膜厚が最大となる点Ｃｍから各半導体層の内側に向かって膜厚が減少する領域Ｔ２を有する。膜厚減少領域Ｔ２は、膜厚が最大となる点Ｃｍ（第１の点）から、半導体層の面内方向において膜厚の変化率の符号が負から正に変化する点Ｃｎ（第２の点）までの領域である。 FIG. 15 is a schematic view showing a cross section of the photoelectric conversion element according to the present embodiment. As shown in FIG. 15, at least one of the n-type and p-type semiconductor layers 15 n and 15 p in the photoelectric conversion element 101 is a film thickness decreasing region from the point Cm at which the film thickness is maximum toward the inside of each semiconductor layer. A region T2 where the film thickness decreases is provided. The film thickness reduction region T2 is a point Cn (second point) at which the sign of the rate of change of film thickness changes from negative to positive in the in-plane direction of the semiconductor layer from the point Cm (first point) at which the film thickness becomes maximum. This is the area up to point).
　すなわち、膜厚減少領域は、シリコン基板１１上に成膜される一の薄膜において、膜厚が最大となる点を第１の点とし、当該薄膜の面内方向において膜厚の減少率が第１の減少率から第１の減少率よりも大きい第２の減少率に変化する点、または、当該薄膜の面内方向において膜厚の変化率の符号が負から正に変化する点を第２の点とした場合、当該薄膜の面内方向における第１の点から第２の点までの領域である。 That is, in the film thickness reduction region, the point where the film thickness is maximum in one thin film formed on the silicon substrate 11 is the first point, and the film thickness reduction rate is the first in the in-plane direction of the thin film. The second point is that the rate of change from the rate of 1 changes to a second rate of decrease that is greater than the first rate of decrease or the sign of the rate of change of film thickness changes from negative to positive in the in-plane direction of the thin film. Is the region from the first point to the second point in the in-plane direction of the thin film.
　＜第６実施形態＞
　本実施形態では、上述した第１実施形態から第５実施形態に係る光電変換素子をモジュール化する場合について説明する。 <Sixth Embodiment>
In the present embodiment, a case will be described in which the photoelectric conversion elements according to the first to fifth embodiments described above are modularized.
　光電変換素子をモジュール化する場合には、図１６Ａに示すように、ｎ型半導体層１５ｎ及びｐ型半導体層１５ｐを覆い、ｎ型電極１６ｎ及びｐ型電極１６ｐの上で離間するように、絶縁膜１７を形成する。絶縁膜１７は、例えば、Ｓｉ、Ａｌ、Ｔｉ、ジルコニア等の酸化膜、Ｓｉ又はＡｌの窒化物膜、Ｓｉ又はＡｌの酸窒化物膜等の無機絶縁膜を用いてもよい。また、絶縁膜１７は、例えば、イミド系樹脂、エポキシ樹脂、フッ素樹脂、ポリカーボネート、液晶ポリマー等の有機物であってもよい。なお、イミド系樹脂としては、例えばポリイミドでもよい。フッ素樹脂としては、例えばポリテトラフルオロエチレン（ＰＴＦＥ）でもよい。また、絶縁膜１７は、レジストをスクリーン印刷で形成してもよいし、シリコン樹脂等を用いてもよい。 When the photoelectric conversion element is modularized, as shown in FIG. 16A, the n-type semiconductor layer 15n and the p-type semiconductor layer 15p are covered so as to be separated from each other on the n-type electrode 16n and the p-type electrode 16p. A film 17 is formed. As the insulating film 17, for example, an oxide film such as Si, Al, Ti, zirconia, an inorganic insulating film such as a nitride film of Si or Al, or an oxynitride film of Si or Al may be used. The insulating film 17 may be an organic material such as an imide resin, an epoxy resin, a fluororesin, a polycarbonate, or a liquid crystal polymer. The imide resin may be polyimide, for example. As the fluororesin, for example, polytetrafluoroethylene (PTFE) may be used. Further, the insulating film 17 may be formed by forming a resist by screen printing, or using a silicon resin or the like.
　次に、図１６Ａに示す光電変換素子１０２と電気的に接合される外部配線回路（以下、配線シートと称する）について説明する。図１６Ｂは、本実施形態における配線シートの一部を拡大した模式図である。 Next, an external wiring circuit (hereinafter referred to as a wiring sheet) that is electrically joined to the photoelectric conversion element 102 shown in FIG. 16A will be described. FIG. 16B is an enlarged schematic view of a part of the wiring sheet in the present embodiment.
　配線シート２００は、絶縁基材２０１の上に、配線材２０２ａ、２０２ｂが形成されて構成されている。絶縁基材２０１は、絶縁性の材料であればよく、例えば、ポリエチレンテレフタレート（ＰＥＴ）、ポリエチレンナフタレート（ＰＥＮ）、ポリフェニレンサルファイド（ＰＰＳ）、ポリビニルフルオライド（ＰＶＦ）、ポリイミド等を用いてもよい。絶縁基材２０１の膜厚は特に限定されないが、２５μｍ以上、１５０μｍ以下程度が好ましい。また、絶縁基材２０１は、１層構造でもよいし、２層以上の多層構造であってもよい。 The wiring sheet 200 is configured by forming wiring members 202 a and 202 b on an insulating base material 201. The insulating base material 201 may be any insulating material, and for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyphenylene sulfide (PPS), polyvinyl fluoride (PVF), polyimide, or the like may be used. . The thickness of the insulating substrate 201 is not particularly limited, but is preferably about 25 μm or more and 150 μm or less. The insulating base 201 may have a single layer structure or a multilayer structure of two or more layers.
　配線材２０２ａ、２０２ｂは、導電性の材料であればよく、例えば、Ｃｕ、Ａｌ、Ａｇ等のいずれかの金属でもよいし、又はこれらいずれかの金属を主成分とする合金等であってもよい。配線材２０２ａ、２０２ｂの膜厚は特に限定されないが、例えば、１０μｍ以上、８０μｍ以下が好ましい。配線材２０２ａ、２０２ｂの膜厚が１０μｍ以下になると配線抵抗が高くなることがある。また、８０μｍ以上になると、配線シート２００と光電変換素子１０１とを貼り合せる際に熱をかける必要がある。配線材２０２ａ、２０２ｂと、光電変換素子１０１のシリコン基板１１の熱膨張係数の違いなどにより、配線シート２００の反りが大きくなるため、配線材２０２ａ、２０２ｂの膜厚は８０μｍ以下がより好ましい。 The wiring members 202a and 202b may be any conductive material, and may be any metal such as Cu, Al, or Ag, or an alloy containing any one of these metals as a main component. Good. The film thickness of the wiring members 202a and 202b is not particularly limited, but is preferably 10 μm or more and 80 μm or less, for example. When the thickness of the wiring members 202a and 202b is 10 μm or less, the wiring resistance may increase. Moreover, when it becomes 80 micrometers or more, it is necessary to apply heat when bonding the wiring sheet 200 and the photoelectric conversion element 101 together. Since the warpage of the wiring sheet 200 increases due to the difference in thermal expansion coefficient between the wiring materials 202a and 202b and the silicon substrate 11 of the photoelectric conversion element 101, the film thickness of the wiring materials 202a and 202b is more preferably 80 μm or less.
　配線材２０２ａ、２０２ｂの表面の一部には、ニッケル、金、白金、パラジウム、銀、錫、インジウム、ＩＴＯなどの導電性材料が形成されてもよい。このように構成することで、配線材２０２ａ、２０２ｂと光電変換素子１０１のｎ型及びｐ型電極１６ｎ、１６ｐとの電気的接続が良好となり、配線材２０２ａ、２０２ｂの耐候性が向上する。配線材２０２ａ、２０２ｂは、１層構造でもよいし、２層以上の多層構造であってもよい。 A conductive material such as nickel, gold, platinum, palladium, silver, tin, indium, or ITO may be formed on part of the surface of the wiring members 202a and 202b. With this configuration, the electrical connection between the wiring members 202a and 202b and the n-type and p- type electrodes 16n and 16p of the photoelectric conversion element 101 is improved, and the weather resistance of the wiring members 202a and 202b is improved. The wiring members 202a and 202b may have a single layer structure or a multilayer structure of two or more layers.
　なお、配線シート２００の形状及び配線材２０２ａ、２０２ｂのパターンは、図１６Ｂに示すものに限定されない。 Note that the shape of the wiring sheet 200 and the patterns of the wiring materials 202a and 202b are not limited to those shown in FIG. 16B.
　配線シート２００の配線材２０２ａ、２０２ｂと、光電変換素子１０２の裏面に形成されたｎ型電極１６ｎ及びｐ型電極１６ｐとが接合される。例えば、図１６Ｂに示す破線枠２００Ａにおける配線材２０２ａは光電変換素子１０１のｐ型電極１６ｐと接合され、配線材２０２ｂは光電変換素子１０２のｎ型電極１６ｎと接合される。また、破線枠２００Ｂにおける配線材２０２ａは光電変換素子１０１のｎ型電極１６ｎと接合され、配線材２０２ｂはｐ型電極１６ｐと接合される。つまり、図１６ＢにおいてＹ軸方向に隣接する光電変換素子１０２の同じ導電型の各電極は、互いに異なる配線材と接合される。 The wiring members 202 a and 202 b of the wiring sheet 200 are joined to the n-type electrode 16 n and the p-type electrode 16 p formed on the back surface of the photoelectric conversion element 102. For example, the wiring material 202a in the broken line frame 200A shown in FIG. 16B is joined to the p-type electrode 16p of the photoelectric conversion element 101, and the wiring material 202b is joined to the n-type electrode 16n of the photoelectric conversion element 102. Further, the wiring material 202a in the broken line frame 200B is joined to the n-type electrode 16n of the photoelectric conversion element 101, and the wiring material 202b is joined to the p-type electrode 16p. That is, in FIG. 16B, each electrode of the same conductivity type of the photoelectric conversion element 102 adjacent in the Y-axis direction is joined to a different wiring material.
　このようにして接合することにより、各光電変換素子１０２は、電気的に直列に接続される。これにより、光電変換素子１０２に太陽光が入射して発生した電流は、配線シート２００における配線材２０２ａ、２０２ｂを通じて外部に出力することができる。 By joining in this way, each photoelectric conversion element 102 is electrically connected in series. Thereby, the electric current generated by the incidence of sunlight on the photoelectric conversion element 102 can be output to the outside through the wiring members 202a and 202b in the wiring sheet 200.
　光電変換素子１０２のｎ型電極１６ｎ及びｐ型電極１６ｐと、配線シート２００の配線材２０２ａ、２０２ｂとを接合する方法は特に限定されないが、以下の方法を用いることができる。例えば、半田樹脂、半田、導電性接着剤、熱硬化型銀ペースト、低温効果型銅ペースト、異方性導電フィルム（ＡＣＦ：Ａｎｉｓｏｔｒｏｐｉｃ　Ｃｏｎｄｕｃｔｉｖｅ　Ｆｉｌｍ）、異方性導電ペースト（ＡＣＰ：Ａｎｉｓｏｔｒｏｐｉｃ　Ｃｏｎｄｕｃｔｉｖｅ　Ｐａｓｔｅ）、及び絶縁性接着剤（ＮＣＰ：Ｎｏｎ　Ｃｏｎｄｕｃｔｉｖｅ　Ｐａｓｔｅ）のいずれか１種類以上の導電性接着剤を用いて接合してもよい。例えば、半田樹脂は、タムラ科研（株）製のＴＣＡＰ－５４０１－２７等を用いてもよい。また、絶縁性接着剤は、エポキシ樹脂、アクリル樹脂、及びウレタン樹脂等のいずれかを用いてもよいし、熱硬化型又は光硬化型の樹脂を用いてもよい。また、導電性接着剤は、錫及びビスマスの少なくとも一方を含む半田粒子などを用いてもよい。より好ましくは、錫と、ビスマス、インジウム、銀等のいずれかとの合金であることが好ましい。このように構成することで、半田融点を抑えることができ、低温での接着プロセスが可能となる。 The method of joining the n-type electrode 16n and the p-type electrode 16p of the photoelectric conversion element 102 and the wiring members 202a and 202b of the wiring sheet 200 is not particularly limited, but the following method can be used. For example, solder resin, solder, conductive adhesive, thermosetting silver paste, low-temperature effect copper paste, anisotropic conductive film (ACF: Anisotropic Conductive Film), anisotropic conductive paste (ACP: Anisotropic Conductive Paste), Alternatively, one or more kinds of conductive adhesives of NCP and Non Inductive Paste (NCP) may be used for bonding. For example, TCAP-5401-27 manufactured by Tamura Kaken Co., Ltd. may be used as the solder resin. In addition, as the insulating adhesive, any of an epoxy resin, an acrylic resin, a urethane resin, or the like may be used, or a thermosetting or photocurable resin may be used. The conductive adhesive may use solder particles containing at least one of tin and bismuth. More preferably, it is an alloy of tin and any of bismuth, indium, silver and the like. With this configuration, the melting point of solder can be suppressed, and an adhesion process at a low temperature becomes possible.
　本実施形態では、図１６Ａに示すように、光電変換素子１０２は、非晶質半導体層であるｎ型半導体層１５ｎ及びｐ型半導体層１５ｐと、ｎ型電極１６ｎ及びｐ型電極１６ｐの上に、絶縁膜１７が形成されている。つまり、絶縁膜１７は、非晶質半導体層の上と、ｎ型電極１６ｎ及びｐ型電極１６ｐの上とに存在し、絶縁膜１７が形成される下地が異なる。下地が異なる絶縁膜１７は、接着プロセスによる熱により、下地の熱膨張係数の違いから剥離等が生じることがある。そのため、特に、２００℃以下での接着プロセスが好ましく、低温で硬化し、電気的に接合できる、熱硬化型銀ペースト、低温効果型銅ペースト、異方性導電フィルム、異方性導電ペースト等を用いることが好ましい。 In this embodiment, as shown in FIG. 16A, the photoelectric conversion element 102 is formed on the n-type semiconductor layer 15n and the p-type semiconductor layer 15p, which are amorphous semiconductor layers, and the n-type electrode 16n and the p-type electrode 16p. An insulating film 17 is formed. That is, the insulating film 17 exists on the amorphous semiconductor layer and on the n-type electrode 16n and the p-type electrode 16p, and the base on which the insulating film 17 is formed is different. The insulating film 17 having a different base may be peeled off due to a difference in thermal expansion coefficient of the base due to heat generated by the bonding process. Therefore, in particular, a bonding process at 200 ° C. or lower is preferable, and a thermosetting silver paste, a low-temperature effect type copper paste, an anisotropic conductive film, an anisotropic conductive paste, etc. that can be cured and electrically bonded at a low temperature. It is preferable to use it.
　なお、ｎ型電極１６ｎとｐ型電極１６ｐの上に上記導電性接着剤を塗布する際、隣り合う導電性接着剤が短絡しないように、導電性接着剤同士を空間的に分離し、電気的に絶縁する。このとき、導電性接着剤は、配線シート２００と光電変換素子１０２との導通を阻害しないように塗布される。 When applying the conductive adhesive on the n-type electrode 16n and the p-type electrode 16p, the conductive adhesives are spatially separated from each other so that adjacent conductive adhesives are not short-circuited. Insulate. At this time, the conductive adhesive is applied so as not to hinder conduction between the wiring sheet 200 and the photoelectric conversion element 102.
　導電性接着剤のパターニングは、スクリーン印刷等を用いてもよい。なお、異方性導電フィルムや異方性導電ペーストの場合には、パターニングの必要はない。配線材２０２ａ、２０２ｂと、光電変換素子１０２上のｎ型電極１６ｎ及びｐ型電極１６ｐとが重なるように位置合わせを行い、圧着させながら加熱処理を行うことで、接着剤の接着力によって、光電変換素子１０２と配線シート２００とが接合される。加熱処理の温度と加熱時間は、導電性接着剤、ｎ型電極１６ｎ及びｐ型電極１６ｐ、配線材２０２ａ、２０２ｂの種類によって異なるが、１２０～２２０℃程度であればよい。本実施形態の加熱処理の温度は１５０℃、加熱時間は数分から１時間程度である。 For patterning the conductive adhesive, screen printing or the like may be used. In the case of an anisotropic conductive film or anisotropic conductive paste, there is no need for patterning. By aligning the wiring members 202a and 202b with the n-type electrode 16n and the p-type electrode 16p on the photoelectric conversion element 102, and performing heat treatment while pressing them, the adhesive force of the adhesive causes photoelectric conversion. The conversion element 102 and the wiring sheet 200 are joined. The temperature and heating time of the heat treatment vary depending on the type of the conductive adhesive, the n-type electrode 16n and the p-type electrode 16p, and the wiring materials 202a and 202b, but may be about 120 to 220 ° C. The temperature of the heat treatment in this embodiment is 150 ° C., and the heating time is about several minutes to 1 hour.
　上記導電性接着剤は、光電変換素子１０２における絶縁膜１７の開口領域Ｆ（図１６Ａ参照）の上に少なくとも形成される。なお、絶縁膜１７によって、電気的絶縁性が保たれているため、開口領域Ｆの外側に導電性接着剤が形成されてもよい。 The conductive adhesive is formed at least on the opening region F of the insulating film 17 in the photoelectric conversion element 102 (see FIG. 16A). In addition, since the electrical insulation is maintained by the insulating film 17, a conductive adhesive may be formed outside the opening region F.
　ｎ型電極１６ｎ及びｐ型電極１６ｐの上を絶縁膜１７が覆っている領域は、絶縁膜１７によって電極表面の酸化等が抑制される。そのため、酸化防止、信頼性向上の観点から、絶縁膜１７で覆われる領域は広い方が好ましく、ｎ型電極１６ｎ、ｐ型電極１６ｐの面内方向の幅Ｘ（図１６Ａ参照）に対し、絶縁膜１７の開口領域Ｆの両側の領域の幅Ｊ１、Ｊ２（図１６Ａ参照）の合計が、３０％以上であることがより好ましい。なお、製造プロセスの尤度を考慮すると、絶縁膜１７の開口領域Ｆは、ｎ型電極１６ｎ、ｐ型電極１６ｐの略中心付近に設けられていることが好ましい。 In the region where the insulating film 17 covers the n-type electrode 16n and the p-type electrode 16p, oxidation of the electrode surface is suppressed by the insulating film 17. For this reason, from the viewpoint of preventing oxidation and improving reliability, it is preferable that the region covered with the insulating film 17 is wide. Insulation with respect to the width X in the in-plane direction of the n-type electrode 16n and the p-type electrode 16p (see FIG. 16A) More preferably, the sum of the widths J1 and J2 (see FIG. 16A) of the regions on both sides of the opening region F of the film 17 is 30% or more. In consideration of the likelihood of the manufacturing process, it is preferable that the opening region F of the insulating film 17 is provided in the vicinity of the approximate center of the n-type electrode 16n and the p-type electrode 16p.
　上記のようにして、配線シート２００と光電変換素子１０２とが接合された配線シート付き光電変換素子は、エチレンビニルアセテート樹脂（ＥＶＡ樹脂）が形成されたガラス基板と、ＥＶＡ樹脂が形成されたＰＥＴフィルムとの間に配置される。そして、ガラス基板側のＥＶＡ樹脂を配線シート付き光電変換素子に真空圧着させる。また、ＰＥＴフィルム側のＥＶＡ樹脂を配線シート付き光電変換素子に真空圧着させた状態で１２５℃に加熱して硬化する。このようにすることで、ガラス基板とＰＥＴフィルムとの間で硬化したＥＶＡ樹脂中に、配線シート付き光電変換素子が封止され、太陽電池モジュールが作製される。 As described above, the photoelectric conversion element with a wiring sheet in which the wiring sheet 200 and the photoelectric conversion element 102 are joined is composed of a glass substrate on which an ethylene vinyl acetate resin (EVA resin) is formed and a PET on which an EVA resin is formed. Arranged between the film. Then, the EVA resin on the glass substrate side is vacuum bonded to the photoelectric conversion element with a wiring sheet. In addition, the EVA resin on the PET film side is cured by heating to 125 ° C. in a state where it is vacuum-pressurized to the photoelectric conversion element with a wiring sheet. By doing in this way, the photoelectric conversion element with a wiring sheet is sealed in EVA resin hardened between a glass substrate and a PET film, and a solar cell module is produced.
　＜第７実施形態＞
　上述した第１実施形態から第６実施形態では、シリコン基板１１の受光面にテクスチャ構造を有する場合を例に説明したが、シリコン基板１１の受光面と裏面にテクスチャ構造を有していてもよい。 <Seventh embodiment>
In the first to sixth embodiments described above, the case where the light receiving surface of the silicon substrate 11 has a texture structure has been described as an example. However, the light receiving surface and the back surface of the silicon substrate 11 may have a texture structure. .
　図１７Ａは、両面にテクスチャ構造が形成されたシリコン基板４０１を用いて作製した光電変換素子４００の断面図である。なお、図１７Ａにおいて、第１実施形態と同様の構成には、第１実施形態と同じ符号を付している。 FIG. 17A is a cross-sectional view of a photoelectric conversion element 400 manufactured using a silicon substrate 401 having a texture structure formed on both sides. In FIG. 17A, the same reference numerals as those in the first embodiment are given to the same configurations as those in the first embodiment.
　光電変換素子４００は、両面にテクスチャ構造を形成したウェハを用いて、上述した図６Ａ～６Ｄに示す各工程によって作製される。 The photoelectric conversion element 400 is manufactured by the steps shown in FIGS. 6A to 6D described above using a wafer having a texture structure formed on both sides.
　図１７Ｂは、シリコン基板４０１の表面のＳＥＭ（Scanning Electron Microscopy）写真を示す図である。図１７Ｂの（ａ）は、テクスチャ構造を構成するピラミッドの底辺の長さが２μｍ以下である場合のＳＥＭ写真を示し、図１７Ｂの（ｂ）は、ピラミッドの底辺の長さが１０μｍ以下である場合のＳＥＭ写真を示している。また、図１７Ｂの（ｃ）は、ピラミッドの底辺の長さが１５μｍ程度である場合のＳＥＭ写真を示している。 FIG. 17B is a view showing an SEM (Scanning Electron Microscopy) photograph of the surface of the silicon substrate 401. FIG. 17B (a) shows an SEM photograph in the case where the length of the base of the pyramid constituting the texture structure is 2 μm or less, and FIG. 17B (b) shows the length of the base of the pyramid is 10 μm or less. The SEM photograph of the case is shown. Moreover, (c) of FIG. 17B has shown the SEM photograph in case the length of the base of a pyramid is about 15 micrometers.
　図１７Ｂの（ａ），（ｂ），（ｃ）に示す３種類のテクスチャ構造を両面に形成したシリコン基板４０１の裏面に、ｐ型半導体層１５ｐとｎ型半導体層１５ｎを形成した。ｐ型半導体層１５ｐとｎ型半導体層１５ｎは、上述した実施形態と同様に、膜厚減少領域Ｔを有する。このように、両面にテクスチャ構造が形成されたシリコン基板４０１を用いても、膜厚減少領域Ｔを有することによるパッシベーション性と低抵抗化の効果を得ることができる。 A p-type semiconductor layer 15p and an n-type semiconductor layer 15n were formed on the back surface of the silicon substrate 401 on which both types of texture structures shown in FIGS. 17B (a), (b), and (c) were formed. The p-type semiconductor layer 15p and the n-type semiconductor layer 15n have a film thickness reduction region T as in the above-described embodiment. Thus, even if the silicon substrate 401 having a texture structure formed on both sides is used, the effect of passivation and low resistance can be obtained by having the film thickness reduction region T.
　また、テクスチャ構造を有するシリコン基板４０１の裏面に、膜厚減少領域Ｔを有するｐ型半導体層１５ｐ及び／又はｎ型半導体層１５ｎを形成し、半導体層上に、ＴＣＯ（Transparent Conductive Oxide）及び／又は電極１６を形成した場合に、凹凸形状に起因するアンカー効果などによって半導体層との密着性が向上する効果が得られた。よって、太陽電池の長期信頼性を向上させるため、シリコン基板の両面にテクスチャが形成される方が好ましい。 Further, a p-type semiconductor layer 15p and / or an n-type semiconductor layer 15n having a film thickness reduction region T is formed on the back surface of the silicon substrate 401 having a texture structure, and TCO (Transparent Conductive Oxide) and / or Alternatively, when the electrode 16 is formed, an effect of improving the adhesion with the semiconductor layer is obtained by an anchor effect or the like due to the uneven shape. Therefore, in order to improve the long-term reliability of the solar cell, it is preferable that the texture is formed on both sides of the silicon substrate.
　なお、光電変換素子４００は、配線シート２００を用いてモジュール化される。また、本実施形態による光電変換素子に用いるシリコン基板は、上述した他の実施形態において用いてもよい。 Note that the photoelectric conversion element 400 is modularized using the wiring sheet 200. Further, the silicon substrate used in the photoelectric conversion element according to the present embodiment may be used in the other embodiments described above.
　＜第８実施形態＞
　本実施形態では、上述した第１実施形態から第５実施形態及び第７実施形態の少なくとも１つの光電変換素子を備えた光電変換モジュールについて説明する。図１８は、本実施形態に係る光電変換モジュールの構成を示す概略図である。光電変換モジュール１０００は、複数の光電変換素子１００１と、カバー１００２と、出力端子１００３，１００４とを備える。 <Eighth Embodiment>
In this embodiment, a photoelectric conversion module including at least one photoelectric conversion element according to the first to fifth embodiments and the seventh embodiment described above will be described. FIG. 18 is a schematic diagram illustrating a configuration of a photoelectric conversion module according to the present embodiment. The photoelectric conversion module 1000 includes a plurality of photoelectric conversion elements 1001, a cover 1002, and output terminals 1003 and 1004.
　複数の光電変換素子１００１は、例えば、第６実施形態に係る配線シート２００上にアレイ状に配置され、直列に接続されている。直列に接続する代わりに、並列接続、または、直列と並列を組み合わせた接続を行ってもよい。 The plurality of photoelectric conversion elements 1001 are, for example, arranged in an array on the wiring sheet 200 according to the sixth embodiment and connected in series. Instead of connecting in series, parallel connection or a combination of series and parallel may be performed.
　カバー１００２は、耐候性のカバーからなり、複数の光電変換素子１００１を覆う。カバー１００２は、例えば、光電変換素子１００１の受光面側に設けられた透明基材（例えばガラス等）と、光電変換素子１００１の受光面側とは反対の裏面側に設けられた裏面基材（例えば、ガラス、樹脂シート等）と、前記透明基材と前記樹脂基材との間の隙間を埋める封止材（例えばＥＶＡ等）とを含む。 The cover 1002 is made of a weather resistant cover and covers the plurality of photoelectric conversion elements 1001. The cover 1002 includes, for example, a transparent base material (for example, glass) provided on the light receiving surface side of the photoelectric conversion element 1001 and a back surface base material (on the reverse side opposite to the light receiving surface side of the photoelectric conversion element 1001). For example, glass, a resin sheet, etc.) and the sealing material (for example, EVA etc.) which fills the clearance gap between the said transparent base material and the said resin base material are included.
　出力端子１００３は、直列に接続された複数の光電変換素子１００１の一方端に配置される配線シート付き光電変換素子１００１に接続される。 The output terminal 1003 is connected to a photoelectric conversion element 1001 with a wiring sheet disposed at one end of a plurality of photoelectric conversion elements 1001 connected in series.
　出力端子１００４は、直列に接続された複数の光電変換素子１００１の他方端に配置される光電変換素子１００１に接続される。 The output terminal 1004 is connected to the photoelectric conversion element 1001 disposed at the other end of the plurality of photoelectric conversion elements 1001 connected in series.
　上述したように、上述した第１実施形態から第５実施形態に係る光電変換素子１、１００～１０２、及び第７実施形態に係る光電変換素子４００は、素子特性が向上している。従って、光電変換モジュール１０００の性能を向上させることができる。 As described above, the photoelectric conversion elements 1 and 100 to 102 according to the first to fifth embodiments described above and the photoelectric conversion element 400 according to the seventh embodiment have improved element characteristics. Therefore, the performance of the photoelectric conversion module 1000 can be improved.
　なお、本実施形態による光電変換モジュールは、図１８に示す構成に限らず、第１実施形態から第５実施形態及び第７実施形態に係る光電変換素子のいずれかを用いる限り、どのような構成であってもよい。 Note that the photoelectric conversion module according to the present embodiment is not limited to the configuration shown in FIG. 18, but any configuration as long as any one of the photoelectric conversion elements according to the first to fifth embodiments and the seventh embodiment is used. It may be.
　＜第９実施形態＞
　図１９Ａは、本実施形態に係る太陽光発電システムの構成を示す概略図である。太陽光発電システム１１００は、光電変換モジュールアレイ１１０１と、接続箱１１０２と、パワーコンディショナー１１０３と、分電盤１１０４と、電力メーター１１０５とを備える。太陽光発電システム１１００には、「ホーム・エネルギー・マネジメント・システム（ＨＥＭＳ：Ｈｏｍｅ　Ｅｎｅｒｇｙ　Ｍａｎａｇｅｍｅｎｔ　Ｓｙｓｔｅｍ）」、「ビルディング・エネルギー・マネジメント・システム（ＢＥＭＳ：Ｂｕｉｌｄｉｎｇ　Ｅｎｅｒｇｙ　Ｍａｎａｇｅｍｅｎｔ　Ｓｙｓｔｅｍ）」等の機能を付加することができる。これにより、太陽光発電システム１１００の発電量の監視、太陽光発電システム１１００に接続される各電気機器類の消費電力量の監視・制御等を行うことができ、エネルギー消費量を削減することができる。 <Ninth Embodiment>
FIG. 19A is a schematic diagram illustrating a configuration of a photovoltaic power generation system according to the present embodiment. The photovoltaic power generation system 1100 includes a photoelectric conversion module array 1101, a connection box 1102, a power conditioner 1103, a distribution board 1104, and a power meter 1105. Functions such as “Home Energy Management System (HEMS)” and “Building Energy Management System (BEMS)” are added to the photovoltaic power generation system 1100. Can do. Thereby, the power generation amount of the solar power generation system 1100 can be monitored, the power consumption amount of each electrical device connected to the solar power generation system 1100 can be monitored and controlled, and the energy consumption can be reduced. it can.
　接続箱１１０２は、光電変換モジュールアレイ１１０１に接続される。パワーコンディショナー１１０３は、接続箱１１０２に接続される。分電盤１１０４は、パワーコンディショナー１１０３および電気機器１１１０に接続される。電力メーター１１０５は、分電盤１１０４および系統連携に接続される。 The connection box 1102 is connected to the photoelectric conversion module array 1101. The power conditioner 1103 is connected to the connection box 1102. Distribution board 1104 is connected to power conditioner 1103 and electrical equipment 1110. The power meter 1105 is connected to the distribution board 1104 and system linkage.
　光電変換モジュールアレイ１１０１は、太陽光を電気に変換して直流電力を発電し、その発電した直流電力を接続箱１１０２に供給する。 The photoelectric conversion module array 1101 converts sunlight into electricity to generate DC power, and supplies the generated DC power to the connection box 1102.
　接続箱１１０２は、光電変換モジュールアレイ１１０１が発電した直流電力を受け、その受けた直流電力をパワーコンディショナー１１０３へ供給する。 The connection box 1102 receives the DC power generated by the photoelectric conversion module array 1101 and supplies the received DC power to the power conditioner 1103.
　パワーコンディショナー１１０３は、接続箱１１０２から受けた直流電力を交流電力に変換し、その変換した交流電力を分電盤１１０４に供給する。 The power conditioner 1103 converts the DC power received from the connection box 1102 into AC power, and supplies the converted AC power to the distribution board 1104.
　分電盤１１０４は、パワーコンディショナー１１０３から受けた交流電力および／または電力メーター１１０５を介して受けた商用電力を電気機器１１１０へ供給する。また、分電盤１１０４は、パワーコンディショナー１１０３から受けた交流電力が電気機器１１１０の消費電力よりも多いとき、余った交流電力を、電力メーター１１０５を介して、系統連携へ供給する。 Distribution board 1104 supplies AC power received from power conditioner 1103 and / or commercial power received via power meter 1105 to electrical equipment 1110. Further, when the AC power received from the power conditioner 1103 is larger than the power consumption of the electrical equipment 1110, the distribution board 1104 supplies the surplus AC power to the system linkage via the power meter 1105.
　電力メーター１１０５は、系統連携から分電盤１１０４へ向かう方向の電力を計測するとともに、分電盤１１０４から系統連携へ向かう方向の電力を計測する。 The power meter 1105 measures the power in the direction from the grid connection to the distribution board 1104 and measures the power in the direction from the distribution board 1104 to the grid cooperation.
　図２０は、図１９Ａに示す光電変換モジュールアレイ１１０１の構成を示す概略図である。図２０を参照して、光電変換モジュールアレイ１１０１は、複数の光電変換モジュール１１２０と、出力端子１１２１，１１２２とを含む。 FIG. 20 is a schematic diagram showing the configuration of the photoelectric conversion module array 1101 shown in FIG. 19A. Referring to FIG. 20, photoelectric conversion module array 1101 includes a plurality of photoelectric conversion modules 1120 and output terminals 1121 and 1122.
　複数の光電変換モジュール１１２０は、アレイ状に配列され、直列に接続される。複数の光電変換モジュール１１２０の各々は、図１８に示す光電変換モジュール１０００からなる。 The plurality of photoelectric conversion modules 1120 are arranged in an array and connected in series. Each of the plurality of photoelectric conversion modules 1120 includes a photoelectric conversion module 1000 shown in FIG.
　出力端子１１２１は、直列に接続された複数の光電変換モジュール１１２０の一方端に位置する光電変換モジュール１１２０に接続される。 The output terminal 1121 is connected to a photoelectric conversion module 1120 located at one end of a plurality of photoelectric conversion modules 1120 connected in series.
　出力端子１１２２は、直列に接続された複数の光電変換モジュール１１２０の他方端に位置する光電変換モジュール１１２０に接続される。 The output terminal 1122 is connected to the photoelectric conversion module 1120 located at the other end of the plurality of photoelectric conversion modules 1120 connected in series.
　太陽光発電システム１１００における動作を説明する。光電変換モジュールアレイ１１０１は、太陽光を電気に変換して直流電力を発電し、その発電した直流電力を、接続箱１１０２を介してパワーコンディショナー１１０３へ供給する。 Operation in the solar power generation system 1100 will be described. The photoelectric conversion module array 1101 generates sunlight by converting sunlight into electricity, and supplies the generated DC power to the power conditioner 1103 via the connection box 1102.
　パワーコンディショナー１１０３は、光電変換モジュールアレイ１１０１から受けた直流電力を交流電力に変換し、その変換した交流電力を分電盤１１０４へ供給する。 The power conditioner 1103 converts the DC power received from the photoelectric conversion module array 1101 into AC power, and supplies the converted AC power to the distribution board 1104.
　分電盤１１０４は、パワーコンディショナー１１０３から受けた交流電力が電気機器１１１０の消費電力以上であるとき、パワーコンディショナー１１０３から受けた交流電力を電気機器１１１０に供給する。そして、分電盤１１０４は、余った交流電力を、電力メーター１１０５を介して系統連携へ供給する。 The distribution board 1104 supplies the AC power received from the power conditioner 1103 to the electrical device 1110 when the AC power received from the power conditioner 1103 is greater than or equal to the power consumption of the electrical device 1110. Then, the distribution board 1104 supplies surplus AC power to the system linkage via the power meter 1105.
　また、分電盤１１０４は、パワーコンディショナー１１０３から受けた交流電力が電気機器１１１０の消費電力よりも少ないとき、系統連携から受けた交流電力およびパワーコンディショナー１１０３から受けた交流電力を電気機器１１１０へ供給する。 In addition, distribution board 1104 supplies AC power received from grid cooperation and AC power received from power conditioner 1103 to electrical equipment 1110 when the AC power received from power conditioner 1103 is less than the power consumption of electrical equipment 1110. To do.
　太陽光発電システム１１００は、上述したように、素子特性が向上している第１実施形態から第５実施形態及び第７実施形態に係る光電変換素子のいずれかを備えている。従って、太陽光発電システム１１００の性能を向上させることができる。 As described above, the photovoltaic power generation system 1100 includes any one of the photoelectric conversion elements according to the first to fifth embodiments and the seventh embodiment in which element characteristics are improved. Therefore, the performance of the photovoltaic power generation system 1100 can be improved.
　なお、本実施形態による太陽光発電システムは、図１９Ａ，２０に示す構成に限らず、第１実施形態から第５実施形態及び第７実施形態に係る光電変換素子のいずれかを用いる限り、どのような構成であってもよい。また、図１９Ｂに示すようにパワーコンディショナー１１０３には蓄電池１１０６が接続されていてもよい。この場合、日照量の変動による出力変動を抑制することができるとともに、日照のない時間帯であっても蓄電池１１０６に蓄電された電力を供給することができる。蓄電池１１０６はパワーコンディショナー１１０３に内蔵されていてもよい。 Note that the photovoltaic power generation system according to the present embodiment is not limited to the configuration illustrated in FIGS. 19A and 20, and as long as any one of the photoelectric conversion elements according to the first to fifth embodiments and the seventh embodiment is used. Such a configuration may be adopted. Further, as shown in FIG. 19B, a storage battery 1106 may be connected to the power conditioner 1103. In this case, output fluctuation due to fluctuations in the amount of sunlight can be suppressed, and power stored in the storage battery 1106 can be supplied even in a time zone without sunlight. The storage battery 1106 may be built in the power conditioner 1103.
　＜第１０実施形態＞
　図２１Ａは、本実施形態に係る太陽光発電システムの構成を示す概略図である。太陽光発電システム１２００は、サブシステム１２０１～１２０ｎ（ｎは２以上の整数）と、パワーコンディショナー１２１１～１２１ｎと、変圧器１２２１とを備える。太陽光発電システム１２００は、図１９Ａ、１９Ｂに示す太陽光発電システム１１００よりも規模が大きい太陽光発電システムである。 <Tenth Embodiment>
FIG. 21A is a schematic diagram illustrating a configuration of a photovoltaic power generation system according to the present embodiment. The photovoltaic power generation system 1200 includes subsystems 1201 to 120n (n is an integer of 2 or more), power conditioners 1211 to 121n, and a transformer 1221. The photovoltaic power generation system 1200 is a photovoltaic power generation system having a larger scale than the photovoltaic power generation system 1100 shown in FIGS. 19A and 19B.
　パワーコンディショナー１２１１～１２１ｎは、それぞれ、サブシステム１２０１～１２０ｎに接続される。 The power conditioners 1211 to 121n are connected to the subsystems 1201 to 120n, respectively.
　変圧器１２２１は、パワーコンディショナー１２１１～１２１ｎおよび系統連携に接続される。 The transformer 1221 is connected to the power conditioners 1211 to 121n and the system linkage.
　サブシステム１２０１～１２０ｎの各々は、モジュールシステム１２３１～１２３ｊ（ｊは２以上の整数）からなる。 Each of the subsystems 1201 to 120n includes module systems 1231 to 123j (j is an integer of 2 or more).
　モジュールシステム１２３１～１２３ｊの各々は、光電変換モジュールアレイ１３０１～１３０ｉ（ｉは２以上の整数）と、接続箱１３１１～１３１ｉと、集電箱１３２１とを含む。 Each of the module systems 1231 to 123j includes photoelectric conversion module arrays 1301 to 130i (i is an integer of 2 or more), connection boxes 1311 to 131i, and a current collection box 1321.
　光電変換モジュールアレイ１３０１～１３０ｉの各々は、図２０に示す光電変換モジュールアレイ１１０１と同じ構成からなる。 Each of the photoelectric conversion module arrays 1301 to 130i has the same configuration as the photoelectric conversion module array 1101 shown in FIG.
　接続箱１３１１～１３１ｉは、それぞれ、光電変換モジュールアレイ１３０１～１３０ｉに接続される。 The connection boxes 1311 to 131i are connected to the photoelectric conversion module arrays 1301 to 130i, respectively.
　集電箱１３２１は、接続箱１３１１～１３１ｉに接続される。また、サブシステム１２０１のｊ個の集電箱１３２１は、パワーコンディショナー１２１１に接続される。サブシステム１２０２のｊ個の集電箱１３２１は、パワーコンディショナー１２１２に接続される。以下、同様にして、サブシステム１２０ｎのｊ個の集電箱１３２１は、パワーコンディショナー１２１ｎに接続される。 The current collection box 1321 is connected to the connection boxes 1311 to 131i. Also, j current collection boxes 1321 of the subsystem 1201 are connected to the power conditioner 1211. The j current collection boxes 1321 of the subsystem 1202 are connected to the power conditioner 1212. Hereinafter, similarly, j current collection boxes 1321 of the subsystem 120n are connected to the power conditioner 121n.
　モジュールシステム１２３１のｉ個の光電変換モジュールアレイ１３０１～１３０ｉは、太陽光を電気に変換して直流電力を発電し、その発電した直流電力を、それぞれ接続箱１３１１～１３１ｉを介して集電箱１３２１へ供給する。モジュールシステム１２３２のｉ個の光電変換モジュールアレイ１３０１～１３０ｉは、太陽光を電気に変換して直流電力を発電し、その発電した直流電力をそれぞれ、接続箱１３１１～１３１ｉを介して集電箱１３２１へ供給する。以下、同様にして、モジュールシステム１２３ｊのｉ個の光電変換モジュールアレイ１３０１～１３０ｉは、太陽光を電気に変換して直流電力を発電し、その発電した直流電力をそれぞれ、接続箱１３１１～１３１ｉを介して集電箱１３２１へ供給する。 The i photoelectric conversion module arrays 1301 to 130i of the module system 1231 generate sunlight by converting sunlight into electricity, and the generated DC power is collected through the connection boxes 1311 to 131i, respectively. To supply. The i photoelectric conversion module arrays 1301 to 130i of the module system 1232 generate sunlight by converting sunlight into electricity, and the generated DC power is collected through the connection boxes 1311 to 131i, respectively. To supply. Similarly, the i photoelectric conversion module arrays 1301 to 130i of the module system 123j convert sunlight into electricity to generate DC power, and the generated DC power is connected to the connection boxes 1311 to 131i, respectively. To the current collection box 1321.
　そして、サブシステム１２０１のｊ個の集電箱１３２１は、直流電力をパワーコンディショナー１２１１へ供給する。 And the j current collection boxes 1321 of the subsystem 1201 supply DC power to the power conditioner 1211.
　サブシステム１２０２のｊ個の集電箱１３２１は、同様にして直流電力をパワーコンディショナー１２１２へ供給する。 The j current collection boxes 1321 of the subsystem 1202 supply DC power to the power conditioner 1212 in the same manner.
　以下、同様にして、サブシステム１２０ｎのｊ個の集電箱１３２１は、直流電力をパワーコンディショナー１２１ｎへ供給する。 Hereinafter, similarly, the j current collecting boxes 1321 of the subsystem 120n supply DC power to the power conditioner 121n.
　パワーコンディショナー１２１１～１２１ｎは、それぞれ、サブシステム１２０１～１２０ｎから受けた直流電力を交流電力に変換し、その変換した交流電力を変圧器１２２１へ供給する。 The power conditioners 1211 to 121n convert the DC power received from the subsystems 1201 to 120n into AC power, and supply the converted AC power to the transformer 1221.
　変圧器１２２１は、パワーコンディショナー１２１１～１２１ｎから交流電力を受け、その受けた交流電力の電圧レベルを変換して系統連携へ供給する。 The transformer 1221 receives AC power from the power conditioners 1211 to 121n, converts the voltage level of the received AC power, and supplies it to the system linkage.
　太陽光発電システム１２００は、上述したように、素子特性が向上している第１実施形態から第５実施形態に係る光電変換素子のいずれかを備えている。従って、太陽光発電システム１２００の性能を向上させることができる。 As described above, the photovoltaic power generation system 1200 includes any one of the photoelectric conversion elements according to the first to fifth embodiments having improved element characteristics. Therefore, the performance of the photovoltaic power generation system 1200 can be improved.
　なお、本実施形態による太陽光発電システムは、図２１Ａに示す構成に限らず、第１実施形態から第５実施形態及び第７実施形態に係る光電変換素子のいずれかを用いる限り、どのような構成であってもよい。 Note that the photovoltaic power generation system according to this embodiment is not limited to the configuration illustrated in FIG. 21A, but any type of photoelectric conversion element according to the first to fifth embodiments and the seventh embodiment is used. It may be a configuration.
　また、図２１Ｂに示すようにパワーコンディショナー１２１１～１２１ｎに蓄電池１２１３が接続されていてもよいし、蓄電池１２１３がパワーコンディショナー１２１１～１２１ｎに内蔵されていてもよい。この場合、パワーコンディショナー１２１１～１２１ｎは、集電箱１３２１から受けた直流電力の一部または全部を適切に電力変換して、蓄電池１２１３に蓄電することができる。蓄電池１２１３に蓄電された電力は、サブシステム１２０１～１２０ｎの発電量に応じて適宜パワーコンディショナー１２１１～１２１ｎ側に供給され、適切に電力変換されて変圧器１２２１へ供給される。 Further, as shown in FIG. 21B, a storage battery 1213 may be connected to the power conditioners 1211 to 121n, or the storage battery 1213 may be built in the power conditioners 1211 to 121n. In this case, the power conditioners 1211 to 121n can appropriately convert part or all of the direct-current power received from the current collection box 1321, and store it in the storage battery 1213. The electric power stored in the storage battery 1213 is appropriately supplied to the power conditioners 1211 to 121n according to the power generation amount of the subsystems 1201 to 120n, and is appropriately converted into electric power and supplied to the transformer 1221.
　＜変形例＞
　以上、本発明の第１～第１０実施形態にかかる光電変換素子について説明した。本発明の光電変換素子は上述の各実施形態のみに限定されず、発明の範囲内で種々の変更が可能である。また、各実施形態は、適宜組み合わせて実施することが可能である。 <Modification>
The photoelectric conversion elements according to the first to tenth embodiments of the present invention have been described above. The photoelectric conversion element of the present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the invention. Moreover, each embodiment can be implemented in combination as appropriate.
　（１）上述した第１実施形態～第１０実施形態において、シリコン基板１１，４０１は、ｎ型単結晶シリコンからなるものでもよいし、ｐ型単結晶シリコンからなるものでもよい。また、ｎ型多結晶シリコン又はｐ型多結晶シリコンからなるものでもよい。なお、シリコン基板１１，４０１がｎ型多結晶シリコンまたはｐ型多結晶シリコンからなる場合、シリコン基板１１，４０１は、受光面、または受光面および裏面がドライエッチングを用いてハニカムテクスチャのようなテクスチャ構造に加工される。 (1) In the first to tenth embodiments described above, the silicon substrates 11 and 401 may be made of n-type single crystal silicon or p-type single crystal silicon. Further, it may be made of n-type polycrystalline silicon or p-type polycrystalline silicon. When the silicon substrates 11 and 401 are made of n-type polycrystalline silicon or p-type polycrystalline silicon, the silicon substrates 11 and 401 have a light-receiving surface or a texture such as a honeycomb texture using dry etching on the light-receiving surface and the back surface. Processed into a structure.
　（２）上述した第１実施形態～第１０実施形態では、シリコン基板１１，４０１の受光面にＡＲＣ１２が形成されている場合を説明したが、ＡＲＣ１２が形成されていなくてもよい。また、ＡＲＣ１２に代えて、高濃度のｎ型ドーパントが拡散されたｎ＋層が形成されていてもよい。あるいは、シリコン基板１１の受光面とＡＲＣ１２との間に、高濃度のｎ型ドーパントが拡散されたｎ＋層が形成されていてもよい。 (2) In the first to tenth embodiments described above, the case where the ARC 12 is formed on the light receiving surfaces of the silicon substrates 11 and 401 has been described, but the ARC 12 may not be formed. Further, instead of the ARC 12, an n + layer in which a high concentration n-type dopant is diffused may be formed. Alternatively, an n + layer in which a high concentration n-type dopant is diffused may be formed between the light receiving surface of the silicon substrate 11 and the ARC 12.
　（３）上述した第１実施形態～第４実施形態では、プラズマＣＶＤ法を用いて非晶質半導体層を形成する場合を説明したが、プラズマＣＶＤ法に代えて、ＣａｔＣＶＤ（Ｃａｔａｌｙｔｉｃ　Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法を用いて非晶質半導体層を形成してもよい。ＣａｔＣＶＤ法を用いる場合、成膜条件は、例えば、シリコン基板１１の温度を１００～３００℃、成膜圧力を１０～５００Ｐａ、熱触媒体の温度（熱触媒体としてタングステンを使用する場合）を１５００～２０００℃、ＲＦパワー密度を０．０１～１Ｗ／ｃｍ２としてもよい。このようにすることで、品質の高い非晶質半導体層を比較的低温かつ短時間で形成することができる。 (3) In the first to fourth embodiments described above, the case where the amorphous semiconductor layer is formed using the plasma CVD method has been described. However, instead of the plasma CVD method, CatCVD (Catalytic Chemical Vapor Deposition) is used. An amorphous semiconductor layer may be formed using a method. When the CatCVD method is used, the film formation conditions are, for example, the temperature of the silicon substrate 11 of 100 to 300 ° C., the film formation pressure of 10 to 500 Pa, and the temperature of the thermal catalyst (when tungsten is used as the thermal catalyst) 1500. The RF power density may be set to 0.01 to 1 W / cm 2 at ˜2000 ° C. Thus, a high-quality amorphous semiconductor layer can be formed at a relatively low temperature and in a short time.
　（４）また、上述した第３実施形態及び第４実施形態において、ｎ型半導体層１５ｎとｐ型半導体層１５ｐにフラット領域Ｌが形成されていなくてもよい。 (4) In the third embodiment and the fourth embodiment described above, the flat region L may not be formed in the n-type semiconductor layer 15n and the p-type semiconductor layer 15p.

Claims (5)

  1. 　半導体基板と、
    　前記半導体基板の一方の面上に形成された第１導電型を有する第１非晶質半導体層と、
    　前記半導体基板の一方の面上に形成され、かつ前記半導体基板の面内方向において前記第１非晶質半導体層に隣接して形成され、前記第１導電型と反対の第２導電型を有する第２非晶質半導体層と、
    　前記第１非晶質半導体層の上に形成された第１電極と、
    　前記第２非晶質半導体層の上に形成された第２電極とを備え、
    　前記半導体基板上に成膜された一の薄膜において、膜厚が最大である点を第１の点とし、当該一の薄膜の面内方向において当該薄膜の膜厚の減少率が第１の減少率から前記第１の減少率よりも大きい第２の減少率に変化する点、または当該一の薄膜の面内方向において当該一の薄膜の膜厚の変化率の符号が負から正に変化する点を第２の点とし、当該一の薄膜の面内方向において前記第１の点から前記第２の点までの領域を膜厚減少領域と定義したとき、
    　前記第１非晶質半導体層及び前記第２非晶質半導体層の少なくとも一方の半導体層は、前記膜厚減少領域を有し、
    　前記少なくとも一方の半導体層に形成された電極の少なくとも一部は、前記膜厚減少領域上に形成されている、光電変換素子。     A semiconductor substrate;
    A first amorphous semiconductor layer having a first conductivity type formed on one surface of the semiconductor substrate;
    Formed on one surface of the semiconductor substrate and adjacent to the first amorphous semiconductor layer in an in-plane direction of the semiconductor substrate and having a second conductivity type opposite to the first conductivity type; A second amorphous semiconductor layer;
    A first electrode formed on the first amorphous semiconductor layer;
    A second electrode formed on the second amorphous semiconductor layer,
    In the one thin film formed on the semiconductor substrate, the point where the film thickness is the maximum is the first point, and the reduction rate of the film thickness in the in-plane direction of the one thin film is the first decrease. The sign of the change rate of the thickness of the one thin film changes from negative to positive in the in-plane direction of the one thin film at a point where the rate changes to a second reduction rate larger than the first reduction rate. When the point is the second point and the region from the first point to the second point in the in-plane direction of the one thin film is defined as a film thickness reduction region,
    At least one of the first amorphous semiconductor layer and the second amorphous semiconductor layer has the thickness reduction region,
    A photoelectric conversion element, wherein at least a part of an electrode formed on the at least one semiconductor layer is formed on the film thickness reduction region.
  2. 　前記膜厚減少領域を有する前記半導体層は、前記半導体基板と同じ導電型を有する、請求項１に記載の光電変換素子。 The photoelectric conversion element according to claim 1, wherein the semiconductor layer having the thickness reduction region has the same conductivity type as the semiconductor substrate.
  3. 　前記第１非晶質半導体層及び前記第２非晶質半導体層の各々は、前記膜厚減少領域を有し、
    　隣接する前記第１非晶質半導体層と前記第２非晶質半導体層の前記膜厚減少領域は、離間して配置されている、請求項１又は２に記載の光電変換素子。     Each of the first amorphous semiconductor layer and the second amorphous semiconductor layer has the thickness reduction region,
    3. The photoelectric conversion element according to claim 1, wherein the film thickness reduction regions of the adjacent first amorphous semiconductor layer and the second amorphous semiconductor layer are arranged apart from each other.
  4. 　さらに、前記半導体基板と、前記第１非晶質半導体層及び前記第２非晶質半導体層との間に形成された第１パッシベーション膜を備える、請求項１から３のいずれか一項に記載の光電変換素子。 4. The semiconductor device according to claim 1, further comprising a first passivation film formed between the semiconductor substrate and the first amorphous semiconductor layer and the second amorphous semiconductor layer. 5. Photoelectric conversion element.
  5. 　さらに、前記第１パッシベーション膜と、前記第１非晶質半導体層及び前記第２非晶質半導体層との間に形成された第２パッシベーション膜を備え、
    　前記第１パッシベーション膜及び前記第２パッシベーション膜は、真性非晶質半導体からなる、請求項４に記載の光電変換素子。
     
     
          And a second passivation film formed between the first passivation film and the first amorphous semiconductor layer and the second amorphous semiconductor layer.
    The photoelectric conversion element according to claim 4, wherein the first passivation film and the second passivation film are made of an intrinsic amorphous semiconductor.


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