WO2016072363A1 - Optical apparatus - Google Patents

Optical apparatus Download PDF

Info

Publication number
WO2016072363A1
WO2016072363A1 PCT/JP2015/080786 JP2015080786W WO2016072363A1 WO 2016072363 A1 WO2016072363 A1 WO 2016072363A1 JP 2015080786 W JP2015080786 W JP 2015080786W WO 2016072363 A1 WO2016072363 A1 WO 2016072363A1
Authority
WO
WIPO (PCT)
Prior art keywords
voltage
electrode
pixel
reflectance
transmittance
Prior art date
Application number
PCT/JP2015/080786
Other languages
French (fr)
Japanese (ja)
Inventor
弘幸 森脇
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Publication of WO2016072363A1 publication Critical patent/WO2016072363A1/en

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/169—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on orientable non-spherical particles having a common optical characteristic, e.g. suspended particles of reflective metal flakes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present invention relates to an optical device, and more particularly to an optical device having a pixel whose reflectance or transmittance changes according to the magnitude of an applied voltage.
  • Patent Document 1 discloses a liquid crystal display device using the memory property of cholesteric liquid crystal.
  • the cholesteric liquid crystal has a property (memory property) that can maintain the alignment state when the applied voltage is zero. Therefore, power consumption can be reduced by reducing the number of times image data is written using this memory property.
  • Patent Document 2 discloses a liquid crystal display device with a built-in pixel memory.
  • a static memory is included in the pixel circuit of each pixel, a refresh operation is not necessary when displaying a still image, and thus power consumption can be reduced.
  • Patent Document 1 Since the technology of Patent Document 1 uses the memory property of a cholesteric liquid crystal material that is a constituent material of the display medium layer (liquid crystal layer), naturally, the display medium layer itself has no memory property. Not applicable.
  • Patent Document 2 can be applied to a display device in which the display medium layer itself does not have a memory property, in order to operate the pixel memory when the applied voltage at the time of writing image data is high. Necessary power consumption increases. Further, since the pixel memory is a binary digital circuit, the technique of Patent Document 2 has a problem that halftone display cannot be performed.
  • the present invention has been made in view of the above problems, and an object thereof is to provide an optical device that is excellent in low power consumption and capable of halftone display.
  • An optical device is an optical device having a pixel, and the reflectance or transmittance of the pixel changes according to the magnitude of a voltage applied to the pixel, the voltage-reflection of the pixel
  • the threshold voltage in the boost curve indicating the voltage-reflectance characteristic or the voltage-transmittance characteristic when the applied voltage is increased decreases the applied voltage.
  • the pixel In the state where the applied voltage is zero, which is higher than the threshold voltage in the step-down curve indicating the voltage-reflectance characteristic or the voltage-transmittance characteristic, the pixel does not have a memory property,
  • the applied voltage is increased from zero, the value of the reflectance or transmittance in the boost curve is determined substantially in a one-to-one relationship with the voltage value, and the value at the time of writing data to the pixel is determined.
  • a pressurized voltage writing voltage is set on the basis of the boost curve.
  • a holding voltage that is an applied voltage when the pixel is in a data holding state is set lower than the writing voltage.
  • the reflectance or transmittance in the step-down curve when the applied voltage is decreased from the writing voltage, is substantially constant in a range from the writing voltage to a predetermined voltage lower than the writing voltage. It is.
  • the holding voltage is 20% or more lower than the write voltage.
  • the reflectance or transmittance of the pixel when the holding voltage is applied is not less than 0.9 times the reflectance or transmittance of the pixel when the write voltage is applied. .1 or less.
  • a driving frequency when the holding voltage is applied to the pixel is lower than a driving frequency when the writing voltage is applied to the pixel.
  • an optical device in one embodiment, includes a first substrate and a second substrate provided to face each other, and an optical layer provided between the first substrate and the second substrate.
  • the optical layer includes a medium and shape anisotropic particles dispersed in the medium and having shape anisotropy.
  • the medium includes a liquid crystal material.
  • different driving sequences are executed when the writing voltage is applied to the pixel and when the holding voltage is applied to the pixel.
  • the polarity of the holding voltage is inverted every frame.
  • the optical device according to the present invention may apply a lateral electric field and / or a fringe electric field to the optical layer.
  • the optical device according to the present invention has a transmittance corresponding to the applied voltage of the current frame when the reflectance corresponding to the applied voltage of the current frame is higher than the reflectance corresponding to the writing voltage of the next frame. Is lower than the transmittance corresponding to the writing voltage of the next frame, the applied voltage to the pixel is once reduced to zero, and then the original writing voltage is applied to the pixel.
  • the optical device according to the present invention has a transmittance corresponding to the applied voltage of the current frame when the reflectance corresponding to the applied voltage of the current frame is higher than the reflectance corresponding to the writing voltage of the next frame. Is lower than the transmittance corresponding to the writing voltage of the next frame, a vertical electric field is once applied to the optical layer, and then the original writing voltage is applied to the pixel.
  • an optical device includes a thin film transistor provided in the pixel, and the thin film transistor includes an oxide semiconductor layer.
  • the optical device according to the present invention includes a color filter provided in the pixel.
  • an optical device that is excellent in low power consumption and capable of halftone display is provided.
  • FIG. 3 is a cross-sectional view schematically showing a display device (optical device) 100 according to an embodiment of the present invention, showing a cross section taken along line 1A-1A ′ in FIG. 2.
  • 3 is a plan view schematically showing the display device 100.
  • FIG. (A) is a figure which shows typically the display apparatus 100 when the electric field is not applied to the optical layer 30, (b) is the display apparatus 100 when the fringe electric field is applied to the optical layer 30.
  • FIG. 3 is a diagram schematically showing the display device 100 when a vertical electric field is applied to the optical layer 30.
  • FIG. 3 is a diagram schematically showing the display device 100 when a fringe electric field and a lateral electric field are applied to the optical layer 30.
  • (A) is a figure which shows the mode of the optical layer 30 immediately after changing the electric field applied to the display medium layer 30 from a fringe electric field and / or a horizontal electric field to a vertical electric field
  • (b) is enough after that It is a figure which shows the mode of the optical layer 30 after a lapse of time. It is a top view which shows the electrode structure in a test cell.
  • the potential V 1 of the first electrode 11 in the test cell, the potential V 2 of the second electrode 12 is a timing chart showing the potential V 4 in the potential V 3 and the fourth electrode 21 of the third electrode 13.
  • FIG. A boosting curve obtained when the driving of increasing the pixel voltage Vop from the off voltage (0 V) to the writing voltage corresponding to white display, subsequently decreasing the pixel voltage Vop to a predetermined holding voltage, and then setting the off voltage again is repeated three times.
  • (A) shows the potential V 1 of the first electrode 11 at the time of data writing, the potential V 2 of the second electrode 12, the potential V 3 of the third electrode 13, the potential V 4 and the pixel voltage Vop of the fourth electrode 21 is a timing chart, (b), the potential V 1 of the first electrode 11 in the data holding state, the potential V 2 of the second electrode 12, the potential V 3 of the third electrode 13, the potential V 4 and the fourth electrode 21 It is a timing chart which shows pixel voltage Vop.
  • a graph showing a step-up curve and a step-down curve when the driving of increasing the pixel voltage Vop from the off voltage (0 V) to the writing voltage, subsequently decreasing the pixel voltage Vop to a predetermined holding voltage, and then turning it off again is repeated five times It is.
  • FIG. 6 is a graph showing a step-up curve and a step-down curve including points P1 and P2 corresponding to data writing and data holding states in a certain halftone D.
  • A) And (b) is a figure which shows the orientation state of the shape anisotropic particle 32 corresponding to the points P1 and P2 in FIG. 14, respectively. It is a graph which shows the pressure
  • (A) And (b) is a figure which shows the orientation state of the shape anisotropic particle 32 corresponding to the points P4 and P5 in FIG. 16, respectively.
  • A) And (b) is a figure which shows the orientation state of the shape anisotropic particle 32 corresponding to the points P6 and P7 in FIG.
  • (A) shows the potential V 1 of the first electrode 11 at the time of data writing, the potential V 2 of the second electrode 12, the potential V 3 of the third electrode 13, the potential V 4 and the pixel voltage Vop of the fourth electrode 21 is a timing chart
  • (b) the potential V 1 of the first electrode 11 in the data holding state, the potential V 2 of the second electrode 12, the potential V 3 of the third electrode 13, the potential V 4 and the fourth electrode 21 It is a timing chart which shows pixel voltage Vop.
  • (A) shows the potential V 1 of the first electrode 11 at the time of data writing, the potential V 2 of the second electrode 12, the potential V 3 of the third electrode 13, the potential V 4 and the pixel voltage Vop of the fourth electrode 21 is a timing chart, (b), the potential V 1 of the first electrode 11 in the data holding state, the potential V 2 of the second electrode 12, the potential V 3 of the third electrode 13, the potential V 4 and the fourth electrode 21 It is a timing chart which shows pixel voltage Vop.
  • (A) is a timing chart showing the potential V1 of the first electrode 11, the potential V2 of the second electrode 12, the potential V3 of the third electrode 13, the potential V4 of the fourth electrode 21 and the pixel voltage Vop in the data holding state.
  • (B) is a timing chart showing the potential V1 of the first electrode 11, the potential V2 of the second electrode 12, the potential V3 of the third electrode 13, the potential V4 of the fourth electrode 21 and the pixel voltage Vop at the time of black insertion.
  • It is. 6 is a diagram showing another electrode configuration of the display device 100.
  • FIG. FIG. 10 is a diagram showing still another electrode configuration of the display device 100. It is a top view which shows the example of the specific wiring structure in the back substrate 10 in the case of performing active matrix drive.
  • the optical device has a pixel, and an optical characteristic (specifically, reflectance or transmittance) of the pixel changes according to the magnitude of the voltage applied to the pixel.
  • the voltage-reflectance characteristic or voltage-transmittance characteristic of the pixel has a hysteresis characteristic, and a curve indicating the voltage-reflectance characteristic or the voltage-transmittance characteristic when the applied voltage is increased (hereinafter referred to as “ The threshold voltage in the “boost curve” is higher than the threshold voltage in the curve indicating the voltage-reflectance characteristic or voltage-transmittance characteristic when the applied voltage is decreased (hereinafter referred to as “step-down curve”). .
  • the pixel does not have memory characteristics, and the reflectance or transmittance value in the boost curve when the applied voltage is increased from zero is the voltage value. It is determined substantially by a one-to-one relationship.
  • An applied voltage at the time of data writing to the pixel (hereinafter referred to as “write voltage”) is set based on the boost curve.
  • the optical device can suitably perform halftone display by having the configuration using the hysteresis characteristic of the optical characteristics of the pixels as described above.
  • power consumption can be reduced by setting an applied voltage (hereinafter referred to as “holding voltage”) when the pixel is in a data holding state to be lower than a writing voltage.
  • FIG. 1 and 2 show an optical device (display device) 100 according to an embodiment of the present invention.
  • FIG. 1 is a cross-sectional view schematically showing the display device 100
  • FIG. 2 is a plan view schematically showing the display device 100.
  • FIG. 1 shows a cross section taken along line 1A-1A 'in FIG.
  • the display device 100 is a reflective display device that can perform display in a reflection mode using light incident from the outside (ambient light).
  • the display device 100 includes pixels.
  • the display device 100 includes a plurality of pixels arranged in a matrix.
  • a display device 100 includes a first substrate 10 and a second substrate 20 provided so as to face each other, and an optical layer (display) provided between the first substrate 10 and the second substrate 20.
  • Medium layer) 30 the first substrate 10 and the second substrate 20
  • the first substrate 10 positioned relatively on the back side may be referred to as a “back side substrate” and may be referred to relatively on the front side (that is, on the viewer side).
  • the second substrate 20 positioned at () may be referred to as a “front substrate”.
  • the first substrate (back substrate) 10 has a first electrode 11 and a second electrode 12 that can be given different potentials.
  • the first electrode 11 and the second electrode 12 are provided in each of the plurality of pixels.
  • Each of the 1st electrode 11 and the 2nd electrode 12 has a comb-tooth shape, as shown in FIG.
  • the first electrode 11 has a trunk portion 11b and a plurality of branch portions 11a extending from the trunk portion 11b.
  • the second electrode 12 includes a trunk portion 12b and a plurality of branch portions 12a extending from the trunk portion 12b.
  • the first electrode 11 and the second electrode 12 are arranged so that the plurality of branch portions 11a and 12a mesh with each other via a predetermined gap (hereinafter also referred to as “interelectrode distance”) g. Yes.
  • the width w 1 of the branch part 11 a of the first electrode 11 and the width w 2 of the branch part 12 a of the second electrode 12 are not particularly limited.
  • the inter-electrode distance g, the width w 1 of the branch portion 11a of the first electrode 11, and the width w 2 of the branch portion 12a of the second electrode 12 are each about several ⁇ m to several tens of ⁇ m, for example.
  • the width w 1 of the branch portion 11a of the first electrode 11 and the width w 2 of the branch portion 12a of the second electrode 12 may be the same or different.
  • the first substrate 10 further includes a third electrode 13 provided below the first electrode 11 and the second electrode 12 with the insulating layer 14 interposed therebetween.
  • the first electrode 11, the second electrode 12, and the third electrode 13 may be referred to as “first upper layer electrode”, “second upper layer electrode”, and “lower layer electrode”, respectively.
  • the third electrode 13 is a so-called solid electrode in which no slit or notch is formed.
  • the first substrate 10 is typically an active matrix substrate, and includes a plurality of thin film transistors (TFTs) provided in each pixel and various wirings (a gate wiring, a source wiring, etc. electrically connected to the TFT). (Both not shown here).
  • TFTs thin film transistors
  • the first electrode 11, the second electrode 12, and the third electrode 13 are electrically connected to the corresponding TFTs, respectively, and supplied with a voltage corresponding to the source signal through the TFTs.
  • the first substrate 10 further includes a light absorption layer 16 that absorbs light.
  • a light absorption layer 16 that absorbs light.
  • a material of the light absorption layer 16 for example, a pigment used for a black matrix material included in a color filter of a liquid crystal display device or the like can be used.
  • a low-reflection chromium film having a two-layer structure (having a structure in which a chromium layer and a chromium oxide layer are stacked) can be used as the light absorption layer 16.
  • the components of the first substrate 10 are supported by an insulating substrate (for example, a glass substrate) 10a.
  • an insulating substrate for example, a glass substrate
  • the light absorption layer 16 is provided on the back side of the substrate 10a.
  • the light absorption layer 16 may be provided on the optical layer 30 side of the substrate 10a.
  • the second substrate (front substrate) 20 has a fourth electrode (counter electrode) 21 facing the first electrode 11, the second electrode 12 and the third electrode 13.
  • the fourth electrode 21 may be a so-called solid electrode in which no slit or notch is formed.
  • the second substrate 20 further includes a dielectric layer (overcoat layer) 22 provided on the fourth electrode 21.
  • the fourth electrode 21 does not need to be electrically independent for each pixel, and may be a continuous single conductive film (that is, a common electrode) common to all pixels.
  • the fourth electrode 21 is a solid electrode common to all the pixels, patterning by a photolithography technique is not necessary, so that the manufacturing cost can be reduced.
  • the second substrate 20 includes a color filter (not shown).
  • the components of the second substrate 20 (such as the fourth electrode 21 described above) are supported by an insulating substrate (for example, a glass substrate) 20a.
  • an insulating substrate for example, a glass substrate
  • Each of the first electrode 11, the second electrode 12, the third electrode 13, and the fourth electrode 21 is made of a transparent conductive material such as ITO (indium tin oxide) or IZO (indium zinc oxide).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • the method for depositing the conductive film to be these electrodes and various known methods such as a sputtering method, a vacuum evaporation method, and a plasma CVD method can be used.
  • the method for patterning the conductive film in order to form the first electrode 11 and the second electrode 12 having a comb-teeth shape and a known patterning method such as photolithography can be used.
  • the thicknesses of the first electrode 11, the second electrode 12, the third electrode 13, and the fourth electrode 21 are, for example, 100 nm.
  • the optical characteristics of the optical layer 30 change according to the applied electric field.
  • the optical layer 30 includes a liquid medium 31 and particles 32 dispersed in the medium 31 and having shape anisotropy (hereinafter referred to as “shape anisotropic particles”).
  • shape anisotropic particles The first substrate 10 and the second substrate 20 described above are bonded together via a seal portion (not shown here) formed so as to surround the display region, and the medium 31 and the shape anisotropic particles 32 are: It is enclosed in a region (that is, a display region) surrounded by the seal portion.
  • the thickness of the optical layer 30 is, for example, 5 ⁇ m to 30 ⁇ m.
  • the shape anisotropic particle 32 has light reflectivity.
  • the shape anisotropic particle 32 has, for example, a flake shape (flaky shape).
  • the orientation direction of the shape anisotropic particles 32 changes according to the electric field (voltage) applied to the optical layer 30. Since the shape anisotropic particles 32 have shape anisotropy, when the orientation direction of the shape anisotropic particles 32 changes, the substrate surface of the shape anisotropic particles 32 (the substrate surface of the first substrate 10). The projected area on the screen also changes, and the optical characteristics (reflectance in this case) of the optical layer 30 change accordingly. In the display device 100, display is performed using this fact. The reason why the orientation direction of the shape anisotropic particles 32 changes according to the applied electric field will be described in detail later.
  • the medium 31 is a liquid crystal material and includes liquid crystal molecules.
  • the liquid crystal material is a nematic liquid crystal material having positive dielectric anisotropy. That is, the medium 31 is a so-called positive nematic liquid crystal material, and the dielectric constant ⁇ // in the major axis direction of the liquid crystal molecules is larger than the dielectric constant ⁇ ⁇ in the minor axis direction. Since the medium 31 is a nematic liquid crystal material, the pixel does not have a memory property when the applied voltage is zero.
  • Each of the first substrate 10 and the second substrate 20 has vertical alignment films 15 and 25 provided on the optical layer 30 side.
  • the vertical alignment films 15 and 25 have an alignment regulating force for vertically aligning liquid crystal molecules contained in the medium (liquid crystal material) 31 (aligned substantially perpendicularly to the substrate surface of the first substrate 10 or the second substrate 20).
  • the vertical alignment films 15 and 25, as will be described in detail later, are alignment restrictions that cause the shape anisotropic particles 32 to be vertically aligned (aligned substantially perpendicularly to the substrate surface of the first substrate 10 or the second substrate 20). Also has power.
  • the vertical alignment film is not necessarily provided on both the first substrate 10 and the second substrate 20, and the vertical alignment film may be provided on only one (for example, only the first substrate 10).
  • a fringe electric field is applied to the optical layer 30 by the first electrode (first upper layer electrode) 11, the second electrode (second upper layer electrode) 12, and the third electrode (lower layer electrode) 13. Is generated.
  • a vertical electric field is generated in the optical layer 30 by the first electrode 11, the second electrode 12, the third electrode 13, and the fourth electrode (counter electrode) 21.
  • FIGS. 3 (a) and 3 (b) are diagram schematically showing the display device 100 when no electric field is applied to the optical layer 30, and FIG. 3B is a diagram when a fringe electric field is applied to the optical layer 30.
  • FIG. It is a figure which shows typically the display apparatus 100 of.
  • the shape anisotropic particle 32 is first (its longitudinal direction) by the alignment regulating force of the vertical alignment films 15 and 25 as shown in FIG.
  • the substrate 10 is oriented so as to be substantially perpendicular to the substrate surface (that is, in a vertically oriented state).
  • the alignment of the liquid crystal molecules substantially perpendicular to the substrate surface by the alignment regulating force of the vertical alignment films 15 and 25 serves to support the shape anisotropic particles 32 taking a vertical alignment state.
  • most of the incident ambient light L is transmitted through the optical layer 30. That is, the optical layer 30 is in a transparent state. Since ambient light transmitted through the optical layer 30 is absorbed by the light absorption layer 16, black display can be performed in this state.
  • the shape anisotropic particles 32 are oriented substantially perpendicular to the substrate surface” means that the shape anisotropic particles 32 are oriented strictly perpendicular to the substrate surface. Refers to a state of being oriented at an angle exhibiting substantially the same optical characteristics as the state of being, specifically, the shape anisotropic particles 32 are oriented at an angle of 75 ° or more with respect to the substrate surface. Refers to the state.
  • the shape anisotropic particles 32 are (on the longitudinal direction) of the first substrate 10. Align so as to be substantially parallel to the substrate surface (that is, take a horizontal alignment state). The liquid crystal molecules are also aligned substantially parallel to the substrate surface of the first substrate 10. In this state, most of the incident ambient light L is reflected by the shape anisotropic particles 32 in the optical layer 30. That is, the optical layer 30 is in a reflective state, and white display can be performed in this state. Further, halftone display can be performed by applying a voltage lower than that during white display.
  • the second substrate 20 includes the fourth electrode 21 that faces the first electrode 11, the second electrode 12, and the third electrode 13, so that a vertical electric field is generated in the optical layer 30. You can also
  • the shape anisotropic particles 32 are formed on the substrate surface of the first substrate 10. Align so as to be substantially vertical (that is, take a vertical alignment state). The liquid crystal molecules are also aligned substantially perpendicular to the substrate surface of the first substrate 10. In this state, most of the incident ambient light L is transmitted through the optical layer 30. That is, the optical layer 30 is in a transparent state. Since ambient light transmitted through the optical layer 30 is absorbed by the light absorption layer 16, black display can be performed in this state.
  • a lateral electric field (represented by electric lines of force Eh) may be applied to the optical layer 30 in addition to the fringe electric field as shown in FIG.
  • a transverse electric field can be generated by the first electrode 11 and the second electrode 12.
  • an electric field generated by a potential difference between two electrodes provided on the same substrate on the same level is called a “lateral electric field”, and is generated by a potential difference between two electrodes provided on different levels on the same substrate.
  • the electric field is called a “fringe electric field”.
  • a mode in which display is performed by applying a fringe electric field and / or a lateral electric field to the optical layer 30 is referred to as a “lateral electric field mode”, and a mode in which display is performed by applying a vertical electric field to the optical layer 30. This is called “vertical electric field mode”.
  • the orientation change of the shape anisotropic particles 32 as described above is caused by the dielectrophoretic force due to the interaction between the electric field and the electric dipole moment induced thereby.
  • 6A and 6B show the optical layer immediately after the electric field applied to the optical layer 30 is changed from a fringe electric field and / or a horizontal electric field to a vertical electric field, and after a sufficient time has elapsed since then. It is a figure which shows the mode 30 (electric charge distribution and an electric force line).
  • the shape anisotropic particle 32 and the dielectric constant of the medium 31 are different, when the direction of the electric field applied to the optical layer 30 changes, as shown in FIG. Large distortion occurs. Therefore, as shown in FIG. 6B, the shape anisotropic particles 32 rotate so that the energy is minimized.
  • the dielectrophoretic force F dep acting on particles dispersed in a medium is expressed as follows, where the dielectric constant of the particles is ⁇ p , the dielectric constant of the medium is ⁇ m , the radius of the particles is a, and the strength of the electric field is E. It is represented by Formula (1). Re in the expression (1) is an operator that extracts a real part.
  • the medium 31 is a liquid crystal material and has dielectric anisotropy.
  • the shape anisotropic particles 32 are allowed to develop a vertical alignment state by the alignment regulating force of the vertical alignment films 15 and 25 and the support of liquid crystal molecules.
  • the vertical alignment operation and the horizontal alignment operation of the shape anisotropic particles 32 can be suitably switched.
  • the orientation direction of the shape anisotropic particles 32 can be changed by applying a voltage to the optical layer 30, which is used for display. It can be carried out. Since the display device 100 does not require a polarizing plate, high light utilization efficiency can be realized.
  • the reflectance of each pixel changes according to the magnitude of the voltage applied to the pixel.
  • the voltage-reflectance characteristic of the pixel has a hysteresis characteristic.
  • this hysteresis property will be specifically described.
  • the step-up curve shown voltage-reflectance characteristics when the applied voltage is increased
  • the step-down curve shown voltage-reflectance characteristics when the applied voltage is reduced
  • the display device 100 according to the embodiment of the present invention was actually prototyped (that is, a test cell was manufactured), and the test cell was obtained.
  • the test cell employs an electrode structure as shown in FIG. 7 instead of active matrix driving.
  • terminals 11t, 12t, and 13t are provided at the respective end portions of the first electrode 11, the second electrode 12, and the third electrode 13.
  • a voltage having a desired waveform was input from the arbitrary waveform generator to the first electrode 11, the second electrode 12, and the third electrode 13 via the terminals 11t, 12t, and 13t.
  • the optical layer 30 has a thickness (cell thickness) of 15 ⁇ m.
  • the medium 31 is a positive nematic liquid crystal material (manufactured by Merck & Co., Inc.) having a dielectric anisotropy ⁇ of 20.4.
  • the average particle diameter of the shape anisotropic particles 32 is 7 ⁇ m, and the content of the shape anisotropic particles 32 in the optical layer 30 is 6% by weight.
  • the substrates 10a and 20a are glass substrates, respectively.
  • Each of the first electrode (first upper layer electrode) 11 and the second electrode (second upper layer electrode) 12 has a comb-tooth shape.
  • the third electrode (lower layer electrode) 13 has a plurality of slits (see FIG. 23 described later).
  • the fourth electrode (counter electrode) 21 is a solid electrode.
  • Each of the first electrode 11, the second electrode 12, the third electrode 13, and the fourth electrode 21 is made of IZO and has a thickness of 100 nm.
  • the width w 1 of the branch portion 11a of the first electrode 11 and the width w 2 of the branch portion 12a of the second electrode 12 are each 3 ⁇ m, and the inter-electrode distance g is 10 ⁇ m.
  • the insulating layer 14 is made of SiNx and has a thickness of 350 nm.
  • the vertical alignment films 15 and 25 are polyamic acid-based vertical alignment films (manufactured by Nissan Chemical Industries) having a surface energy of 35 mJ / m 2 .
  • the potential V 1 of the first electrode 11 in the test cell, the potential V 2 of the second electrode 12 is a timing chart showing the potential V 4 in the potential V 3 and the fourth electrode 21 of the third electrode 13.
  • the potential V 2 of the potentials V 1 and second electrode 12 of the first electrode 11 is a rectangular wave having a period of four frames, each frame within one period (about 16.7 msec) Change to + aV, 0V, -aV, 0V.
  • the potential V 3 and the potential V 4 of the fourth electrode 21 of the third electrode 13 is much 0V (ground potential).
  • FIG. 9 shows a step-up curve and a step-down curve of the display device 100 (test cell).
  • FIG. 9 is a graph showing the relationship between the pixel voltage (voltage between the first electrode 11 and the second electrode 12 and the third electrode 13) Vop (V) and the reflectance (Y value) of the SCE method. .
  • the voltage-reflectance characteristic of the pixel has hysteresis, and the threshold voltage in the boost curve is higher than the threshold voltage in the buck curve. Further, the reflectance value in the boost curve when the applied voltage is increased from zero is substantially determined in a one-to-one relationship with the voltage value.
  • the mechanism by which such hysteresis is developed will be described with reference to FIG.
  • FIG. 10 shows the orientation state of the shape anisotropic particles 32 at points A-1, A-2, B-3, B-4, C-5, C-6, C-7 and A-8 in FIG. FIG.
  • FIG. 10 see the alignment states corresponding to points A-1, A-2, B-3, B-4, and C-5
  • the optical layer 30 increases.
  • the electric field strength in the thickness direction increases.
  • the shape anisotropic particles 32 in the vertical alignment state move to the first substrate 10 side and are horizontally aligned.
  • FIG. 10 see the alignment state corresponding to points C-6 and C-7
  • the applied voltage from the state in which many shape anisotropic particles 32 are horizontally aligned on the first substrate 10 side.
  • the shape anisotropic particles 32 do not exist so much on the counter substrate 20 side where the electric field strength is weak, most of the shape anisotropic particles 32 are in the horizontal alignment state on the first substrate 10 side. To maintain. This is the cause of the hysteresis. Further, as can be seen from FIG. 10 (see the alignment state corresponding to points A-8 and A-1), the shape anisotropy can no longer maintain the horizontal alignment state when the applied voltage is further decreased. The particles 32 diffuse toward the second substrate 20 side.
  • the step-up curve and the step-down curve (see FIG. 9) of the display device 100 include three regions A, B, and C.
  • the region A including points A-1, A-2, and A-8
  • the region B including points B-3 and B-4
  • the shape anisotropic particles 32 on the second substrate 20 side having relatively weak electric field strength move to the first substrate 10 side, and the orientation direction thereof changes.
  • the shape anisotropic particles 32 maintain the horizontal alignment state on the first substrate 10 side.
  • the voltage-reflectance characteristic of the pixel has a hysteresis characteristic, and the reflectance value in the boost curve when the applied voltage is increased from zero. Is determined in a substantially one-to-one relationship with the voltage value. Therefore, halftone display can be suitably performed by setting the writing voltage (applied voltage at the time of writing data to the pixel) based on the boosting curve.
  • the power consumption can be reduced by setting the holding voltage (the applied voltage when the pixel is in the data holding state) to be lower than the writing voltage. Furthermore, since the holding voltage is lower than the writing voltage, stress due to the voltage is suppressed, so that high reliability can be obtained.
  • FIG. 11 shows the result of verifying the repeatability of hysteresis.
  • FIG. 11 shows a case where the driving of increasing the pixel voltage Vop from the off voltage (0 V) to the writing voltage corresponding to the white display, subsequently decreasing the pixel voltage Vop to a predetermined holding voltage, and then setting the off voltage again is repeated three times. It is a graph which shows the pressure
  • the holding voltage is preferably 20% or more lower than the writing voltage as in the example shown in FIG. Since the power consumption is proportional to the square of the voltage, by reducing the holding voltage by 20% or more than the write voltage, the power consumption can be reduced by 40% or more, and the power consumption can be greatly reduced (for example, halved). Can be realized.
  • the reflectance in the step-down curve when the applied voltage is decreased from the write voltage, the reflectance is substantially constant in a range r from the write voltage to a predetermined voltage lower than the write voltage.
  • the reflectance is substantially constant means that the reflectance R in the range r is not less than 0.8 times and not more than 1.2 times the reflectance Rw when the write voltage is applied. (That is, the relationship 0.8Rw ⁇ R ⁇ 1.2Rw is satisfied).
  • the step-down curve has such a range r, the reflectance can be sufficiently maintained even in a low power consumption state (a state where a holding voltage lower than the writing voltage is applied to the pixel).
  • the variation in reflectance with respect to the voltage within the range r can be reduced.
  • the reflectance Rh of the pixel when the holding voltage is applied is 0.9 to 1.1 times the reflectance Rw of the pixel when the writing voltage is applied (that is, 0.9Rw ⁇ Rh). It is preferable that the relationship of ⁇ 1.1 Rw is satisfied. If the former reflectivity Rh is 0.9 to 1.1 times greater than the latter reflectivity Rw, the observer recognizes the change in reflectivity when the applied voltage changes from the write voltage to the holding voltage. Hateful.
  • FIG. 12 shows an example of driving switching between data writing and data holding state.
  • 12 (a) is, the potential V 1 of the first electrode 11 at the time of data writing, the potential V 2 of the second electrode 12, the potential V 3 of the third electrode 13, the potential V 4 and the pixel voltage of the fourth electrode 21 Vop is a timing chart showing, FIG. 12 (b), the potential V 1 of the first electrode 11 in the data holding state, the potential V 2 of the second electrode 12, the potential V 3 of the third electrode 13, the fourth electrode 21 3 is a timing chart showing a potential V4 and a pixel voltage Vop.
  • the potential V 2 of the potentials V 1 and second electrode 12 of the first electrode 11 is for the period of four frames, for each frame within one period (about 16.7 msec) It changes as + aV, 0V, -aV, 0V.
  • the potential V 3 and the potential V 4 of the fourth electrode 21 of the third electrode 13 is much 0V (ground potential). Therefore, the pixel voltage Vop at the time of data writing changes to + aV, 0V, ⁇ aV, and 0V every frame (about 16.7 msec) within one period with a period of four frames.
  • the potential V 2 of the potentials V 1 and second electrode 12 of the first electrode 11 is for the period of four frames, one frame (about 16.7 msec) in one cycle It changes to + bV, 0V, -bV, 0V every time.
  • the potential V 3 and the potential V 4 of the fourth electrode 21 of the third electrode 13 is much 0V (ground potential). Therefore, the pixel voltage Vop in the data holding state changes to + bV, 0V, ⁇ bV, and 0V every one frame (about 16.7 msec) within one period with a period of four frames.
  • a> b That is, the pixel voltage Vop in the data holding state is lower than the pixel voltage Vop at the time of data writing.
  • FIG. 13 shows a step-up curve and a step-down when the drive of increasing the pixel voltage Vop from the off voltage (0 V) to the write voltage, subsequently decreasing the pixel voltage Vop to a predetermined holding voltage, and then turning it off again is repeated five times. It is a graph which shows a curve.
  • the first and fifth writing voltages are voltages corresponding to white display, whereas the second, third and fourth writing voltages are voltages corresponding to halftone display.
  • FIG. 13 shows that the boosting curve in the second and subsequent driving matches the boosting curve in the first driving. Therefore, when switching from black display to halftone display, data is written with the pixel voltage Vop having a reflectance corresponding to the desired halftone display according to the boost curve, and then the pixel voltage Vop is reduced to a predetermined holding voltage. You can do it.
  • FIG. 13 also shows that there are ranges r1, r2, r3, and r4 in which the reflectivity is substantially constant in the step-down curve after the data is written with the voltage corresponding to the halftone display. .
  • FIG. 14 is a graph showing a step-up curve and a step-down curve including points P1 and P2 corresponding to the data writing and data holding states in the halftone D, and FIGS. It is a figure which shows the orientation state of the shape anisotropic particle 32 corresponding to P2.
  • the write voltage corresponding to the halftone D is applied to the pixel (point P1: see FIG. 15A), and the holding voltage corresponding to the halftone D is applied to the pixel.
  • Point P2: see FIG. 15B is reversible. That is, in the voltage range (corresponding to the region C in FIG. 9) in which the shape anisotropic particles 32 maintain the horizontal alignment state on the first substrate 10 side, the change in the alignment state is reversible. Therefore, switching from the display of halftone D to the display of halftone E on the higher gradation side (or white display) applies the write voltage corresponding to halftone E as it is from the data holding state corresponding to halftone D. (Point P3 in FIG. 14), and then the pixel voltage Vop is reduced to the holding voltage corresponding to the halftone E.
  • FIG. 16 is a graph showing a step-up curve and a step-down curve.
  • FIGS. 17A, 17B, 18A, and 18B are respectively shown at points P4, P5, P6, and P7 in FIG. It is a figure which shows the orientation state of the corresponding shape anisotropic particle.
  • the step-down curve differs depending on the magnitude of the previous writing voltage. For this reason, the pixel voltage Vop and the reflectance are not determined in a one-to-one relationship.
  • the boosting curve differs depending on the amount of the shape anisotropic particles 32 maintaining the horizontal alignment state. Vop and reflectance are not determined in a one-to-one relationship. Therefore, when switching from white or a certain halftone D display to a lower halftone F display, the pixel voltage Vop is once set to zero (hereinafter also referred to as “black insertion”).
  • the pixel voltage Vop and the reflectance can be determined in a one-to-one relationship according to a boosting curve (including points P6 and P7) with the starting point being zero. From FIG. 16, after black insertion is performed, data is written with the write voltage corresponding to the halftone F (point P7), and when data is written directly from the point P4 with the write voltage corresponding to the halftone F. It can be seen that the reflectance is different between (Point P5).
  • the applied voltage to the pixel is once reduced to zero, and then the original writing voltage is applied to the pixel. do it.
  • FIG. 19 shows another example of driving switching between data writing and data holding state.
  • FIG. 19 (a) the potential V 1 of the first electrode 11 at the time of data writing, the potential V 2 of the second electrode 12, the potential V 3 of the third electrode 13, the potential V 4 and the pixel voltage of the fourth electrode 21 Vop is a timing chart showing
  • FIG. 19 (b) the potential V 1 of the first electrode 11 in the data holding state, the potential V 2 of the second electrode 12, the potential V 3 of the third electrode 13, the fourth electrode 21 3 is a timing chart showing a potential V4 and a pixel voltage Vop.
  • the potential V 2 of the potentials V 1 and second electrode 12 of the first electrode 11, the four frames has a period, for each frame within one period (about 16.7 msec) It changes as + 10V, 0V, -10V, 0V.
  • the potential V 3 and the potential V 4 of the fourth electrode 21 of the third electrode 13 is much 0V (ground potential). For this reason, the pixel voltage Vop at the time of data writing changes to +10 V, 0 V, ⁇ 10 V, and 0 V every frame (about 16.7 msec) within one cycle with a cycle of four frames.
  • the potential V 2 of the potentials V 1 and second electrode 12 of the first electrode 11 is for the period of two frames, one frame within one period (about 16.7 msec) It changes to + 6V and -6V every time.
  • the potential V 3 and the potential V 4 of the fourth electrode 21 of the third electrode 13 is much 0V (ground potential). Therefore, the pixel voltage Vop in the data holding state changes to +6 V and ⁇ 6 V every frame (about 16.7 msec) within one cycle with a cycle of two frames.
  • Favorable drive sequence may differ between data writing and data holding state. Therefore, by adopting a configuration in which different driving sequences are executed in the data writing state and in the data holding state, a preferable driving sequence can be used for each of the data writing state and the data holding state.
  • the drive sequence shown in FIG. 19A is a preferable drive sequence at the time of data writing.
  • the voltage applied to the optical layer 30 is alternately switched between a first period having a relatively large absolute value and a second period having a relatively small absolute value.
  • the medium 31 can be swung, thereby increasing the proportion of the shape anisotropic particles 32 that change the desired orientation. Therefore, higher reflectance (or transmittance) can be realized.
  • the smaller the absolute value of the oscillating voltage in the second period is relative to the absolute value of the oscillating voltage in the first period, the stronger the medium 31 can be swung, and the oscillating voltage in the second period is substantially reduced.
  • the voltage is 0 V, the medium 31 can be rocked most strongly.
  • the driving sequence shown in FIG. 19B is a driving sequence preferable for the data holding state.
  • the polarity of the holding voltage is reversed every frame as in the example shown in FIG. 19B, the sticking of the shape anisotropic particles 32 to the first substrate 10 (deterioration of reliability due to seizure) is suppressed, Reliability can be improved.
  • FIG. 20 shows still another example of switching of driving between data writing and data holding state.
  • 20 (a) is the potential V 1 of the first electrode 11 at the time of data writing, the potential V 2 of the second electrode 12, the potential V 3 of the third electrode 13, the potential V 4 and the pixel voltage of the fourth electrode 21 Vop is a timing chart showing, FIG. 20 (b), the potential V 1 of the first electrode 11 in the data holding state, the potential V 2 of the second electrode 12, the potential V 3 of the third electrode 13, the fourth electrode 21 3 is a timing chart showing a potential V4 and a pixel voltage Vop.
  • the potential V 2 of the potentials V 1 and second electrode 12 of the first electrode 11 is for the period of four frames, for each frame within one period (about 16.7 msec) It changes as + 10V, 0V, -10V, 0V.
  • the potential V 3 and the potential V 4 of the fourth electrode 21 of the third electrode 13 is much 0V (ground potential). For this reason, the pixel voltage Vop at the time of data writing changes to +10 V, 0 V, ⁇ 10 V, and 0 V every frame (about 16.7 msec) within one cycle with a cycle of four frames.
  • the potential V 2 of the potentials V 1 and second electrode 12 of the first electrode 11 is for the period of 120 frames, the 60 frame by frame (1 sec) within one period + 6V , And changes to -6V.
  • the potential V 3 and the potential V 4 of the fourth electrode 21 of the third electrode 13 is much 0V (ground potential). Therefore, the pixel voltage Vop in the data holding state changes to +6 V and ⁇ 6 V every 60 frames (1 sec) within one cycle with a cycle of 120 frames.
  • the drive frequency when the holding voltage is applied to the pixel is lower than the drive frequency when the write voltage is applied to the pixel. Since the power consumption is proportional to the drive frequency, the drive frequency in the data holding state is made lower than the drive frequency at the time of data writing as in the example shown in FIGS. Low power consumption can be realized.
  • FIG. 21 shows an example of switching of the data holding state and driving during black insertion.
  • FIG. 21 (a) the potential V 1 of the first electrode 11 in the data holding state, the potential V 2 of the second electrode 12, the potential V 3 of the third electrode 13, the potential V 4 and the pixel voltage of the fourth electrode 21 Vop is a timing chart showing, FIG. 21 (b), the potential V 1 of the first electrode 11 at the time of black sweep, the potential V 2 of the second electrode 12, the potential V 3 of the third electrode 13, fourth electrode 21 6 is a timing chart showing a potential V 4 and a pixel voltage Vop.
  • the potential V 2 of the potentials V 1 and second electrode 12 of the first electrode 11 is for the period of 120 frames, the 60 frame by frame (1 sec) within one period + 6V, - It changes with 6V.
  • the potential V 3 and the potential V 4 of the fourth electrode 21 of the third electrode 13 is much 0V (ground potential). Therefore, the pixel voltage Vop in the data holding state changes to +6 V and ⁇ 6 V every 60 frames (1 sec) within one cycle with a cycle of 120 frames.
  • the second frame has a period, 1 period Therefore, it changes to + 10V and -10V every frame (about 16.7msec).
  • the potential V 4 of the fourth electrode 21 is always 0 V (ground potential). Therefore, the pixel voltage at the time of black insertion (here, the voltage between the first electrode 11, the second electrode 12, the third electrode 13, and the fourth electrode 21) Vop is one period with a period of two frames. Within each frame, the voltage changes to +10 V and ⁇ 10 V every frame (about 16.7 msec). Further, when driving as in the example shown in FIG. 21B is performed during black insertion, a vertical electric field is applied to the optical layer 30 (see FIG. 4).
  • a vertical electric field is applied to the optical layer 30 during black insertion (that is, the reflectance corresponding to the applied voltage of the current frame is higher than the reflectance corresponding to the writing voltage of the next frame).
  • a vertical electric field is once applied to the optical layer 30 and then an original writing voltage is applied to the pixel), and the applied voltage to the pixel is set to zero to bring the shape anisotropic particles 32 into a vertically aligned state.
  • the response speed can be improved as compared with the case of returning.
  • the hysteresis characteristic of the optical characteristics of the pixels is used.
  • the above-described hysteresis property of the optical characteristics is manifested in the display device (optical device) 100 in which the optical layer 30 includes the medium 31 and the shape anisotropic particles 32 as illustrated.
  • the medium 31 of the optical layer 30 is preferably a liquid crystal material.
  • the orientation direction of the shape anisotropic particles 32 can be efficiently changed by utilizing the change of the director of the liquid crystal molecules.
  • the liquid crystal material generally has a high specific resistance
  • the medium 31 is a liquid crystal material
  • off-leakage through the medium 31 is prevented in a state where the TFT after writing to the pixel is off. Therefore, a high voltage holding ratio can be obtained, and active matrix driving can be suitably performed.
  • the leakage current is small, power consumption can be further reduced.
  • the power consumption P of the display device 100 is expressed by the following formula (2), where C is the panel capacitance, V is the voltage applied to the optical layer 30, f is the drive frequency, and I is the leakage current.
  • P C ⁇ V ⁇ f + I ⁇ V (2)
  • Equation (2) The first term on the right side of Equation (2) should be called the pixel capacitance term, and the second term should be called the leakage current term. That is, the power consumption P can be considered separately for the pixel capacitance component and the leakage current component. When the specific resistance of the medium 31 is high, the leakage current I decreases, so that the power consumption P can be reduced as is apparent from the equation (2).
  • the behavior of the shape anisotropic particles 32 and the behavior of the liquid crystal molecules when an electric field is applied to the optical layer 30 match.
  • the electric field applied to the optical layer 30 is switched from a fringe electric field and / or a horizontal electric field to a vertical electric field
  • the shape anisotropic molecules 32 try to change from the horizontal alignment state to the vertical alignment state, and the liquid crystal molecules are also aligned horizontally. Attempts to change from state to vertical alignment. Therefore, since the number (existence probability) of the shape anisotropic particles 32 that are properly vertically aligned can be increased, a higher contrast ratio can be realized.
  • a liquid crystal material for a liquid crystal display device can be used widely and suitably.
  • a fluorine-based liquid crystal material in which fluorine is introduced into the side chain can be suitably used.
  • Fluorine-based liquid crystal materials are often used in active matrix-driven liquid crystal display devices and have large dielectric anisotropy and high specific resistance.
  • a dielectric constant in the major axis direction epsilon // 24.7, the short axial permittivity epsilon ⁇ 4.3, the specific resistance ⁇ is a liquid crystal material 6 ⁇ 10 13 ⁇ ⁇ cm be able to.
  • the dielectric constant and specific resistance of the liquid crystal material are not limited to those exemplified here.
  • the specific resistance of the liquid crystal material is preferably 1 ⁇ 10 11 to 12 ⁇ ⁇ cm or more.
  • the dielectric anisotropy ⁇ of the liquid crystal material preferably exceeds 10 ( ⁇ > 10).
  • a liquid crystal material having negative dielectric anisotropy (that is, a negative liquid crystal material) may be used as the medium 31.
  • the shape anisotropic particles 32 are caused by the alignment regulating force of the vertical alignment films 15 and 25. Is prevented from sticking to the substrate surface in a horizontal state.
  • a vertical alignment film for a liquid crystal display device in a VA (Vertical Alignment) mode for example, a polyimide-based or polyamic acid-based vertical alignment film manufactured by JSR or Nissan Chemical
  • VA Vertical Alignment
  • each of the vertical alignment films 15 and 25 is, for example, 100 nm. Of course, it is not limited to this.
  • the display device 100 is preferably capable of applying a fringe electric field and / or a lateral electric field to the optical layer 30 as in the present embodiment. That is, it is preferable that the display device 100 can use the horizontal electric field mode.
  • each shape anisotropic particle 32 basically takes only one of a horizontal alignment state and a vertical alignment state (that is, a binary state). Since the electric field strength in the thickness direction can be changed, the amount (number) of the shape anisotropic particles 32 horizontally oriented on the first substrate 10 side can be controlled. Therefore, halftone display can be suitably performed.
  • the vertical electric field mode since the electric field strength in the cell thickness direction is constant, halftone display is difficult.
  • the shape anisotropic particles 32 are attracted toward the first substrate 10 having a high electric field strength in accordance with the applied voltage at the time of data writing. In the range r) in FIG. 11, the horizontal orientation state of the shape anisotropic particles 32 can be maintained.
  • the structure of the 1st electrode 11, the 2nd electrode 12, and the 3rd electrode 13 is not limited to what was illustrated in FIG. FIG. 22 shows another electrode configuration of the display device 100.
  • a further insulating layer 17 is provided so as to cover the first electrode 11, and the second electrode 12 is provided on the further insulating layer 17. That is, the second electrode 12 is provided above the first electrode 11 via the further insulating layer 17.
  • a fringe electric field (electric field lines) is generated instead of a lateral electric field due to a potential difference between the first electrode 11 and the second electrode 12. Ef ′) is generated.
  • a further insulating layer 17 is located between the first electrode 11 and the second electrode 12, a short circuit occurs even if the interval between the first electrode 11 and the second electrode 12 is narrowed. The advantage is that there is no.
  • FIG. 23 shows still another electrode configuration of the display device 100.
  • the third electrode 13 has a plurality of slits 13 s formed at positions overlapping the first electrode 11 and the second electrode 12.
  • the fringe electric field distribution is concentrated from the end of the first electrode 11 or the second electrode 12 to between the first electrode 11 and the second electrode 12 (between adjacent branch portions 11a and 12a). ), It is possible to make it closer to the center.
  • the third electrode 13 is a solid electrode
  • the first electrode 11 and the second electrode 12 the third electrode 13, and the insulating layer 14 positioned between them. The advantage that an auxiliary capacity can be configured is obtained.
  • first TFT, second TFT, and third TFT are provided for each pixel.
  • the first electrode 11, the second electrode 12, and the third electrode 13 are electrically connected to the first TFT t1, the second TFT t2, and the third TFT t3, respectively.
  • a gate line GL extending in the row direction and a first source line SL1, a second source line SL2, and a third source line SL3 extending in the column direction are provided.
  • the first TFT t1 is supplied with a gate signal and a first source signal from the gate line GL and the first source line SL1.
  • the second TFT t2 is supplied with a gate signal and a second source signal from the gate line GL and the second source line SL2.
  • the third TFT t3 is supplied with the gate signal and the third source signal from the gate line GL and the third source line SL3.
  • the material of the semiconductor layer included in the first TFT t1, the second TFT t2, and the third TFT t3 various known semiconductor materials can be used.
  • amorphous silicon, polycrystalline silicon, continuous grain boundary crystal silicon (CGS: Continuous Grain Silicon) Etc. can be used.
  • the semiconductor layer may be an oxide semiconductor layer formed from an oxide semiconductor.
  • the oxide semiconductor layer includes, for example, an In—Ga—Zn—O-based semiconductor.
  • the In—Ga—Zn—O-based semiconductor may be amorphous or crystalline.
  • a semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface is preferable.
  • Such a crystal structure of an In—Ga—Zn—O-based semiconductor is disclosed in, for example, Japanese Patent Laid-Open No. 2012-134475.
  • Japanese Patent Laid-Open No. 2012-134475 the entire disclosure of Japanese Patent Application Laid-Open No. 2012-134475 is incorporated herein by reference.
  • a TFT having an In—Ga—Zn—O-based semiconductor layer has high mobility (more than 20 times that of an a-Si TFT) and low leakage current (less than one hundredth of that of an a-Si TFT). Therefore, when an oxide semiconductor layer formed using an In—Ga—Zn—O-based semiconductor is used as the semiconductor layer, power consumption can be further reduced because off-leakage is small.
  • the oxide semiconductor layer is not limited to the In—Ga—Zn—O-based semiconductor layer.
  • the oxide semiconductor layer includes, for example, a Zn—O based semiconductor (ZnO), an In—Zn—O based semiconductor (IZO), a Zn—Ti—O based semiconductor (ZTO), a Cd—Ge—O based semiconductor, a Cd—Pb—
  • ZnO Zn—O based semiconductor
  • IZO In—Zn—O based semiconductor
  • ZTO Zn—Ti—O based semiconductor
  • Cd—Ge—O based semiconductor a Cd—Pb—
  • An O-based semiconductor, an In—Sn—Zn—O based semiconductor (eg, In 2 O 3 —SnO 2 —ZnO), an In—Ga—Sn—O based semiconductor, or the like may be included.
  • the active matrix driving can be performed by the wiring structure shown in FIG.
  • the wiring structure of the back substrate 10 is not limited to the example shown in FIG.
  • an oxide semiconductor TFT including an oxide semiconductor layer is used as a thin film transistor (TFT) provided in each pixel, there is less off-leakage, and thus low-frequency driving as illustrated in FIG. 20B can be suitably performed. .
  • the fourth electrode 21 is provided on the second substrate 20 side, but the fourth electrode 21 may be omitted. This is because, when the optical layer 30 is in a state where no electric field is applied, the shape anisotropic particles 32 take a vertical alignment state. However, from the viewpoint of response speed, it is preferable to adopt a configuration in which the fourth electrode 21 is provided on the second substrate 20 side (that is, a configuration in which a vertical electric field can be applied to the optical layer 30). That is, it is preferable that display is performed by switching between a state in which a vertical electric field is generated in the optical layer 30 and a state in which a fringe electric field and / or a horizontal electric field is generated in the optical layer 30. Since the change from the former state to the latter state and the change from the latter state to the former state are both performed by changing the direction of the applied electric field, a sufficient response speed can be realized. .
  • the display device 100 can suitably perform halftone display. Therefore, by providing a color filter for each pixel, multicolor display corresponding to gradation can be performed.
  • the shape anisotropic particles 32 are not particularly limited in specific shape and material as long as the projected area on the substrate surface changes according to the applied voltage (direction of applied electric field) as described above.
  • the shape anisotropic member 32 may have a flake shape (flaky shape), a cylindrical shape, an oval shape, or the like. From the viewpoint of realizing a high contrast ratio, the shape anisotropic particle 32 preferably has a shape such that the ratio of the maximum projected area to the minimum projected area is 2: 1 or more.
  • the shape anisotropic particles 32 may be a dielectric multilayer film or may be formed from a cholesteric resin material.
  • an insulating layer (dielectric layer) is preferably formed on the surface of the shape anisotropic particles 32.
  • the dielectric constant of a single metal is an imaginary number, by forming an insulating layer (for example, a resin layer or a metal oxide layer) on the surface, the shape anisotropic particles 32 formed of a metal material can be handled as a dielectric. it can.
  • shape anisotropic particles 32 for example, aluminum flakes whose surfaces are coated with a resin material (for example, acrylic resin) can be used.
  • the aluminum flake content of the display medium layer 30 is, for example, 6% by weight.
  • aluminum flakes having an SiO 2 layer formed on the surface, aluminum flakes having an aluminum oxide layer formed on the surface, or the like can also be used.
  • a metal material other than aluminum may be used as the metal material.
  • the shape anisotropic particles 32 may be colored.
  • the length of the shape anisotropic particles 32 is not particularly limited, but is preferably 4 ⁇ m or more and 10 ⁇ m or less. If the length of the shape anisotropic particles 32 exceeds 10 ⁇ m, the shape anisotropic particles 32 may be difficult to move. On the other hand, when the length of the shape anisotropic particles 32 is less than 4 ⁇ m, it may be difficult to produce the shape anisotropic particles 32 or the reflective performance of the shape anisotropic particles 32 may be insufficient. Further, in the reflective display device as in the present embodiment, when it is desired to cover the substrate surface with the shape anisotropic particles 32 in the horizontal alignment state in order to obtain a high reflectance, the length of the shape anisotropic particles 32 is increased.
  • the thickness of the shape anisotropic particle 32 is not particularly limited. However, since the transmittance of the display medium layer 30 in the transparent state can be increased as the thickness of the shape anisotropic particles 32 is smaller, the thickness of the shape anisotropic particles 32 is larger than the inter-electrode distance g. It is preferably small (for example, 4 ⁇ m or less), and more preferably light wavelength or less (for example, 0.5 ⁇ m or less).
  • the specific gravity of the shape anisotropic particles 32 is preferably 11g / cm 3 or less, more preferably 3 g / cm 3 or less, further preferably the specific gravity substantially equal to that of the medium 31. This is because if the specific gravity of the shape anisotropic particles 32 is significantly different from the specific gravity of the medium 31, there may be a problem that the shape anisotropic particles 32 settle or float. From the viewpoint of increasing the effect of moving the shape anisotropic particles 32 by the peristaltic motion of the medium 31, the shape anisotropic particles 32 are preferably light.
  • the configuration in which the first substrate 10 which is an active matrix substrate is arranged on the back side is illustrated, but the arrangement of the first substrate 10 is not limited to this.
  • the first substrate 10 may be disposed on the front side. Since the first substrate 10 that is an active matrix substrate includes components formed from a light-shielding material, if the configuration in which the first substrate 10 is disposed on the back side is adopted, the shape anisotropic particles 32 The reflection effect can be used to the maximum.
  • the reflective display device 100 has been described as an example.
  • the embodiment of the present invention is also suitable for a transmissive display device (or a transmissive / reflective display device for transparent display). Used for.
  • a transmissive display device a light absorption layer (the light absorption layer 16 illustrated in FIG. 1 and the like) is not provided on the back substrate.
  • an illumination element backlight that irradiates light to the display panel is provided.
  • the voltage-transmittance characteristic of the pixel has hysteresis, and the threshold value in the boost curve indicating the voltage-transmittance characteristic when the applied voltage is increased
  • the voltage is higher than the threshold voltage in the step-down curve indicating the voltage-transmittance characteristics when the applied voltage is decreased.
  • the write voltage is set based on the boosting curve.
  • halftone display can be suitably performed.
  • power consumption can be reduced by setting the holding voltage lower than the writing voltage.
  • the transmittance is substantially constant in a range from the writing voltage to a predetermined voltage lower than the writing voltage.
  • the transmittance can be sufficiently maintained even in a low power consumption state, and the variation in transmittance with respect to the voltage within the above range can be reduced.
  • the holding voltage is preferably 20% or more lower than the writing voltage. By making the holding voltage 20% or more lower than the write voltage, a significant reduction in power consumption can be realized.
  • the pixel transmittance Th when the holding voltage is applied is 0.9 to 1.1 times the pixel transmittance Tw when the writing voltage is applied (that is, 0.9Tw ⁇ Th). It is preferable that the relationship of ⁇ 1.1 Tw is satisfied. If the former transmittance Th is 0.9 times or more and 1.1 times or less than the latter transmittance Tw, the observer recognizes the change in the transmittance when the applied voltage changes from the writing voltage to the holding voltage. Hard to do.
  • the applied voltage to the pixel is once reduced to zero and then the original writing voltage is applied to the pixel.
  • a vertical electric field may be once applied to the optical layer, and then an original writing voltage may be applied to the pixel.
  • an optical device that is excellent in low power consumption and capable of halftone display is provided.

Abstract

This optical apparatus (100) has pixels, the reflectance or transmittance of the pixels changing according to the magnitude of voltage applied to the pixels. The voltage-reflectance characteristics or voltage-transmittance characteristics of the pixels have hysteresis, such that the threshold voltage on a rising voltage curve that represents the voltage-reflectance characteristics or the voltage-transmittance characteristics when the applied voltage is increasing is higher than the threshold voltage on a falling voltage curve that represents the voltage-reflectance characteristics or the voltage-transmittance characteristics when the applied voltage is decreasing. The pixels lack memory in a state in which the applied voltage is zero, and the value of reflectance or transmittance on the rising voltage curve when the applied voltage is increased from zero is determined by a substantially one-to-one relationship to the voltage value. The write voltage, which is the applied voltage to the pixels when writing data, is set on the basis of the rising voltage curve.

Description

光学装置Optical device
　本発明は、光学装置に関し、特に、印加電圧の大きさに応じて反射率または透過率が変化する画素を有する光学装置に関する。 The present invention relates to an optical device, and more particularly to an optical device having a pixel whose reflectance or transmittance changes according to the magnitude of an applied voltage.
　近年、表示装置の低消費電力化のための様々な提案がなされている。 In recent years, various proposals for reducing power consumption of display devices have been made.
　例えば、特許文献１には、コレステリック液晶のメモリ性を利用した液晶表示装置が開示されている。コレステリック液晶は、印加電圧がゼロのときにその配向状態を維持することができる性質（メモリ性）を有する。そのため、このメモリ性を利用して画像データの書き込み回数を減らすことにより、消費電力を低減することができる。 For example, Patent Document 1 discloses a liquid crystal display device using the memory property of cholesteric liquid crystal. The cholesteric liquid crystal has a property (memory property) that can maintain the alignment state when the applied voltage is zero. Therefore, power consumption can be reduced by reducing the number of times image data is written using this memory property.
　また、特許文献２には、画素メモリ内蔵型の液晶表示装置が開示されている。この液晶表示装置では、各画素の画素回路にスタティックメモリが含まれていることにより、静止画を表示する場合にはリフレッシュ動作が不要となるので、消費電力を低減することができる。 Patent Document 2 discloses a liquid crystal display device with a built-in pixel memory. In this liquid crystal display device, since a static memory is included in the pixel circuit of each pixel, a refresh operation is not necessary when displaying a still image, and thus power consumption can be reduced.
特開平１０－１０５０８５号公報Japanese Patent Laid-Open No. 10-105085 特開２００７－１９９４４１号公報JP 2007-199441 A
　特許文献１の技術は、表示媒体層（液晶層）の構成材料であるコレステリック液晶材料のメモリ性を利用するものであるので、当然ながら、表示媒体層自体がメモリ性を有しない表示装置には適用できない。 Since the technology of Patent Document 1 uses the memory property of a cholesteric liquid crystal material that is a constituent material of the display medium layer (liquid crystal layer), naturally, the display medium layer itself has no memory property. Not applicable.
　これに対し、特許文献２の技術は、表示媒体層自体がメモリ性を有しない表示装置にも適用できるものの、画像データの書き込み時の印加電圧が高い場合には、画素メモリを動作させるために必要な消費電力が大きくなってしまう。また、画素メモリは２値のデジタル回路であるので、特許文献２の技術には、中間調表示ができないという問題もある。 On the other hand, although the technique of Patent Document 2 can be applied to a display device in which the display medium layer itself does not have a memory property, in order to operate the pixel memory when the applied voltage at the time of writing image data is high. Necessary power consumption increases. Further, since the pixel memory is a binary digital circuit, the technique of Patent Document 2 has a problem that halftone display cannot be performed.
　本発明は、上記問題に鑑みてなされたものであり、その目的は、低消費電力性に優れ、中間調表示が可能な光学装置を提供することにある。 The present invention has been made in view of the above problems, and an object thereof is to provide an optical device that is excellent in low power consumption and capable of halftone display.
　本発明の実施形態による光学装置は、画素を有し、前記画素への印加電圧の大きさに応じて前記画素の反射率または透過率が変化する光学装置であって、前記画素の電圧－反射率特性または電圧－透過率特性がヒステリシス性を有し、印加電圧を増加させていくときの前記電圧－反射率特性または前記電圧－透過率特性を示す昇圧曲線における閾値電圧が、印加電圧を減少させていくときの前記電圧－反射率特性または前記電圧－透過率特性を示す降圧曲線における閾値電圧よりも高く、印加電圧がゼロである状態において、前記画素はメモリ性を有しておらず、印加電圧をゼロから増加させていくときの前記昇圧曲線における反射率または透過率の値は、電圧値に対して実質的に１対１の関係で決まり、前記画素へのデータ書き込み時の印加電圧である書き込み電圧が、前記昇圧曲線に基づいて設定されている。 An optical device according to an embodiment of the present invention is an optical device having a pixel, and the reflectance or transmittance of the pixel changes according to the magnitude of a voltage applied to the pixel, the voltage-reflection of the pixel The threshold voltage in the boost curve indicating the voltage-reflectance characteristic or the voltage-transmittance characteristic when the applied voltage is increased decreases the applied voltage. In the state where the applied voltage is zero, which is higher than the threshold voltage in the step-down curve indicating the voltage-reflectance characteristic or the voltage-transmittance characteristic, the pixel does not have a memory property, When the applied voltage is increased from zero, the value of the reflectance or transmittance in the boost curve is determined substantially in a one-to-one relationship with the voltage value, and the value at the time of writing data to the pixel is determined. A pressurized voltage writing voltage is set on the basis of the boost curve.
　ある実施形態では、前記画素がデータ保持状態にあるときの印加電圧である保持電圧が、前記書き込み電圧よりも低く設定されている。 In one embodiment, a holding voltage that is an applied voltage when the pixel is in a data holding state is set lower than the writing voltage.
　ある実施形態では、印加電圧を前記書き込み電圧から減少させていくときの前記降圧曲線において、前記書き込み電圧から前記書き込み電圧よりも低い所定の電圧までの範囲で反射率または透過率が実質的に一定である。 In one embodiment, in the step-down curve when the applied voltage is decreased from the writing voltage, the reflectance or transmittance is substantially constant in a range from the writing voltage to a predetermined voltage lower than the writing voltage. It is.
　ある実施形態では、前記保持電圧は、前記書き込み電圧よりも２０％以上低い。 In one embodiment, the holding voltage is 20% or more lower than the write voltage.
　ある実施形態では、前記保持電圧が印加されているときの前記画素の反射率または透過率は、前記書き込み電圧が印加されているときの前記画素の反射率または透過率の０．９倍以上１．１倍以下である。 In one embodiment, the reflectance or transmittance of the pixel when the holding voltage is applied is not less than 0.9 times the reflectance or transmittance of the pixel when the write voltage is applied. .1 or less.
　ある実施形態では、前記画素に前記保持電圧が印加されるときの駆動周波数が、前記画素に前記書き込み電圧が印加されるときの駆動周波数よりも低い。 In one embodiment, a driving frequency when the holding voltage is applied to the pixel is lower than a driving frequency when the writing voltage is applied to the pixel.
　ある実施形態では、本発明による光学装置は、互いに対向するように設けられた第１基板および第２基板と、前記第１基板および前記第２基板の間に設けられた光学層と、を備え、前記光学層は、媒体と、前記媒体中に分散され、形状異方性を有する形状異方性粒子とを含む。 In one embodiment, an optical device according to the present invention includes a first substrate and a second substrate provided to face each other, and an optical layer provided between the first substrate and the second substrate. The optical layer includes a medium and shape anisotropic particles dispersed in the medium and having shape anisotropy.
　ある実施形態では、前記媒体は、液晶材料を含む。 In one embodiment, the medium includes a liquid crystal material.
　ある実施形態では、前記画素に前記書き込み電圧が印加されるときと、前記画素に前記保持電圧が印加されるときとで、互いに異なる駆動シーケンスが実行される。 In one embodiment, different driving sequences are executed when the writing voltage is applied to the pixel and when the holding voltage is applied to the pixel.
　ある実施形態では、前記保持電圧の極性が１フレームごとに反転する。 In one embodiment, the polarity of the holding voltage is inverted every frame.
　ある実施形態では、本発明による光学装置は、前記光学層に横電界および／またはフリンジ電界を印加し得る。 In one embodiment, the optical device according to the present invention may apply a lateral electric field and / or a fringe electric field to the optical layer.
　ある実施形態では、本発明による光学装置は、現フレームの印加電圧に対応する反射率が次フレームの書き込み電圧に対応する反射率よりも高い場合、または、現フレームの印加電圧に対応する透過率が次フレームの書き込み電圧に対応する透過率よりも低い場合、前記画素への印加電圧をいったんゼロにし、その後、前記画素に本来の書き込み電圧を印加する。 In one embodiment, the optical device according to the present invention has a transmittance corresponding to the applied voltage of the current frame when the reflectance corresponding to the applied voltage of the current frame is higher than the reflectance corresponding to the writing voltage of the next frame. Is lower than the transmittance corresponding to the writing voltage of the next frame, the applied voltage to the pixel is once reduced to zero, and then the original writing voltage is applied to the pixel.
　ある実施形態では、本発明による光学装置は、現フレームの印加電圧に対応する反射率が次フレームの書き込み電圧に対応する反射率よりも高い場合、または、現フレームの印加電圧に対応する透過率が次フレームの書き込み電圧に対応する透過率よりも低い場合、前記光学層にいったん縦電界を印加し、その後、前記画素に本来の書き込み電圧を印加する。 In one embodiment, the optical device according to the present invention has a transmittance corresponding to the applied voltage of the current frame when the reflectance corresponding to the applied voltage of the current frame is higher than the reflectance corresponding to the writing voltage of the next frame. Is lower than the transmittance corresponding to the writing voltage of the next frame, a vertical electric field is once applied to the optical layer, and then the original writing voltage is applied to the pixel.
　ある実施形態では、本発明による光学装置は、前記画素に設けられた薄膜トランジスタを有し、前記薄膜トランジスタは、酸化物半導体層を含む。 In one embodiment, an optical device according to the present invention includes a thin film transistor provided in the pixel, and the thin film transistor includes an oxide semiconductor layer.
　ある実施形態では、本発明による光学装置は、前記画素に設けられたカラーフィルタを備える。 In one embodiment, the optical device according to the present invention includes a color filter provided in the pixel.
　本発明の実施形態によると、低消費電力性に優れ、中間調表示が可能な光学装置が提供される。 According to the embodiment of the present invention, an optical device that is excellent in low power consumption and capable of halftone display is provided.
本発明の実施形態による表示装置（光学装置）１００を模式的に示す断面図であり、図２中の１Ａ－１Ａ’線に沿った断面を示している。FIG. 3 is a cross-sectional view schematically showing a display device (optical device) 100 according to an embodiment of the present invention, showing a cross section taken along line 1A-1A ′ in FIG. 2. 表示装置１００を模式的に示す平面図である。3 is a plan view schematically showing the display device 100. FIG. （ａ）は、光学層３０に電界が印加されていないときの表示装置１００を模式的に示す図であり、（ｂ）は、光学層３０にフリンジ電界が印加されているときの表示装置１００を模式的に示す図である。(A) is a figure which shows typically the display apparatus 100 when the electric field is not applied to the optical layer 30, (b) is the display apparatus 100 when the fringe electric field is applied to the optical layer 30. FIG. 光学層３０に縦電界が印加されているときの表示装置１００を模式的に示す図である。3 is a diagram schematically showing the display device 100 when a vertical electric field is applied to the optical layer 30. FIG. 光学層３０にフリンジ電界および横電界が印加されているときの表示装置１００を模式的に示す図である。3 is a diagram schematically showing the display device 100 when a fringe electric field and a lateral electric field are applied to the optical layer 30. FIG. （ａ）は、表示媒体層３０に印加されている電界をフリンジ電界および／または横電界から縦電界に変化させた直後の光学層３０の様子を示す図であり、（ｂ）は、その後十分な時間が経過した後の光学層３０の様子を示す図である。(A) is a figure which shows the mode of the optical layer 30 immediately after changing the electric field applied to the display medium layer 30 from a fringe electric field and / or a horizontal electric field to a vertical electric field, (b) is enough after that It is a figure which shows the mode of the optical layer 30 after a lapse of time. テストセルにおける電極構造を示す平面図である。It is a top view which shows the electrode structure in a test cell. テストセルにおける第１電極１１の電位Ｖ1、第２電極１２の電位Ｖ2、第３電極１３の電位Ｖ3および第４電極２１の電位Ｖ4を示すタイミングチャートである。The potential V 1 of the first electrode 11 in the test cell, the potential V 2 of the second electrode 12 is a timing chart showing the potential V 4 in the potential V 3 and the fourth electrode 21 of the third electrode 13. 画素電圧（第１電極１１および第２電極１２と第３電極１３との間の電圧）Ｖｏｐ（Ｖ）と、ＳＣＥ方式の反射率（Ｙ値）との関係を示すグラフである。It is a graph which shows the relationship between pixel voltage (The voltage between the 1st electrode 11, the 2nd electrode 12, and the 3rd electrode 13) Vop (V) and the reflectance (Y value) of a SCE system. 図９中の点Ａ－１、Ａ－２、Ｂ－３、Ｂ－４、Ｃ－５、Ｃ－６、Ｃ－７およびＡ－８における形状異方性粒子３２の配向状態を模式的に示す図である。The orientation state of the shape anisotropic particles 32 at points A-1, A-2, B-3, B-4, C-5, C-6, C-7 and A-8 in FIG. FIG. 画素電圧Ｖｏｐを、オフ電圧（０Ｖ）から白表示に対応する書き込み電圧まで増加させ、続いて所定の保持電圧まで減少させ、その後再びオフ電圧にするという駆動を３回繰り返したときの昇圧曲線および降圧曲線を示すグラフである。A boosting curve obtained when the driving of increasing the pixel voltage Vop from the off voltage (0 V) to the writing voltage corresponding to white display, subsequently decreasing the pixel voltage Vop to a predetermined holding voltage, and then setting the off voltage again is repeated three times. It is a graph which shows a pressure | voltage fall curve. （ａ）は、データ書き込み時における第１電極１１の電位Ｖ1、第２電極１２の電位Ｖ2、第３電極１３の電位Ｖ3、第４電極２１の電位Ｖ4および画素電圧Ｖｏｐを示すタイミングチャートであり、（ｂ）は、データ保持状態における第１電極１１の電位Ｖ1、第２電極１２の電位Ｖ2、第３電極１３の電位Ｖ3、第４電極２１の電位Ｖ4および画素電圧Ｖｏｐを示すタイミングチャートである。(A) shows the potential V 1 of the first electrode 11 at the time of data writing, the potential V 2 of the second electrode 12, the potential V 3 of the third electrode 13, the potential V 4 and the pixel voltage Vop of the fourth electrode 21 is a timing chart, (b), the potential V 1 of the first electrode 11 in the data holding state, the potential V 2 of the second electrode 12, the potential V 3 of the third electrode 13, the potential V 4 and the fourth electrode 21 It is a timing chart which shows pixel voltage Vop. 画素電圧Ｖｏｐを、オフ電圧（０Ｖ）から書き込み電圧まで増加させ、続いて所定の保持電圧まで減少させ、その後再びオフ電圧にするという駆動を５回繰り返したときの昇圧曲線および降圧曲線を示すグラフである。A graph showing a step-up curve and a step-down curve when the driving of increasing the pixel voltage Vop from the off voltage (0 V) to the writing voltage, subsequently decreasing the pixel voltage Vop to a predetermined holding voltage, and then turning it off again is repeated five times It is. ある中間調Ｄでのデータ書き込みおよびデータ保持状態に対応する点Ｐ１およびＰ２を含む昇圧曲線および降圧曲線を示すグラフである。6 is a graph showing a step-up curve and a step-down curve including points P1 and P2 corresponding to data writing and data holding states in a certain halftone D. （ａ）および（ｂ）は、それぞれ図１４中の点Ｐ１およびＰ２に対応する形状異方性粒子３２の配向状態を示す図である。(A) And (b) is a figure which shows the orientation state of the shape anisotropic particle 32 corresponding to the points P1 and P2 in FIG. 14, respectively. 表示装置１００（テストセル）の昇圧曲線および降圧曲線を示すグラフである。It is a graph which shows the pressure | voltage rise curve and pressure | voltage fall curve of the display apparatus 100 (test cell). （ａ）および（ｂ）は、それぞれ図１６中の点Ｐ４およびＰ５に対応する形状異方性粒子３２の配向状態を示す図である。(A) And (b) is a figure which shows the orientation state of the shape anisotropic particle 32 corresponding to the points P4 and P5 in FIG. 16, respectively. （ａ）および（ｂ）は、それぞれ図１６中の点Ｐ６およびＰ７に対応する形状異方性粒子３２の配向状態を示す図である。(A) And (b) is a figure which shows the orientation state of the shape anisotropic particle 32 corresponding to the points P6 and P7 in FIG. 16, respectively. （ａ）は、データ書き込み時における第１電極１１の電位Ｖ1、第２電極１２の電位Ｖ2、第３電極１３の電位Ｖ3、第４電極２１の電位Ｖ4および画素電圧Ｖｏｐを示すタイミングチャートであり、（ｂ）は、データ保持状態における第１電極１１の電位Ｖ1、第２電極１２の電位Ｖ2、第３電極１３の電位Ｖ3、第４電極２１の電位Ｖ4および画素電圧Ｖｏｐを示すタイミングチャートである。(A) shows the potential V 1 of the first electrode 11 at the time of data writing, the potential V 2 of the second electrode 12, the potential V 3 of the third electrode 13, the potential V 4 and the pixel voltage Vop of the fourth electrode 21 is a timing chart, (b), the potential V 1 of the first electrode 11 in the data holding state, the potential V 2 of the second electrode 12, the potential V 3 of the third electrode 13, the potential V 4 and the fourth electrode 21 It is a timing chart which shows pixel voltage Vop. （ａ）は、データ書き込み時における第１電極１１の電位Ｖ1、第２電極１２の電位Ｖ2、第３電極１３の電位Ｖ3、第４電極２１の電位Ｖ4および画素電圧Ｖｏｐを示すタイミングチャートであり、（ｂ）は、データ保持状態における第１電極１１の電位Ｖ1、第２電極１２の電位Ｖ2、第３電極１３の電位Ｖ3、第４電極２１の電位Ｖ4および画素電圧Ｖｏｐを示すタイミングチャートである。(A) shows the potential V 1 of the first electrode 11 at the time of data writing, the potential V 2 of the second electrode 12, the potential V 3 of the third electrode 13, the potential V 4 and the pixel voltage Vop of the fourth electrode 21 is a timing chart, (b), the potential V 1 of the first electrode 11 in the data holding state, the potential V 2 of the second electrode 12, the potential V 3 of the third electrode 13, the potential V 4 and the fourth electrode 21 It is a timing chart which shows pixel voltage Vop. （ａ）は、データ保持状態における第１電極１１の電位Ｖ１、第２電極１２の電位Ｖ２、第３電極１３の電位Ｖ３、第４電極２１の電位Ｖ４および画素電圧Ｖｏｐを示すタイミングチャートであり、（ｂ）は、黒挿引時における第１電極１１の電位Ｖ１、第２電極１２の電位Ｖ２、第３電極１３の電位Ｖ３、第４電極２１の電位Ｖ４および画素電圧Ｖｏｐを示すタイミングチャートである。(A) is a timing chart showing the potential V1 of the first electrode 11, the potential V2 of the second electrode 12, the potential V3 of the third electrode 13, the potential V4 of the fourth electrode 21 and the pixel voltage Vop in the data holding state. , (B) is a timing chart showing the potential V1 of the first electrode 11, the potential V2 of the second electrode 12, the potential V3 of the third electrode 13, the potential V4 of the fourth electrode 21 and the pixel voltage Vop at the time of black insertion. It is. 表示装置１００の他の電極構成を示す図である。6 is a diagram showing another electrode configuration of the display device 100. FIG. 表示装置１００のさらに他の電極構成を示す図である。FIG. 10 is a diagram showing still another electrode configuration of the display device 100. アクティブマトリクス駆動を行う場合の背面基板１０における具体的な配線構造の例を示す平面図である。It is a top view which shows the example of the specific wiring structure in the back substrate 10 in the case of performing active matrix drive.
　本発明の実施形態による光学装置は、画素を有し、この画素の光学特性（具体的には反射率または透過率）が、画素への印加電圧の大きさに応じて変化する。また、画素の電圧－反射率特性または電圧－透過率特性は、ヒステリシス性を有し、印加電圧を増加させていくときの電圧－反射率特性または電圧－透過率特性を示す曲線（以下では「昇圧曲線」と呼ぶ）における閾値電圧が、印加電圧を減少させていくときの電圧－反射率特性または電圧－透過率特性を示す曲線（以下では「降圧曲線」と呼ぶ）における閾値電圧よりも高い。さらに、印加電圧がゼロである状態において、画素はメモリ性を有しておらず、印加電圧をゼロから増加させていくときの昇圧曲線における反射率または透過率の値は、電圧値に対して実質的に１対１の関係で決まる。そして、画素へのデータ書き込み時の印加電圧（以下では「書き込み電圧」と呼ぶ）が、昇圧曲線に基づいて設定されている。 The optical device according to the embodiment of the present invention has a pixel, and an optical characteristic (specifically, reflectance or transmittance) of the pixel changes according to the magnitude of the voltage applied to the pixel. Further, the voltage-reflectance characteristic or voltage-transmittance characteristic of the pixel has a hysteresis characteristic, and a curve indicating the voltage-reflectance characteristic or the voltage-transmittance characteristic when the applied voltage is increased (hereinafter referred to as “ The threshold voltage in the “boost curve” is higher than the threshold voltage in the curve indicating the voltage-reflectance characteristic or voltage-transmittance characteristic when the applied voltage is decreased (hereinafter referred to as “step-down curve”). . Further, in a state where the applied voltage is zero, the pixel does not have memory characteristics, and the reflectance or transmittance value in the boost curve when the applied voltage is increased from zero is the voltage value. It is determined substantially by a one-to-one relationship. An applied voltage at the time of data writing to the pixel (hereinafter referred to as “write voltage”) is set based on the boost curve.
　本発明の実施形態による光学装置は、上述したような、画素の光学特性のヒステリシス性を利用する構成を有していることにより、中間調表示を好適に行うことができる。また、画素がデータ保持状態にあるときの印加電圧（以下では「保持電圧」と呼ぶ）を書き込み電圧よりも低く設定することにより、消費電力を低減することもできる。 The optical device according to the embodiment of the present invention can suitably perform halftone display by having the configuration using the hysteresis characteristic of the optical characteristics of the pixels as described above. In addition, power consumption can be reduced by setting an applied voltage (hereinafter referred to as “holding voltage”) when the pixel is in a data holding state to be lower than a writing voltage.
　以下、図面を参照しながら本発明による実施形態の光学装置をより具体的に説明する。なお、本発明は以下の実施形態に限定されるものではない。 Hereinafter, an optical device according to an embodiment of the present invention will be described in more detail with reference to the drawings. In addition, this invention is not limited to the following embodiment.
　図１および図２に、本発明の実施形態による光学装置（表示装置）１００を示す。図１は、表示装置１００を模式的に示す断面図であり、図２は、表示装置１００を模式的に示す平面図である。図１は、図２中の１Ａ－１Ａ’線に沿った断面を示している。 1 and 2 show an optical device (display device) 100 according to an embodiment of the present invention. FIG. 1 is a cross-sectional view schematically showing the display device 100, and FIG. 2 is a plan view schematically showing the display device 100. FIG. 1 shows a cross section taken along line 1A-1A 'in FIG.
　表示装置１００は、外部から入射する光（周囲光）を用いて反射モードで表示を行うことができる反射型表示装置である。表示装置１００は、画素を有する。ここでは、表示装置１００は、マトリクス状に配列された複数の画素を有する。 The display device 100 is a reflective display device that can perform display in a reflection mode using light incident from the outside (ambient light). The display device 100 includes pixels. Here, the display device 100 includes a plurality of pixels arranged in a matrix.
　図１に示すように、表示装置１００は、互いに対向するように設けられた第１基板１０および第２基板２０と、第１基板１０および第２基板２０の間に設けられた光学層（表示媒体層）３０とを備える。以下では、第１基板１０および第２基板２０のうちの、相対的に背面側に位置する第１基板１０を「背面側基板」と呼ぶことがあり、相対的に前面側（つまり観察者側）に位置する第２基板２０を「前面側基板」と呼ぶことがある。 As shown in FIG. 1, a display device 100 includes a first substrate 10 and a second substrate 20 provided so as to face each other, and an optical layer (display) provided between the first substrate 10 and the second substrate 20. Medium layer) 30. Hereinafter, of the first substrate 10 and the second substrate 20, the first substrate 10 positioned relatively on the back side may be referred to as a “back side substrate” and may be referred to relatively on the front side (that is, on the viewer side). The second substrate 20 positioned at () may be referred to as a “front substrate”.
　第１基板（背面側基板）１０は、互いに異なる電位を与えられ得る第１電極１１および第２電極１２を有する。第１電極１１および第２電極１２は、複数の画素のそれぞれに設けられている。第１電極１１および第２電極１２のそれぞれは、図２に示すように、櫛歯形状を有する。 The first substrate (back substrate) 10 has a first electrode 11 and a second electrode 12 that can be given different potentials. The first electrode 11 and the second electrode 12 are provided in each of the plurality of pixels. Each of the 1st electrode 11 and the 2nd electrode 12 has a comb-tooth shape, as shown in FIG.
　第１電極１１は、幹部１１ｂと、幹部１１ｂから延びる複数の枝部１１ａとを有する。第２電極１２は、同様に、幹部１２ｂと、幹部１２ｂから延びる複数の枝部１２ａとを有する。第１電極１１と第２電極１２とは、それぞれの複数の枝部１１ａ、１２ａが所定の間隙（以下では「電極間距離」と呼ぶこともある）ｇを介して噛合するように配置されている。 The first electrode 11 has a trunk portion 11b and a plurality of branch portions 11a extending from the trunk portion 11b. Similarly, the second electrode 12 includes a trunk portion 12b and a plurality of branch portions 12a extending from the trunk portion 12b. The first electrode 11 and the second electrode 12 are arranged so that the plurality of branch portions 11a and 12a mesh with each other via a predetermined gap (hereinafter also referred to as “interelectrode distance”) g. Yes.
　電極間距離ｇに特に制限はない。また、第１電極１１の枝部１１ａの幅ｗ1および第２電極１２の枝部１２ａの幅ｗ2にも特に制限はない。電極間距離ｇ、第１電極１１の枝部１１ａの幅ｗ1および第２電極１２の枝部１２ａの幅ｗ2は、それぞれ例えば数μｍ～十数μｍ程度である。第１電極１１の枝部１１ａの幅ｗ1と、第２電極１２の枝部１２ａの幅ｗ2とは、同じであってもよいし、異なっていてもよい。 There is no restriction | limiting in particular in the distance g between electrodes. Further, the width w 1 of the branch part 11 a of the first electrode 11 and the width w 2 of the branch part 12 a of the second electrode 12 are not particularly limited. The inter-electrode distance g, the width w 1 of the branch portion 11a of the first electrode 11, and the width w 2 of the branch portion 12a of the second electrode 12 are each about several μm to several tens of μm, for example. The width w 1 of the branch portion 11a of the first electrode 11 and the width w 2 of the branch portion 12a of the second electrode 12 may be the same or different.
　また、第１基板１０は、絶縁層１４を介して第１電極１１および第２電極１２の下方に設けられた第３電極１３をさらに有する。以下では、第１電極１１、第２電極１２および第３電極１３を、それぞれ「第１上層電極」、「第２上層電極」および「下層電極」と呼ぶこともある。図１および図２に示している例では、第３電極１３は、スリットや切欠き部が形成されていない、いわゆるべた電極である。 The first substrate 10 further includes a third electrode 13 provided below the first electrode 11 and the second electrode 12 with the insulating layer 14 interposed therebetween. Hereinafter, the first electrode 11, the second electrode 12, and the third electrode 13 may be referred to as “first upper layer electrode”, “second upper layer electrode”, and “lower layer electrode”, respectively. In the example shown in FIGS. 1 and 2, the third electrode 13 is a so-called solid electrode in which no slit or notch is formed.
　第１基板１０は、典型的には、アクティブマトリクス基板であり、各画素に設けられた複数の薄膜トランジスタ（ＴＦＴ）と、各種の配線（ＴＦＴに電気的に接続されたゲート配線、ソース配線など）とを有する（いずれもここでは不図示）。第１電極１１、第２電極１２および第３電極１３は、それぞれ対応するＴＦＴに電気的に接続されており、ＴＦＴを介してソース信号に対応した電圧を供給される。 The first substrate 10 is typically an active matrix substrate, and includes a plurality of thin film transistors (TFTs) provided in each pixel and various wirings (a gate wiring, a source wiring, etc. electrically connected to the TFT). (Both not shown here). The first electrode 11, the second electrode 12, and the third electrode 13 are electrically connected to the corresponding TFTs, respectively, and supplied with a voltage corresponding to the source signal through the TFTs.
　第１基板１０は、さらに、光を吸収する光吸収層１６を有する。光吸収層１６の材料に特に制限はない。光吸収層１６の材料としては、例えば、液晶表示装置等のカラーフィルタに含まれるブラックマトリクスの材料などに用いられる顔料を用いることができる。あるいは、光吸収層１６として、二層構造の低反射クロム膜（クロム層と酸化クロム層とが積層された構造を有する）を用いることもできる。 The first substrate 10 further includes a light absorption layer 16 that absorbs light. There is no restriction | limiting in particular in the material of the light absorption layer 16. FIG. As a material of the light absorption layer 16, for example, a pigment used for a black matrix material included in a color filter of a liquid crystal display device or the like can be used. Alternatively, a low-reflection chromium film having a two-layer structure (having a structure in which a chromium layer and a chromium oxide layer are stacked) can be used as the light absorption layer 16.
　第１基板１０の構成要素（上述した第１電極１１など）は、絶縁性を有する基板（例えばガラス基板）１０ａによって支持されている。なお、図１では、光吸収層１６は基板１０ａの背面側に設けられているが、光吸収層１６が基板１０ａの光学層３０側に設けられていてもよい。 The components of the first substrate 10 (such as the first electrode 11 described above) are supported by an insulating substrate (for example, a glass substrate) 10a. In FIG. 1, the light absorption layer 16 is provided on the back side of the substrate 10a. However, the light absorption layer 16 may be provided on the optical layer 30 side of the substrate 10a.
　第２基板（前面側基板）２０は、第１電極１１、第２電極１２および第３電極１３に対向する第４電極（対向電極）２１を有する。第４電極２１は、スリットや切欠き部が形成されていない、いわゆるべた電極であってよい。図１に示している例では、第２基板２０は、第４電極２１上に設けられた誘電体層（オーバーコート層）２２をさらに有する。第４電極２１は、画素ごとに電気的に独立している必要はなく、すべての画素に共通の連続した単一の導電膜（つまり共通電極）であってよい。第４電極２１が、すべての画素に共通のべた電極であると、フォトリソグラフィ技術によるパターニングが不要となるので、製造コストを低減することができる。また、カラー表示を行う場合には、第２基板２０は、カラーフィルタ（不図示）を有する。 The second substrate (front substrate) 20 has a fourth electrode (counter electrode) 21 facing the first electrode 11, the second electrode 12 and the third electrode 13. The fourth electrode 21 may be a so-called solid electrode in which no slit or notch is formed. In the example illustrated in FIG. 1, the second substrate 20 further includes a dielectric layer (overcoat layer) 22 provided on the fourth electrode 21. The fourth electrode 21 does not need to be electrically independent for each pixel, and may be a continuous single conductive film (that is, a common electrode) common to all pixels. When the fourth electrode 21 is a solid electrode common to all the pixels, patterning by a photolithography technique is not necessary, so that the manufacturing cost can be reduced. When performing color display, the second substrate 20 includes a color filter (not shown).
　第２基板２０の構成要素（上述した第４電極２１など）は、絶縁性を有する基板（例えばガラス基板）２０ａによって支持されている。 The components of the second substrate 20 (such as the fourth electrode 21 described above) are supported by an insulating substrate (for example, a glass substrate) 20a.
　第１電極１１、第２電極１２、第３電極１３および第４電極２１のそれぞれは、ＩＴＯ（インジウム錫酸化物）やＩＺＯ（インジウム亜鉛酸化物）などの透明導電材料から形成されている。これらの電極となる導電膜を堆積する方法に特に制限はなく、スパッタリング法、真空蒸着法、プラズマＣＶＤ法等、公知の種々の方法を用いることができる。また、櫛歯形状を有する第１電極１１および第２電極１２を形成するために導電膜をパターニングする方法にも特に制限はなく、フォトリソグラフィ等の公知のパターニング方法を用いることができる。第１電極１１、第２電極１２、第３電極１３および第４電極２１の厚さは、例えば、１００ｎｍである。 Each of the first electrode 11, the second electrode 12, the third electrode 13, and the fourth electrode 21 is made of a transparent conductive material such as ITO (indium tin oxide) or IZO (indium zinc oxide). There is no particular limitation on the method for depositing the conductive film to be these electrodes, and various known methods such as a sputtering method, a vacuum evaporation method, and a plasma CVD method can be used. Further, there is no particular limitation on the method for patterning the conductive film in order to form the first electrode 11 and the second electrode 12 having a comb-teeth shape, and a known patterning method such as photolithography can be used. The thicknesses of the first electrode 11, the second electrode 12, the third electrode 13, and the fourth electrode 21 are, for example, 100 nm.
　光学層３０は、印加された電界に応じてその光学特性が変化する。光学層３０は、液状の媒体３１と、媒体３１中に分散され、形状異方性を有する粒子（以下では「形状異方性粒子」と呼ぶ）３２とを含む。上述した第１基板１０および第２基板２０は、表示領域を包囲するように形成されたシール部（ここでは不図示）を介して貼り合わされており、媒体３１および形状異方性粒子３２は、シール部に包囲された領域（つまり表示領域）内に封入されている。光学層３０の厚さ（セルギャップ）に特に制限はない。光学層３０の厚さは、例えば、５μｍ～３０μｍである。 The optical characteristics of the optical layer 30 change according to the applied electric field. The optical layer 30 includes a liquid medium 31 and particles 32 dispersed in the medium 31 and having shape anisotropy (hereinafter referred to as “shape anisotropic particles”). The first substrate 10 and the second substrate 20 described above are bonded together via a seal portion (not shown here) formed so as to surround the display region, and the medium 31 and the shape anisotropic particles 32 are: It is enclosed in a region (that is, a display region) surrounded by the seal portion. There is no particular limitation on the thickness (cell gap) of the optical layer 30. The thickness of the optical layer 30 is, for example, 5 μm to 30 μm.
　形状異方性粒子３２は、光反射性を有する。形状異方性粒子３２は、例えばフレーク状（薄片状）である。 The shape anisotropic particle 32 has light reflectivity. The shape anisotropic particle 32 has, for example, a flake shape (flaky shape).
　形状異方性粒子３２は、光学層３０に印加された電界（電圧）に応じて配向方向が変化する。形状異方性粒子３２は、形状異方性を有しているので、形状異方性粒子３２の配向方向が変化すると、形状異方性粒子３２の基板面（第１基板１０の基板面）への投影面積も変化し、それに伴って、光学層３０の光学特性（ここでは反射率）が変化する。表示装置１００では、そのことを利用して表示が行われる。形状異方性粒子３２の配向方向が印加電界に応じて変化する理由については、後に詳述する。 The orientation direction of the shape anisotropic particles 32 changes according to the electric field (voltage) applied to the optical layer 30. Since the shape anisotropic particles 32 have shape anisotropy, when the orientation direction of the shape anisotropic particles 32 changes, the substrate surface of the shape anisotropic particles 32 (the substrate surface of the first substrate 10). The projected area on the screen also changes, and the optical characteristics (reflectance in this case) of the optical layer 30 change accordingly. In the display device 100, display is performed using this fact. The reason why the orientation direction of the shape anisotropic particles 32 changes according to the applied electric field will be described in detail later.
　本実施形態の表示装置１００では、媒体３１は、液晶材料であり、液晶分子を含んでいる。ここでは、液晶材料は、正の誘電異方性を有するネマチック液晶材料である。つまり、媒体３１は、いわゆるポジ型のネマチック液晶材料であり、液晶分子の長軸方向の誘電率ε//は、短軸方向の誘電率ε⊥よりも大きい。媒体３１がネマチック液晶材料であるので、印加電圧がゼロである状態において、画素はメモリ性を有していない。 In the display device 100 of this embodiment, the medium 31 is a liquid crystal material and includes liquid crystal molecules. Here, the liquid crystal material is a nematic liquid crystal material having positive dielectric anisotropy. That is, the medium 31 is a so-called positive nematic liquid crystal material, and the dielectric constant ε // in the major axis direction of the liquid crystal molecules is larger than the dielectric constant ε の in the minor axis direction. Since the medium 31 is a nematic liquid crystal material, the pixel does not have a memory property when the applied voltage is zero.
　第１基板１０および第２基板２０のそれぞれは、光学層３０側に設けられた垂直配向膜１５および２５を有する。垂直配向膜１５および２５は、媒体（液晶材料）３１に含まれる液晶分子を垂直配向（第１基板１０または第２基板２０の基板面に対して略垂直に配向）させる配向規制力を有する。また、垂直配向膜１５および２５は、後に詳述するように、形状異方性粒子３２を垂直配向（第１基板１０または第２基板２０の基板面に対して略垂直に配向）させる配向規制力も有する。なお、必ずしも第１基板１０および第２基板２０の両方に垂直配向膜が設けられている必要はなく、一方のみ（例えば第１基板１０のみ）に垂直配向膜が設けられていてもよい。 Each of the first substrate 10 and the second substrate 20 has vertical alignment films 15 and 25 provided on the optical layer 30 side. The vertical alignment films 15 and 25 have an alignment regulating force for vertically aligning liquid crystal molecules contained in the medium (liquid crystal material) 31 (aligned substantially perpendicularly to the substrate surface of the first substrate 10 or the second substrate 20). Further, the vertical alignment films 15 and 25, as will be described in detail later, are alignment restrictions that cause the shape anisotropic particles 32 to be vertically aligned (aligned substantially perpendicularly to the substrate surface of the first substrate 10 or the second substrate 20). Also has power. Note that the vertical alignment film is not necessarily provided on both the first substrate 10 and the second substrate 20, and the vertical alignment film may be provided on only one (for example, only the first substrate 10).
　本発明の実施形態による表示装置１００では、第１電極（第１上層電極）１１および第２電極（第２上層電極）１２と、第３電極（下層電極）１３とによって光学層３０にフリンジ電界が生成される。本発明の実施形態による表示装置１００では、さらに、第１電極１１、第２電極１２および第３電極１３と、第４電極（対向電極）２１とによって光学層３０に縦電界が生成される。 In the display device 100 according to the embodiment of the present invention, a fringe electric field is applied to the optical layer 30 by the first electrode (first upper layer electrode) 11, the second electrode (second upper layer electrode) 12, and the third electrode (lower layer electrode) 13. Is generated. In the display device 100 according to the embodiment of the present invention, a vertical electric field is generated in the optical layer 30 by the first electrode 11, the second electrode 12, the third electrode 13, and the fourth electrode (counter electrode) 21.
　以下、図３（ａ）および（ｂ）を参照しながら、形状異方性粒子３２の配向方向が印加電界（印加電圧）に応じて変化する理由をより具体的に説明する。図３（ａ）は、光学層３０に電界が印加されていないときの表示装置１００を模式的に示す図であり、図３（ｂ）は、光学層３０にフリンジ電界が印加されているときの表示装置１００を模式的に示す図である。 Hereinafter, the reason why the orientation direction of the shape anisotropic particles 32 changes according to the applied electric field (applied voltage) will be described in more detail with reference to FIGS. 3 (a) and 3 (b). 3A is a diagram schematically showing the display device 100 when no electric field is applied to the optical layer 30, and FIG. 3B is a diagram when a fringe electric field is applied to the optical layer 30. FIG. It is a figure which shows typically the display apparatus 100 of.
　光学層３０に電界が印加されていない場合、図３（ａ）に示すように、形状異方性粒子３２は、垂直配向膜１５および２５の配向規制力によって、（その長手方向が）第１基板１０の基板面に対して略垂直になるように配向している（つまり垂直配向状態をとる）。また、垂直配向膜１５および２５の配向規制力によって液晶分子が基板面に略垂直に配向することが、形状異方性粒子３２が垂直配向状態をとることをサポートするように働く。この状態において、入射した周囲光Ｌの多くは光学層３０を透過する。つまり、光学層３０は透明状態となる。光学層３０を透過した周囲光は、光吸収層１６で吸収されるので、この状態において、黒表示を行うことができる。なお、本願明細書において、「形状異方性粒子３２が基板面に対して略垂直に配向している」とは、形状異方性粒子３２が、基板面に対して厳密に垂直に配向している状態と実質的に同程度の光学特性を示すような角度で配向している状態を指し、具体的には、形状異方性粒子３２が基板面に対して７５°以上の角度で配向した状態を指す。 When an electric field is not applied to the optical layer 30, the shape anisotropic particle 32 is first (its longitudinal direction) by the alignment regulating force of the vertical alignment films 15 and 25 as shown in FIG. The substrate 10 is oriented so as to be substantially perpendicular to the substrate surface (that is, in a vertically oriented state). In addition, the alignment of the liquid crystal molecules substantially perpendicular to the substrate surface by the alignment regulating force of the vertical alignment films 15 and 25 serves to support the shape anisotropic particles 32 taking a vertical alignment state. In this state, most of the incident ambient light L is transmitted through the optical layer 30. That is, the optical layer 30 is in a transparent state. Since ambient light transmitted through the optical layer 30 is absorbed by the light absorption layer 16, black display can be performed in this state. In the present specification, “the shape anisotropic particles 32 are oriented substantially perpendicular to the substrate surface” means that the shape anisotropic particles 32 are oriented strictly perpendicular to the substrate surface. Refers to a state of being oriented at an angle exhibiting substantially the same optical characteristics as the state of being, specifically, the shape anisotropic particles 32 are oriented at an angle of 75 ° or more with respect to the substrate surface. Refers to the state.
　図３（ｂ）に示すように、光学層３０にフリンジ電界（電気力線Ｅｆで表わされる）が印加されると、形状異方性粒子３２は、（その長手方向が）第１基板１０の基板面に略平行になるように配向する（つまり水平配向状態をとる）。また、液晶分子も、第１基板１０の基板面に略平行に配向する。この状態において、入射した周囲光Ｌの多くは光学層３０中の形状異方性粒子３２で反射される。つまり、光学層３０は反射状態となり、この状態において、白表示を行うことができる。また、白表示時よりも低い電圧を印加することにより、中間調表示を行うこともできる。 As shown in FIG. 3 (b), when a fringe electric field (represented by the lines of electric force Ef) is applied to the optical layer 30, the shape anisotropic particles 32 are (on the longitudinal direction) of the first substrate 10. Align so as to be substantially parallel to the substrate surface (that is, take a horizontal alignment state). The liquid crystal molecules are also aligned substantially parallel to the substrate surface of the first substrate 10. In this state, most of the incident ambient light L is reflected by the shape anisotropic particles 32 in the optical layer 30. That is, the optical layer 30 is in a reflective state, and white display can be performed in this state. Further, halftone display can be performed by applying a voltage lower than that during white display.
　また、表示装置１００では、第２基板２０が、第１電極１１、第２電極１２および第３電極１３に対向する第４電極２１を有しているので、光学層３０に縦電界を生成することもできる。 Further, in the display device 100, the second substrate 20 includes the fourth electrode 21 that faces the first electrode 11, the second electrode 12, and the third electrode 13, so that a vertical electric field is generated in the optical layer 30. You can also
　図４に示すように、光学層３０に縦電界（電気力線Ｅｖで表わされる）が印加されると、形状異方性粒子３２は、（その長手方向が）第１基板１０の基板面に略垂直になるように配向する（つまり垂直配向状態をとる）。また、液晶分子も、第１基板１０の基板面に略垂直に配向する。この状態において、入射した周囲光Ｌの多くは光学層３０を透過する。つまり、光学層３０は透明状態となる。光学層３０を透過した周囲光は、光吸収層１６で吸収されるので、この状態において、黒表示を行うことができる。 As shown in FIG. 4, when a longitudinal electric field (represented by electric lines of force Ev) is applied to the optical layer 30, the shape anisotropic particles 32 (on the longitudinal direction) are formed on the substrate surface of the first substrate 10. Align so as to be substantially vertical (that is, take a vertical alignment state). The liquid crystal molecules are also aligned substantially perpendicular to the substrate surface of the first substrate 10. In this state, most of the incident ambient light L is transmitted through the optical layer 30. That is, the optical layer 30 is in a transparent state. Since ambient light transmitted through the optical layer 30 is absorbed by the light absorption layer 16, black display can be performed in this state.
　なお、白表示および中間調表示を行う場合、図５に示すように、フリンジ電界に加えて横電界（電気力線Ｅｈで表わされる）が光学層３０に印加されてもよい。横電界は、第１電極１１と第２電極１２とによって生成され得る。本願明細書では、同一基板の同一レベルに設けられた２つの電極の電位差によって生成される電界を「横電界」と呼び、同一基板の異なるレベルに設けられた２つの電極の電位差によって生成される電界を「フリンジ電界」と呼ぶ。また、本願明細書では、光学層３０にフリンジ電界および／または横電界を印加して表示を行うモードを「横電界モード」と呼び、光学層３０に縦電界を印加して表示を行うモードを「縦電界モード」と呼ぶ。 When white display and halftone display are performed, a lateral electric field (represented by electric lines of force Eh) may be applied to the optical layer 30 in addition to the fringe electric field as shown in FIG. A transverse electric field can be generated by the first electrode 11 and the second electrode 12. In this specification, an electric field generated by a potential difference between two electrodes provided on the same substrate on the same level is called a “lateral electric field”, and is generated by a potential difference between two electrodes provided on different levels on the same substrate. The electric field is called a “fringe electric field”. Further, in this specification, a mode in which display is performed by applying a fringe electric field and / or a lateral electric field to the optical layer 30 is referred to as a “lateral electric field mode”, and a mode in which display is performed by applying a vertical electric field to the optical layer 30. This is called “vertical electric field mode”.
　上述したような形状異方性粒子３２の配向変化は、電界とそれによって誘起された電気双極子モーメントとの相互作用による誘電泳動力に起因している。以下、図６（ａ）および（ｂ）を参照しながら、より具体的に説明を行う。図６（ａ）および（ｂ）は、光学層３０に印加されている電界をフリンジ電界および／または横電界から縦電界に変化させた直後、およびその後十分な時間が経過した後の、光学層３０の様子（電荷の分布および電気力線）を示す図である。 The orientation change of the shape anisotropic particles 32 as described above is caused by the dielectrophoretic force due to the interaction between the electric field and the electric dipole moment induced thereby. Hereinafter, a more specific description will be given with reference to FIGS. 6 (a) and 6 (b). 6A and 6B show the optical layer immediately after the electric field applied to the optical layer 30 is changed from a fringe electric field and / or a horizontal electric field to a vertical electric field, and after a sufficient time has elapsed since then. It is a figure which shows the mode 30 (electric charge distribution and an electric force line).
　形状異方性粒子３２の誘電率と、媒体３１の誘電率とが異なっている場合、光学層３０への印加電界の方向が変化すると、図６（ａ）に示すように、電気力線に大きな歪みが生じる。そのため、形状異方性粒子３２は、図６（ｂ）に示すように、エネルギーが最小となるように回転する。 When the dielectric constant of the shape anisotropic particle 32 and the dielectric constant of the medium 31 are different, when the direction of the electric field applied to the optical layer 30 changes, as shown in FIG. Large distortion occurs. Therefore, as shown in FIG. 6B, the shape anisotropic particles 32 rotate so that the energy is minimized.
　一般に、媒体中に分散された粒子に働く誘電泳動力Ｆdepは、粒子の誘電率をεp、媒体の誘電率をεm、粒子の半径をａ、電界の強さをＥとすると、下記式（１）で表される。式（１）中のＲｅは、実部を取り出す演算子である。なお、本実施形態では、媒体３１は、液晶材料であり、誘電異方性を有している。つまり、液晶分子の長軸方向の誘電率ε//と短軸方向の誘電率ε⊥とが異なっており、εm＝ε//－ε⊥＝Δεに相当すると考えられる。 In general, the dielectrophoretic force F dep acting on particles dispersed in a medium is expressed as follows, where the dielectric constant of the particles is ε p , the dielectric constant of the medium is ε m , the radius of the particles is a, and the strength of the electric field is E. It is represented by Formula (1). Re in the expression (1) is an operator that extracts a real part. In the present embodiment, the medium 31 is a liquid crystal material and has dielectric anisotropy. That is, the dielectric constant epsilon ⊥ the long axis direction of the dielectric constant epsilon // and the minor axis direction of liquid crystal molecules is different, is considered to correspond to ε m = ε // -ε ⊥ = Δε.
Figure JPOXMLDOC01-appb-M000001
Figure JPOXMLDOC01-appb-M000001
　また、既に説明したことからもわかるように、上記の誘電泳動力以外に垂直配向膜１５および２５の配向規制力と液晶分子のサポートとにより形状異方性粒子３２に垂直配向状態を発現させることにより、形状異方性粒子３２の垂直配向動作および水平配向動作の切り替えを好適に行うことができる。 Further, as can be seen from the above description, in addition to the above-described dielectrophoretic force, the shape anisotropic particles 32 are allowed to develop a vertical alignment state by the alignment regulating force of the vertical alignment films 15 and 25 and the support of liquid crystal molecules. Thus, the vertical alignment operation and the horizontal alignment operation of the shape anisotropic particles 32 can be suitably switched.
　上述したように、本発明の実施形態による表示装置１００では、光学層３０への電圧の印加により、形状異方性粒子３２の配向方向を変化させることができ、そのことを利用して表示を行うことができる。表示装置１００は、偏光板を必要としないので、高い光利用効率を実現することができる。 As described above, in the display device 100 according to the embodiment of the present invention, the orientation direction of the shape anisotropic particles 32 can be changed by applying a voltage to the optical layer 30, which is used for display. It can be carried out. Since the display device 100 does not require a polarizing plate, high light utilization efficiency can be realized.
　各画素の反射率は、画素への印加電圧の大きさに応じて変化する。上述した構成を有する表示装置１００では、画素の電圧－反射率特性は、ヒステリシス性を有する。以下、このヒステリシス性を具体的に説明する。なお、以下の説明において例示する昇圧曲線（印加電圧を増加させていくときの電圧－反射率特性を示す）および降圧曲線（印加電圧を減少させていくときの電圧－反射率特性を示す）は、本発明の実施形態による表示装置１００を実際に試作し（つまりテストセルを作製し）、そのテストセルについて求めたものである。 反射 The reflectance of each pixel changes according to the magnitude of the voltage applied to the pixel. In the display device 100 having the above-described configuration, the voltage-reflectance characteristic of the pixel has a hysteresis characteristic. Hereinafter, this hysteresis property will be specifically described. In the following explanation, the step-up curve (showing voltage-reflectance characteristics when the applied voltage is increased) and the step-down curve (showing voltage-reflectance characteristics when the applied voltage is reduced) are shown as examples. The display device 100 according to the embodiment of the present invention was actually prototyped (that is, a test cell was manufactured), and the test cell was obtained.
　テストセルは、アクティブマトリクス駆動ではなく、図７に示すような電極構造を採用した。図７に示す電極構造では、第１電極１１、第２電極１２および第３電極１３のそれぞれの端部に端子１１ｔ、１２ｔおよび１３ｔが設けられている。第１電極１１、第２電極１２および第３電極１３に、端子１１ｔ、１２ｔおよび１３ｔを介して任意波形発生器から所望の波形の電圧を入力した。 The test cell employs an electrode structure as shown in FIG. 7 instead of active matrix driving. In the electrode structure shown in FIG. 7, terminals 11t, 12t, and 13t are provided at the respective end portions of the first electrode 11, the second electrode 12, and the third electrode 13. A voltage having a desired waveform was input from the arbitrary waveform generator to the first electrode 11, the second electrode 12, and the third electrode 13 via the terminals 11t, 12t, and 13t.
　テストセルでは、光学層３０の厚さ（セル厚）は、１５μｍである。媒体３１は、誘電異方性Δεが２０．４のポジ型ネマチック液晶材料（メルク株式会社製）である。形状異方性粒子３２の平均粒径は７μｍであり、光学層３０における形状異方性粒子３２の含有量は６重量％である。基板１０ａおよび２０ａは、それぞれガラス基板である。第１電極（第１上層電極）１１および第２電極（第２上層電極）１２のそれぞれは、櫛歯形状を有する。第３電極（下層電極）１３は、複数のスリットを有する（後述する図２３参照）。第４電極（対向電極）２１は、べた電極である。第１電極１１、第２電極１２、第３電極１３および第４電極２１のそれぞれは、ＩＺＯから形成されており、１００ｎｍの厚さを有する。第１電極１１の枝部１１ａの幅ｗ1および第２電極１２の枝部１２ａの幅ｗ2は、それぞれ３μｍであり、電極間距離ｇは１０μｍである。絶縁層１４は、ＳｉＮｘから形成されており、３５０ｎｍの厚さを有する。オーバーコート層２２は、比誘電率εｒ＝３．４のフォトレジスト（凸版印刷社製）から形成されており、３μｍの厚さを有する。垂直配向膜１５および２５は、表面エネルギーが３５ｍＪ／ｍ2のポリアミック酸系垂直配向膜（日産化学社製）である。 In the test cell, the optical layer 30 has a thickness (cell thickness) of 15 μm. The medium 31 is a positive nematic liquid crystal material (manufactured by Merck & Co., Inc.) having a dielectric anisotropy Δε of 20.4. The average particle diameter of the shape anisotropic particles 32 is 7 μm, and the content of the shape anisotropic particles 32 in the optical layer 30 is 6% by weight. The substrates 10a and 20a are glass substrates, respectively. Each of the first electrode (first upper layer electrode) 11 and the second electrode (second upper layer electrode) 12 has a comb-tooth shape. The third electrode (lower layer electrode) 13 has a plurality of slits (see FIG. 23 described later). The fourth electrode (counter electrode) 21 is a solid electrode. Each of the first electrode 11, the second electrode 12, the third electrode 13, and the fourth electrode 21 is made of IZO and has a thickness of 100 nm. The width w 1 of the branch portion 11a of the first electrode 11 and the width w 2 of the branch portion 12a of the second electrode 12 are each 3 μm, and the inter-electrode distance g is 10 μm. The insulating layer 14 is made of SiNx and has a thickness of 350 nm. The overcoat layer 22 is formed of a photoresist (manufactured by Toppan Printing Co., Ltd.) having a relative dielectric constant εr = 3.4, and has a thickness of 3 μm. The vertical alignment films 15 and 25 are polyamic acid-based vertical alignment films (manufactured by Nissan Chemical Industries) having a surface energy of 35 mJ / m 2 .
　図８は、テストセルにおける第１電極１１の電位Ｖ1、第２電極１２の電位Ｖ2、第３電極１３の電位Ｖ3および第４電極２１の電位Ｖ4を示すタイミングチャートである。図８に示すように、第１電極１１の電位Ｖ1および第２電極１２の電位Ｖ2は、４フレームを周期とする矩形波であり、１周期内で１フレーム（約１６．７ｍｓｅｃ）ごとに＋ａＶ、０Ｖ、－ａＶ、０Ｖと変化する。また、第３電極１３の電位Ｖ3および第４電極２１の電位Ｖ4は、ずっと０Ｖ（接地電位）である。 8, the potential V 1 of the first electrode 11 in the test cell, the potential V 2 of the second electrode 12 is a timing chart showing the potential V 4 in the potential V 3 and the fourth electrode 21 of the third electrode 13. As shown in FIG. 8, the potential V 2 of the potentials V 1 and second electrode 12 of the first electrode 11 is a rectangular wave having a period of four frames, each frame within one period (about 16.7 msec) Change to + aV, 0V, -aV, 0V. The potential V 3 and the potential V 4 of the fourth electrode 21 of the third electrode 13 is much 0V (ground potential).
　図９に、表示装置１００（テストセル）の昇圧曲線および降圧曲線を示す。図９は、画素電圧（第１電極１１および第２電極１２と第３電極１３との間の電圧）Ｖｏｐ（Ｖ）と、ＳＣＥ方式の反射率（Ｙ値）との関係を示すグラフである。 FIG. 9 shows a step-up curve and a step-down curve of the display device 100 (test cell). FIG. 9 is a graph showing the relationship between the pixel voltage (voltage between the first electrode 11 and the second electrode 12 and the third electrode 13) Vop (V) and the reflectance (Y value) of the SCE method. .
　図９からわかるように、画素の電圧－反射率特性は、ヒステリシス性を有しており、昇圧曲線における閾値電圧が、降圧曲線における閾値電圧よりも高い。また、印加電圧をゼロから増加させていくときの昇圧曲線における反射率の値は、電圧値に対して実質的に１対１の関係で決まる。以下、図１０も参照しながら、このようなヒステリシス性が発現するメカニズムを説明する。 As can be seen from FIG. 9, the voltage-reflectance characteristic of the pixel has hysteresis, and the threshold voltage in the boost curve is higher than the threshold voltage in the buck curve. Further, the reflectance value in the boost curve when the applied voltage is increased from zero is substantially determined in a one-to-one relationship with the voltage value. Hereinafter, the mechanism by which such hysteresis is developed will be described with reference to FIG.
　図１０は、図９中の点Ａ－１、Ａ－２、Ｂ－３、Ｂ－４、Ｃ－５、Ｃ－６、Ｃ－７およびＡ－８における形状異方性粒子３２の配向状態を模式的に示す図である。図１０からわかるように（点Ａ－１、Ａ－２、Ｂ－３、Ｂ－４、Ｃ－５に対応する配向状態を参照されたい）、印加電圧が増加していくと、光学層３０の厚さ方向（セル厚方向）の電界強度が強くなる。それに伴い、垂直配向状態にある形状異方性粒子３２が第１基板１０側に移動して水平配向していく。また、図１０からわかるように（点Ｃ－６およびＣ－７に対応する配向状態を参照されたい）、多くの形状異方性粒子３２が第１基板１０側で水平配向した状態から印加電圧を減少させていっても、電界強度が弱い対向基板２０側には形状異方性粒子３２があまり存在していないので、形状異方性粒子３２の多くは第１基板１０側で水平配向状態を維持する。このことが、ヒステリシス性が発現する原因である。また、図１０からわかるように（点Ａ－８およびＡ－１に対応する配向状態を参照されたい）、さらに印加電圧を減少させていくと、水平配向状態を維持できなくなった形状異方性粒子３２が第２基板２０側に拡散していく。 FIG. 10 shows the orientation state of the shape anisotropic particles 32 at points A-1, A-2, B-3, B-4, C-5, C-6, C-7 and A-8 in FIG. FIG. As can be seen from FIG. 10 (see the alignment states corresponding to points A-1, A-2, B-3, B-4, and C-5), as the applied voltage increases, the optical layer 30 increases. The electric field strength in the thickness direction (cell thickness direction) increases. Accordingly, the shape anisotropic particles 32 in the vertical alignment state move to the first substrate 10 side and are horizontally aligned. Further, as can be seen from FIG. 10 (see the alignment state corresponding to points C-6 and C-7), the applied voltage from the state in which many shape anisotropic particles 32 are horizontally aligned on the first substrate 10 side. However, since the shape anisotropic particles 32 do not exist so much on the counter substrate 20 side where the electric field strength is weak, most of the shape anisotropic particles 32 are in the horizontal alignment state on the first substrate 10 side. To maintain. This is the cause of the hysteresis. Further, as can be seen from FIG. 10 (see the alignment state corresponding to points A-8 and A-1), the shape anisotropy can no longer maintain the horizontal alignment state when the applied voltage is further decreased. The particles 32 diffuse toward the second substrate 20 side.
　上述の説明からもわかるように、表示装置１００の昇圧曲線および降圧曲線（図９参照）は、３つの領域Ａ、ＢおよびＣを含んでいる。領域Ａ（点Ａ－１、Ａ－２およびＡ－８を含む）では、相対的に電界強度が強い第１基板１０側の形状異方性粒子３２の配向方向が変化する。領域Ｂ（点Ｂ－３およびＢ－４を含む）では、相対的に電界強度が弱い第２基板２０側の形状異方性粒子３２が第１基板１０側に移動し、その配向方向が変化する。領域Ｃ（点Ｃ－５、Ｃ－６およびＣ－７を含む）では、第１基板１０側で形状異方性粒子３２が水平配向状態を維持する。 As can be seen from the above description, the step-up curve and the step-down curve (see FIG. 9) of the display device 100 include three regions A, B, and C. In the region A (including points A-1, A-2, and A-8), the orientation direction of the shape anisotropic particles 32 on the first substrate 10 side where the electric field strength is relatively strong changes. In the region B (including points B-3 and B-4), the shape anisotropic particles 32 on the second substrate 20 side having relatively weak electric field strength move to the first substrate 10 side, and the orientation direction thereof changes. To do. In the region C (including the points C-5, C-6, and C-7), the shape anisotropic particles 32 maintain the horizontal alignment state on the first substrate 10 side.
　上述したように、本発明の実施形態による表示装置１００では、画素の電圧－反射率特性がヒステリシス性を有しており、印加電圧をゼロから増加させていくときの昇圧曲線における反射率の値は、電圧値に対して実質的に１対１の関係で決まる。そのため、書き込み電圧（画素へのデータ書き込み時の印加電圧）を、昇圧曲線に基づいて設定することにより、中間調表示を好適に行うことができる。 As described above, in the display device 100 according to the embodiment of the present invention, the voltage-reflectance characteristic of the pixel has a hysteresis characteristic, and the reflectance value in the boost curve when the applied voltage is increased from zero. Is determined in a substantially one-to-one relationship with the voltage value. Therefore, halftone display can be suitably performed by setting the writing voltage (applied voltage at the time of writing data to the pixel) based on the boosting curve.
　また、保持電圧（画素がデータ保持状態にあるときの印加電圧）を、書き込み電圧よりも低く設定することにより、消費電力を低減することができる。さらに、保持電圧が書き込み電圧よりも低いことにより、電圧によるストレスが抑制されるので、高い信頼性が得られる。 Also, the power consumption can be reduced by setting the holding voltage (the applied voltage when the pixel is in the data holding state) to be lower than the writing voltage. Furthermore, since the holding voltage is lower than the writing voltage, stress due to the voltage is suppressed, so that high reliability can be obtained.
　ここで、ヒステリシス性を利用した表示方法をより具体的に説明する。 Here, the display method using the hysteresis characteristic will be described more specifically.
　まず、黒表示および白表示を説明する。図１１に、ヒステリシス性の繰り返し再現性を検証した結果を示す。図１１は、画素電圧Ｖｏｐを、オフ電圧（０Ｖ）から白表示に対応する書き込み電圧まで増加させ、続いて所定の保持電圧まで減少させ、その後再びオフ電圧にするという駆動を３回繰り返したときの昇圧曲線および降圧曲線を示すグラフである。 First, black display and white display will be described. FIG. 11 shows the result of verifying the repeatability of hysteresis. FIG. 11 shows a case where the driving of increasing the pixel voltage Vop from the off voltage (0 V) to the writing voltage corresponding to the white display, subsequently decreasing the pixel voltage Vop to a predetermined holding voltage, and then setting the off voltage again is repeated three times. It is a graph which shows the pressure | voltage rise curve and pressure | voltage fall curve of this.
　図１１から、１回目、２回目および３回目の昇圧曲線および降圧曲線が重なっており、ヒステリシス性が高い精度で再現されていることがわかる。従って、黒表示と白表示との切り替えを繰り返して好適に行うことができる。 From FIG. 11, it can be seen that the first time, the second time and the third time pressure increase curve and the pressure decrease curve are overlapped, and the hysteresis property is reproduced with high accuracy. Accordingly, it is possible to suitably perform switching between black display and white display repeatedly.
　保持電圧は、図１１に示す例のように、書き込み電圧よりも２０％以上低いことが好ましい。消費電力は電圧の二乗に比例するので、保持電圧を書き込み電圧よりも２０％以上低くすることにより、４０％以上の消費電力を低減することができ、消費電力の大幅な低減（例えば半減）を実現することができる。 The holding voltage is preferably 20% or more lower than the writing voltage as in the example shown in FIG. Since the power consumption is proportional to the square of the voltage, by reducing the holding voltage by 20% or more than the write voltage, the power consumption can be reduced by 40% or more, and the power consumption can be greatly reduced (for example, halved). Can be realized.
　また、図１１に示す例では、印加電圧を書き込み電圧から減少させていくときの降圧曲線において、書き込み電圧から書き込み電圧よりも低い所定の電圧までの範囲ｒで反射率が実質的に一定である。ここで、「反射率が実質的に一定である」とは、範囲ｒ内において反射率Ｒが書き込み電圧が印加されているときの反射率Ｒｗの０．８倍以上１．２倍以下である（つまり０．８Ｒｗ≦Ｒ≦１．２Ｒｗの関係が満足される）ことを意味している。降圧曲線がこのような範囲ｒを有することにより、低消費電力状態（書き込み電圧よりも低い保持電圧が画素に印加されている状態）においても反射率を十分に維持することができる。また、範囲ｒ内における電圧に対する反射率のばらつきを低減することができる。 In the example shown in FIG. 11, in the step-down curve when the applied voltage is decreased from the write voltage, the reflectance is substantially constant in a range r from the write voltage to a predetermined voltage lower than the write voltage. . Here, “the reflectance is substantially constant” means that the reflectance R in the range r is not less than 0.8 times and not more than 1.2 times the reflectance Rw when the write voltage is applied. (That is, the relationship 0.8Rw ≦ R ≦ 1.2Rw is satisfied). When the step-down curve has such a range r, the reflectance can be sufficiently maintained even in a low power consumption state (a state where a holding voltage lower than the writing voltage is applied to the pixel). In addition, the variation in reflectance with respect to the voltage within the range r can be reduced.
　保持電圧が印加されているときの画素の反射率Ｒｈは、書き込み電圧が印加されているときの画素の反射率Ｒｗの０．９倍以上１．１倍以下である（つまり０．９Ｒｗ≦Ｒｈ≦１．１Ｒｗの関係が満足される）ことが好ましい。前者の反射率Ｒｈが、後者の反射率Ｒｗの０．９倍以上１．１倍以下であると、印加電圧が書き込み電圧から保持電圧に変化する際の反射率の変化を観察者が認識しにくい。 The reflectance Rh of the pixel when the holding voltage is applied is 0.9 to 1.1 times the reflectance Rw of the pixel when the writing voltage is applied (that is, 0.9Rw ≦ Rh). It is preferable that the relationship of ≦ 1.1 Rw is satisfied. If the former reflectivity Rh is 0.9 to 1.1 times greater than the latter reflectivity Rw, the observer recognizes the change in reflectivity when the applied voltage changes from the write voltage to the holding voltage. Hateful.
　図１２に、データ書き込み時とデータ保持状態とにおける駆動の切り替えの例を示す。図１２（ａ）は、データ書き込み時における第１電極１１の電位Ｖ1、第２電極１２の電位Ｖ2、第３電極１３の電位Ｖ3、第４電極２１の電位Ｖ4および画素電圧Ｖｏｐを示すタイミングチャートであり、図１２（ｂ）は、データ保持状態における第１電極１１の電位Ｖ1、第２電極１２の電位Ｖ2、第３電極１３の電位Ｖ3、第４電極２１の電位Ｖ4および画素電圧Ｖｏｐを示すタイミングチャートである。 FIG. 12 shows an example of driving switching between data writing and data holding state. 12 (a) is, the potential V 1 of the first electrode 11 at the time of data writing, the potential V 2 of the second electrode 12, the potential V 3 of the third electrode 13, the potential V 4 and the pixel voltage of the fourth electrode 21 Vop is a timing chart showing, FIG. 12 (b), the potential V 1 of the first electrode 11 in the data holding state, the potential V 2 of the second electrode 12, the potential V 3 of the third electrode 13, the fourth electrode 21 3 is a timing chart showing a potential V4 and a pixel voltage Vop.
　図１２（ａ）に示す例では、第１電極１１の電位Ｖ1および第２電極１２の電位Ｖ2は、４フレームを周期としており、１周期内で１フレーム（約１６．７ｍｓｅｃ）ごとに＋ａＶ、０Ｖ、－ａＶ、０Ｖと変化する。また、第３電極１３の電位Ｖ3および第４電極２１の電位Ｖ4は、ずっと０Ｖ（接地電位）である。そのため、データ書き込み時の画素電圧Ｖｏｐは、４フレームを周期として１周期内で１フレーム（約１６．７ｍｓｅｃ）ごとに＋ａＶ、０Ｖ、－ａＶ、０Ｖと変化する。 In the example shown in FIG. 12 (a), the potential V 2 of the potentials V 1 and second electrode 12 of the first electrode 11 is for the period of four frames, for each frame within one period (about 16.7 msec) It changes as + aV, 0V, -aV, 0V. The potential V 3 and the potential V 4 of the fourth electrode 21 of the third electrode 13 is much 0V (ground potential). Therefore, the pixel voltage Vop at the time of data writing changes to + aV, 0V, −aV, and 0V every frame (about 16.7 msec) within one period with a period of four frames.
　また、図１２（ｂ）に示す例では、第１電極１１の電位Ｖ1および第２電極１２の電位Ｖ2は、４フレームを周期としており、１周期内で１フレーム（約１６．７ｍｓｅｃ）ごとに＋ｂＶ、０Ｖ、－ｂＶ、０Ｖと変化する。また、第３電極１３の電位Ｖ3および第４電極２１の電位Ｖ4は、ずっと０Ｖ（接地電位）である。そのため、データ保持状態における画素電圧Ｖｏｐは、４フレームを周期として１周期内で１フレーム（約１６．７ｍｓｅｃ）ごとに＋ｂＶ、０Ｖ、－ｂＶ、０Ｖと変化する。ここで、ａ＞ｂである。つまり、データ保持状態における画素電圧Ｖｏｐは、データ書き込み時の画素電圧Ｖｏｐよりも低い。図１２（ａ）および（ｂ）に例示したような駆動の切り替えを行うことにより、低消費電力化を図ることができる。 Further, in the example shown in FIG. 12 (b), the potential V 2 of the potentials V 1 and second electrode 12 of the first electrode 11 is for the period of four frames, one frame (about 16.7 msec) in one cycle It changes to + bV, 0V, -bV, 0V every time. The potential V 3 and the potential V 4 of the fourth electrode 21 of the third electrode 13 is much 0V (ground potential). Therefore, the pixel voltage Vop in the data holding state changes to + bV, 0V, −bV, and 0V every one frame (about 16.7 msec) within one period with a period of four frames. Here, a> b. That is, the pixel voltage Vop in the data holding state is lower than the pixel voltage Vop at the time of data writing. By switching the drive as exemplified in FIGS. 12A and 12B, power consumption can be reduced.
　続いて、中間調表示を説明する。まず、図１３を参照しながら、黒表示と中間調表示との切り替えについて説明を行う。図１３は、画素電圧Ｖｏｐを、オフ電圧（０Ｖ）から書き込み電圧まで増加させ、続いて所定の保持電圧まで減少させ、その後再びオフ電圧にするという駆動を５回繰り返したときの昇圧曲線および降圧曲線を示すグラフである。１回目および５回目の書き込み電圧が白表示に対応する電圧であるのに対し、２回目、３回目および４回目の書き込み電圧は中間調表示に対応する電圧である。 Next, the halftone display will be explained. First, switching between black display and halftone display will be described with reference to FIG. FIG. 13 shows a step-up curve and a step-down when the drive of increasing the pixel voltage Vop from the off voltage (0 V) to the write voltage, subsequently decreasing the pixel voltage Vop to a predetermined holding voltage, and then turning it off again is repeated five times. It is a graph which shows a curve. The first and fifth writing voltages are voltages corresponding to white display, whereas the second, third and fourth writing voltages are voltages corresponding to halftone display.
　図１３から、２回目以降の駆動における昇圧曲線が、１回目の駆動における昇圧曲線に一致していることがわかる。そのため、黒表示から中間調表示への切り替えは、昇圧曲線に従い、所望の中間調表示に対応する反射率となる画素電圧Ｖｏｐでデータ書き込みを行い、その後、画素電圧Ｖｏｐを所定の保持電圧まで減少させればよい。また、図１３から、中間調表示に対応する電圧でデータ書き込みを行った後の降圧曲線においても、反射率が実質的に一定な範囲ｒ１、ｒ２、ｒ３およびｒ４が存在していることがわかる。 FIG. 13 shows that the boosting curve in the second and subsequent driving matches the boosting curve in the first driving. Therefore, when switching from black display to halftone display, data is written with the pixel voltage Vop having a reflectance corresponding to the desired halftone display according to the boost curve, and then the pixel voltage Vop is reduced to a predetermined holding voltage. You can do it. FIG. 13 also shows that there are ranges r1, r2, r3, and r4 in which the reflectivity is substantially constant in the step-down curve after the data is written with the voltage corresponding to the halftone display. .
　次に、図１４および図１５を参照しながら、ある中間調（中間調Ｄ）の表示からより高階調側の中間調（中間調Ｅ）の表示または白表示への切り替えについて説明を行う。図１４は、中間調Ｄでのデータ書き込みおよびデータ保持状態に対応する点Ｐ１およびＰ２を含む昇圧曲線および降圧曲線を示すグラフであり、図１５（ａ）および（ｂ）は、それぞれ点Ｐ１およびＰ２に対応する形状異方性粒子３２の配向状態を示す図である。 Next, with reference to FIG. 14 and FIG. 15, switching from a halftone (halftone D) display to a higher halftone (halftone E) display or white display will be described. FIG. 14 is a graph showing a step-up curve and a step-down curve including points P1 and P2 corresponding to the data writing and data holding states in the halftone D, and FIGS. It is a figure which shows the orientation state of the shape anisotropic particle 32 corresponding to P2.
　図１４からわかるように、中間調Ｄに対応する書き込み電圧が画素に印加された状態（点Ｐ１：図１５（ａ）参照）と、中間調Ｄに対応する保持電圧が画素に印加された状態（点Ｐ２：図１５（ｂ）参照）とは、可逆である。つまり、第１基板１０側で形状異方性粒子３２が水平配向状態を維持する電圧範囲（図９中の領域Ｃに対応）では、配向状態の変化が可逆的である。そのため、中間調Ｄの表示から、より高階調側の中間調Ｅの表示（または白表示）への切り替えは、中間調Ｄに対応するデータ保持状態からそのまま中間調Ｅに対応する書き込み電圧の印加を行い（図１４中の点Ｐ３）、その後、中間調Ｅに対応する保持電圧まで画素電圧Ｖｏｐを減少させればよい。 As can be seen from FIG. 14, the write voltage corresponding to the halftone D is applied to the pixel (point P1: see FIG. 15A), and the holding voltage corresponding to the halftone D is applied to the pixel. (Point P2: see FIG. 15B) is reversible. That is, in the voltage range (corresponding to the region C in FIG. 9) in which the shape anisotropic particles 32 maintain the horizontal alignment state on the first substrate 10 side, the change in the alignment state is reversible. Therefore, switching from the display of halftone D to the display of halftone E on the higher gradation side (or white display) applies the write voltage corresponding to halftone E as it is from the data holding state corresponding to halftone D. (Point P3 in FIG. 14), and then the pixel voltage Vop is reduced to the holding voltage corresponding to the halftone E.
　続いて、図１６、図１７および図１８を参照しながら、白またはある中間調Ｄの表示からより低階調側の中間調（中間調Ｆ）の表示への切り替えについて説明を行う。図１６は、昇圧曲線および降圧曲線を示すグラフであり、図１７（ａ）、（ｂ）および図１８（ａ）、（ｂ）は、それぞれ図１６中の点Ｐ４、Ｐ５、Ｐ６およびＰ７に対応する形状異方性粒子３２の配向状態を示す図である。 Subsequently, switching from white or a certain halftone D display to a lower halftone (halftone F) display will be described with reference to FIGS. FIG. 16 is a graph showing a step-up curve and a step-down curve. FIGS. 17A, 17B, 18A, and 18B are respectively shown at points P4, P5, P6, and P7 in FIG. It is a figure which shows the orientation state of the corresponding shape anisotropic particle.
　白または中間調Ｄのデータ保持状態から画素電圧Ｖｏｐを点Ｐ４まで減少させる場合、降圧曲線は、その前の書き込み電圧の大きさに依存して異なる。そのため、画素電圧Ｖｏｐと反射率とが１対１の関係では決まらない。また、点Ｐ４から画素電圧Ｖｏｐを増加させてデータ書き込みを行う場合、水平配向状態を維持している形状異方性粒子３２の量に依存して昇圧曲線が異なるので、この場合にも画素電圧Ｖｏｐと反射率とが１対１の関係では決まらない。そのため、白またはある中間調Ｄの表示からより低階調側の中間調Ｆの表示への切り替えに際しては、いったん画素電圧Ｖｏｐをゼロにする（以下では「黒挿引」と呼ぶこともある）ことにより、起点をゼロとする昇圧曲線（点Ｐ６およびＰ７を含む）に従って、画素電圧Ｖｏｐと反射率とを１対１の関係で決めることができる。図１６から、いったん黒挿引を行った後に中間調Ｆに対応する書き込み電圧でデータ書き込みを行う場合（点Ｐ７）と、点Ｐ４から直接中間調Ｆに対応する書き込み電圧でデータ書き込みを行う場合（点Ｐ５）とで、反射率が異なっていることがわかる。 When the pixel voltage Vop is decreased from the white or halftone D data holding state to the point P4, the step-down curve differs depending on the magnitude of the previous writing voltage. For this reason, the pixel voltage Vop and the reflectance are not determined in a one-to-one relationship. In addition, when data is written by increasing the pixel voltage Vop from the point P4, the boosting curve differs depending on the amount of the shape anisotropic particles 32 maintaining the horizontal alignment state. Vop and reflectance are not determined in a one-to-one relationship. Therefore, when switching from white or a certain halftone D display to a lower halftone F display, the pixel voltage Vop is once set to zero (hereinafter also referred to as “black insertion”). Accordingly, the pixel voltage Vop and the reflectance can be determined in a one-to-one relationship according to a boosting curve (including points P6 and P7) with the starting point being zero. From FIG. 16, after black insertion is performed, data is written with the write voltage corresponding to the halftone F (point P7), and when data is written directly from the point P4 with the write voltage corresponding to the halftone F. It can be seen that the reflectance is different between (Point P5).
　このように、現フレームの印加電圧に対応する反射率が次フレームの書き込み電圧に対応する反射率よりも高い場合、画素への印加電圧をいったんゼロにし、その後、画素に本来の書き込み電圧を印加すればよい。 Thus, when the reflectance corresponding to the applied voltage of the current frame is higher than the reflectance corresponding to the writing voltage of the next frame, the applied voltage to the pixel is once reduced to zero, and then the original writing voltage is applied to the pixel. do it.
　図１９に、データ書き込み時とデータ保持状態とにおける駆動の切り替えの他の例を示す。図１９（ａ）は、データ書き込み時における第１電極１１の電位Ｖ1、第２電極１２の電位Ｖ2、第３電極１３の電位Ｖ3、第４電極２１の電位Ｖ4および画素電圧Ｖｏｐを示すタイミングチャートであり、図１９（ｂ）は、データ保持状態における第１電極１１の電位Ｖ1、第２電極１２の電位Ｖ2、第３電極１３の電位Ｖ3、第４電極２１の電位Ｖ4および画素電圧Ｖｏｐを示すタイミングチャートである。 FIG. 19 shows another example of driving switching between data writing and data holding state. FIG. 19 (a), the potential V 1 of the first electrode 11 at the time of data writing, the potential V 2 of the second electrode 12, the potential V 3 of the third electrode 13, the potential V 4 and the pixel voltage of the fourth electrode 21 Vop is a timing chart showing, FIG. 19 (b), the potential V 1 of the first electrode 11 in the data holding state, the potential V 2 of the second electrode 12, the potential V 3 of the third electrode 13, the fourth electrode 21 3 is a timing chart showing a potential V4 and a pixel voltage Vop.
　図１９（ａ）に示す例では、第１電極１１の電位Ｖ1および第２電極１２の電位Ｖ2は、４フレームを周期としており、１周期内で１フレーム（約１６．７ｍｓｅｃ）ごとに＋１０Ｖ、０Ｖ、－１０Ｖ、０Ｖと変化する。また、第３電極１３の電位Ｖ3および第４電極２１の電位Ｖ4は、ずっと０Ｖ（接地電位）である。そのため、データ書き込み時の画素電圧Ｖｏｐは、４フレームを周期として１周期内で１フレーム（約１６．７ｍｓｅｃ）ごとに＋１０Ｖ、０Ｖ、－１０Ｖ、０Ｖと変化する。 In the example shown in FIG. 19 (a), the potential V 2 of the potentials V 1 and second electrode 12 of the first electrode 11, the four frames has a period, for each frame within one period (about 16.7 msec) It changes as + 10V, 0V, -10V, 0V. The potential V 3 and the potential V 4 of the fourth electrode 21 of the third electrode 13 is much 0V (ground potential). For this reason, the pixel voltage Vop at the time of data writing changes to +10 V, 0 V, −10 V, and 0 V every frame (about 16.7 msec) within one cycle with a cycle of four frames.
　また、図１９（ｂ）に示す例では、第１電極１１の電位Ｖ1および第２電極１２の電位Ｖ2は、２フレームを周期としており、１周期内で１フレーム（約１６．７ｍｓｅｃ）ごとに＋６Ｖ、－６Ｖと変化する。また、第３電極１３の電位Ｖ3および第４電極２１の電位Ｖ4は、ずっと０Ｖ（接地電位）である。そのため、データ保持状態における画素電圧Ｖｏｐは、２フレームを周期として１周期内で１フレーム（約１６．７ｍｓｅｃ）ごとに＋６Ｖ、－６Ｖと変化する。 Further, in the example shown in FIG. 19 (b), the potential V 2 of the potentials V 1 and second electrode 12 of the first electrode 11 is for the period of two frames, one frame within one period (about 16.7 msec) It changes to + 6V and -6V every time. The potential V 3 and the potential V 4 of the fourth electrode 21 of the third electrode 13 is much 0V (ground potential). Therefore, the pixel voltage Vop in the data holding state changes to +6 V and −6 V every frame (about 16.7 msec) within one cycle with a cycle of two frames.
　このように、図１９（ａ）および（ｂ）に示す例では、画素に書き込み電圧が印加されるときと、画素に保持電圧が印加されるときとで、互いに異なる駆動シーケンスが実行される。また、図１９（ｂ）に示す例では、保持電圧の極性が１フレームごとに反転する。 As described above, in the example shown in FIGS. 19A and 19B, different driving sequences are executed when the writing voltage is applied to the pixel and when the holding voltage is applied to the pixel. In the example shown in FIG. 19B, the polarity of the holding voltage is inverted every frame.
　データ書き込み時と、データ保持状態とでは、好ましい駆動シーケンスが異なり得る。そのため、データ書き込み時とデータ保持状態とで互いに異なる駆動シーケンスを実行する構成を採用することにより、データ書き込み時およびデータ保持状態のそれぞれについて好ましい駆動シーケンスを用いることができる。 Favorable drive sequence may differ between data writing and data holding state. Therefore, by adopting a configuration in which different driving sequences are executed in the data writing state and in the data holding state, a preferable driving sequence can be used for each of the data writing state and the data holding state.
　図１９（ａ）に示す駆動シーケンスは、データ書き込み時に好ましい駆動シーケンスである。図１９（ａ）に示す例のように、光学層３０に印加される電圧を、相対的に絶対値が大きい第１の期間と、相対的に絶対値が小さい第２の期間とを交互に有する振動電圧とすると、媒体３１を搖動することができ、そのことによって所望の配向変化をする形状異方性粒子３２の割合を高くすることができる。そのため、より高い反射率（または透過率）を実現することができる。なお、第２の期間における振動電圧の絶対値が、第１の期間における振動電圧の絶対値に対して小さいほど、媒体３１をより強く搖動することができ、第２の期間における振動電圧が略０Ｖであると、媒体３１をもっとも強く搖動することができる。 The drive sequence shown in FIG. 19A is a preferable drive sequence at the time of data writing. As in the example shown in FIG. 19A, the voltage applied to the optical layer 30 is alternately switched between a first period having a relatively large absolute value and a second period having a relatively small absolute value. When the oscillating voltage is included, the medium 31 can be swung, thereby increasing the proportion of the shape anisotropic particles 32 that change the desired orientation. Therefore, higher reflectance (or transmittance) can be realized. The smaller the absolute value of the oscillating voltage in the second period is relative to the absolute value of the oscillating voltage in the first period, the stronger the medium 31 can be swung, and the oscillating voltage in the second period is substantially reduced. When the voltage is 0 V, the medium 31 can be rocked most strongly.
　また、図１９（ｂ）に示す駆動シーケンスは、データ保持状態に好ましい駆動シーケンスである。図１９（ｂ）に示す例のように、保持電圧の極性が１フレームごとに反転すると、形状異方性粒子３２の第１基板１０への貼り付き（焼き付きによる信頼性悪化）を抑制し、信頼性を向上させることができる。 Further, the driving sequence shown in FIG. 19B is a driving sequence preferable for the data holding state. When the polarity of the holding voltage is reversed every frame as in the example shown in FIG. 19B, the sticking of the shape anisotropic particles 32 to the first substrate 10 (deterioration of reliability due to seizure) is suppressed, Reliability can be improved.
　図２０に、データ書き込み時とデータ保持状態とにおける駆動の切り替えのさらに他の例を示す。図２０（ａ）は、データ書き込み時における第１電極１１の電位Ｖ1、第２電極１２の電位Ｖ2、第３電極１３の電位Ｖ3、第４電極２１の電位Ｖ4および画素電圧Ｖｏｐを示すタイミングチャートであり、図２０（ｂ）は、データ保持状態における第１電極１１の電位Ｖ1、第２電極１２の電位Ｖ2、第３電極１３の電位Ｖ3、第４電極２１の電位Ｖ4および画素電圧Ｖｏｐを示すタイミングチャートである。 FIG. 20 shows still another example of switching of driving between data writing and data holding state. 20 (a) is the potential V 1 of the first electrode 11 at the time of data writing, the potential V 2 of the second electrode 12, the potential V 3 of the third electrode 13, the potential V 4 and the pixel voltage of the fourth electrode 21 Vop is a timing chart showing, FIG. 20 (b), the potential V 1 of the first electrode 11 in the data holding state, the potential V 2 of the second electrode 12, the potential V 3 of the third electrode 13, the fourth electrode 21 3 is a timing chart showing a potential V4 and a pixel voltage Vop.
　図２０（ａ）に示す例では、第１電極１１の電位Ｖ1および第２電極１２の電位Ｖ2は、４フレームを周期としており、１周期内で１フレーム（約１６．７ｍｓｅｃ）ごとに＋１０Ｖ、０Ｖ、－１０Ｖ、０Ｖと変化する。また、第３電極１３の電位Ｖ3および第４電極２１の電位Ｖ4は、ずっと０Ｖ（接地電位）である。そのため、データ書き込み時の画素電圧Ｖｏｐは、４フレームを周期として１周期内で１フレーム（約１６．７ｍｓｅｃ）ごとに＋１０Ｖ、０Ｖ、－１０Ｖ、０Ｖと変化する。 Figure 20 In the example shown in (a), the potential V 2 of the potentials V 1 and second electrode 12 of the first electrode 11 is for the period of four frames, for each frame within one period (about 16.7 msec) It changes as + 10V, 0V, -10V, 0V. The potential V 3 and the potential V 4 of the fourth electrode 21 of the third electrode 13 is much 0V (ground potential). For this reason, the pixel voltage Vop at the time of data writing changes to +10 V, 0 V, −10 V, and 0 V every frame (about 16.7 msec) within one cycle with a cycle of four frames.
　また、図２０（ｂ）に示す例では、第１電極１１の電位Ｖ1および第２電極１２の電位Ｖ2は、１２０フレームを周期としており、１周期内で６０フレーム（１ｓｅｃ）ごとに＋６Ｖ、－６Ｖと変化する。また、第３電極１３の電位Ｖ3および第４電極２１の電位Ｖ4は、ずっと０Ｖ（接地電位）である。そのため、データ保持状態における画素電圧Ｖｏｐは、１２０フレームを周期として１周期内で６０フレーム（１ｓｅｃ）ごとに＋６Ｖ、－６Ｖと変化する。 Further, in the example shown in FIG. 20 (b), the potential V 2 of the potentials V 1 and second electrode 12 of the first electrode 11 is for the period of 120 frames, the 60 frame by frame (1 sec) within one period + 6V , And changes to -6V. The potential V 3 and the potential V 4 of the fourth electrode 21 of the third electrode 13 is much 0V (ground potential). Therefore, the pixel voltage Vop in the data holding state changes to +6 V and −6 V every 60 frames (1 sec) within one cycle with a cycle of 120 frames.
　このように、図２０（ａ）および（ｂ）に示す例では、画素に保持電圧が印加されるときの駆動周波数が、画素に書き込み電圧が印加されるときの駆動周波数よりも低い。消費電力は、駆動周波数に比例するので、図２０（ａ）および（ｂ）に示す例のように、データ保持状態における駆動周波数を、データ書き込み時における駆動周波数よりも低くすることにより、いっそうの低消費電力化を実現することができる。 As described above, in the example shown in FIGS. 20A and 20B, the drive frequency when the holding voltage is applied to the pixel is lower than the drive frequency when the write voltage is applied to the pixel. Since the power consumption is proportional to the drive frequency, the drive frequency in the data holding state is made lower than the drive frequency at the time of data writing as in the example shown in FIGS. Low power consumption can be realized.
　図２１に、データ保持状態と黒挿引時における駆動の切り替えの例を示す。図２１（ａ）は、データ保持状態における第１電極１１の電位Ｖ1、第２電極１２の電位Ｖ2、第３電極１３の電位Ｖ3、第４電極２１の電位Ｖ4および画素電圧Ｖｏｐを示すタイミングチャートであり、図２１（ｂ）は、黒挿引時における第１電極１１の電位Ｖ1、第２電極１２の電位Ｖ2、第３電極１３の電位Ｖ3、第４電極２１の電位Ｖ4および画素電圧Ｖｏｐを示すタイミングチャートである。 FIG. 21 shows an example of switching of the data holding state and driving during black insertion. FIG. 21 (a), the potential V 1 of the first electrode 11 in the data holding state, the potential V 2 of the second electrode 12, the potential V 3 of the third electrode 13, the potential V 4 and the pixel voltage of the fourth electrode 21 Vop is a timing chart showing, FIG. 21 (b), the potential V 1 of the first electrode 11 at the time of black sweep, the potential V 2 of the second electrode 12, the potential V 3 of the third electrode 13, fourth electrode 21 6 is a timing chart showing a potential V 4 and a pixel voltage Vop.
　図２１（ａ）に示す例では、第１電極１１の電位Ｖ1および第２電極１２の電位Ｖ2は、１２０フレームを周期としており、１周期内で６０フレーム（１ｓｅｃ）ごとに＋６Ｖ、－６Ｖと変化する。また、第３電極１３の電位Ｖ3および第４電極２１の電位Ｖ4は、ずっと０Ｖ（接地電位）である。そのため、データ保持状態における画素電圧Ｖｏｐは、１２０フレームを周期として１周期内で６０フレーム（１ｓｅｃ）ごとに＋６Ｖ、－６Ｖと変化する。 In the example shown in FIG. 21 (a), the potential V 2 of the potentials V 1 and second electrode 12 of the first electrode 11 is for the period of 120 frames, the 60 frame by frame (1 sec) within one period + 6V, - It changes with 6V. The potential V 3 and the potential V 4 of the fourth electrode 21 of the third electrode 13 is much 0V (ground potential). Therefore, the pixel voltage Vop in the data holding state changes to +6 V and −6 V every 60 frames (1 sec) within one cycle with a cycle of 120 frames.
　また、図２１（ｂ）に示す例では、第１電極１１の電位Ｖ1、第２電極１２の電位Ｖ2および第３電極１３の電位Ｖ3は、２フレームを周期としており、１周期内で１フレーム（約１６．７ｍｓｅｃ）ごとに＋１０Ｖ、－１０Ｖと変化する。また、および第４電極２１の電位Ｖ4は、ずっと０Ｖ（接地電位）である。そのため、黒挿引時の画素電圧（ここでは第１電極１１、第２電極１２および第３電極１３と、第４電極２１との間の電圧である）Ｖｏｐは、２フレームを周期として１周期内で１フレーム（約１６．７ｍｓｅｃ）ごとに＋１０Ｖ、－１０Ｖと変化する。また、黒挿引時に図２１（ｂ）に示す例のような駆動が行われると、光学層３０には、縦電界が印加されることになる（図４参照）。 Further, in the example shown in FIG. 21 (b), the potential V 1 of the first electrode 11, the potential V 3 of the potential V 2 and the third electrode 13 of the second electrode 12, the second frame has a period, 1 period Therefore, it changes to + 10V and -10V every frame (about 16.7msec). The potential V 4 of the fourth electrode 21 is always 0 V (ground potential). Therefore, the pixel voltage at the time of black insertion (here, the voltage between the first electrode 11, the second electrode 12, the third electrode 13, and the fourth electrode 21) Vop is one period with a period of two frames. Within each frame, the voltage changes to +10 V and −10 V every frame (about 16.7 msec). Further, when driving as in the example shown in FIG. 21B is performed during black insertion, a vertical electric field is applied to the optical layer 30 (see FIG. 4).
　図２１（ｂ）に示す例のように、黒挿引時に光学層３０に縦電界を印加する（つまり、現フレームの印加電圧に対応する反射率が次フレームの書き込み電圧に対応する反射率よりも高い場合に、光学層３０にいったん縦電界を印加し、その後、画素に本来の書き込み電圧を印加する）と、画素への印加電圧をゼロにして形状異方性粒子３２を垂直配向状態に戻す場合よりも応答速度を向上させることができる。 As in the example shown in FIG. 21B, a vertical electric field is applied to the optical layer 30 during black insertion (that is, the reflectance corresponding to the applied voltage of the current frame is higher than the reflectance corresponding to the writing voltage of the next frame). In the case of a higher value, a vertical electric field is once applied to the optical layer 30 and then an original writing voltage is applied to the pixel), and the applied voltage to the pixel is set to zero to bring the shape anisotropic particles 32 into a vertically aligned state. The response speed can be improved as compared with the case of returning.
　このように、本発明の実施形態による表示装置１００では、画素の光学特性のヒステリシス性を利用する。光学特性の上述したようなヒステリシス性は、例示しているような、光学層３０が、媒体３１および形状異方性粒子３２を含む表示装置（光学装置）１００において発現する。 Thus, in the display device 100 according to the embodiment of the present invention, the hysteresis characteristic of the optical characteristics of the pixels is used. The above-described hysteresis property of the optical characteristics is manifested in the display device (optical device) 100 in which the optical layer 30 includes the medium 31 and the shape anisotropic particles 32 as illustrated.
　光学層３０の媒体３１は、液晶材料であることが好ましい。媒体３１が液晶材料であると、液晶分子のダイレクタの変化も利用することにより、形状異方性粒子３２の配向方向を効率的に変化させることができる。 The medium 31 of the optical layer 30 is preferably a liquid crystal material. When the medium 31 is a liquid crystal material, the orientation direction of the shape anisotropic particles 32 can be efficiently changed by utilizing the change of the director of the liquid crystal molecules.
　また、液晶材料は、一般に、比抵抗が高いので、媒体３１が液晶材料であると、画素への書き込み後のＴＦＴがオフである状態において、媒体３１を介したオフリークの発生が防止される。そのため、高い電圧保持率が得られ、アクティブマトリクス駆動を好適に行うことができる。また、リーク電流が少ないので、消費電力をいっそう低減することができる。表示装置１００の消費電力Ｐは、パネル容量をＣ、光学層３０への印加電圧をＶ、駆動周波数をｆ、リーク電流をＩとすると、下記式（２）で表される。
　Ｐ＝Ｃ・Ｖ・ｆ＋Ｉ・Ｖ　　　　　・・・（２） In addition, since the liquid crystal material generally has a high specific resistance, when the medium 31 is a liquid crystal material, off-leakage through the medium 31 is prevented in a state where the TFT after writing to the pixel is off. Therefore, a high voltage holding ratio can be obtained, and active matrix driving can be suitably performed. In addition, since the leakage current is small, power consumption can be further reduced. The power consumption P of the display device 100 is expressed by the following formula (2), where C is the panel capacitance, V is the voltage applied to the optical layer 30, f is the drive frequency, and I is the leakage current.
P = C · V · f + I · V (2)
　式（２）の右辺における第１項は、画素容量項と呼ぶべきものであり、第２項は、リーク電流項と呼ぶべきものである。つまり、消費電力Ｐは、画素容量成分と、リーク電流成分とに分けて考えることができる。媒体３１の比抵抗が高いと、リーク電流Ｉが減少するので、式（２）からも明らかなように、消費電力Ｐを低減することができる。 The first term on the right side of Equation (2) should be called the pixel capacitance term, and the second term should be called the leakage current term. That is, the power consumption P can be considered separately for the pixel capacitance component and the leakage current component. When the specific resistance of the medium 31 is high, the leakage current I decreases, so that the power consumption P can be reduced as is apparent from the equation (2).
　また、液晶材料がポジ型であると、光学層３０に電界が印加されたときの形状異方性粒子３２の挙動と液晶分子の挙動とが一致する。例えば、光学層３０に印加されている電界をフリンジ電界および／または横電界から縦電界に切り替えると、形状異方性分子３２は水平配向状態から垂直配向状態に変化しようとし、液晶分子も水平配向状態から垂直配向状態に変化しようとする。そのため、きちんと垂直配向する形状異方性粒子３２の数（存在確率）を増やすことができるので、いっそう高いコントラスト比を実現することができる。 Further, if the liquid crystal material is a positive type, the behavior of the shape anisotropic particles 32 and the behavior of the liquid crystal molecules when an electric field is applied to the optical layer 30 match. For example, when the electric field applied to the optical layer 30 is switched from a fringe electric field and / or a horizontal electric field to a vertical electric field, the shape anisotropic molecules 32 try to change from the horizontal alignment state to the vertical alignment state, and the liquid crystal molecules are also aligned horizontally. Attempts to change from state to vertical alignment. Therefore, since the number (existence probability) of the shape anisotropic particles 32 that are properly vertically aligned can be increased, a higher contrast ratio can be realized.
　ポジ型液晶材料としては、液晶表示装置用の液晶材料を広く好適に用いることができる。例えば、側鎖にフッ素が導入されたフッ素系の液晶材料を好適に用いることができる。フッ素系の液晶材料は、アクティブマトリクス駆動の液晶表示装置によく用いられ、大きな誘電異方性および高い比抵抗を有する。具体的には、例えば、長軸方向の誘電率ε//が２４．７、短軸方向の誘電率ε⊥が４．３、比抵抗ρが６×１０13Ω・ｃｍの液晶材料を用いることができる。勿論、液晶材料の誘電率や比抵抗は、ここで例示したものに限定されない。媒体３１を介したオフリークの発生を十分に抑制する観点からは、液晶材料の比抵抗は、１×１０11～12Ω・ｃｍ以上であることが好ましい。また、液晶材料の誘電異方性Δεは、１０を超える（Δε＞１０）ことが好ましい。 As the positive liquid crystal material, a liquid crystal material for a liquid crystal display device can be used widely and suitably. For example, a fluorine-based liquid crystal material in which fluorine is introduced into the side chain can be suitably used. Fluorine-based liquid crystal materials are often used in active matrix-driven liquid crystal display devices and have large dielectric anisotropy and high specific resistance. Specifically, for example, a dielectric constant in the major axis direction epsilon // 24.7, the short axial permittivity epsilon ⊥ 4.3, the specific resistance ρ is a liquid crystal material 6 × 10 13 Ω · cm be able to. Of course, the dielectric constant and specific resistance of the liquid crystal material are not limited to those exemplified here. From the viewpoint of sufficiently suppressing the occurrence of off-leakage through the medium 31, the specific resistance of the liquid crystal material is preferably 1 × 10 11 to 12 Ω · cm or more. The dielectric anisotropy Δε of the liquid crystal material preferably exceeds 10 (Δε> 10).
　なお、媒体３１として、負の誘電異方性を有する液晶材料（つまりネガ型の液晶材料）を用いてもよい。 Note that a liquid crystal material having negative dielectric anisotropy (that is, a negative liquid crystal material) may be used as the medium 31.
　また、本実施形態のように、第１基板１０および第２基板２０が垂直配向膜１５および２５を有していると、垂直配向膜１５および２５の配向規制力により、形状異方性粒子３２が水平状態のまま基板表面に貼り付いてしまうことが防止される。垂直配向膜１５および２５としては、ＶＡ（Vertical Alignment）モードの液晶表示装置用の垂直配向膜（例えばＪＳＲ社製や日産化学社製の、ポリイミド系やポリアミック酸系垂直配向膜）を好適に用いることができる。高誘電率のポジ型液晶材料を垂直配向させるためには、アルキル基やフッ素含有基のような疎水構造が比較的多く側鎖に導入された垂直配向膜を用いることが好ましい。垂直配向膜１５および２５のそれぞれの厚さは、例えば１００ｎｍである。勿論、これに限定されるものではない。 Further, when the first substrate 10 and the second substrate 20 have the vertical alignment films 15 and 25 as in the present embodiment, the shape anisotropic particles 32 are caused by the alignment regulating force of the vertical alignment films 15 and 25. Is prevented from sticking to the substrate surface in a horizontal state. As the vertical alignment films 15 and 25, a vertical alignment film for a liquid crystal display device in a VA (Vertical Alignment) mode (for example, a polyimide-based or polyamic acid-based vertical alignment film manufactured by JSR or Nissan Chemical) is preferably used. be able to. In order to vertically align a high dielectric constant positive liquid crystal material, it is preferable to use a vertical alignment film in which a relatively large number of hydrophobic structures such as alkyl groups and fluorine-containing groups are introduced into the side chain. The thickness of each of the vertical alignment films 15 and 25 is, for example, 100 nm. Of course, it is not limited to this.
　表示装置１００は、本実施形態のように、光学層３０にフリンジ電界および／または横電界を印加し得ることが好ましい。つまり、表示装置１００は、横電界モードを利用し得ることが好ましい。既に説明したように、個々の形状異方性粒子３２は、基本的には水平配向状態および垂直配向状態のいずれかのみをとる（つまり２値状態）が、横電界モードを用いることにより、セル厚方向の電界強度を変化させることができるので、第１基板１０側で水平配向する形状異方性粒子３２の量（数）を制御することができる。そのため、中間調表示を好適に行なうことができる。これに対し、縦電界モードでは、セル厚方向の電界強度が一定であるので、中間調表示が困難である。また、横電界モードでは、データ書き込み時の印加電圧に応じて、形状異方性粒子３２が電界強度の強い第１基板１０側へ引き寄せられるので、書き込み電圧から降圧する際の所定の電圧範囲（図１１中の範囲ｒ）において、形状異方性粒子３２の水平配向状態を維持することができる。 The display device 100 is preferably capable of applying a fringe electric field and / or a lateral electric field to the optical layer 30 as in the present embodiment. That is, it is preferable that the display device 100 can use the horizontal electric field mode. As described above, each shape anisotropic particle 32 basically takes only one of a horizontal alignment state and a vertical alignment state (that is, a binary state). Since the electric field strength in the thickness direction can be changed, the amount (number) of the shape anisotropic particles 32 horizontally oriented on the first substrate 10 side can be controlled. Therefore, halftone display can be suitably performed. On the other hand, in the vertical electric field mode, since the electric field strength in the cell thickness direction is constant, halftone display is difficult. In the horizontal electric field mode, the shape anisotropic particles 32 are attracted toward the first substrate 10 having a high electric field strength in accordance with the applied voltage at the time of data writing. In the range r) in FIG. 11, the horizontal orientation state of the shape anisotropic particles 32 can be maintained.
　なお、第１電極１１、第２電極１２および第３電極１３の構成は、図１などに例示したものに限定されない。図２２に、表示装置１００の他の電極構成を示す。 In addition, the structure of the 1st electrode 11, the 2nd electrode 12, and the 3rd electrode 13 is not limited to what was illustrated in FIG. FIG. 22 shows another electrode configuration of the display device 100.
　図２２に示す例では、第１電極１１を覆うようにさらなる絶縁層１７が設けられており、第２電極１２は、このさらなる絶縁層１７上に設けられている。つまり、第２電極１２は、さらなる絶縁層１７を介して第１電極１１の上方に設けられている。図２２に示す構成では、第１電極１１と第２電極１２とが異なるレベルに設けられているので、第１電極１１と第２電極１２との電位差により横電界ではなくフリンジ電界（電気力線Ｅｆ’で表わされる）が生成される。図２２に示す構成では、第１電極１１と第２電極１２との間にさらなる絶縁層１７が位置しているので、第１電極１１と第２電極１２との間隔を狭めても短絡することがないという利点が得られる。 In the example shown in FIG. 22, a further insulating layer 17 is provided so as to cover the first electrode 11, and the second electrode 12 is provided on the further insulating layer 17. That is, the second electrode 12 is provided above the first electrode 11 via the further insulating layer 17. In the configuration shown in FIG. 22, since the first electrode 11 and the second electrode 12 are provided at different levels, a fringe electric field (electric field lines) is generated instead of a lateral electric field due to a potential difference between the first electrode 11 and the second electrode 12. Ef ′) is generated. In the configuration shown in FIG. 22, since a further insulating layer 17 is located between the first electrode 11 and the second electrode 12, a short circuit occurs even if the interval between the first electrode 11 and the second electrode 12 is narrowed. The advantage is that there is no.
　図２３に、表示装置１００のさらに他の電極構成を示す。図２３に示す例では、第３電極１３は、第１電極１１および第２電極１２に重なる位置に形成された複数のスリット１３ｓを有する。図２３に示す構成では、フリンジ電界の分布を、第１電極１１または第２電極１２の端部に集中したものから、第１電極１１および第２電極１２間（隣接する枝部１１ａおよび１２ａ間）の中央寄りのものにすることができるという利点が得られる。一方、図１などに示したように、第３電極１３がべた電極である構成では、第１電極１１および第２電極１２と、第３電極１３と、これらの間に位置する絶縁層１４とによって補助容量を構成できるという利点が得られる。 FIG. 23 shows still another electrode configuration of the display device 100. In the example shown in FIG. 23, the third electrode 13 has a plurality of slits 13 s formed at positions overlapping the first electrode 11 and the second electrode 12. In the configuration shown in FIG. 23, the fringe electric field distribution is concentrated from the end of the first electrode 11 or the second electrode 12 to between the first electrode 11 and the second electrode 12 (between adjacent branch portions 11a and 12a). ), It is possible to make it closer to the center. On the other hand, as shown in FIG. 1 and the like, in the configuration in which the third electrode 13 is a solid electrode, the first electrode 11 and the second electrode 12, the third electrode 13, and the insulating layer 14 positioned between them. The advantage that an auxiliary capacity can be configured is obtained.
　勿論、図２２および図２３に例示した電極構成以外の改変例を採用してもよい。例えば、第１電極１１および第２電極１２の一方を省略してもよい。 Of course, modifications other than the electrode configuration illustrated in FIGS. 22 and 23 may be adopted. For example, one of the first electrode 11 and the second electrode 12 may be omitted.
　ここで、図２４を参照しながら、アクティブマトリクス駆動を行う場合の背面基板１０における具体的な配線構造の例を説明する。 Here, an example of a specific wiring structure in the rear substrate 10 when active matrix driving is performed will be described with reference to FIG.
　図２４に示す例では、各画素に３つのＴＦＴ（第１ＴＦＴ、第２ＴＦＴおよび第３ＴＦＴ）ｔ１、ｔ２およびｔ３が設けられている。第１電極１１、第２電極１２および第３電極１３は、それぞれ第１ＴＦＴｔ１、第２ＴＦＴｔ２および第３ＴＦＴｔ３に電気的に接続されている。また、図２４に示す例では、行方向に延びるゲート配線ＧＬと、列方向に延びる第１ソース配線ＳＬ１、第２ソース配線ＳＬ２および第３ソース配線ＳＬ３とが設けられている。第１ＴＦＴｔ１は、ゲート配線ＧＬおよび第１ソース配線ＳＬ１からゲート信号および第１ソース信号を供給される。第２ＴＦＴｔ２は、ゲート配線ＧＬおよび第２ソース配線ＳＬ２からゲート信号および第２ソース信号を供給される。第３ＴＦＴｔ３は、ゲート配線ＧＬおよび第３ソース配線ＳＬ３からゲート信号および第３ソース信号を供給される。 In the example shown in FIG. 24, three TFTs (first TFT, second TFT, and third TFT) t1, t2, and t3 are provided for each pixel. The first electrode 11, the second electrode 12, and the third electrode 13 are electrically connected to the first TFT t1, the second TFT t2, and the third TFT t3, respectively. In the example shown in FIG. 24, a gate line GL extending in the row direction and a first source line SL1, a second source line SL2, and a third source line SL3 extending in the column direction are provided. The first TFT t1 is supplied with a gate signal and a first source signal from the gate line GL and the first source line SL1. The second TFT t2 is supplied with a gate signal and a second source signal from the gate line GL and the second source line SL2. The third TFT t3 is supplied with the gate signal and the third source signal from the gate line GL and the third source line SL3.
　第１ＴＦＴｔ１、第２ＴＦＴｔ２および第３ＴＦＴｔ３が有する半導体層の材料としては、公知の種々の半導体材料を用いることができ、例えば、アモルファスシリコン、多結晶シリコン、連続粒界結晶シリコン（ＣＧＳ：Continuous Grain Silicon）などを用いることができる。 As the material of the semiconductor layer included in the first TFT t1, the second TFT t2, and the third TFT t3, various known semiconductor materials can be used. For example, amorphous silicon, polycrystalline silicon, continuous grain boundary crystal silicon (CGS: Continuous Grain Silicon) Etc. can be used.
　また、半導体層は、酸化物半導体から形成された酸化物半導体層であってもよい。酸化物半導体層は、例えばＩｎ－Ｇａ－Ｚｎ－Ｏ系の半導体を含む。ここで、Ｉｎ－Ｇａ－Ｚｎ－Ｏ系半導体は、Ｉｎ（インジウム）、Ｇａ（ガリウム）、Ｚｎ（亜鉛）の三元系酸化物であって、Ｉｎ、ＧａおよびＺｎの割合（組成比）は特に限定されず、例えばＩｎ：Ｇａ：Ｚｎ＝２：２：１、Ｉｎ：Ｇａ：Ｚｎ＝１：１：１、Ｉｎ：Ｇａ：Ｚｎ＝１：１：２等を含む。Ｉｎ－Ｇａ－Ｚｎ－Ｏ系半導体は、アモルファスでもよいし、結晶質でもよい。結晶質のＩｎ－Ｇａ－Ｚｎ－Ｏ系半導体としては、ｃ軸が層面に概ね垂直に配向したものが好ましい。このようなＩｎ－Ｇａ－Ｚｎ－Ｏ系半導体の結晶構造は、例えば、特開２０１２－１３４４７５号公報に開示されている。参考のために、特開２０１２－１３４４７５号公報の開示内容の全てを本明細書に援用する。Ｉｎ－Ｇａ－Ｚｎ－Ｏ系半導体層を有するＴＦＴは、高い移動度（ａ－ＳｉＴＦＴに比べ２０倍超）および低いリーク電流（ａ－ＳｉＴＦＴに比べ１００分の１未満）を有している。従って、半導体層として、Ｉｎ－Ｇａ－Ｚｎ－Ｏ系半導体から形成された酸化物半導体層を用いると、オフリークが少ないので、消費電力のいっそうの低減を図ることができる。 The semiconductor layer may be an oxide semiconductor layer formed from an oxide semiconductor. The oxide semiconductor layer includes, for example, an In—Ga—Zn—O-based semiconductor. Here, the In—Ga—Zn—O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio (composition ratio) of In, Ga, and Zn is It is not specifically limited, For example, In: Ga: Zn = 2: 2: 1, In: Ga: Zn = 1: 1: 1, In: Ga: Zn = 1: 1: 2, etc. are included. The In—Ga—Zn—O-based semiconductor may be amorphous or crystalline. As the crystalline In—Ga—Zn—O-based semiconductor, a semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface is preferable. Such a crystal structure of an In—Ga—Zn—O-based semiconductor is disclosed in, for example, Japanese Patent Laid-Open No. 2012-134475. For reference, the entire disclosure of Japanese Patent Application Laid-Open No. 2012-134475 is incorporated herein by reference. A TFT having an In—Ga—Zn—O-based semiconductor layer has high mobility (more than 20 times that of an a-Si TFT) and low leakage current (less than one hundredth of that of an a-Si TFT). Therefore, when an oxide semiconductor layer formed using an In—Ga—Zn—O-based semiconductor is used as the semiconductor layer, power consumption can be further reduced because off-leakage is small.
　なお、酸化物半導体層は、Ｉｎ－Ｇａ－Ｚｎ－Ｏ系半導体層に限定されない。酸化物半導体層は、例えばＺｎ－Ｏ系半導体（ＺｎＯ）、Ｉｎ－Ｚｎ－Ｏ系半導体（ＩＺＯ）、Ｚｎ－Ｔｉ－Ｏ系半導体（ＺＴＯ）、Ｃｄ－Ｇｅ－Ｏ系半導体、Ｃｄ－Ｐｂ－Ｏ系半導体、Ｉｎ－Ｓｎ－Ｚｎ－Ｏ系半導体（例えばＩｎ2Ｏ3－ＳｎＯ2－ＺｎＯ）、Ｉｎ－Ｇａ－Ｓｎ－Ｏ系半導体などを含んでいてもよい。 Note that the oxide semiconductor layer is not limited to the In—Ga—Zn—O-based semiconductor layer. The oxide semiconductor layer includes, for example, a Zn—O based semiconductor (ZnO), an In—Zn—O based semiconductor (IZO), a Zn—Ti—O based semiconductor (ZTO), a Cd—Ge—O based semiconductor, a Cd—Pb— An O-based semiconductor, an In—Sn—Zn—O based semiconductor (eg, In 2 O 3 —SnO 2 —ZnO), an In—Ga—Sn—O based semiconductor, or the like may be included.
　図２４に示す配線構造により、アクティブマトリクス駆動を行うことができる。勿論、背面基板１０の配線構造は、図２４に示す例に限定されない。各画素に設けられる薄膜トランジスタ（ＴＦＴ）として、酸化物半導体層を含む酸化物半導体ＴＦＴを用いると、オフリークが少ないので、図２０（ｂ）に例示したような低周波駆動を好適に行うことができる。 The active matrix driving can be performed by the wiring structure shown in FIG. Of course, the wiring structure of the back substrate 10 is not limited to the example shown in FIG. When an oxide semiconductor TFT including an oxide semiconductor layer is used as a thin film transistor (TFT) provided in each pixel, there is less off-leakage, and thus low-frequency driving as illustrated in FIG. 20B can be suitably performed. .
　なお、本実施形態では、第２基板２０側に第４電極２１が設けられているが、第４電極２１は省略されてもよい。光学層３０を電界無印加状態にすることにより、形状異方性粒子３２は垂直配向状態をとるからである。ただし、応答速度の観点からは、第２基板２０側に第４電極２１が設けられた構成（つまり光学層３０に縦電界が印加され得る構成）を採用することが好ましい。つまり、光学層３０に縦電界が生成された状態と、光学層３０にフリンジ電界および／または横電界が生成された状態とを切り替えることによって表示が行われることが好ましい。前者の状態から後者の状態への変化、および、後者の状態から前者の状態への変化は、いずれも印加電界の方向を変化させることにより行われるので、十分な応答速度を実現することができる。 In the present embodiment, the fourth electrode 21 is provided on the second substrate 20 side, but the fourth electrode 21 may be omitted. This is because, when the optical layer 30 is in a state where no electric field is applied, the shape anisotropic particles 32 take a vertical alignment state. However, from the viewpoint of response speed, it is preferable to adopt a configuration in which the fourth electrode 21 is provided on the second substrate 20 side (that is, a configuration in which a vertical electric field can be applied to the optical layer 30). That is, it is preferable that display is performed by switching between a state in which a vertical electric field is generated in the optical layer 30 and a state in which a fringe electric field and / or a horizontal electric field is generated in the optical layer 30. Since the change from the former state to the latter state and the change from the latter state to the former state are both performed by changing the direction of the applied electric field, a sufficient response speed can be realized. .
　また、既に説明したように、本発明の実施形態による表示装置１００は、中間調表示を好適に行うことができる。そのため、各画素にカラーフィルタを設けることにより、階調に応じたマルチカラー表示を行うことができる。 Also, as already described, the display device 100 according to the embodiment of the present invention can suitably perform halftone display. Therefore, by providing a color filter for each pixel, multicolor display corresponding to gradation can be performed.
　形状異方性粒子３２は、上述したように印加電圧（印加電界の方向）に応じて基板面への投影面積が変化する限り、その具体的な形状や材料には、特に制限はない。形状異方性部材３２は、フレーク状（薄片状）であってもよいし、円柱状や楕円球状などであってもよい。高いコントラスト比を実現する観点からは、形状異方性粒子３２は、最大投影面積と最小投影面積との比が２：１以上となるような形状であることが好ましい。 The shape anisotropic particles 32 are not particularly limited in specific shape and material as long as the projected area on the substrate surface changes according to the applied voltage (direction of applied electric field) as described above. The shape anisotropic member 32 may have a flake shape (flaky shape), a cylindrical shape, an oval shape, or the like. From the viewpoint of realizing a high contrast ratio, the shape anisotropic particle 32 preferably has a shape such that the ratio of the maximum projected area to the minimum projected area is 2: 1 or more.
　形状異方性粒子３２の材料としては、金属材料、半導体材料、誘電体材料およびこれらの複合材料を用いることができる。また、形状異方性粒子３２は、誘電体多層膜であってもよいし、コレステリック樹脂材料から形成されてもよい。なお、形状異方性粒子３２の材料として金属材料を用いる場合、形状異方性粒子３２の表面に絶縁層（誘電体層）が形成されていることが好ましい。金属単体の誘電率は虚数であるが、表面に絶縁層（例えば樹脂層や金属酸化物層）を形成することにより、金属材料から形成された形状異方性粒子３２を誘電体として扱うことができる。また、表面に絶縁層が形成されていることにより、金属材料から形成された形状異方性粒子３２同士の接触による導通や、物理的な相互作用による凝集等を防止する効果も得られる。このような形状異方性粒子３２としては、例えば、表面を樹脂材料（例えばアクリル樹脂）で被覆されたアルミニウムフレークを用いることができる。表示媒体層３０のアルミニウムフレーク含有量は、例えば６重量％である。あるいは、表面にＳｉＯ2層が形成されたアルミニウムフレークや、表面に酸化アルミニウム層が形成されたアルミニウムフレークなどを用いることもできる。勿論、金属材料としてアルミニウム以外の金属材料を用いてもよい。また、形状異方性粒子３２は、着色されていてもよい。 As a material of the shape anisotropic particle 32, a metal material, a semiconductor material, a dielectric material, and a composite material thereof can be used. The shape anisotropic particles 32 may be a dielectric multilayer film or may be formed from a cholesteric resin material. When a metal material is used as the material for the shape anisotropic particles 32, an insulating layer (dielectric layer) is preferably formed on the surface of the shape anisotropic particles 32. Although the dielectric constant of a single metal is an imaginary number, by forming an insulating layer (for example, a resin layer or a metal oxide layer) on the surface, the shape anisotropic particles 32 formed of a metal material can be handled as a dielectric. it can. In addition, since the insulating layer is formed on the surface, an effect of preventing conduction due to contact between the shape anisotropic particles 32 formed of a metal material, aggregation due to physical interaction, and the like can be obtained. As such shape anisotropic particles 32, for example, aluminum flakes whose surfaces are coated with a resin material (for example, acrylic resin) can be used. The aluminum flake content of the display medium layer 30 is, for example, 6% by weight. Alternatively, aluminum flakes having an SiO 2 layer formed on the surface, aluminum flakes having an aluminum oxide layer formed on the surface, or the like can also be used. Of course, a metal material other than aluminum may be used as the metal material. Further, the shape anisotropic particles 32 may be colored.
　形状異方性粒子３２の長さは、特に制限されないが、４μｍ以上１０μｍ以下であることが好ましい。形状異方性粒子３２の長さが１０μｍを超えると、形状異方性粒子３２が移動しにくくなることがある。一方、形状異方性粒子３２の長さが４μｍ未満になると、形状異方性粒子３２の製造が困難になったり、形状異方性粒子３２の反射性能が十分でなくなったりすることがある。また、本実施形態のような反射型表示装置で、高い反射率を得るために水平配向状態において形状異方性粒子３２で基板面を覆い尽くしたい場合には、形状異方性粒子３２の長さを、電極ピッチｐ（図２参照）以上とすることが好ましい。形状異方性粒子３２の厚さも、特に制限されない。ただし、形状異方性粒子３２の厚さが小さいほど、透明状態における表示媒体層３０の透過率を高くすることができるので、形状異方性粒子３２の厚さは、電極間距離ｇよりも小さい（例えば４μｍ以下）ことが好ましく、光の波長以下である（例えば０．５μｍ以下）ことがより好ましい。 The length of the shape anisotropic particles 32 is not particularly limited, but is preferably 4 μm or more and 10 μm or less. If the length of the shape anisotropic particles 32 exceeds 10 μm, the shape anisotropic particles 32 may be difficult to move. On the other hand, when the length of the shape anisotropic particles 32 is less than 4 μm, it may be difficult to produce the shape anisotropic particles 32 or the reflective performance of the shape anisotropic particles 32 may be insufficient. Further, in the reflective display device as in the present embodiment, when it is desired to cover the substrate surface with the shape anisotropic particles 32 in the horizontal alignment state in order to obtain a high reflectance, the length of the shape anisotropic particles 32 is increased. It is preferable that the pitch be equal to or greater than the electrode pitch p (see FIG. 2). The thickness of the shape anisotropic particle 32 is not particularly limited. However, since the transmittance of the display medium layer 30 in the transparent state can be increased as the thickness of the shape anisotropic particles 32 is smaller, the thickness of the shape anisotropic particles 32 is larger than the inter-electrode distance g. It is preferably small (for example, 4 μm or less), and more preferably light wavelength or less (for example, 0.5 μm or less).
　形状異方性粒子３２の比重は、１１ｇ／ｃｍ3以下であることが好ましく、３ｇ／ｃｍ3以下であることがより好ましく、媒体３１と同程度の比重であることがさらに好ましい。これは、形状異方性粒子３２の比重が媒体３１の比重と大きく異なっていると、形状異方性粒子３２が沈降または浮遊するという問題が生じ得るからである。また、媒体３１の搖動によって形状異方性粒子３２を移動させる効果を高くする観点からは、形状異方性粒子３２は軽いことが好ましい。 The specific gravity of the shape anisotropic particles 32 is preferably 11g / cm 3 or less, more preferably 3 g / cm 3 or less, further preferably the specific gravity substantially equal to that of the medium 31. This is because if the specific gravity of the shape anisotropic particles 32 is significantly different from the specific gravity of the medium 31, there may be a problem that the shape anisotropic particles 32 settle or float. From the viewpoint of increasing the effect of moving the shape anisotropic particles 32 by the peristaltic motion of the medium 31, the shape anisotropic particles 32 are preferably light.
　なお、上記の説明では、アクティブマトリクス基板である第１基板１０が背面側に配置されている構成を例示したが、第１基板１０の配置は、これに限定されるものではない。第１基板１０は、前面側に配置されていてもよい。アクティブマトリクス基板である第１基板１０は、遮光性を有する材料から形成された構成要素を含むので、第１基板１０が背面側に配置されている構成を採用すると、形状異方性粒子３２の反射効果を最大限利用することができる。 In the above description, the configuration in which the first substrate 10 which is an active matrix substrate is arranged on the back side is illustrated, but the arrangement of the first substrate 10 is not limited to this. The first substrate 10 may be disposed on the front side. Since the first substrate 10 that is an active matrix substrate includes components formed from a light-shielding material, if the configuration in which the first substrate 10 is disposed on the back side is adopted, the shape anisotropic particles 32 The reflection effect can be used to the maximum.
　また、上記の説明では、反射型の表示装置１００を例として説明を行ったが、本発明の実施形態は、透過型の表示装置（あるいは透過反射両用型の透明ディスプレイ用表示装置）にも好適に用いられる。透過型の表示装置では、背面側の基板には光吸収層（図１などに示されている光吸収層１６）は設けられない。また、透過型の表示装置では、表示パネルに光を照射する照明素子（バックライト）が設けられる。 In the above description, the reflective display device 100 has been described as an example. However, the embodiment of the present invention is also suitable for a transmissive display device (or a transmissive / reflective display device for transparent display). Used for. In the transmissive display device, a light absorption layer (the light absorption layer 16 illustrated in FIG. 1 and the like) is not provided on the back substrate. In a transmissive display device, an illumination element (backlight) that irradiates light to the display panel is provided.
　本発明の実施形態を透過型の表示装置に適用した場合、画素の電圧－透過率特性がヒステリシス性を有し、印加電圧を増加させていくときの電圧－透過率特性を示す昇圧曲線における閾値電圧が、印加電圧を減少させていくときの電圧－透過率特性を示す降圧曲線における閾値電圧よりも高い。そして、印加電圧をゼロから増加させていくときの昇圧曲線における透過率の値が、電圧値に対して実質的に１対１の関係で決まるので、書き込み電圧を、昇圧曲線に基づいて設定することにより、中間調表示を好適に行うことができる。また、保持電圧を書き込み電圧よりも低く設定することにより、消費電力を低減することができる。 When the embodiment of the present invention is applied to a transmissive display device, the voltage-transmittance characteristic of the pixel has hysteresis, and the threshold value in the boost curve indicating the voltage-transmittance characteristic when the applied voltage is increased The voltage is higher than the threshold voltage in the step-down curve indicating the voltage-transmittance characteristics when the applied voltage is decreased. Then, since the transmittance value in the boosting curve when the applied voltage is increased from zero is determined in a substantially one-to-one relationship with the voltage value, the write voltage is set based on the boosting curve. Thus, halftone display can be suitably performed. Further, power consumption can be reduced by setting the holding voltage lower than the writing voltage.
　降圧曲線において、書き込み電圧から書き込み電圧よりも低い所定の電圧までの範囲で透過率が実質的に一定であることが好ましい。降圧曲線がこのような範囲を有することにより、低消費電力状態においても透過率を十分に維持することができ、上記範囲内における電圧に対する透過率のばらつきを低減することができる。 In the step-down curve, it is preferable that the transmittance is substantially constant in a range from the writing voltage to a predetermined voltage lower than the writing voltage. When the step-down curve has such a range, the transmittance can be sufficiently maintained even in a low power consumption state, and the variation in transmittance with respect to the voltage within the above range can be reduced.
　透過型の表示装置においても、保持電圧は、書き込み電圧よりも２０％以上低いことが好ましい。保持電圧を書き込み電圧よりも２０％以上低くすることにより、消費電力の大幅な低減を実現することができる。 Also in the transmissive display device, the holding voltage is preferably 20% or more lower than the writing voltage. By making the holding voltage 20% or more lower than the write voltage, a significant reduction in power consumption can be realized.
　保持電圧が印加されているときの画素の透過率Ｔｈは、書き込み電圧が印加されているときの画素の透過率Ｔｗの０．９倍以上１．１倍以下である（つまり０．９Ｔｗ≦Ｔｈ≦１．１Ｔｗの関係が満足される）ことが好ましい。前者の透過率Ｔｈが、後者の透過率Ｔｗの０．９倍以上１．１倍以下であると、印加電圧が書き込み電圧から保持電圧に変化する際の透過率率の変化を観察者が認識しにくい。 The pixel transmittance Th when the holding voltage is applied is 0.9 to 1.1 times the pixel transmittance Tw when the writing voltage is applied (that is, 0.9Tw ≦ Th). It is preferable that the relationship of ≦ 1.1 Tw is satisfied. If the former transmittance Th is 0.9 times or more and 1.1 times or less than the latter transmittance Tw, the observer recognizes the change in the transmittance when the applied voltage changes from the writing voltage to the holding voltage. Hard to do.
　また、現フレームの印加電圧に対応する透過率が次フレームの書き込み電圧に対応する透過率よりも低い場合、画素への印加電圧をいったんゼロにし、その後、画素に本来の書き込み電圧を印加すればよい。あるいは、光学層にいったん縦電界を印加し、その後、画素に本来の書き込み電圧を印加してもよい。 If the transmittance corresponding to the applied voltage of the current frame is lower than the transmittance corresponding to the writing voltage of the next frame, the applied voltage to the pixel is once reduced to zero and then the original writing voltage is applied to the pixel. Good. Alternatively, a vertical electric field may be once applied to the optical layer, and then an original writing voltage may be applied to the pixel.
　本発明の実施形態によると、低消費電力性に優れ、中間調表示が可能な光学装置が提供される。 According to the embodiment of the present invention, an optical device that is excellent in low power consumption and capable of halftone display is provided.
　１０　　第１基板
　１０ａ　　基板
　１１　　第１電極（第１上層電極）
　１１ａ　　第１電極の枝部
　１１ｂ　　第１電極の幹部
　１２　　第２電極（第２上層電極）
　１２ａ　　第２電極の枝部
　１２ｂ　　第２電極の幹部
　１３　　第３電極（下層電極）
　１３ｓ　　第３電極のスリット
　１４　　絶縁層
　１５、２５　　垂直配向膜
　１６　　光吸収層
　１７　　さらなる絶縁層
　２０　　第２基板
　２０ａ　　基板
　２１　　第４電極（対向電極）
　２２　　誘電体層（オーバーコート層）
　３０　　光学層（表示媒体層）
　３１　　媒体（液晶材料）
　３２　　形状異方性粒子
　１００　　表示装置
　ＧＬ　　ゲート配線
　ＳＬ１　　第１ソース配線
　ＳＬ２　　第２ソース配線
　ＳＬ３　　第３ソース配線
　ｔ１　　第１薄膜トランジスタ
　ｔ２　　第２薄膜トランジスタ
　ｔ３　　第３薄膜トランジスタ DESCRIPTION OF SYMBOLS 10 1st board | substrate 10a board | substrate 11 1st electrode (1st upper layer electrode)
11a Branch portion of the first electrode 11b Trunk portion of the first electrode 12 Second electrode (second upper layer electrode)
12a Branch portion of second electrode 12b Trunk portion of second electrode 13 Third electrode (lower layer electrode)
13s Slit of third electrode 14 Insulating layer 15, 25 Vertical alignment film 16 Light absorbing layer 17 Further insulating layer 20 Second substrate 20a Substrate 21 Fourth electrode (counter electrode)
22 Dielectric layer (overcoat layer)
30 Optical layer (display medium layer)
31 Medium (Liquid Crystal Material)
32 shape anisotropic particle 100 display device GL gate wiring SL1 first source wiring SL2 second source wiring SL3 third source wiring t1 first thin film transistor t2 second thin film transistor t3 third thin film transistor

Claims (15)

  1. 　画素を有し、前記画素への印加電圧の大きさに応じて前記画素の反射率または透過率が変化する光学装置であって、
    　前記画素の電圧－反射率特性または電圧－透過率特性がヒステリシス性を有し、
    　印加電圧を増加させていくときの前記電圧－反射率特性または前記電圧－透過率特性を示す昇圧曲線における閾値電圧が、印加電圧を減少させていくときの前記電圧－反射率特性または前記電圧－透過率特性を示す降圧曲線における閾値電圧よりも高く、
    　印加電圧がゼロである状態において、前記画素はメモリ性を有しておらず、
    　印加電圧をゼロから増加させていくときの前記昇圧曲線における反射率または透過率の値は、電圧値に対して実質的に１対１の関係で決まり、
    　前記画素へのデータ書き込み時の印加電圧である書き込み電圧が、前記昇圧曲線に基づいて設定されている光学装置。     An optical device having a pixel, wherein the reflectance or transmittance of the pixel changes according to the magnitude of an applied voltage to the pixel,
    The voltage-reflectance characteristic or voltage-transmittance characteristic of the pixel has hysteresis.
    The threshold voltage in the boost curve indicating the voltage-reflectance characteristic or the voltage-transmittance characteristic when the applied voltage is increased is the voltage-reflectance characteristic or the voltage- when the applied voltage is decreased. It is higher than the threshold voltage in the step-down curve indicating the transmittance characteristic,
    In a state where the applied voltage is zero, the pixel does not have a memory property,
    When the applied voltage is increased from zero, the value of reflectance or transmittance in the boosting curve is determined by a substantially one-to-one relationship with the voltage value,
    An optical device in which a writing voltage, which is an applied voltage when writing data to the pixel, is set based on the boost curve.
  2. 　前記画素がデータ保持状態にあるときの印加電圧である保持電圧が、前記書き込み電圧よりも低く設定されている請求項１に記載の光学装置。 The optical device according to claim 1, wherein a holding voltage, which is an applied voltage when the pixel is in a data holding state, is set lower than the writing voltage.
  3. 　印加電圧を前記書き込み電圧から減少させていくときの前記降圧曲線において、前記書き込み電圧から前記書き込み電圧よりも低い所定の電圧までの範囲で反射率または透過率が実質的に一定である請求項２に記載の光学装置。 The reflectance or transmittance is substantially constant in a range from the write voltage to a predetermined voltage lower than the write voltage in the step-down curve when the applied voltage is decreased from the write voltage. An optical device according to 1.
  4. 　前記保持電圧は、前記書き込み電圧よりも２０％以上低い請求項２または３に記載の光学装置。 4. The optical device according to claim 2, wherein the holding voltage is 20% or more lower than the writing voltage.
  5. 　前記保持電圧が印加されているときの前記画素の反射率または透過率は、前記書き込み電圧が印加されているときの前記画素の反射率または透過率の０．９倍以上１．１倍以下である請求項２から４のいずれかに記載の光学装置。 The reflectance or transmittance of the pixel when the holding voltage is applied is 0.9 to 1.1 times the reflectance or transmittance of the pixel when the writing voltage is applied. The optical device according to claim 2.
  6. 　前記画素に前記保持電圧が印加されるときの駆動周波数が、前記画素に前記書き込み電圧が印加されるときの駆動周波数よりも低い請求項２から５のいずれかに記載の光学装置。 6. The optical device according to claim 2, wherein a driving frequency when the holding voltage is applied to the pixel is lower than a driving frequency when the writing voltage is applied to the pixel.
  7. 　互いに対向するように設けられた第１基板および第２基板と、
    　前記第１基板および前記第２基板の間に設けられた光学層と、を備え、
    　前記光学層は、媒体と、前記媒体中に分散され、形状異方性を有する形状異方性粒子とを含む請求項２から６のいずれかに記載の光学装置。     A first substrate and a second substrate provided to face each other;
    An optical layer provided between the first substrate and the second substrate,
    The optical device according to claim 2, wherein the optical layer includes a medium and shape anisotropic particles dispersed in the medium and having shape anisotropy.
  8. 　前記媒体は、液晶材料を含む請求項７に記載の光学装置。 The optical device according to claim 7, wherein the medium includes a liquid crystal material.
  9. 　前記画素に前記書き込み電圧が印加されるときと、前記画素に前記保持電圧が印加されるときとで、互いに異なる駆動シーケンスが実行される請求項７または８に記載の光学装置。 9. The optical device according to claim 7, wherein different driving sequences are executed when the writing voltage is applied to the pixel and when the holding voltage is applied to the pixel.
  10. 　前記保持電圧の極性が１フレームごとに反転する請求項７から９のいずれかに記載の光学装置。 10. The optical device according to claim 7, wherein the polarity of the holding voltage is inverted every frame.
  11. 　前記光学層に横電界および／またはフリンジ電界を印加し得る請求項７から１０のいずれかに記載の光学装置。 The optical device according to claim 7, wherein a lateral electric field and / or a fringe electric field can be applied to the optical layer.
  12. 　現フレームの印加電圧に対応する反射率が次フレームの書き込み電圧に対応する反射率よりも高い場合、または、現フレームの印加電圧に対応する透過率が次フレームの書き込み電圧に対応する透過率よりも低い場合、前記画素への印加電圧をいったんゼロにし、その後、前記画素に本来の書き込み電圧を印加する請求項１から１１のいずれかに記載の光学装置。 When the reflectance corresponding to the applied voltage of the current frame is higher than the reflectance corresponding to the writing voltage of the next frame, or the transmittance corresponding to the applied voltage of the current frame is higher than the transmittance corresponding to the writing voltage of the next frame. The optical device according to any one of claims 1 to 11, wherein when the voltage is lower, an applied voltage to the pixel is once reduced to zero, and then an original writing voltage is applied to the pixel.
  13. 　現フレームの印加電圧に対応する反射率が次フレームの書き込み電圧に対応する反射率よりも高い場合、または、現フレームの印加電圧に対応する透過率が次フレームの書き込み電圧に対応する透過率よりも低い場合、前記光学層にいったん縦電界を印加し、その後、前記画素に本来の書き込み電圧を印加する請求項７から１１のいずれかに記載の光学装置。 When the reflectance corresponding to the applied voltage of the current frame is higher than the reflectance corresponding to the writing voltage of the next frame, or the transmittance corresponding to the applied voltage of the current frame is higher than the transmittance corresponding to the writing voltage of the next frame. The optical device according to any one of claims 7 to 11, wherein when the voltage is lower, a vertical electric field is once applied to the optical layer, and then an original writing voltage is applied to the pixel.
  14. 　前記画素に設けられた薄膜トランジスタを有し、
    　前記薄膜トランジスタは、酸化物半導体層を含む請求項１から１３のいずれかに記載の光学装置。     A thin film transistor provided in the pixel;
    The optical device according to claim 1, wherein the thin film transistor includes an oxide semiconductor layer.
  15. 　前記画素に設けられたカラーフィルタを備える請求項１から１４のいずれかに記載の光学装置。 The optical device according to claim 1, further comprising a color filter provided in the pixel.
PCT/JP2015/080786 2014-11-06 2015-10-30 Optical apparatus WO2016072363A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2014-226381 2014-11-06
JP2014226381 2014-11-06

Publications (1)

Publication Number Publication Date
WO2016072363A1 true WO2016072363A1 (en) 2016-05-12

Family

ID=55909088

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2015/080786 WO2016072363A1 (en) 2014-11-06 2015-10-30 Optical apparatus

Country Status (1)

Country Link
WO (1) WO2016072363A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108919533A (en) * 2018-08-07 2018-11-30 京东方科技集团股份有限公司 Display panel test method and device, electronic equipment

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0695624A (en) * 1992-09-11 1994-04-08 Citizen Watch Co Ltd Method for driving anti-ferroelectric liquid crystal panel
JPH07140447A (en) * 1993-11-16 1995-06-02 Seiko Epson Corp Display element
WO2014007193A1 (en) * 2012-07-05 2014-01-09 シャープ株式会社 Liquid crystal display apparatus and method for driving liquid crystal display apparatus
WO2014061492A1 (en) * 2012-10-17 2014-04-24 シャープ株式会社 Optical device and display device provided with same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0695624A (en) * 1992-09-11 1994-04-08 Citizen Watch Co Ltd Method for driving anti-ferroelectric liquid crystal panel
JPH07140447A (en) * 1993-11-16 1995-06-02 Seiko Epson Corp Display element
WO2014007193A1 (en) * 2012-07-05 2014-01-09 シャープ株式会社 Liquid crystal display apparatus and method for driving liquid crystal display apparatus
WO2014061492A1 (en) * 2012-10-17 2014-04-24 シャープ株式会社 Optical device and display device provided with same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108919533A (en) * 2018-08-07 2018-11-30 京东方科技集团股份有限公司 Display panel test method and device, electronic equipment
CN108919533B (en) * 2018-08-07 2021-04-27 京东方科技集团股份有限公司 Display panel testing method and device and electronic equipment

Similar Documents

Publication Publication Date Title
WO2012128085A1 (en) Liquid crystal display panel and liquid crystal display device
JP5719439B2 (en) Liquid crystal drive device and liquid crystal display device
US9430979B2 (en) Liquid crystal display panel, method for driving the same and display device
TWI390291B (en) Liquid crystal display device
WO2012128061A1 (en) Liquid crystal drive method and liquid crystal display device
JP5728587B2 (en) Liquid crystal driving method and liquid crystal display device
US10663826B2 (en) Liquid crystal display device
WO2013001984A1 (en) Liquid crystal display panel and liquid crystal display device
US9348178B2 (en) Liquid crystal display panel and liquid crystal display device
JP5898307B2 (en) Liquid crystal driving method and liquid crystal display device
WO2014174896A1 (en) Optical apparatus and display apparatus provided with same
WO2015062310A1 (en) Liquid crystal display panel, display device and drive method therefor
US9733535B2 (en) Array substrate, liquid crystal display panel and display device
US8339533B2 (en) Vertical alignment mode liquid crystal display and method of manufacturing the same
US10180613B2 (en) Optical device
US20140240649A1 (en) Display device
WO2016072363A1 (en) Optical apparatus
WO2016080244A1 (en) Optical device
US10073310B2 (en) Liquid crystal display device
TWI395031B (en) Pixel structure, liquid crystal display and method for operating the same
WO2015098184A1 (en) Optical device and display device provided with same
WO2016063880A1 (en) Display device
JP5608963B2 (en) Matrix type display device
WO2013146856A1 (en) Liquid crystal display apparatus and liquid crystal drive method
KR101878170B1 (en) Liquid crystal display device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15856454

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

NENP Non-entry into the national phase

Ref country code: JP

122 Ep: pct application non-entry in european phase

Ref document number: 15856454

Country of ref document: EP

Kind code of ref document: A1