WO2016067585A1 - Thin film semiconductor device, organic el display device and method for manufacturing thin film semiconductor device - Google Patents
Thin film semiconductor device, organic el display device and method for manufacturing thin film semiconductor device Download PDFInfo
- Publication number
- WO2016067585A1 WO2016067585A1 PCT/JP2015/005358 JP2015005358W WO2016067585A1 WO 2016067585 A1 WO2016067585 A1 WO 2016067585A1 JP 2015005358 W JP2015005358 W JP 2015005358W WO 2016067585 A1 WO2016067585 A1 WO 2016067585A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- film
- oxide semiconductor
- thin film
- hydrogen
- layer
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 182
- 239000010409 thin film Substances 0.000 title claims abstract description 91
- 238000000034 method Methods 0.000 title claims description 30
- 238000004519 manufacturing process Methods 0.000 title claims description 24
- 239000010408 film Substances 0.000 claims abstract description 420
- 239000001257 hydrogen Substances 0.000 claims abstract description 129
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 129
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 103
- 230000004888 barrier function Effects 0.000 claims abstract description 44
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 53
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 50
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 44
- 229910052738 indium Inorganic materials 0.000 claims description 15
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000011701 zinc Substances 0.000 claims description 11
- 229910052733 gallium Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 8
- 229910052725 zinc Inorganic materials 0.000 claims description 8
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 150000001875 compounds Chemical class 0.000 claims description 4
- 229910044991 metal oxide Inorganic materials 0.000 claims description 4
- 150000004706 metal oxides Chemical class 0.000 claims description 4
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 2
- 239000012466 permeate Substances 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 222
- 238000005401 electroluminescence Methods 0.000 description 45
- 239000000758 substrate Substances 0.000 description 39
- 238000005530 etching Methods 0.000 description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 17
- 239000007789 gas Substances 0.000 description 16
- 229910052814 silicon oxide Inorganic materials 0.000 description 16
- 238000010586 diagram Methods 0.000 description 14
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 12
- 239000000463 material Substances 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 150000002431 hydrogen Chemical class 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 239000011521 glass Substances 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 238000004544 sputter deposition Methods 0.000 description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 7
- 239000001301 oxygen Substances 0.000 description 7
- 229910052760 oxygen Inorganic materials 0.000 description 7
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 7
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 6
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- 239000011159 matrix material Substances 0.000 description 6
- 239000002356 single layer Substances 0.000 description 6
- 239000011787 zinc oxide Substances 0.000 description 6
- 239000000203 mixture Substances 0.000 description 5
- 125000004430 oxygen atom Chemical group O* 0.000 description 5
- 238000002161 passivation Methods 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 238000002474 experimental method Methods 0.000 description 4
- -1 for example Substances 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 230000000704 physical effect Effects 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 238000005033 Fourier transform infrared spectroscopy Methods 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 229910007541 Zn O Inorganic materials 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 3
- 239000000470 constituent Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 229910000077 silane Inorganic materials 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910001882 dioxygen Inorganic materials 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 125000000896 monocarboxylic acid group Chemical group 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 239000001272 nitrous oxide Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 1
- 206010021143 Hypoxia Diseases 0.000 description 1
- 229910000914 Mn alloy Inorganic materials 0.000 description 1
- 229910052779 Neodymium Inorganic materials 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- HSFWRNGVRCDJHI-UHFFFAOYSA-N alpha-acetylene Natural products C#C HSFWRNGVRCDJHI-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 229920001940 conductive polymer Polymers 0.000 description 1
- HPDFFVBPXCTEDN-UHFFFAOYSA-N copper manganese Chemical compound [Mn].[Cu] HPDFFVBPXCTEDN-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000005525 hole transport Effects 0.000 description 1
- 238000005984 hydrogenation reaction Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- WPBNNNQJVZRUHP-UHFFFAOYSA-L manganese(2+);methyl n-[[2-(methoxycarbonylcarbamothioylamino)phenyl]carbamothioyl]carbamate;n-[2-(sulfidocarbothioylamino)ethyl]carbamodithioate Chemical compound [Mn+2].[S-]C(=S)NCCNC([S-])=S.COC(=O)NC(=S)NC1=CC=CC=C1NC(=S)NC(=O)OC WPBNNNQJVZRUHP-UHFFFAOYSA-L 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- MGRWKWACZDFZJT-UHFFFAOYSA-N molybdenum tungsten Chemical compound [Mo].[W] MGRWKWACZDFZJT-UHFFFAOYSA-N 0.000 description 1
- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 150000007524 organic acids Chemical class 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920001197 polyacetylene Polymers 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 229920000123 polythiophene Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000005477 sputtering target Methods 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 239000013077 target material Substances 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B33/00—Electroluminescent light sources
- H05B33/12—Light sources with substantially two-dimensional radiating surfaces
- H05B33/22—Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of auxiliary dielectric or reflective layers
Definitions
- the present disclosure relates to a thin film semiconductor device, an organic EL display device, and a method for manufacturing a thin film semiconductor device, and in particular, a thin film transistor (TFT: Thin Film Transistor) having an oxide semiconductor layer, a method for manufacturing the thin film transistor, and an organic film using the thin film transistor
- TFT Thin Film Transistor
- the present invention relates to an EL display device.
- Patent Document 1 discloses an active matrix organic EL display device using a TFT substrate.
- the channel layer of the TFT has a channel region in which carrier movement is controlled by a voltage applied to the gate electrode.
- various semiconductor materials such as silicon have been studied.
- an oxide semiconductor TFT using an oxide semiconductor such as a transparent amorphous oxide semiconductor TAOS: Transparent Amorphous Oxide Semiconductor
- TAOS transparent amorphous oxide semiconductor
- a TFT having a channel layer made of an oxide semiconductor has a problem that it is difficult to obtain desired performance.
- one embodiment of a thin film semiconductor device includes an oxide semiconductor layer, an insulating film, and hydrogen that is formed between the oxide semiconductor layer and the insulating film and suppresses permeation of hydrogen.
- a hydrogen barrier film having a barrier property, and the insulating film contains hydrogen in an amount capable of passing through the hydrogen barrier film.
- One embodiment of a method for manufacturing a thin film semiconductor device includes a step of forming an oxide semiconductor layer, a step of forming an insulating film, and transmitting hydrogen between the oxide semiconductor layer and the insulating film. And a step of forming a hydrogen barrier film having a hydrogen barrier property, wherein the insulating film contains an amount of hydrogen that can pass through the hydrogen barrier film.
- a thin film semiconductor device having desired performance can be realized.
- FIG. 1 is a cross-sectional view of a thin film transistor according to an embodiment.
- FIG. 2 is a diagram for explaining a manufacturing method of the TFT.
- FIG. 3 is a diagram illustrating the relationship between the standby time from when the resist is removed and the oxide semiconductor layer is exposed until it is covered with the insulating layer, and the threshold voltage of the TFT.
- FIG. 4A is a diagram showing film formation conditions for the three types of silicon nitride films used in the experiment.
- FIG. 4B is a diagram showing physical property values of three types of silicon nitride films deposited under the deposition conditions of FIG. 4A.
- FIG. 5 shows a waiting time from when the resist is removed and the oxide semiconductor layer is exposed to covering with an insulating layer in a TFT using three types of silicon nitride films formed under the film forming conditions of FIG. 4A. It is a figure which shows the relationship with the threshold voltage of TFT.
- 6A is a diagram for explaining hydrogen diffusion in the thin film transistor of Comparative Example 1.
- FIG. 6B is a diagram for explaining hydrogen diffusion in the thin film transistor according to the embodiment having the structure shown in FIG. 1.
- 6C is a diagram for explaining hydrogen diffusion in the thin film transistor of Comparative Example 2.
- FIG. FIG. 7A is a cross-sectional view of the gate electrode formation step in the TFT manufacturing method according to the embodiment.
- FIG. 7B is a cross-sectional view of the gate insulating layer forming step in the TFT manufacturing method according to the embodiment.
- FIG. 7C is a cross-sectional view of the oxide semiconductor film formation step in the TFT manufacturing method according to the exemplary embodiment.
- FIG. 7D is a cross-sectional view of a resist formation step in the TFT manufacturing method according to the embodiment.
- FIG. 7E is a cross-sectional view of the oxide semiconductor film processing step in the manufacturing method of the TFT according to the exemplary embodiment.
- FIG. 7F is a cross-sectional view of the resist removal step in the TFT manufacturing method according to the embodiment.
- FIG. 7G is a cross-sectional view of the insulating layer forming step in the TFT manufacturing method according to the embodiment.
- FIG. 7H is a cross-sectional view of the contact hole forming step in the TFT manufacturing method according to the embodiment.
- FIG. 7I is a cross-sectional view of the source electrode and drain electrode forming step in the TFT manufacturing method according to the embodiment.
- FIG. 7J is a cross-sectional view of an insulating layer forming step in the TFT manufacturing method according to the embodiment.
- FIG. 8 is a partially cutaway perspective view of the organic EL display device according to the embodiment.
- FIG. 9 is a perspective view illustrating an example of a pixel bank of the organic EL display device according to the embodiment.
- FIG. 10 is an electric circuit diagram illustrating a configuration of a pixel circuit in the organic EL display device according to the embodiment.
- a thin film transistor including an oxide semiconductor layer as a channel layer will be described as an example of a thin film semiconductor device including an oxide semiconductor layer.
- FIG. 1 is a cross-sectional view of a thin film transistor according to an embodiment.
- the thin film transistor 10 is an oxide semiconductor TFT having an oxide semiconductor as a channel layer, and includes a substrate 1, a gate electrode 2, a gate insulating layer 3, an oxide semiconductor layer 4, and an insulating layer. A layer 5, a source electrode 6 ⁇ / b> S and a drain electrode 6 ⁇ / b> D, and an insulating layer 7 are provided.
- the thin film transistor 10 in this embodiment is a channel protection type bottom gate type TFT and adopts a top contact structure.
- the substrate 1 is an insulating substrate made of an insulating material, for example, a glass substrate made of a glass material such as quartz glass, non-alkali glass, or high heat resistant glass.
- the substrate 1 is, for example, a G8 glass substrate.
- the substrate 1 is not limited to a glass substrate but may be a resin substrate or the like.
- the substrate 1 may be a flexible substrate instead of a rigid substrate. Further, an undercoat layer may be formed on the surface of the substrate 1.
- the gate electrode 2 is an electrode having a single layer structure or a multilayer structure of a conductive film made of a conductive material such as metal or an alloy thereof, and is formed in a predetermined shape above the substrate 1.
- the film thickness of the gate electrode 2 is, for example, about 20 nm to 500 nm.
- Examples of the material of the gate electrode 2 include molybdenum, aluminum, copper, tungsten, titanium, manganese, chromium, tantalum, niobium, silver, gold, platinum, palladium, indium, nickel, neodymium, or the like.
- An alloy of a metal selected from (for example, molybdenum tungsten) is used.
- the material of the gate electrode 2 is not limited to these, and conductive metal oxides such as indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), and gallium-doped zinc oxide (GZO), polythiophene, A conductive polymer material such as polyacetylene can also be used.
- conductive metal oxides such as indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), and gallium-doped zinc oxide (GZO), polythiophene, A conductive polymer material such as polyacetylene can also be used.
- titanium, aluminum, gold, or the like can be used as the gate electrode 2 as a metal having good adhesion to the oxide, and a sandwich between these metals is used. .
- the gate insulating layer (gate insulating film) 3 is disposed between the gate electrode 2 and the oxide semiconductor layer 4.
- the gate insulating layer 3 is disposed so as to be located above the gate electrode 2.
- the gate insulating layer 3 is formed so as to cover the gate electrode 2 over the entire surface of the substrate 1 on which the gate electrode 2 is formed.
- the film thickness of the gate insulating layer 3 is, for example, about 50 nm to 300 nm.
- the gate insulating layer 3 is made of a material having electrical insulation, and as an example, a single layer film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, a tantalum oxide film, or a hafnium oxide film, or A laminated film in which a plurality of these films are laminated.
- the oxide semiconductor layer 4 is formed in a predetermined shape on the gate insulating layer 3 above the gate electrode 2.
- the oxide semiconductor layer 4 is formed in an island shape over the gate insulating layer 3.
- the oxide semiconductor layer 4 is a channel layer of the thin film transistor 10. That is, the oxide semiconductor layer 4 is a semiconductor layer including a channel region facing the gate electrode 2 with the gate insulating layer 3 interposed therebetween.
- the film thickness of the oxide semiconductor layer 4 is, for example, 10 nm to 200 nm.
- the oxide semiconductor layer 4 is composed of an oxide semiconductor.
- the oxide semiconductor layer 4 is made of, for example, an oxide semiconductor containing at least one of indium (In), gallium (Ga), and zinc (Zn), specifically zinc oxide (ZnO x ), oxide Indium gallium (InGaO x ), indium gallium zinc oxide (InGaZnO x ), or the like.
- the oxide semiconductor layer 4 is a transparent amorphous oxide semiconductor (TAOS), and is an IGZO film made of InGaZnO x which is a metal oxide of In, Ga, and Zn.
- the oxide semiconductor of InGaZnO X can be formed, for example, by a vapor deposition method such as a sputtering method or a laser deposition method using a polycrystalline sintered body having an InGaO 3 (ZnO) 4 composition as a target.
- a vapor deposition method such as a sputtering method or a laser deposition method using a polycrystalline sintered body having an InGaO 3 (ZnO) 4 composition as a target.
- the insulating layer 5 (first insulating layer) is disposed on the oxide semiconductor layer 4. Specifically, the insulating layer 5 is formed over the gate insulating layer 3 so as to cover the oxide semiconductor layer 4. In this embodiment, the insulating layer 5 functions as a protective film (channel protective layer) that protects the channel region of the oxide semiconductor layer 4. In the present embodiment, the insulating layer 5 is an interlayer insulating film formed on the entire upper surface of the substrate 1. The film thickness of the insulating layer 5 is, for example, about 50 nm to 500 nm.
- the insulating layer 5 is made of a material having electrical insulation properties, and is, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a single layer film of an aluminum oxide film, or a laminated film of these oxide films. .
- an opening is formed in the insulating layer 5 so as to penetrate a part of the insulating layer 5.
- the oxide semiconductor layer 4 is connected to the source electrode 6S and the drain electrode 6D through the opening of the insulating layer 5.
- the source electrode 6 ⁇ / b> S and the drain electrode 6 ⁇ / b> D are formed in a predetermined shape so that at least a part thereof is located above the insulating layer 5 and is connected to the oxide semiconductor layer 4.
- the source electrode 6S and the drain electrode 6D are disposed on the insulating layer 5 so as to be spaced apart from each other in the horizontal direction (substrate horizontal direction) with respect to the substrate 1 and opposed to each other. It is connected to the oxide semiconductor layer 4 through the formed opening.
- the film thickness of the source electrode 6S and the drain electrode 6D is, for example, about 100 nm to 500 nm.
- the source electrode 6S and the drain electrode 6D are electrodes having a single layer structure or a multilayer structure of a conductive film made of a conductive material or an alloy thereof.
- the material of the source electrode 6S and the drain electrode 6D for example, aluminum, tantalum, molybdenum, tungsten, silver, copper, titanium, or chromium is used.
- the source electrode 6S and the drain electrode 6D are electrodes having a three-layer structure in which a molybdenum film (Mo film), a copper film (Cu film), and a copper manganese alloy film (CuMn film) are formed in order from the bottom.
- Mo film molybdenum film
- Cu film copper film
- CuMn film copper manganese alloy film
- the resistance of the source electrode 6S and the drain electrode 6D can be reduced, and the source electrode 6S and the drain electrode 6D The resistance of the wiring in the same layer can be reduced.
- the insulating layer 7 (second insulating layer) is a passivation film, and is formed on the insulating layer 5 so as to cover the source electrode 6S and the drain electrode 6D.
- the insulating layer 7 has a three-layer structure, and includes a first insulating film 71, a second insulating film 72, and a third insulating film 73.
- the first insulating film 71 is formed on the insulating layer 5 so as to cover the source electrode 6S and the drain electrode 6D.
- the first insulating film 71 is preferably a film having good adhesion to the source electrode 6S and the drain electrode 6D and having a low hydrogen content in the film.
- the insulating layer 7 is used as an interlayer insulating film, contact holes are formed in the insulating layer 7 and wirings, electrodes, and the like are connected to the source electrode 6S and the drain electrode 6D.
- the film can ensure workability by etching. Therefore, for example, a silicon oxide film is preferably used as the first insulating film 71.
- the film thickness of the first insulating film 71 is, for example, about 50 nm to 500 nm.
- the second insulating film 72 is formed between the oxide semiconductor layer 4 and the third insulating film 73.
- the second insulating film 72 is formed over the first insulating film 71.
- the second insulating film 72 is a hydrogen barrier film having a hydrogen barrier property that suppresses permeation of hydrogen.
- the second insulating film 72 is preferably a film that can ensure workability by etching. Therefore, for example, an aluminum oxide film (alumina film) is preferably used as the second insulating film 72.
- the aluminum oxide film used as the second insulating film 72 in this embodiment has a film quality with a relatively low film density (that is, a film quality is coarse), and a part of hydrogen that permeates the aluminum oxide film Is blocked, and part of it is transmitted.
- the second insulating film 72 is a hydrogen barrier film having a film quality that does not completely block hydrogen but allows hydrogen to permeate.
- a hydrogen barrier film having a performance capable of simultaneously realizing hydrogen permeation and hydrogen blocking according to the amount of hydrogen can be easily realized.
- the film density can be used 2.80 g / cm 3 or more 3.25 g / cm 3 or less of the aluminum oxide film.
- the above hydrogen barrier property can be obtained by setting the film density of the aluminum oxide film to 2.80 g / cm 3 or more.
- the film density of the aluminum oxide film is set to 3.25 g / cm 3 or less, workability by etching can be ensured.
- film density of the aluminum oxide film may further When it is 2.85 g / cm 3 or more 2.95 g / cm 3 or less.
- the film density is deposited 2.80 g / cm 3 or more 3.25 g / cm 3 or less in the range aluminum oxide film may if the film thickness of the aluminum oxide film is 3nm or 30nm or less,
- the refractive index of the aluminum oxide film is preferably from 1.58 to 1.66.
- the aluminum oxide film is expressed by a composition formula of AlO x, and the number of oxygen atoms x is preferably 1.5 ⁇ x ⁇ 2.0.
- the aluminum oxide film having a stoichiometric composition is Al 2 O 3 and the number of oxygen atoms x is 1.5. In this case, the Al 2 O 3 aluminum oxide film has a crystal structure.
- AlO x aluminum oxide film in which the number of oxygen atoms x is 1.5 ⁇ x ⁇ 2.0, the aluminum oxide constituting the aluminum oxide film has an amorphous structure and the film quality is rough.
- the etchant used for wet etching for example, phosphoric acid (HPO 4 ), nitric acid (HNO 3 ), acetic acid (CH 3 COOH), and It becomes easy to react with a chemical solution mixed with water. Therefore, the aluminum oxide film in which the aluminum oxide has an amorphous structure is improved in the processability to etching than the aluminum oxide film having a crystalline structure. Therefore, in the aluminum oxide film represented by AlO x , the number of oxygen atoms x is preferably 1.5 ⁇ x ⁇ 2.0, and more preferably 1.79 ⁇ x ⁇ 1.85.
- the third insulating film 73 is formed on the second insulating film 72.
- the third insulating film 73 contains an amount of hydrogen that can pass through the second insulating film 72 (hydrogen barrier film). That is, the third insulating film 73 is a high hydrogen film.
- the third insulating film 73 in this embodiment is made of a compound containing silicon and nitrogen, and specifically made of silicon nitride.
- the ratio of the Si—H bond concentration to the N—H bond concentration is greater than 0.3 (Si—H / N). -H> 0.3) and more preferably larger than 0.4 (Si-H / N-H> 0.4).
- the third insulating film 73 may be a film having a barrier property against moisture or the like in order to suppress entry of moisture or oxygen into the lower layer, and further, similarly to the first insulating film 71.
- a film that can ensure workability by etching is preferable. Therefore, as the third insulating film 73, for example, a single layer film of a silicon nitride film or a silicon oxynitride film, or a stacked film in which a plurality of these films are stacked may be used.
- the film thickness of the third insulating film 73 is, for example, about 50 nm to 700 nm.
- a silicon oxide film is used as the first insulating film 71
- an aluminum oxide film is used as the second insulating film 72
- a silicon nitride film is used as the third insulating film 73.
- the TFT is formed, for example, by the method shown in FIG.
- FIG. 2 is a diagram for explaining a manufacturing method of the TFT.
- a gate insulating layer 3 is formed so as to cover the gate electrode 2 formed on the substrate 1.
- the gate insulating layer 3 is a silicon oxide film, for example, and can be formed by a plasma CVD Chemical Vapor Deposition method.
- an oxide semiconductor film 4 a is formed on the gate insulating layer 3.
- an IGZO film is formed as the oxide semiconductor film 4a over the entire surface of the gate insulating layer 3 by a sputtering method.
- a resist R having a predetermined shape is formed on the oxide semiconductor film 4a.
- the resist R is, for example, a photosensitive resin material, and the resist R having a predetermined shape can be formed by exposing and developing the resist film formed on the entire surface of the oxide semiconductor film 4a.
- the oxide semiconductor film 4a is processed into a predetermined shape by etching the oxide semiconductor film 4a using the resist R as a mask.
- the island-shaped oxide semiconductor layer 4 can be formed at a position facing the gate electrode 2. Etching is, for example, wet etching.
- the resist R is removed. At this time, the surface of the oxide semiconductor layer 4 is exposed by removing the resist R.
- an insulating layer 5 such as a silicon oxide film is formed on the gate insulating layer 3 so as to cover the oxide semiconductor layer 4.
- a contact hole is formed in the insulating layer 5, a metal film is formed and etched, thereby forming a source electrode 6S and a drain electrode 6D.
- an insulating layer 7A is formed on the insulating layer 5 so as to cover the source electrode 6S and the drain electrode 6D.
- a first insulating film 71A, a second insulating film 72A, and a third insulating film 73A are sequentially formed.
- a silicon oxide film is formed as the first insulating film 71A
- an aluminum oxide film is formed as the second insulating film 72A
- a silicon nitride film is formed as the third insulating film 73A.
- the TFT can be manufactured in this way, but in the process of processing the oxide semiconductor film 4a in FIG. 2, the waiting time from the exposure of the oxide semiconductor layer 4 to the covering of the insulating layer 5 Exists. During standby, the film is left in the atmosphere, and the film surface during production is exposed to the atmosphere.
- the present inventor considered that this standby time might affect the threshold voltage (Vth) of the TFT, and conducted an experiment on the dependence between the standby time and the threshold voltage of the TFT. The result is shown in FIG.
- FIG. 3 shows data relating to the TFT manufactured by the method shown in FIG. 2. The waiting time until the resist R is removed and the oxide semiconductor layer 4 is exposed and covered with the insulating layer 5 and the threshold voltage of the TFT are shown. Shows the relationship.
- an IGZO film is used as the oxide semiconductor film 4a.
- the resist R is removed to expose the oxide semiconductor layer 4 (FIG. 2E), and then the oxide semiconductor layer 4 is insulated. It has been found that there is a correlation between the waiting time until coating with the layer 5 and the threshold voltage of the TFT using the oxide semiconductor layer 4.
- the standby time the surface exposure time of the oxide semiconductor layer 4
- the threshold voltage Vth
- An increase in the threshold voltage of the TFT causes a decrease in display uniformity and reliability of the display panel, and also causes an increase in power consumption.
- the inventor of the present application has adjusted the threshold value of the TFT by adjusting the amount of hydrogen contained in the third insulating film 73A (SiN) of the insulating layer 7A in FIG. An experiment was conducted on the third insulating film 73A (SiN) on the assumption that the voltage could be controlled.
- the oxide semiconductor layer 4 is covered with the insulating layer 5 after the oxide semiconductor layer 4 is exposed as shown in FIG.
- the relationship between the waiting time until the TFT and the threshold voltage of the TFT using the oxide semiconductor layer 4 was examined.
- an IGZO film is used as the oxide semiconductor film 4a.
- FIG. 4A shows the deposition conditions for the three types of third insulating films 73A used at that time.
- Samples 1, 2 and 3 were all silicon nitride films (SiN) and were formed using a parallel plate RF plasma CVD apparatus.
- the film formation conditions (numerical values) shown in FIG. 4A are standardized with the film formation conditions of Sample 1 as “1”, and the film formation conditions of Samples 1, 2, and 3 are shown as relative ratios. Note that the film formation temperature is the same in all cases.
- the film forming conditions of sample 1 are conditions for forming a silicon nitride film having a high stress and low hydrogen film quality
- the film forming conditions of sample 2 are low stress and high hydrogen.
- This is a condition for forming a silicon nitride film having a film quality
- the film forming condition for the sample 3 is a condition for forming a silicon nitride film having a low stress and a low hydrogen film quality.
- the high hydrogen film (sample 2) can be produced by increasing the SiH 4 / NH 3 flow rate ratio, the RF power, and the pressure with respect to the low hydrogen film (sample 1, sample 3).
- FIG. 4B shows physical property values of three types of third insulating films 73A (SiN) of Sample 1, Sample 2, and Sample 3 obtained under the film forming conditions of FIG. 4A.
- Si—H is a bond between silicon and hydrogen (Si—H bond), and the value indicates the concentration of Si—H bond in the silicon nitride film.
- N—H is a bond between nitrogen and hydrogen (N—H bond), and the value indicates the concentration of the N—H bond in the silicon nitride film.
- Si—H and N—H were measured by a Fourier transform infrared spectrophotometer (FTIR: Fourier Transform Infrared Spectroscopy).
- the high-hydrogen silicon nitride (sample 2) has a higher concentration of Si—H bonds in the silicon nitride film, compared to the low-hydrogen silicon nitride (sample 1, sample 3). It can be seen that the ratio of the Si—H bond concentration to the N—H bond concentration (Si—H / NH) is large.
- high-hydrogen silicon nitride (sample 2) has a Si—H / N—H ratio five times or more that of low-hydrogen silicon nitride (sample 1 and sample 3).
- FIG. 5 shows a waiting time from when the resist R is removed and the oxide semiconductor layer 4 is exposed to covering with the insulating layer 5 with respect to the TFTs manufactured using the samples 1, 2 and 3. The relationship with the threshold voltage of TFT is shown.
- the threshold voltage of the TFT increases as the standby time increases for silicon nitride (sample 1) having a low hydrogen and high stress film quality. It can also be seen that the threshold voltage of the TFT increases as the standby time increases for silicon nitride (sample 3) having a low hydrogen and low stress film quality. In other words, regardless of the magnitude of the film stress, it is considered that the threshold voltage of the TFT of low hydrogen silicon nitride increases as the standby time increases.
- the threshold voltage of the TFT does not change much even when the standby time is increased. Rather, the threshold voltage of the TFT is increased as the standby time is increased. It can be seen that it gradually decreases and then saturates.
- the threshold voltage of the third insulating film 73 which is a silicon nitride film, increases as the standby time increases in the case of low hydrogen (Si—H / N—H ⁇ 0.1).
- Si—H / N—H > 0.4 it gradually decreases as the standby time increases and then saturates.
- FIG. 6A is a diagram for explaining hydrogen diffusion in the thin film transistor of Comparative Example 1.
- FIG. 6B is a diagram for explaining hydrogen diffusion in the thin film transistor according to the embodiment having the structure shown in FIG. 1.
- 6C is a diagram for explaining hydrogen diffusion in the thin film transistor of Comparative Example 2.
- the oxide semiconductor TFT when a silicon nitride film is used as a passivation film formed above the oxide semiconductor layer, a low-hydrogen silicon nitride film is usually used from the viewpoint of ensuring reliability. This is to prevent hydrogen contained in the silicon nitride film from entering the oxide semiconductor layer by a thermal process or the like and causing hydrogen damage to the oxide semiconductor layer.
- the threshold voltage of the TFT changes. In other words, hydrogen is likely to diffuse if there are many Si—H bonds in the silicon nitride film, and therefore it is generally considered that it is important to keep the Si—H bonds low. It is common sense.
- a low-hydrogen silicon nitride film has been used as the passivation film above the oxide semiconductor layer, and a hydrogen barrier film has been introduced between the silicon nitride film and the oxide semiconductor layer. It was.
- the oxide semiconductor layer 4 when the oxide semiconductor layer 4 is formed by etching the oxide semiconductor film, the oxide semiconductor layer 4 (IGZO film) immediately after the etching process (FIG. 2D) In, Ga, and Zn are bonded to oxygen at an equal ratio, and oxygen vacancies are generated at an equal ratio. That is, the oxide semiconductor layer 4 immediately after the etching process has a uniform film quality.
- Ga—O bond is stronger than the In—O bond and the Zn—O bond, so that the oxygen deficiency of Ga fills preferentially over In and Zn on the surface of the oxide semiconductor layer 4, and In and Zn This is probably because Ga—O bonds are increased on the surface of the oxide semiconductor layer 4 as a result of Ga depriving of oxygen.
- the bond energy of the Ga—O bond is 374 (kJmol ⁇ 1 ) and the bond energy of the In—O bond is 346 (kJmol ⁇ 1 ), but the bond energy of the Zn—O bond is 250 (kJmol ⁇ 1). ).
- the Ga excess layer 41 is locally generated on the surface of the oxide semiconductor layer 4.
- the composition of the oxide semiconductor layer 4 is changed, and the threshold voltage (Vth) of the TFT is positively shifted.
- Vth threshold voltage
- the inventor of the present application has increased the waiting time (the surface exposure time of the oxide semiconductor layer 4) by making the upper insulating film (silicon nitride film) of the hydrogen barrier film a high hydrogen film. It was found that the increase in the threshold voltage accompanying the above can be mitigated.
- the threshold voltage of the TFT can be controlled by controlling the amount of hydrogen contained in the insulating film. I found it. The principle will be described with reference to FIG. 6B.
- the third insulating film 73 an insulating film containing hydrogen in an amount that can pass through the second insulating film 72 that is a hydrogen barrier film is used. Yes. That is, the third insulating film 73 has such an amount that hydrogen blocked by the second insulating film 72 (hydrogen barrier film) and hydrogen that passes through the second insulating film 72 (hydrogen barrier film) exist. Contains hydrogen.
- the second insulating film 72 a silicon nitride film formed under the film forming conditions of the sample 2 in FIG. 4A is used. Therefore, the second insulating film 72 is a high-hydrogen, low-stress silicon nitride film (Si—H / N—H> 0.4) having the physical property values of the sample 2 in FIG. 4B.
- a low-hydrogen silicon nitride film Si—H / N—H ⁇ 0.1
- Si—H / N—H silicon nitride film of high hydrogen
- an increase in threshold fluctuation accompanying an increase in the surface exposure time (standby time) of the oxide semiconductor layer 4 can be suppressed.
- the second insulating film 72 (aluminum oxide film) that is a hydrogen barrier film is not formed in the thin film transistor in this embodiment is also conceivable.
- the third insulating film 73 silicon nitride film
- the excess oxide of the Ga excess layer 41 is caused by a large amount of hydrogen diffused all at once without being blocked.
- the oxide in the original oxide semiconductor layer 4 may be reduced. As a result, the oxide semiconductor layer 4 becomes conductive, and there is a possibility that the original operation as a TFT cannot be obtained.
- a hydrogen barrier film (second insulating film 72) having a hydrogen barrier property is provided between the oxide semiconductor layer 4 and the insulating film containing hydrogen (third insulating film 73).
- a hydrogen barrier film is inserted between the oxide semiconductor layer 4 and the insulating film (third insulating film 73). Therefore, it is preferable to suppress excessive diffusion of hydrogen from the insulating film (third insulating film 73).
- the inventors of the present application have found that the threshold voltage of the TFT can be controlled by controlling the amount of hydrogen contained in the insulating film (third insulating film 73).
- FIGS. 7A to 7J are cross-sectional views of each step in the method of manufacturing the thin film transistor according to the embodiment.
- a substrate 1 is prepared, and a gate electrode 2 having a predetermined shape is formed above the substrate 1.
- a glass substrate is prepared as the substrate 1
- a gate metal film is formed on the glass substrate by a sputtering method, and the gate metal film is processed using a photolithography method and a wet etching method, whereby a predetermined shape is obtained.
- the gate electrode 2 is formed.
- an undercoat layer is formed on the surface of the substrate 1, the gate electrode 2 is formed on the undercoat layer.
- a gate insulating layer 3 is formed on the gate electrode 2.
- a film is formed on the entire upper surface of the substrate 1 so as to cover the gate electrode 2.
- the gate insulating layer 3 is, for example, a silicon oxide film.
- a silicon oxide film can be formed by a plasma CVD method using silane gas (SiH 4 ) and nitrous oxide gas (N 2 O) as an introduction gas.
- the gate insulating layer 3 may be a single layer film or a laminated film.
- a stacked film in which a silicon nitride film and a silicon oxide film are sequentially formed can be used as the gate insulating layer 3.
- the silicon nitride film can be formed by a plasma CVD method using, for example, silane gas (SiH 4 ), ammonia gas (NH 3 ), and nitrogen gas (N 2 ) as introduction gases.
- the oxide semiconductor film 4 a is formed over the substrate 1. Specifically, the oxide semiconductor film 4 a is formed over the gate insulating layer 3.
- the oxide semiconductor film 4a is an IGZO film made of, for example, InGaZnO X and can be formed by a sputtering method.
- argon (Ar) gas as an inert gas flows into the vacuum chamber and a gas containing oxygen (O 2 ) as a reactive gas flows, and a voltage with a predetermined power density is applied to the target material.
- the oxide semiconductor film 4a made of an amorphous IGZO film can be formed on the gate insulating layer 3.
- the oxide semiconductor film 4a is patterned to form the oxide semiconductor layer 4 having a predetermined shape.
- the patterning of the oxide semiconductor film 4a can be performed using a photolithography method and an etching method.
- a resist R having a predetermined shape is formed on the oxide semiconductor film 4a.
- the resist R is, for example, a photosensitive resin material, and the resist R having a predetermined shape can be formed by exposing and developing the resist film formed on the entire surface of the oxide semiconductor film 4a. Specifically, the resist film is exposed and developed so as to leave the resist R at least at a position facing the gate electrode 2.
- the oxide semiconductor film 4a is etched using the resist R as a mask. Accordingly, the oxide semiconductor film 4a in a region where the resist R is not formed is removed by etching, and the oxide semiconductor film 4a is processed, so that the oxide semiconductor layer 4 having a predetermined shape can be formed. Specifically, the island-shaped oxide semiconductor layer 4 is formed so as to include a position facing the gate electrode 2.
- Etching is, for example, wet etching.
- a chemical solution in which phosphoric acid (H 3 PO 4 ), nitric acid (HNO 3 ), acetic acid (CH 3 COOH), and water are mixed is used. Use it.
- the resist R is removed (peeled).
- the resist R can be removed with a stripping solution.
- the surface of the oxide semiconductor layer 4 is exposed by removing the resist R. Thereby, the oxide semiconductor layer 4 having a predetermined shape can be formed.
- an insulating layer 5 is formed on the oxide semiconductor layer 4.
- the insulating layer 5 is formed over the entire surface of the gate insulating layer 3 so as to cover the oxide semiconductor layer 4.
- the insulating layer 5 is, for example, a silicon oxide film.
- a silicon oxide film can be formed by a plasma CVD method using silane gas (SiH 4 ) and nitrous oxide gas (N 2 O) as an introduction gas.
- contact holes CH openings are formed in the insulating layer 5.
- the contact hole CH is formed by removing a part of the insulating layer 5 using a photolithography method and an etching method so that a part of the oxide semiconductor layer 4 is exposed.
- the contact hole CH can be formed in the silicon oxide film by a dry etching method using a reactive ion etching (RIE) method.
- RIE reactive ion etching
- carbon tetrafluoride (CF 4 ) and oxygen gas (O 2 ) can be used as the etching gas.
- the contact hole CH is formed over a region to be a source contact region and a drain contact region of the oxide semiconductor layer 4.
- a source electrode 6S and a drain electrode 6D having a predetermined shape are formed so as to be connected to the oxide semiconductor layer 4.
- a source / drain metal film is formed on the insulating layer 5 by a sputtering method so as to fill the contact hole CH of the insulating layer 5, and then the source / drain metal film is formed using a photolithography method and an etching method.
- a source electrode 6S and a drain electrode 6D having a predetermined shape can be formed.
- a metal film having a three-layer structure of a Mo film, a Cu film, and a CuMn film can be used.
- wet etching of a source / drain metal film made of a Mo film, a Cu film, and a CuMn film can be performed using, for example, a chemical solution in which a hydrogen peroxide solution (H 2 O 2 ) and an organic acid are mixed.
- the insulating layer 7 is formed on the substrate 1 on which the source electrode 6S and the drain electrode 6D are formed.
- an insulating layer 7 having a three-layer structure including a first insulating film 71, a second insulating film 72, and a third insulating film 73 is formed.
- the first insulating film 71 is a silicon oxide film
- the second insulating film 72 is an aluminum oxide film
- the third insulating film 73 is a silicon nitride film, and these are sequentially deposited. Yes.
- the first insulating film 71 which is a silicon oxide film, can be formed by, for example, plasma CVD.
- the second insulating film 72 which is an aluminum oxide film, is formed by sputtering, for example.
- an aluminum oxide film can be formed by performing sputtering using aluminum as a target and argon gas and oxygen gas as process gases. Note that aluminum oxide may be used as a target. In this case, argon gas is used as the process gas.
- the third insulating film 73 which is a silicon nitride film, can be formed by plasma CVD or the like, for example.
- a silicon nitride film is formed under the film formation conditions of the sample 2 in FIG. 4A.
- the third insulating film 73 is a high-hydrogen silicon nitride film, and contains at least hydrogen in an amount that can pass through the second insulating film 72 (aluminum oxide film).
- the thin film transistor 10 can be manufactured. After that, if necessary, a contact hole may be formed in the insulating layer 7 to form an electrode or a wiring, or a passivation film may be formed on the insulating layer 7. Further, heat treatment (annealing) may be performed at a temperature exceeding 290 ° C. in order to repair oxygen vacancies in the oxide semiconductor layer 4 and stabilize the characteristics of the oxide semiconductor layer 4.
- the oxide semiconductor layer 4 As described above, according to the thin film transistor 10 of the present embodiment, the oxide semiconductor layer 4, the insulating film (third insulating film 73), the oxide semiconductor layer 4 and the insulating film (third insulating film). And a hydrogen barrier film (second insulating film 72) formed between the insulating film (third insulating film 73) and the hydrogen barrier film (second insulating film 72). An amount of hydrogen that can permeate is included.
- the threshold voltage of the TFT is increased as the standby time (the surface exposure time of the oxide semiconductor layer 4) from when the resist R is removed and the oxide semiconductor layer 4 is exposed until it is covered with the insulating layer 5 increases. The increase can be suppressed. Therefore, the thin film transistor 10 having desired performance can be realized.
- the insulating film (third insulating film 73) is made of a compound containing silicon and nitrogen (for example, silicon nitride), and the insulating film (third insulating film 73).
- the ratio of the Si—H bond concentration to the N—H bond concentration in) is greater than 0.3. That is, the insulating film (third insulating film 73) is a high hydrogen film containing a large amount of hydrogen.
- an insulating film (third insulating film 73) containing hydrogen that can pass through the hydrogen barrier film (second insulating film 72) and modify the surface of the oxide semiconductor layer 4 can be obtained.
- the thin film transistor 10 having desired performance can be easily realized.
- the second insulating film 72 that is a hydrogen barrier film is an aluminum oxide film.
- the film density of the second insulating film 72 is aluminum oxide film is 2.80 g / cm 3 or more 3.25 g / cm 3 or less.
- FIG. 8 is a partially cutaway perspective view of the organic EL display device according to the embodiment.
- FIG. 9 is a perspective view illustrating an example of a pixel bank of the organic EL display device according to the embodiment.
- the above-described thin film transistor 10 can be used as a switching element or a driving element of an active matrix substrate in an organic EL display device.
- the organic EL display device 100 includes a TFT substrate (TFT array substrate) 110 on which a plurality of thin film transistors (not shown) are arranged, an anode 131 as a lower electrode, and an organic material. It is composed of a laminated structure of an EL layer 132 that is a light emitting layer and an organic EL element (light emitting portion) 130 that includes a cathode 133 that is a transparent upper electrode.
- the organic EL display device 100 in this embodiment is a top emission type, and the anode 131 is a reflective electrode.
- the organic EL display device 100 is not limited to the top emission type, and may be a bottom emission type.
- the TFT substrate 110 has a plurality of pixels 120 arranged in a matrix, and each pixel 120 is provided with a pixel circuit.
- the organic EL element 130 is formed corresponding to each of the plurality of pixels 120, and the light emission of each organic EL element 130 is controlled by a pixel circuit provided in each pixel 120.
- the organic EL element 130 is formed on an interlayer insulating film (planarization layer) formed so as to cover a plurality of thin film transistors.
- the organic EL element 130 has a configuration in which an EL layer 132 is disposed between the anode 131 and the cathode 133.
- a hole transport layer is further stacked between the anode 131 and the EL layer 132, and an electron transport layer is further stacked between the EL layer 132 and the cathode 133.
- another functional layer such as a hole injection layer or an electron injection layer may be provided between the anode 131 and the cathode 133.
- each pixel 120 is driven and controlled by each pixel circuit.
- the TFT substrate 110 includes a plurality of gate wirings (scanning lines) 140 arranged along the row direction of the pixels 120 and the column direction of the pixels 120 so as to intersect the gate wirings 140.
- a plurality of source wirings (signal wirings) 150 arranged along the lines and a plurality of power source wirings (not shown in FIG. 8) arranged in parallel with the source wirings 150 are formed.
- Each pixel 120 is partitioned by, for example, an orthogonal gate wiring 140 and a source wiring 150.
- the gate wiring 140 is connected to the gate electrode of the thin film transistor operating as a switching element included in each pixel circuit for each row.
- the source wiring 150 is connected to the source electrode of the thin film transistor operating as a switching element included in each pixel circuit for each column.
- the power supply wiring is connected to the drain electrode of the thin film transistor operating as a driving element included in each pixel circuit for each column.
- each pixel 120 of the organic EL display device 100 is composed of sub-pixels 120R, 120G, and 120B of three colors (red, green, and blue), and these sub-pixels 120R, 120G, and 120B. Are arranged in a matrix.
- the sub-pixels 120R, 120G, and 120B are separated from each other by the bank 121.
- the banks 121 are formed in a lattice shape so that the ridges extending in parallel to the gate wiring 140 and the ridges extending in parallel to the source wiring 150 intersect each other.
- Each of the portions surrounded by the protrusions (that is, the opening of the bank 121) and each of the sub-pixels 120R, 120G, and 120B have a one-to-one correspondence.
- the bank 121 is a pixel bank, but may be a line bank.
- the anode 131 is formed for each of the sub-pixels 120R, 120G, and 120B on the interlayer insulating film (flattening layer) on the TFT substrate 110 and in the opening of the bank 121.
- the EL layer 132 is formed for each of the sub-pixels 120R, 120G, and 120B on the anode 131 and in the opening of the bank 121.
- the transparent cathode 133 is continuously formed on the plurality of banks 121 so as to cover all the EL layers 132 (all the sub-pixels 120R, 120G, and 120B).
- the pixel circuit is provided for each of the sub-pixels 120R, 120G, and 120B, and each of the sub-pixels 120R, 120G, and 120B and the corresponding pixel circuit are electrically connected by a contact hole and a relay electrode. Yes.
- the sub-pixels 120R, 120G, and 120B have the same configuration except that the emission color of the EL layer 132 is different.
- FIG. 10 is an electric circuit diagram illustrating a configuration of a pixel circuit in the organic EL display device according to the embodiment. Note that the pixel circuit is not limited to the configuration shown in FIG.
- the pixel circuit in each pixel 120 includes a thin film transistor SwTr that operates as a switching element, a thin film transistor DrTr that operates as a drive element, and a capacitor C that stores data to be displayed on the corresponding pixel 120. Composed.
- the thin film transistor SwTr is a switching transistor for selecting the pixel 120
- the thin film transistor DrTr is a drive transistor for driving the organic EL element 130.
- the thin film transistor SwTr includes a gate electrode G1 connected to the gate wiring 140, a source electrode S1 connected to the source wiring 150, a drain electrode D1 connected to the capacitor C and the gate electrode G2 of the thin film transistor DrTr, and a channel layer (FIG. Not shown).
- a predetermined voltage is applied to the connected gate wiring 140 and source wiring 150
- the voltage applied to the source wiring 150 is stored in the capacitor C as a data voltage.
- the thin film transistor DrTr includes a gate electrode G2 connected to the drain electrode D1 of the thin film transistor SwTr and the capacitor C, a drain electrode D2 connected to the power supply wiring 160 and the capacitor C, and a source electrode connected to the anode 131 of the organic EL element 130. It is comprised by S2 and a semiconductor film (not shown).
- the thin film transistor DrTr supplies a current corresponding to the data voltage held by the capacitor C from the power supply wiring 160 to the anode 131 of the organic EL element 130 through the source electrode S2. Thereby, in the organic EL element 130, a drive current flows from the anode 131 to the cathode 133, and the EL layer 132 emits light.
- the organic EL display device 100 having the above configuration employs an active matrix system in which display control is performed for each pixel 120 located at the intersection of the gate wiring 140 and the source wiring 150. Thereby, the corresponding organic EL element 130 selectively emits light by the thin film transistors SwTr and DrTr of each pixel 120 (each sub-pixel 120R, 120G, 120B), and a desired image is displayed.
- the thin film transistor 10 in the above embodiment is used in the organic EL display device 100 in the present embodiment, a display device having excellent display performance can be realized.
- the insulating layer 7 has a three-layer structure, but without forming the first insulating film 71, an aluminum oxide film (lower layer) and silicon nitride are formed from the oxide semiconductor layer 4 side. It is good also as a layer structure which laminated
- the oxide semiconductor film 4a and the oxide semiconductor layer 4 are oxide semiconductors (in particular, IGZO films) including at least one of In, Ga, and Zn.
- the present invention is not limited to this. Absent.
- an ISO film made of an oxide semiconductor (In—Si—O) containing indium (In) and silicon (Si), indium (In), and tungsten (W ) Containing an oxide semiconductor (In—W—O), an oxide semiconductor in which Zn (zinc) is further added to In and W (In—W—Zn—O), and the like.
- the thin film transistor 10 is a bottom gate type, but the technology of the present disclosure can also be applied to a top gate type thin film transistor.
- the thin film transistor 10 is a channel etching stopper type (channel protection type), but the technique of the present disclosure can also be applied to a channel etching type thin film transistor.
- the thin film transistor in the above embodiment can also be applied to another display device such as a liquid crystal display device.
- the display device can be used as a flat panel display.
- a display device such as an organic EL display device can be used as a display panel of any electronic device such as a television set, a personal computer, or a mobile phone.
- it is suitable for a large-screen and high-definition display device.
- the technique disclosed herein can be widely used in a thin film transistor using an oxide semiconductor, a manufacturing method thereof, a display device such as an organic EL display device using the thin film transistor, and the like.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
This thin film semiconductor device comprises an oxide semiconductor layer (4), an insulating film (a third insulating film (73)), and a hydrogen barrier film (a second insulating film (72)) that is formed between the oxide semiconductor layer (4) and the insulating film and has hydrogen barrier properties that suppress permeation of hydrogen. The insulating film contains such an amount of hydrogen that can permeate through the hydrogen barrier film.
Description
本開示は、薄膜半導体装置、有機EL表示装置及び薄膜半導体装置の製造方法に関し、特に、酸化物半導体層を有する薄膜トランジスタ(TFT:Thin Film Transistor)、この薄膜トランジスタの製造方法及びこの薄膜トランジスタを用いた有機EL表示装置に関する。
The present disclosure relates to a thin film semiconductor device, an organic EL display device, and a method for manufacturing a thin film semiconductor device, and in particular, a thin film transistor (TFT: Thin Film Transistor) having an oxide semiconductor layer, a method for manufacturing the thin film transistor, and an organic film using the thin film transistor The present invention relates to an EL display device.
液晶表示装置や有機EL(Electro Luminescence)表示装置等のアクティブマトリクス方式の表示装置では、スイッチング素子又は駆動素子としてTFTが形成されたTFT基板が用いられる。例えば、特許文献1には、TFT基板を用いたアクティブマトリクス方式の有機EL表示装置が開示されている。
In an active matrix display device such as a liquid crystal display device or an organic EL (Electro Luminescence) display device, a TFT substrate on which TFTs are formed as switching elements or driving elements is used. For example, Patent Document 1 discloses an active matrix organic EL display device using a TFT substrate.
TFTのチャネル層は、ゲート電極に印加される電圧によってキャリアの移動が制御されるチャネル領域を有する。チャネル層の材料としては、シリコン等の種々の半導体材料が検討されている。
The channel layer of the TFT has a channel region in which carrier movement is controlled by a voltage applied to the gate electrode. As a material for the channel layer, various semiconductor materials such as silicon have been studied.
近年、透明アモルファス酸化物半導体(TAOS:Transparent Amorphous Oxide Semiconductor)等の酸化物半導体をチャネル層に用いた酸化物半導体TFTの開発が進められている。例えば、インジウム(In)、ガリウム(Ga)及び亜鉛(Zn)の金属酸化物(IGZO)からなるTAOSをチャネル層に用いた酸化物半導体TFTが実用化されている。
In recent years, development of an oxide semiconductor TFT using an oxide semiconductor such as a transparent amorphous oxide semiconductor (TAOS: Transparent Amorphous Oxide Semiconductor) as a channel layer has been promoted. For example, an oxide semiconductor TFT using TAOS made of a metal oxide (IGZO) of indium (In), gallium (Ga), and zinc (Zn) as a channel layer has been put into practical use.
しかしながら、チャネル層が酸化物半導体によって構成されたTFTでは、所望の性能を得ることが難しいという課題がある。
However, a TFT having a channel layer made of an oxide semiconductor has a problem that it is difficult to obtain desired performance.
本開示の技術は、所望の性能を有する薄膜半導体装置、有機EL表示装置及び薄膜半導体装置の製造方法を提供することを目的とする。
It is an object of the technology of the present disclosure to provide a thin film semiconductor device, an organic EL display device, and a thin film semiconductor device manufacturing method having desired performance.
上記目的を達成するために、薄膜半導体装置の一態様は、酸化物半導体層と、絶縁膜と、前記酸化物半導体層と前記絶縁膜との間に形成された、水素の透過を抑制する水素バリア性を有する水素バリア膜とを有し、前記絶縁膜には、前記水素バリア膜を透過することができる量の水素が含まれていることを特徴とする。
In order to achieve the above object, one embodiment of a thin film semiconductor device includes an oxide semiconductor layer, an insulating film, and hydrogen that is formed between the oxide semiconductor layer and the insulating film and suppresses permeation of hydrogen. A hydrogen barrier film having a barrier property, and the insulating film contains hydrogen in an amount capable of passing through the hydrogen barrier film.
また、薄膜半導体装置の製造方法の一態様は、酸化物半導体層を形成する工程と、絶縁膜を成膜する工程と、前記酸化物半導体層と前記絶縁膜との間に、水素の透過を抑制する水素バリア性を有する水素バリア膜を成膜する工程とを有し、前記絶縁膜には、前記水素バリア膜を透過することができる量の水素が含まれていることを特徴とする。
One embodiment of a method for manufacturing a thin film semiconductor device includes a step of forming an oxide semiconductor layer, a step of forming an insulating film, and transmitting hydrogen between the oxide semiconductor layer and the insulating film. And a step of forming a hydrogen barrier film having a hydrogen barrier property, wherein the insulating film contains an amount of hydrogen that can pass through the hydrogen barrier film.
所望の性能を有する薄膜半導体装置を実現できる。
A thin film semiconductor device having desired performance can be realized.
以下、本開示の一実施の形態について、図面を用いて説明する。なお、以下に説明する実施の形態は、いずれも本開示の好ましい一具体例を示すものである。したがって、以下の実施の形態で示される、数値、形状、材料、構成要素、構成要素の配置位置及び接続形態、工程(ステップ)、工程の順序等は、一例であって本開示を限定する主旨ではない。よって、以下の実施の形態における構成要素のうち、本開示の最上位概念を示す独立請求項に記載されていない構成要素については、任意の構成要素として説明される。
Hereinafter, an embodiment of the present disclosure will be described with reference to the drawings. Note that each of the embodiments described below shows a preferred specific example of the present disclosure. Accordingly, the numerical values, shapes, materials, components, arrangement positions and connection forms of components, steps (steps), order of steps, and the like shown in the following embodiments are merely examples and are intended to limit the present disclosure. is not. Therefore, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims indicating the highest concept of the present disclosure are described as arbitrary constituent elements.
なお、各図は、模式図であり、必ずしも厳密に図示されたものではない。また、各図において、実質的に同一の構成に対しては同一の符号を付しており、重複する説明は省略又は簡略化する。
Each figure is a schematic diagram and is not necessarily shown strictly. Moreover, in each figure, the same code | symbol is attached | subjected to the substantially same structure, The overlapping description is abbreviate | omitted or simplified.
(実施の形態)
以下の実施の形態では、酸化物半導体層を有する薄膜半導体装置の一例として、酸化物半導体層をチャネル層とする薄膜トランジスタについて説明する。 (Embodiment)
In the following embodiments, a thin film transistor including an oxide semiconductor layer as a channel layer will be described as an example of a thin film semiconductor device including an oxide semiconductor layer.
以下の実施の形態では、酸化物半導体層を有する薄膜半導体装置の一例として、酸化物半導体層をチャネル層とする薄膜トランジスタについて説明する。 (Embodiment)
In the following embodiments, a thin film transistor including an oxide semiconductor layer as a channel layer will be described as an example of a thin film semiconductor device including an oxide semiconductor layer.
[薄膜トランジスタの構成]
まず、実施の形態に係る薄膜トランジスタ10の構成について、図1を用いて説明する。図1は、実施の形態に係る薄膜トランジスタの断面図である。 [Configuration of thin film transistor]
First, the structure of thethin film transistor 10 according to the embodiment will be described with reference to FIG. FIG. 1 is a cross-sectional view of a thin film transistor according to an embodiment.
まず、実施の形態に係る薄膜トランジスタ10の構成について、図1を用いて説明する。図1は、実施の形態に係る薄膜トランジスタの断面図である。 [Configuration of thin film transistor]
First, the structure of the
図1に示すように、薄膜トランジスタ10は、酸化物半導体をチャネル層とする酸化物半導体TFTであって、基板1と、ゲート電極2と、ゲート絶縁層3と、酸化物半導体層4と、絶縁層5と、ソース電極6S及びドレイン電極6Dと、絶縁層7とを備える。本実施の形態における薄膜トランジスタ10は、チャネル保護型でボトムゲート型のTFTであり、また、トップコンタクト構造が採用されている。
As shown in FIG. 1, the thin film transistor 10 is an oxide semiconductor TFT having an oxide semiconductor as a channel layer, and includes a substrate 1, a gate electrode 2, a gate insulating layer 3, an oxide semiconductor layer 4, and an insulating layer. A layer 5, a source electrode 6 </ b> S and a drain electrode 6 </ b> D, and an insulating layer 7 are provided. The thin film transistor 10 in this embodiment is a channel protection type bottom gate type TFT and adopts a top contact structure.
以下、本実施の形態に係る薄膜トランジスタ10の各構成要素について詳述する。
Hereinafter, each component of the thin film transistor 10 according to the present embodiment will be described in detail.
基板1は、絶縁材料からなる絶縁基板であり、例えば、石英ガラス、無アルカリガラス又は高耐熱性ガラス等のガラス材料で構成されるガラス基板である。基板1は、例えば、G8ガラス基板である。
The substrate 1 is an insulating substrate made of an insulating material, for example, a glass substrate made of a glass material such as quartz glass, non-alkali glass, or high heat resistant glass. The substrate 1 is, for example, a G8 glass substrate.
なお、基板1は、ガラス基板に限らず、樹脂基板等であってもよい。また、基板1は、リジッド基板ではなく、フレキシブル基板であってもよい。また、基板1の表面にアンダーコート層を形成してもよい。
The substrate 1 is not limited to a glass substrate but may be a resin substrate or the like. The substrate 1 may be a flexible substrate instead of a rigid substrate. Further, an undercoat layer may be formed on the surface of the substrate 1.
ゲート電極2は、金属等の導電性材料又はその合金等からなる導電膜の単層構造又は多層構造の電極であり、基板1の上方に所定形状で形成される。ゲート電極2の膜厚は、例えば、20nm~500nm程度である。
The gate electrode 2 is an electrode having a single layer structure or a multilayer structure of a conductive film made of a conductive material such as metal or an alloy thereof, and is formed in a predetermined shape above the substrate 1. The film thickness of the gate electrode 2 is, for example, about 20 nm to 500 nm.
ゲート電極2の材料としては、例えば、モリブデン、アルミニウム、銅、タングステン、チタン、マンガン、クロム、タンタル、ニオブ、銀、金、プラチナ、パラジウム、インジウム、ニッケル、ネオジム等の金属、又は、これらの中から選ばれる金属の合金(例えばモリブデンタングステン)が用いられる。
Examples of the material of the gate electrode 2 include molybdenum, aluminum, copper, tungsten, titanium, manganese, chromium, tantalum, niobium, silver, gold, platinum, palladium, indium, nickel, neodymium, or the like. An alloy of a metal selected from (for example, molybdenum tungsten) is used.
なお、ゲート電極2の材料は、これらに限るものではなく、酸化インジウムスズ(ITO)、アルミニウムドープ酸化亜鉛(AZO)、ガリウムドープ酸化亜鉛(GZO)等の導電性金属酸化物、又は、ポリチオフェンやポリアセチレン等の導電性高分子材料等を用いることもできる。また、膜の密着性を高めるために、酸化物との密着性が良い金属として、例えばチタン、アルミニウム、金等を用いて、これらの金属を挟んだ積層体をゲート電極2として用いることもできる。
The material of the gate electrode 2 is not limited to these, and conductive metal oxides such as indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), and gallium-doped zinc oxide (GZO), polythiophene, A conductive polymer material such as polyacetylene can also be used. In addition, in order to improve the adhesion of the film, for example, titanium, aluminum, gold, or the like can be used as the gate electrode 2 as a metal having good adhesion to the oxide, and a sandwich between these metals is used. .
ゲート絶縁層(ゲート絶縁膜)3は、ゲート電極2と酸化物半導体層4との間に配置される。本実施の形態において、ゲート絶縁層3は、ゲート電極2の上方に位置するように配置される。例えば、ゲート絶縁層3は、ゲート電極2が形成された基板1上の全面にゲート電極2を覆うように成膜される。ゲート絶縁層3の膜厚は、例えば50nm~300nm程度である。
The gate insulating layer (gate insulating film) 3 is disposed between the gate electrode 2 and the oxide semiconductor layer 4. In the present embodiment, the gate insulating layer 3 is disposed so as to be located above the gate electrode 2. For example, the gate insulating layer 3 is formed so as to cover the gate electrode 2 over the entire surface of the substrate 1 on which the gate electrode 2 is formed. The film thickness of the gate insulating layer 3 is, for example, about 50 nm to 300 nm.
ゲート絶縁層3は、電気絶縁性を有する材料から構成され、一例として、酸化シリコン膜、窒化シリコン膜、酸窒化シリコン膜、酸化アルミニウム膜、酸化タンタル膜又は酸化ハフニウム膜等の単層膜、あるいは、これらの膜を複数積層した積層膜である。
The gate insulating layer 3 is made of a material having electrical insulation, and as an example, a single layer film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, a tantalum oxide film, or a hafnium oxide film, or A laminated film in which a plurality of these films are laminated.
酸化物半導体層4は、ゲート電極2の上方において、ゲート絶縁層3上に所定形状で形成される。例えば、酸化物半導体層4は、ゲート絶縁層3上に島状に形成される。本実施の形態において、酸化物半導体層4は、薄膜トランジスタ10のチャネル層である。つまり、酸化物半導体層4は、ゲート絶縁層3を挟んでゲート電極2と対向するチャネル領域を含む半導体層である。酸化物半導体層4の膜厚は、例えば、10nm~200nmである。
The oxide semiconductor layer 4 is formed in a predetermined shape on the gate insulating layer 3 above the gate electrode 2. For example, the oxide semiconductor layer 4 is formed in an island shape over the gate insulating layer 3. In this embodiment, the oxide semiconductor layer 4 is a channel layer of the thin film transistor 10. That is, the oxide semiconductor layer 4 is a semiconductor layer including a channel region facing the gate electrode 2 with the gate insulating layer 3 interposed therebetween. The film thickness of the oxide semiconductor layer 4 is, for example, 10 nm to 200 nm.
酸化物半導体層4は、酸化物半導体によって構成される。酸化物半導体層4は、例えば、インジウム(In)、ガリウム(Ga)及び亜鉛(Zn)のうち少なくとも1種を含む酸化物半導体によって構成され、具体的には、酸化亜鉛(ZnOx)、酸化インジウムガリウム(InGaOx)、又は、酸化インジウムガリウム亜鉛(InGaZnOx)等である。本実施の形態において、酸化物半導体層4は、透明アモルファス酸化物半導体(TAOS)であり、In、Ga及びZnの金属酸化物であるInGaZnOxからなるIGZO膜である。
The oxide semiconductor layer 4 is composed of an oxide semiconductor. The oxide semiconductor layer 4 is made of, for example, an oxide semiconductor containing at least one of indium (In), gallium (Ga), and zinc (Zn), specifically zinc oxide (ZnO x ), oxide Indium gallium (InGaO x ), indium gallium zinc oxide (InGaZnO x ), or the like. In this embodiment, the oxide semiconductor layer 4 is a transparent amorphous oxide semiconductor (TAOS), and is an IGZO film made of InGaZnO x which is a metal oxide of In, Ga, and Zn.
InGaZnOXの酸化物半導体は、例えば、InGaO3(ZnO)4組成を有する多結晶焼結体をターゲットとして、スパッタリング法やレーザー蒸着法等の気相成膜法により成膜することができる。
The oxide semiconductor of InGaZnO X can be formed, for example, by a vapor deposition method such as a sputtering method or a laser deposition method using a polycrystalline sintered body having an InGaO 3 (ZnO) 4 composition as a target.
絶縁層5(第1絶縁層)は、酸化物半導体層4上に配置される。具体的には、絶縁層5は、酸化物半導体層4を覆うようにゲート絶縁層3上に成膜される。本実施の形態において、絶縁層5は、酸化物半導体層4のチャネル領域を保護する保護膜(チャネル保護層)として機能する。また、本実施の形態において、絶縁層5は、基板1の上方全面に形成された層間絶縁膜である。絶縁層5の膜厚は、例えば、50nm~500nm程度である。
The insulating layer 5 (first insulating layer) is disposed on the oxide semiconductor layer 4. Specifically, the insulating layer 5 is formed over the gate insulating layer 3 so as to cover the oxide semiconductor layer 4. In this embodiment, the insulating layer 5 functions as a protective film (channel protective layer) that protects the channel region of the oxide semiconductor layer 4. In the present embodiment, the insulating layer 5 is an interlayer insulating film formed on the entire upper surface of the substrate 1. The film thickness of the insulating layer 5 is, for example, about 50 nm to 500 nm.
絶縁層5は、電気絶縁性を有する材料から構成され、一例として、酸化シリコン膜、窒化シリコン膜、酸窒化シリコン膜、酸化アルミニウム膜の単層膜、あるいは、これらの酸化膜の積層膜である。
The insulating layer 5 is made of a material having electrical insulation properties, and is, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a single layer film of an aluminum oxide film, or a laminated film of these oxide films. .
また、絶縁層5には、当該絶縁層5の一部を貫通するように開口部(コンタクトホール)が形成されている。この絶縁層5の開口部を介して、酸化物半導体層4とソース電極6S及びドレイン電極6Dとが接続されている。
In addition, an opening (contact hole) is formed in the insulating layer 5 so as to penetrate a part of the insulating layer 5. The oxide semiconductor layer 4 is connected to the source electrode 6S and the drain electrode 6D through the opening of the insulating layer 5.
ソース電極6S及びドレイン電極6Dは、絶縁層5の上方に少なくとも一部が位置し、かつ、酸化物半導体層4と接続されるように所定形状で形成される。具体的には、ソース電極6S及びドレイン電極6Dは、絶縁層5上においては基板1に水平な方向(基板水平方向)に離間して互いに対向して配置されており、かつ、絶縁層5に形成された開口部を介して酸化物半導体層4に接続されている。ソース電極6S及びドレイン電極6Dの膜厚は、例えば100nm~500nm程度である。
The source electrode 6 </ b> S and the drain electrode 6 </ b> D are formed in a predetermined shape so that at least a part thereof is located above the insulating layer 5 and is connected to the oxide semiconductor layer 4. Specifically, the source electrode 6S and the drain electrode 6D are disposed on the insulating layer 5 so as to be spaced apart from each other in the horizontal direction (substrate horizontal direction) with respect to the substrate 1 and opposed to each other. It is connected to the oxide semiconductor layer 4 through the formed opening. The film thickness of the source electrode 6S and the drain electrode 6D is, for example, about 100 nm to 500 nm.
ソース電極6S及びドレイン電極6Dは、導電性材料又はその合金等からなる導電膜の単層構造又は多層構造の電極である。ソース電極6S及びドレイン電極6Dの材料には、例えば、アルミニウム、タンタル、モリブデン、タングステン、銀、銅、チタン又はクロム等が用いられる。一例として、ソース電極6S及びドレイン電極6Dは、下から順に、モリブデン膜(Mo膜)、銅膜(Cu膜)及び銅マンガン合金膜(CuMn膜)が形成された3層構造の電極である。このように、ソース電極6S及びドレイン電極6Dとして低抵抗材料であるCu膜を用いることによって、ソース電極6S及びドレイン電極6Dの低抵抗化を図ることができるとともに、ソース電極6S及びドレイン電極6Dと同層の配線の低抵抗化を図ることができる。
The source electrode 6S and the drain electrode 6D are electrodes having a single layer structure or a multilayer structure of a conductive film made of a conductive material or an alloy thereof. As the material of the source electrode 6S and the drain electrode 6D, for example, aluminum, tantalum, molybdenum, tungsten, silver, copper, titanium, or chromium is used. As an example, the source electrode 6S and the drain electrode 6D are electrodes having a three-layer structure in which a molybdenum film (Mo film), a copper film (Cu film), and a copper manganese alloy film (CuMn film) are formed in order from the bottom. Thus, by using the Cu film which is a low resistance material as the source electrode 6S and the drain electrode 6D, the resistance of the source electrode 6S and the drain electrode 6D can be reduced, and the source electrode 6S and the drain electrode 6D The resistance of the wiring in the same layer can be reduced.
絶縁層7(第2絶縁層)は、パッシベーション膜であり、ソース電極6S及びドレイン電極6Dを覆うように絶縁層5上に成膜される。本実施の形態において、絶縁層7は、三層構造であり、第1の絶縁膜71、第2の絶縁膜72及び第3の絶縁膜73によって構成されている。
The insulating layer 7 (second insulating layer) is a passivation film, and is formed on the insulating layer 5 so as to cover the source electrode 6S and the drain electrode 6D. In the present embodiment, the insulating layer 7 has a three-layer structure, and includes a first insulating film 71, a second insulating film 72, and a third insulating film 73.
第1の絶縁膜71は、ソース電極6S及びドレイン電極6Dを覆うように絶縁層5上に形成される。第1の絶縁膜71は、ソース電極6S及びドレイン電極6Dとの密着性がよく、膜中に水素の含有量が少ない膜であるとよい。また、絶縁層7を層間絶縁膜として用いて当該絶縁層7にコンタクトホールを形成してソース電極6S及びドレイン電極6Dに配線や電極等を接続する場合もあるので、第1の絶縁膜71は、さらに、エッチングによる加工性を確保できる膜であるとよい。そのため、第1の絶縁膜71としては、例えば、酸化シリコン膜を用いるとよい。第1の絶縁膜71の膜厚は、例えば50nm~500nm程度である。
The first insulating film 71 is formed on the insulating layer 5 so as to cover the source electrode 6S and the drain electrode 6D. The first insulating film 71 is preferably a film having good adhesion to the source electrode 6S and the drain electrode 6D and having a low hydrogen content in the film. In some cases, the insulating layer 7 is used as an interlayer insulating film, contact holes are formed in the insulating layer 7 and wirings, electrodes, and the like are connected to the source electrode 6S and the drain electrode 6D. Furthermore, it is preferable that the film can ensure workability by etching. Therefore, for example, a silicon oxide film is preferably used as the first insulating film 71. The film thickness of the first insulating film 71 is, for example, about 50 nm to 500 nm.
第2の絶縁膜72は、酸化物半導体層4と第3の絶縁膜73との間に形成される。本実施の形態において、第2の絶縁膜72は、第1の絶縁膜71の上に成膜される。また、第2の絶縁膜72は、水素の透過を抑制する水素バリア性を有する水素バリア膜である。さらに、第2の絶縁膜72は、第1の絶縁膜71と同様に、エッチングによる加工性を確保できる膜であるとよい。そのため、第2の絶縁膜72としては、例えば、酸化アルミニウム膜(アルミナ膜)を用いるとよい。
The second insulating film 72 is formed between the oxide semiconductor layer 4 and the third insulating film 73. In the present embodiment, the second insulating film 72 is formed over the first insulating film 71. The second insulating film 72 is a hydrogen barrier film having a hydrogen barrier property that suppresses permeation of hydrogen. Further, like the first insulating film 71, the second insulating film 72 is preferably a film that can ensure workability by etching. Therefore, for example, an aluminum oxide film (alumina film) is preferably used as the second insulating film 72.
本実施の形態における第2の絶縁膜72として用いられる酸化アルミニウム膜は、膜密度が比較的に小さい膜質(つまり、膜質が粗)であり、酸化アルミニウム膜を透過しようとする水素は、一部が遮断され、一部が透過する。つまり、第2の絶縁膜72は、水素を完全に遮断するのではなく水素を透過させることができる膜質の水素バリア膜である。このように、第2の絶縁膜72として酸化アルミニウム膜を用いることによって、水素の量に応じて水素の透過と水素の遮断とを同時に実現できる性能を有する水素バリア膜を容易に実現できる。
The aluminum oxide film used as the second insulating film 72 in this embodiment has a film quality with a relatively low film density (that is, a film quality is coarse), and a part of hydrogen that permeates the aluminum oxide film Is blocked, and part of it is transmitted. In other words, the second insulating film 72 is a hydrogen barrier film having a film quality that does not completely block hydrogen but allows hydrogen to permeate. As described above, by using the aluminum oxide film as the second insulating film 72, a hydrogen barrier film having a performance capable of simultaneously realizing hydrogen permeation and hydrogen blocking according to the amount of hydrogen can be easily realized.
このような第2の絶縁膜72としては、膜密度が2.80g/cm3以上3.25g/cm3以下の酸化アルミニウム膜を用いることができる。なお、酸化アルミニウム膜の膜密度を2.80g/cm3以上にすることで、上記の水素バリア性を得ることができる。また、酸化アルミニウム膜の膜密度を3.25g/cm3以下にすることで、エッチングによる加工性を確保することができる。水素バリア性及び加工性の観点から、酸化アルミニウム膜の膜密度は、さらに、2.85g/cm3以上2.95g/cm3以下であるとよい。
Such second insulating film 72, the film density can be used 2.80 g / cm 3 or more 3.25 g / cm 3 or less of the aluminum oxide film. Note that the above hydrogen barrier property can be obtained by setting the film density of the aluminum oxide film to 2.80 g / cm 3 or more. Further, when the film density of the aluminum oxide film is set to 3.25 g / cm 3 or less, workability by etching can be ensured. From the viewpoint of the hydrogen barrier property and processability, film density of the aluminum oxide film may further When it is 2.85 g / cm 3 or more 2.95 g / cm 3 or less.
なお、膜密度が2.80g/cm3以上3.25g/cm3以下の範囲の酸化アルミニウム膜を成膜するには、酸化アルミニウム膜の膜厚については3nm以上30nm以下であるとよく、また、酸化アルミニウム膜の屈折率については1.58以上1.66以下であるとよい。
Incidentally, the film density is deposited 2.80 g / cm 3 or more 3.25 g / cm 3 or less in the range aluminum oxide film may if the film thickness of the aluminum oxide film is 3nm or 30nm or less, The refractive index of the aluminum oxide film is preferably from 1.58 to 1.66.
また、酸化アルミニウム膜はAlOxの組成式で表されるが、酸素原子数xは、1.5<x<2.0であるとよい。化学量論的組成の酸化アルミニウム膜はAl2O3であり、酸素原子数xは1.5である。この場合、Al2O3の酸化アルミニウム膜は結晶構造である。一方、酸素原子数xが1.5<x<2.0である酸化アルミニウム膜(AlOx)では、当該酸化アルミニウム膜を構成する酸化アルミニウムが、アモルファス構造であり、膜質が粗である。なお、酸化アルミニウム膜は、膜内に含まれる酸素原子が多いほど、ウェットエッチングする際に用いられるエッチング液(例えば、リン酸(HPO4)、硝酸(HNO3)、酢酸(CH3COOH)及び水を混合した薬液)と反応しやすくなる。そのため、酸化アルミニウムがアモルファス構造となっている酸化アルミニウム膜の方が、結晶構造の酸化アルミニウム膜よりもエッチングに対する加工性が向上する。したがって、AlOxで表される酸化アルミニウム膜において、酸素原子数xは、1.5<x<2.0であるとよく、1.79≦x≦1.85がより好ましい。
The aluminum oxide film is expressed by a composition formula of AlO x, and the number of oxygen atoms x is preferably 1.5 <x <2.0. The aluminum oxide film having a stoichiometric composition is Al 2 O 3 and the number of oxygen atoms x is 1.5. In this case, the Al 2 O 3 aluminum oxide film has a crystal structure. On the other hand, in the aluminum oxide film (AlO x ) in which the number of oxygen atoms x is 1.5 <x <2.0, the aluminum oxide constituting the aluminum oxide film has an amorphous structure and the film quality is rough. Note that as the aluminum oxide film contains more oxygen atoms, the etchant used for wet etching (for example, phosphoric acid (HPO 4 ), nitric acid (HNO 3 ), acetic acid (CH 3 COOH), and It becomes easy to react with a chemical solution mixed with water. Therefore, the aluminum oxide film in which the aluminum oxide has an amorphous structure is improved in the processability to etching than the aluminum oxide film having a crystalline structure. Therefore, in the aluminum oxide film represented by AlO x , the number of oxygen atoms x is preferably 1.5 <x <2.0, and more preferably 1.79 ≦ x ≦ 1.85.
第3の絶縁膜73は、第2の絶縁膜72の上に成膜される。第3の絶縁膜73には、第2の絶縁膜72(水素バリア膜)を透過することができる量の水素が含まれている。つまり、第3の絶縁膜73は、高水素膜である。本実施の形態における第3の絶縁膜73は、シリコン及び窒素を含む化合物によって構成されており、具体的には窒化シリコンで構成されている。
The third insulating film 73 is formed on the second insulating film 72. The third insulating film 73 contains an amount of hydrogen that can pass through the second insulating film 72 (hydrogen barrier film). That is, the third insulating film 73 is a high hydrogen film. The third insulating film 73 in this embodiment is made of a compound containing silicon and nitrogen, and specifically made of silicon nitride.
窒化シリコンからなる第3の絶縁膜73において、N-H結合の濃度に対するSi-H結合の濃度の比(Si-H/N-H)は、0.3よりも大きく(Si-H/N-H>0.3)、さらに、0.4よりも大きい(Si-H/N-H>0.4)方がよい。
In the third insulating film 73 made of silicon nitride, the ratio of the Si—H bond concentration to the N—H bond concentration (Si—H / N—H) is greater than 0.3 (Si—H / N). -H> 0.3) and more preferably larger than 0.4 (Si-H / N-H> 0.4).
また、第3の絶縁膜73は、下層への水分や酸素の進入を抑制するために、水分等に対してバリア性を有する膜であるとよく、さらに、第1の絶縁膜71と同様に、エッチングによる加工性を確保できる膜であるとよい。そのため、第3の絶縁膜73としては、例えば、窒化シリコン膜又は酸窒化シリコン膜の単層膜、あるいは、これらの膜を複数積層した積層膜を用いるとよい。第3の絶縁膜73の膜厚は、例えば50nm~700nm程度である。
Further, the third insulating film 73 may be a film having a barrier property against moisture or the like in order to suppress entry of moisture or oxygen into the lower layer, and further, similarly to the first insulating film 71. A film that can ensure workability by etching is preferable. Therefore, as the third insulating film 73, for example, a single layer film of a silicon nitride film or a silicon oxynitride film, or a stacked film in which a plurality of these films are stacked may be used. The film thickness of the third insulating film 73 is, for example, about 50 nm to 700 nm.
本実施の形態における絶縁層7では、第1の絶縁膜71として酸化シリコン膜を用い、第2の絶縁膜72として酸化アルミニウム膜を用い、第3の絶縁膜73として窒化シリコン膜を用いている。
In the insulating layer 7 in this embodiment, a silicon oxide film is used as the first insulating film 71, an aluminum oxide film is used as the second insulating film 72, and a silicon nitride film is used as the third insulating film 73. .
[本開示の特徴]
次に、本開示の特徴について、本開示の知見を得るに至った経緯も含めて詳細に説明する。 [Features of the present disclosure]
Next, features of the present disclosure will be described in detail, including the background to obtaining the knowledge of the present disclosure.
次に、本開示の特徴について、本開示の知見を得るに至った経緯も含めて詳細に説明する。 [Features of the present disclosure]
Next, features of the present disclosure will be described in detail, including the background to obtaining the knowledge of the present disclosure.
TFTは、例えば図2に示される方法で形成される。図2は、TFTの製造方法を説明するための図である。
The TFT is formed, for example, by the method shown in FIG. FIG. 2 is a diagram for explaining a manufacturing method of the TFT.
図2の(a)に示すように、基板1上に形成されたゲート電極2を覆うようにゲート絶縁層3を成膜する。ゲート絶縁層3は、例えば酸化シリコン膜であり、プラズマCVDChemical Vapor Deposition)法によって成膜することができる。
As shown in FIG. 2A, a gate insulating layer 3 is formed so as to cover the gate electrode 2 formed on the substrate 1. The gate insulating layer 3 is a silicon oxide film, for example, and can be formed by a plasma CVD Chemical Vapor Deposition method.
次に、図2の(b)に示すように、ゲート絶縁層3の上に酸化物半導体膜4aを成膜する。例えば、酸化物半導体膜4aとしてIGZO膜をスパッタリング法によってゲート絶縁層3の全面に成膜する。
Next, as illustrated in FIG. 2B, an oxide semiconductor film 4 a is formed on the gate insulating layer 3. For example, an IGZO film is formed as the oxide semiconductor film 4a over the entire surface of the gate insulating layer 3 by a sputtering method.
次に、図2の(c)に示すように、酸化物半導体膜4a上に所定形状のレジストRを形成する。レジストRは例えば感光性樹脂材料であり、酸化物半導体膜4aの全面に形成したレジスト膜を露光及び現像することによって所定形状のレジストRを形成することができる。
Next, as shown in FIG. 2C, a resist R having a predetermined shape is formed on the oxide semiconductor film 4a. The resist R is, for example, a photosensitive resin material, and the resist R having a predetermined shape can be formed by exposing and developing the resist film formed on the entire surface of the oxide semiconductor film 4a.
次に、図2の(d)に示すように、レジストRをマスクとして酸化物半導体膜4aをエッチングすることで酸化物半導体膜4aを所定の形状に加工する。これにより、ゲート電極2と対向する位置に島状の酸化物半導体層4を形成することができる。エッチングは、例えばウェットエッチングである。
Next, as shown in FIG. 2D, the oxide semiconductor film 4a is processed into a predetermined shape by etching the oxide semiconductor film 4a using the resist R as a mask. Thus, the island-shaped oxide semiconductor layer 4 can be formed at a position facing the gate electrode 2. Etching is, for example, wet etching.
次に、図2の(e)に示すように、レジストRを除去する。このとき、レジストRを除去することによって酸化物半導体層4の表面が露出する。
Next, as shown in FIG. 2E, the resist R is removed. At this time, the surface of the oxide semiconductor layer 4 is exposed by removing the resist R.
次に、図2の(f)に示すように、酸化物半導体層4を覆うようにゲート絶縁層3の上に酸化シリコン膜等の絶縁層5を成膜する。
Next, as shown in FIG. 2F, an insulating layer 5 such as a silicon oxide film is formed on the gate insulating layer 3 so as to cover the oxide semiconductor layer 4.
次に、図2の(g)に示すように、絶縁層5にコンタクトホールを形成して、金属膜を成膜してエッチング加工することによって、ソース電極6S及びドレイン電極6Dを形成する。
Next, as shown in FIG. 2G, a contact hole is formed in the insulating layer 5, a metal film is formed and etched, thereby forming a source electrode 6S and a drain electrode 6D.
次に、図2の(h)に示すように、ソース電極6S及びドレイン電極6Dを覆うように絶縁層5の上に絶縁層7Aを形成する。具体的には、絶縁層7Aとして、第1の絶縁膜71A、第2の絶縁膜72A及び第3の絶縁膜73Aを順次成膜する。例えば、第1の絶縁膜71Aとして酸化シリコン膜を成膜し、第2の絶縁膜72Aとして酸化アルミニウム膜を成膜し、第3の絶縁膜73Aとして窒化シリコン膜を成膜する。
Next, as shown in FIG. 2H, an insulating layer 7A is formed on the insulating layer 5 so as to cover the source electrode 6S and the drain electrode 6D. Specifically, as the insulating layer 7A, a first insulating film 71A, a second insulating film 72A, and a third insulating film 73A are sequentially formed. For example, a silicon oxide film is formed as the first insulating film 71A, an aluminum oxide film is formed as the second insulating film 72A, and a silicon nitride film is formed as the third insulating film 73A.
TFTは、このようにして製造することができるが、図2における酸化物半導体膜4aの加工プロセスにおいては、酸化物半導体層4が露出してから絶縁層5を被覆するまでの間の待機時間が存在する。待機中は、大気中に放置され、製造途中の膜表面が大気に曝される。
The TFT can be manufactured in this way, but in the process of processing the oxide semiconductor film 4a in FIG. 2, the waiting time from the exposure of the oxide semiconductor layer 4 to the covering of the insulating layer 5 Exists. During standby, the film is left in the atmosphere, and the film surface during production is exposed to the atmosphere.
本願発明者は、この待機時間がTFTの閾値電圧(Vth)に影響を及ぼすのではないかと考え、待機時間とTFTの閾値電圧との依存性について実験を行った。その結果を図3に示す。
The present inventor considered that this standby time might affect the threshold voltage (Vth) of the TFT, and conducted an experiment on the dependence between the standby time and the threshold voltage of the TFT. The result is shown in FIG.
図3は、図2に示す方法で製造したTFTに関するデータであり、レジストRを除去して酸化物半導体層4が露出してから絶縁層5で被覆するまでの待機時間とTFTの閾値電圧との関係を示している。なお、図3では、酸化物半導体膜4aとしてIGZO膜を用いている。
FIG. 3 shows data relating to the TFT manufactured by the method shown in FIG. 2. The waiting time until the resist R is removed and the oxide semiconductor layer 4 is exposed and covered with the insulating layer 5 and the threshold voltage of the TFT are shown. Shows the relationship. In FIG. 3, an IGZO film is used as the oxide semiconductor film 4a.
図3に示すように、成膜した酸化物半導体膜4aをエッチング加工した後にレジストRを除去して酸化物半導体層4を露出(図2(e))させてから酸化物半導体層4を絶縁層5で被覆するまでの待機時間と、当該酸化物半導体層4を用いたTFTの閾値電圧との間には相関があることが分かった。
As shown in FIG. 3, after the oxide semiconductor film 4a is etched, the resist R is removed to expose the oxide semiconductor layer 4 (FIG. 2E), and then the oxide semiconductor layer 4 is insulated. It has been found that there is a correlation between the waiting time until coating with the layer 5 and the threshold voltage of the TFT using the oxide semiconductor layer 4.
具体的には、酸化物半導体層4が露出してから当該酸化物半導体層4を絶縁層5で被覆するまでの待機時間(酸化物半導体層4の表面露出時間)が増加するに従って、TFTの閾値電圧(Vth)が増加することが分かった。TFTの閾値電圧の増加は、表示パネルの表示均一性や信頼性の低下が低下を引き起こし、また、消費電力の増大を引き起こす。
Specifically, as the standby time (the surface exposure time of the oxide semiconductor layer 4) from the exposure of the oxide semiconductor layer 4 to the covering of the oxide semiconductor layer 4 with the insulating layer 5 increases, It was found that the threshold voltage (Vth) increases. An increase in the threshold voltage of the TFT causes a decrease in display uniformity and reliability of the display panel, and also causes an increase in power consumption.
そこで、本願発明者は、この問題を解決する手段について鋭意検討した結果、図2における絶縁層7Aの第3の絶縁膜73A(SiN)に含まれる水素の量を調整することによって、TFTの閾値電圧を制御できるのではないかと考えて、第3の絶縁膜73A(SiN)について実験を行った。
Therefore, as a result of intensive studies on means for solving this problem, the inventor of the present application has adjusted the threshold value of the TFT by adjusting the amount of hydrogen contained in the third insulating film 73A (SiN) of the insulating layer 7A in FIG. An experiment was conducted on the third insulating film 73A (SiN) on the assumption that the voltage could be controlled.
具体的には、物性値の異なる第3の絶縁膜73A(SiN)を用いて、図3のように、酸化物半導体層4を露出させてから酸化物半導体層4を絶縁層5で被覆するまでの待機時間と、当該酸化物半導体層4を用いたTFTの閾値電圧との関係を調べた。なお、この実験では、酸化物半導体膜4aとしてIGZO膜を用いている。
Specifically, using the third insulating film 73A (SiN) having different physical properties, the oxide semiconductor layer 4 is covered with the insulating layer 5 after the oxide semiconductor layer 4 is exposed as shown in FIG. The relationship between the waiting time until the TFT and the threshold voltage of the TFT using the oxide semiconductor layer 4 was examined. In this experiment, an IGZO film is used as the oxide semiconductor film 4a.
図4Aは、そのときに用いた3種類の第3の絶縁膜73Aの成膜条件を示している。試料1、試料2及び試料3は、いずれも窒化シリコン膜(SiN)であり、平行平板型RFプラズマCVD装置を用いて成膜した。
FIG. 4A shows the deposition conditions for the three types of third insulating films 73A used at that time. Samples 1, 2 and 3 were all silicon nitride films (SiN) and were formed using a parallel plate RF plasma CVD apparatus.
図4Aに示す成膜条件(数値)は、試料1の成膜条件を「1」として規格化したものであり、試料1、2、3の成膜条件は相対比で示している。なお、成膜温度は、いずれも同じにしている。
The film formation conditions (numerical values) shown in FIG. 4A are standardized with the film formation conditions of Sample 1 as “1”, and the film formation conditions of Samples 1, 2, and 3 are shown as relative ratios. Note that the film formation temperature is the same in all cases.
図4Aに示すように、試料1の成膜条件は、高応力で低水素の膜質の窒化シリコン膜を成膜するための条件であり、試料2の成膜条件は、低応力で高水素の膜質の窒化シリコン膜を成膜するための条件であり、試料3の成膜条件は、低応力で低水素の膜質の窒化シリコン膜を成膜するための条件である。このように、高水素膜(試料2)は、低水素膜(試料1、試料3)に対して、SiH4/NH3流量比、RFパワー及び圧力を増加させることで作製することができる。
As shown in FIG. 4A, the film forming conditions of sample 1 are conditions for forming a silicon nitride film having a high stress and low hydrogen film quality, and the film forming conditions of sample 2 are low stress and high hydrogen. This is a condition for forming a silicon nitride film having a film quality, and the film forming condition for the sample 3 is a condition for forming a silicon nitride film having a low stress and a low hydrogen film quality. Thus, the high hydrogen film (sample 2) can be produced by increasing the SiH 4 / NH 3 flow rate ratio, the RF power, and the pressure with respect to the low hydrogen film (sample 1, sample 3).
図4Bは、図4Aの成膜条件で得られた、試料1、試料2及び試料3の3種類の第3の絶縁膜73A(SiN)の物性値を示している。
FIG. 4B shows physical property values of three types of third insulating films 73A (SiN) of Sample 1, Sample 2, and Sample 3 obtained under the film forming conditions of FIG. 4A.
図4Bにおいて、「Si-H」は、シリコンと水素との結合(Si-H結合)であり、その値は、窒化シリコン膜におけるSi-H結合の濃度を示している。同様に、「N-H」は、窒素と水素との結合(N-H結合)であり、その値は、窒化シリコン膜におけるN-H結合の濃度を示している。なお、「Si-H」及び「N-H」は、フーリエ変換赤外分光光度計(FTIR:Fourier Transform Infrared Spectroscopy)によって測定した。
In FIG. 4B, “Si—H” is a bond between silicon and hydrogen (Si—H bond), and the value indicates the concentration of Si—H bond in the silicon nitride film. Similarly, “N—H” is a bond between nitrogen and hydrogen (N—H bond), and the value indicates the concentration of the N—H bond in the silicon nitride film. “Si—H” and “N—H” were measured by a Fourier transform infrared spectrophotometer (FTIR: Fourier Transform Infrared Spectroscopy).
図4Bに示すように、高水素の窒化シリコン(試料2)は、窒化シリコン膜におけるSi-H結合の濃度が大きくなっており、低水素の窒化シリコン(試料1、試料3)と比べて、N-H結合の濃度に対するSi-H結合の濃度の比(Si-H/N-H)の値が大きいことが分かる。
As shown in FIG. 4B, the high-hydrogen silicon nitride (sample 2) has a higher concentration of Si—H bonds in the silicon nitride film, compared to the low-hydrogen silicon nitride (sample 1, sample 3). It can be seen that the ratio of the Si—H bond concentration to the N—H bond concentration (Si—H / NH) is large.
具体的には、高水素の窒化シリコン(試料2)では、Si-H/N-H>0.4であり、低水素の窒化シリコン(試料1、試料3)では、Si-H/N-H<0.1であり、高水素の窒化シリコン(試料2)は、低水素の窒化シリコン(試料1、試料3)に対して、Si-H/N-Hが5倍以上になっている。
Specifically, Si—H / N—H> 0.4 for high hydrogen silicon nitride (sample 2), and Si—H / N— for low hydrogen silicon nitride (sample 1, sample 3). H <0.1, and high-hydrogen silicon nitride (sample 2) has a Si—H / N—H ratio five times or more that of low-hydrogen silicon nitride (sample 1 and sample 3). .
図5は、試料1、試料2及び試料3の各試料を用いて作製したTFTについて、レジストRを除去して酸化物半導体層4が露出してから絶縁層5で被覆するまでの待機時間とTFTの閾値電圧との関係を示している。
FIG. 5 shows a waiting time from when the resist R is removed and the oxide semiconductor layer 4 is exposed to covering with the insulating layer 5 with respect to the TFTs manufactured using the samples 1, 2 and 3. The relationship with the threshold voltage of TFT is shown.
図5に示すように、低水素で高応力の膜質である窒化シリコン(試料1)については、待機時間が増加するに従ってTFTの閾値電圧が増加していくことが分かる。また、低水素で低応力の膜質である窒化シリコン(試料3)についても、待機時間が増加するに従ってTFTの閾値電圧が増加していくことが分かる。つまり、膜応力の大小にかかわらず、低水素の窒化シリコンは、待機時間が増加するに従ってTFTの閾値電圧が増加すると考えられる。
As can be seen from FIG. 5, the threshold voltage of the TFT increases as the standby time increases for silicon nitride (sample 1) having a low hydrogen and high stress film quality. It can also be seen that the threshold voltage of the TFT increases as the standby time increases for silicon nitride (sample 3) having a low hydrogen and low stress film quality. In other words, regardless of the magnitude of the film stress, it is considered that the threshold voltage of the TFT of low hydrogen silicon nitride increases as the standby time increases.
一方、高水素で低応力の膜質である窒化シリコン(試料2)については、待機時間が増加してもTFTの閾値電圧があまり変化せず、むしろ、待機時間が増加するに従ってTFTの閾値電圧が徐々に低下していき、その後飽和することが分かる。
On the other hand, in the case of silicon nitride (sample 2) having a high hydrogen and low stress film quality, the threshold voltage of the TFT does not change much even when the standby time is increased. Rather, the threshold voltage of the TFT is increased as the standby time is increased. It can be seen that it gradually decreases and then saturates.
図5に示す結果から、窒化シリコン膜である第3の絶縁膜73は、低水素(Si-H/N-H<0.1)の場合は待機時間の増加に伴って閾値電圧が上昇するが、高水素(Si-H/N-H>0.4)の場合は待機時間の増加に伴って緩やかに減少し、その後飽和する。
From the results shown in FIG. 5, the threshold voltage of the third insulating film 73, which is a silicon nitride film, increases as the standby time increases in the case of low hydrogen (Si—H / N—H <0.1). However, in the case of high hydrogen (Si—H / N—H> 0.4), it gradually decreases as the standby time increases and then saturates.
本願発明者は、この結果について検討した結果、以下の理由でTFTの閾値電圧が変化していることが分かった。この理由について、図6A、図6B及び図6Cを用いて説明する。図6Aは、比較例1の薄膜トランジスタにおける水素拡散を説明するための図である。図6Bは、図1に示す構造の実施の形態に係る薄膜トランジスタにおける水素拡散を説明するための図である。図6Cは、比較例2の薄膜トランジスタにおける水素拡散を説明するための図である。
As a result of examining this result, the inventors of the present application have found that the threshold voltage of the TFT changes for the following reason. The reason for this will be described with reference to FIGS. 6A, 6B, and 6C. 6A is a diagram for explaining hydrogen diffusion in the thin film transistor of Comparative Example 1. FIG. FIG. 6B is a diagram for explaining hydrogen diffusion in the thin film transistor according to the embodiment having the structure shown in FIG. 1. 6C is a diagram for explaining hydrogen diffusion in the thin film transistor of Comparative Example 2. FIG.
酸化物半導体TFTでは、酸化物半導体層の上方に形成されるパッシベーション膜として窒化シリコン膜を用いる場合、信頼性確保の観点から、通常、低水素の窒化シリコン膜が用いられる。これは、窒化シリコン膜に含まれる水素が熱工程等で酸化物半導体層に進入して酸化物半導体層に水素ダメージを与えることを抑制するためである。酸化物半導体層が水素ダメージを受けるとTFTの閾値電圧が変動することになる。つまり、窒化シリコン膜においてSi-H結合が多いと水素が拡散しやすいので、一般的には、Si-H結合を以下に低く抑えるかが重要であると考えられており、これが当業者の技術常識となっている。
In the oxide semiconductor TFT, when a silicon nitride film is used as a passivation film formed above the oxide semiconductor layer, a low-hydrogen silicon nitride film is usually used from the viewpoint of ensuring reliability. This is to prevent hydrogen contained in the silicon nitride film from entering the oxide semiconductor layer by a thermal process or the like and causing hydrogen damage to the oxide semiconductor layer. When the oxide semiconductor layer is damaged by hydrogen, the threshold voltage of the TFT changes. In other words, hydrogen is likely to diffuse if there are many Si—H bonds in the silicon nitride film, and therefore it is generally considered that it is important to keep the Si—H bonds low. It is common sense.
しかも、窒化シリコン膜中の水素が下層に拡散することをさらに防止するために、図6Aに示すように、酸化物半導体層4と第3の絶縁膜73J(窒化シリコン膜)との間に、第2の絶縁膜72として水素バリア膜である酸化アルミニウムを挿入することも考えられている。これにより、第3の絶縁膜73J(窒化シリコン膜)から拡散する水素を、第2の絶縁膜72(酸化アルミニウム膜)によってブロックできるので、水素による酸化物半導体層4のダメージを防止できると考えられてきた。
Moreover, in order to further prevent hydrogen in the silicon nitride film from diffusing into the lower layer, as shown in FIG. 6A, between the oxide semiconductor layer 4 and the third insulating film 73J (silicon nitride film), It is also considered to insert aluminum oxide, which is a hydrogen barrier film, as the second insulating film 72. Thereby, hydrogen diffused from the third insulating film 73J (silicon nitride film) can be blocked by the second insulating film 72 (aluminum oxide film), so that damage to the oxide semiconductor layer 4 due to hydrogen can be prevented. Has been.
このように、これまでは、酸化物半導体層の上方のパッシベーション膜としては低水素の窒化シリコン膜を用いて、かつ、窒化シリコン膜と酸化物半導体層との間に水素バリア膜を導入していた。
Thus, so far, a low-hydrogen silicon nitride film has been used as the passivation film above the oxide semiconductor layer, and a hydrogen barrier film has been introduced between the silicon nitride film and the oxide semiconductor layer. It was.
しかしながら、実際に図6Aの構造の薄膜トランジスタを作製してみると、十分なTFT特性を得ることができていない。本願発明者は、この点について鋭意検討したところ、酸化物半導体層4の表面露出時間が閾値電圧に影響を与えていることをつきとめた。この点について、以下詳細に説明する。
However, when the thin film transistor having the structure shown in FIG. 6A is actually manufactured, sufficient TFT characteristics cannot be obtained. The inventor of the present application diligently studied this point and found that the surface exposure time of the oxide semiconductor layer 4 has an influence on the threshold voltage. This point will be described in detail below.
上記図2に示されるように、酸化物半導体膜をエッチング加工して酸化物半導体層4を形成する場合、エッチング加工直後(図2(d))の酸化物半導体層4(IGZO膜)では、In、Ga及びZnはそれぞれ均等な割合で酸素と結合するとともに均等な割合で酸素欠損が生成される。つまり、エッチング加工直後の酸化物半導体層4は均一組成の膜質となっている。
As shown in FIG. 2, when the oxide semiconductor layer 4 is formed by etching the oxide semiconductor film, the oxide semiconductor layer 4 (IGZO film) immediately after the etching process (FIG. 2D) In, Ga, and Zn are bonded to oxygen at an equal ratio, and oxygen vacancies are generated at an equal ratio. That is, the oxide semiconductor layer 4 immediately after the etching process has a uniform film quality.
しかしながら、その後、図2(e)に示すように、酸化物半導体層4上のレジストRが除去されて酸化物半導体層4が大気に放置されると、酸化物半導体層4の表面が大気に曝される。これにより、図6Aに示すように、酸化物半導体層4の表面層として、ガリウム(Ga)が過剰に含まれるGa過剰層(Gaリッチ層)41が生成されることが分かった。
However, after that, as shown in FIG. 2E, when the resist R on the oxide semiconductor layer 4 is removed and the oxide semiconductor layer 4 is left in the atmosphere, the surface of the oxide semiconductor layer 4 is exposed to the atmosphere. Be exposed. Thereby, as shown in FIG. 6A, it was found that a Ga-excess layer (Ga-rich layer) 41 containing gallium (Ga) excessively was generated as the surface layer of the oxide semiconductor layer 4.
これは、Ga-O結合がIn-O結合及びZn-O結合よりも強いために、酸化物半導体層4の表面においてGaの酸素欠損がIn及びZnより優先的に埋まり、また、In及びZnからGaが酸素を奪った結果、酸化物半導体層4の表面にGa-O結合が増加したからであると考えられる。
This is because the Ga—O bond is stronger than the In—O bond and the Zn—O bond, so that the oxygen deficiency of Ga fills preferentially over In and Zn on the surface of the oxide semiconductor layer 4, and In and Zn This is probably because Ga—O bonds are increased on the surface of the oxide semiconductor layer 4 as a result of Ga depriving of oxygen.
なお、Ga-O結合の結合エネルギーは374(kJmol-1)であり、In-O結合の結合エネルギーは346(kJmol-1)であるが、Zn-O結合の結合エネルギーは250(kJmol-1)未満である。また、Ga過剰層41は、酸化物半導体層4の表面に局所的に発生しているとも考えられる。
Note that the bond energy of the Ga—O bond is 374 (kJmol −1 ) and the bond energy of the In—O bond is 346 (kJmol −1 ), but the bond energy of the Zn—O bond is 250 (kJmol −1). ). In addition, it is considered that the Ga excess layer 41 is locally generated on the surface of the oxide semiconductor layer 4.
このように、酸化物半導体層4の表面層としてGa過剰層41が生成すると、酸化物半導体層4の組成が変化して、TFTの閾値電圧(Vth)が正シフトする。この結果、上記の図3に示すような結果になったと考えられる。つまり、酸化物半導体層4の表面露出時間(待機時間)の増大がTFTの閾値電圧の増加につながっていると考えられる。
Thus, when the Ga excess layer 41 is generated as the surface layer of the oxide semiconductor layer 4, the composition of the oxide semiconductor layer 4 is changed, and the threshold voltage (Vth) of the TFT is positively shifted. As a result, it is considered that the result shown in FIG. 3 was obtained. That is, it is considered that an increase in the surface exposure time (standby time) of the oxide semiconductor layer 4 leads to an increase in the threshold voltage of the TFT.
そこで、本願発明者は、鋭意検討した結果、水素バリア膜の上層の絶縁膜(窒化シリコン膜)を高水素膜にすることによって上記の待機時間(酸化物半導体層4の表面露出時間)の増加に伴う閾値電圧の増加を緩和できることを見出した。
Therefore, as a result of intensive studies, the inventor of the present application has increased the waiting time (the surface exposure time of the oxide semiconductor layer 4) by making the upper insulating film (silicon nitride film) of the hydrogen barrier film a high hydrogen film. It was found that the increase in the threshold voltage accompanying the above can be mitigated.
つまり、酸化物半導体層と絶縁膜との間に水素バリア膜が形成された構造の薄膜半導体装置において、当該絶縁膜に含まれる水素の量を制御することによって、TFTの閾値電圧を制御できることを見出した。その原理を図6Bを用いて説明する。
That is, in a thin film semiconductor device having a structure in which a hydrogen barrier film is formed between an oxide semiconductor layer and an insulating film, the threshold voltage of the TFT can be controlled by controlling the amount of hydrogen contained in the insulating film. I found it. The principle will be described with reference to FIG. 6B.
図6Bに示すように、本実施の形態における薄膜トランジスタでは、第3の絶縁膜73として、水素バリア膜である第2の絶縁膜72を透過することができる量の水素を含む絶縁膜を用いている。つまり、第3の絶縁膜73は、第2の絶縁膜72(水素バリア膜)でブロックされる水素と第2の絶縁膜72(水素バリア膜)を透過する水素とが存在するような量の水素を含んでいる。
As shown in FIG. 6B, in the thin film transistor in this embodiment, as the third insulating film 73, an insulating film containing hydrogen in an amount that can pass through the second insulating film 72 that is a hydrogen barrier film is used. Yes. That is, the third insulating film 73 has such an amount that hydrogen blocked by the second insulating film 72 (hydrogen barrier film) and hydrogen that passes through the second insulating film 72 (hydrogen barrier film) exist. Contains hydrogen.
具体的には、第2の絶縁膜72として、図4Aの試料2の成膜条件で成膜した窒化シリコン膜を用いている。したがって、第2の絶縁膜72は、図4Bの試料2の物性値を有する高水素で低応力の窒化シリコン膜(Si-H/N-H>0.4)である。
Specifically, as the second insulating film 72, a silicon nitride film formed under the film forming conditions of the sample 2 in FIG. 4A is used. Therefore, the second insulating film 72 is a high-hydrogen, low-stress silicon nitride film (Si—H / N—H> 0.4) having the physical property values of the sample 2 in FIG. 4B.
これにより、図6Bに示すように、第3の絶縁膜73(窒化シリコン膜)に含まれる水素が熱工程等によって拡散した場合、一部の水素は水素バリア膜である第2の絶縁膜72でブロックされるが、他の一部の水素は水素バリア膜である第2の絶縁膜72を透過することになる。そして、第2の絶縁膜72を透過した水素は、酸化物半導体層4の表面に生成するGa過剰層41を還元する。つまり、第2の絶縁膜72を透過した水素によって、Ga過剰層41における過剰酸化物が還元される。この結果、酸化物半導体層4の表面が改質されて、Ga過剰層41によって変動した閾値電圧の特性が元に戻り、閾値電圧が正常化する。
Thereby, as shown in FIG. 6B, when hydrogen contained in the third insulating film 73 (silicon nitride film) is diffused by a thermal process or the like, part of the hydrogen is the second insulating film 72 which is a hydrogen barrier film. However, the other part of hydrogen passes through the second insulating film 72 which is a hydrogen barrier film. Then, the hydrogen that has passed through the second insulating film 72 reduces the Ga excess layer 41 generated on the surface of the oxide semiconductor layer 4. That is, the excess oxide in the Ga excess layer 41 is reduced by the hydrogen that has passed through the second insulating film 72. As a result, the surface of the oxide semiconductor layer 4 is modified, the characteristics of the threshold voltage changed by the Ga excess layer 41 are restored, and the threshold voltage is normalized.
このように、酸化物半導体層4の上方に形成する絶縁膜(パッシベーション膜)については、通常、低水素の窒化シリコン膜(Si-H/N-H<0.1)を用いるが、本実施の形態における薄膜トランジスタでは、あえて高水素(Si-H/N-H>0.4)の窒化シリコン膜を用いている。これにより、酸化物半導体層4の表面露出時間(待機時間)の増加に伴う閾値変動の増加を抑制することができる。
As described above, as the insulating film (passivation film) formed above the oxide semiconductor layer 4, a low-hydrogen silicon nitride film (Si—H / N—H <0.1) is usually used. In the thin film transistor in this embodiment, a silicon nitride film of high hydrogen (Si—H / N—H> 0.4) is used. Thereby, an increase in threshold fluctuation accompanying an increase in the surface exposure time (standby time) of the oxide semiconductor layer 4 can be suppressed.
なお、図6Cに示すように、本実施の形態における薄膜トランジスタにおいて、水素バリア膜である第2の絶縁膜72(酸化アルミニウム膜)を成膜しない構造も考えられる。しかしながら、この場合、第3の絶縁膜73(窒化シリコン膜)に含まれる水素が熱工程等によって拡散すると、ブロックされることなく一斉に拡散した多量の水素によってGa過剰層41の過剰酸化物が還元されるだけではなく、本来の酸化物半導体層4中の酸化物も還元されてしまうおそれがある。この結果、酸化物半導体層4が導通化して、TFTとして本来の動作が得られなくなる可能性がある。
As shown in FIG. 6C, a structure in which the second insulating film 72 (aluminum oxide film) that is a hydrogen barrier film is not formed in the thin film transistor in this embodiment is also conceivable. However, in this case, if hydrogen contained in the third insulating film 73 (silicon nitride film) is diffused by a thermal process or the like, the excess oxide of the Ga excess layer 41 is caused by a large amount of hydrogen diffused all at once without being blocked. In addition to being reduced, the oxide in the original oxide semiconductor layer 4 may be reduced. As a result, the oxide semiconductor layer 4 becomes conductive, and there is a possibility that the original operation as a TFT cannot be obtained.
したがって、図6Bに示すように、酸化物半導体層4と水素を含有する絶縁膜(第3の絶縁膜73)との間には、水素バリア性を有する水素バリア膜(第2の絶縁膜72)を挿入することが望まれる。つまり、第3の絶縁膜73の高水素化に伴うTFT信頼性低下の副作用については、酸化物半導体層4と絶縁膜(第3の絶縁膜73)との間に水素バリア膜を挿入することで、絶縁膜(第3の絶縁膜73)から水素が拡散しすぎることを抑制するとよい。
Therefore, as shown in FIG. 6B, a hydrogen barrier film (second insulating film 72) having a hydrogen barrier property is provided between the oxide semiconductor layer 4 and the insulating film containing hydrogen (third insulating film 73). ) Is desired. In other words, with respect to the side effect of the decrease in TFT reliability due to the high hydrogenation of the third insulating film 73, a hydrogen barrier film is inserted between the oxide semiconductor layer 4 and the insulating film (third insulating film 73). Therefore, it is preferable to suppress excessive diffusion of hydrogen from the insulating film (third insulating film 73).
このように、本願発明者は、絶縁膜(第3の絶縁膜73)に含まれる水素の量を制御することによってTFTの閾値電圧を制御できることを見出した。
Thus, the inventors of the present application have found that the threshold voltage of the TFT can be controlled by controlling the amount of hydrogen contained in the insulating film (third insulating film 73).
[薄膜トランジスタ基板の製造方法]
次に、実施の形態に係る薄膜トランジスタ10の製造方法について、図7A~図7Jを用いて説明する。図7A~図7Jは、実施の形態に係る薄膜トランジスタの製造方法における各工程の断面図である。 [Thin Film Transistor Substrate Manufacturing Method]
Next, a method for manufacturing thethin film transistor 10 according to the embodiment will be described with reference to FIGS. 7A to 7J. 7A to 7J are cross-sectional views of each step in the method of manufacturing the thin film transistor according to the embodiment.
次に、実施の形態に係る薄膜トランジスタ10の製造方法について、図7A~図7Jを用いて説明する。図7A~図7Jは、実施の形態に係る薄膜トランジスタの製造方法における各工程の断面図である。 [Thin Film Transistor Substrate Manufacturing Method]
Next, a method for manufacturing the
まず、図7Aに示すように、基板1を準備して、当該基板1の上方に所定形状のゲート電極2を形成する。例えば、基板1としてガラス基板を準備して、ガラス基板の上にゲート金属膜をスパッタリング法によって成膜し、フォトリソグラフィ法及びウェットエッチング法を用いてゲート金属膜を加工することにより、所定形状のゲート電極2を形成する。なお、基板1の表面にアンダーコート層が形成されている場合には、アンダーコート層上にゲート電極2を形成する。
First, as shown in FIG. 7A, a substrate 1 is prepared, and a gate electrode 2 having a predetermined shape is formed above the substrate 1. For example, a glass substrate is prepared as the substrate 1, a gate metal film is formed on the glass substrate by a sputtering method, and the gate metal film is processed using a photolithography method and a wet etching method, whereby a predetermined shape is obtained. The gate electrode 2 is formed. When an undercoat layer is formed on the surface of the substrate 1, the gate electrode 2 is formed on the undercoat layer.
次に、図7Bに示すように、ゲート電極2上にゲート絶縁層3を形成する。例えば、ゲート電極2を覆うようにして基板1の上方全面に成膜する。ゲート絶縁層3は、例えば、酸化シリコン膜である。この場合、シランガス(SiH4)及び亜酸化窒素ガス(N2O)を導入ガスに用いて、プラズマCVD法によって酸化シリコン膜を成膜することができる。
Next, as shown in FIG. 7B, a gate insulating layer 3 is formed on the gate electrode 2. For example, a film is formed on the entire upper surface of the substrate 1 so as to cover the gate electrode 2. The gate insulating layer 3 is, for example, a silicon oxide film. In this case, a silicon oxide film can be formed by a plasma CVD method using silane gas (SiH 4 ) and nitrous oxide gas (N 2 O) as an introduction gas.
なお、ゲート絶縁層3は、単層膜でもよいが、積層膜としてもよい。例えば、ゲート絶縁層3として、窒化シリコン膜と酸化シリコン膜とを順に成膜した積層膜を用いることができる。窒化シリコン膜は、例えば、シランガス(SiH4)、アンモニアガス(NH3)及び窒素ガス(N2)を導入ガスに用いて、プラズマCVD法によって成膜することができる。
Note that the gate insulating layer 3 may be a single layer film or a laminated film. For example, as the gate insulating layer 3, a stacked film in which a silicon nitride film and a silicon oxide film are sequentially formed can be used. The silicon nitride film can be formed by a plasma CVD method using, for example, silane gas (SiH 4 ), ammonia gas (NH 3 ), and nitrogen gas (N 2 ) as introduction gases.
次に、図7Cに示すように、基板1の上方に酸化物半導体膜4aを成膜する。具体的には、ゲート絶縁層3の上に酸化物半導体膜4aを成膜する。酸化物半導体膜4aは、例えば、InGaZnOXからなるIGZO膜であり、スパッタリング法によって成膜することができる。
Next, as illustrated in FIG. 7C, the oxide semiconductor film 4 a is formed over the substrate 1. Specifically, the oxide semiconductor film 4 a is formed over the gate insulating layer 3. The oxide semiconductor film 4a is an IGZO film made of, for example, InGaZnO X and can be formed by a sputtering method.
具体的には、スパッタリングターゲットとして、例えば、In:Ga:Zn=1:1:1の組成比である、In、Ga及びZnからなる酸化物半導体(In-Ga-Zn-O)を用いて、酸素雰囲気でスパッタリングする。この場合、真空チャンバー内に不活性ガスとしてアルゴン(Ar)ガスを流入するとともに反応性ガスとして酸素(O2)を含むガスを流入し、所定のパワー密度の電圧をターゲット材に印加する。これにより、ゲート絶縁層3の上に、アモルファスのIGZO膜からなる酸化物半導体膜4aを成膜することができる。
Specifically, for example, an oxide semiconductor (In—Ga—Zn—O) made of In, Ga, and Zn having a composition ratio of In: Ga: Zn = 1: 1: 1 is used as a sputtering target. Sputtering in an oxygen atmosphere. In this case, argon (Ar) gas as an inert gas flows into the vacuum chamber and a gas containing oxygen (O 2 ) as a reactive gas flows, and a voltage with a predetermined power density is applied to the target material. Thus, the oxide semiconductor film 4a made of an amorphous IGZO film can be formed on the gate insulating layer 3.
次に、図7D~図7Fに示すように、酸化物半導体膜4aをパターニングすることによって所定形状の酸化物半導体層4を形成する。酸化物半導体膜4aのパターニングは、フォトリソグラフィ法及びエッチング法を用いて行うことができる。
Next, as shown in FIGS. 7D to 7F, the oxide semiconductor film 4a is patterned to form the oxide semiconductor layer 4 having a predetermined shape. The patterning of the oxide semiconductor film 4a can be performed using a photolithography method and an etching method.
具体的には、まず、酸化物半導体膜4a上に図7Dに示すように、酸化物半導体膜4a上に所定形状のレジストRを形成する。レジストRは例えば感光性樹脂材料であり、酸化物半導体膜4aの全面に形成したレジスト膜を露光及び現像することによって所定形状のレジストRを形成することができる。具体的には、少なくともゲート電極2に対向する位置にレジストRを残すようにしてレジスト膜を露光及び現像して加工する。
Specifically, first, as shown in FIG. 7D, a resist R having a predetermined shape is formed on the oxide semiconductor film 4a. The resist R is, for example, a photosensitive resin material, and the resist R having a predetermined shape can be formed by exposing and developing the resist film formed on the entire surface of the oxide semiconductor film 4a. Specifically, the resist film is exposed and developed so as to leave the resist R at least at a position facing the gate electrode 2.
次に、図7Eに示すように、レジストRをマスクとして酸化物半導体膜4aをエッチングする。これにより、レジストRが形成されていない領域の酸化物半導体膜4aがエッチングによって除去されて酸化物半導体膜4aが加工され、所定形状の酸化物半導体層4を形成することができる。具体的には、ゲート電極2に対向する位置を含むように、島状の酸化物半導体層4が形成される。
Next, as shown in FIG. 7E, the oxide semiconductor film 4a is etched using the resist R as a mask. Accordingly, the oxide semiconductor film 4a in a region where the resist R is not formed is removed by etching, and the oxide semiconductor film 4a is processed, so that the oxide semiconductor layer 4 having a predetermined shape can be formed. Specifically, the island-shaped oxide semiconductor layer 4 is formed so as to include a position facing the gate electrode 2.
エッチングは、例えばウェットエッチングである。この場合、酸化物半導体膜4aがIGZo膜である場合、エッチング液としては、例えば、リン酸(H3PO4)、硝酸(HNO3)、酢酸(CH3COOH)及び水を混合した薬液を用いればよい。
Etching is, for example, wet etching. In this case, when the oxide semiconductor film 4a is an IGZo film, as an etching solution, for example, a chemical solution in which phosphoric acid (H 3 PO 4 ), nitric acid (HNO 3 ), acetic acid (CH 3 COOH), and water are mixed is used. Use it.
次に、図7Fに示すように、レジストRを除去(剥離)する。レジストRは、剥離液によって除去することができる。このとき、レジストRを除去することによって酸化物半導体層4の表面が露出する。これにより、所定形状の酸化物半導体層4を形成することができる。
Next, as shown in FIG. 7F, the resist R is removed (peeled). The resist R can be removed with a stripping solution. At this time, the surface of the oxide semiconductor layer 4 is exposed by removing the resist R. Thereby, the oxide semiconductor layer 4 having a predetermined shape can be formed.
次に、図7Gに示すように、酸化物半導体層4の上に絶縁層5を成膜する。本実施の形態では、酸化物半導体層4を覆うようにしてゲート絶縁層3上に全面に絶縁層5を成膜する。
Next, as shown in FIG. 7G, an insulating layer 5 is formed on the oxide semiconductor layer 4. In this embodiment, the insulating layer 5 is formed over the entire surface of the gate insulating layer 3 so as to cover the oxide semiconductor layer 4.
絶縁層5は、例えば、酸化シリコン膜である。この場合、シランガス(SiH4)及び亜酸化窒素ガス(N2O)を導入ガスに用いて、プラズマCVD法によって酸化シリコン膜を成膜することができる。
The insulating layer 5 is, for example, a silicon oxide film. In this case, a silicon oxide film can be formed by a plasma CVD method using silane gas (SiH 4 ) and nitrous oxide gas (N 2 O) as an introduction gas.
次に、図7Hに示すように、絶縁層5にコンタクトホールCH(開口部)を形成する。例えば、酸化物半導体層4の一部が露出するように、フォトリソグラフィ法及びエッチング法を用いて絶縁層5の一部を除去してコンタクトホールCHを形成する。
Next, as shown in FIG. 7H, contact holes CH (openings) are formed in the insulating layer 5. For example, the contact hole CH is formed by removing a part of the insulating layer 5 using a photolithography method and an etching method so that a part of the oxide semiconductor layer 4 is exposed.
例えば、絶縁層5が酸化シリコン膜である場合、反応性イオンエッチング(RIE)法によるドライエッチング法によって酸化シリコン膜にコンタクトホールCHを形成することができる。この場合、エッチングガスとしては、例えば、四フッ化炭素(CF4)及び酸素ガス(O2)を用いることができる。なお、コンタクトホールCHは、酸化物半導体層4のソースコンタクト領域及びドレインコンタクト領域となる領域上に形成する。
For example, when the insulating layer 5 is a silicon oxide film, the contact hole CH can be formed in the silicon oxide film by a dry etching method using a reactive ion etching (RIE) method. In this case, for example, carbon tetrafluoride (CF 4 ) and oxygen gas (O 2 ) can be used as the etching gas. Note that the contact hole CH is formed over a region to be a source contact region and a drain contact region of the oxide semiconductor layer 4.
次に、図7Iに示すように、酸化物半導体層4に接続するように所定形状のソース電極6S及びドレイン電極6Dを形成する。具体的には、絶縁層5のコンタクトホールCHを埋めるようにして絶縁層5上にソースドレイン金属膜をスパッタリング法で成膜し、その後、フォトリソグラフィ法及びエッチング法を用いてソースドレイン金属膜を加工することで、所定形状のソース電極6S及びドレイン電極6Dを形成することができる。
Next, as shown in FIG. 7I, a source electrode 6S and a drain electrode 6D having a predetermined shape are formed so as to be connected to the oxide semiconductor layer 4. Specifically, a source / drain metal film is formed on the insulating layer 5 by a sputtering method so as to fill the contact hole CH of the insulating layer 5, and then the source / drain metal film is formed using a photolithography method and an etching method. By processing, a source electrode 6S and a drain electrode 6D having a predetermined shape can be formed.
なお、ソースドレイン金属膜としては、Mo膜、Cu膜及びCuMn膜の3層構造の金属膜を用いることができる。また、Mo膜、Cu膜及びCuMn膜からなるソースドレイン金属膜のウェットエッチングは、例えば、過酸化水素水(H2O2)及び有機酸を混合した薬液を用いて行うことができる。
As the source / drain metal film, a metal film having a three-layer structure of a Mo film, a Cu film, and a CuMn film can be used. In addition, wet etching of a source / drain metal film made of a Mo film, a Cu film, and a CuMn film can be performed using, for example, a chemical solution in which a hydrogen peroxide solution (H 2 O 2 ) and an organic acid are mixed.
次に、図7Jに示すように、ソース電極6S及びドレイン電極6Dが形成された基板1上に絶縁層7を形成する。本実施の形態では、第1の絶縁膜71、第2の絶縁膜72及び第3の絶縁膜73の3層構造の絶縁層7を形成する。一例として、第1の絶縁膜71は、酸化シリコン膜であり、第2の絶縁膜72は酸化アルミニウム膜であり、第3の絶縁膜73は、窒化シリコン膜であり、これらが順に堆積されている。
Next, as shown in FIG. 7J, the insulating layer 7 is formed on the substrate 1 on which the source electrode 6S and the drain electrode 6D are formed. In this embodiment mode, an insulating layer 7 having a three-layer structure including a first insulating film 71, a second insulating film 72, and a third insulating film 73 is formed. As an example, the first insulating film 71 is a silicon oxide film, the second insulating film 72 is an aluminum oxide film, the third insulating film 73 is a silicon nitride film, and these are sequentially deposited. Yes.
具体的には、酸化シリコン膜である第1の絶縁膜71は、例えばプラズマCVD等によって成膜することができる。
Specifically, the first insulating film 71, which is a silicon oxide film, can be formed by, for example, plasma CVD.
酸化アルミニウム膜である第2の絶縁膜72は、例えばスパッタリング法により成膜する。例えば、ターゲットとしてアルミニウムを用いて、プロセスガスとしてアルゴンガスと酸素ガス等を用いてスパッタリングを行うことで、酸化アルミニウム膜を成膜することができる。なお、酸化アルミニウムをターゲットとして用いてもよい。この場合、プロセスガスにはアルゴンガスが用いられる。
The second insulating film 72, which is an aluminum oxide film, is formed by sputtering, for example. For example, an aluminum oxide film can be formed by performing sputtering using aluminum as a target and argon gas and oxygen gas as process gases. Note that aluminum oxide may be used as a target. In this case, argon gas is used as the process gas.
窒化シリコン膜である第3の絶縁膜73は、例えばプラズマCVD等によって成膜することができる。本実施の形態では、図4Aの試料2の成膜条件で窒化シリコン膜を成膜した。したがって、第3の絶縁膜73は、高水素の窒化シリコン膜であり、少なくとも第2の絶縁膜72(酸化アルミニウム膜)を透過することができる量の水素が含まれている。
The third insulating film 73, which is a silicon nitride film, can be formed by plasma CVD or the like, for example. In this embodiment mode, a silicon nitride film is formed under the film formation conditions of the sample 2 in FIG. 4A. Accordingly, the third insulating film 73 is a high-hydrogen silicon nitride film, and contains at least hydrogen in an amount that can pass through the second insulating film 72 (aluminum oxide film).
以上により、薄膜トランジスタ10を作製することができる。なお、その後、必要に応じて、絶縁層7にコンタクトホールを形成して電極や配線を形成したり、さらに、絶縁層7の上にパッシベーション膜を形成したりしてもよい。また、酸化物半導体層4の酸素欠損を修復して酸化物半導体層4の特性を安定化させるために290℃を越える温度で熱処理(アニール処理)を行ってもよい。
Thus, the thin film transistor 10 can be manufactured. After that, if necessary, a contact hole may be formed in the insulating layer 7 to form an electrode or a wiring, or a passivation film may be formed on the insulating layer 7. Further, heat treatment (annealing) may be performed at a temperature exceeding 290 ° C. in order to repair oxygen vacancies in the oxide semiconductor layer 4 and stabilize the characteristics of the oxide semiconductor layer 4.
[まとめ]
以上説明したように、本実施の形態に係る薄膜トランジスタ10によれば、酸化物半導体層4と、絶縁膜(第3の絶縁膜73)と、酸化物半導体層4と絶縁膜(第3の絶縁膜73)との間に形成された水素バリア膜(第2の絶縁膜72)とを有し、絶縁膜(第3の絶縁膜73)には水素バリア膜(第2の絶縁膜72)を透過することができる量の水素が含まれている。 [Summary]
As described above, according to thethin film transistor 10 of the present embodiment, the oxide semiconductor layer 4, the insulating film (third insulating film 73), the oxide semiconductor layer 4 and the insulating film (third insulating film). And a hydrogen barrier film (second insulating film 72) formed between the insulating film (third insulating film 73) and the hydrogen barrier film (second insulating film 72). An amount of hydrogen that can permeate is included.
以上説明したように、本実施の形態に係る薄膜トランジスタ10によれば、酸化物半導体層4と、絶縁膜(第3の絶縁膜73)と、酸化物半導体層4と絶縁膜(第3の絶縁膜73)との間に形成された水素バリア膜(第2の絶縁膜72)とを有し、絶縁膜(第3の絶縁膜73)には水素バリア膜(第2の絶縁膜72)を透過することができる量の水素が含まれている。 [Summary]
As described above, according to the
これにより、絶縁膜(第3の絶縁膜73)に含まれる水素の一部が水素バリア膜(第2の絶縁膜72)を透過して酸化物半導体層4の表面を改質して本来の状態に戻すことができる。この結果、レジストRを除去して酸化物半導体層4が露出してから絶縁層5で被覆するまでの待機時間(酸化物半導体層4の表面露出時間)の増大に伴ってTFTの閾値電圧が増大することを抑制できる。したがって、所望の性能を有する薄膜トランジスタ10を実現できる。
As a result, part of hydrogen contained in the insulating film (third insulating film 73) permeates the hydrogen barrier film (second insulating film 72) and modifies the surface of the oxide semiconductor layer 4 to thereby improve the original property. It can be returned to the state. As a result, the threshold voltage of the TFT is increased as the standby time (the surface exposure time of the oxide semiconductor layer 4) from when the resist R is removed and the oxide semiconductor layer 4 is exposed until it is covered with the insulating layer 5 increases. The increase can be suppressed. Therefore, the thin film transistor 10 having desired performance can be realized.
また、本実施の形態に係る薄膜トランジスタ10において、絶縁膜(第3の絶縁膜73)は、シリコン及び窒素を含む化合物(例えば窒化シリコン)によって構成されており、絶縁膜(第3の絶縁膜73)におけるN-H結合の濃度に対するSi-H結合の濃度の比は、0.3よりも大きい。つまり、絶縁膜(第3の絶縁膜73)は、水素を多く含む高水素膜である。
In the thin film transistor 10 according to the present embodiment, the insulating film (third insulating film 73) is made of a compound containing silicon and nitrogen (for example, silicon nitride), and the insulating film (third insulating film 73). The ratio of the Si—H bond concentration to the N—H bond concentration in) is greater than 0.3. That is, the insulating film (third insulating film 73) is a high hydrogen film containing a large amount of hydrogen.
これにより、水素バリア膜(第2の絶縁膜72)を透過して酸化物半導体層4の表面を改質できるだけの水素を含む絶縁膜(第3の絶縁膜73)を得ることができるので、所望の性能を有する薄膜トランジスタ10を容易に実現できる。
Thus, an insulating film (third insulating film 73) containing hydrogen that can pass through the hydrogen barrier film (second insulating film 72) and modify the surface of the oxide semiconductor layer 4 can be obtained. The thin film transistor 10 having desired performance can be easily realized.
また、本実施の形態に係る薄膜トランジスタ10において、水素バリア膜である第2の絶縁膜72は、酸化アルミニウム膜である。
In the thin film transistor 10 according to the present embodiment, the second insulating film 72 that is a hydrogen barrier film is an aluminum oxide film.
これにより、絶縁膜(第3の絶縁膜73)から拡散してくる水素の量に応じて水素の透過と水素の遮断とを同時に作用させることのできる水素バリア膜を実現することができる。
Thereby, it is possible to realize a hydrogen barrier film capable of simultaneously allowing hydrogen permeation and hydrogen blocking according to the amount of hydrogen diffusing from the insulating film (third insulating film 73).
また、本実施の形態に係る薄膜トランジスタ10において、酸化アルミニウム膜である第2の絶縁膜72の膜密度は、2.80g/cm3以上3.25g/cm3以下である。
Further, in the thin film transistor 10 according to this embodiment, the film density of the second insulating film 72 is aluminum oxide film is 2.80 g / cm 3 or more 3.25 g / cm 3 or less.
これにより、水素の透過と水素の遮断とを同時に実現できる性能の水素バリア膜を確実に実現することができる。
This makes it possible to reliably realize a hydrogen barrier film capable of simultaneously realizing hydrogen permeation and hydrogen blocking.
[有機EL表示装置]
次に、上記の実施の形態に係る薄膜トランジスタ10を表示装置に適用した例について、図8及び図9を用いて説明する。なお、本実施の形態では、有機EL表示装置への適用例について説明する。 [Organic EL display device]
Next, an example in which thethin film transistor 10 according to the above embodiment is applied to a display device will be described with reference to FIGS. In this embodiment, an application example to an organic EL display device will be described.
次に、上記の実施の形態に係る薄膜トランジスタ10を表示装置に適用した例について、図8及び図9を用いて説明する。なお、本実施の形態では、有機EL表示装置への適用例について説明する。 [Organic EL display device]
Next, an example in which the
図8は、実施の形態に係る有機EL表示装置の一部切り欠き斜視図である。図9は、実施の形態に係る有機EL表示装置のピクセルバンクの例を示す斜視図である。上述の薄膜トランジスタ10は、有機EL表示装置におけるアクティブマトリクス基板のスイッチング素子又は駆動素子として用いることができる。
FIG. 8 is a partially cutaway perspective view of the organic EL display device according to the embodiment. FIG. 9 is a perspective view illustrating an example of a pixel bank of the organic EL display device according to the embodiment. The above-described thin film transistor 10 can be used as a switching element or a driving element of an active matrix substrate in an organic EL display device.
図8及び図9に示すように、有機EL表示装置100は、複数個の薄膜トランジスタ(不図示)が配置されたTFT基板(TFTアレイ基板)110と、下部電極である陽極131、有機材料からなる発光層であるEL層132及び透明な上部電極である陰極133からなる有機EL素子(発光部)130との積層構造により構成される。
As shown in FIGS. 8 and 9, the organic EL display device 100 includes a TFT substrate (TFT array substrate) 110 on which a plurality of thin film transistors (not shown) are arranged, an anode 131 as a lower electrode, and an organic material. It is composed of a laminated structure of an EL layer 132 that is a light emitting layer and an organic EL element (light emitting portion) 130 that includes a cathode 133 that is a transparent upper electrode.
本実施の形態における有機EL表示装置100は、トップエミッション型であり、陽極131は反射電極である。なお、有機EL表示装置100は、トップエミッション型に限るものではなく、ボトムエミッション型としてもよい。
The organic EL display device 100 in this embodiment is a top emission type, and the anode 131 is a reflective electrode. The organic EL display device 100 is not limited to the top emission type, and may be a bottom emission type.
TFT基板110には複数の画素120がマトリクス状に配置されており、各画素120には画素回路が設けられている。
The TFT substrate 110 has a plurality of pixels 120 arranged in a matrix, and each pixel 120 is provided with a pixel circuit.
有機EL素子130は、複数の画素120のそれぞれに対応して形成されており、各画素120に設けられた画素回路によって各有機EL素子130の発光の制御が行われる。有機EL素子130は、複数の薄膜トランジスタを覆うように形成された層間絶縁膜(平坦化層)の上に形成される。
The organic EL element 130 is formed corresponding to each of the plurality of pixels 120, and the light emission of each organic EL element 130 is controlled by a pixel circuit provided in each pixel 120. The organic EL element 130 is formed on an interlayer insulating film (planarization layer) formed so as to cover a plurality of thin film transistors.
また、有機EL素子130は、陽極131と陰極133との間にEL層132が配置された構成となっている。陽極131とEL層132との間にはさらに正孔輸送層が積層され、EL層132と陰極133との間にはさらに電子輸送層が積層されている。なお、陽極131と陰極133との間には、正孔注入層や電子注入層等のその他の機能層が設けられていてもよい。
The organic EL element 130 has a configuration in which an EL layer 132 is disposed between the anode 131 and the cathode 133. A hole transport layer is further stacked between the anode 131 and the EL layer 132, and an electron transport layer is further stacked between the EL layer 132 and the cathode 133. Note that another functional layer such as a hole injection layer or an electron injection layer may be provided between the anode 131 and the cathode 133.
各画素120は、それぞれの画素回路によって駆動制御される。また、図8に示すように、TFT基板110には、画素120の行方向に沿って配置される複数のゲート配線(走査線)140と、ゲート配線140と交差するように画素120の列方向に沿って配置される複数のソース配線(信号配線)150と、ソース配線150と平行に配置される複数の電源配線(図8では省略)とが形成されている。各画素120は、例えば直交するゲート配線140とソース配線150とによって区画されている。
Each pixel 120 is driven and controlled by each pixel circuit. Further, as shown in FIG. 8, the TFT substrate 110 includes a plurality of gate wirings (scanning lines) 140 arranged along the row direction of the pixels 120 and the column direction of the pixels 120 so as to intersect the gate wirings 140. A plurality of source wirings (signal wirings) 150 arranged along the lines and a plurality of power source wirings (not shown in FIG. 8) arranged in parallel with the source wirings 150 are formed. Each pixel 120 is partitioned by, for example, an orthogonal gate wiring 140 and a source wiring 150.
ゲート配線140は、各画素回路に含まれるスイッチング素子として動作する薄膜トランジスタのゲート電極と行毎に接続されている。ソース配線150は、各画素回路に含まれるスイッチング素子として動作する薄膜トランジスタのソース電極と列毎に接続されている。電源配線は、各画素回路に含まれる駆動素子として動作する薄膜トランジスタのドレイン電極と列毎に接続されている。
The gate wiring 140 is connected to the gate electrode of the thin film transistor operating as a switching element included in each pixel circuit for each row. The source wiring 150 is connected to the source electrode of the thin film transistor operating as a switching element included in each pixel circuit for each column. The power supply wiring is connected to the drain electrode of the thin film transistor operating as a driving element included in each pixel circuit for each column.
図9に示すように、有機EL表示装置100の各画素120は、3色(赤色、緑色、青色)のサブ画素120R、120G及び120Bによって構成されており、これらのサブ画素120R、120G及び120Bは、複数個マトリクス状に配列されている。各サブ画素120R、120G及び120Bは、バンク121によって互いに分離されている。バンク121は、ゲート配線140に平行に延びる突条と、ソース配線150に平行に延びる突条とが互いに交差するように、格子状に形成されている。そして、この突条で囲まれる部分(すなわち、バンク121の開口部)の各々とサブ画素120R、120G及び120Bの各々とが一対一で対応している。なお、本実施の形態において、バンク121はピクセルバンクとしたが、ラインバンクとしても構わない。
As shown in FIG. 9, each pixel 120 of the organic EL display device 100 is composed of sub-pixels 120R, 120G, and 120B of three colors (red, green, and blue), and these sub-pixels 120R, 120G, and 120B. Are arranged in a matrix. The sub-pixels 120R, 120G, and 120B are separated from each other by the bank 121. The banks 121 are formed in a lattice shape so that the ridges extending in parallel to the gate wiring 140 and the ridges extending in parallel to the source wiring 150 intersect each other. Each of the portions surrounded by the protrusions (that is, the opening of the bank 121) and each of the sub-pixels 120R, 120G, and 120B have a one-to-one correspondence. In the present embodiment, the bank 121 is a pixel bank, but may be a line bank.
陽極131は、TFT基板110上の層間絶縁膜(平坦化層)上でかつバンク121の開口部内に、サブ画素120R、120G及び120B毎に形成されている。同様に、EL層132は、陽極131上でかつバンク121の開口部内に、サブ画素120R、120G、120B毎に形成されている。透明な陰極133は、複数のバンク121上で、かつ全てのEL層132(全てのサブ画素120R、120G、120B)を覆うように、連続的に形成されている。
The anode 131 is formed for each of the sub-pixels 120R, 120G, and 120B on the interlayer insulating film (flattening layer) on the TFT substrate 110 and in the opening of the bank 121. Similarly, the EL layer 132 is formed for each of the sub-pixels 120R, 120G, and 120B on the anode 131 and in the opening of the bank 121. The transparent cathode 133 is continuously formed on the plurality of banks 121 so as to cover all the EL layers 132 (all the sub-pixels 120R, 120G, and 120B).
さらに、画素回路は、各サブ画素120R、120G及び120B毎に設けられており、各サブ画素120R、120G及び120Bと、対応する画素回路とは、コンタクトホール及び中継電極によって電気的に接続されている。なお、サブ画素120R、120G及び120Bは、EL層132の発光色が異なることを除いて同一の構成である。
Furthermore, the pixel circuit is provided for each of the sub-pixels 120R, 120G, and 120B, and each of the sub-pixels 120R, 120G, and 120B and the corresponding pixel circuit are electrically connected by a contact hole and a relay electrode. Yes. Note that the sub-pixels 120R, 120G, and 120B have the same configuration except that the emission color of the EL layer 132 is different.
ここで、画素120における画素回路の回路構成の一例について、図10を用いて説明する。図10は、実施の形態に係る有機EL表示装置における画素回路の構成を示す電気回路図である。なお、画素回路は、図10に示す構成に限定されるものではない。
Here, an example of the circuit configuration of the pixel circuit in the pixel 120 will be described with reference to FIG. FIG. 10 is an electric circuit diagram illustrating a configuration of a pixel circuit in the organic EL display device according to the embodiment. Note that the pixel circuit is not limited to the configuration shown in FIG.
図10に示すように、各画素120における画素回路は、スイッチング素子として動作する薄膜トランジスタSwTrと、駆動素子として動作する薄膜トランジスタDrTrと、対応する画素120に表示するためのデータを記憶するキャパシタCとで構成される。本実施の形態において、薄膜トランジスタSwTrは、画素120を選択するためのスイッチングトランジスタであり、薄膜トランジスタDrTrは、有機EL素子130を駆動するための駆動トランジスタである。
As shown in FIG. 10, the pixel circuit in each pixel 120 includes a thin film transistor SwTr that operates as a switching element, a thin film transistor DrTr that operates as a drive element, and a capacitor C that stores data to be displayed on the corresponding pixel 120. Composed. In the present embodiment, the thin film transistor SwTr is a switching transistor for selecting the pixel 120, and the thin film transistor DrTr is a drive transistor for driving the organic EL element 130.
薄膜トランジスタSwTrは、ゲート配線140に接続されるゲート電極G1と、ソース配線150に接続されるソース電極S1と、キャパシタC及び薄膜トランジスタDrTrのゲート電極G2に接続されるドレイン電極D1と、チャネル層(図示せず)とで構成される。この薄膜トランジスタSwTrは、接続されたゲート配線140及びソース配線150に所定の電圧が印加されると、当該ソース配線150に印加された電圧がデータ電圧としてキャパシタCに保存される。
The thin film transistor SwTr includes a gate electrode G1 connected to the gate wiring 140, a source electrode S1 connected to the source wiring 150, a drain electrode D1 connected to the capacitor C and the gate electrode G2 of the thin film transistor DrTr, and a channel layer (FIG. Not shown). In the thin film transistor SwTr, when a predetermined voltage is applied to the connected gate wiring 140 and source wiring 150, the voltage applied to the source wiring 150 is stored in the capacitor C as a data voltage.
薄膜トランジスタDrTrは、薄膜トランジスタSwTrのドレイン電極D1及びキャパシタCに接続されるゲート電極G2と、電源配線160及びキャパシタCに接続されるドレイン電極D2と、有機EL素子130の陽極131に接続されるソース電極S2と、半導体膜(図示せず)とで構成される。この薄膜トランジスタDrTrは、キャパシタCが保持しているデータ電圧に対応する電流を電源配線160からソース電極S2を通じて有機EL素子130の陽極131に供給する。これにより、有機EL素子130では、陽極131から陰極133へと駆動電流が流れてEL層132が発光する。
The thin film transistor DrTr includes a gate electrode G2 connected to the drain electrode D1 of the thin film transistor SwTr and the capacitor C, a drain electrode D2 connected to the power supply wiring 160 and the capacitor C, and a source electrode connected to the anode 131 of the organic EL element 130. It is comprised by S2 and a semiconductor film (not shown). The thin film transistor DrTr supplies a current corresponding to the data voltage held by the capacitor C from the power supply wiring 160 to the anode 131 of the organic EL element 130 through the source electrode S2. Thereby, in the organic EL element 130, a drive current flows from the anode 131 to the cathode 133, and the EL layer 132 emits light.
なお、上記構成の有機EL表示装置100では、ゲート配線140とソース配線150との交点に位置する画素120毎に表示制御を行うアクティブマトリクス方式が採用されている。これにより、各画素120(各サブ画素120R、120G、120B)の薄膜トランジスタSwTr及びDrTrによって、対応する有機EL素子130が選択的に発光し、所望の画像が表示される。
Note that the organic EL display device 100 having the above configuration employs an active matrix system in which display control is performed for each pixel 120 located at the intersection of the gate wiring 140 and the source wiring 150. Thereby, the corresponding organic EL element 130 selectively emits light by the thin film transistors SwTr and DrTr of each pixel 120 (each sub-pixel 120R, 120G, 120B), and a desired image is displayed.
以上、本実施の形態における有機EL表示装置100には、上記実施の形態における薄膜トランジスタ10が用いられているので、表示性能に優れた表示装置を実現できる。
As described above, since the thin film transistor 10 in the above embodiment is used in the organic EL display device 100 in the present embodiment, a display device having excellent display performance can be realized.
(変形例)
以上、薄膜トランジスタ及びその製造方法等について、実施の形態に基づいて説明したが、本開示の技術は、上記実施の形態に限定されるものではない。 (Modification)
As described above, the thin film transistor and the manufacturing method thereof have been described based on the embodiment, but the technology of the present disclosure is not limited to the above embodiment.
以上、薄膜トランジスタ及びその製造方法等について、実施の形態に基づいて説明したが、本開示の技術は、上記実施の形態に限定されるものではない。 (Modification)
As described above, the thin film transistor and the manufacturing method thereof have been described based on the embodiment, but the technology of the present disclosure is not limited to the above embodiment.
例えば、上記実施の形態において、絶縁層7は、3層構造としたが、第1の絶縁膜71を成膜せずに、酸化物半導体層4側から、酸化アルミニウム膜(下層)と窒化シリコン膜(上層)を積層した層構造としてもよい。
For example, in the above embodiment, the insulating layer 7 has a three-layer structure, but without forming the first insulating film 71, an aluminum oxide film (lower layer) and silicon nitride are formed from the oxide semiconductor layer 4 side. It is good also as a layer structure which laminated | stacked the film | membrane (upper layer).
また、上記実施の形態において、酸化物半導体膜4a及び酸化物半導体層4は、In、Ga及びZnのうち少なくとも1種を含む酸化物半導体(特にIGZO膜)としたが、これに限るものではない。例えば、酸化物半導体膜4a及び酸化物半導体層4としては、インジウム(In)及びシリコン(Si)を含む酸化物半導体(In-Si-O)からなるISO膜、インジウム(In)及びタングステン(W)を含む酸化物半導体(In-W-O)からなるIWO膜、In及びWにZn(亜鉛)がさらに添加された酸化物半導体(In-W-Zn-O)からなるIWZO膜等であってもよく、また、その他に、Hf又はTiを添加材とするIn酸化物系酸化物半導体膜、又は、Si、W、Ga、Hf、Tiを添加材とするZn酸化物系酸化物半導体膜等であってもよい。
In the above embodiment, the oxide semiconductor film 4a and the oxide semiconductor layer 4 are oxide semiconductors (in particular, IGZO films) including at least one of In, Ga, and Zn. However, the present invention is not limited to this. Absent. For example, as the oxide semiconductor film 4a and the oxide semiconductor layer 4, an ISO film made of an oxide semiconductor (In—Si—O) containing indium (In) and silicon (Si), indium (In), and tungsten (W ) Containing an oxide semiconductor (In—W—O), an oxide semiconductor in which Zn (zinc) is further added to In and W (In—W—Zn—O), and the like. In addition, an In oxide-based oxide semiconductor film containing Hf or Ti as an additive, or a Zn oxide-based oxide semiconductor film containing Si, W, Ga, Hf, and Ti as additives. Etc.
また、上記実施の形態において、薄膜トランジスタ10は、ボトムゲート型としたが、本開示の技術は、トップゲート型の薄膜トランジスタにも適用することができる。
In the above embodiment, the thin film transistor 10 is a bottom gate type, but the technology of the present disclosure can also be applied to a top gate type thin film transistor.
また、上記実施の形態において、薄膜トランジスタ10は、チャネルエッチングストッパー型(チャネル保護型)としたが、本開示の技術は、チャネルエッチング型の薄膜トランジスタにも適用することができる。
In the above embodiment, the thin film transistor 10 is a channel etching stopper type (channel protection type), but the technique of the present disclosure can also be applied to a channel etching type thin film transistor.
また、上記実施の形態において、薄膜トランジスタは有機EL表示装置に適用する例について説明したが、上記実施の形態における薄膜トランジスタは、液晶表示装置等の他の表示装置にも適用することができる。
In the above embodiment, an example in which the thin film transistor is applied to an organic EL display device has been described. However, the thin film transistor in the above embodiment can also be applied to another display device such as a liquid crystal display device.
この場合、表示装置(表示パネル)は、フラットパネルディスプレイとして利用することができる。例えば、有機EL表示装置等の表示装置は、テレビジョンセット、パーソナルコンピュータ又は携帯電話等、あらゆる電子機器の表示パネルとして利用することができる。特に、大画面及び高精細の表示装置に適している。
In this case, the display device (display panel) can be used as a flat panel display. For example, a display device such as an organic EL display device can be used as a display panel of any electronic device such as a television set, a personal computer, or a mobile phone. In particular, it is suitable for a large-screen and high-definition display device.
その他、各実施の形態及び変形例に対して当業者が思いつく各種変形を施して得られる形態や、本開示の趣旨を逸脱しない範囲で各実施の形態及び変形例における構成要素及び機能を任意に組み合わせることで実現される形態も本開示に含まれる。
In addition, the form obtained by making various modifications conceived by those skilled in the art with respect to each embodiment and modification, and the components and functions in each embodiment and modification are arbitrarily set within the scope of the present disclosure. A form realized by combination is also included in the present disclosure.
ここに開示された技術は、酸化物半導体を用いた薄膜トランジスタ及びその製造方法、並びに、薄膜トランジスタを用いた有機EL表示装置等の表示装置等において広く利用することができる。
The technique disclosed herein can be widely used in a thin film transistor using an oxide semiconductor, a manufacturing method thereof, a display device such as an organic EL display device using the thin film transistor, and the like.
1 基板
2、G1、G2 ゲート電極
3 ゲート絶縁層
4 酸化物半導体層
4a 酸化物半導体膜
5、7、7A 絶縁層
6S、S1、S2 ソース電極
6D、D1、D2 ドレイン電極
10 薄膜トランジスタ
41 Ga過剰層
71、71A 第1の絶縁膜
72、72A 第2の絶縁膜
73、73A、73J 第3の絶縁膜
100 有機EL表示装置
110 TFT基板
120 画素
120R、120G、120B サブ画素
121 バンク
130 有機EL素子
131 陽極
132 EL層
133 陰極
140 ゲート配線
150 ソース配線
160 電源配線
SwTr、DrTr 薄膜トランジスタ
C キャパシタ
CH コンタクトホール DESCRIPTION OFSYMBOLS 1 Substrate 2, G1, G2 Gate electrode 3 Gate insulating layer 4 Oxide semiconductor layer 4a Oxide semiconductor film 5, 7, 7A Insulating layer 6S, S1, S2 Source electrode 6D, D1, D2 Drain electrode 10 Thin film transistor 41 Ga excess layer 71, 71A First insulating film 72, 72A Second insulating film 73, 73A, 73J Third insulating film 100 Organic EL display device 110 TFT substrate 120 Pixel 120R, 120G, 120B Subpixel 121 Bank 130 Organic EL element 131 Anode 132 EL layer 133 Cathode 140 Gate wiring 150 Source wiring 160 Power supply wiring SwTr, DrTr Thin film transistor C Capacitor CH Contact hole
2、G1、G2 ゲート電極
3 ゲート絶縁層
4 酸化物半導体層
4a 酸化物半導体膜
5、7、7A 絶縁層
6S、S1、S2 ソース電極
6D、D1、D2 ドレイン電極
10 薄膜トランジスタ
41 Ga過剰層
71、71A 第1の絶縁膜
72、72A 第2の絶縁膜
73、73A、73J 第3の絶縁膜
100 有機EL表示装置
110 TFT基板
120 画素
120R、120G、120B サブ画素
121 バンク
130 有機EL素子
131 陽極
132 EL層
133 陰極
140 ゲート配線
150 ソース配線
160 電源配線
SwTr、DrTr 薄膜トランジスタ
C キャパシタ
CH コンタクトホール DESCRIPTION OF
Claims (14)
- 酸化物半導体層と、
絶縁膜と、
前記酸化物半導体層と前記絶縁膜との間に形成された、水素の透過を抑制する水素バリア性を有する水素バリア膜とを有し、
前記絶縁膜には、前記水素バリア膜を透過することができる量の水素が含まれている
薄膜半導体装置。 An oxide semiconductor layer;
An insulating film;
A hydrogen barrier film formed between the oxide semiconductor layer and the insulating film and having a hydrogen barrier property to suppress permeation of hydrogen;
The thin film semiconductor device, wherein the insulating film contains an amount of hydrogen that can pass through the hydrogen barrier film. - 前記絶縁膜は、シリコン及び窒素を含む化合物によって構成されており、
前記絶縁膜におけるN-H結合の濃度に対するSi-H結合の濃度の比は、0.3よりも大きい
請求項1に記載の薄膜半導体装置。 The insulating film is made of a compound containing silicon and nitrogen,
2. The thin film semiconductor device according to claim 1, wherein a ratio of the Si—H bond concentration to the N—H bond concentration in the insulating film is greater than 0.3. - 前記絶縁膜は、シリコン及び窒素を含む化合物によって構成されており、
前記絶縁膜におけるN-H結合の濃度に対するSi-H結合の濃度の比は、0.4よりも大きい
請求項1に記載の薄膜半導体装置。 The insulating film is made of a compound containing silicon and nitrogen,
2. The thin film semiconductor device according to claim 1, wherein a ratio of the Si—H bond concentration to the N—H bond concentration in the insulating film is greater than 0.4. - 前記絶縁膜は、窒化シリコン膜である
請求項2又は3に記載の薄膜半導体装置。 The thin film semiconductor device according to claim 2, wherein the insulating film is a silicon nitride film. - 前記水素バリア膜は、酸化アルミニウム膜である
請求項1~4のいずれか1項に記載の薄膜半導体装置。 The thin film semiconductor device according to any one of claims 1 to 4, wherein the hydrogen barrier film is an aluminum oxide film. - 前記酸化アルミニウム膜の膜密度は、2.80g/cm3以上3.25g/cm3以下である
請求項5に記載の薄膜半導体装置。 The film density of the aluminum oxide film, a thin film semiconductor device according to claim 5 is 2.80 g / cm 3 or more 3.25 g / cm 3 or less. - 前記酸化アルミニウム膜は、AlOxで表され、
1.5<x<2.0である
請求項5又は6に記載の薄膜半導体装置。 The aluminum oxide film is represented by AlO x
The thin film semiconductor device according to claim 5, wherein 1.5 <x <2.0. - 前記酸化アルミニウム膜の屈折率は、1.58以上1.66以下である
請求項5~7のいずれか1項に記載の薄膜半導体装置。 The thin film semiconductor device according to any one of claims 5 to 7, wherein a refractive index of the aluminum oxide film is 1.58 or more and 1.66 or less. - 前記酸化アルミニウム膜の膜厚は、3nm以上30nm以下
である
請求項5~8のいずれか1項に記載の薄膜半導体装置。 The thin film semiconductor device according to any one of claims 5 to 8, wherein the aluminum oxide film has a thickness of 3 nm to 30 nm. - 前記酸化アルミニウム膜を構成する酸化アルミニウムは、アモルファス構造である
請求項5~9のいずれか1項に記載の薄膜半導体装置。 The thin film semiconductor device according to any one of claims 5 to 9, wherein the aluminum oxide constituting the aluminum oxide film has an amorphous structure. - 前記酸化物半導体層は、インジウム、ガリウム及び亜鉛の金属酸化物によって構成されている
請求項1~10のいずれか1項に記載の薄膜半導体装置。 The thin film semiconductor device according to any one of claims 1 to 10, wherein the oxide semiconductor layer is made of a metal oxide of indium, gallium, and zinc. - 前記薄膜半導体装置は、薄膜トランジスタであり、
前記酸化物半導体層は、チャネル層である
請求項1~11のいずれか1項に記載の薄膜半導体装置。 The thin film semiconductor device is a thin film transistor,
The thin film semiconductor device according to any one of claims 1 to 11, wherein the oxide semiconductor layer is a channel layer. - 請求項1~12のいずれか1項に記載の薄膜半導体装置を備える
有機EL表示装置。 An organic EL display device comprising the thin film semiconductor device according to any one of claims 1 to 12. - 酸化物半導体層を形成する工程と、
絶縁膜を成膜する工程と、
前記酸化物半導体層と前記絶縁膜との間に、水素の透過を抑制する水素バリア性を有する水素バリア膜を成膜する工程とを有し、
前記絶縁膜には、前記水素バリア膜を透過することができる量の水素が含まれている
薄膜半導体装置の製造方法。 Forming an oxide semiconductor layer;
Forming an insulating film;
Forming a hydrogen barrier film having a hydrogen barrier property that suppresses permeation of hydrogen between the oxide semiconductor layer and the insulating film;
The method for manufacturing a thin film semiconductor device, wherein the insulating film contains an amount of hydrogen that can pass through the hydrogen barrier film.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014-220868 | 2014-10-29 | ||
JP2014220868 | 2014-10-29 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2016067585A1 true WO2016067585A1 (en) | 2016-05-06 |
Family
ID=55856951
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2015/005358 WO2016067585A1 (en) | 2014-10-29 | 2015-10-26 | Thin film semiconductor device, organic el display device and method for manufacturing thin film semiconductor device |
Country Status (1)
Country | Link |
---|---|
WO (1) | WO2016067585A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10192876B2 (en) | 2017-03-17 | 2019-01-29 | Toshiba Memory Corporation | Transistor, memory, and manufacturing method of transistor |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009141002A (en) * | 2007-12-04 | 2009-06-25 | Canon Inc | Oxide semiconductor element having insulating layer, and display device using the same |
JP2012216806A (en) * | 2011-04-01 | 2012-11-08 | Semiconductor Energy Lab Co Ltd | Manufacturing method for semiconductor device |
JP2013062495A (en) * | 2011-08-19 | 2013-04-04 | Semiconductor Energy Lab Co Ltd | Semiconductor device and method for manufacturing semiconductor device |
JP2014002827A (en) * | 2012-05-25 | 2014-01-09 | Semiconductor Energy Lab Co Ltd | Method for driving memory element |
-
2015
- 2015-10-26 WO PCT/JP2015/005358 patent/WO2016067585A1/en active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009141002A (en) * | 2007-12-04 | 2009-06-25 | Canon Inc | Oxide semiconductor element having insulating layer, and display device using the same |
JP2012216806A (en) * | 2011-04-01 | 2012-11-08 | Semiconductor Energy Lab Co Ltd | Manufacturing method for semiconductor device |
JP2013062495A (en) * | 2011-08-19 | 2013-04-04 | Semiconductor Energy Lab Co Ltd | Semiconductor device and method for manufacturing semiconductor device |
JP2014002827A (en) * | 2012-05-25 | 2014-01-09 | Semiconductor Energy Lab Co Ltd | Method for driving memory element |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10192876B2 (en) | 2017-03-17 | 2019-01-29 | Toshiba Memory Corporation | Transistor, memory, and manufacturing method of transistor |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9201280B2 (en) | Semiconductor device | |
US10283529B2 (en) | Method of manufacturing thin-film transistor, thin-film transistor substrate, and flat panel display apparatus | |
CN101794821B (en) | Thin-film transistor and display device | |
US9312279B2 (en) | Thin film transistor array substrate, method of manufacturing the same, and display apparatus including the same | |
US9246007B2 (en) | Oxide thin film transistor and method for manufacturing the same, array substrate, and display apparatus | |
US10204973B2 (en) | Display device and thin-film transistors substrate | |
US10276722B2 (en) | Thin film transistor | |
US9741588B2 (en) | Method of manufacturing thin-film transistor substrate | |
KR101407814B1 (en) | Display device and method for manufacturing display device | |
US9691906B2 (en) | Method for producing thin film transistor | |
JP6331052B2 (en) | THIN FILM TRANSISTOR, METHOD FOR PRODUCING THIN FILM TRANSISTOR AND ORGANIC EL DISPLAY DEVICE | |
JP6142300B2 (en) | Thin film transistor manufacturing method | |
US9595601B2 (en) | Method of fabricating thin-film semiconductor substrate | |
JP2016092148A (en) | Thin film transistor and manufacturing method of the same | |
WO2013187046A1 (en) | Thin film transistor | |
JP6263721B2 (en) | THIN FILM TRANSISTOR, METHOD FOR PRODUCING THIN FILM TRANSISTOR AND ORGANIC EL DISPLAY DEVICE | |
WO2016067585A1 (en) | Thin film semiconductor device, organic el display device and method for manufacturing thin film semiconductor device | |
JP6500202B2 (en) | Thin film transistor and method of manufacturing thin film transistor | |
US20160322507A1 (en) | Thin film transistor array panel and method of manufacturing the same | |
WO2015186349A1 (en) | Thin film transistor substrate manufacturing method | |
JP2016058554A (en) | Thin film transistor | |
JP6500203B2 (en) | Thin film transistor and method of manufacturing thin film transistor | |
WO2016067527A1 (en) | Thin film transistor manufacturing method | |
JP2016111092A (en) | Thin film transistor | |
JP6357664B2 (en) | Thin film transistor and manufacturing method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 15855091 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
NENP | Non-entry into the national phase |
Ref country code: JP |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 15855091 Country of ref document: EP Kind code of ref document: A1 |