WO2016064697A1

WO2016064697A1 - Wafer scale integration of red, green, and blue leds

Info

Publication number: WO2016064697A1
Application number: PCT/US2015/056142
Authority: WO
Inventors: Scott Brad Herner
Original assignee: Glo Ab
Priority date: 2014-10-23
Filing date: 2015-10-19
Publication date: 2016-04-28

Abstract

Provided is a panel for a pixilated display device which includes a wafer made of a substrate, a first light-emitting diode (LED) located above the substrate, a first transparent support located above the first at least one LED, and a second LED located above the first transparent support. Further embodiments include methods of integrating hundreds of thousands or millions of LEDs into the panel by stacking wafers. A bonded assembly of multiple wafers can be formed. Transparent insulating layer can embed contact structures, interconnect structures, and contact pads on each wafer. Transparent substrates can be employed to enhance transmission of the light from underlying wafers. Contact via structures extending to different wafers can be employed to provide electrical contact to the LEDs.

Description

Wafer Scale Integration of Red, Green, and Blue LEDs

RELATED APPLICATIONS

[0001] This application claims the benefit of priority to U.S. Provisional Patent Application No. 62/067,651, filed October 23, 2014, the entire contents of which are incorporated herein by reference.

FIELD

[0002] The present disclosure is directed to the field of light emitting diode (LED) structures, and more particularly to a stacked LED structures for providing a pixilated display device and a method of manufacturing the same.

BACKGROUND

[0003] Many display devices include panels comprising millions of pixels. Each pixel may contain light emitting diodes (LEDs) of different colors, such as red, green, and blue. Placement, fixturing, contacting, and sealing each LED die into packages or submounts is a costly and time consuming process involving discrete robotic movements and large amounts of wasted material. It is thus cost prohibitive to assemble large amounts of LEDs, such as tens of thousands or millions of LEDs, into a single panel on a display device. Therefore, there is a need in the art for an efficient and cost-effective integration of LEDs into display devices.

SUMMARY

[0004] According to an aspect of the present disclosure, a pixilated display device is provided, which comprises a bonded assembly including at least a first wafer and a second wafer. The first wafer comprises a first substrate, a first light-emitting diode (LED) located above the first substrate, and a first transparent insulating layer located above the first LED. The second wafer comprises a second substrate including a transparent material and located on a top surface of the first transparent insulating layer, and second LED located above the second substrate.

[0005] According to another aspect of the present disclosure, a method of forming a pixilated display device is provided. A plurality of wafers is provided. Each of the plurality of wafers comprises a substrate and a set of at least one LED located on the substrate. The plurality of wafers is vertically bonded to form a bonded assembly including the plurality of wafers. Each wafer within the bonded assembly includes a transparent insulating layer overlying a respective set of at least one LED. Each wafer other than the bottom wafer within the bonded assembly includes a substrate including a respective transparent material and underlying the respective set of at least one LED.

[0006] Embodiments include a pixelated display device and methods for producing the same. In an embodiment, a single wafer may be formed by providing an LED on a substrate. Multiple wafers may then be stacked so as to form pixels for a display device. In an embodiment, each wafer may comprise several LEDs. In an

embodiment, each wafer may further comprise several LEDs of a single color, such as red, green, or blue. In an embodiment, the wafers are overlaid such that the LEDs form a desired pattern. For example, overlaid LEDs may form lines of alternating blue, green, and red LEDs. A sufficient arrangement of LEDs may be controlled so as to provide displays.

[0007] In an embodiment, each LED is in electrical contact with a single interconnect structure, and each interconnect structure is in electrical contact with a single LED. In a further embodiment, the interconnect structures are arranged such that no

interconnect structures are in electrical contact with each other. In yet a further embodiment, the interconnect structures are arranged such that the interconnect structures do not block light emitted from LEDs on a lower wafer. As opposed to related art, embodiments thus employ a streamlined approach to forming a pixelated display device, thereby simultaneously decreasing manufacturing time and wasted material. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1 is a vertical cross-sectional view of a portion of a wafer including one LED according to an embodiment of the present disclosure.

[0009] FIG. 2 is a perspective view of a portion of a wafer including six LEDs according to an embodiment of the present disclosure.

[0010] FIG. 3 illustrates a plan view of a sample interconnect structure design wherein interconnect structures may be attached to corresponding contact pads according to an embodiment of the present disclosure.

[0011] FIG. 4 illustrates wafer bonding of two wafers according to an embodiment of the present disclosure.

[0012] FIGS. 5A-5C illustrate a plan view of patterns formed by the LEDs as wafers are stacked on top of each other according to an embodiment of the present disclosure.

[0013] FIG. 6 illustrates a plan view of an alternative LED pattern formed by stacking multiple wafers according to an embodiment of the present disclosure.

[0014] FIG. 7 is a vertical cross-sectional view of a portion of a stack of wafers illustrating via cavities for contact pads according to an embodiment of the present disclosure.

[0015] FIG. 8 is a vertical cross-sectional view of a portion of a stack of wafers illustrating contact via structures for contact pads according to an embodiment of the present disclosure.

[0016] FIG. 9 is a vertical cross-sectional view of another portion of a stack of wafers illustrating additional contact via structures that contact first conductivity type layers of wafers within the stack according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] The various embodiments will be described in detail with reference to the accompanying drawing. Wherever possible, the same reference numbers will be used throughout the drawing to refer to the same or like parts. References made to particular examples and implementations are for illustrative purposes, and are not intended to limit the scope of the invention or the claims.

[0018] As used herein, a first element is "electrically connected to" a second element if the first element is electrically shorted to the second element, i.e., if the first element and the second element are at the same voltage under all operational conditions.

[0019] An embodiment provides a method of assembling a pixilated display device, comprising providing a second conductivity type layer and first conductivity type layer over a substrate, providing an transparent film over the substrate, etching the transparent film such that the second conductivity type layer or the first conductivity type layer is exposed, forming a contact structure to the second conductivity type layer or the first conductivity type layer, forming an interconnect structure from the contact structure, providing another transparent film over the interconnect structure, thereby forming a wafer, and stacking the wafer over another wafer. As used herein, a first conductivity type is one of p-type and n-type, and a second conductivity type is the opposite of the first conductivity type. Thus, if the first conductivity type is n-type, the second conductivity type is p-type, and vice versa.

[0020] FIG. 1 is a vertical cross-sectional view of a portion of a wafer 100 including one LED. A substrate 102 may form the base of the wafer 100. The substrate 102 may be formed of any material that can provide structural support to the devices to be formed thereupon. For example, the substrate 102 may include silicon oxide, sapphire, or a semiconductor material. In one embodiment, the substrate 102 may include a transparent dielectric material such as silicon oxide or sapphire. A first conductivity type layer 104, such as first conductivity type GaN, may be provided above the substrate 102. A second conductivity type layer 106, such as second conductivity type GaN, may be provided above the first conductivity type layer 104. . In one embodiment, the first conductivity type can be n-type, and the second conductivity type can be p-type. In another embodiment, the first conductivity type can be p-type, and the second conductivity type can be n-type. In an embodiment, the first conductivity type layer 104 may be thicker than the second conductivity type layer 106. A quantum well 105 may be provided between the first conductivity type layer 104 and second conductivity type layer 106. A transparent conductive oxide layer 107, which can include indium tin oxide (ITO), fluorine doped tin oxide (FTO), and/or doped zinc oxide, may then be provided above the second conductivity type layer 106.

[0021] In an embodiment, a mesa etch process may be performed to etch through the transparent conductive oxide layer 107, the second conductivity type layer 106, and the optional quantum well 105. For example, a patterned mask layer (such as a patterned photoresist layer) can be formed to cover a region in which a mesa structure is to be formed, and portions of the transparent conductive oxide layer 107, the second conductivity type layer 106, and the optional quantum well 105 that are not covered by the patterned mask layer can be removed by the mesa etch process that employs the patterned mask layer as an etch mask. The mesa etch process can be an anisotropic etch or an isotropic etch. In one embodiment, the mesa etch process can be an anisotropic etch process such as a reactive ion etch process.

[0022] In one embodiment, the mesa etch process may stop in the first conductivity type layer 104. The mesa etch process may remove material portions having a total thickness in a range from 100 nm to 5,000 nm, although lesser and greater thicknesses can also be employed. The total thickness of the remove material portions can be the same as the height of the mesa structure formed by the mesa etch process. The mesa etch process can be an anisotropic etch process in which etchant ions impinge in a direction perpendicular to the surface of the transparent conductive oxide layer 107. The mesa etch process may be performed over any area of the transparent conductive oxide layer 107, and may be performed over multiple areas of the transparent conductive oxide layer 107. For example, in FIG. 1, the mesa etch process is performed on either side of the transparent conductive oxide layer 107 such that the transparent conductive oxide layer 107 is located in the center of the portion of the wafer 100.

[0023] After the mesa etch process is performed, a transparent insulating layer 112, such as Si0₂ or A1₂0₃, may be deposited above the transparent conductive oxide layer 107. A via may then be etched in the transparent insulating layer 112, opening a contact via cavity to the second conductivity type layer 106. In an embodiment, the contact via cavity may be etched in a small corner of the transparent insulating layer 112. A contact structure 110 and interconnect structure 108 may be formed by use of the contact via cavity. In an embodiment, the contact structure 110 and interconnect structure 108 may be formed by depositing a metal, such as Ti or Al, on the wafer such that the metal is in electrical contact with the second conductivity type layer 104. The metal may then be patterned and etched, forming an interconnect structure 108 from the second conductivity type layer 104 to the outside edge of a panel containing the wafer. Alternatively, the metal may be deposited in multiple layers in order to conserve lateral space on the wafer. Alternatively, the interconnect structure 108 and contact structure 110 may be formed by a damascene process, such as that typically used for Cu interconnects. Alternatively, the metal may be replaced by a transparent conductive interconnect structure such as ITO. Use of ITO would enable less absorption of light in the panel, although ITO has a higher resistivity than metal.

[0024] A contact structure 1 10 and an interconnect structure 108 may be formed prior to, during, or after formation of a transparent insulating layer 112. The transparent insulating layer 112 may include a single insulating material layer or a plurality of insulating material layers. In one embodiment, one or more of the multiple material layers in the transparent insulating layer 122 may be formed prior to formation of the contact structure 110 and the interconnect structure 108, and at least another of the multiple material layers in the transparent insulating layer 122 may be formed after formation of the contact structure 110 and the interconnect structure 122. In one embodiment, the insulating material(s) of the transparent insulating layer 112 can include dielectric materials such as silicon oxide, aluminum oxide, silicon nitride, organosilicate glass, or a combination thereof.

[0025] A planarization process can be performed on the wafer 100 to planarize the top surface of the transparent insulating layer 112. The planarization process can employ, for example, chemical mechanical planarization, a recess etch, or a combination thereof. In an embodiment, it may be advantageous for the purpose of planarization to use an LED shape with three degrees of symmetry, such as a triangle. Such a design would allow three LEDs to be arranged with a coincident corner to each other.

However, any LED shape may be used, such as a circle, square, rectangle, rhombus, or any other shape. An embodiment thus provides a pixilated display device comprising a substrate, a first at least one light-emitting diode (LED) located above the substrate, a first transparent support located above the first at least one LED, and a second at least one LED located above the first transparent support.

[0026] FIG. 2 is a perspective view of a portion of a wafer 100a including six LEDs (202a - 202f). The LEDs (202a - 202f) may be formed via a process described in the discussion of FIG. 1 above. In an embodiment, LEDs (202a - 202f) may emit light of the same or similar wavelengths, such as blue light. A substrate, such as sapphire, may form the base of the wafer 100a. As described above in the discussion of FIG. 1, the wafer 100a may include a transparent insulating layer 112a, such as Si0₂ or AI2O3, which can be disposed above the substrate before the contact structures (110a - 110f)and interconnect structures (108a - 108f) are integrated into the wafer. As further described above in the discussion of FIG. 1, the wafer 100a may also include a transparent insulating layer 112b, such as Si0₂ or A1₂0₃, which can be disposed above the substrate after contact structures (110a - 110f)and interconnect structures (108a - 108h) are integrated into the wafer 100a.

[0027] In an embodiment, each LED (202a - 202f) may have one corresponding interconnect structure (108a - 108f). For example, interconnect structure 108a connects to LED 202a via contact structure 110a, interconnect structure 108b connects to LED 202b via contact structure 110b, etc. It may be desirable to prevent interconnect structures (108a - 108h) from coming in electrical contact with each other. To that end, it may be necessary to provide interconnect structures (108a - 108h) in specific patterns or designs such that they do not come in electrical contact with each other. One possible design is illustrated in FIG. 2, in which interconnect structures (108a - 108h) run parallel to each other. As illustrated in FIG. 2, interconnect structures (108a - 108f) may run some distance from their corresponding contact structures (110a - 1 lOf) perpendicular to interconnect structures (108g, 108h) before turning ninety degrees to run parallel to interconnect structures (108g, 108h). Interconnect structures (108g, 108h) may be interconnect structures corresponding to other LEDs located in wafer 100a not shown in FIG. 2.

[0028] FIG. 3 illustrates a plan view of an exemplary interconnect structure design in which each interconnect structure (108a, 108b, 108c, 108g) may be attached to a corresponding contact pad (302a, 302b, 302c, 302g), respectively. Although only a limited number of interconnect structures (108a, 108b, 108c, 108g) are shown in FIG. 3, in general any number of interconnect structures may be included in an interconnect structure pattern. Further, any interconnect structure pattern may be used; the "fan- out" pattern shown in FIG. 3 is merely depicted for illustrative purposes. In an embodiment, interconnect structures (108a, 108b, 108c, 108g) may continue to contact pads (302a, 302b, 302c, 302g) located near the edge of wafer 100a. In an embodiment, each individual interconnect structure may have its own connection. In FIG. 3, interconnect structure 108a connects to contact pad 302a, interconnect structure 108b connects to contact pad 308b, etc.

[0029] FIG. 4 illustrates wafer bonding of wafers 100a, 400a. Wafer 100a may be the same or a similar wafer to that illustrated in FIG. 2. Wafer 400a may be similar to wafer 100a. For example, wafer 400a may have interconnect structures (408a - 408c) which are similar to interconnect structures (108a - 108c), connections (410a - 410c) which are similar to connections 1 lOa-c, and substrate 402a and transparent insulating layers (412a, 412b) which are similar to substrate 102a and transparent insulating layers 112a, b. In an embodiment, wafer 400a may have a fan-out pattern with contact pads as described in FIG. 3.

[0030] Like LEDs 102a-c, LEDs (402a - 402C) may be constructed similarly to the LED illustrated in FIG. 1. It may be desirable for all the LEDs on wafer 100a to emit light of a certain wavelength, such as blue light, and the LEDs on wafer 400a to emit light of another wavelength, such as red light. In general, however, any LEDs on any wafer may emit light of any wavelength. For example, LED 202a may emit blue light and LED 202b may emit red light, and LED 402a may emit green light. Also, even if the LEDs (202a - 202C) on wafer 100a emit light of a certain wavelength and the LEDs (402a - 402C) on wafer 400a emit light of another wavelength, LEDs 202 a-c may emit light of any wavelength, such as red, and LEDs (402a - 402C) may emit light of any wavelength, such as blue.

[0031] Wafer 400a may be aligned to, and bonded to, wafer 100a. The bonding may be achieved through a wafer-bonding technique, which can be, for example, thermocompression bonding or anodic bonding. Two or more wafers may be bonded together. In one embodiment, the total number of bonded wafers may be the same as the types of LED' s to be employed in the assembly of the wafers, each wafer providing one type of LED. Optionally, the bottommost wafer may be equipped with a reflector at its base so as to maximize the light propagating in a desired direction. As discussed in conjunction with FIGS. 5A-5C, the layout of the LEDs, patterns of the interconnects, and alignment of wafers 100a, 400a may be such that when wafer 400a is placed on wafer 100a, light emitted from wafer 100a is not obstructed by wafer 400a. Thus, the individual LEDs and interconnect structures may be arranged within a wafer to avoid such obstruction.

[0032] FIGS. 5A-5C illustrate a plan view of patterns formed by the LEDs as wafers are stacked on top of each other, and bonded to each other or one another, to form a bonded assembly. FIG. 5 A illustrates a plan view of a single wafer, such as wafer 100a. FIG. 5 A only shows LEDs 202 and interconnect structures 108. The LEDs 202 may emit light of any selected wavelength. For the example illustrated in FIG. 5 A, the LEDs 202 may emit blue light. FIG. 5A also illustrates an alternate interconnect structure pattern that is different from the pattern described in FIGS. 2 and 4.

Specifically, instead of a configuration in which all the interconnect structures 108 run in the same direction, some interconnect structures 108 in FIG. 5 A run in one direction, and some other interconnect structures 108 in FIG. 5A run in the opposite direction.

[0033] FIG. 5B illustrates a plan view of LEDs resulting from two bonded wafers. The wafer from FIG. 5A may be bonded above or below the wafer with LEDs 402. LEDs 402 may emit light of any selected wavelength, which can be different from the wavelength of the LEDs 202. For the example illustrated, in FIG. 5B, LEDs 402 may emit red light. The light emitted from the lower wafer may pass through substrate 402a and transparent insulating layer 112a, b such that light of both wavelengths propagate outside the panel. In an embodiment, the bonded wafers may form a pattern of alternating red LEDs, blue LEDs, and blank spaces, as illustrated in FIG. 5B.

However, any LED pattern may be formed via proper wafer alignment and

LED/interconnect structure placement within each wafer.

[0034] FIG. 5C illustrates a plan view of LEDs resulting from three bonded wafers. The assembly of the two wafers from FIG. 5B may be bonded above or below the wafer with LEDs 502. LEDs 502 may emit light of any selected wavelength, which can be different from the wavelengtii of the LEDs 202 and from the wavelength of the LEDs 402. For the example illustrated, in FIG. 5C, LEDs 502 may emit green light. The three bonded wafers may be bonded in any order. In a non-limiting illustrative example, a wafer of LEDs which emit only blue light may be the bottom wafer, a wafer of LEDs which emit only red light may be the middle wafer, and a wafer of LEDs which emit only green light may be the top wafer. In an embodiment, the bonded wafers may form a pattern of alternating red, blue, and green LEDs, as illustrated in FIG. 5C. However, any LED pattern may be formed via proper wafer alignment and LED/interconnect structure placement within each wafer. [0035] In general, a plurality of wafers can be provided to form a bonded assembly. Each wafer can include a substrate and a set of at least one LED located on the substrate. The plurality of wafers can be bonded vertically to form a bonded assembly including the plurality of wafers. Each wafer within the bonded assembly can include a transparent insulating layer overlying a respective set of at least one LED. Each wafer other than the bottom wafer within the bonded assembly can include a substrate including a respective transparent material and underlying the respective set of at least one LED. The substrate of the bottom wafer may, or may not, be transparent. In one embodiment, a reflector can be formed on the bottom surface of the bottom wafer.

[0036] FIG. 6 illustrates a plan view of an alternative LED pattern 600 formed by stacking multiple wafers. LEDs 202, 402, 502 may all be on different wafers such that a plan view of any individual wafer will yield an LED in the shape of a third of a circle. In an embodiment, LED 202 may emit blue light, LED 402 may emit red light, and LED 502 may emit green light. In a non-limiting illustrative example, LED 202 may be located on the bottom wafer, LED 402 may be located on the middle wafer, and LED 502 may be located on the top wafer. Light from LEDs 202, 402 may pass through the wafers above them such that light from all the wafers may be visible and may contribute to the formation of an image. LEDs 202, 402, 502 may be repeated periodically on their respective wafers such that the alternative LED pattern 600 may be repeated periodically when the wafers are stacked. Alternative LED pattern 600 is merely an example of a pattern that may be formed by stacking wafers; in general, any LED pattern that can be formed by stacking wafers may be used.

[0037] FIG. 7 is a vertical cross-sectional view of a portion of a bonded assembly 701 of wafers (100a, 400a, 700a) illustrating vias for contact pads, such as contact pads (302a, 302b, 302c, 302g) from FIG. 3. The bonded assembly 701 may comprise wafers similar to those described in FIGS. 1-2, 4. For example, wafer 700a may comprise interconnect structures 708, transparent insulating layer 712, first conductivity type layer 704, and substrate 702. Wafer 700a may also comprise a reflector 714. In general, it may be desirable to include a reflector at the bottom of the bonded assembly 701 to maximize the amplitude of the light signal in a preferred direction. Although the bonded assembly 701 comprises three wafers (100a, 400a, 700a), in general a bonded assembly may include any number of wafers. Further, the wavelength of light emitted by any LED may be the same or different from any other LED on any other wafer. In FIG. 7, wafer 100a may emit only red light, wafer 400a may emit only blue light, and wafer 700a may emit only green light.

[0038] Via cavities (716a - 716c) may be formed by anisotropically etching various portions of the bonded assembly 701 of wafers. The via cavities (716a - 716c) can be subsequently filled with a conductive material to provide electrical connections to the contact pads (302a, 302b, 302c, 302g) located within each wafer (100a, 400a, 700a) within the bonded assembly 701.

[0039] The portion of the bonded assembly 701 shown in FIG. 7 may be the edge of the panel. The interconnect structures 108, 408, 708 may fan out into contact pads near the edge of the panel in a similar manner to that illustrated in FIG. 3. For example, interconnect structures 108, which may correspond to the topmost wafer 100a, may fan out into contact pads that are located the farthest from the edge of the panel; interconnect structures 408, which may correspond to the middle wafer 400a, may fan out into contact pads closer to the edge (i.e., less far out from the edge) than interconnect structures 108 of the topmost wafer 100a; and interconnect structures 708, which may correspond to the bottom wafer 700a, may fan out closer to the edge (i.e., less far out from the edge) than interconnect structures 408 out of the middle wafer 400a. More generally, it may be desirable for the interconnect structures in upper wafers to fan out into contact pads farther from the edge than interconnect structures in lower wafers so that the via cavities (716a - 716c) may be formed without cutting into the interconnect structures of the lower wafers or electrically insulating the contact pads from the LEDs within the lower wafers.

[0040] Referring to FIG. 8, dielectric spacers (814a - 814c) can be formed on the sidewalls of the via cavities (716a - 716c) to provide lateral electrical isolation of the various contact via structures (816a - 816c) to be subsequently formed. The dielectric spacers (814a - 814c) can be formed, for example, by conformal deposition of a dielectric material layer, and an anisotropic etch that removes the horizontal portions of the dielectric material layer. Each remaining vertical portion of the conformal dielectric layer constitutes the dielectric spacers (814a - 814c), each of which is formed at a periphery of a via cavity (716a - 716c). The dielectric spacers (814a - 814c) includes a dielectric material such as silicon oxide, silicon nitride, a dielectric metal oxide (such as aluminum oxide or hafnium oxide), or a combination thereof.

[0041] Various contact via structures (816a - 816c) can be formed in the remaining volumes of the via cavities (71 a - 716c) by deposition of a conductive material and subsequent planarization of the deposited conductive material. Non-limiting examples of the conductive material include a conductive metallic nitride liner such as TiN, TaN, and WN and/or a conductive metallic material such as W, Cu, Ag, Au, or an alloy thereof. Excess portions of the deposited conductive material can be removed from above the topmost surface of the top wafer 100a, for example, by chemical mechanical planarization and/or a recess etch. The contact via structures (816a - 816c) can include a plurality of first contact via structure 816a that contacts the contact pads within the top wafer 100a, a plurality of second contact via structure 816b that contacts the contact pads within the middle wafer 400a, and a plurality of third contact via structures 816c that contacts the contact pads within the bottom wafer 700a.

[0042] The first plurality of contact via structures 816a provides a means to control LEDs on wafer 100a, the second plurality of contact via structures 816b provides a means to control LEDs on wafer 400a, and the third plurality of contact via structures 816c provides a means to control LEDs on wafer 700a. Any of the LEDs may be turned on and/or off to form a desired picture or pattern from the panel. Any number of contact via structures may be formed in an individual wafer or a bonded assembly of wafers, and the total number of contact via structures may vary depending on the number of LEDs present within the bonded assembly 701. The number and location of contact via structures may vary depending upon, for example, the number of wafers within a bonded assembly, the arrangement of wafers within a bonded assembly, and the setup of individual wafers (e.g., the pattern of interconnects).

[0043] Referring to FIG. 9, additional via cavities extending to a top surface of each first conductivity type layer within the various wafers in the bonded assembly 701 can be formed, for example, by repetition of a combination of a lithographic process and an anisotropic etch. In one embodiment, a single photoresist layer can be

lithographically exposed multiple times with intervening anisotropic etch processes that gradually increases the number of etched via cavities and/or the depths of the etched via cavities. In another embodiment, multiple photoresist layers can be employed in combination with multiple anisotropic etch processes to provide via cavities having different depths and extending to a top surface of a respective first conductivity type layer within each wafer.

[0044] Various additional dielectric spacers (824a - 824c) and various additional contact via structures (826a - 826c) can be subsequently formed. In one embodiment, formation of the additional via cavities can be performed prior to formation of the dielectric spacers (814a - 814c) illustrated in FIG. 8, and formation of the various additional dielectric spacers (824a - 824c) can be performed concurrently with formation of the dielectric spacers (814a - 814c) illustrated in FIG. 8. In addition, formation of the additional contact via structures (826a - 826c) can be performed concurrently with formation of the contact via structures (816a - 816c) illustrated in FIG. 8. The additional contact via structures (826a - 826c) contact the first conductivity type layers, which are semiconductor material layers having a doping of the first conductivity type, and are herein referred to as layer contact via structures (826a - 826c).

[0045] In one embodiment, the substrates within the wafers of the bonded assembly 701 other than the substrate of the bottom wafer 700 can include a transparent dielectric material, i.e., can be a transparent dielectric substrate. In one embodiment, each substrate within the wafers of the bonded assembly 701 can include a transparent dielectric substrate. In one embodiment, the substrates within the wafers of the bonded assembly 701 other than the substrate of the bottom wafer 700 can include silicon oxide, i.e., can be a silicon oxide substrate. In one embodiment, each substrate within the wafers of the bonded assembly 701 can include a silicon oxide substrate.

[0046] In one embodiment, the patterns of the LEDs within the plurality of wafers can be selected such that a corresponding set of at least one LED for any given wafer is located within a respective area that do not overlap with areas of any other set of at least one LED in other wafers within the plurality of wafers.

[0047] In one embodiment, at least one contact structure, at least one interconnect structure, and at least one contact pad can be formed on respective at least one LED for each of the plurality of wafers prior to bonding the plurality of wafers.

Subsequently, a set of contact via structures (816a - 816c) can be formed through portions of the bonded assembly. Each contact via structure (816a - 816c) can contact a respective contact pad. Multiple respective contact pads may be located within different wafers among the plurality of wafers.

[0048] In one embodiment, each wafer can comprise a first conductivity layer 104 located on a respective substrate 102 of the wafer and constituting a node of respective at least one LED. A set of layer contact via structures (826a - 826c) can be formed through additional portions of the bonded assembly. The layer contact via structures (826a- 826c) can contact respective first conductivity material layers 104 that are located within different wafers among the plurality of wafers.

[0049] In one embodiment, each set of at least one LED can be formed on a respective substrate by forming a material stack on the respective substrate 102. The material stack includes, from bottom to top, a first conductivity type layer 104, an optional quantum well 105, a second conductivity type layer 106, and a transparent conductive oxide layer 107. A mesa structure can be formed by patterning the transparent conductive oxide layer 107, the second conductivity type layer 106, and the optional quantum well 105. A bottom periphery of sidewalls of the mesa structure (105, 106, 107) can be formed on a surface of the first conductivity type layer 104. The mesa structure (105, 106, 107) in conjunction with an underlying portion of the first conductivity type layer 104 constitutes an LED.

[0050] In one embodiment, the transparent insulating layers of each wafer within the bonded assembly can include silicon oxide. In this case, the wafer-to-wafer bonding processes employed in the present disclosure can be a silicon oxide to silicon oxide bonding, which can be performed at an elevated temperature in a range from 300 degrees Celsius to 1,000 degrees Celsius.

[0051] The structure of the present disclosure can constitute a pixilated display device that comprises a bonded assembly including at least a first wafer and a second wafer. The first wafer comprises a first substrate (e.g., the substrate 102) and a first light- emitting diode (LED) located above the first substrate, and a first transparent insulating layer (e.g., the transparent insulating layer 112) located above the first LED. The second wafer comprises a second substrate including a transparent material and located on a top surface of the first transparent insulating layer, and a second LED located above the second substrate.

[0052] The pixilated display device can further comprise a first contact pad electrically connected to a node of the first LED and embedded within the first transparent insulating layer. The pixilated display device can further comprise a combination of a first contact structure and a first interconnect structure that is embedded within the first transparent insulating layer and contacting the node of the first LED at one end, and contacting the first contact pad at another end.

[0053] The pixilated display device can further comprise a first contact via structure (e.g., 816c in FIG. 8) extending through the second wafer and an upper portion of the first wafer and contacting the first contact pad. In one embodiment, the second wafer can comprise a second transparent insulating layer located above the second LED, and a second contact pad electrically connected to a node of the second LED and embedded within the second transparent insulating layer. The pixilated display device can further comprise a second contact via structure (e.g., 816b in FIG. 8) extending through an upper portion of the second wafer and contacting the second contact pad. In one embodiment, the first contact via structure and the second contact via structure can have the same material composition and have top surfaces that are coplanar with each other.

[0054] In one embodiment, the first LED can includes a first mesa structure having a first area, and the second LED can include a second mesa structure having a second area that does not overlap with any of the first area. As used herein, an "overlap" refers to an areal overlap of two areas. Presence of an overlap between a first area and a second area means that at least one point belonging to the first area and to the second area. Absence of an overlap between a first area and a second area means that there is no point that is located within the first area and within the second area. Each area is defined within horizontal planes that are parallel to the interface between the first wafer and the second wafer.

[0055] In one embodiment, the bonded assembly further includes a third wafer that is bonded to the second wafer, the second wafer comprises a second transparent insulating layer located above the second LED, and the third wafer comprises a third substrate including another transparent material and located on a top surface of the second transparent insulating layer, and a third LED located above the third substrate. In one embodiment, the first LED, the second LED, and the third LED can be arranged such that areas of the first, second, and third LEDs are within a rectangular strip having a uniform width, and a pair of edges of each of the first, second, and third LEDs can coincide with a pair of parallel edges of the rectangular strip as illustrated in FIG. 5C. In another embodiment, the first LED, the second LED, and the third LED can be arranged such that areas of the first, second, and third LEDs are within an elliptical region, and each of the first, second, and third LEDs can have an edge that coincided with a periphery of the elliptical region as illustrated in FIG. 6. As used herein, an elliptical region can be a region of an ellipse (of which the eccentricity is non-zero) or a region of a circle (of which the eccentricity is zero). [0056] In one embodiment, the first LED can include a first mesa structure having a first area, the second LED can include a second mesa structure having a second area, and the third LED can include a third mesa structure having a third area. Each of the first, second, and third area is defined within horizontal planes that are parallel to an interface between the first wafer and the second wafer. Each of the first, second, and third area does not overlap with any other of the first, second, and third areas as illustrated in FIGS. 5C and 6.

[0057] In one embodiment, the first wafer (e.g., the bottom wafer 700a) can comprises a first conductivity type layer located on the first substrate and constituting a node of the first LED and at least another first LED located over the first substrate (i.e., a plurality of first LEDs). A first layer contact via structure (e.g., 826c in FIG. 9) can extend through the second wafer and the first transparent insulating layer and can contact a surface of the first conductivity type layer. The second wafer (e.g., the middle wafer 400a) can comprise an additional first conductivity type layer located on the second substrate and constituting a node of the second LED and at least another second LED located over the second substrate. A second layer contact via structure (e.g., 826b in FIG. 9) can contact a surface of the additional first conductivity type layer.

[0058] In one embodiment, the first LED and at least another first LED can emit light at a first wavelength, the second LED and the at least another second LED can emit light at a second wavelength that is different from the first wavelength, and the third LED and at least another third LED can emit light at a third wavelength that is different from the first wavelength and the second wavelength.

[0059] The foregoing method descriptions are provided merely as illustrative examples and are not intended to require or imply that the steps of the various embodiments must be performed in the order presented. As will be appreciated by one of skill in the art the order of steps in the foregoing embodiments may be performed in any order. Words such as "thereafter," "then," "next," etc. are not necessarily intended to limit the order of the steps; these words may be used to guide the reader through the description of the methods. Further, any reference to claim elements in the singular, for example, using the articles "a," "an" or "the" is not to be construed as limiting the element to the singular.

[0060] Further, any step of any embodiment described herein can be used in any other embodiment. The preceding description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the invention. Thus, the present invention is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

What is claimed is:

1. A pixilated display device, comprising:

a bonded assembly including at least a first wafer and a second wafer, wherein: the first wafer comprises:

a first substrate;

a first light-emitting diode (LED) located above the first substrate; and a first transparent insulating layer located above the first LED,

and the second wafer comprises:

a second substrate including a transparent material and located on a top surface of the first transparent insulating layer; and

a second LED located above the second substrate.

2. The pixilated display device of Claim 1, further comprising a first contact pad electrically connected to a node of the first LED and embedded within the first transparent insulating layer.

3. The pixilated display device of Claim 2, further comprising a combination of a first contact structure and a first interconnect structure that is embedded within the first transparent insulating layer and contacting the node of the first LED at one end, and contacting the first contact pad at another end.

4. The pixilated display device of Claim 2, further comprising a first contact via structure extending through the second wafer and an upper portion of the first wafer and contacting the first contact pad.

5. The pixilated display device of Claim 4, wherein the second wafer comprises: a second transparent insulating layer located above the second LED; and a second contact pad electrically connected to a node of the second LED and embedded within the second transparent insulating layer.

6. The pixilated display device of Claim 5, further comprising a second contact via structure extending through an upper portion of the second wafer and contacting the second contact pad.

7. The pixilated display device of Claim 6, wherein the first contact via structure and the second contact via structure have a same material composition and have top surfaces that are coplanar with each other.

8. The pixilated display device of Claim 1, wherein:

the first LED includes a first mesa structure having a first area; and

the second LED includes a second mesa structure having a second area that does not overlap with any of the first area, each of the first area and the second area being defined within horizontal planes that are parallel to an interface between the first wafer and the second wafer.

9. The pixilated display device of Claim 1, wherein:

the bonded assembly further includes a third wafer that is bonded to the second wafer;

the second wafer comprises a second transparent insulating layer located above the second LED; and

the third wafer comprises:

a third substrate including another transparent material and located on a top surface of the second transparent insulating layer; and

a third LED located above the third substrate.

10. The pixilated display device of Claim 9, wherein:

the first LED, the second LED, and the third LED are arranged such that areas of the first, second, and third LEDs are within a rectangular strip having a uniform width; and

a pair of edges of each of the first, second, and third LEDs coincide with a pair of parallel edges of the rectangular strip.

11. The pixilated display device of Claim 9, wherein:

the first LED, the second LED, and the third LED are arranged such that areas of the first, second, and third LEDs are within an elliptical region; and

each of the first, second, and third LEDs have an edge that coincided with a periphery of the elliptical region.

12. The pixilated display device of Claim 9, wherein:

the first LED includes a first mesa structure having a first area;

the second LED includes a second mesa structure having a second area;

the third LED includes a third mesa structure having a third area;

each of the first, second, and third area is defined within horizontal planes that are parallel to an interface between the first wafer and the second wafer; and

each of the first, second, and third area does not overlap with any other of the first, second, and third areas.

13. The pixilated display device of Claim 1, wherein:

the first wafer further comprises a first conductivity type layer located on the first substrate and constituting a node of the first LED and at least another first LED located over the first substrate; and

a first layer contact via structure extends through the second wafer and the first transparent insulating layer and contacts a surface of the first conductivity type layer.

14. The pixilated display device of Claim 13, wherein:

the second wafer further comprises an additional first conductivity type layer located on the second substrate and constituting a node of the second LED and at least another second LED located over the second substrate; and

a second layer contact via structure contacts a surface of the additional first conductivity type layer.

15. The pixilated display device of Claim 14, wherein: the first LED and at least another first LED emit light at a first wavelength; and the second LED and the at least another second LED emit light at a second wavelength that is different from the first wavelength.

16. A method of forming a pixilated display device, comprising:

providing a plurality of wafers, each comprising a substrate and a set of at least one LED located on the substrate; and

bonding the plurality of wafers vertically to form a bonded assembly including the plurality of wafers, wherein:

each wafer within the bonded assembly includes a transparent insulating layer overlying a respective set of at least one LED; and

each wafer other than the bottom wafer within the bonded assembly includes a substrate including a respective transparent material and underlying the respective set of at least one LED.

17. the method of Claim 16, wherein the patterns of the LEDs within the plurality of wafers are such that a corresponding set of at least one LED for any given wafer is located within a respective area that do not overlap with areas of any other set of at least one LED in other wafers within the plurality of wafers.

18. The method of Claim 16, further comprising:

forming at least one contact structure, at least one interconnect structure, and at least one contact pad on respective at least one LED for each of the plurality of wafers prior to bonding the plurality of wafers; and

forming a set of contact via structures through portions of the bonded assembly, wherein each contact via structure contacts a respective contact pad that are located within different wafers among the plurality of wafers.

19. The method of Claim 18, wherein:

each wafer comprises a first conductivity layer located on a respective substrate of the wafer and constituting a node of respective at least one LED; and the method further comprises forming a set of layer contact via structures through additional portions of the bonded assembly, wherein the layer contact via structures contact respective first conductivity material layers that are located within different wafers among the plurality of wafers.

20. The method of Claim 16, wherein each set of at least one LED is formed on a respective substrate by:

forming a material stack on the respective substrate, the material stack including at least, from bottom to top, a first conductivity type layer, a second conductivity type layer, and a transparent conductive oxide layer; and

forming a mesa structure by patterning at least the transparent conductive oxide layer and the second conductivity type layer, wherein a bottom periphery of sidewalls of the mesa structure is formed on a surface of the first conductivity type layer, and the mesa structure in conjunction with an underlying portion of the first conductivity type layer constitutes an LED.