WO2016063608A1 - Heterojunction back contact solar cell and method for manufacturing same - Google Patents

Heterojunction back contact solar cell and method for manufacturing same Download PDF

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Publication number
WO2016063608A1
WO2016063608A1 PCT/JP2015/073572 JP2015073572W WO2016063608A1 WO 2016063608 A1 WO2016063608 A1 WO 2016063608A1 JP 2015073572 W JP2015073572 W JP 2015073572W WO 2016063608 A1 WO2016063608 A1 WO 2016063608A1
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type amorphous
film
amorphous semiconductor
semiconductor film
back contact
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PCT/JP2015/073572
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French (fr)
Japanese (ja)
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親扶 岡本
正道 小林
田所　宏之
健 稗田
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シャープ株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present invention relates to a hetero back contact solar cell and a method for manufacturing the same.
  • FIG. 37 shows a schematic cross-sectional view of the solar cell described in Patent Document 1.
  • an i-type amorphous semiconductor layer 112i made of i-type amorphous silicon containing hydrogen and hydrogen are applied to a part of the back surface 100b of the semiconductor substrate 100 made of n-type single crystal silicon.
  • An IN stacked body 112 with an n-type amorphous semiconductor layer 112n made of n-type amorphous silicon is provided.
  • An insulating layer 118 made of silicon oxide, silicon nitride, silicon oxynitride, or the like is provided over the n-type amorphous semiconductor layer 112n.
  • an i-type amorphous film made of i-type amorphous silicon containing hydrogen so as to cover the non-formation surface of the IN stacked body 112 on the back surface 100 b of the semiconductor substrate 100 and the stacked body of the insulating layer 118 on the IN stacked body 112.
  • the first conductive layer 119a, the second conductive layer 119b, and the third conductive layer 119c are formed so as to cover the non-formation surface of the insulating layer 118 on the surface of the n-type amorphous semiconductor layer 112n and the IP stacked body 113.
  • a conductive layer stack 119 is formed by sequentially stacking the fourth conductive layer 119d.
  • a groove 120 extending to the surface of the insulating layer 118 is formed in the stacked body 119 of the conductive layer, whereby an n electrode 114 on the IN stacked body 112 and a p electrode 115 on the IP stacked body 113 are formed. It is separated.
  • an i-type amorphous semiconductor layer 117i made of i-type amorphous silicon containing hydrogen and an n-type amorphous semiconductor layer made of n-type amorphous silicon containing hydrogen.
  • 117n and an insulating layer 116 made of silicon oxide, silicon nitride, silicon oxynitride, or the like are provided.
  • the embodiment disclosed herein includes a step of forming a dielectric film containing nitrogen and silicon so as to be in contact with the first surface of the semiconductor substrate, and a second surface opposite to the first surface of the semiconductor substrate. Forming a first conductive type amorphous semiconductor film and a second conductive type amorphous semiconductor film on the surface side, forming a first electrode on the first conductive type amorphous semiconductor film, Forming a second electrode on the second conductive type amorphous semiconductor film.
  • a method for manufacturing a heterojunction back contact cell is a method for manufacturing a heterojunction back contact cell.
  • the embodiment disclosed herein is a dielectric film containing a semiconductor substrate of a first conductivity type or a second conductivity type, and nitrogen and silicon provided in contact with the first surface of the semiconductor substrate.
  • a first conductivity type amorphous semiconductor film and a second conductivity type amorphous semiconductor film provided on a second surface side opposite to the first surface of the semiconductor substrate, and a first conductivity type amorphous semiconductor A heterojunction back contact cell comprising a first electrode on a porous semiconductor film and a second electrode on a second conductive amorphous semiconductor film.
  • FIG. 3 is a schematic cross-sectional view of the heterojunction back contact cell of Embodiment 1.
  • FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment.
  • FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment.
  • FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment.
  • FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment.
  • FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment.
  • FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment.
  • FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment.
  • FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment.
  • FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment.
  • FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment.
  • FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment.
  • FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment.
  • 6 is a schematic cross-sectional view of a heterojunction back contact cell of Embodiment 2.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4. It is typical sectional drawing illustrating a part of manufacturing process of the heterojunction type back contact cell of a comparative example. It is typical sectional drawing illustrating a part of manufacturing process of the heterojunction type back contact cell of a comparative example. It is typical sectional drawing illustrating a part of manufacturing process of the heterojunction type back contact cell of a comparative example.
  • FIG. 1 is a schematic cross-sectional view of a solar cell described in Patent Document 1.
  • FIG. 1 is a schematic cross-sectional view of a solar cell described in Patent Document 1.
  • FIG. 1 is a schematic cross-sectional view of the heterojunction back contact cell of the first embodiment.
  • the heterojunction back contact cell of Embodiment 1 has a semiconductor substrate 1 which is an n-type single crystal silicon substrate.
  • the first surface 1a (light-receiving surface) of the semiconductor substrate 1 has an uneven shape, and a dielectric film 6 containing nitrogen (N) and silicon (Si) is in contact with the first surface 1a. Is provided.
  • the dielectric film 6 containing N and Si for example, a film containing silicon nitride can be used.
  • the dielectric film 6 may contain one or more atoms selected from the group consisting of oxygen (O), carbon (C), and fluorine (F) in addition to N and Si.
  • the composition of the dielectric film 6 is, for example, SiN x C y O z F w H v (0 ⁇ x, 0 ⁇ y, 0 ⁇ z, 0 ⁇ w and 0 ⁇ v) (hereinafter, “SiN x C y O z Fw Hv ”)).
  • SiN x C y O z Fw Hv the composition of the dielectric film 6 can be expressed by the formula “SiN x ”.
  • the composition of the dielectric film 6 can be expressed by the formula “SiN x O z ”.
  • the composition of the dielectric film 6 can be obtained by measuring the content of each atom of the dielectric film 6 by secondary ion mass spectrometry (SIMS).
  • the thickness of the dielectric film 6 is not particularly limited, but can be, for example, 60 nm or more and 150 nm or less.
  • a natural oxide film of silicon may exist in at least a part of the region between the first surface 1a and the dielectric film 6.
  • the thickness of the natural oxide film is, for example, 5 nm or less, preferably 1 nm or less.
  • each of the first i-type amorphous semiconductor film 2 and the second i-type amorphous semiconductor film 4 is an i-type amorphous silicon film.
  • i-type means not only a completely intrinsic state but also a sufficiently low concentration (the n-type impurity concentration is less than 1 ⁇ 10 15 / cm 3 and the p-type impurity concentration is 1 ⁇ (Less than 10 15 / cm 3 ) is meant to include n-type or p-type impurities.
  • n-type means a state where the n-type impurity concentration is 1 ⁇ 10 15 / cm 3 or more
  • p-type means that the p-type impurity concentration is 1 ⁇ 10 15 / cm 3 or more. Means the state.
  • the n-type impurity concentration and the p-type impurity concentration can be measured by, for example, secondary ion mass spectrometry.
  • amorphous silicon includes not only amorphous silicon in which the dangling bonds of silicon atoms are not terminated with hydrogen, but also dangling bonds of silicon atoms such as hydrogenated amorphous silicon. In which is terminated with hydrogen.
  • a first conductive type amorphous semiconductor film 3 which is a p-type amorphous silicon film in contact with the first i-type amorphous semiconductor film 2 is provided.
  • a second conductive amorphous semiconductor film 5 which is an n-type amorphous silicon film in contact with the second i-type amorphous semiconductor film 4, is provided. Is provided.
  • the end of the stacked body 52 of the second i-type amorphous semiconductor film 4 and the second conductivity-type amorphous semiconductor film 5 is the first i-type amorphous semiconductor film 2 and the first conductivity-type amorphous.
  • the edge part of the laminated body 51 with the quality semiconductor film 3 is covered. Therefore, the end of the second i-type amorphous semiconductor film 4 is located between the first conductive type amorphous semiconductor film 3 and the second conductive type amorphous semiconductor film 5.
  • the end of the second i-type amorphous semiconductor film 4 is in contact with both the first conductive type amorphous semiconductor film 3 and the second conductive type amorphous semiconductor film 5.
  • the first conductive amorphous semiconductor film 3 and the second conductive amorphous semiconductor film 5 are separated by the second i-type amorphous semiconductor film 4.
  • first electrode 7 in contact with the first conductive type amorphous semiconductor film 3 is provided on the first conductive type amorphous semiconductor film 3.
  • a second electrode 8 that is in contact with the second conductive type amorphous semiconductor film 5 is provided on the second conductive type amorphous semiconductor film 5.
  • the first electrode 7 and the second electrode 8 aluminum, silver, or the like can be used.
  • an uneven shape is formed on the first surface 1 a serving as the light receiving surface of the semiconductor substrate 1.
  • the uneven shape of the first surface 1a can be formed, for example, by texture-etching the first surface 1a of the semiconductor substrate 1 after forming a texture mask over the entire second surface 1b of the semiconductor substrate 1. it can.
  • silicon nitride or silicon oxide can be used as the texture mask.
  • an etchant used for texture etching for example, an alkaline solution capable of dissolving silicon can be used.
  • a dielectric film 6 is formed so as to be in contact with the entire surface of the first surface 1 a of the semiconductor substrate 1.
  • the dielectric film 6 can be formed, for example, by a plasma CVD (Chemical Vapor Deposition) method.
  • SiH 4 can be used as the Si source gas, and at least one of N 2 and NH 3 can be used as the N source gas.
  • SiN x O z film is formed as the dielectric film 6, SiH 4 as Si source gas, at least one of N 2 and NH 3 as N source gas, and oxygen source gas O 2 gas can be used.
  • Each of C, O, and F in the dielectric film 6 may be intentionally introduced using a source gas containing these atoms, or may be introduced unavoidably without using the source gas. Also good.
  • the dielectric film 6 can be formed, for example, at 400 ° C. or more and 600 ° C. or less. Thereby, in the etching process described later, the dielectric film 6 can function as a protective film having etching resistance of the first surface 1a of the semiconductor substrate 1. Therefore, in the etching process described later, the first surface 1a side It is not necessary to form a protective film. For this reason, it is possible to reduce the number of manufacturing steps, thereby reducing the manufacturing cost.
  • the insulating layer 116 is formed at about 100 ° C. to 200 ° C. This is because, when the temperature at which the insulating layer 116 is formed is increased (for example, 450 ° C. or higher), hydrogen in the amorphous semiconductor layer already formed on the semiconductor substrate 100 is excessively removed, and thus amorphous. This is because the quality of the quality semiconductor layer deteriorates. Since the insulating layer formed at such a low temperature has low etching resistance, it is necessary to provide a protective film over the insulating layer 116 in preparation for an etching process described later.
  • a first i-type amorphous semiconductor film 2 is formed on the entire second surface 1 b of the semiconductor substrate 1.
  • the method for forming the first i-type amorphous semiconductor film 2 is not particularly limited, and for example, a plasma CVD method can be used.
  • an i-type amorphous silicon film can be preferably used, but is not limited to an i-type amorphous silicon film.
  • a quality semiconductor film can also be used.
  • a first conductivity type amorphous semiconductor film 3 is formed on the first i-type amorphous semiconductor film 2.
  • the formation method of the 1st conductivity type amorphous semiconductor film 3 is not specifically limited, For example, plasma CVD method can be used.
  • the first conductive type amorphous semiconductor film 3 a p-type amorphous silicon film can be preferably used.
  • the first conductive type amorphous semiconductor film 3 is not limited to a p-type amorphous silicon film.
  • a semiconductor film can also be used.
  • boron can be used as the p-type impurity.
  • a stacked body of the first i-type amorphous semiconductor film 2 and the first conductive-type amorphous semiconductor film 3 is formed on the first conductive-type amorphous semiconductor film 3.
  • An etching mask 31 such as a photoresist having an opening at a portion to be etched in the thickness direction is formed.
  • the stacked body 51 of the first i-type amorphous semiconductor film 2 and the first conductive amorphous semiconductor film 3 is etched in the thickness direction using the etching mask 31 as a mask. As a result, a part of the second surface 1b of the semiconductor substrate 1 is exposed.
  • a second i-type amorphous semiconductor film 4 is formed so as to cover the exposed surface of the semiconductor substrate 1 and the first conductive amorphous semiconductor film 3.
  • the method for forming the second i-type amorphous semiconductor film 4 is not particularly limited, and for example, a plasma CVD method can be used.
  • an i-type amorphous silicon film can be suitably used, but is not limited to an i-type amorphous silicon film.
  • a conventionally known i-type amorphous silicon film is used.
  • a quality semiconductor film can also be used.
  • a second conductivity type amorphous semiconductor film 5 is formed on the second i-type amorphous semiconductor film 4.
  • the formation method of the 2nd conductivity type amorphous semiconductor film 5 is not specifically limited, For example, plasma CVD method can be used.
  • an n-type amorphous silicon film can be preferably used, but is not limited to an n-type amorphous silicon film.
  • a conventionally known n-type amorphous silicon film is used.
  • a semiconductor film can also be used.
  • phosphorus can be used as the n-type impurity.
  • a photoresist is formed only on a portion where the stacked body of the second i-type amorphous semiconductor film 4 and the second conductive type amorphous semiconductor film 5 is left on the back surface of the semiconductor substrate 1.
  • Etching mask 32 is formed.
  • a part of the stacked body 52 of the second i-type amorphous semiconductor film 4 and the second conductive amorphous semiconductor film 5 is etched in the thickness direction using the etching mask 32 as a mask.
  • the etching mask 32 is completely removed.
  • the first electrode 7 is formed so as to be in contact with the first conductive amorphous semiconductor film 3, and the second electrode is in contact with the second conductive amorphous semiconductor film 5. 8 is formed.
  • the formation method of the 1st electrode 7 and the 2nd electrode 8 is not specifically limited, For example, a vapor deposition method etc. can be used.
  • the solar cell described in Patent Document 1 is manufactured by simultaneously forming an i-type amorphous semiconductor layer 117i on the light receiving surface 100a and an i-type amorphous semiconductor layer 112i on the back surface 100b. This is because the i-type amorphous semiconductor layer 117i and the i-type amorphous semiconductor layer 112i are essential for improving the passivation of the light receiving surface 100a and the back surface 100b of the semiconductor substrate 100, respectively, and it is more efficient to form them simultaneously. It was because it was thought to be the target.
  • the present inventors in the solar cell described in Patent Document 1, the i-type amorphous semiconductor layer 117i on the light receiving surface 100a of the semiconductor substrate 100 emits light in a short wavelength region (wavelength of 300 nm or more and 500 nm or less). It has been found that it is easy to absorb and this does not increase the short circuit current density as expected.
  • an amorphous semiconductor film is not provided between the first surface 1a of the semiconductor substrate 1 and the dielectric film 6, and the first surface 1a and the dielectric are not provided. It has a structure in contact with the film 6. Thereby, the absorption of light in the short wavelength region by the amorphous semiconductor film on the light receiving surface side can be suppressed and the amount of light incident on the semiconductor substrate 1 can be increased, so that the heterojunction back contact cell of Embodiment 1 is Compared with the solar cell described in Patent Document 1, the short-circuit current density can be improved.
  • the difference between the refractive index of the semiconductor substrate 1 and the refractive index of the dielectric film 6 is preferably 1.0 or less, and preferably 0.8 or less. More preferred. Thereby, the dielectric film 6 can have higher passivation property.
  • the refractive index means an absolute refractive index.
  • FIG. 13 is a schematic cross-sectional view of the heterojunction back contact cell of the second embodiment.
  • the heterojunction back contact cell of Embodiment 2 is characterized by having a first dielectric film 6a in contact with the first surface 1a and a second dielectric film 6b provided on the first dielectric film 6a. There is.
  • the first dielectric film 6a and the second dielectric film 6b are each a dielectric film containing N and Si, and the content of Si in the second dielectric film 6b is the same as that in the first dielectric film 6a. Less than Si content. That is, in the dielectric film 6, the Si content is gradually reduced as the distance from the first surface 1 a of the semiconductor substrate 1 increases. As a result, the refractive index decreases in the order of the semiconductor substrate 1, the first dielectric film 6a, and the second dielectric film 6b.
  • the ratio of the flow rate of the Si source gas to the source material gas can be set lower than the ratio of the flow rate of the Si source gas to the N source gas.
  • the refractive index of the dielectric film 6 can be reduced stepwise as the distance from the first surface 1a of the semiconductor substrate 1 increases.
  • the antireflection function of the film 6 can be enhanced.
  • the difference between the refractive index of the semiconductor substrate 1 and the refractive index of the first dielectric film 6a is 1.0 or less, particularly 0.8 or less, the semiconductor substrate 1 is formed by the first dielectric film 6a.
  • the passivation property of the 1st surface 1a can be improved.
  • the dielectric film 6 includes the first dielectric film 6a and the second dielectric film 6b has been described.
  • the present invention is not limited to this, and the dielectric film 6 is a dielectric film having three or more layers. May be configured to be stacked.
  • the heterojunction back contact cell of Embodiment 3 is characterized in that the Si content in the dielectric film 6 is continuously reduced as the distance from the first surface 1a of the semiconductor substrate 1 increases.
  • the heterojunction back contact cell of Embodiment 3 is obtained by continuously decreasing the ratio of the flow rate of the Si source gas to the N source gas, for example, in the plasma CVD method when forming the dielectric film 6. Can be manufactured.
  • Embodiment 3 other than the above is the same as that of Embodiment 1 and Embodiment 2, and therefore description thereof will not be repeated.
  • a concavo-convex shape is formed on the first surface 1a which becomes the light receiving surface of the semiconductor substrate 1.
  • a first i-type amorphous semiconductor film 2 is formed on the entire second surface 1 b of the semiconductor substrate 1.
  • a first conductivity type amorphous semiconductor film 3 is formed on the first i-type amorphous semiconductor film 2.
  • an etching mask 31 is formed on the first conductive type amorphous semiconductor film 3.
  • the stacked body 51 of the first i-type amorphous semiconductor film 2 and the first conductive amorphous semiconductor film 3 is etched in the thickness direction using the etching mask 31 as a mask. As a result, a part of the second surface 1b of the semiconductor substrate 1 is exposed.
  • the second i-type amorphous semiconductor film 4 is formed so as to cover the exposed surface of the second surface 1 b of the semiconductor substrate 1 and the first conductive type amorphous semiconductor film 3. Form.
  • a second conductivity type amorphous semiconductor film 5 is formed on the second i-type amorphous semiconductor film 4.
  • etching mask 32 is formed only on the substrate.
  • a part of the stacked body 52 of the second i-type amorphous semiconductor film 4 and the second conductive amorphous semiconductor film 5 is etched in the thickness direction using the etching mask 32 as a mask.
  • the etching mask 32 is completely removed.
  • a dielectric film 6 is formed so as to be in contact with the entire surface of the first surface 1a of the semiconductor substrate 1.
  • the dielectric film 6 is preferably formed by setting the temperature of the semiconductor substrate 1 to 100 ° C. or more and 200 ° C. or less. This is because when the temperature of the semiconductor substrate 1 is set higher than 200 ° C. and the dielectric film 6 is formed, excessive escape of hydrogen from each amorphous semiconductor film provided on the second surface 1b side. This is because.
  • the first electrode 7 is formed so as to be in contact with the first conductive type amorphous silicon film 3, and the second electrode is formed so as to be in contact with the second conductive type amorphous silicon film 5. 8 is formed.
  • the process performed after forming the dielectric film 6 is a process of forming the first electrode 7 and a process of forming the second electrode 8. There is no need to provide a protective film having etching resistance. Therefore, according to the manufacturing method of Embodiment 4, the manufacturing process can be simplified, thereby reducing the manufacturing cost.
  • the dielectric film 6 is a single layer has been described.
  • the present invention is not limited to this, and the content of Si in the dielectric film 6 gradually increases as the distance from the first surface 1a of the semiconductor substrate 1 increases.
  • the dielectric film 6 may be formed after each film on the second surface 1b side is formed.
  • a concavo-convex shape was formed on the first surface 1a serving as the light receiving surface of the semiconductor substrate 1 which is an n-type single crystal silicon substrate after removal of slice damage.
  • the uneven shape of the first surface 1a is obtained by forming a texture mask on the entire second surface 1b of the semiconductor substrate 1 and then performing texture etching using an alkaline solution on the first surface 1a of the semiconductor substrate 1. Was formed. Then, after removing the texture mask from the semiconductor substrate 1, the semiconductor substrate 1 was cleaned.
  • a dielectric film 6 was formed so as to be in contact with the entire surface of the first surface 1 a of the semiconductor substrate 1.
  • the dielectric film 6, by a plasma CVD method, a laminate by laminating a the SiN x film of the SiN x film and the refractive index 1.8 of the refractive index 2.0 in this order from the first surface 1a side of the semiconductor substrate 1 Formed as. Thereafter, the semiconductor substrate 1 was cleaned.
  • a first i-type amorphous semiconductor film 2 made of an i-type amorphous silicon film was formed on the entire second surface 1b of the semiconductor substrate 1 by plasma CVD.
  • a first conductive type amorphous semiconductor film 3 made of an i type amorphous silicon film is formed on the entire surface of the first i type amorphous semiconductor film 2 by plasma CVD. .
  • a stacked body of the first i-type amorphous semiconductor film 2 and the first conductive-type amorphous semiconductor film 3 is formed on the first conductive-type amorphous semiconductor film 3.
  • An etching mask 31 made of a photoresist having an opening at a portion to be etched in the thickness direction was formed.
  • the first i-type amorphous semiconductor film 2 and the dielectric film 6 on the light receiving surface of the semiconductor substrate 1 and the etching mask 31 on the back surface of the semiconductor substrate 1 are used as masks.
  • a portion of the second surface 1b of the semiconductor substrate 1 was exposed by etching the stacked body 51 with the first conductive type amorphous semiconductor film 3 in the thickness direction. Then, after removing the etching mask 31, the semiconductor substrate 1 was cleaned.
  • the second surface made of the i-type amorphous silicon film is formed by plasma CVD so as to cover the exposed surface of the semiconductor substrate 1 and the first conductive type amorphous semiconductor film 3.
  • An i-type amorphous semiconductor film 4 was formed.
  • a second conductive amorphous semiconductor film 5 made of an n-type amorphous silicon film is formed on the second i-type amorphous semiconductor film 4 by plasma CVD. did.
  • a photoresist is formed only on a portion where the stacked body of the second i-type amorphous semiconductor film 4 and the second conductive type amorphous semiconductor film 5 is left on the back surface of the semiconductor substrate 1.
  • An etching mask 32 made of is formed.
  • a laminate of the second i-type amorphous semiconductor film 4 and the second conductive amorphous semiconductor film 5 By etching a part of 52 in the thickness direction, a part of the first conductive type amorphous semiconductor film 3 was exposed as shown in FIG. Thereafter, as shown in FIG. 12, the etching mask 32 was completely removed. Thereafter, the semiconductor substrate 1 was cleaned.
  • a metal film made of silver is deposited on the entire surface of the first conductive type amorphous semiconductor film 3 and the second conductive type amorphous semiconductor film 5, and an opening is formed at a location where the metal film is etched in the thickness direction.
  • the metal film was etched using the dielectric film 6 on the light-receiving surface of the semiconductor substrate 1 and the etching mask on the back surface of the semiconductor substrate 1 as a mask in a state where an etching mask made of a photoresist was formed on the metal film. .
  • the first electrode 7 in contact with the first conductive type amorphous semiconductor film 3 is formed, and the second electrode 8 is set in contact with the second conductive type amorphous semiconductor film 5. Formed.
  • the etching mask on the back surface of the semiconductor substrate 1 was removed.
  • the heterojunction back contact cell of the example was completed.
  • a concavo-convex shape is formed on the first surface 1a serving as the light-receiving surface of the semiconductor substrate 1 which is the n-type single crystal silicon substrate after removing the slice damage, After removing the texture mask from the substrate 1, the semiconductor substrate 1 was cleaned.
  • an i-type amorphous silicon film and n are formed from the side of the semiconductor substrate 1 so as to be in contact with the entire surface of the first surface 1a serving as the light receiving surface of the semiconductor substrate 1.
  • Type amorphous silicon films are deposited in this order by plasma CVD, and as shown in the schematic cross-sectional view of FIG. 24, an i-type amorphous silicon film and an n-type amorphous silicon film A laminate 61 made of was formed.
  • the first i-type amorphous semiconductor film 2 and the first conductivity-type amorphous semiconductor film 3 are formed on the entire surface of the second surface 1b which is the back surface of the semiconductor substrate 1.
  • the layers were sequentially deposited by the plasma CVD method (see FIG. 25).
  • a stacked body of the first i-type amorphous semiconductor film 2 and the first conductive-type amorphous semiconductor film 3 is formed on the first conductive-type amorphous semiconductor film 3.
  • An etching mask 31 made of a photoresist having an opening at a portion to be etched in the thickness direction was formed (see FIG. 26).
  • the etching mask 31 is also formed on the stacked body 61 of the i-type amorphous silicon film and the n-type amorphous silicon film on the light receiving surface of the semiconductor substrate 1.
  • the etching mask 31 as a mask, the stacked body of the first i-type amorphous semiconductor film 2 and the first conductive amorphous semiconductor film 3 is etched in the thickness direction. As a result, a part of the second surface 1b of the semiconductor substrate 1 was exposed (see FIG. 27). Then, after removing the etching masks 31 on the light receiving surface and the back surface of the semiconductor substrate 1, the semiconductor substrate 1 was cleaned.
  • the second surface made of the i-type amorphous silicon film is formed by plasma CVD so as to cover the exposed surface of the semiconductor substrate 1 and the first conductive type amorphous semiconductor film 3.
  • An i-type amorphous semiconductor film 4 is formed (see FIG. 28), and a second conductivity type non-crystalline film made of an n-type amorphous silicon film is formed on the second i-type amorphous semiconductor film 4 by plasma CVD.
  • a crystalline semiconductor film 5 was formed (see FIG. 29).
  • the photoresist is applied only to the portion where the stacked body of the second i-type amorphous semiconductor film 4 and the second conductive type amorphous semiconductor film 5 is left on the back surface of the semiconductor substrate 1.
  • An etching mask 32 made of (see FIG. 30) was formed.
  • the etching mask 32 is also formed on the stacked body 61 on the light receiving surface of the semiconductor substrate 1.
  • a part of the stacked body 52 of the second i-type amorphous semiconductor film 4 and the second conductive amorphous semiconductor film 5 is etched in the thickness direction using the etching mask 32 as a mask.
  • a part of the first conductive type amorphous semiconductor film 3 was exposed (see FIG. 31). Then, after removing the etching masks 32 on the light receiving surface and the back surface of the semiconductor substrate 1, the semiconductor substrate 1 was cleaned.
  • plasma CVD is performed on a stacked body 61 of an i-type amorphous silicon film and an n-type amorphous silicon film on the light receiving surface of the semiconductor substrate 1.
  • SiN x film of the SiN x film and the refractive index 1.8 of the refractive index 2.0 by stacking of a stack 61 side in this order, the SiN x film and the refractive index of the refractive index 2.0 1.
  • a dielectric film 6 composed of a stack of 8 SiN x films was formed.
  • the first conductivity type amorphous film is formed with an etching mask 33 made of a photoresist formed on the entire surface of the dielectric film 6 on the light receiving surface of the semiconductor substrate 1.
  • a metal film 9 made of silver was deposited on the entire surface of the semiconductor film 3 and the second conductive type amorphous semiconductor film 5.
  • an etching mask 33 made of a photoresist having an opening at a location where the metal film 9 is etched in the thickness direction was formed on the metal film 9.
  • FIG. 34 an etching mask 33 made of a photoresist having an opening at a location where the metal film 9 is etched in the thickness direction was formed on the metal film 9.
  • the metal film 9 is etched using the etching mask 33 on the light receiving surface and the back surface of the semiconductor substrate 1 as a mask, so that the first conductivity type amorphous semiconductor film is obtained. 3 was formed, and the second electrode 8 was formed in contact with the second conductive type amorphous semiconductor film 5.
  • the etching masks 33 on the light receiving surface and the back surface of the semiconductor substrate 1 were removed after the first electrode 7 and the second electrode 8 were formed. Thus, the heterojunction back contact cell of the comparative example was completed.
  • FIG. 36 shows the spectral sensitivities of the light receiving surfaces of the heterojunction back contact cells of the example and the comparative example with respect to light having a wavelength of 300 nm to 500 nm, and the horizontal axis of FIG. 36 represents the wavelength [nm].
  • the vertical axis represents the external quantum efficiency (EQE) [%].
  • the external quantum efficiency means the ratio [%] of the number of carrier pairs (electron and hole pairs) generated for one photon of incident light.
  • the heterojunction back contact cell of the example has higher spectral sensitivity of light on the short wavelength side than the heterojunction back contact cell of the comparative example.
  • the external quantum efficiency of the heterojunction back contact cell of the example was about 80%
  • the external quantum efficiency of the heterojunction back contact cell of the comparative example was about 60%, there was a large difference of about 20%.
  • the SiN x C y O z F w H v film has the same physical properties as the SiN x film. , even in the case of forming a direct SiN x C y O z F w H v film on the light receiving surface of the semiconductor substrate 1 in place of the SiN x film, the same effect as in the case of forming a the SiN x film described above is obtained Conceivable.
  • a method for manufacturing a heterojunction back contact cell According to the method for manufacturing a heterojunction back contact cell of the embodiment disclosed herein, a heterojunction back contact cell having excellent short-circuit current density characteristics can be manufactured.
  • the step of forming the dielectric film includes the first conductive type amorphous semiconductor film and the second conductive type on the second surface side. It is preferably performed before the step of forming the type amorphous semiconductor film.
  • the dielectric film can be used as a protective film having etching resistance, the step of forming the protective film having etching resistance before the etching process can be reduced, and thus the heterojunction back contact cell. The manufacturing cost can be reduced.
  • the step of forming a dielectric film includes a first conductive type amorphous semiconductor film and a second conductive type on the second surface side.
  • the step of forming the dielectric film is preferably performed at 450 ° C. or higher and 500 ° C. or lower. In this case, since the etching resistance of the dielectric film can be increased, it is not necessary to form a protective film for protecting the dielectric film in the manufacturing process. Therefore, since the manufacturing process can be simplified, the manufacturing cost of the heterojunction back contact cell can be reduced.
  • the step of forming the dielectric film includes the first conductive type amorphous semiconductor film and the second conductive type on the second surface side. It is preferably performed after the step of forming the type amorphous semiconductor film. In this case, since it is necessary to form a protective film having etching resistance after the dielectric film is formed, the manufacturing cost of the heterojunction back contact cell can be reduced.
  • the step of forming a dielectric film includes a first conductive type amorphous semiconductor film and a second conductive type on the second surface side.
  • the step of forming the dielectric film is preferably performed at 100 ° C. or higher and 200 ° C. or lower. Also in this case, the manufacturing cost can be reduced.
  • the dielectric content of the dielectric film decreases as the distance from the first surface increases. In this case, the antireflection function and the passivation property of the dielectric film can be enhanced mutually.
  • the silicon content is preferably continuously reduced as the distance from the first surface increases. Also in this case, the antireflection function and the passivation property of the dielectric film can be enhanced mutually.
  • the silicon content is preferably reduced stepwise as the distance from the first surface increases. Also in this case, the antireflection function and the passivation property of the dielectric film can be enhanced mutually.
  • the dielectric film preferably further includes one or more atoms selected from the group consisting of oxygen, carbon, and fluorine. Also in this case, a heterojunction back contact cell having excellent short-circuit current density characteristics can be manufactured.
  • the composition of the dielectric film is preferably represented by the formula of SiN x C y O z F w H v. Also in this case, a heterojunction back contact cell having excellent short-circuit current density characteristics can be manufactured.
  • the step of forming the first conductive type amorphous semiconductor film and the second conductive type amorphous semiconductor film is performed on a semiconductor substrate. Forming a first i-type amorphous semiconductor film on the second surface side, forming a first conductivity-type amorphous semiconductor film on the first i-type amorphous semiconductor film, Removing a part of the stack of the first i-type amorphous semiconductor film and the first conductive amorphous semiconductor film, and forming the second i-type amorphous semiconductor film on the second surface side And a step of forming a second conductivity type amorphous semiconductor film on the second i-type amorphous semiconductor film. Also in this case, a heterojunction back contact cell having excellent short-circuit current density characteristics can be manufactured.
  • the first i-type amorphous semiconductor film preferably contains i-type amorphous silicon. Also in this case, a heterojunction back contact cell having excellent short-circuit current density characteristics can be manufactured.
  • the second i-type amorphous semiconductor film preferably contains i-type amorphous silicon. Also in this case, a heterojunction back contact cell having excellent short-circuit current density characteristics can be manufactured.
  • the semiconductor substrate preferably includes n-type crystalline silicon. Also in this case, a heterojunction back contact cell having excellent short-circuit current density characteristics can be manufactured.
  • a heterojunction back contact cell includes a semiconductor substrate of a first conductivity type or a second conductivity type, and nitrogen provided in contact with a first surface of the semiconductor substrate.
  • a heterojunction back contact cell comprising a first electrode on the first conductive type amorphous semiconductor film and a second electrode on the second conductive type amorphous semiconductor film.
  • the dielectric film preferably has a silicon content that decreases as the distance from the first surface increases. In this case, the antireflection function and the passivation property of the dielectric film can be enhanced mutually.
  • the silicon content is preferably continuously reduced as the distance from the first surface increases. Also in this case, the antireflection function and the passivation property of the dielectric film can be enhanced mutually.
  • the silicon content is reduced stepwise as the distance from the first surface increases. Also in this case, the antireflection function and the passivation property of the dielectric film can be enhanced mutually.
  • the dielectric film preferably further includes one or more selected from the group consisting of oxygen, carbon, and fluorine. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
  • the composition of the dielectric film is preferably represented by the formula of SiN x C y O z F w H v. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
  • a heterojunction back contact cell includes a first i-type amorphous semiconductor film between a semiconductor substrate and a first conductive amorphous semiconductor film, a semiconductor substrate, It is preferable to further include a second i-type amorphous semiconductor film between the second conductive type amorphous semiconductor film. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
  • the first i-type amorphous semiconductor film preferably includes i-type amorphous silicon. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
  • the second i-type amorphous semiconductor film preferably contains i-type amorphous silicon. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
  • the semiconductor substrate and the first i-type amorphous semiconductor film are in contact with each other. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
  • the semiconductor substrate and the second i-type amorphous semiconductor film are in contact with each other. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
  • the first i-type amorphous semiconductor film and the first conductive amorphous semiconductor film are in contact with each other. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
  • the second i-type amorphous semiconductor film and the second conductive amorphous semiconductor film are in contact with each other. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
  • the second i-type amorphous semiconductor film is interposed between the first conductive amorphous semiconductor film and the second conductive amorphous semiconductor film.
  • the end of the semiconductor film is preferably located. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
  • the end of the second i-type amorphous semiconductor film is formed of the first conductive type amorphous semiconductor film and the second conductive type amorphous semiconductor. It is preferable to be in contact with each of the crystalline semiconductor films. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
  • the semiconductor substrate preferably contains n-type crystalline silicon. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
  • the embodiment disclosed herein can be suitably used for a heterojunction back contact cell and a manufacturing method thereof.
  • 1,100 semiconductor substrate 1a first surface, 1b second surface, 2nd first i-type amorphous semiconductor film, 3rd first conductivity type amorphous semiconductor film, 4th second i-type amorphous Semiconductor film, 5 Second conductive type amorphous semiconductor film, 6 Dielectric film, 6a First dielectric film, 6b Second dielectric film, 7 First electrode, 8 Second electrode, 9 Metal film, 31, 32 33, etching mask, 51, 52, 61 laminate, 100a light receiving surface, 100b back surface, 112 IN laminate, 112i, 113i, 117i, 121, 124 i-type amorphous semiconductor layer, 112n, 117n, 122 n-type non-layer Crystalline semiconductor layer, 113 IP stack, 113p, 125 p-type amorphous semiconductor layer, 114 n-side electrode, 115 p-side electrode, 116, 118, 123 insulating layer, 119 stack, 119a, 119b, 1 9c, 119

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Abstract

This method for manufacturing a heterojunction back contact cell comprises: a step for forming a dielectric film (6) so as to be in contact with a first surface (1a) of a semiconductor substrate (1), said dielectric film (6) containing nitrogen and silicon; a step for forming an amorphous semiconductor film (3) of a first conductivity type and an amorphous semiconductor film (5) of a second conductivity type on a second surface (1b) of the semiconductor substrate (1), said second surface (1b) being on the reverse side of the first surface (1a); a step for forming a first electrode (7) on the amorphous semiconductor film (3) of a first conductivity type; and a step for forming a second electrode (8) on the amorphous semiconductor film (5) of a second conductivity type.

Description

ヘテロバックコンタクト型太陽電池とその製造方法Hetero back contact solar cell and method of manufacturing the same
　本発明は、ヘテロバックコンタクト型太陽電池とその製造方法に関する。 The present invention relates to a hetero back contact solar cell and a method for manufacturing the same.
　太陽光エネルギを電気エネルギに直接変換する太陽電池は、近年、特に、地球環境問題の観点から、次世代のエネルギ源としての期待が急激に高まっている。太陽電池には、化合物半導体または有機材料を用いたものなど様々な種類のものがあるが、現在、主流となっているのはシリコン結晶を用いたものである。なかでも、現在、最も多く製造および販売されている太陽電池は、太陽光が入射する側の面である受光面と受光面の反対側である裏面とにそれぞれ電極が形成された構造のものである。 In recent years, expectations for solar cells that directly convert solar energy into electrical energy have increased rapidly, especially from the viewpoint of global environmental problems. There are various types of solar cells such as those using compound semiconductors or organic materials, but currently, the mainstream is using silicon crystals. Of these, the most manufactured and sold solar cells have a structure in which electrodes are formed on the light receiving surface on the side where sunlight enters and the back surface on the opposite side of the light receiving surface, respectively. is there.
　しかしながら、受光面に電極を形成した場合には、電極における太陽光の反射および吸収があることから、電極の面積分だけ入射する太陽光の量が減少する。そのため、裏面のみに電極を形成した太陽電池の開発が進められている（たとえば特許文献１参照）。 However, when an electrode is formed on the light receiving surface, sunlight is reflected and absorbed by the electrode, so that the amount of incident sunlight is reduced by the area of the electrode. For this reason, development of solar cells in which electrodes are formed only on the back surface is being promoted (see, for example, Patent Document 1).
　図３７に、特許文献１に記載の太陽電池の模式的な断面図を示す。図３７に示される太陽電池においては、ｎ型の単結晶シリコンからなる半導体基板１００の裏面１００ｂの一部に、水素を含むｉ型のアモルファスシリコンからなるｉ型非晶質半導体層１１２ｉと水素を含むｎ型のアモルファスシリコンからなるｎ型非晶質半導体層１１２ｎとのＩＮ積層体１１２が設けられている。また、ｎ型非晶質半導体層１１２ｎ上に酸化ケイ素、窒化ケイ素または酸窒化ケイ素などからなる絶縁層１１８が設けられている。 FIG. 37 shows a schematic cross-sectional view of the solar cell described in Patent Document 1. In the solar cell shown in FIG. 37, an i-type amorphous semiconductor layer 112i made of i-type amorphous silicon containing hydrogen and hydrogen are applied to a part of the back surface 100b of the semiconductor substrate 100 made of n-type single crystal silicon. An IN stacked body 112 with an n-type amorphous semiconductor layer 112n made of n-type amorphous silicon is provided. An insulating layer 118 made of silicon oxide, silicon nitride, silicon oxynitride, or the like is provided over the n-type amorphous semiconductor layer 112n.
　また、半導体基板１００の裏面１００ｂのＩＮ積層体１１２の非形成面、ならびにＩＮ積層体１１２上の絶縁層１１８の積層体を覆うように、水素を含むｉ型のアモルファスシリコンからなるｉ型非晶質半導体層１１３ｉと水素を含むｐ型のアモルファスシリコンからなるｐ型非晶質半導体層１１３ｐとのＩＰ積層体１１３が設けられている。 In addition, an i-type amorphous film made of i-type amorphous silicon containing hydrogen so as to cover the non-formation surface of the IN stacked body 112 on the back surface 100 b of the semiconductor substrate 100 and the stacked body of the insulating layer 118 on the IN stacked body 112. There is provided an IP stacked body 113 of a crystalline semiconductor layer 113i and a p-type amorphous semiconductor layer 113p made of p-type amorphous silicon containing hydrogen.
　また、ｎ型非晶質半導体層１１２ｎの表面の絶縁層１１８の非形成面、ならびにＩＰ積層体１１３を覆うように第１の導電層１１９ａ、第２の導電層１１９ｂ、第３の導電層１１９ｃおよび第４の導電層１１９ｄが順次積層されることにより構成された導電層の積層体１１９が設けられている。また、導電層の積層体１１９には絶縁層１１８の表面まで至る溝１２０が形成されており、これにより、ＩＮ積層体１１２上のｎ電極１１４と、ＩＰ積層体１１３上のｐ電極１１５とが分離されている。 The first conductive layer 119a, the second conductive layer 119b, and the third conductive layer 119c are formed so as to cover the non-formation surface of the insulating layer 118 on the surface of the n-type amorphous semiconductor layer 112n and the IP stacked body 113. In addition, a conductive layer stack 119 is formed by sequentially stacking the fourth conductive layer 119d. In addition, a groove 120 extending to the surface of the insulating layer 118 is formed in the stacked body 119 of the conductive layer, whereby an n electrode 114 on the IN stacked body 112 and a p electrode 115 on the IP stacked body 113 are formed. It is separated.
　さらに、半導体基板１００の受光面１００ａ上には、水素を含むｉ型のアモルファスシリコンからなるｉ型非晶質半導体層１１７ｉと、水素を含むｎ型のアモルファスシリコンからなるｎ型非晶質半導体層１１７ｎと、酸化ケイ素、窒化ケイ素または酸窒化ケイ素などからなる絶縁層１１６とが設けられている。 Further, on the light receiving surface 100a of the semiconductor substrate 100, an i-type amorphous semiconductor layer 117i made of i-type amorphous silicon containing hydrogen and an n-type amorphous semiconductor layer made of n-type amorphous silicon containing hydrogen. 117n and an insulating layer 116 made of silicon oxide, silicon nitride, silicon oxynitride, or the like are provided.
　特許文献１に記載の太陽電池は、半導体基板１００の受光面１００ａ上のｉ型非晶質半導体層１１７ｉと、半導体基板１０の裏面１００ｂ上のｉ型非晶質半導体層１１２ｉとが同時に形成されて作製される（たとえば特許文献１の段落［００４２］参照）。 In the solar cell described in Patent Document 1, an i-type amorphous semiconductor layer 117 i on the light receiving surface 100 a of the semiconductor substrate 100 and an i-type amorphous semiconductor layer 112 i on the back surface 100 b of the semiconductor substrate 10 are formed simultaneously. (See, for example, paragraph [0042] of Patent Document 1).
特開２０１２－０４９１９３号公報JP 2012-049193 A
　しかしながら、特許文献１に記載の太陽電池においては、短絡電流密度（Ｊsc）が低かったため、短絡電流密度の向上が求められていた。 However, in the solar cell described in Patent Document 1, since the short-circuit current density (J sc ) was low, an improvement in the short-circuit current density was demanded.
　ここで開示された実施の形態は、半導体基板の第１の面に接するように、窒素と珪素とを含む誘電体膜を形成する工程と、半導体基板の第１の面と反対側の第２の面側に、第１導電型非晶質半導体膜および第２導電型非晶質半導体膜を形成する工程と、第１導電型非晶質半導体膜上に第１電極を形成する工程と、第２導電型非晶質半導体膜上に第２電極を形成する工程と、を含む、ヘテロ接合型バックコンタクトセルの製造方法である。 The embodiment disclosed herein includes a step of forming a dielectric film containing nitrogen and silicon so as to be in contact with the first surface of the semiconductor substrate, and a second surface opposite to the first surface of the semiconductor substrate. Forming a first conductive type amorphous semiconductor film and a second conductive type amorphous semiconductor film on the surface side, forming a first electrode on the first conductive type amorphous semiconductor film, Forming a second electrode on the second conductive type amorphous semiconductor film. A method for manufacturing a heterojunction back contact cell.
　また、ここで開示された実施の形態は、第１導電型または第２導電型の半導体基板と、半導体基板の第１の面に接するように設けられた、窒素と珪素とを含む誘電体膜と、半導体基板の第１の面と反対側の第２の面側に設けられた、第１導電型非晶質半導体膜および第２導電型非晶質半導体膜と、第１導電型非晶質半導体膜上の第１電極と、第２導電型非晶質半導体膜上の第２電極と、を備える、ヘテロ接合型バックコンタクトセルである。 The embodiment disclosed herein is a dielectric film containing a semiconductor substrate of a first conductivity type or a second conductivity type, and nitrogen and silicon provided in contact with the first surface of the semiconductor substrate. A first conductivity type amorphous semiconductor film and a second conductivity type amorphous semiconductor film provided on a second surface side opposite to the first surface of the semiconductor substrate, and a first conductivity type amorphous semiconductor A heterojunction back contact cell comprising a first electrode on a porous semiconductor film and a second electrode on a second conductive amorphous semiconductor film.
　ここで開示された実施の形態によれば、短絡電流密度の特性に優れたヘテロ接合型バックコンタクトセルの製造方法およびヘテロ接合型バックコンタクトセルを提供することができる。 According to the embodiment disclosed herein, it is possible to provide a method for manufacturing a heterojunction back contact cell and a heterojunction back contact cell having excellent short-circuit current density characteristics.
実施形態１のヘテロ接合型バックコンタクトセルの模式的な断面図である。FIG. 3 is a schematic cross-sectional view of the heterojunction back contact cell of Embodiment 1. 実施形態１のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部を図解する模式的な断面図である。FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment. 実施形態１のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部を図解する模式的な断面図である。FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment. 実施形態１のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部を図解する模式的な断面図である。FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment. 実施形態１のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部を図解する模式的な断面図である。FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment. 実施形態１のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部を図解する模式的な断面図である。FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment. 実施形態１のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部を図解する模式的な断面図である。FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment. 実施形態１のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部を図解する模式的な断面図である。FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment. 実施形態１のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部を図解する模式的な断面図である。FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment. 実施形態１のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部を図解する模式的な断面図である。FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment. 実施形態１のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部を図解する模式的な断面図である。FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment. 実施形態１のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部を図解する模式的な断面図である。FIG. 3 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment. 実施形態２のヘテロ接合型バックコンタクトセルの模式的な断面図である。6 is a schematic cross-sectional view of a heterojunction back contact cell of Embodiment 2. FIG. 実施形態４のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部を図解する模式的な断面図である。FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4. 実施形態４のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部を図解する模式的な断面図である。FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4. 実施形態４のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部を図解する模式的な断面図である。FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4. 実施形態４のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部を図解する模式的な断面図である。FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4. 実施形態４のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部を図解する模式的な断面図である。FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4. 実施形態４のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部を図解する模式的な断面図である。FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4. 実施形態４のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部を図解する模式的な断面図である。FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4. 実施形態４のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部を図解する模式的な断面図である。FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4. 実施形態４のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部を図解する模式的な断面図である。FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4. 実施形態４のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部を図解する模式的な断面図である。FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 4. 比較例のヘテロ接合型バックコンタクトセルの製造工程の一部を図解する模式的な断面図である。It is typical sectional drawing illustrating a part of manufacturing process of the heterojunction type back contact cell of a comparative example. 比較例のヘテロ接合型バックコンタクトセルの製造工程の一部を図解する模式的な断面図である。It is typical sectional drawing illustrating a part of manufacturing process of the heterojunction type back contact cell of a comparative example. 比較例のヘテロ接合型バックコンタクトセルの製造工程の一部を図解する模式的な断面図である。It is typical sectional drawing illustrating a part of manufacturing process of the heterojunction type back contact cell of a comparative example. 比較例のヘテロ接合型バックコンタクトセルの製造工程の一部を図解する模式的な断面図である。It is typical sectional drawing illustrating a part of manufacturing process of the heterojunction type back contact cell of a comparative example. 比較例のヘテロ接合型バックコンタクトセルの製造工程の一部を図解する模式的な断面図である。It is typical sectional drawing illustrating a part of manufacturing process of the heterojunction type back contact cell of a comparative example. 比較例のヘテロ接合型バックコンタクトセルの製造工程の一部を図解する模式的な断面図である。It is typical sectional drawing illustrating a part of manufacturing process of the heterojunction type back contact cell of a comparative example. 比較例のヘテロ接合型バックコンタクトセルの製造工程の一部を図解する模式的な断面図である。It is typical sectional drawing illustrating a part of manufacturing process of the heterojunction type back contact cell of a comparative example. 比較例のヘテロ接合型バックコンタクトセルの製造工程の一部を図解する模式的な断面図である。It is typical sectional drawing illustrating a part of manufacturing process of the heterojunction type back contact cell of a comparative example. 比較例のヘテロ接合型バックコンタクトセルの製造工程の一部を図解する模式的な断面図である。It is typical sectional drawing illustrating a part of manufacturing process of the heterojunction type back contact cell of a comparative example. 比較例のヘテロ接合型バックコンタクトセルの製造工程の一部を図解する模式的な断面図である。It is typical sectional drawing illustrating a part of manufacturing process of the heterojunction type back contact cell of a comparative example. 比較例のヘテロ接合型バックコンタクトセルの製造工程の一部を図解する模式的な断面図である。It is typical sectional drawing illustrating a part of manufacturing process of the heterojunction type back contact cell of a comparative example. 比較例のヘテロ接合型バックコンタクトセルの製造工程の一部を図解する模式的な断面図である。It is typical sectional drawing illustrating a part of manufacturing process of the heterojunction type back contact cell of a comparative example. 波長３００ｎｍ～５００ｎｍの光に対する実施例および比較例のヘテロ接合型バックコンタクトセルの受光面の分光感度の測定結果である。3 is a measurement result of spectral sensitivity of a light receiving surface of a heterojunction back contact cell of an example and a comparative example with respect to light having a wavelength of 300 nm to 500 nm. 特許文献１に記載の太陽電池の模式的な断面図である。2 is a schematic cross-sectional view of a solar cell described in Patent Document 1. FIG.
　［実施形態１］
　＜ヘテロ接合型バックコンタクトセルの構成＞
　図１に、実施形態１のヘテロ接合型バックコンタクトセルの模式的な断面図を示す。実施形態１のヘテロ接合型バックコンタクトセルは、ｎ型単結晶シリコン基板である半導体基板１を有する。半導体基板１の第１の面１ａ（受光面）には、凹凸形状が形成されており、第１の面１ａと接するように、窒素（Ｎ）と珪素（Ｓｉ）とを含む誘電体膜６が設けられている。 [Embodiment 1]
<Configuration of heterojunction back contact cell>
FIG. 1 is a schematic cross-sectional view of the heterojunction back contact cell of the first embodiment. The heterojunction back contact cell of Embodiment 1 has a semiconductor substrate 1 which is an n-type single crystal silicon substrate. The first surface 1a (light-receiving surface) of the semiconductor substrate 1 has an uneven shape, and a dielectric film 6 containing nitrogen (N) and silicon (Si) is in contact with the first surface 1a. Is provided.
　ＮとＳｉとを含む誘電体膜６としては、たとえば窒化シリコンを含む膜を用いることができる。また、誘電体膜６は、ＮおよびＳｉ以外にも、酸素（Ｏ）、炭素（Ｃ）およびフッ素（Ｆ）からなる群より選択される１つ以上の原子を含んでいてもよい。 As the dielectric film 6 containing N and Si, for example, a film containing silicon nitride can be used. The dielectric film 6 may contain one or more atoms selected from the group consisting of oxygen (O), carbon (C), and fluorine (F) in addition to N and Si.
　誘電体膜６の組成は、たとえばＳｉＮxＣyＯzＦwＨv（０＜ｘ、０≦ｙ、０≦ｚ、０≦ｗおよび０≦ｖ）（以下、「ＳｉＮxＣyＯzＦwＨv」という。）の式で表すことができる。たとえば、誘電体膜６がＮとＳｉとからなる場合には、誘電体膜６の組成は「ＳｉＮx」の式で表すことができる。また、たとえば、誘電体膜６が、ＮおよびＳｉとＯとからなる場合には、誘電体膜６の組成は、「ＳｉＮxＯz」の式で表すことができる。誘電体膜６の組成は、二次イオン質量分析法（ＳＩＭＳ；Secondary　Ion　Mass　Spectrometry）によって誘電体膜６の各原子の含有量を測定することによって求めることができる。 The composition of the dielectric film 6 is, for example, SiN x C y O z F w H v (0 <x, 0 ≦ y, 0 ≦ z, 0 ≦ w and 0 ≦ v) (hereinafter, “SiN x C y O z Fw Hv ")). For example, when the dielectric film 6 is made of N and Si, the composition of the dielectric film 6 can be expressed by the formula “SiN x ”. Further, for example, when the dielectric film 6 is made of N, Si, and O, the composition of the dielectric film 6 can be expressed by the formula “SiN x O z ”. The composition of the dielectric film 6 can be obtained by measuring the content of each atom of the dielectric film 6 by secondary ion mass spectrometry (SIMS).
　また、誘電体膜６の厚さは特に制限されないが、たとえば６０ｎｍ以上１５０ｎｍ以下とすることができる。なお、第１の面１ａと誘電体膜６との間の少なくとも一部の領域には、シリコンの自然酸化膜が存在していてもよい。自然酸化膜の厚さは、たとえば５ｎｍ以下であり、好ましくは１ｎｍ以下である。 Further, the thickness of the dielectric film 6 is not particularly limited, but can be, for example, 60 nm or more and 150 nm or less. Note that a natural oxide film of silicon may exist in at least a part of the region between the first surface 1a and the dielectric film 6. The thickness of the natural oxide film is, for example, 5 nm or less, preferably 1 nm or less.
　半導体基板１の第１の面１ａと反対側の第２の面１ｂ（裏面）には、第２の面１ｂに接する、第１のｉ型非晶質半導体膜２と第２のｉ型非晶質半導体膜４とが設けられている。実施形態１において、第１のｉ型非晶質半導体膜２および第２のｉ型非晶質半導体膜４は、それぞれ、ｉ型非晶質シリコン膜である。 On the second surface 1b (back surface) opposite to the first surface 1a of the semiconductor substrate 1, the first i-type amorphous semiconductor film 2 and the second i-type non-contact are in contact with the second surface 1b. A crystalline semiconductor film 4 is provided. In the first embodiment, each of the first i-type amorphous semiconductor film 2 and the second i-type amorphous semiconductor film 4 is an i-type amorphous silicon film.
　なお、本明細書において「ｉ型」とは、完全な真性の状態だけでなく、十分に低濃度（ｎ型不純物濃度が１×１０15個／ｃｍ3未満、かつｐ型不純物濃度が１×１０15個／ｃｍ3未満）であればｎ型またはｐ型の不純物が混入された状態のものも含む意味である。また、本明細書において「ｎ型」はｎ型不純物濃度が１×１０15個／ｃｍ3以上の状態を意味し、「ｐ型」はｐ型不純物濃度が１×１０15個／ｃｍ3以上の状態を意味する。ｎ型不純物濃度およびｐ型不純物濃度は、たとえば二次イオン質量分析法によって測定することができる。 In the present specification, “i-type” means not only a completely intrinsic state but also a sufficiently low concentration (the n-type impurity concentration is less than 1 × 10 15 / cm 3 and the p-type impurity concentration is 1 × (Less than 10 15 / cm 3 ) is meant to include n-type or p-type impurities. In this specification, “n-type” means a state where the n-type impurity concentration is 1 × 10 15 / cm 3 or more, and “p-type” means that the p-type impurity concentration is 1 × 10 15 / cm 3 or more. Means the state. The n-type impurity concentration and the p-type impurity concentration can be measured by, for example, secondary ion mass spectrometry.
　また、本明細書において「非晶質シリコン」には、シリコン原子の未結合手が水素で終端されていない非晶質シリコンだけでなく、水素化非晶質シリコンなどのシリコン原子の未結合手が水素で終端されたものも含まれるものとする。 In this specification, “amorphous silicon” includes not only amorphous silicon in which the dangling bonds of silicon atoms are not terminated with hydrogen, but also dangling bonds of silicon atoms such as hydrogenated amorphous silicon. In which is terminated with hydrogen.
　第１のｉ型非晶質半導体膜２上には、第１のｉ型非晶質半導体膜２に接するｐ型非晶質シリコン膜である第１導電型非晶質半導体膜３が設けられている。また、第２のｉ型非晶質半導体膜４上には、第２のｉ型非晶質半導体膜４に接するｎ型非晶質シリコン膜である第２導電型非晶質半導体膜５が設けられている。 On the first i-type amorphous semiconductor film 2, a first conductive type amorphous semiconductor film 3 which is a p-type amorphous silicon film in contact with the first i-type amorphous semiconductor film 2 is provided. ing. On the second i-type amorphous semiconductor film 4, a second conductive amorphous semiconductor film 5, which is an n-type amorphous silicon film in contact with the second i-type amorphous semiconductor film 4, is provided. Is provided.
　第２のｉ型非晶質半導体膜４と第２導電型非晶質半導体膜５との積層体５２の端部は、第１のｉ型非晶質半導体膜２と第１導電型非晶質半導体膜３との積層体５１の端部を覆っている。そのため、第１導電型非晶質半導体膜３と第２導電型非晶質半導体膜５との間には第２のｉ型非晶質半導体膜４の端部が位置している。第２のｉ型非晶質半導体膜４の端部は、第１導電型非晶質半導体膜３および第２導電型非晶質半導体膜５の両方と接している。これにより、第１導電型非晶質半導体膜３と第２導電型非晶質半導体膜５とは第２のｉ型非晶質半導体膜４によって分離されている。 The end of the stacked body 52 of the second i-type amorphous semiconductor film 4 and the second conductivity-type amorphous semiconductor film 5 is the first i-type amorphous semiconductor film 2 and the first conductivity-type amorphous. The edge part of the laminated body 51 with the quality semiconductor film 3 is covered. Therefore, the end of the second i-type amorphous semiconductor film 4 is located between the first conductive type amorphous semiconductor film 3 and the second conductive type amorphous semiconductor film 5. The end of the second i-type amorphous semiconductor film 4 is in contact with both the first conductive type amorphous semiconductor film 3 and the second conductive type amorphous semiconductor film 5. As a result, the first conductive amorphous semiconductor film 3 and the second conductive amorphous semiconductor film 5 are separated by the second i-type amorphous semiconductor film 4.
　第１導電型非晶質半導体膜３上には、第１導電型非晶質半導体膜３に接する第１電極７が設けられている。また、第２導電型非晶質半導体膜５上には、第２導電型非晶質半導体膜５に接する第２電極８が設けられている。第１電極７および第２電極８としては、アルミニウムまたは銀などを用いることができる。 On the first conductive type amorphous semiconductor film 3, a first electrode 7 in contact with the first conductive type amorphous semiconductor film 3 is provided. A second electrode 8 that is in contact with the second conductive type amorphous semiconductor film 5 is provided on the second conductive type amorphous semiconductor film 5. As the first electrode 7 and the second electrode 8, aluminum, silver, or the like can be used.
　＜ヘテロ接合型バックコンタクトセルの製造方法＞
　以下、図２～図１２の模式的断面図を参照して、実施形態１のヘテロ接合型バックコンタクトセルの製造方法の一例について説明する。 <Method for manufacturing heterojunction back contact cell>
Hereinafter, an example of a method for manufacturing the heterojunction back contact cell of Embodiment 1 will be described with reference to the schematic cross-sectional views of FIGS.
　まず、図２に示すように、半導体基板１の受光面となる第１の面１ａに凹凸形状を形成する。第１の面１ａの凹凸形状は、たとえば、半導体基板１の第２の面１ｂの全面にテクスチャマスクを形成した後に、半導体基板１の第１の面１ａをテクスチャエッチングすることにより形成することができる。テクスチャマスクとしては、たとえば、窒化シリコンまたは酸化シリコンを用いることができる。また、テクスチャエッチングに用いられるエッチャントとしては、たとえば、シリコンを溶解可能なアルカリ溶液を用いることができる。 First, as shown in FIG. 2, an uneven shape is formed on the first surface 1 a serving as the light receiving surface of the semiconductor substrate 1. The uneven shape of the first surface 1a can be formed, for example, by texture-etching the first surface 1a of the semiconductor substrate 1 after forming a texture mask over the entire second surface 1b of the semiconductor substrate 1. it can. For example, silicon nitride or silicon oxide can be used as the texture mask. Moreover, as an etchant used for texture etching, for example, an alkaline solution capable of dissolving silicon can be used.
　次に、図３に示すように、半導体基板１の第１の面１ａの全面に接するように、誘電体膜６を形成する。誘電体膜６は、たとえばプラズマＣＶＤ（Chemical　Vapor　Deposition）法により形成することができる。 Next, as shown in FIG. 3, a dielectric film 6 is formed so as to be in contact with the entire surface of the first surface 1 a of the semiconductor substrate 1. The dielectric film 6 can be formed, for example, by a plasma CVD (Chemical Vapor Deposition) method.
　たとえば、誘電体膜６としてＳｉＮx膜を形成する場合には、Ｓｉの原料ガスとしてＳｉＨ4を用いることができ、Ｎの原料ガスとしてＮ2およびＮＨ3の少なくとも一方を用いることができる。また、たとえば誘電体膜６としてＳｉＮxＯz膜を形成する場合には、Ｓｉの原料ガスとしてＳｉＨ4と、Ｎの原料ガスとしてのＮ2およびＮＨ3の少なくとも一方と、酸素の原料ガスとしてのＯ2ガスを用いることができる。なお、誘電体膜６中のＣ、ＯおよびＦのそれぞれは、これらの各原子を含む原料ガスを用いて意図的に導入してもよく、原料ガスを用いずに不可避不純物的に導入されてもよい。 For example, when a SiN x film is formed as the dielectric film 6, SiH 4 can be used as the Si source gas, and at least one of N 2 and NH 3 can be used as the N source gas. For example, when a SiN x O z film is formed as the dielectric film 6, SiH 4 as Si source gas, at least one of N 2 and NH 3 as N source gas, and oxygen source gas O 2 gas can be used. Each of C, O, and F in the dielectric film 6 may be intentionally introduced using a source gas containing these atoms, or may be introduced unavoidably without using the source gas. Also good.
　実施形態１の製造方法において、誘電体膜６の形成は、たとえば４００℃以上６００℃以下で行うことができる。これにより、後述するエッチング工程において、誘電体膜６を半導体基板１の第１の面１ａのエッチング耐性を有する保護膜として機能させることができるため、後述するエッチング工程において、第１の面１ａ側に保護膜を形成する必要がない。このため、製造工程を減少させることができ、もって製造コストの低減を図ることができる。 In the manufacturing method of the first embodiment, the dielectric film 6 can be formed, for example, at 400 ° C. or more and 600 ° C. or less. Thereby, in the etching process described later, the dielectric film 6 can function as a protective film having etching resistance of the first surface 1a of the semiconductor substrate 1. Therefore, in the etching process described later, the first surface 1a side It is not necessary to form a protective film. For this reason, it is possible to reduce the number of manufacturing steps, thereby reducing the manufacturing cost.
　なお、特許文献１に記載の太陽電池においては、絶縁層１１６の形成は１００℃～２００℃程度で実施される。これは、絶縁層１１６を形成する際の温度を高めた（たとえば４５０℃以上）場合、すでに半導体基板１００上に形成されている非晶質半導体層中の水素が過剰に抜け落ち、これによって非晶質半導体層の品質が低下するためである。このような低い温度で形成された絶縁層はエッチング耐性が低いため、後述するエッチング工程に備えて、絶縁層１１６上に保護膜を設ける必要がある。 In the solar cell described in Patent Document 1, the insulating layer 116 is formed at about 100 ° C. to 200 ° C. This is because, when the temperature at which the insulating layer 116 is formed is increased (for example, 450 ° C. or higher), hydrogen in the amorphous semiconductor layer already formed on the semiconductor substrate 100 is excessively removed, and thus amorphous. This is because the quality of the quality semiconductor layer deteriorates. Since the insulating layer formed at such a low temperature has low etching resistance, it is necessary to provide a protective film over the insulating layer 116 in preparation for an etching process described later.
　次に、図４に示すように、半導体基板１の第２の面１ｂの全面に第１のｉ型非晶質半導体膜２を形成する。第１のｉ型非晶質半導体膜２の形成方法は特に限定されないが、たとえばプラズマＣＶＤ法を用いることができる。 Next, as shown in FIG. 4, a first i-type amorphous semiconductor film 2 is formed on the entire second surface 1 b of the semiconductor substrate 1. The method for forming the first i-type amorphous semiconductor film 2 is not particularly limited, and for example, a plasma CVD method can be used.
　第１のｉ型非晶質半導体膜２としては、ｉ型非晶質シリコン膜を好適に用いることができるがｉ型非晶質シリコン膜に限定されず、たとえば従来から公知のｉ型非晶質半導体膜を用いることもできる。 As the first i-type amorphous semiconductor film 2, an i-type amorphous silicon film can be preferably used, but is not limited to an i-type amorphous silicon film. A quality semiconductor film can also be used.
　次に、図５に示すように、第１のｉ型非晶質半導体膜２上に第１導電型非晶質半導体膜３を形成する。第１導電型非晶質半導体膜３の形成方法は特に限定されないが、たとえばプラズマＣＶＤ法を用いることができる。 Next, as shown in FIG. 5, a first conductivity type amorphous semiconductor film 3 is formed on the first i-type amorphous semiconductor film 2. Although the formation method of the 1st conductivity type amorphous semiconductor film 3 is not specifically limited, For example, plasma CVD method can be used.
　第１導電型非晶質半導体膜３としては、ｐ型非晶質シリコン膜を好適に用いることができるがｐ型非晶質シリコン膜に限定されず、たとえば従来から公知のｐ型非晶質半導体膜を用いることもできる。ｐ型不純物としては、たとえばボロンを用いることができる。 As the first conductive type amorphous semiconductor film 3, a p-type amorphous silicon film can be preferably used. However, the first conductive type amorphous semiconductor film 3 is not limited to a p-type amorphous silicon film. A semiconductor film can also be used. For example, boron can be used as the p-type impurity.
　次に、図６に示すように、第１導電型非晶質半導体膜３上に、第１のｉ型非晶質半導体膜２と第１導電型非晶質半導体膜３との積層体を厚さ方向にエッチングする箇所に開口部を有するフォトレジスト等のエッチングマスク３１を形成する。 Next, as shown in FIG. 6, a stacked body of the first i-type amorphous semiconductor film 2 and the first conductive-type amorphous semiconductor film 3 is formed on the first conductive-type amorphous semiconductor film 3. An etching mask 31 such as a photoresist having an opening at a portion to be etched in the thickness direction is formed.
　次に、図７に示すように、エッチングマスク３１をマスクとして、第１のｉ型非晶質半導体膜２と第１導電型非晶質半導体膜３との積層体５１を厚さ方向にエッチングすることによって、半導体基板１の第２の面１ｂの一部を露出させる。 Next, as shown in FIG. 7, the stacked body 51 of the first i-type amorphous semiconductor film 2 and the first conductive amorphous semiconductor film 3 is etched in the thickness direction using the etching mask 31 as a mask. As a result, a part of the second surface 1b of the semiconductor substrate 1 is exposed.
　次に、図８に示すように、半導体基板１の露出面および第１導電型非晶質半導体膜３を覆うようにして第２のｉ型非晶質半導体膜４を形成する。第２のｉ型非晶質半導体膜４の形成方法は特に限定されないが、たとえばプラズマＣＶＤ法を用いることができる。 Next, as shown in FIG. 8, a second i-type amorphous semiconductor film 4 is formed so as to cover the exposed surface of the semiconductor substrate 1 and the first conductive amorphous semiconductor film 3. The method for forming the second i-type amorphous semiconductor film 4 is not particularly limited, and for example, a plasma CVD method can be used.
　第２のｉ型非晶質半導体膜４としては、ｉ型非晶質シリコン膜を好適に用いることができるがｉ型非晶質シリコン膜に限定されず、たとえば従来から公知のｉ型非晶質半導体膜を用いることもできる。 As the second i-type amorphous semiconductor film 4, an i-type amorphous silicon film can be suitably used, but is not limited to an i-type amorphous silicon film. For example, a conventionally known i-type amorphous silicon film is used. A quality semiconductor film can also be used.
　次に、図９に示すように、第２のｉ型非晶質半導体膜４上に第２導電型非晶質半導体膜５を形成する。第２導電型非晶質半導体膜５の形成方法は特に限定されないが、たとえばプラズマＣＶＤ法を用いることができる。 Next, as shown in FIG. 9, a second conductivity type amorphous semiconductor film 5 is formed on the second i-type amorphous semiconductor film 4. Although the formation method of the 2nd conductivity type amorphous semiconductor film 5 is not specifically limited, For example, plasma CVD method can be used.
　第２導電型非晶質半導体膜５としては、ｎ型非晶質シリコン膜を好適に用いることができるがｎ型非晶質シリコン膜に限定されず、たとえば従来から公知のｎ型非晶質半導体膜を用いることもできる。ｎ型不純物としては、たとえばリンを用いることができる。 As the second conductive type amorphous semiconductor film 5, an n-type amorphous silicon film can be preferably used, but is not limited to an n-type amorphous silicon film. For example, a conventionally known n-type amorphous silicon film is used. A semiconductor film can also be used. For example, phosphorus can be used as the n-type impurity.
　次に、図１０に示すように、半導体基板１の裏面上の第２のｉ型非晶質半導体膜４と第２導電型非晶質半導体膜５との積層体を残す部分にのみフォトレジスト等のエッチングマスク３２を形成する。 Next, as shown in FIG. 10, a photoresist is formed only on a portion where the stacked body of the second i-type amorphous semiconductor film 4 and the second conductive type amorphous semiconductor film 5 is left on the back surface of the semiconductor substrate 1. Etching mask 32 is formed.
　次に、エッチングマスク３２をマスクとして、第２のｉ型非晶質半導体膜４と第２導電型非晶質半導体膜５との積層体５２の一部を厚さ方向にエッチングすることによって、図１１に示すように、第１導電型非晶質半導体膜３の一部を露出させる。その後、図１２に示すように、エッチングマスク３２を完全に除去する。 Next, a part of the stacked body 52 of the second i-type amorphous semiconductor film 4 and the second conductive amorphous semiconductor film 5 is etched in the thickness direction using the etching mask 32 as a mask. As shown in FIG. 11, a part of the first conductive type amorphous semiconductor film 3 is exposed. Thereafter, as shown in FIG. 12, the etching mask 32 is completely removed.
　次に、図１に示すように、第１導電型非晶質半導体膜３に接するように第１電極７を形成するとともに、第２導電型非晶質半導体膜５に接するように第２電極８を形成する。第１電極７および第２電極８の形成方法は特に限定されないが、たとえば蒸着法などを用いることができる。 Next, as shown in FIG. 1, the first electrode 7 is formed so as to be in contact with the first conductive amorphous semiconductor film 3, and the second electrode is in contact with the second conductive amorphous semiconductor film 5. 8 is formed. Although the formation method of the 1st electrode 7 and the 2nd electrode 8 is not specifically limited, For example, a vapor deposition method etc. can be used.
　以上により、図１に示す構成の実施形態１のヘテロ接合型バックコンタクトセルが完成する。 Thus, the heterojunction back contact cell according to the first embodiment having the configuration shown in FIG. 1 is completed.
　＜作用効果＞
　特許文献１に記載の太陽電池は、受光面１００ａ上のｉ型非晶質半導体層１１７ｉと裏面１００ｂ上のｉ型非晶質半導体層１１２ｉとが同時に形成されて作製される。これは、ｉ型非晶質半導体層１１７ｉおよびｉ型非晶質半導体層１１２ｉは、それぞれ半導体基板１００の受光面１００ａおよび裏面１００ｂのパッシベーション性を向上させるために必須であり、同時に形成するほうが効率的であると考えられていたためである。 <Effect>
The solar cell described in Patent Document 1 is manufactured by simultaneously forming an i-type amorphous semiconductor layer 117i on the light receiving surface 100a and an i-type amorphous semiconductor layer 112i on the back surface 100b. This is because the i-type amorphous semiconductor layer 117i and the i-type amorphous semiconductor layer 112i are essential for improving the passivation of the light receiving surface 100a and the back surface 100b of the semiconductor substrate 100, respectively, and it is more efficient to form them simultaneously. It was because it was thought to be the target.
　しかし、本発明者らは、特許文献１に記載の太陽電池において、半導体基板１００の受光面１００ａ上のｉ型非晶質半導体層１１７ｉが、短波長領域（波長３００ｎｍ以上５００ｎｍ以下）の光を吸収しやすく、これにより、短絡電流密度が期待されるほどに大きくならないことを知見した。 However, the present inventors, in the solar cell described in Patent Document 1, the i-type amorphous semiconductor layer 117i on the light receiving surface 100a of the semiconductor substrate 100 emits light in a short wavelength region (wavelength of 300 nm or more and 500 nm or less). It has been found that it is easy to absorb and this does not increase the short circuit current density as expected.
　そこで、実施形態１のヘテロ接合型バックコンタクトセルにおいては、半導体基板１の第１の面１ａと誘電体膜６との間に非晶質半導体膜を設けず、第１の面１ａと誘電体膜６とが接する構造を有する。これにより、受光面側の非晶質半導体膜による短波長領域の光の吸収を抑制して半導体基板１への入射光量を増大させることができるため、実施形態１のヘテロ接合型バックコンタクトセルは、特許文献１に記載の太陽電池と比べて短絡電流密度を向上することができる。 Therefore, in the heterojunction back contact cell of Embodiment 1, an amorphous semiconductor film is not provided between the first surface 1a of the semiconductor substrate 1 and the dielectric film 6, and the first surface 1a and the dielectric are not provided. It has a structure in contact with the film 6. Thereby, the absorption of light in the short wavelength region by the amorphous semiconductor film on the light receiving surface side can be suppressed and the amount of light incident on the semiconductor substrate 1 can be increased, so that the heterojunction back contact cell of Embodiment 1 is Compared with the solar cell described in Patent Document 1, the short-circuit current density can be improved.
　また、実施形態１のヘテロ接合型バックコンタクトセルにおいて、半導体基板１の屈折率と誘電体膜６の屈折率との差は１．０以下であることが好ましく、０．８以下であることがより好ましい。これにより、誘電体膜６は、より高いパッシベーション性を有することができる。 In the heterojunction back contact cell of Embodiment 1, the difference between the refractive index of the semiconductor substrate 1 and the refractive index of the dielectric film 6 is preferably 1.0 or less, and preferably 0.8 or less. More preferred. Thereby, the dielectric film 6 can have higher passivation property.
　この理由は明確ではないが、半導体基板１の屈折率と誘電体膜６との屈折率との差が小さくなるほど、誘電体膜６のダングリングボンドの数が半導体基板１のダングリングボンドの数に近づくために、誘電体膜６によって半導体基板１のダングリングボンドをより多く終端することができるためと推察される。なお、本明細書において、屈折率は絶対屈折率を意味する。 The reason for this is not clear, but the smaller the difference between the refractive index of the semiconductor substrate 1 and the refractive index of the dielectric film 6, the more the number of dangling bonds in the dielectric film 6 is the number of dangling bonds in the semiconductor substrate 1. This is presumed to be because more dangling bonds of the semiconductor substrate 1 can be terminated by the dielectric film 6. In this specification, the refractive index means an absolute refractive index.
　［実施の形態２］
　図１３に、実施形態２のヘテロ接合型バックコンタクトセルの模式的な断面図を示す。実施形態２のヘテロ接合型バックコンタクトセルは、第１の面１ａに接する第１誘電体膜６ａと、第１誘電体膜６ａ上に設けられた第２誘電体膜６ｂとを有する点に特徴がある。 [Embodiment 2]
FIG. 13 is a schematic cross-sectional view of the heterojunction back contact cell of the second embodiment. The heterojunction back contact cell of Embodiment 2 is characterized by having a first dielectric film 6a in contact with the first surface 1a and a second dielectric film 6b provided on the first dielectric film 6a. There is.
　第１誘電体膜６ａおよび第２誘電体膜６ｂは、それぞれＮとＳｉとを含む誘電体膜であり、第２誘電体膜６ｂ中のＳｉの含有量は、第１誘電体膜６ａ中のＳｉの含有量よりも少ない。すなわち、誘電体膜６において、半導体基板１の第１の面１ａから離れるにつれてＳｉの含有量が段階的に低減している。これにより、半導体基板１、第１誘電体膜６ａおよび第２誘電体膜６ｂの順に屈折率が低くなる。 The first dielectric film 6a and the second dielectric film 6b are each a dielectric film containing N and Si, and the content of Si in the second dielectric film 6b is the same as that in the first dielectric film 6a. Less than Si content. That is, in the dielectric film 6, the Si content is gradually reduced as the distance from the first surface 1 a of the semiconductor substrate 1 increases. As a result, the refractive index decreases in the order of the semiconductor substrate 1, the first dielectric film 6a, and the second dielectric film 6b.
　なお、実施形態２のヘテロ接合型バックコンタクトセルは、たとえば、第１誘電体膜６ａおよび第２誘電体膜６ｂをプラズマＣＶＤ法で形成する際、第２誘電体膜６ｂを形成するときのＮの原料ガスに対するＳｉの原料ガスの流量の割合を、第１誘電体膜６ａを形成するときＮの原料ガスに対するＳｉの原料ガスの流量の割合よりも低く設定して、製造することができる。これにより、第１誘電体膜６ａ中のＳｉの含有量と比べて、第２誘電体膜６ｂ中のＳｉの含有量を少なくすることができるため、第２誘電体膜６ｂの屈折率を第１誘電体膜６ａの屈折率よりも低くすることができる。 In the heterojunction back contact cell of the second embodiment, for example, when the first dielectric film 6a and the second dielectric film 6b are formed by the plasma CVD method, N when the second dielectric film 6b is formed. When the first dielectric film 6a is formed, the ratio of the flow rate of the Si source gas to the source material gas can be set lower than the ratio of the flow rate of the Si source gas to the N source gas. Thereby, since the Si content in the second dielectric film 6b can be reduced as compared with the Si content in the first dielectric film 6a, the refractive index of the second dielectric film 6b is set to the first refractive index. The refractive index of the dielectric film 6a can be made lower.
　上述のように、実施形態２のヘテロ接合型バックコンタクトセルにおいて、誘電体膜６の屈折率を、半導体基板１の第１の面１ａから離れるにつれて段階的に低減させることができるため、誘電体膜６の反射防止機能を高めることができる。また、半導体基板１の屈折率と第１誘電体膜６ａとの屈折率との差を１．０以下、特に０．８以下とした場合には、第１誘電体膜６ａによる半導体基板１の第１の面１ａのパッシベーション性を向上させることができる。 As described above, in the heterojunction back contact cell according to the second embodiment, the refractive index of the dielectric film 6 can be reduced stepwise as the distance from the first surface 1a of the semiconductor substrate 1 increases. The antireflection function of the film 6 can be enhanced. In addition, when the difference between the refractive index of the semiconductor substrate 1 and the refractive index of the first dielectric film 6a is 1.0 or less, particularly 0.8 or less, the semiconductor substrate 1 is formed by the first dielectric film 6a. The passivation property of the 1st surface 1a can be improved.
　実施形態２では、誘電体膜６が第１誘電体膜６ａおよび第２誘電体膜６ｂからなる場合について説明したが、これに限定されず、誘電体膜６は、３層以上の誘電体膜が積層された構成であってもよい。 In the second embodiment, the case where the dielectric film 6 includes the first dielectric film 6a and the second dielectric film 6b has been described. However, the present invention is not limited to this, and the dielectric film 6 is a dielectric film having three or more layers. May be configured to be stacked.
　実施形態２における上記以外の説明は実施形態１と同様であるため、その説明については繰り返さない。 Since the description other than the above in the second embodiment is the same as that in the first embodiment, the description thereof will not be repeated.
　［実施形態３］
　実施形態３のヘテロ接合型バックコンタクトセルは、誘電体膜６中のＳｉの含有量が、半導体基板１の第１の面１ａから離れるにつれて連続的に低減している点に特徴がある。 [Embodiment 3]
The heterojunction back contact cell of Embodiment 3 is characterized in that the Si content in the dielectric film 6 is continuously reduced as the distance from the first surface 1a of the semiconductor substrate 1 increases.
　実施形態３のヘテロ接合型バックコンタクトセルは、たとえば誘電体膜６を形成する際のプラズマＣＶＤ法において、Ｎの原料ガスに対するＳｉの原料ガスの流量の割合を連続的に減少させていくことにより、製造することができる。 The heterojunction back contact cell of Embodiment 3 is obtained by continuously decreasing the ratio of the flow rate of the Si source gas to the N source gas, for example, in the plasma CVD method when forming the dielectric film 6. Can be manufactured.
　実施形態３における上記以外の説明は、実施形態１および実施形態２と同様であるため、その説明については繰り返さない。 Description of Embodiment 3 other than the above is the same as that of Embodiment 1 and Embodiment 2, and therefore description thereof will not be repeated.
　［実施形態４］
　実施形態４は、ヘテロ接合型バックコンタクトセルの製造方法において、半導体基板１の第２の面１ｂ側に各膜を形成した後に、半導体基板１の第１の面１ａ上に誘電体膜６を形成する点に特徴がある。 [Embodiment 4]
In the fourth embodiment, in the method of manufacturing a heterojunction back contact cell, after forming each film on the second surface 1b side of the semiconductor substrate 1, the dielectric film 6 is formed on the first surface 1a of the semiconductor substrate 1. There is a feature in the point to form.
　以下、図２および図１４～図２３の模式的断面図を参照して、実施形態４のヘテロ接合型バックコンタクトセルの製造方法の一例について説明する。 Hereinafter, an example of a method for manufacturing the heterojunction back contact cell of Embodiment 4 will be described with reference to the schematic cross-sectional views of FIG. 2 and FIGS.
　まず、図２に示すように、半導体基板１の受光面となる第１の面１ａ上に凹凸形状を形成する。 First, as shown in FIG. 2, a concavo-convex shape is formed on the first surface 1a which becomes the light receiving surface of the semiconductor substrate 1.
　次に、図１４に示すように、半導体基板１の第２の面１ｂの全面に第１のｉ型非晶質半導体膜２を形成する。 Next, as shown in FIG. 14, a first i-type amorphous semiconductor film 2 is formed on the entire second surface 1 b of the semiconductor substrate 1.
　次に、図１５に示すように、第１のｉ型非晶質半導体膜２上に第１導電型非晶質半導体膜３を形成する。 Next, as shown in FIG. 15, a first conductivity type amorphous semiconductor film 3 is formed on the first i-type amorphous semiconductor film 2.
　次に、図１６に示すように、第１導電型非晶質半導体膜３上に、エッチングマスク３１を形成する。 Next, as shown in FIG. 16, an etching mask 31 is formed on the first conductive type amorphous semiconductor film 3.
　次に、図１７に示すように、エッチングマスク３１をマスクとして、第１のｉ型非晶質半導体膜２と第１導電型非晶質半導体膜３との積層体５１を厚さ方向にエッチングすることによって、半導体基板１の第２の面１ｂの一部を露出させる。 Next, as shown in FIG. 17, the stacked body 51 of the first i-type amorphous semiconductor film 2 and the first conductive amorphous semiconductor film 3 is etched in the thickness direction using the etching mask 31 as a mask. As a result, a part of the second surface 1b of the semiconductor substrate 1 is exposed.
　次に、図１８に示すように、半導体基板１の第２の面１ｂの露出面および第１導電型非晶質半導体膜３を覆うようにして第２のｉ型非晶質半導体膜４を形成する。 Next, as shown in FIG. 18, the second i-type amorphous semiconductor film 4 is formed so as to cover the exposed surface of the second surface 1 b of the semiconductor substrate 1 and the first conductive type amorphous semiconductor film 3. Form.
　次に、図１９に示すように、第２のｉ型非晶質半導体膜４上に第２導電型非晶質半導体膜５を形成する。 Next, as shown in FIG. 19, a second conductivity type amorphous semiconductor film 5 is formed on the second i-type amorphous semiconductor film 4.
　次に、図２０に示すように、半導体基板１の第２の面１ｂ上の第２のｉ型非晶質半導体膜４と第２導電型非晶質半導体膜５との積層体を残す部分にのみエッチングマスク３２を形成する。 Next, as shown in FIG. 20, a portion where the stacked body of the second i-type amorphous semiconductor film 4 and the second conductive amorphous semiconductor film 5 on the second surface 1 b of the semiconductor substrate 1 is left. The etching mask 32 is formed only on the substrate.
　次に、エッチングマスク３２をマスクとして、第２のｉ型非晶質半導体膜４と第２導電型非晶質半導体膜５との積層体５２の一部を厚さ方向にエッチングすることによって、図２１に示すように、第１導電型非晶質半導体膜３の一部を露出させる。その後、図２２に示すように、エッチングマスク３２を完全に除去する。 Next, a part of the stacked body 52 of the second i-type amorphous semiconductor film 4 and the second conductive amorphous semiconductor film 5 is etched in the thickness direction using the etching mask 32 as a mask. As shown in FIG. 21, a part of the first conductive type amorphous semiconductor film 3 is exposed. Thereafter, as shown in FIG. 22, the etching mask 32 is completely removed.
　次に、図２３に示すように、半導体基板１の第１の面１ａの全面に接するように誘電体膜６を形成する。誘電体膜６は、半導体基板１の温度を１００℃以上２００℃以下にすることによって形成することが好ましい。これは、半導体基板１の温度を２００℃よりも高く設定して誘電体膜６を形成した場合、第２の面１ｂ側に設けられている各非晶質半導体膜からの水素の過剰な抜けが生じるためである。 Next, as shown in FIG. 23, a dielectric film 6 is formed so as to be in contact with the entire surface of the first surface 1a of the semiconductor substrate 1. The dielectric film 6 is preferably formed by setting the temperature of the semiconductor substrate 1 to 100 ° C. or more and 200 ° C. or less. This is because when the temperature of the semiconductor substrate 1 is set higher than 200 ° C. and the dielectric film 6 is formed, excessive escape of hydrogen from each amorphous semiconductor film provided on the second surface 1b side. This is because.
　次に、図１に示すように、第１導電型非晶質シリコン膜３に接するように第１電極７を形成するとともに、第２導電型非晶質シリコン膜５に接するように第２電極８を形成する。 Next, as shown in FIG. 1, the first electrode 7 is formed so as to be in contact with the first conductive type amorphous silicon film 3, and the second electrode is formed so as to be in contact with the second conductive type amorphous silicon film 5. 8 is formed.
　実施形態４の製造方法によれば、誘電体膜６を形成した後に実施される工程は、第１電極７を形成する工程および第２電極８を形成する工程であるため、誘電体膜６上にエッチング耐性を有する保護膜を設ける必要がない。したがって、実施形態４の製造方法によれば、製造プロセスを簡略化することができ、これによって製造コストを低減することができる。 According to the manufacturing method of the fourth embodiment, the process performed after forming the dielectric film 6 is a process of forming the first electrode 7 and a process of forming the second electrode 8. There is no need to provide a protective film having etching resistance. Therefore, according to the manufacturing method of Embodiment 4, the manufacturing process can be simplified, thereby reducing the manufacturing cost.
　実施形態４では、誘電体膜６が単層である場合について説明したが、これに限られず、誘電体膜６において、半導体基板１の第１の面１ａから離れるにつれてＳｉの含有量が段階的に低減する場合、および連続的に低減する場合についても、第２の面１ｂ側の各膜を形成した後に、誘電体膜６を形成してもよい。 In the fourth embodiment, the case where the dielectric film 6 is a single layer has been described. However, the present invention is not limited to this, and the content of Si in the dielectric film 6 gradually increases as the distance from the first surface 1a of the semiconductor substrate 1 increases. In the case of reducing the film thickness to the above and continuously, the dielectric film 6 may be formed after each film on the second surface 1b side is formed.
　実施形態４における上記以外の説明は実施形態１～実施形態３と同様であるため、その説明については繰り返さない。 Since the description other than the above in the fourth embodiment is the same as that in the first to third embodiments, the description thereof will not be repeated.
　＜実施例＞
　まず、ｎ型単結晶シリコンインゴットをスライスしたｎ型単結晶シリコン基板の表面のスライスダメージを除去した。 <Example>
First, slice damage on the surface of an n-type single crystal silicon substrate obtained by slicing an n-type single crystal silicon ingot was removed.
　次に、図２に示すように、スライスダメージ除去後のｎ型単結晶シリコン基板である半導体基板１の受光面となる第１の面１ａに凹凸形状を形成した。第１の面１ａの凹凸形状は、半導体基板１の第２の面１ｂの全面にテクスチャマスクを形成した後に、半導体基板１の第１の面１ａに対してアルカリ溶液を用いたテクスチャエッチングを行うことにより形成した。そして、半導体基板１からテクスチャマスクを除去した後に、半導体基板１の洗浄を行った。 Next, as shown in FIG. 2, a concavo-convex shape was formed on the first surface 1a serving as the light receiving surface of the semiconductor substrate 1 which is an n-type single crystal silicon substrate after removal of slice damage. The uneven shape of the first surface 1a is obtained by forming a texture mask on the entire second surface 1b of the semiconductor substrate 1 and then performing texture etching using an alkaline solution on the first surface 1a of the semiconductor substrate 1. Was formed. Then, after removing the texture mask from the semiconductor substrate 1, the semiconductor substrate 1 was cleaned.
　次に、図３に示すように、半導体基板１の第１の面１ａの全面に接するように、誘電体膜６を形成した。誘電体膜６は、プラズマＣＶＤ法により、半導体基板１の第１の面１ａ側から屈折率２．０のＳｉＮx膜と屈折率１．８のＳｉＮx膜とをこの順序で積層した積層体として形成した。その後、半導体基板１の洗浄を行った。 Next, as shown in FIG. 3, a dielectric film 6 was formed so as to be in contact with the entire surface of the first surface 1 a of the semiconductor substrate 1. The dielectric film 6, by a plasma CVD method, a laminate by laminating a the SiN x film of the SiN x film and the refractive index 1.8 of the refractive index 2.0 in this order from the first surface 1a side of the semiconductor substrate 1 Formed as. Thereafter, the semiconductor substrate 1 was cleaned.
　次に、図４に示すように、半導体基板１の第２の面１ｂの全面にプラズマＣＶＤ法によりｉ型非晶質シリコン膜からなる第１のｉ型非晶質半導体膜２を形成した。次に、図５に示すように、第１のｉ型非晶質半導体膜２の全面にプラズマＣＶＤ法によりｉ型非晶質シリコン膜からなる第１導電型非晶質半導体膜３を形成した。 Next, as shown in FIG. 4, a first i-type amorphous semiconductor film 2 made of an i-type amorphous silicon film was formed on the entire second surface 1b of the semiconductor substrate 1 by plasma CVD. Next, as shown in FIG. 5, a first conductive type amorphous semiconductor film 3 made of an i type amorphous silicon film is formed on the entire surface of the first i type amorphous semiconductor film 2 by plasma CVD. .
　次に、図６に示すように、第１導電型非晶質半導体膜３上に、第１のｉ型非晶質半導体膜２と第１導電型非晶質半導体膜３との積層体を厚さ方向にエッチングする箇所に開口部を有するフォトレジストからなるエッチングマスク３１を形成した。次に、図７に示すように、半導体基板１の受光面上の誘電体膜６および半導体基板１の裏面上のエッチングマスク３１をそれぞれマスクとして、第１のｉ型非晶質半導体膜２と第１導電型非晶質半導体膜３との積層体５１を厚さ方向にエッチングすることによって、半導体基板１の第２の面１ｂの一部を露出させた。そして、エッチングマスク３１を除去した後に半導体基板１の洗浄を行った。 Next, as shown in FIG. 6, a stacked body of the first i-type amorphous semiconductor film 2 and the first conductive-type amorphous semiconductor film 3 is formed on the first conductive-type amorphous semiconductor film 3. An etching mask 31 made of a photoresist having an opening at a portion to be etched in the thickness direction was formed. Next, as shown in FIG. 7, the first i-type amorphous semiconductor film 2 and the dielectric film 6 on the light receiving surface of the semiconductor substrate 1 and the etching mask 31 on the back surface of the semiconductor substrate 1 are used as masks. A portion of the second surface 1b of the semiconductor substrate 1 was exposed by etching the stacked body 51 with the first conductive type amorphous semiconductor film 3 in the thickness direction. Then, after removing the etching mask 31, the semiconductor substrate 1 was cleaned.
　次に、図８に示すように、半導体基板１の露出面および第１導電型非晶質半導体膜３を覆うようにして、プラズマＣＶＤ法により、ｉ型非晶質シリコン膜からなる第２のｉ型非晶質半導体膜４を形成した。次に、図９に示すように、第２のｉ型非晶質半導体膜４上に、プラズマＣＶＤ法により、ｎ型非晶質シリコン膜からなる第２導電型非晶質半導体膜５を形成した。 Next, as shown in FIG. 8, the second surface made of the i-type amorphous silicon film is formed by plasma CVD so as to cover the exposed surface of the semiconductor substrate 1 and the first conductive type amorphous semiconductor film 3. An i-type amorphous semiconductor film 4 was formed. Next, as shown in FIG. 9, a second conductive amorphous semiconductor film 5 made of an n-type amorphous silicon film is formed on the second i-type amorphous semiconductor film 4 by plasma CVD. did.
　次に、図１０に示すように、半導体基板１の裏面上の第２のｉ型非晶質半導体膜４と第２導電型非晶質半導体膜５との積層体を残す部分にのみフォトレジストからなるエッチングマスク３２を形成した。次に、半導体基板１の受光面上の誘電体膜６およびエッチングマスク３２をそれぞれマスクとして、第２のｉ型非晶質半導体膜４と第２導電型非晶質半導体膜５との積層体５２の一部を厚さ方向にエッチングすることによって、図１１に示すように、第１導電型非晶質半導体膜３の一部を露出させた。その後、図１２に示すように、エッチングマスク３２を完全に除去した。その後、半導体基板１の洗浄を行った。 Next, as shown in FIG. 10, a photoresist is formed only on a portion where the stacked body of the second i-type amorphous semiconductor film 4 and the second conductive type amorphous semiconductor film 5 is left on the back surface of the semiconductor substrate 1. An etching mask 32 made of is formed. Next, using the dielectric film 6 and the etching mask 32 on the light receiving surface of the semiconductor substrate 1 as a mask, a laminate of the second i-type amorphous semiconductor film 4 and the second conductive amorphous semiconductor film 5 By etching a part of 52 in the thickness direction, a part of the first conductive type amorphous semiconductor film 3 was exposed as shown in FIG. Thereafter, as shown in FIG. 12, the etching mask 32 was completely removed. Thereafter, the semiconductor substrate 1 was cleaned.
　次に、第１導電型非晶質半導体膜３および第２導電型非晶質半導体膜５の全面に銀からなる金属膜を蒸着し、金属膜を厚さ方向にエッチングする箇所に開口部を有するフォトレジストからなるエッチングマスクを金属膜上に形成した状態で、半導体基板１の受光面上の誘電体膜６および半導体基板１の裏面上のエッチングマスクをそれぞれマスクとして金属膜のエッチングを行った。これにより、図１に示すように、第１導電型非晶質半導体膜３に接する第１電極７を形成するとともに、第２導電型非晶質半導体膜５に接するように第２電極８を形成した。そして、第１電極７および第２電極８の形成後に、半導体基板１の裏面上のエッチングマスクを除去した。以上により、実施例のヘテロ接合型バックコンタクトセルを完成させた。 Next, a metal film made of silver is deposited on the entire surface of the first conductive type amorphous semiconductor film 3 and the second conductive type amorphous semiconductor film 5, and an opening is formed at a location where the metal film is etched in the thickness direction. The metal film was etched using the dielectric film 6 on the light-receiving surface of the semiconductor substrate 1 and the etching mask on the back surface of the semiconductor substrate 1 as a mask in a state where an etching mask made of a photoresist was formed on the metal film. . As a result, as shown in FIG. 1, the first electrode 7 in contact with the first conductive type amorphous semiconductor film 3 is formed, and the second electrode 8 is set in contact with the second conductive type amorphous semiconductor film 5. Formed. Then, after the formation of the first electrode 7 and the second electrode 8, the etching mask on the back surface of the semiconductor substrate 1 was removed. Thus, the heterojunction back contact cell of the example was completed.
　＜比較例＞
　まず、実施例と同様にして、図２に示すように、スライスダメージ除去後のｎ型単結晶シリコン基板である半導体基板１の受光面となる第１の面１ａに凹凸形状を形成し、半導体基板１からテクスチャマスクを除去した後に半導体基板１の洗浄を行った。 <Comparative example>
First, in the same manner as in the example, as shown in FIG. 2, a concavo-convex shape is formed on the first surface 1a serving as the light-receiving surface of the semiconductor substrate 1 which is the n-type single crystal silicon substrate after removing the slice damage, After removing the texture mask from the substrate 1, the semiconductor substrate 1 was cleaned.
　次に、実施例の誘電体膜６を形成する代わりに、半導体基板１の受光面となる第１の面１ａの全面に接するように半導体基板１側からｉ型の非晶質シリコン膜とｎ型の非晶質シリコン膜とをこの順序でプラズマＣＶＤ法により堆積して、図２４の模式的断面図に示すように、ｉ型の非晶質シリコン膜とｎ型の非晶質シリコン膜とからなる積層体６１を形成した。 Next, instead of forming the dielectric film 6 of the embodiment, an i-type amorphous silicon film and n are formed from the side of the semiconductor substrate 1 so as to be in contact with the entire surface of the first surface 1a serving as the light receiving surface of the semiconductor substrate 1. Type amorphous silicon films are deposited in this order by plasma CVD, and as shown in the schematic cross-sectional view of FIG. 24, an i-type amorphous silicon film and an n-type amorphous silicon film A laminate 61 made of was formed.
　次に、実施例と同様にして、半導体基板１の裏面となる第２の面１ｂの全面に第１のｉ型非晶質半導体膜２と第１導電型非晶質半導体膜３とをこの順序でプラズマＣＶＤ法により堆積した（図２５参照）。 Next, in the same manner as in the example, the first i-type amorphous semiconductor film 2 and the first conductivity-type amorphous semiconductor film 3 are formed on the entire surface of the second surface 1b which is the back surface of the semiconductor substrate 1. The layers were sequentially deposited by the plasma CVD method (see FIG. 25).
　次に、実施例と同様にして、第１導電型非晶質半導体膜３上に、第１のｉ型非晶質半導体膜２と第１導電型非晶質半導体膜３との積層体を厚さ方向にエッチングする箇所に開口部を有するフォトレジストからなるエッチングマスク３１を形成した（図２６参照）。なお、比較例においては、エッチングマスク３１は、半導体基板１の受光面のｉ型の非晶質シリコン膜とｎ型の非晶質シリコン膜との積層体６１上にも形成した。 Next, in the same manner as in the example, a stacked body of the first i-type amorphous semiconductor film 2 and the first conductive-type amorphous semiconductor film 3 is formed on the first conductive-type amorphous semiconductor film 3. An etching mask 31 made of a photoresist having an opening at a portion to be etched in the thickness direction was formed (see FIG. 26). In the comparative example, the etching mask 31 is also formed on the stacked body 61 of the i-type amorphous silicon film and the n-type amorphous silicon film on the light receiving surface of the semiconductor substrate 1.
　次に、実施例と同様にして、エッチングマスク３１をマスクとして、第１のｉ型非晶質半導体膜２と第１導電型非晶質半導体膜３との積層体を厚さ方向にエッチングすることによって、半導体基板１の第２の面１ｂの一部を露出させた（図２７参照）。そして、半導体基板１の受光面上および裏面上のエッチングマスク３１をそれぞれ除去した後に半導体基板１の洗浄を行った。 Next, in the same manner as in the example, using the etching mask 31 as a mask, the stacked body of the first i-type amorphous semiconductor film 2 and the first conductive amorphous semiconductor film 3 is etched in the thickness direction. As a result, a part of the second surface 1b of the semiconductor substrate 1 was exposed (see FIG. 27). Then, after removing the etching masks 31 on the light receiving surface and the back surface of the semiconductor substrate 1, the semiconductor substrate 1 was cleaned.
　次に、実施例と同様にして、半導体基板１の露出面および第１導電型非晶質半導体膜３を覆うようにして、プラズマＣＶＤ法により、ｉ型非晶質シリコン膜からなる第２のｉ型非晶質半導体膜４を形成し（図２８参照）、第２のｉ型非晶質半導体膜４上に、プラズマＣＶＤ法により、ｎ型非晶質シリコン膜からなる第２導電型非晶質半導体膜５を形成した（図２９参照）。 Next, in the same manner as in the example, the second surface made of the i-type amorphous silicon film is formed by plasma CVD so as to cover the exposed surface of the semiconductor substrate 1 and the first conductive type amorphous semiconductor film 3. An i-type amorphous semiconductor film 4 is formed (see FIG. 28), and a second conductivity type non-crystalline film made of an n-type amorphous silicon film is formed on the second i-type amorphous semiconductor film 4 by plasma CVD. A crystalline semiconductor film 5 was formed (see FIG. 29).
　次に、実施例と同様にして、半導体基板１の裏面上の第２のｉ型非晶質半導体膜４と第２導電型非晶質半導体膜５との積層体を残す部分にのみフォトレジストからなるエッチングマスク３２を形成した（図３０参照）。なお、比較例においては、半導体基板１の受光面上の積層体６１上にもエッチングマスク３２を形成した。 Next, in the same manner as in the example, the photoresist is applied only to the portion where the stacked body of the second i-type amorphous semiconductor film 4 and the second conductive type amorphous semiconductor film 5 is left on the back surface of the semiconductor substrate 1. An etching mask 32 made of (see FIG. 30) was formed. In the comparative example, the etching mask 32 is also formed on the stacked body 61 on the light receiving surface of the semiconductor substrate 1.
　次に、エッチングマスク３２をマスクとして、第２のｉ型非晶質半導体膜４と第２導電型非晶質半導体膜５との積層体５２の一部を厚さ方向にエッチングすることによって、第１導電型非晶質半導体膜３の一部を露出させた（図３１参照）。そして、半導体基板１の受光面上および裏面上のエッチングマスク３２をそれぞれ除去した後に、半導体基板１の洗浄を行った。 Next, a part of the stacked body 52 of the second i-type amorphous semiconductor film 4 and the second conductive amorphous semiconductor film 5 is etched in the thickness direction using the etching mask 32 as a mask. A part of the first conductive type amorphous semiconductor film 3 was exposed (see FIG. 31). Then, after removing the etching masks 32 on the light receiving surface and the back surface of the semiconductor substrate 1, the semiconductor substrate 1 was cleaned.
　次に、図３２の模式的断面図に示すように、半導体基板１の受光面上のｉ型の非晶質シリコン膜とｎ型の非晶質シリコン膜との積層体６１上に、プラズマＣＶＤ法により、屈折率２．０のＳｉＮx膜と屈折率１．８のＳｉＮx膜とを積層体６１側からこの順序で積層して、屈折率２．０のＳｉＮx膜と屈折率１．８のＳｉＮx膜と積層体からなる誘電体膜６を形成した。 Next, as shown in the schematic cross-sectional view of FIG. 32, plasma CVD is performed on a stacked body 61 of an i-type amorphous silicon film and an n-type amorphous silicon film on the light receiving surface of the semiconductor substrate 1. by law, with the the SiN x film of the SiN x film and the refractive index 1.8 of the refractive index 2.0 by stacking of a stack 61 side in this order, the SiN x film and the refractive index of the refractive index 2.0 1. A dielectric film 6 composed of a stack of 8 SiN x films was formed.
　次に、図３３の模式的断面図に示すように、半導体基板１の受光面上の誘電体膜６の全面にフォトレジストからなるエッチングマスク３３を形成した状態で、第１導電型非晶質半導体膜３および第２導電型非晶質半導体膜５の全面に銀からなる金属膜９を蒸着した。次に、図３４の模式的断面図に示すように、金属膜９を厚さ方向にエッチングする箇所に開口部を有するフォトレジストからなるエッチングマスク３３を金属膜９上に形成した。次に、図３５の模式的断面図に示すように、半導体基板１の受光面上および裏面上のエッチングマスク３３をマスクとして金属膜９のエッチングを行って、第１導電型非晶質半導体膜３に接する第１電極７を形成するとともに、第２導電型非晶質半導体膜５に接する第２電極８を形成した。半導体基板１の受光面上および裏面上のエッチングマスク３３は、第１電極７および第２電極８の形成後にそれぞれ除去した。以上により、比較例のヘテロ接合型バックコンタクトセルを完成させた。 Next, as shown in the schematic cross-sectional view of FIG. 33, the first conductivity type amorphous film is formed with an etching mask 33 made of a photoresist formed on the entire surface of the dielectric film 6 on the light receiving surface of the semiconductor substrate 1. A metal film 9 made of silver was deposited on the entire surface of the semiconductor film 3 and the second conductive type amorphous semiconductor film 5. Next, as shown in the schematic cross-sectional view of FIG. 34, an etching mask 33 made of a photoresist having an opening at a location where the metal film 9 is etched in the thickness direction was formed on the metal film 9. Next, as shown in the schematic cross-sectional view of FIG. 35, the metal film 9 is etched using the etching mask 33 on the light receiving surface and the back surface of the semiconductor substrate 1 as a mask, so that the first conductivity type amorphous semiconductor film is obtained. 3 was formed, and the second electrode 8 was formed in contact with the second conductive type amorphous semiconductor film 5. The etching masks 33 on the light receiving surface and the back surface of the semiconductor substrate 1 were removed after the first electrode 7 and the second electrode 8 were formed. Thus, the heterojunction back contact cell of the comparative example was completed.
　＜評価＞
　上記のようにして作製した実施例のヘテロ接合型バックコンタクトセルと比較例のヘテロ接合型バックコンタクトセルとについて分光感度を測定した。分光感度は、分光機器（株）製のＣＥＰ－２５ＲＲＬを用い、実施例と比較例のそれぞれのヘテロ接合型バックコンタクトセルの受光面に白色光をバイアス照射することによって波長５ｎｍ刻みで測定した。その結果を図３６に示す。なお、図３６には、波長３００ｎｍ～５００ｎｍの光に対する実施例および比較例のそれぞれのヘテロ接合型バックコンタクトセルの受光面の分光感度が示されており、図３６の横軸が波長［ｎｍ］を示し、縦軸が外部量子効率（ＥＱＥ：External　Quantum　Efficiency）［％］を示している。なお、外部量子効率は、入射光の全光子１個対して発生したキャリア対（電子と正孔との対）の個数の割合［％］を意味している。 <Evaluation>
Spectral sensitivities were measured for the heterojunction back contact cell of the example manufactured as described above and the heterojunction back contact cell of the comparative example. Spectral sensitivity was measured in steps of 5 nm by applying white light to the light receiving surfaces of the heterojunction back contact cells of Examples and Comparative Examples using CEP-25RRL manufactured by Spectroscopic Co., Ltd. The result is shown in FIG. FIG. 36 shows the spectral sensitivities of the light receiving surfaces of the heterojunction back contact cells of the example and the comparative example with respect to light having a wavelength of 300 nm to 500 nm, and the horizontal axis of FIG. 36 represents the wavelength [nm]. The vertical axis represents the external quantum efficiency (EQE) [%]. The external quantum efficiency means the ratio [%] of the number of carrier pairs (electron and hole pairs) generated for one photon of incident light.
　図３６に示すように、実施例のヘテロ接合型バックコンタクトセルは、比較例のヘテロ接合型バックコンタクトセルと比べて、短波長側の光の分光感度が高くなることが確認された。特に、波長３００ｎｍの光の分光感度については、実施例のヘテロ接合型バックコンタクトセルの外部量子効率が約８０％であったのに対し、比較例のヘテロ接合型バックコンタクトセルの外部量子効率は約６０％であり、約２０％の大差があった。 As shown in FIG. 36, it was confirmed that the heterojunction back contact cell of the example has higher spectral sensitivity of light on the short wavelength side than the heterojunction back contact cell of the comparative example. In particular, for the spectral sensitivity of light having a wavelength of 300 nm, the external quantum efficiency of the heterojunction back contact cell of the example was about 80%, whereas the external quantum efficiency of the heterojunction back contact cell of the comparative example was About 60%, there was a large difference of about 20%.
　以上の結果により、ｉ型非晶質シリコン膜およびｎ型非晶質シリコン膜を介さずに半導体基板１の受光面に直接ＳｉＮx膜を形成した場合（実施例のヘテロ接合型バックコンタクトセル）には、ｉ型非晶質シリコン膜およびｎ型非晶質シリコン膜を介して半導体基板１の受光面上にＳｉＮx膜を形成した場合（比較例のヘテロ接合型バックコンタクトセル）と比べて、短波長側の光の吸収量が大幅に増大し、短絡電流密度が大幅に向上することがわかる。 As a result of the above, when the SiN x film is formed directly on the light-receiving surface of the semiconductor substrate 1 without the i-type amorphous silicon film and the n-type amorphous silicon film (heterojunction back contact cell of the example) Compared to the case where a SiN x film is formed on the light receiving surface of the semiconductor substrate 1 via an i-type amorphous silicon film and an n-type amorphous silicon film (heterojunction back contact cell of a comparative example). It can be seen that the amount of light absorbed on the short wavelength side is greatly increased and the short-circuit current density is greatly improved.
　なお、本実施例においては、半導体基板１の受光面に直接ＳｉＮx膜を形成した場合について述べたが、ＳｉＮxＣyＯzＦwＨv膜はＳｉＮx膜と同様の物性を有するため、ＳｉＮx膜の代わりに半導体基板１の受光面に直接ＳｉＮxＣyＯzＦwＨv膜を形成した場合にも、上述のＳｉＮx膜を形成した場合と同様の効果が得られると考えられる。 In the present embodiment, the case where the SiN x film is directly formed on the light receiving surface of the semiconductor substrate 1 has been described. However, the SiN x C y O z F w H v film has the same physical properties as the SiN x film. , even in the case of forming a direct SiN x C y O z F w H v film on the light receiving surface of the semiconductor substrate 1 in place of the SiN x film, the same effect as in the case of forming a the SiN x film described above is obtained Conceivable.
　［付記］
　（１）ここで開示された実施形態は、半導体基板の第１の面に接するように、窒素と珪素とを含む誘電体膜を形成する工程と、半導体基板記第１の面と反対側の第２の面側に、第１導電型非晶質半導体膜および第２導電型非晶質半導体膜を形成する工程と、第１導電型非晶質半導体膜上に第１電極を形成する工程と、第２導電型非晶質半導体膜上に第２電極を形成する工程と、を含む、ヘテロ接合型バックコンタクトセルの製造方法である。ここで開示された実施形態のヘテロ接合型バックコンタクトセルの製造方法によれば、短絡電流密度の特性に優れたヘテロ接合型バックコンタクトセルを製造することができる。 [Appendix]
(1) In the embodiment disclosed herein, a step of forming a dielectric film containing nitrogen and silicon so as to be in contact with the first surface of the semiconductor substrate; Forming a first conductive amorphous semiconductor film and a second conductive amorphous semiconductor film on the second surface side, and forming a first electrode on the first conductive amorphous semiconductor film; And a step of forming a second electrode on the second conductive type amorphous semiconductor film. A method for manufacturing a heterojunction back contact cell. According to the method for manufacturing a heterojunction back contact cell of the embodiment disclosed herein, a heterojunction back contact cell having excellent short-circuit current density characteristics can be manufactured.
　（２）ここで開示された実施形態のヘテロ接合型バックコンタクトセルの製造方法において、誘電体膜を形成する工程は、第２の面側に第１導電型非晶質半導体膜および第２導電型非晶質半導体膜を形成する工程の前に行われることが好ましい。この場合には、誘電体膜をエッチング耐性を有する保護膜として用いることができることから、エッチング工程の前にエッチング耐性を有する保護膜を形成する工程を削減することができ、もってヘテロ接合バックコンタクトセルの製造コストを低減することができる。 (2) In the method of manufacturing a heterojunction back contact cell according to the embodiment disclosed herein, the step of forming the dielectric film includes the first conductive type amorphous semiconductor film and the second conductive type on the second surface side. It is preferably performed before the step of forming the type amorphous semiconductor film. In this case, since the dielectric film can be used as a protective film having etching resistance, the step of forming the protective film having etching resistance before the etching process can be reduced, and thus the heterojunction back contact cell. The manufacturing cost can be reduced.
　（３）ここで開示された実施形態のヘテロ接合型バックコンタクトセルの製造方法において、誘電体膜を形成する工程が、第２の面側に第１導電型非晶質半導体膜および第２導電型非晶質半導体膜を形成する工程の前に行われる場合には、誘電体膜を形成する工程は４５０℃以上５００℃以下で行われることが好ましい。この場合には、誘電体膜のエッチング耐性を高めることができるため、製造工程において誘電体膜を保護するための保護膜を形成する必要がない。したがって、製造プロセスを簡略化することができるため、ヘテロ接合バックコンタクトセルの製造コストを低減することができる。 (3) In the method of manufacturing a heterojunction back contact cell according to the embodiment disclosed herein, the step of forming a dielectric film includes a first conductive type amorphous semiconductor film and a second conductive type on the second surface side. When performed before the step of forming the type amorphous semiconductor film, the step of forming the dielectric film is preferably performed at 450 ° C. or higher and 500 ° C. or lower. In this case, since the etching resistance of the dielectric film can be increased, it is not necessary to form a protective film for protecting the dielectric film in the manufacturing process. Therefore, since the manufacturing process can be simplified, the manufacturing cost of the heterojunction back contact cell can be reduced.
　（４）ここで開示された実施形態のヘテロ接合型バックコンタクトセルの製造方法において、誘電体膜を形成する工程は、第２の面側に第１導電型非晶質半導体膜および第２導電型非晶質半導体膜を形成する工程の後に行われることが好ましい。この場合には、誘電体膜の形成後にエッチング耐性を有する保護膜を形成する必要となるため、ヘテロ接合バックコンタクトセルの製造コストを低減することができる。 (4) In the method of manufacturing a heterojunction back contact cell according to the embodiment disclosed herein, the step of forming the dielectric film includes the first conductive type amorphous semiconductor film and the second conductive type on the second surface side. It is preferably performed after the step of forming the type amorphous semiconductor film. In this case, since it is necessary to form a protective film having etching resistance after the dielectric film is formed, the manufacturing cost of the heterojunction back contact cell can be reduced.
　（５）ここで開示された実施形態のヘテロ接合型バックコンタクトセルの製造方法において、誘電体膜を形成する工程が、第２の面側に第１導電型非晶質半導体膜および第２導電型非晶質半導体膜を形成する工程の後に行われる場合には、誘電体膜を形成する工程は１００℃以上２００℃以下で行われることが好ましい。この場合にも、製造コストを低減することができる。 (5) In the method of manufacturing a heterojunction back contact cell according to the embodiment disclosed herein, the step of forming a dielectric film includes a first conductive type amorphous semiconductor film and a second conductive type on the second surface side. When performed after the step of forming the type amorphous semiconductor film, the step of forming the dielectric film is preferably performed at 100 ° C. or higher and 200 ° C. or lower. Also in this case, the manufacturing cost can be reduced.
　（６）ここで開示された実施形態のヘテロ接合型バックコンタクトセルの製造方法において、誘電体膜は、第１の面から離れるにつれて珪素の含有量が低減することが好ましい。この場合には、誘電体膜の反射防止機能とパッシベーション性とを相互に高めることができる。 (6) In the method of manufacturing a heterojunction back contact cell according to the embodiment disclosed herein, it is preferable that the dielectric content of the dielectric film decreases as the distance from the first surface increases. In this case, the antireflection function and the passivation property of the dielectric film can be enhanced mutually.
　（７）ここで開示された実施形態のヘテロ接合型バックコンタクトセルの製造方法において、珪素の含有量は、第１の面から離れるにつれて連続的に低減することが好ましい。この場合にも、誘電体膜の反射防止機能とパッシベーション性とを相互に高めることができる。 (7) In the method of manufacturing a heterojunction back contact cell according to the embodiment disclosed herein, the silicon content is preferably continuously reduced as the distance from the first surface increases. Also in this case, the antireflection function and the passivation property of the dielectric film can be enhanced mutually.
　（８）ここで開示された実施形態のヘテロ接合型バックコンタクトセルの製造方法において、珪素の含有量は、第１の面から離れるにつれて段階的に低減することが好ましい。この場合にも、誘電体膜の反射防止機能とパッシベーション性とを相互に高めることができる。 (8) In the method of manufacturing a heterojunction back contact cell according to the embodiment disclosed herein, the silicon content is preferably reduced stepwise as the distance from the first surface increases. Also in this case, the antireflection function and the passivation property of the dielectric film can be enhanced mutually.
　（９）ここで開示された実施形態のヘテロ接合型バックコンタクトセルの製造方法において、誘電体膜は、酸素、炭素およびフッ素からなる群より選択された１つ以上の原子をさらに含むことが好ましい。この場合にも、短絡電流密度の特性に優れたヘテロ接合型バックコンタクトセルを製造することができる。 (9) In the method for manufacturing a heterojunction back contact cell according to the embodiment disclosed herein, the dielectric film preferably further includes one or more atoms selected from the group consisting of oxygen, carbon, and fluorine. . Also in this case, a heterojunction back contact cell having excellent short-circuit current density characteristics can be manufactured.
　（１０）ここで開示された実施形態のヘテロ接合型バックコンタクトセルの製造方法において、誘電体膜の組成は、ＳｉＮxＣyＯzＦwＨvの式で表されることが好ましい。この場合にも、短絡電流密度の特性に優れたヘテロ接合型バックコンタクトセルを製造することができる。 (10) In the method for manufacturing a heterojunction back contact cell of the disclosed embodiments herein, the composition of the dielectric film, is preferably represented by the formula of SiN x C y O z F w H v. Also in this case, a heterojunction back contact cell having excellent short-circuit current density characteristics can be manufactured.
　（１１）ここで開示された実施形態のヘテロ接合型バックコンタクトセルの製造方法において、第１導電型非晶質半導体膜および第２導電型非晶質半導体膜を形成する工程は、半導体基板の第２の面側に第１のｉ型非晶質半導体膜を形成する工程と、第１のｉ型非晶質半導体膜上に第１導電型非晶質半導体膜を形成する工程と、第１のｉ型非晶質半導体膜と第１導電型非晶質半導体膜との積層体の一部を除去する工程と、第２の面側に第２のｉ型非晶質半導体膜を形成する工程と、第２のｉ型非晶質半導体膜上に第２導電型非晶質半導体膜を形成する工程と、を含むことが好ましい。この場合にも、短絡電流密度の特性に優れたヘテロ接合型バックコンタクトセルを製造することができる。 (11) In the method of manufacturing a heterojunction back contact cell according to the embodiment disclosed herein, the step of forming the first conductive type amorphous semiconductor film and the second conductive type amorphous semiconductor film is performed on a semiconductor substrate. Forming a first i-type amorphous semiconductor film on the second surface side, forming a first conductivity-type amorphous semiconductor film on the first i-type amorphous semiconductor film, Removing a part of the stack of the first i-type amorphous semiconductor film and the first conductive amorphous semiconductor film, and forming the second i-type amorphous semiconductor film on the second surface side And a step of forming a second conductivity type amorphous semiconductor film on the second i-type amorphous semiconductor film. Also in this case, a heterojunction back contact cell having excellent short-circuit current density characteristics can be manufactured.
　（１２）ここで開示された実施形態のヘテロ接合型バックコンタクトセルの製造方法において、第１のｉ型非晶質半導体膜は、ｉ型非晶質シリコンを含むことが好ましい。この場合にも、短絡電流密度の特性に優れたヘテロ接合型バックコンタクトセルを製造することができる。 (12) In the method of manufacturing a heterojunction back contact cell according to the embodiment disclosed herein, the first i-type amorphous semiconductor film preferably contains i-type amorphous silicon. Also in this case, a heterojunction back contact cell having excellent short-circuit current density characteristics can be manufactured.
　（１３）ここで開示された実施形態のヘテロ接合型バックコンタクトセルの製造方法において、第２のｉ型非晶質半導体膜は、ｉ型非晶質シリコンを含むことが好ましい。この場合にも、短絡電流密度の特性に優れたヘテロ接合型バックコンタクトセルを製造することができる。 (13) In the method of manufacturing a heterojunction back contact cell according to the embodiment disclosed herein, the second i-type amorphous semiconductor film preferably contains i-type amorphous silicon. Also in this case, a heterojunction back contact cell having excellent short-circuit current density characteristics can be manufactured.
　（１４）ここで開示された実施形態のヘテロ接合型バックコンタクトセルの製造方法において、半導体基板は、ｎ型結晶シリコンを含むことが好ましい。この場合にも、短絡電流密度の特性に優れたヘテロ接合型バックコンタクトセルを製造することができる。 (14) In the method of manufacturing a heterojunction back contact cell according to the embodiment disclosed herein, the semiconductor substrate preferably includes n-type crystalline silicon. Also in this case, a heterojunction back contact cell having excellent short-circuit current density characteristics can be manufactured.
　（１５）ここで開示された実施形態のヘテロ接合型バックコンタクトセルは、第１導電型または第２導電型の半導体基板と、半導体基板の第１の面に接するように設けられた、窒素と珪素とを含む誘電体膜と、半導体基板の第１の面と反対側の第２の面側に設けられた、第１導電型非晶質半導体膜および第２導電型非晶質半導体膜と、第１導電型非晶質半導体膜上の第１電極と、第２導電型非晶質半導体膜上の第２電極と、を備える、ヘテロ接合型バックコンタクトセルである。ここで開示された実施形態のヘテロ接合型バックコンタクトセルは、半導体基板１と誘電体膜６との間に非晶質半導体膜が形成されていないため、当該非晶質半導体膜による短波長領域の光の吸収を抑制することができ、もって短絡電流密度の特性に優れる。 (15) A heterojunction back contact cell according to an embodiment disclosed herein includes a semiconductor substrate of a first conductivity type or a second conductivity type, and nitrogen provided in contact with a first surface of the semiconductor substrate. A dielectric film containing silicon, and a first conductive type amorphous semiconductor film and a second conductive type amorphous semiconductor film provided on a second surface side opposite to the first surface of the semiconductor substrate; A heterojunction back contact cell comprising a first electrode on the first conductive type amorphous semiconductor film and a second electrode on the second conductive type amorphous semiconductor film. In the heterojunction back contact cell of the embodiment disclosed herein, since an amorphous semiconductor film is not formed between the semiconductor substrate 1 and the dielectric film 6, a short wavelength region by the amorphous semiconductor film is formed. Absorption of light can be suppressed, and the short-circuit current density characteristics are excellent.
　（１６）ここで開示された実施形態のヘテロ接合型バックコンタクトセルにおいて、誘電体膜は、第１の面から離れるにつれて珪素の含有量が低減することが好ましい。この場合には、誘電体膜の反射防止機能とパッシベーション性とを相互に高めることができる。 (16) In the heterojunction back contact cell of the embodiment disclosed herein, the dielectric film preferably has a silicon content that decreases as the distance from the first surface increases. In this case, the antireflection function and the passivation property of the dielectric film can be enhanced mutually.
　（１７）ここで開示された実施形態のヘテロ接合型バックコンタクトセルにおいて、珪素の含有量は、第１の面から離れるにつれて連続的に低減することが好ましい。この場合にも、誘電体膜の反射防止機能とパッシベーション性とを相互に高めることができる。 (17) In the heterojunction back contact cell of the embodiment disclosed herein, the silicon content is preferably continuously reduced as the distance from the first surface increases. Also in this case, the antireflection function and the passivation property of the dielectric film can be enhanced mutually.
　（１８）ここで開示された実施形態のヘテロ接合型バックコンタクトセルにおいて、珪素の含有量は、第１の面から離れるにつれて段階的に低減することが好ましい。この場合にも、誘電体膜の反射防止機能とパッシベーション性とを相互に高めることができる。 (18) In the heterojunction back contact cell of the embodiment disclosed herein, it is preferable that the silicon content is reduced stepwise as the distance from the first surface increases. Also in this case, the antireflection function and the passivation property of the dielectric film can be enhanced mutually.
　（１９）ここで開示された実施形態のヘテロ接合型バックコンタクトセルにおいて、誘電体膜は、酸素、炭素およびフッ素からなる群より選択された１つ以上をさらに含むことが好ましい。この場合にも、短絡電流密度の特性に優れたヘテロバックコンタクトセルとすることができる。 (19) In the heterojunction back contact cell of the embodiment disclosed herein, the dielectric film preferably further includes one or more selected from the group consisting of oxygen, carbon, and fluorine. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
　（２０）ここで開示された実施形態のヘテロ接合型バックコンタクトセルにおいて、誘電体膜の組成は、ＳｉＮxＣyＯzＦwＨvの式で表されることが好ましい。この場合にも、短絡電流密度の特性に優れたヘテロバックコンタクトセルとすることができる。 (20) Here, in heterozygous back contact cell of the disclosed embodiments, the composition of the dielectric film, is preferably represented by the formula of SiN x C y O z F w H v. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
　（２１）ここで開示された実施形態のヘテロ接合型バックコンタクトセルは、半導体基板と第１導電型非晶質半導体膜との間の第１のｉ型非晶質半導体膜と、半導体基板と第２導電型非晶質半導体膜との間の第２のｉ型非晶質半導体膜とをさらに含むことが好ましい。この場合にも、短絡電流密度の特性に優れたヘテロバックコンタクトセルとすることができる。 (21) A heterojunction back contact cell according to an embodiment disclosed herein includes a first i-type amorphous semiconductor film between a semiconductor substrate and a first conductive amorphous semiconductor film, a semiconductor substrate, It is preferable to further include a second i-type amorphous semiconductor film between the second conductive type amorphous semiconductor film. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
　（２２）ここで開示された実施形態のヘテロ接合型バックコンタクトセルにおいて、第１のｉ型非晶質半導体膜は、ｉ型非晶質シリコンを含むことが好ましい。この場合にも、短絡電流密度の特性に優れたヘテロバックコンタクトセルとすることができる。 (22) In the heterojunction back contact cell of the embodiment disclosed herein, the first i-type amorphous semiconductor film preferably includes i-type amorphous silicon. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
　（２３）ここで開示された実施形態のヘテロ接合型バックコンタクトセルにおいて、第２のｉ型非晶質半導体膜は、ｉ型非晶質シリコンを含むことが好ましい。この場合にも、短絡電流密度の特性に優れたヘテロバックコンタクトセルとすることができる。 (23) In the heterojunction back contact cell of the embodiment disclosed herein, the second i-type amorphous semiconductor film preferably contains i-type amorphous silicon. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
　（２４）ここで開示された実施形態のヘテロ接合型バックコンタクトセルにおいて、半導体基板と第１のｉ型非晶質半導体膜とが接していることが好ましい。この場合にも、短絡電流密度の特性に優れたヘテロバックコンタクトセルとすることができる。 (24) In the heterojunction back contact cell of the embodiment disclosed herein, it is preferable that the semiconductor substrate and the first i-type amorphous semiconductor film are in contact with each other. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
　（２５）ここで開示された実施形態のヘテロ接合型バックコンタクトセルにおいて、半導体基板と第２のｉ型非晶質半導体膜とが接していることが好ましい。この場合にも、短絡電流密度の特性に優れたヘテロバックコンタクトセルとすることができる。 (25) In the heterojunction back contact cell of the embodiment disclosed herein, it is preferable that the semiconductor substrate and the second i-type amorphous semiconductor film are in contact with each other. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
　（２６）ここで開示された実施形態のヘテロ接合型バックコンタクトセルにおいて、第１のｉ型非晶質半導体膜と第１導電型非晶質半導体膜とが接していることが好ましい。この場合にも、短絡電流密度の特性に優れたヘテロバックコンタクトセルとすることができる。 (26) In the heterojunction back contact cell of the embodiment disclosed herein, it is preferable that the first i-type amorphous semiconductor film and the first conductive amorphous semiconductor film are in contact with each other. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
　（２７）ここで開示された実施形態のヘテロ接合型バックコンタクトセルにおいて、第２のｉ型非晶質半導体膜と第２導電型非晶質半導体膜とが接していることが好ましい。この場合にも、短絡電流密度の特性に優れたヘテロバックコンタクトセルとすることができる。 (27) In the heterojunction back contact cell of the embodiment disclosed herein, it is preferable that the second i-type amorphous semiconductor film and the second conductive amorphous semiconductor film are in contact with each other. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
　（２８）ここで開示された実施形態のヘテロ接合型バックコンタクトセルにおいて、第１導電型非晶質半導体膜と第２導電型非晶質半導体膜との間に第２のｉ型非晶質半導体膜の端部が位置していることが好ましい。この場合にも、短絡電流密度の特性に優れたヘテロバックコンタクトセルとすることができる。 (28) In the heterojunction back contact cell of the embodiment disclosed herein, the second i-type amorphous semiconductor film is interposed between the first conductive amorphous semiconductor film and the second conductive amorphous semiconductor film. The end of the semiconductor film is preferably located. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
　（２９）ここで開示された実施形態のヘテロ接合型バックコンタクトセルにおいて、第２のｉ型非晶質半導体膜の端部が、第１導電型非晶質半導体膜および第２導電型非晶質半導体膜のそれぞれと接していることが好ましい。この場合にも、短絡電流密度の特性に優れたヘテロバックコンタクトセルとすることができる。 (29) In the heterojunction back contact cell according to the embodiment disclosed herein, the end of the second i-type amorphous semiconductor film is formed of the first conductive type amorphous semiconductor film and the second conductive type amorphous semiconductor. It is preferable to be in contact with each of the crystalline semiconductor films. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
　（３０）ここで開示された実施形態のヘテロ接合型バックコンタクトセルにおいて、半導体基板は、ｎ型結晶シリコンを含むことが好ましい。この場合にも、短絡電流密度の特性に優れたヘテロバックコンタクトセルとすることができる。 (30) In the heterojunction back contact cell of the embodiment disclosed herein, the semiconductor substrate preferably contains n-type crystalline silicon. Also in this case, a hetero back contact cell having excellent short-circuit current density characteristics can be obtained.
　以上のように本発明の実施形態について説明を行なったが、上述の各実施形態の構成を適宜組み合わせることも当初から予定している。 As described above, the embodiments of the present invention have been described, but it is also planned from the beginning to appropriately combine the configurations of the above-described embodiments.
　今回開示された実施形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。 The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
　ここで開示された実施形態は、ヘテロ接合型バックコンタクトセルおよびその製造方法に好適に利用することができる。 The embodiment disclosed herein can be suitably used for a heterojunction back contact cell and a manufacturing method thereof.
　１，１００　半導体基板、１ａ　第１の面、１ｂ　第２の面、２　第１のｉ型非晶質半導体膜、３　第１導電型非晶質半導体膜、４　第２のｉ型非晶質半導体膜、５　第２導電型非晶質半導体膜、６　誘電体膜、６ａ　第１誘電体膜、６ｂ　第２誘電体膜、７　第１電極、８　第２電極、９　金属膜、３１，３２，３３　エッチングマスク、５１，５２，６１　積層体、１００ａ　受光面、１００ｂ　裏面、１１２　ＩＮ積層体、１１２ｉ，１１３ｉ，１１７ｉ，１２１，１２４　ｉ型非晶質半導体層、１１２ｎ，１１７ｎ，１２２　ｎ型非晶質半導体層、１１３　ＩＰ積層体、１１３ｐ，１２５　ｐ型非晶質半導体層、１１４　ｎ側電極、１１５　ｐ側電極、１１６，１１８，１２３　絶縁層、１１９　積層体、１１９ａ，１１９ｂ，１１９ｃ，１１９ｄ　導電層。 1,100 semiconductor substrate, 1a first surface, 1b second surface, 2nd first i-type amorphous semiconductor film, 3rd first conductivity type amorphous semiconductor film, 4th second i-type amorphous Semiconductor film, 5 Second conductive type amorphous semiconductor film, 6 Dielectric film, 6a First dielectric film, 6b Second dielectric film, 7 First electrode, 8 Second electrode, 9 Metal film, 31, 32 33, etching mask, 51, 52, 61 laminate, 100a light receiving surface, 100b back surface, 112 IN laminate, 112i, 113i, 117i, 121, 124 i-type amorphous semiconductor layer, 112n, 117n, 122 n-type non-layer Crystalline semiconductor layer, 113 IP stack, 113p, 125 p-type amorphous semiconductor layer, 114 n-side electrode, 115 p-side electrode, 116, 118, 123 insulating layer, 119 stack, 119a, 119b, 1 9c, 119d conductive layer.

Claims (9)

  1. 　半導体基板の第１の面に接するように、窒素と珪素とを含む誘電体膜を形成する工程と、
    　前記半導体基板の前記第１の面と反対側の第２の面側に、第１導電型非晶質半導体膜および第２導電型非晶質半導体膜を形成する工程と、
    　前記第１導電型非晶質半導体膜上に第１電極を形成する工程と、
    　前記第２導電型非晶質半導体膜上に第２電極を形成する工程と、を含む、ヘテロ接合型バックコンタクトセルの製造方法。     Forming a dielectric film containing nitrogen and silicon so as to be in contact with the first surface of the semiconductor substrate;
    Forming a first conductivity type amorphous semiconductor film and a second conductivity type amorphous semiconductor film on a second surface side opposite to the first surface of the semiconductor substrate;
    Forming a first electrode on the first conductive type amorphous semiconductor film;
    Forming a second electrode on the second conductive amorphous semiconductor film. A method of manufacturing a heterojunction back contact cell.
  2. 　前記誘電体膜を形成する工程は、前記第２の面側に前記第１導電型非晶質半導体膜および前記第２導電型非晶質半導体膜を形成する工程の前に行われる、請求項１に記載のヘテロ接合型バックコンタクトセルの製造方法。 The step of forming the dielectric film is performed before the step of forming the first conductive type amorphous semiconductor film and the second conductive type amorphous semiconductor film on the second surface side. 2. A method for producing a heterojunction back contact cell according to 1.
  3. 　前記誘電体膜を形成する工程は、前記第２の面側に前記第１導電型非晶質半導体膜および前記第２導電型非晶質半導体膜を形成する工程の後に行われる、請求項１に記載のヘテロ接合型バックコンタクトセルの製造方法。 The step of forming the dielectric film is performed after the step of forming the first conductive type amorphous semiconductor film and the second conductive type amorphous semiconductor film on the second surface side. A method for producing a heterojunction back contact cell according to claim 1.
  4. 　前記誘電体膜は、酸素、炭素およびフッ素からなる群より選択された１つ以上をさらに含む、請求項１～請求項３のいずれか１項に記載のヘテロ接合型バックコンタクトセルの製造方法。 The method of manufacturing a heterojunction back contact cell according to any one of claims 1 to 3, wherein the dielectric film further includes one or more selected from the group consisting of oxygen, carbon, and fluorine.
  5. 　第１導電型または第２導電型の半導体基板と、
    　前記半導体基板の第１の面に接するように設けられた、窒素と珪素とを含む誘電体膜と、
    　前記半導体基板の前記第１の面と反対側の第２の面側に設けられた、第１導電型非晶質半導体膜および第２導電型非晶質半導体膜と、
    　前記第１導電型非晶質半導体膜上の第１電極と、
    　前記第２導電型非晶質半導体膜上の第２電極と、を備える、ヘテロ接合型バックコンタクトセル。     A semiconductor substrate of a first conductivity type or a second conductivity type;
    A dielectric film containing nitrogen and silicon provided in contact with the first surface of the semiconductor substrate;
    A first conductivity type amorphous semiconductor film and a second conductivity type amorphous semiconductor film provided on a second surface side opposite to the first surface of the semiconductor substrate;
    A first electrode on the first conductive type amorphous semiconductor film;
    A heterojunction back contact cell comprising: a second electrode on the second conductive type amorphous semiconductor film.
  6. 　前記誘電体膜は、前記第１の面から離れるにつれて前記珪素の含有量が低減する、請求項５に記載のヘテロ接合型バックコンタクトセル。 The heterojunction back contact cell according to claim 5, wherein the dielectric film has a content of silicon that decreases as the distance from the first surface increases.
  7. 　前記珪素の含有量は、前記第１の面から離れるにつれて連続的に低減する、請求項６に記載のヘテロ接合型バックコンタクトセル。 The heterojunction back contact cell according to claim 6, wherein the silicon content continuously decreases as the distance from the first surface increases.
  8. 　前記珪素の含有量は、前記第１の面から離れるにつれて段階的に低減する、請求項６に記載のヘテロ接合型バックコンタクトセル。 The heterojunction back contact cell according to claim 6, wherein the silicon content decreases stepwise as the distance from the first surface increases.
  9. 　前記誘電体膜は、酸素、炭素およびフッ素からなる群より選択された１つ以上をさらに含む、請求項５～請求項８のいずれか１項に記載のヘテロ接合型バックコンタクトセル。 9. The heterojunction back contact cell according to claim 5, wherein the dielectric film further includes one or more selected from the group consisting of oxygen, carbon, and fluorine.
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