WO2016041156A1 - Cpu调度的方法和装置 - Google Patents

Cpu调度的方法和装置 Download PDF

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Publication number
WO2016041156A1
WO2016041156A1 PCT/CN2014/086702 CN2014086702W WO2016041156A1 WO 2016041156 A1 WO2016041156 A1 WO 2016041156A1 CN 2014086702 W CN2014086702 W CN 2014086702W WO 2016041156 A1 WO2016041156 A1 WO 2016041156A1
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storage medium
delay
delay type
access
type
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PCT/CN2014/086702
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English (en)
French (fr)
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徐君
朱冠宇
王元钢
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华为技术有限公司
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Priority to PCT/CN2014/086702 priority Critical patent/WO2016041156A1/zh
Priority to CN201480036990.2A priority patent/CN105612505B/zh
Publication of WO2016041156A1 publication Critical patent/WO2016041156A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices

Definitions

  • Embodiments of the present invention relate to the field of computers, and, more particularly, to a method and apparatus for CPU scheduling.
  • a storage device connected to a Central Processing Unit (CPU) through a memory bus may include different types of storage media.
  • the access latency of the CPU is different.
  • the CPU accesses different types of storage devices through unified paths and instructions, it cannot distinguish the type of storage media to be accessed. Therefore, when the CPU chooses to wait for the currently running process, the extended storage medium during access will occupy the kernel for a long time. Resources cause a waste of CPU resources; when the CPU chooses to suspend the currently running process, the overhead of the system is too large for a storage medium with a short access time.
  • the embodiment of the invention provides a method and a device for scheduling a CPU, which can reduce the waste of CPU resources and reduce the overhead of the system.
  • the first aspect provides a method for scheduling a CPU, where the method is applied to an integrated storage device, where the integrated storage device includes a plurality of different types of storage media, the method includes: obtaining an access address of a current access operation; The access address determines a storage medium accessed by the access operation; determines a delay type of the storage medium; and in the case where it is determined that the delay type of the storage medium is the first delay type, suspending the process of running the access operation; determining the delay of the storage medium When the type is the second delay type, the process of the access operation is continued, wherein the access delay of the storage medium of the first delay type is greater than the access delay of the storage medium of the second delay type.
  • the determining a delay type of the storage medium includes: acquiring an access delay of the storage medium; if the access delay of the storage medium is greater than a preset The value of the storage medium is determined to be the first delay type. If the storage medium is not greater than the preset value, the delay type of the storage medium is determined to be the second delay type.
  • the determining a delay type of the storage medium includes: obtaining a correspondence between a preset storage medium and a delay type of the storage medium According to the correspondence, the delay type of the storage medium is determined.
  • the method before determining the delay type of the storage medium, further includes: determining to wait for the access operation Whether the access data is stored in the cache; determining the type of the delay of the storage medium corresponding to the memory access address comprises: determining the type of the delay of the storage medium in the case of determining that the data to be accessed is not stored in the cache.
  • the first delay type storage medium comprises a hard disk drive HDD, a solid state hard disk SSD, and a nonvolatile At least one storage medium in the flash NAND flash
  • the second delay type storage medium includes at least one of a dynamic random access memory DRAM and a nonvolatile solid state memory NVM.
  • a second aspect provides a device for scheduling a CPU, where the device is applied to an integrated storage device, where the integrated storage device includes a plurality of different types of storage media, and the device includes: an acquiring module, configured to acquire a current access operation.
  • the first determining module is configured to determine, according to the access address obtained by the obtaining module, the storage medium accessed by the access operation; the second determining module is configured to determine a delay type of the storage medium; and the executing module is configured to determine the second
  • the delay type of the storage medium determined by the module is the first delay type, the process of running the access operation is aborted; when the delay type of the storage medium determined by the second determining module is the second delay type, the access operation is continued.
  • the process wherein the access delay of the storage medium of the first delay type is greater than the access delay of the storage medium of the second delay type.
  • the second determining module is specifically configured to: obtain an access delay of the storage medium; if the access delay of the storage medium is greater than a preset value, determine the storage medium The delay type is the first delay type. If the access delay of the storage medium is not greater than the preset value, the delay type of the storage medium is determined to be the second delay type.
  • the second determining module includes: an acquiring unit, configured to acquire a correspondence between a preset storage medium and a delay type of the storage medium; And a unit, configured to determine a delay type of the storage medium according to the correspondence obtained by the obtaining unit.
  • the apparatus further includes: a third determining module, configured to determine whether the to-be-accessed data of the access operation is stored in the cache, where the second determining module is specifically configured to determine, in the third determining module, the data to be accessed In the case where it is not stored in the cache, the type of delay of accessing the storage medium is determined.
  • the first delay type storage medium comprises a hard disk drive HDD, a solid state hard disk SSD, and a nonvolatile At least one storage medium in the flash NAND flash
  • the second delay type storage medium includes at least one of a dynamic random access memory DRAM and a nonvolatile solid state memory NVM.
  • a storage device in a third aspect, includes a controller and a plurality of different types of storage media.
  • the storage medium is configured to store data; the controller is configured to: obtain an access address of the current access operation; determine a storage medium accessed by the access operation according to the access address; determine a delay type of the storage medium; and determine a delay type of the storage medium as In the case of the first delay type, the process of running the access operation is suspended; in the case where it is determined that the delay type of the storage medium is the second delay type, the process of the access operation is continued, wherein the storage of the first delay type The access delay of the medium is greater than the access delay of the storage medium of the second delay type.
  • the controller is specifically configured to: obtain an access delay of the storage medium; and determine a delay of the storage medium if an access delay of the storage medium is greater than a preset value The type is the first delay type. If the access delay of the storage medium is not greater than the preset value, the delay type of the storage medium is determined to be the second delay type.
  • the controller is specifically configured to: obtain a correspondence between a preset storage medium and a delay type of the storage medium; determine, according to the corresponding relationship, the storage The type of delay for the media.
  • the controller is further configured to: determine the access operation before determining the delay type of the storage medium Whether the data to be accessed is stored in the cache; in the case where it is determined that the data to be accessed is not stored in the cache, the type of delay of the storage medium is determined.
  • the first delay type storage medium comprises a hard disk drive HDD, a solid state hard disk SSD, and a nonvolatile At least one storage medium in the flash NAND flash
  • the second delay type storage medium includes at least one of a dynamic random access memory DRAM and a nonvolatile solid state memory NVM.
  • the CPU scheduling method determines the storage medium accessed by the current access operation according to the access address by obtaining the access address of the current access operation, and further determines the delay type of the storage medium.
  • the delay type of the storage medium is a type with a large delay
  • the process of performing the current access operation is suspended, and the process switching is implemented.
  • it is determined that the storage medium is of a type that is accessed less it continues to wait for the current access process to be executed. According to this manner, the waiting time of the access operation can be reduced to some extent, and the processing efficiency of the process can be improved, thereby reducing the waste of CPU resources and reducing the overhead of the system.
  • FIG. 1 is a schematic diagram of an application scenario according to an embodiment of the present invention.
  • FIG. 2 shows a schematic flow chart of a method of CPU scheduling according to an embodiment of the present invention.
  • FIG. 3 shows a schematic flow chart of a method for CPU scheduling according to another embodiment of the present invention.
  • FIG. 4 shows a schematic flow chart of a method for CPU scheduling according to another embodiment of the present invention.
  • FIG. 5 shows a schematic flow chart of a method for CPU scheduling according to another embodiment of the present invention.
  • FIG. 6 shows a schematic interaction process diagram of a method of CPU scheduling according to another embodiment of the present invention.
  • FIG. 7 shows a schematic block diagram of an apparatus for CPU scheduling in accordance with one embodiment of the present invention.
  • FIG. 8 shows a schematic block diagram of an apparatus for CPU scheduling according to another embodiment of the present invention.
  • Figure 9 shows a schematic block diagram of a memory device in accordance with one embodiment of the present invention.
  • FIG. 1 is a schematic diagram of an application scenario according to an embodiment of the present invention.
  • the system includes a central processing unit (CPU) (100) and a storage device (106). To connect through the memory bus.
  • the CPU integrates a CPU core (101), a Memory Management Unit (MMU) (102), a Translation Lookaside Buffer (TLB) (103), a cache (104), and a message type.
  • MMC Memory Controller
  • the storage device shown in the figure includes three different types of storage media, but the method of the embodiment of the present invention is not limited thereto, and may be one, two or more than three types of storage media. It should be understood that the storage device shown in FIG. 1 may be a Unified Access Storage (UAS), the UAS includes a controller and multiple types of storage media, and the UAS includes multiple storage media that can pass through the same memory access interface. Was visited.
  • UAS Unified Access Storage
  • the process in which the CPU core writes data to be accessed or reads data to be accessed from the storage device may include the following steps:
  • Step 1 The CPU core initiates an access request for the current access operation, where the access request includes a virtual address corresponding to the to-be-accessed data of the current access operation.
  • Step 2 The MMU queries the TLB according to the virtual address.
  • step 3 the TLB feeds back the physical address corresponding to the virtual address to the MMU.
  • step 4 the MMU feeds back the physical address corresponding to the data to be accessed to the CPU core.
  • step 5 the CPU core accesses the cache according to the physical address.
  • Step 6 When the data to be accessed is not stored in the cache, that is, in the case of a cache miss, the CPU core sends the physical address to the MMC.
  • the MMC writes or reads the data to be accessed in the corresponding storage medium in the storage device according to the physical address.
  • the storage device feeds back to the MMC that the data to be accessed has been written or read.
  • the MMC replaces the read data to be read into the cache.
  • the CPU core reads the data to be accessed from the cache or the message that the CPU core receives the MMC feedback and the data to be accessed has been written.
  • the type of the storage medium to be accessed cannot be distinguished when the CPU accesses the storage medium through a unified path and instructions, the overhead of the system cannot be reduced according to the access delay characteristic of the storage medium.
  • the CPU core accesses the cache cache according to the physical address, and when the cache stores the data to be accessed, that is, in the case of a cache hit, if the CPU core wants to write the data of the physical address.
  • the CPU core can update the data stored in the cache, or the data corresponding to the physical address that the CPU core needs to read is stored in the cache, and the CPU core can directly read from the cache according to the physical address.
  • the data That is to say, in the case of a cache hit, the CPU core does not need to access the storage medium, and the memory access request can be quickly completed in the cache, so there is no problem that the access delay is different due to different types of storage media. .
  • the CPU core accesses the cache cache according to the physical address, including: the CPU core sends a physical address to the cache; the cache receives the physical address sent by the CPU core, and determines the cache according to the physical address. Whether the data to be accessed is stored.
  • a process is the execution of a program (instructions and data) that is running.
  • the access latency of a storage medium refers to the time required for the CPU to perform a read operation on the storage medium.
  • FIG. 2 shows a schematic flow diagram of a method 200 of CPU scheduling in accordance with one embodiment of the present invention.
  • the method 200 of FIG. 2 can be applied to an integrated storage device, wherein the integrated storage device includes a plurality of different types of storage media, and the method 200 includes:
  • Step 210 Obtain an access address of the current access operation.
  • the access address may include a virtual address, a physical address, or another access address, where the virtual address is a non-physical access address in the virtual address space, and the physical address is an actual address in the physical address space.
  • the access address that is, the actual access address to which the CPU is to write data, or the actual access address at which the CPU is to read data.
  • Current access operations may include read operations, write operations, or other operations.
  • Step 220 Determine, according to the access address obtained in step 210, a storage medium accessed by the current access operation.
  • the storage medium corresponding to the physical address may be determined according to the physical address.
  • the virtual address may be determined according to the virtual address.
  • the storage medium corresponding to the access address may be determined by querying the correspondence between the access address of the storage medium stored in the local or storage device and the storage medium.
  • the access address is within a range of address spaces corresponding to a certain storage medium, it can be determined that the storage medium corresponding to the access address is the storage medium, for example, the access address obtained in step 210 is a physical address.
  • the physical address is in the range of 0-4 GB physical address space, and the physical address space of the storage medium DRAM corresponds to 0-4 GB physical address space, it can be determined that the storage medium corresponding to the physical address is DRAM.
  • the access address obtained in step 210 is virtual
  • the storage medium corresponding to the virtual address may also be determined according to this method. For the sake of brevity, no further details are provided herein.
  • Step 230 Determine a delay type of the storage medium according to the determining the storage medium in step 220.
  • the delay type of the storage medium may be determined according to the correspondence between the storage medium and the delay type of the storage medium.
  • the delay type of the storage medium corresponding to the memory access address may be determined according to the correspondence between the memory access address and the delay type of the storage medium.
  • Step 240 In a case where it is determined that the delay type of the storage medium is the first delay type, the process of running the current access operation is suspended.
  • the process of suspending the current access operation refers to a process that can suspend the current access operation, so that the process of the current access operation enters a dormant state, thereby releasing the CUP resource occupied by the current access operation process, and facilitating the process.
  • Step 250 If it is determined that the delay type of the storage medium is the second delay type, the process of performing the access operation is continued, where the access delay of the storage medium of the first delay type is greater than the storage of the second delay type. Media access latency.
  • the CPU scheduling method determines the access medium of the current access operation, determines the storage medium accessed by the current access operation according to the access address, and further determines the delay type of the storage medium, when determining the storage medium.
  • the type of the delay type is a type with a large delay
  • the process of performing the current access operation is aborted, and the process switching is implemented.
  • it continues to wait for the current access process to be executed. According to this manner, the waiting time of the access operation can be reduced to some extent, and the processing efficiency of the process can be improved, thereby reducing the waste of CPU resources and reducing the overhead of the system.
  • an access delay of the storage medium may be acquired; if the access delay of the storage medium is greater than a preset value, determining that the delay type of the storage medium is the first delay type; The access delay of the storage medium is not greater than a preset value, and the delay type of the storage medium is determined to be a second delay type.
  • the delay type of the storage medium is compared with the preset value, and the delay type of the storage medium is determined to be the first delay type or the second delay type.
  • the access delay of the storage medium of the delay type is greater than the access delay of the storage medium of the second delay type.
  • the comparison process may be performed only once, and the comparison result, that is, the correspondence between the storage medium and the delay type of the storage medium, is stored to the local or storage device.
  • the storage relationship may be searched directly to the local device or the storage device to determine the type of the delay of the storage medium.
  • the embodiment of the present invention is not limited thereto.
  • the CPU may also be in the CPU.
  • the preset value may be determined according to the time required for the CPU core to perform a read operation on the storage medium, and may be configured in advance.
  • the delay type of the storage medium is determined to be the first according to a relative proportional relationship between the access delay of the storage medium and the time resource overhead of the process switching by the CPU.
  • the delay type is still the second delay type. For example, when the access delay of the storage medium exceeds 4 times of the time resource overhead of the process switching by the CPU, it is determined that the delay type of the storage medium is the first delay type, otherwise, the delay type of the storage medium is determined to be the second time. Extension type.
  • the relative proportional relationship between the access delay of the storage medium and the time resource overhead of the process switching by the CPU is not limited to four times, and may be increased or decreased.
  • the present invention is implemented by way of example only. The technical methods of the examples are described without any limitation on the embodiments of the present invention.
  • determining whether the delay type of the storage medium is the first delay type or the first according to the relative proportional relationship between the access delay of the storage medium and the time resource overhead of the process switching by the CPU.
  • the process of the two-latency type may also be performed only once, and the determined result, that is, the correspondence between the storage medium and the delay type of the storage medium is stored in the local or storage device, and when the CPU core initiates the memory access request again, The storage relationship is directly searched for in the local device or the storage device, and the delay type of the storage medium is determined, but the embodiment of the present invention is not limited thereto.
  • the delay type of the storage medium when the access delay of the storage medium is greater than the preset value, the delay type of the storage medium is determined to be the first delay type; when the access delay of the storage medium is not greater than the preset value, The delay type of the storage medium is determined to be a second delay type.
  • the storage medium of the first delay type may include a hard disk drive (HDD), a solid state disk (SSD), and a non-volatile flash memory (NAND Flash).
  • the at least one storage medium, the second delay type storage medium may include at least one of a dynamic random access memory (DRAM) and a non-volatile memory (NVM).
  • DRAM dynamic random access memory
  • NVM non-volatile memory
  • non-volatile solid-state memory may include a phase change memory (PCM) and a magnetic memory (Magnetic Random Access Memory, At least one of MRAM) and Resistive Random Access Memory (RRAM), or NVM may also include other new types of memory, and embodiments of the present invention are not limited thereto.
  • PCM phase change memory
  • RRAM Resistive Random Access Memory
  • a correspondence between a preset storage medium and a delay type of the storage medium may be acquired, and then determining a delay of the storage medium according to the obtained correspondence relationship.
  • the type is the first delay type or the second delay type, where the access delay of the storage medium of the first delay type is greater than the access delay of the storage medium of the second delay type.
  • the correspondence between the preset storage medium and the delay type of the storage medium may be a correspondence between a storage medium pre-stored in the local or storage device and a delay type of the storage medium.
  • the method 200 further includes:
  • Step 260 Determine whether the to-be-accessed data of the current access operation is stored in the cache.
  • Step 230 In step 260, if it is determined that the to-be-accessed data is not stored in the cache, determine a delay type of the storage medium.
  • the cache may include all levels of cache cache in the CPU, a cache in the message memory controller MMC, or a cache in the cache in the software manager, and when the storage device is When the storage device UAS is integrated, it also includes the cache in the controller of the UAS. For example, in step 260, it may be determined in sequence according to the memory access address whether the data to be accessed is stored in each level of the cache in the CPU, the cache in the MMC, and the cache in the cache in the controller of the UAS, when step 260 When it is determined that the data to be accessed is not stored in any of the caches of the caches, the delay type of the storage medium is determined in step 230.
  • the to-be-accessed data when it is determined that the to-be-accessed data is stored in the cache, it may be implemented according to the prior art, that is, directly reading the to-be-accessed data from the cache or updating the to-be-accessed data. Go to the cache.
  • the to-be-accessed data when it is determined that the to-be-accessed data is stored in the cache, it may be implemented according to the prior art, that is, directly reading the to-be-accessed data from the cache or updating the to-be-accessed data. Go to the cache.
  • FIG. 4 shows a schematic flow chart of a method 300 of CPU scheduling according to another embodiment of the present invention.
  • the method 300 shown in FIG. 4 illustrates the solution of the embodiment of the present invention by taking the access address as a physical address as an example, as shown in FIG. 4 .
  • Step 310 Acquire an access address of a current access operation, where the access address is a physical address.
  • Step 320 Determine, according to the physical address obtained in step 310, a storage medium corresponding to the physical address.
  • Step 330 Determine a delay type of the storage medium according to the storage medium determined in step 320.
  • the delay type of the storage medium may be compared according to the comparison result of the storage medium, and the delay type of the storage medium may be determined according to the comparison result. For example, when the access delay of the storage medium is greater than a preset value, the The delay type of the storage medium is the first delay type. When the access delay of the storage medium is not greater than the preset value, the delay type of the storage medium may be determined to be the second delay type.
  • the preset value may be determined according to a time required by the kernel to perform a read operation on the storage medium.
  • the first preset value may be set to 100 ⁇ s-1 ms, for example, the first preset.
  • the value can be set to 500 ⁇ s, and the time for the CPU to perform a read operation on the HDD is 4 ms, which is greater than the first preset value of 500 ⁇ s. Therefore, the delay type of the HDD is the first delay type, that is, the HDD is the storage of the first delay type. medium.
  • the second preset value can be set to 600 ns-1 ⁇ s.
  • the second preset value can be set to 800 ns, and the CPU performs a read operation on the DRAM for 600 ns, which is less than the second preset value of 800 ns, so the DRAM
  • the delay type is the second delay type, that is, the DRAM is a storage medium of the second delay type.
  • the first preset value and the second preset value may be set to the same value, for example, may be set to 1 ⁇ s-100 ⁇ s, for example, may be set to 60 ⁇ s, and the CPU performs a read operation on the NVM for 300 ns, which is less than
  • the preset value is 60 ⁇ s
  • the delay type of the NVM is the second delay type, that is, the NVM is the storage medium of the second delay type
  • the time for the CPU to perform a read operation on the SSD is 70 ⁇ s, which is greater than the preset value of 60 ⁇ s
  • the delay type of the SSD is the first delay type, that is, the SSD is the storage medium of the first delay type.
  • the correspondence between the storage medium stored in the local or storage device and the delay type of the storage medium may also be obtained, and the delay type of the storage medium is determined.
  • the correspondence between the storage medium and the delay type of the storage medium can be obtained by querying a correspondence table or a document corresponding to the correspondence between the storage medium stored in the local storage device and the storage medium. And determining the type of delay of the storage medium.
  • the delay type of the storage medium and the storage medium may be obtained by querying a correspondence table or a document corresponding to a correspondence between a physical address of the storage medium stored in the local storage device and the delay type of the storage medium. The correspondence between the two, and then determine the type of delay of the storage medium.
  • the correspondence table may include: a storage medium and a delay type of the storage medium.
  • the correspondence table can be as shown in Table 1.
  • 0 can represent the second delay type
  • “1” can represent the first delay type
  • the delay type of the HDD is the first delay type
  • the delay type of the NVM is the second delay type.
  • the second delay type storage medium may be represented by "Y”.
  • "X" indicates the first delay type storage medium, or is directly expressed as "second delay type” and "first delay type” and the like.
  • the correspondence between the storage medium and the physical address space range of the storage medium may be obtained before the correspondence between the storage medium and the delay type of the storage medium is obtained, for example, It is a correspondence table as shown in Table 2.
  • the physical address space corresponding to the storage medium DRAM is in the range of 0-4 GB. It should be understood that the address space of the DRAM may be continuous or discrete, and the embodiment of the present invention is not limited.
  • the storage medium corresponding to the physical address is DRAM, and according to the correspondence between Table 1, the delay type of the DRAM is determined to be the second delay type.
  • the correspondence table may further include: a starting physical address and an ending physical address of the storage medium, for example, a physical space of a storage device including a plurality of storage media of different delays is 64M,
  • the correspondence table can be as shown in Table 3.
  • the storage medium corresponding to the physical address is DRAM
  • the delay type of the DRAM is the second delay type.
  • the delay type of the storage medium corresponding to the physical address is the second delay type. Therefore, the delay type of the storage medium corresponding to the physical address can be directly determined according to the correspondence between the physical address and the delay type of the storage medium.
  • the physical address of the storage medium shown in Table 2 and Table 3 may be determined according to the actual situation, and is only used to explain the technical solution of the embodiment of the present invention, and is not limited to the embodiment of the present invention, but needs to be pointed out.
  • the corresponding physical address space of the storage medium DRAM, HDD, SSD, NVM, etc. is a physical address space that does not overlap.
  • the physical address is taken as an example for detailed description, but the embodiment of the present invention is not limited thereto.
  • the correspondence table may also include: a virtual address, a storage medium, and a delay.
  • the virtual address can include a starting virtual address of the storage medium, ending the virtual address. For the sake of brevity, it will not be repeated here.
  • step 330 When it is determined in step 330 that the delay type of the storage medium is the first delay type, and the current access operation is a read operation, the following steps are performed:
  • Step 341a suspending the process of the current access operation, and reading the to-be-accessed data of the current access operation from the storage medium.
  • the MMC may send an interrupt request to the CPU core, where the interrupt request triggers the CPU to suspend the currently running process, that is, the CPU core can release the CPU resources occupied by the currently running process, so that Other processes that are running consume this CPU resource.
  • step 342a when the reading of the data to be accessed is completed, the process suspended before the operation is resumed.
  • the MMC can send a recovery request to the CPU core that triggers the process that was suspended before the CPU core resumes operation.
  • the process that is suspended before the recovery is resumed may be re-tuned into the ready queue for queuing, or the process may be preferentially run directly in the form of a queue.
  • step 330 When it is determined in step 330 that the delay type of the storage medium is the second delay type, and the current access When the operation is a read operation, perform the following steps:
  • Step 341b reading the data to be accessed from the storage medium.
  • step 342b when the reading of the data to be accessed is completed, the process of the current access operation is continued.
  • the third request is sent to the CPU core.
  • a message for example, can send a trigger request to the CPU core that triggers the CPU core to run the currently waiting process.
  • the currently waiting process refers to a process that occupies CPU core resources but does not run.
  • the CPU scheduling method determines the access medium of the current access operation, determines the storage medium accessed by the current access operation according to the access address, and further determines the delay type of the storage medium, when determining the storage medium.
  • the type of the delay type is a large delay
  • the process of performing the current access operation is aborted, and the process switching is implemented.
  • the storage medium is determined to be of a type with a small delay
  • the process of continuing to wait for execution is continued. To some extent, the waiting time of the access operation is reduced, and the processing efficiency of the process is improved, thereby reducing the waste of CPU resources and reducing the overhead of the system.
  • the current access operation when the current access operation is a write operation, the current access operation may be implemented according to the prior art, that is, the data to be accessed may be written to the storage without determining the delay type of the storage medium corresponding to the memory access address. medium. It can also be implemented according to the process in the embodiment of the present invention, that is, it is determined in step 320 that the delay type of the storage medium is the first delay type, and when the data to be accessed is written, the CPU core can be scheduled to suspend the current operation. The process is performed, and the data to be accessed is written into the storage medium; when the writing of the data to be accessed is completed, the CPU is scheduled to resume the process that is suspended before the running, and the embodiment of the present invention is not limited thereto.
  • the technical solution in the embodiment of the present invention can also support the hyper-threading technology.
  • the two logical cores can be simulated into two physical cores by using special hardware support, so that a single processor can use the thread.
  • the characteristics of the level of parallel computing, for the storage medium of the second delay type the thread or process can be quickly switched between multiple sets of registers of the CPU, without
  • the context of a thread or process is loaded in a storage medium of a two-latency type, and the overhead of such switching is much smaller than the overhead of accessing the storage medium of the second delay type, so no CPU waits; and for the first delay
  • a type of storage medium because its access delay is long, the CPU waits to cause excessive overhead, and the context of the thread or process needs to be loaded from the storage medium of the first delay type, which requires the CPU to perform process switching, thereby reducing Overhead.
  • FIG. 5 shows a schematic flow diagram of a method 500 of CPU scheduling in accordance with another embodiment of the present invention. As shown in Figure 5,
  • Step 510 Obtain an access address of the current access operation.
  • Step 520 Determine, according to the access address obtained in step 510, whether the data to be accessed of the current access operation is stored in the cache.
  • the cache may be a cache cache of various levels in the CPU 100 in FIG. 1 .
  • Step 530a when it is determined in step 520 that the data to be accessed is not stored in the cache, determine the storage medium corresponding to the access address according to the access address obtained in step 510.
  • Step 540a Determine a delay type of the storage medium according to the storage medium determined in step 530a.
  • step 540a When it is determined in step 540a that the delay type of the storage medium is the first delay type, and the current access operation is a read operation, the following steps are performed:
  • step 541a the currently running process is suspended, and the data to be accessed is read from the storage medium.
  • step 542a when the reading of the data to be accessed is completed, the CPU kernel is scheduled to resume the process that was suspended before the operation.
  • step 540a When it is determined in step 540a that the delay type of the storage medium is the second delay type or when it is determined in step 520 that the data to be accessed is already stored in the cache, the following steps are performed:
  • Step 541b controlling to read the data to be accessed from the storage medium.
  • step 542b when the reading of the data to be accessed is completed, the CPU core is scheduled to run the currently waiting process.
  • the CPU scheduling method determines the access address of the current access operation, determines that the to-be-accessed data of the access operation is not stored in the cache according to the access address, determines the storage medium corresponding to the access address, and further determines The type of the delay of the storage medium.
  • the process of performing the current access operation is suspended, and the process switching is implemented.
  • the waiting time of the access operation can be reduced to some extent, and the processing efficiency of the process can be improved, thereby further reducing the waste of CPU resources and reducing the overhead of the system.
  • FIG. 6 shows a schematic interaction process diagram of a method 600 of CPU scheduling in accordance with another embodiment of the present invention.
  • the method of FIG. 6 may be performed by a CPU, wherein a delay type of a storage medium corresponding to a physical address may be determined by a message type memory controller MMC within the CPU.
  • the method 600 shown in FIG. 6 is an example of FIG. 2, FIG. 4 or FIG. 5, as shown in FIG.
  • step 610 the CPU core sends the physical address of the current access operation to the MMC.
  • step 620 the MMC receives the physical address sent by the CPU core.
  • step 630 it is determined that the to-be-accessed data of the current access operation is not stored in the cache in the MMC.
  • Step 640 The MMC determines the delay type of the storage medium corresponding to the physical address as the first delay type by querying the corresponding relationship between the storage medium and the storage medium type.
  • the MMC can determine the delay type of the storage medium corresponding to the physical address as the first delay type by comparing the relationship between the access delay of the storage medium corresponding to the physical address and the preset value.
  • the storage medium of the first delay type may be HDD, SSD or NAND Flash.
  • step 650 the MMC sends an interrupt request to the CPU core, the interrupt request is used to instruct the CPU core to suspend the currently running process.
  • step 660 the CPU core receives the interrupt request sent by the MMC, and suspends the currently running process according to the instruction of the interrupt request.
  • Step 670 The MMC reads the data to be accessed from the storage medium corresponding to the physical address.
  • step 660 the MMC sends a recovery request to the CPU core, the recovery request is used to instruct the CPU kernel to resume the previously suspended process.
  • the MMC needs to store the to-be-accessed data read from the storage medium corresponding to the physical address into the cache, so that step 660 can be performed.
  • Step 690 The CPU core receives the recovery request sent by the MMC, and resumes the process that was suspended before the operation according to the instruction of the recovery request.
  • the CPU scheduling method determines the physical address corresponding to the physical address, and determines the storage medium corresponding to the physical address, by determining the physical address of the current access operation and determining that the to-be-accessed data of the access operation is not stored in the cache according to the physical address.
  • the delay type of the storage medium When it is determined that the delay type of the storage medium is a type with a large delay, the process of performing the current access operation is suspended. The process is now switched, which can further reduce the waste of CPU resources and reduce the overhead of the system.
  • the step 640 may include: determining, by the MMC, the delay of the storage medium by receiving an indication message that the delay type of the storage medium corresponding to the physical address fed back by the controller of the UAS is the first delay type.
  • the type is the first delay type.
  • step 630 If it is determined in step 630 that the data to be accessed is already stored in the cache in the MMC, the data to be accessed is directly read from the cache and stored in the cache, and the steps in step 640 and subsequent steps are not performed.
  • step 640 the MMC determines that the delay type of the storage medium corresponding to the physical address is the second delay type, and then the MMC sends a trigger request to the CPU core by querying the corresponding relationship between the locally stored storage medium and the storage medium type.
  • the request is used to instruct the CPU core to resume running the currently waiting process, and the CPU core receives the trigger request sent by the MMC, and resumes running the currently waiting process according to the indication of the trigger request, that is, the process of continuing the current access operation.
  • the storage device is a UAS, and the controller of the UAS has a cache. Then, after step 640, before step 650, the following steps are also performed:
  • step 641 the MMC sends a physical address to the controller of the UAS.
  • Step 642 the controller of the UAS determines, according to the physical address, whether the data to be accessed is stored in a cache in the controller of the UAS.
  • Step 643a (not shown in the figure), when the controller of the UAS determines that the data to be accessed is not stored in the cache in the controller of the UAS, the steps of step 650 and subsequent steps are performed;
  • Step 643b when the MMC determines that the data to be accessed is stored in the cache in the controller of the UAS, directly reads the data to be accessed from the cache, and stores it in the cache, no longer Step 650 and subsequent steps are performed.
  • FIG. 7 shows a schematic block diagram of an apparatus 700 for CPU scheduling in accordance with an embodiment of the present invention.
  • the device 700 is applied to an integrated storage device, where the integrated storage device includes a plurality of different types of storage media, and the device 700 includes an obtaining module 710, a first determining module 720, and a second determining module. 730 and execution module 740, wherein:
  • the obtaining module 710 is configured to obtain a memory access address of the current access operation.
  • the first determining module 720 is configured to determine an access address obtained by the obtaining module 710 to determine an access operation.
  • the storage medium to be accessed.
  • the second determining module 730 is configured to determine a delay type of the storage medium determined by the first determining module 720.
  • the execution module 740 is configured to suspend the process of running the access operation when the delay type of the storage medium determined by the second determining module 730 is the first delay type; the delay type of the storage medium determined by the second determining module 730 is When the second delay type is used, the process of the access operation is continued, wherein the access delay of the storage medium of the first delay type is greater than the access delay of the storage medium of the second delay type.
  • the apparatus for scheduling a CPU core determines the storage medium accessed by the current access operation according to the access address by obtaining the access address of the current access operation, and further determines the delay type of the storage medium, when determining the storage medium.
  • the delay type is a type with a large delay
  • the process of performing the current access operation is aborted, and the process switching is implemented.
  • the storage medium is determined to be of a type with a small delay
  • the process of continuing to wait for execution is continued.
  • the waiting time of the access operation can be reduced to some extent, and the processing efficiency of the process can be improved, thereby reducing the waste of CPU resources and reducing the overhead of the system.
  • the second determining module 730 is specifically configured to obtain an access delay of the storage medium; if the access delay of the storage medium is greater than a preset value, determining that the delay type of the storage medium is the first The delay type is determined. If the access delay of the storage medium is not greater than a preset value, determining that the delay type of the storage medium is the second delay type.
  • the second determining module 730 is specifically configured to obtain a correspondence between the preset storage medium and a delay type of the storage medium, and determine the storage according to the correspondence acquired by the obtaining unit.
  • the type of delay for the media is specifically configured to obtain a correspondence between the preset storage medium and a delay type of the storage medium, and determine the storage according to the correspondence acquired by the obtaining unit. The type of delay for the media.
  • the storage medium of the first delay type may include at least one of a hard disk drive (HDD), a solid state disk (SSD), and a non-volatile flash memory (NAND Flash).
  • the storage medium of the second delay type may include at least one of a dynamic random access memory (DRAM) and a non-volatile memory (NVM).
  • DRAM dynamic random access memory
  • NVM non-volatile memory
  • the apparatus 700 further includes:
  • the third determining module 750 is configured to determine whether the to-be-accessed data of the access operation is stored in the cache,
  • the second determining module 730 is specifically configured to determine a delay type of the storage medium when the third determining module 750 determines that the to-be-accessed data is not stored in the cache.
  • the apparatus 700 in the CPU scheduling according to the embodiment of the present invention may correspond to the execution body of the method according to the embodiment of the present invention, and the foregoing modules of the CPU 700 are scheduled by the CPU. And other operations and/or functions, respectively, in order to implement the corresponding processes of the respective methods in FIG. 2 to FIG. 6, for brevity, no further details are provided herein.
  • the apparatus for scheduling a CPU determines the access medium of the current access operation according to the access address, determines the storage medium accessed by the current access operation according to the access address, and further determines the delay type of the storage medium, when determining the storage medium.
  • the type of the delay type is a large delay
  • the process of performing the current access operation is aborted, and the process switching is implemented.
  • the storage medium is determined to be of a type with a small delay, the process of continuing to wait for execution is continued. To some extent, the waiting time of the access operation is reduced, and the processing efficiency of the process is improved, thereby reducing the waste of CPU resources and reducing the overhead of the system.
  • FIG. 9 shows a schematic block diagram of a memory device 900 in accordance with an embodiment of the present invention.
  • the storage device 900 includes a controller 910 and a plurality of different types of storage media 920. among them,
  • a storage medium 920 is used to store data.
  • the storage medium 920 may be an integrated storage device UAS, and the UAS includes a plurality of different types of storage media and controllers of the UAS, and the storage media may be accessed through the same memory interface.
  • the controller 910 is configured to: obtain an access address of the current access operation; determine a storage medium accessed by the access operation according to the access address; determine a delay type of the storage medium; and determine that the delay type of the storage medium is the first delay type
  • the process of running the access operation is aborted; in the case that the delay type of the storage medium is determined to be the second delay type, the process of the access operation is continued, wherein the access delay of the storage medium of the first delay type is greater than the second The access latency of the storage medium of the delay type.
  • the controller 910 may include a core core 912, a memory management unit MMU 914, a cache cache 916, and a message memory controller MMC918.
  • the core core 912 is used to obtain the access address of the current access operation
  • the MMU 914 is configured to convert the virtual address into a corresponding physical address
  • the MMC 918 can be used to determine the storage medium accessed by the access operation according to the access address, and determine the delay type of the storage medium.
  • the kernel core 912 is further configured to: when the MMC 918 determines that the delay type of the storage medium is the first delay type, suspend the process of running the access operation; and determine, in the MMC 918, the delay type of the storage medium is the second delay type. In the case, the process of the access operation continues.
  • the storage device can obtain the access address of the current access operation, determine the storage medium accessed by the current access operation according to the access address, and further determine the delay type of the storage medium, and determine the delay of the storage medium.
  • the type is a type with a large delay
  • the process of performing the current access operation is aborted, and the process switching is implemented.
  • the process of continuing to wait for execution is continued, according to this manner, To some extent, the waiting time of the access operation is reduced, and the processing efficiency of the process is improved, thereby reducing the waste of CPU resources and reducing the overhead of the system.
  • the MMC 918 can also receive the delay type of the storage medium fed back by the controller of the UAS, and the core core 912 is used to receive the delay type of the storage medium fed back by the controller of the UAS at the MMC 918.
  • the process of running the access operation is aborted; in the case where the delay type of the storage medium fed back by the controller of the UAS received by the MMC 918 is the second delay type, the process of continuing the access operation is continued. .
  • the controller 910 is specifically configured to: obtain an access delay of the storage medium; if the access delay of the storage medium is greater than a preset value, determine that the delay type of the storage medium is a first delay type; If the access delay of the storage medium is not greater than the preset value, determine that the delay type of the storage medium is the second delay type.
  • the controller 910 is specifically configured to: obtain a correspondence between a preset storage medium and a delay type of the storage medium; and determine a delay type of the storage medium according to the correspondence.
  • the controller 910 is further configured to: before determining the delay type of the storage medium, determine whether the to-be-accessed data of the current access operation is stored in the cache; and determine that the to-be-accessed data is not stored in the cache. In the case of the medium, the type of delay of the storage medium is determined.
  • the first delay type storage medium includes at least one of a hard disk drive HDD, a solid state hard disk SSD, and a nonvolatile flash NAND Flash
  • the second delay type storage medium includes dynamic randomness.
  • the storage device of the embodiment of the present invention obtains the access address of the current access operation, determines the storage medium accessed by the current access operation according to the access address, and further determines the delay type of the storage medium, and determines the delay type of the storage medium as the delay.
  • the process of executing the current access operation is aborted, and the process switching is implemented.
  • the process of continuing to wait for execution is continued, and according to this manner, the access can be reduced to some extent. Waiting time for operation In addition, improve the processing efficiency of the process, thereby reducing the waste of CPU resources and reducing the overhead of the system.
  • the controller 910 of the storage device 900 may correspond to an execution body of the method according to the embodiment of the present invention, and the controller 910 of the storage device 900 may implement The corresponding processes of the respective methods in FIG. 2 to FIG. 6 are not described herein again for the sake of brevity.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.

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Abstract

提供一种调度CPU内核的方法和装置，该方法包括：获取当前访问操作的访问地址（210）；根据访问地址确定访问操作访问的存储介质（220）；确定存储介质的时延类型（230）；在确定存储介质的时延类型为第一时延类型的情况下，中止运行访问操作的进程（240）；在确定存储介质的时延类型为第二时延类型的情况下，继续执行访问操作的进程（250）。该方法是当确定存储介质的时延类型为时延较大的类型时，中止执行访问操作的进程，实现进程切换，当确定存储介质的为时延较小的类型时，继续等待执行访问进程，根据这种方式，可以在一定程度上减少访问操作的等待时间，提高进程处理效率，从而能够减小CPU资源的浪费，降低***的开销。

Description

CPU调度的方法和装置 技术领域
本发明实施例涉及计算机领域，并且更具体地，涉及一种CPU调度的方法和装置。
背景技术
通过内存总线连接到中央处理器(Central Processing Unit，CPU)的存储设备可能包括不同类型的存储介质。而对于不同类型的存储介质，CPU的访问时延不同。当CPU通过统一的路径和指令访问不同类型的存储设备时，并不能区分要访问的存储介质的类型，所以，当CPU选择等待当前运行的进程时，访问时延长的存储介质会长时间占用内核资源，造成CPU资源的浪费；当CPU选择挂起当前运行的进程时，则对访问时延短的存储介质而言，***的开销过大。
因此，当CPU通过统一的路径和指令访问包括不同类型的存储介质的存储设备时，由于不能区分要访问的存储介质的时延类型，从而造成CPU资源的浪费和***开销较大的问题。
发明内容
本发明实施例提供一种CPU调度的方法和装置，能够减小CPU资源的浪费，降低***的开销。
第一方面，提供一种CPU调度的方法，该方法应用于一体化存储设备中，其中一体化存储设备包含有多种不同类型的存储介质，该方法包括：获取当前访问操作的访问地址；根据访问地址确定访问操作访问的存储介质；确定存储介质的时延类型；在确定存储介质的时延类型为第一时延类型的情况下，中止运行访问操作的进程；在确定存储介质的时延类型为第二时延类型的情况下，继续执行访问操作的进程，其中，第一时延类型的存储介质的访问时延大于第二时延类型的存储介质的访问时延。
结合第一方面，在第一方面的第一种可能的实现方式中，所述确定所述存储介质的时延类型包括：获取存储介质的访问时延；若存储介质的访问时延大于预设值，确定存储介质的时延类型为第一时延类型；若存储介质的访问时延不大于预设值，确定存储介质的时延类型为第二时延类型。
结合第一方面，在第一方面的第二种可能的实现方式中，所述确定所述存储介质的时延类型包括：获取预设的存储介质与存储介质的时延类型之间的对应关系；根据对应关系，确定存储介质的时延类型。
结合第一方面或上述可能的实现方式中的任一种，在第一方面的第三种可能的实现方式中，在确定存储介质的时延类型之前，该方法还包括：确定访问操作的待访问数据是否存储在缓存中；确定访存地址对应的存储介质的时延类型包括：在确定待访问数据未存储在缓存中的情况下，确定存储介质的时延类型。
结合第一方面或上述可能的实现方式中的任一种，在第一方面的第四种可能的实现方式中，第一时延类型的存储介质包括硬盘驱动器HDD、固态硬盘SSD和非易失性闪存NAND Flash中的至少一种存储介质，第二时延类型的存储介质包括动态随机存储器DRAM和非易失固态存储器NVM中的至少一种存储介质。
第二方面，提供一种CPU调度的装置，该装置应用于一体化存储设备中，其中一体化存储设备包含有多种不同类型的存储介质，该装置包括：获取模块，用于获取当前访问操作的访问地址；第一确定模块，用于根据获取模块获取的访问地址确定访问操作访问的存储介质；第二确定模块，用于确定存储介质的时延类型；执行模块，用于在第二确定模块确定的存储介质的时延类型为第一时延类型时，中止运行访问操作的进程；在第二确定模块确定的存储介质的时延类型为第二时延类型时，继续执行访问操作的进程，其中，第一时延类型的存储介质的访问时延大于第二时延类型的存储介质的访问时延。
结合第二方面，在第二方面的第一种可能的实现中，第二确定模块具体用于：获取存储介质的访问时延；若存储介质的访问时延大于预设值，确定存储介质的时延类型为第一时延类型；若存储介质的访问时延不大于预设值，确定存储介质的时延类型为第二时延类型。
结合第二方面，在第二方面的第二种可能的实现方式中，第二确定模块包括：获取单元，用于获取预设的存储介质与存储介质的时延类型之间的对应关系；确定单元，用于根据获取单元获取的对应关系，确定存储介质的时延类型。
结合第二方面或上述可能的实现方式中的任一种，在第二方面的第三种 可能的实现方式中，该装置还包括：第三确定模块，用于确定访问操作的待访问数据是否存储在缓存中，其中，第二确定模块，具体用于在第三确定模块确定待访问数据未存储在缓存中的情况下，确定访存储介质的时延类型。
结合第二方面或上述可能的实现方式中的任一种，在第二方面的第四种可能的实现方式中，第一时延类型的存储介质包括硬盘驱动器HDD、固态硬盘SSD和非易失性闪存NAND Flash中的至少一种存储介质，第二时延类型的存储介质包括动态随机存储器DRAM和非易失固态存储器NVM中的至少一种存储介质。
第三方面，提供一种存储设备，该存储设备包括控制器以及多种不同类型的存储介质。其中，存储介质，用于存储数据；控制器用于：获取当前访问操作的访问地址；根据访问地址确定访问操作访问的存储介质；确定存储介质的时延类型；在确定存储介质的时延类型为第一时延类型的情况下，中止运行访问操作的进程；在确定存储介质的时延类型为第二时延类型的情况下，继续执行访问操作的进程，其中，第一时延类型的存储介质的访问时延大于第二时延类型的存储介质的访问时延。
结合第三方面，在第三方面的第一种可能的实现中，控制器具体用于：获取存储介质的访问时延；若存储介质的访问时延大于预设值，确定存储介质的时延类型为第一时延类型；若存储介质的访问时延不大于预设值，确定存储介质的时延类型为第二时延类型。
结合第三方面，在第三方面的第二种可能的实现方式中，控制器具体用于：获取预设的存储介质与存储介质的时延类型之间的对应关系；根据对应关系，确定存储介质的时延类型。
结合第三方面或上述可能的实现方式中的任一种，在第三方面的第三种可能的实现方式中，控制器还用于：在确定存储介质的时延类型之前，确定访问操作的待访问数据是否存储在缓存中；在确定待访问数据未存储在缓存中的情况下，确定存储介质的时延类型。
结合第三方面或上述可能的实现方式中的任一种，在第三方面的第四种可能的实现方式中，第一时延类型的存储介质包括硬盘驱动器HDD、固态硬盘SSD和非易失性闪存NAND Flash中的至少一种存储介质，第二时延类型的存储介质包括动态随机存储器DRAM和非易失固态存储器NVM中的至少一种存储介质。
因此，根据本发明实施例的CPU调度的方法，通过获取当前访问操作的访问地址，根据访问地址确定当前访问操作访问的存储介质，进而确定的存储介质的时延类型。当确定存储介质的时延类型为时延较大的类型时，中止执行当前访问操作的进程，实现进程切换。当确定存储介质的为访问较小的类型时，继续等待执行当前访问进程。根据这种方式，可以在一定程度上减少访问操作的等待时间，提高进程处理效率，从而能够减小CPU资源的浪费，降低***的开销。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了根据本发明实施例的应用场景示意图。
图2示出了根据本发明一个实施例的CPU调度的方法的示意性流程图。
图3示出了根据本发明另一实施例的CPU调度的方法的示意性流程图。
图4示出了根据本发明另一实施例的CPU调度的方法的示意性流程图。
图5示出了根据本发明另一实施例的CPU调度的方法的示意性流程图。
图6示出了根据本发明另一实施例的CPU调度的方法的示意***互过程图。
图7示出了根据本发明一个实施例的CPU调度的装置的示意性框图。
图8示出了根据本发明另一实施例的CPU调度的装置的示意性框图。
图9示出了根据本发明一个实施例的存储设备的示意性框图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
图1示出了根据本发明实施例的应用场景示意图。如图1所示，***包括中央处理器(Central Processing Unit，CPU)(100)和存储设备(106)可 以通过内存总线连接。CPU中集成了CPU内核(101)、内存管理单元(Memory Management Unit，MMU)(102)、转换查询缓存(Translation Lookaside Buffer，TLB)(103)、高速缓冲存储器(cache)(104)和消息式内存控制器(Message Memory Controller，MMC)(105)。需要说明的是，图中虽然只示出了1个CPU内核和1个存储设备的情况，但本发明实施例的方法并不局限于此，还可以是多个CPU内核和多个存储设备的情况。图中示出的存储设备包括3种不同类型的存储介质，但本发明实施例的方法并不局限于此，还可以是1种、2种或者多于3种类型的存储介质的情况。应理解，图1所示的存储设备可以是一体化存储设备(Unified Access Storage，UAS)，UAS包含控制器和多种类型的存储介质，UAS包含的多种存储介质可以通过相同的内存访问接口被访问。
如图1所示，CPU内核要将待访问数据写入存储设备或者从存储设备中读取待访问数据的过程可以包括以下步骤：
步骤①，CPU内核发起当前访问操作的访问请求，该访问请求中包括当前访问操作的待访问数据对应的虚拟地址。步骤②，MMU根据虚拟地址查询TLB。步骤③，TLB向MMU反馈与虚拟地址对应的物理地址。步骤④，MMU向CPU内核反馈待访问数据对应的物理地址。步骤⑤，CPU内核根据物理地址访问cache。步骤⑥，当cache中未存储待访问数据时，即：在cache不命中的情况下，CPU内核将物理地址发送给MMC。步骤⑦，MMC根据物理地址在存储设备中对应的存储介质中写入或读取待访问数据。步骤⑧，存储设备向MMC反馈待访问数据已写入或已读取。步骤⑨，MMC将读取的待访问数据替换到cache中。步骤⑩，CPU内核从cache中读取待访问的数据或表示CPU内核接收MMC反馈的待访问数据已写入的消息。
由于当CPU通过统一的路径和指令访问存储介质时，并不能区分要访问的存储介质的类型，所以不能根据存储介质的访问时延特性降低***的开销。
需要说明的是，在步骤⑤中，CPU内核根据该物理地址访问高速缓冲存储器cache，当cache中存储待访问数据时，即：在cache命中的情况下，如果CPU内核要写入物理地址的数据已存储在cache中，CPU内核可以将存储在cache中的数据进行更新，或者CPU内核要读取的与物理地址对应的数据已存储在cache中，CPU内核根据物理地址可以直接从cache中读取该 数据。也就是说，在cache命中的情况下，CPU内核并不需要去访问存储介质，访存请求可以在cache内快速完成，所以不会出现因存储介质的类型不同而造成的访问时延不同的问题。
还需要说明的是，在步骤⑤中，CPU内核根据该物理地址访问高速缓冲存储器cache包括：CPU内核向cache发送物理地址；cache接收CPU内核发送的物理地址，并根据该物理地址，确定cache中是否存储了待访问数据。
为了方便理解本发明实施例，首先在此介绍本发明实施例描述中会引入的几个要素。
进程是指正在运行的程序(指令和数据)的执行过程。
存储介质的访问时延是指CPU对存储介质进行一次读操作所需的时间。
图2示出了根据本发明一个实施例的CPU调度的方法200的示意性流程图。图2的方法200可以应用于一体化存储设备中，其中一体化存储设备包含有多种不同类型的存储介质，该方法200包括：
步骤210，获取当前访问操作的访问地址。
具体地，在本发明实施例中，访问地址可以包括虚拟地址、物理地址或其他访问地址，其中，虚拟地址是虚拟地址空间中的非物理的访问地址，物理地址是物理地址空间中的实际的访问地址，即：指CPU要写入数据的实际的访问地址，或者CPU要读取数据的实际的访问地址。当前访问操作可以包括读操作、写操作或其他操作。
步骤220，根据步骤210中获取的访问地址确定当前访问操作访问的存储介质。
在本发明实施例中，在步骤210中获取的是物理地址时，可以根据物理地址确定与该物理地址对应的存储介质，在步骤210中获取的是虚拟地址时，可以根据虚拟地址确定与该虚拟地址对应的存储介质。
具体地，可以通过查询本地或存储设备中存储的存储介质的访问地址与存储介质的对应关系，确定访问地址对应的存储介质。换句话说，当访问地址在某个存储介质对应的一段地址空间范围之内时，就可以确定该访问地址对应的存储介质为这个存储介质，例如：在步骤210中获取的访问地址为物理地址，且该物理地址在0-4GB的物理地址空间范围之内，而存储介质DRAM的物理地址空间对应于0-4GB的物理地址空间，则可以确定该物理地址对应的存储介质为DRAM。类似地，当步骤210中获取的访问地址为虚 拟地址时，也可以根据这种方法确定该虚拟地址对应的存储介质，为了简便，在此不再赘述。
步骤230，根据步骤220中确定存储介质确定存储介质的时延类型。
在本发明实施例中，可以根据该存储介质与存储介质的时延类型的对应关系确定该存储介质的时延类型。或者，也可以根据访存地址与存储介质的时延类型的对应关系确定该访存地址对应的存储介质的时延类型。
步骤240，在确定存储介质的时延类型为第一时延类型的情况下，中止运行当前访问操作的进程。
在本发明实施例中，中止运行当前访问操作的进程是指可以挂起当前访问操作的进程，使当前访问操作的进程进入休眠状态，从而可以释放当前访问操作的进程占用的CUP资源，便于待运行的其他进程来占用CPU资源，从而实现进程切换。
步骤250，在确定存储介质的时延类型为第二时延类型的情况下，继续执行访问操作的进程，其中，第一时延类型的存储介质的访问时延大于第二时延类型的存储介质的访问时延。
因此，本发明实施例提供的CPU调度的方法，通过获取当前访问操作的访问地址，根据访问地址确定当前访问操作访问的存储介质，进而确定的存储介质的时延类型，当确定存储介质的时延类型为时延较大的类型时，中止执行当前访问操作的进程，实现进程切换。当确定存储介质的时延较小时，继续等待执行当前访问进程。根据这种方式，可以在一定程度上减少访问操作的等待时间，提高进程处理效率，从而能够减小CPU资源的浪费，降低***的开销。
可选地，作为一个实施例，在步骤230中，可以获取存储介质的访问时延；若存储介质的访问时延大于预设值，确定存储介质的时延类型为第一时延类型；若存储介质的访问时延不大于预设值，确定存储介质的时延类型为第二时延类型。
具体地，可以通过比较存储介质的访问时延与预设值的大小关系，根据比较结果确定该存储介质的时延类型为第一时延类型，还是为第二时延类型，这里，第一时延类型的存储介质的访问时延大于第二时延类型的存储介质的访问时延。需要说明的是，这个比较过程可以只进行一次，并将比较结果，即：存储介质与存储介质的时延类型的对应关系存储到本地或存储设备 中，当CPU内核再次发起访存请求时，可以直接到本地或者存储设备中查找存储的对应关系，确定存储介质的时延类型，但本发明实施例并不仅限于此，例如：也可以在CPU内核每次发起访存请求时，执行这个比较过程。还应理解，在本发明实施例中，预设值可以根据CPU内核对存储介质进行一次读操作所需的时间来确定，并可以进行预先的配置。
可替换地，作为另一实施例，在步骤230中，还可以根据存储介质的访问时延与CPU进行进程切换的时间资源开销之间的相对比例关系，确定存储介质的时延类型为第一时延类型，还是为第二时延类型。例如：当存储介质的访问时延超过CPU进行进程切换的时间资源开销的4倍，则确定存储介质的时延类型为第一时延类型，否则，确定存储介质的时延类型为第二时延类型。需要说明的是，存储介质的访问时延与CPU进行进程切换的时间资源开销之间的相对比例关系并不仅限于4倍，还可以增大或减小，这里仅是以举例的方式对本发明实施例的技术方法进行说明，并不对本发明实施例构成任何限定。
还应理解，在本发明实施例中，根据存储介质的访问时延与CPU进行进程切换的时间资源开销之间的相对比例关系，确定存储介质的时延类型为第一时延类型还是为第二时延类型的过程也可以只进行一次，将确定的结果，即：存储介质与存储介质的时延类型的对应关系存储到本地或存储设备中，当CPU内核再次发起访存请求时，可以直接到本地或者存储设备中查找存储的对应关系，确定存储介质的时延类型，但本发明实施例并不仅限于此。
根据本发明实施例，当存储介质的访问时延大于预设值时，可以确定该存储介质的时延类型为第一时延类型；当存储介质的访问时延不大于预设值时，可以确定该存储介质的时延类型为第二时延类型。
应理解，在本发明实施例中，第一时延类型的存储介质可以包括硬盘驱动器(Hard Disk Drive，HDD)、固态硬盘(Solid State Disk，SSD)和非易失性闪存(NAND Flash)中的至少一种存储介质，第二时延类型的存储介质可以包括动态随机存储器(Dynamic Random Access Memory，DRAM)和非易失固态存储器(Non-violate Memory，NVM)中的至少一种存储介质。
需要说明的是，非易失固体存储器NVM可以包括相变内存器(Phase Change Memory，PCM)、磁性存储器(Magnetic Random Access Memory， MRAM)和忆阻存储器(Resistive Random Access Memory，RRAM)中的至少一种存储器，或者，NVM也可以包括其他新型的存储器，本发明实施例并不仅限于此。
可选地，作为另一实施例，在步骤230中，可以获取预设的存储介质与该存储介质的时延类型之间的对应关系，再根据获取的对应关系，确定该存储介质的时延类型为第一时延类型或第二时延类型，其中，第一时延类型的存储介质的访问时延大于第二时延类型的存储介质的访问时延。应理解，预设的的存储介质与该存储介质的时延类型之间的对应关系可以是预先存储在本地或存储设备中的存储介质与该存储介质的时延类型之间的对应关系。
可选地，作为另一实施例，如图3所示，在步骤230之前，所述方法200还包括：
步骤260，确定当前访问操作的待访问数据是否存储在缓存中，
其中，步骤230，在步骤260中确定该待访问数据未存储在缓存中的情况下，确定该存储介质的时延类型。
具体地，在本发明实施例中，缓存可以包括CPU内的各级高速缓存cache、消息式内存控制器MMC内的缓存或软件管理器内的缓存中的任一级缓存，并且当存储设备为一体换存储设备UAS时，还包括UAS的控制器内的缓存。例如：在步骤260中，可以根据访存地址依次确定待访问数据是否存储在CPU内的各级cache、MMC内的缓存和UAS的控制器内的缓存中的任一级缓存中，当步骤260中确定待访问数据未存储在这些缓存中的任一级缓存中时，在步骤230中确定存储介质的时延类型。
需要说明的是，在本发明实施例中，在确定待访问数据已存储在缓存中时，可以根据现有技术来实现，即：直接从该缓存中读取待访问数据或者将待访问数据更新到该缓存。
需要说明的是，在本发明实施例中，在确定待访问数据已存储在缓存中时，可以根据现有技术来实现，即：直接从该缓存中读取待访问数据或者将待访问数据更新到该缓存。
下面，结合具体的实施例，对本发明实施例的方法进行详细的描述。
图4示出了根据本发明另一实施例的CPU调度的方法300的示意性流程图。图4所示的方法300以访问地址为物理地址为例对本发明实施例的方案进行详细的说明，如图4所示，
步骤310，获取当前访问操作的访问地址，该访问地址为物理地址。
步骤320，根据步骤310中获取的物理地址，确定该物理地址对应的存储介质。
步骤330，根据步骤320中确定的存储介质，确定该存储介质的时延类型。
具体地，可以通过比较存储介质的访问时延与预设值的大小关系，根据比较结果确定该存储介质的时延类型，例如：当存储介质的访问时延大于预设值时，可以确定该存储介质的时延类型为第一时延类型；当存储介质的访问时延不大于预设值时，可以确定该存储介质的时延类型为第二时延类型。
应理解，在本发明实施例中，预设值可以根据内核对存储介质进行一次读操作所需的时间来确定，例如：第一预设值可以设置成100μs-1ms，例如：第一预设值可以设置成500μs，CPU对HDD进行一次读操作的时间为4ms，大于第一预设值500μs，所以HDD的时延类型为第一时延类型，即：HDD为第一时延类型的存储介质。再如：第二预设值可以设置成600ns-1μs，例如：第二预设值可以设置成800ns，CPU对DRAM进行一次读操作的时间为600ns，小于第二预设值800ns，所以DRAM的时延类型为第二时延类型，即：DRAM为第二时延类型的存储介质。
应理解，第一预设值与第二预设值可以设置成相同的数值，例如：可以设置成1μs-100μs，例如：可以设置成60μs，CPU对NVM进行一次读操作的时间为300ns，小于预设值60μs，所以NVM的时延类型为第二时延类型，即：NVM为第二时延类型的存储介质；CPU对SSD进行一次读操作的时间为70μs，大于预设值60μs，所以SSD的时延类型为第一时延类型，即：SSD为第一时延类型的存储介质。
应理解，也可以获取本地或存储设备中存储的存储介质与该存储介质的时延类型之间的对应关系，确定该存储介质的时延类型。例如：可以通过查询本地或存储设备中存储的存储介质与该存储介质的时延类型之间的对应关系的对应关系表或文档，获取存储介质与该存储介质的时延类型之间的对应关系，进而确定该存储介质的时延类型。或者，还可以通过查询本地或存储设备中存储的存储介质的物理地址与该存储介质的时延类型之间的对应关系的对应关系表或文档，获取存储介质与该存储介质的时延类型之间的对应关系，进而确定该存储介质的时延类型。
应理解，在本发明实施例中，对应关系表可以包括：存储介质和存储介质的时延类型。例如：对应关系表可以如表1所示,
表1
存储介质 DRAM HDD SSD NVM
时延类型 0 1 1 0
其中，“0”可以表示第二时延类型，“1”可以表示第一时延类型。例如：当物理地址对应的存储介质为HDD时，该HDD的时延类型为第一时延类型。当物理地址对应的存储介质为NVM时，该NVM的时延类型为第二时延类型。
应理解，表1所示的情况只是本发明实施例的一个例子，并不对本发明实施例构成限定，也可以有其他的表示方式，例如：可以用“Y”表示第二时延类型存储介质，“X”表示第一时延类型存储介质，或者，直接表示为“第二时延类型”和“第一时延类型”等等。
需要说明的是，在本发明实施例中，可以在获取存储介质与该存储介质的时延类型之间的对应关系前，获取存储介质与存储介质的物理地址空间范围的对应关系，例如：可以是如表2所示的对应关系表。
表2
起始物理地址 0 4GB 20GB 532GB
结束物理地址 4GB 20GB 532GB 2580GB
存储介质 DRAM NVM SSD HDD
例如：存储介质DRAM对应的物理地址空间为0-4GB的范围，应理解，DRAM的地址空间可能是连续的，也可能是离散的，本发明实施例对应并不做限定。当物理地址在物理地址空间为0-4GB的范围内时，该物理地址对应的存储介质为DRAM，再根据表1的对应关系，确定DRAM的时延类型为第二时延类型。
还应理解，在本发明实施例中，对应关系表还可以包括：存储介质的起始物理地址、结束物理地址，例如：包括多种不同时延的存储介质的存储设备的物理空间为64M，对应关系表可以如表3所示,
表3
起始物理地址 0 4GB 20GB 532GB
结束物理地址 4GB 20GB 532GB 2580GB
存储介质 DRAM NVM SSD HDD
时延类型 0 0 1 1
例如：当物理地址在物理地址空间为0-4GB的范围内时，该物理地址对应的存储介质为DRAM，而该DRAM的时延类型为第二时延类型。或者，当物理地址在物理地址空间为0-4GB的范围内时，该物理地址对应的存储介质的时延类型为第二时延类型。因此，可以直接根据物理地址与存储介质的时延类型的对应关系，确定物理地址对应的存储介质的时延类型。
应理解，表2和表3所示的存储介质的物理地址的划分可以根据实际情况而定，这里仅是为了说明本发明实施例的技术方案，并不对本发明实施例构成限定，但需要指出的是：存储介质DRAM、HDD、SSD、NVM等对应的物理地址空间是不重叠的物理地址空间。
还应理解，在本发明实施例中，仅以物理地址为例进行了详细说明，但本发明实施例并不仅限于此，类似地，对应关系表也可以包括：虚拟地址、存储介质和时延类型，其中，虚拟地址可以包括存储介质的起始虚拟地址、结束虚拟地址。为了简洁，在此不再赘述。
当在步骤330中确定存储介质的时延类型为第一时延类型，且当前访问操作为读操作时，执行以下步骤：
步骤341a，挂起当前访问操作的进程，并从该存储介质中读取当前访问操作的待访问数据。
具体地，在本发明实施例中，MMC可以向CPU内核发送中断请求，该中断请求触发CPU内核挂起当前正在运行的进程，即：CPU内核可以释放当前运行的进程所占用的CPU资源，以便其他待运行的进程占用该CPU资源。
步骤342a，当待访问数据的读取完成时，恢复运行之前挂起的进程。
具体地，在本发明实施例中，对待访问数据进行读操作，则要将从物理地址对应的存储介质中读取的待访问数据反馈并存储到cache中，才意味着待访问数据的读取完成，此时，MMC可以向CPU内核发送恢复请求，该恢复请求触发CPU内核恢复运行之前挂起的进程。
应理解，恢复运行之前挂起的进程，可以是将该进程重新调入就绪队列中进行排队，或者，可以直接以插队的方式，优先运行该进程。
当在步骤330中确定存储介质的时延类型为第二时延类型，且当前访问 操作为读操作时，执行以下步骤：
步骤341b，从该存储介质中读取待访问数据。
步骤342b，当待访问数据的读取完成时，继续运行当前访问操作的进程。
具体地，在本发明实施例中，由于物理地址对应的存储介质的访问时延短，无需向CPU内核发送中断请求，只需在待访问数据的读取完成时，向CPU内核发送第三请求消息，例如：可以向CPU内核发送触发请求，该触发请求触发CPU内核运行当前等待的进程。需要说明的是：当前等待的进程是指占用着CPU内核资源，但是没有运行的进程。而当CPU内核收到触发消息时，例如：收到第三请求消息时，就会运行该进程。
因此，本发明实施例提供的CPU调度的方法，通过获取当前访问操作的访问地址，根据访问地址确定当前访问操作访问的存储介质，进而确定的存储介质的时延类型，当确定存储介质的时延类型为时延较大的类型时，中止执行当前访问操作的进程，实现进程切换，当确定存储介质的为时延较小的类型时，继续等待执行当前访问进程，根据这种方式，可以在一定程度上减少访问操作的等待时间，提高进程处理效率，从而能够减小CPU资源的浪费，降低***的开销。
应理解，在本发明实施例中，当前访问操作为写操作时，可以根据现有技术来实现，即：可以不判断访存地址对应的存储介质的时延类型，将待访问数据写入存储介质。也可以根据本发明实施例中的流程来实现，即：在步骤320中确定存储介质的时延类型为第一时延类型，且对待访问数据进行写操作时，可以调度CPU内核挂起当前运行的进程，并将待访问数据写入该存储介质中；当待访问数据的写入完成时，调度CPU内核恢复运行之前挂起的进程，本发明实施例并不仅限于此。
还应理解，在本发明实施例中，仅是以物理地址空间为例对本发明实施例的技术方案进行了详细的说明，不应对本发明实施例的技术方案构成任何限定，类似地，也可以是虚拟地址空间，为了简洁，在此不再赘述。
还应理解，本发明实施例中的技术方案还可以支持超线程技术，基于这种技术能够利用特殊的硬件支持，把两个逻辑内核模拟成两个物理核，让单个处理器都能使用线程级并行计算的特点，对于第二时延类型的存储介质，可以直接在CPU的多套寄存器之间进行线程或进程的快速切换，无需从第 二时延类型的存储介质中加载线程或进程的上下文，且这种切换的开销相对于访问第二时延类型的存储介质的开销要小得多，所以不用CPU等待；而对于第一时延类型的存储介质，由于其访问时延较长，CPU等待就会导致开销过大，需要从第一时延类型的存储介质中加载线程或进程的上下文，这就需要CPU执行进程切换，从而降低开销。
图5示出了根据本发明另一实施例的CPU调度的方法500的示意性流程图。如图5所示，
步骤510，获取当前访问操作的访问地址。
步骤520，根据步骤510中获取的访问地址，确定当前访问操作的待访问数据是否存储在缓存中。
具体地，在本发明实施例中，缓存可以为如图1中CPU100内的各级高速缓存cache。
步骤530a，当在步骤520中确定待访问数据未存储在缓存中时，根据步骤510中获取的访问地址，确定该访问地址对应的存储介质。
步骤540a，根据步骤530a中确定的存储介质，确定该存储介质的时延类型。
当在步骤540a中确定存储介质的时延类型为第一时延类型时，且当前访问操作为读操作时，执行以下步骤：
步骤541a，挂起当前运行的进程，并从该存储介质中读取待访问数据。
步骤542a，当待访问数据的读取完成时，调度CPU内核恢复运行之前挂起的进程。
当在步骤540a中确定存储介质的时延类型为第二时延类型时或当在步骤520中确定待访问数据已存储在缓存中时，执行以下步骤：
步骤541b，控制从该存储介质中读取待访问数据。
步骤542b，当待访问数据的读取完成时，调度CPU内核运行当前等待的进程。
因此，本发明实施例提供的CPU调度的方法，通过获取当前访问操作的访问地址，根据访问地址确定访问操作的待访问数据未存储在缓存中时，确定访问地址对应的存储介质，进而确定的存储介质的时延类型，当确定存储介质的时延类型为时延较大的类型时，中止执行当前访问操作的进程，实现进程切换，当确定存储介质的为时延较小的类型时，继续等待执行当前访 问进程，根据这种方式，可以在一定程度上减少访问操作的等待时间，提高进程处理效率，从而能够进一步减小CPU资源的浪费，降低***的开销。
应理解，在本发明实施例中，除步骤520之外的其他步骤的具体实现方法分别与图4中的各个步骤的具体实现方法类似，为了简洁，在此不再赘述。
图6示出了根据本发明另一实施例的CPU调度的方法600的示意***互过程图。图6的方法可以由CPU执行，其中，可以由CPU内的消息式内存控制器MMC来确定物理地址对应的存储介质的时延类型。图6所示的方法600为图2、图4或图5的一个例子，如图6所示，
步骤610，CPU内核向MMC发送当前访问操作的物理地址。
步骤620，MMC接收CPU内核发送的物理地址。
步骤630，确定当前访问操作的待访问数据未存储在MMC内的缓存中。
步骤640，MMC通过查询本地存储的存储介质与存储介质类型的对应关系，确定物理地址对应的存储介质的时延类型为第一时延类型。
具体地，MMC也可以通过比较物理地址对应的存储介质的访问时延与预设值的大小关系，确定物理地址对应的存储介质的时延类型为第一时延类型。第一时延类型的存储介质可以是HDD、SSD或NAND Flash。
步骤650，MMC向CPU内核发送中断请求，该中断请求用于指示CPU内核挂起当前正在运行的进程。
步骤660，CPU内核接收MMC发送的中断请求，并根据该中断请求的指示挂起当前正在运行的进程。
步骤670，MMC将从物理地址对应的存储介质中读取待访问数据。
步骤660，MMC向CPU内核发送恢复请求，该恢复请求用于指示CPU内核恢复之前挂起的进程。
具体地，当前访问操作为读操作时，MMC需要将从物理地址对应的存储介质中读取的待访问数据存储到cache中，才可以执行步骤660。
步骤690、CPU内核接收MMC发送的恢复请求，并根据该恢复请求的指示恢复运行之前挂起的进程。
因此，本发明实施例提供的CPU调度的方法，通过获取当前访问操作的物理地址，根据物理地址确定访问操作的待访问数据未存储在缓存中时，确定物理地址对应的存储介质，进而确定的存储介质的时延类型，当确定存储介质的时延类型为时延较大的类型时，中止执行当前访问操作的进程，实 现进程切换，从而能够进一步减小CPU资源的浪费，降低***的开销。
应理解，在本发明实施例中，步骤640可以包括：MMC通过接收UAS的控制器反馈的物理地址对应的存储介质的时延类型为第一时延类型的指示消息，确定存储介质的时延类型为第一时延类型。
需要说明的是，在本发明实施例中，还可以包括以下几种情况：
1、若步骤630中确定待访问数据已存储在MMC内的缓存中时，直接从该缓存中读取待访问数据，并将其存储到cache中，不再执行步骤640及其之后的步骤。
2、若步骤640中MMC通过查询本地存储的存储介质与存储介质类型的对应关系，确定物理地址对应的存储介质的时延类型为第二时延类型，则执行MMC向CPU内核发送触发请求，该请求用于指示CPU内核恢复运行当前等待的进程，以及CPU内核接收MMC发送的触发请求，并根据该触发请求的指示恢复运行当前等待的进程，即：继续执行当前访问操作的进程。
3、存储设备为UAS，且UAS的控制器内有缓存。则在步骤640之后步骤650之前还要执行以下步骤：
步骤641(图中未示出)、MMC向UAS的控制器发送物理地址。
步骤642(图中未示出)、UAS的控制器根据物理地址，确定待访问数据是否存储在UAS的控制器内的缓存中。
步骤643a、(图中未示出)、在UAS的控制器确定待访问数据未存储在UAS的控制器内的缓存中时，执行步骤650及其之后的步骤；
步骤643b(图中未示出)、在MMC确定待访问数据已存储在UAS的控制器内的缓存中时，直接从该缓存中读取待访问数据，并将其存储到cache中，不再执行步骤650及其之后的步骤。
上文中结合图2至图6，详细描述了根据本发明实施例的CPU调度的方法，下面将结合图7和图8，详细描述根据本发明实施例的CPU调度的装置。
图7示出了根据本发明实施例的CPU调度的装置700的示意性框图。如图7所示，该装置700应用于一体化存储设备中，其中一体化存储设备包含有多种不同类型的存储介质，该装置700包括获取模块710、第一确定模块720、第二确定模块730和执行模块740，其中：
获取模块710，用于获取当前访问操作的访存地址。
第一确定模块720，用于确定获取模块710获取的访问地址确定访问操 作访问的存储介质。
第二确定模块730，用于确定第一确定模块720确定的存储介质的时延类型。
执行模块740，用于在第二确定模块730确定的存储介质的时延类型为第一时延类型时，中止运行访问操作的进程；在第二确定模块730确定的存储介质的时延类型为第二时延类型时，继续执行访问操作的进程，其中，第一时延类型的存储介质的访问时延大于第二时延类型的存储介质的访问时延。
因此，本发明实施例提供的调度CPU内核的装置，通过获取当前访问操作的访问地址，根据访问地址确定当前访问操作访问的存储介质，进而确定的存储介质的时延类型，当确定存储介质的时延类型为时延较大的类型时，中止执行当前访问操作的进程，实现进程切换，当确定存储介质的为时延较小的类型时，继续等待执行当前访问进程，根据这种方式，可以在一定程度上减少访问操作的等待时间，提高进程处理效率，从而能够减小CPU资源的浪费，降低***的开销。
可选地，在一种情形下，第二确定模块730具体用于获取存储介质的访问时延；若存储介质的访问时延大于预设值时，确定该存储介质的时延类型为第一时延类型；若存储介质的访问时延不大于预设值时，确定该存储介质的时延类型为所述第二时延类型。
可选地，在另一种情形下，第二确定模块730具体用于获取预设的存储介质与该存储介质的时延类型之间的对应关系，并根据获取单元获取的对应关系，确定存储介质的时延类型。
在本发明实施例中，第一时延类型的存储介质可以包括硬盘驱动器(Hard Disk Drive，HDD)、固态硬盘(Solid State Disk，SSD)和非易失性闪存(NAND Flash)中的至少一种存储介质，第二时延类型的存储介质可以包括动态随机存储器(Dynamic Random Access Memory，DRAM)和非易失固态存储器(Non-violate Memory，NVM)中的至少一种存储介质。
可选地，作为另一实施例，如图8所示，该装置700还包括：
第三确定模块750，用于确定访问操作的待访问数据是否存储在缓存中，
其中，第二确定模块730，具体用于在第三确定模块750确定待访问数据未存储在所述缓存中时，确定存储介质的时延类型。
应理解，在本发明实施例中，根据本发明实施例的CPU调度内的装置700，可对应于根据本发明实施例的方法的执行主体，并且该CPU调度的装置700中的各个模块的上述和其它操作和/或功能分别为了实现图2至图6中的各个方法的相应流程，为了简洁，在此不再赘述。
因此，本发明实施例提供的CPU调度的装置，通过获取当前访问操作的访问地址，根据访问地址确定当前访问操作访问的存储介质，进而确定的存储介质的时延类型，当确定存储介质的时延类型为时延较大的类型时，中止执行当前访问操作的进程，实现进程切换，当确定存储介质的为时延较小的类型时，继续等待执行当前访问进程，根据这种方式，可以在一定程度上减少访问操作的等待时间，提高进程处理效率，从而能够减小CPU资源的浪费，降低***的开销。
图9示出了根据本发明实施例的存储设备900的示意性框图。如图9所示，该存储设备900包括控制器910以及多种不同类型的存储介质920。其中，
存储介质920，用于存储数据。具体地，在本发明实施例中，存储介质920可以为一体化存储设备UAS，UAS包括多种不同类型的存储介质和UAS的控制器，这些存储介质可以通过同一个内存接口被访问。
控制器910用于：获取当前访问操作的访问地址；根据访问地址确定访问操作访问的存储介质；确定存储介质的时延类型；在确定存储介质的时延类型为第一时延类型的情况下，中止运行访问操作的进程；在确定存储介质的时延类型为第二时延类型的情况下，继续执行访问操作的进程，其中，第一时延类型的存储介质的访问时延大于第二时延类型的存储介质的访问时延。
具体地，在本发明实施例中，控制器910可以包括内核core 912、内存管理单元MMU 914、高速缓冲存储器cache 916以及消息式内存控制器MMC918。内核core 912用于获取当前访问操作的访问地址，MMU 914用于将虚拟地址转化为对应的物理地址，MMC918可以用于根据访问地址确定访问操作访问的存储介质，并确定存储介质的时延类型，内核core 912还用于在MMC 918确定存储介质的时延类型为第一时延类型的情况下，中止运行访问操作的进程；在MMC 918确定存储介质的时延类型为第二时延类型的情况下，继续执行访问操作的进程。
因此，根据本发明实施例的存储设备，可以通过获取当前访问操作的访问地址，根据访问地址确定当前访问操作访问的存储介质，进而确定的存储介质的时延类型，当确定存储介质的时延类型为时延较大的类型时，中止执行当前访问操作的进程，实现进程切换，当确定存储介质的为时延较小的类型时，继续等待执行当前访问进程，根据这种方式，可以在一定程度上减少访问操作的等待时间，提高进程处理效率，从而能够减小CPU资源的浪费，降低***的开销。
应理解，在本发明实施例中，MMC 918还可以接收UAS的控制器反馈的存储介质的时延类型，内核core 912用于在MMC 918接收到UAS的控制器反馈的存储介质的时延类型为第一时延类型的情况下，中止运行访问操作的进程；在MMC 918接收到UAS的控制器反馈的存储介质的时延类型为第二时延类型的情况下，继续执行访问操作的进程。
可选地，在一种情形下控制器910具体用于：获取存储介质的访问时延；若存储介质的访问时延大于预设值，确定存储介质的时延类型为第一时延类型；若存储介质的访问时延不大于预设值，确定存储介质的时延类型为第二时延类型。
可选地，在又一种情形下控制器910具体用于：获取预设的存储介质与存储介质的时延类型之间的对应关系；根据对应关系，确定存储介质的时延类型。
可选地，在又一种情形下控制器910还用于：在确定存储介质的时延类型之前，确定当前访问操作的待访问数据是否存储在缓存中；在确定待访问数据未存储在缓存中的情况下，确定存储介质的时延类型。
在本发明实施例中，第一时延类型的存储介质包括硬盘驱动器HDD、固态硬盘SSD和非易失性闪存NAND Flash中的至少一种存储介质，第二时延类型的存储介质包括动态随机存储器DRAM和非易失固态存储器NVM中的至少一种存储介质。
本发明实施例的存储设备通过获取当前访问操作的访问地址，根据访问地址确定当前访问操作访问的存储介质，进而确定的存储介质的时延类型，当确定存储介质的时延类型为时延较大的类型时，中止执行当前访问操作的进程，实现进程切换，当确定存储介质的为时延较小的类型时，继续等待执行当前访问进程，根据这种方式，可以在一定程度上减少访问操作的等待时 间，提高进程处理效率，从而能够减小CPU资源的浪费，降低***的开销。
还应理解，在本发明实施例中，根据本发明实施例的存储设备900的控制器910，可对应于根据本发明实施例的方法的执行主体，并且该存储设备900的控制器910可以实现图2至图6中的各个方法的相应流程，为了简洁，在此不再赘述。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的***、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的***、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个***，或一些特征可以忽略，或不执行。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应所述以权利要求的保护范围为准。

Claims (15)

  1. 一种CPU调度的方法，所述方法应用于一体化存储设备中，其中所述一体化存储设备包含有多种不同类型的存储介质，其特征在于，包括：
    获取当前访问操作的访问地址；
    根据所述访问地址确定所述访问操作访问的存储介质；
    确定所述存储介质的时延类型；
    在确定所述存储介质的时延类型为第一时延类型的情况下，中止运行所述访问操作的进程；
    在确定所述存储介质的时延类型为第二时延类型的情况下，继续执行所述访问操作的进程，
    其中，所述第一时延类型的存储介质的访问时延大于所述第二时延类型的存储介质的访问时延。
  2. 根据权利要求1所述的方法，其特征在于，所述确定所述存储介质的时延类型包括：
    获取所述存储介质的访问时延；
    若所述存储介质的访问时延大于预设值，确定所述存储介质的时延类型为所述第一时延类型；
    若所述存储介质的访问时延不大于所述预设值，确定所述存储介质的时延类型为所述第二时延类型。
  3. 根据权利要求1所述的方法，其特征在于，所述确定所述存储介质的时延类型包括：
    获取预设的所述存储介质与所述存储介质的时延类型之间的对应关系；
    根据所述对应关系，确定所述存储介质的时延类型。
  4. 根据权利要求1至3中任一项所述的方法，其特征在于，在所述确定所述存储介质的时延类型之前，所述方法还包括：
    确定所述访问操作的待访问数据是否存储在缓存中；
    所述确定所述访存地址对应的存储介质的时延类型包括：
    在确定所述待访问数据未存储在所述缓存中的情况下，确定所述存储介质的时延类型。
  5. 根据权利要求1至4中任一项所述的方法，其特征在于，所述第一时延类型的存储介质包括硬盘驱动器HDD、固态硬盘SSD和非易失性闪存 NAND Flash中的至少一种存储介质，所述第二时延类型的存储介质包括动态随机存储器DRAM和非易失固态存储器NVM中的至少一种存储介质。
  6. 一种CPU调度的装置，所述装置应用于一体化存储设备中，其中所述一体化存储设备包含有多种不同类型的存储介质，其特征在于，所述装置包括：
    获取模块，用于获取当前访问操作的访问地址；
    第一确定模块，用于根据所述获取模块获取的所述访问地址确定所述访问操作访问的存储介质；
    第二确定模块，用于确定所述存储介质的时延类型；
    执行模块，用于在所述第二确定模块确定的所述存储介质的时延类型为第一时延类型时，中止运行所述访问操作的进程；在所述第二确定模块确定的所述存储介质的时延类型为第二时延类型时，继续执行所述访问操作的进程，其中，所述第一时延类型的存储介质的访问时延大于所述第二时延类型的存储介质的访问时延。
  7. 根据权利要求6所述的装置，其特征在于，所述第二确定模块具体用于：
    获取所述存储介质的访问时延；
    若所述存储介质的访问时延大于预设值，确定所述存储介质的时延类型为所述第一时延类型；
    若所述存储介质的访问时延不大于所述预设值，确定所述存储介质的时延类型为所述第二时延类型。
  8. 根据权利要求6所述的装置，其特征在于，所述第二确定模块包括：
    获取单元，用于获取预设的所述存储介质与所述存储介质的时延类型之间的对应关系；
    确定单元，用于根据所述获取单元获取的所述对应关系，确定所述存储介质的时延类型。
  9. 根据权利要求6至8中任一项所述的装置，其特征在于，所述装置还包括：
    第三确定模块，用于确定所述访问操作的待访问数据是否存储在缓存中，
    其中，所述第二确定模块，具体用于在所述第三确定模块确定所述待访 问数据未存储在所述缓存中的情况下，确定所述存储介质的时延类型。
  10. 根据权利要求6至9中任一项所述的装置，其特征在于，所述第一时延类型的存储介质包括硬盘驱动器HDD、固态硬盘SSD和非易失性闪存NAND Flash中的至少一种存储介质，所述第二时延类型的存储介质包括动态随机存储器DRAM和非易失固态存储器NVM中的至少一种存储介质。
  11. 一种存储设备，所述存储设备包括控制器以及多种不同类型的存储介质，其特征在于：
    所述存储介质，用于存储数据；
    所述控制器，用于：
    获取当前访问操作的访问地址；
    根据所述访问地址确定所述访问操作访问的存储介质；
    确定所述存储介质的时延类型；
    在确定所述存储介质的时延类型为第一时延类型的情况下，中止运行所述访问操作的进程；
    在确定所述存储介质的时延类型为第二时延类型的情况下，继续执行所述访问操作的进程，
    其中，所述第一时延类型的存储介质的访问时延大于所述第二时延类型的存储介质的访问时延。
  12. 根据权利要求11所述的存储设备，其特征在于，所述控制器具体用于：
    获取所述存储介质的访问时延；
    若所述存储介质的访问时延大于预设值，确定所述存储介质的时延类型为所述第一时延类型；
    若所述存储介质的访问时延不大于所述预设值，确定所述存储介质的时延类型为所述第二时延类型。
  13. 根据权利要求11所述的存储设备，其特征在于，所述控制器具体用于：
    获取预设的所述存储介质与所述存储介质的时延类型之间的对应关系；
    根据所述对应关系，确定所述存储介质的时延类型。
  14. 根据权利要求11至13中任意一项所述的存储设备，其特征在于，所述控制器还用于：
    在所述确定所述存储介质的时延类型之前，确定所述访问操作的待访问数据是否存储在缓存中；
    在确定所述待访问数据未存储在所述缓存中的情况下，确定所述存储介质的时延类型。
  15. 根据权利要求11至14中任意一项所述的存储设备，其特征在于，所述第一时延类型的存储介质包括硬盘驱动器HDD、固态硬盘SSD和非易失性闪存NAND Flash中的至少一种存储介质，所述第二时延类型的存储介质包括动态随机存储器DRAM和非易失固态存储器NVM中的至少一种存储介质。
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