WO2016033614A1 - Dopage laser pour la réalisation de cellules solaires à jonction arrière et contact arrière - Google Patents

Dopage laser pour la réalisation de cellules solaires à jonction arrière et contact arrière Download PDF

Info

Publication number
WO2016033614A1
WO2016033614A1 PCT/US2015/047837 US2015047837W WO2016033614A1 WO 2016033614 A1 WO2016033614 A1 WO 2016033614A1 US 2015047837 W US2015047837 W US 2015047837W WO 2016033614 A1 WO2016033614 A1 WO 2016033614A1
Authority
WO
WIPO (PCT)
Prior art keywords
solar cell
laser
emitter
contact
base
Prior art date
Application number
PCT/US2015/047837
Other languages
English (en)
Inventor
Pawan Kapur
Virendra V. Rana
Anand Deshpande
Mehrdad M. Moslehi
Original Assignee
Solexel, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Solexel, Inc. filed Critical Solexel, Inc.
Publication of WO2016033614A1 publication Critical patent/WO2016033614A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells

Definitions

  • the present disclosure relates in general to the fields of photovoltaic (PV) solar cells, and more particularly to laser doping for making back contact back junction solar cells.
  • PV photovoltaic
  • solar cell contact structure includes conductive metallization on base and emitter diffusion areas - for example aluminum metallization connecting silicon in base and emitter contact areas through relatively heavy phosphorous and boron areas, respectively.
  • FIGs. 1A through IF are cross-sectional diagrams of a solar cell absorber after key processing steps described in Table 2;
  • FIG. 2 is a cross-sectional diagram of an exemplary back contact back junction solar cell
  • Fig. 3 is a graph showing a boron dopant profile in crystalline silicon that was obtained using green nanosecond laser.
  • Fig. 4 is a graph showing a boron dopant profile in crystalline silicon that was obtained using infrared nanosecond laser.
  • the present application provides laser doping based efficient manufacturing solutions for making high efficiency back contact back junction solar cells.
  • Process flows and methods to manufacture back contact back junction solar cells using laser doping on an n-type substrate are described.
  • the laser doping base and emitter region formation solutions provided may significantly reduce the number of solar cell manufacturing process steps without compromising efficiency, thus resulting in low fabrication cost solar cells.
  • the p/n junction (i.e., base and emitter region) manufacturing solutions described provide for the formation self-aligned back contact solar cell structures and may be particularly advantageous for the formation of high efficiency solar cells in combination with thin (e.g., semiconductor absorbers having a thickness in the range of approximately 5 ⁇ to 100 ⁇ ) back contact back junction solar cells supported by a backplane.
  • thin e.g., semiconductor absorbers having a thickness in the range of approximately 5 ⁇ to 100 ⁇
  • the manufacturing methods provided are equally applicable to thick (e.g., semiconductor absorbers having a thickness greater than approximately 100 ⁇ ) solar cells which may or may not have a supporting backplane.
  • Table 1 shows a known self-aligned p/n junction and contact
  • Open base contact (e.g., using pico-second laser or using inkjet/screen masks and etch)
  • Deposit phosphorous doping source e.g., screen print phosphorous paste
  • Laser open emitter e.g., using pico-second laser or using inkjet/screen masks and etch
  • Deposit metal e.g., using screen printed Al paste or PVD variants of aluminum, titanium/aluminum, or nickel/aluminum
  • metal pad for via drill stop Anneal paste (if applicable)
  • the manufacturing process flow of Table 1 relies on opening the contact areas which need to be heavily doped, applying patterned (for example screen printed) dopants, annealing, etching away the dopants and opening contacts, and finally applying base and emitter metallization (e.g., metal deposition followed by metal patterning). In some instances, this manufacturing process may suffer complexities such as, for example, shunting at the edge of the contacts from cross diffusion during anneal. In one
  • additional process steps may be used and these steps, including the base and emitter opening steps, are performed sequentially rather than simultaneously as shown in Table 1 - thus resulting in addition process steps and process step restrictions.
  • the metal may either be, for example, a screen printed based patterned metal (e.g., Al paste) or a PVD based metal (e.g., Al, Al silicon having 1% silicon, Ti/Al, Ni/Al) or other known combinations which yield low contact resistance.
  • PVD metal deposition may be preceded by a presputter etch.
  • Table 2 below shows a laser doping self-aligned p/n junction and contact solar cell manufacturing process flow solution. As may be readily evident, the manufacturing solution cuts down three process steps as compared to the process flow described in Table 1. In the process flow of Table 2, the first steps to make the base doping are consistent with Table 1. However, the emitter contact doping is created in merely one step using laser doping through the boron doped AI2O3 layer. The laser not only drives the dopant atoms from the source (i.e., the AI2O3 layer into the silicon) but it
  • the process relaxation of not having boron doping in the AI2O3 layer also frees up the space for using other techniques to deposit AI2O3 including atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • 3 Open base contact e.g., using pico-second laser or using inkjet/screen masks and etch
  • Figs. 1A through IF are cross-sectional diagrams of a solar cell absorber after key processing steps described in Table 2.
  • AI2O3 4 is deposited on n-type silicon substrate 2.
  • base contact opening 6 is formed through AI2O3 4 to n-type silicon substrate 2.
  • phosphorous dopant 8 is formed in base contact opening 6.
  • step 5 of Table 2 forms p- field emitter 10 (boron diffusion from AI2O3 4 to n-type silicon substrate 2 to form p- field emitter 10), n+ base region 12
  • dielectric 14 comprising AI2O3 4 and a smaller portion of silicon oxide after anneal.
  • step 6 of Table 2 laser beam 18 is applied to dielectric 14 to form p+ emitter region 16 (boron diffusion from AI2O3 4 to n-type silicon substrate 2 to form p+ emitter region 16).
  • step 7 of Table 2 phosphorous dopant 8 is removed resulting in a back contact back junction solar cell absorber.
  • the process sequence for the dopant removal may be changed.
  • the dopant source etch process is performed after the laser doping through AI2O3 to form the selective emitter.
  • the primary purpose of this etch is to remove the phosphorous dopant source
  • etching after the laser doping step may also help remove any thin residual layers of oxide not removed during laser doping.
  • the dopant source for phosphorous may be a spin on dopant (SOD) material or an inkjet based patterned dopant phosphorous source or an APCVD based PSG source, instead of screen printed phosphorous paste as shown in Table 2.
  • SOD spin on dopant
  • APCVD APCVD based PSG source
  • Fig. 2 shows an example boron dopant profile in crystalline silicon that was obtained using green nanosecond laser.
  • the dopant source was APCVD deposited Boron doped AI2O3.
  • the pulse width of the laser was greater than 25 nanoseconds.
  • Fig. 3 shows a boron dopant profile in crystalline silicon that was obtained using infrared wavelength laser (as compared to green wavelength laser as shown in Fig. 2).
  • Table 3 below shows an alternative process flow based on laser doping and may be equally efficient as the flow described in Table 2.
  • both emitter and base contacts are opened together either with a pico second laser or using inkjet/screen-printed mask and etch. Subsequent to the openings, the large area emitter is formed by diffusing the boron in AI2O3 into the silicon using a high temperature anneal. Because the anneal is now completed, the doping in the contacts is performed using laser doping.
  • both boron and phosphorous sources are printed (e.g., using screen print or using inkjet or other sources) followed by lasering these areas with the appropriate laser to drive the dopant source boron and phosphorous from the source into the silicon. Subsequently, the dopant sources are etched together in one step and metallization may then be performed consistent as shown in Table 2.
  • Anneal to make the emitter e.g., at temps, in the range of approximately 850°C to 1100°C in a furnace.
  • Deposit metal e.g., using screen printed Al paste or PVD variants of Al, Ti/Al, or
  • Ni/Al Ni/Al
  • metal pad for via drill stop
  • a variant of the process sequence described in Table 3 uses non pre- patterned dopant sources such as spin on dopants which are spun using a spin coater on full and are hit by the laser in areas where the dopant diffusion is desired (i.e., on top of already pre -opened contacts). These dopants may have an advantage of being low cost as they are much thinner than screen printed pastes.
  • the process flow may be modified such as that shown in Table 4 below.
  • Anneal to make the emitter e.g., at temps, in the range of approximately 850°C to 1100°C in a furnace.
  • Deposit metal e.g., using screen printed Al paste or PVD variants of Al, Ti/Al, or
  • Ni/Al Ni/Al
  • metal pad for via drill stop
  • the selective emitter doping through AI2O3 (described in Table 2) may be combined with the laser doping on the base side using a phosphorous source - an example process flow of which is shown in Table 5.
  • Table 5 The process flow described in Table 5 should not be taken in a limited sense and it should be noted that several other process flows based on the flow of Table 5 may be generated by shuffling the sequences of anneal and laser doping and open steps.
  • Anneal to make the emitter e.g., at temps, in the range of approximately 850°C to 1100°C in a furnace.
  • Deposit metal e.g., using screen printed Al paste or PVD variants of Al, Ti/Al, or
  • Ni/Al Ni/Al
  • metal pad for via drill stop
  • the metal is may be a PVD metal such as aluminum, or in some instances a screen printed metal such as aluminum.
  • Variant 1 of this class is shown in Table 6 and requires Al metal to be fired by the laser through the underling AI2O3 dielectric and make contact to the underlying silicon.
  • Variant 2 shown in Table 7 has an extra step of contact open at the emitter so metal is directly and already in contact with silicon. When laser hits the metal in these areas, it directly drives Al into the silicon without having to go through the underlying dielectric (as described in Table 8).
  • Open base contact (e.g., using pico-second laser or using inkjet/screen masks and etch)
  • Deposit phosphorous doping source e.g., screen print phosphorous paste
  • Deposit metal e.g., using screen printed Al paste or PVD variants of Al, Ti/Al, or
  • Ni/Al Ni/Al
  • metal pad for via drill stop
  • Open base contact e.g., using pico-second laser or using inkjet/screen masks and etch
  • Deposit phosphorous doping source e.g., screen print phosphorous paste
  • Deposit metal e.g., using screen printed Al paste or PVD variants of Al, Ti/Al, or Ni/Al
  • metal pad for via drill stop
  • the laser doping solutions provided herein may be advantageously integrated with known back contact back junction solar cell fabrication methods and structures. Thin back contact back junction solar cells may particularly benefit from the self-aligned laser doping solutions provided. Structures and methods relating to backplane supported back contact back junction solar cells having dual-level metallization may be found in U.S. Pat. Pub. 2013/0000715 published Jan. 3, 2013, U.S. Pat. Pub. 2013/0228221 published Sept. 5, 2013, and U.S. Pat. Pub. 2013/0213469 published Aug. 22, 2013, all of which are hereby incorporated by reference in their entirety.
  • a back contact back junction solar cell resulting from the laser doping back contact back junction solar cell fabrication methods provided, such as that shown in Fig. IF, may be integrated with back contact back junction solar cell fabrication methods resulting in a back contact back junction solar cell with metallization structure having a first level metal (Metal 1 or Ml) in conjunction with an electrically insulating backplane layer, providing base and emitter metallization and a second level metal (Metal 2 or M2) patterned orthogonally to fine -pitched interdigitated Ml and providing cell level connection.
  • Fig. 4 is cross-sectional diagram of solar cell with a self aligned contact structure consistent with Fig. IF and having multi-level metallization. Specifically, Fig.
  • FIG. 4 shows first level (Ml) base metallization 20 contacting n+ base region 12 and first level (Ml) emitter metallization 24 contacting p+ emitter region 16.
  • Second level (M2) base metallization 26 contacts first level (Ml) base metallization 20 through backplane 22.
  • the front/sunny side of the solar cell is textured, passivated, and anti-reflection coated (shown as texture/passivation/ ARC 28 in Fig. 4). As shown, Fig.
  • FIG. 4 is a cross-sectional diagram showing a first level metallization Ml to second level metallization M2 base connection through a backplane via where the interdigitated fingers of second level metallization M2 are patterned orthogonally to the interdigitated fingers of first level metallization M 1.
  • trench-partitioned isled solar cells are provided. Structures and methods for forming isled solar cells having integrated backplane supported dual level metallization structure referred to as an iCell may be found in related U.S. Patent Pub. 2014/0370650 published Dec. 18, 2014, which is hereby incorporated by reference in its entirety.
  • Tables 8 and 9 below show two cell fabrication process flows beginning after first level metallization (Ml) formation (e.g., first level metallization described in step 8 of Table 2) and resulting in the solar cell structure of Fig. 4.
  • Ml first level metallization
  • the backend fabrication process requires that the wafer is laminated to a specially designed backplane material (e.g., prepreg). Subsequent to this lamination, the backplane material (e.g., prepreg), which is stable under different chemistries, is used to support the silicon substrate during silicon etch back and thin down silicon (this renders a lower lifetime wafer to become higher efficiency).
  • a specially designed backplane material e.g., prepreg
  • An advantage of silicon etch back after the icell cut is that any laser damage during the cut is removed during the etch back process.
  • a second advantage is that because the laser icell cut now is partial (rest of the opening is done by the wet chemistry), the laser does not need to have selectivity to the backplane (e.g., prepreg) and thus wavelengths other than infra-red may be used (infrared laser has selectivity to the prepreg).
  • An additional advantage of the sequence of Table 9 is that since laser does not touch the backplane (e.g., prepreg) any splattering of the backplane (e.g., prepreg) and the ensuing particles are eliminated.
  • the patterned metal may followed by pads of screen printed paste on top of the patterned metal in specific locations.
  • the purpose of these pads is to serve as via drill stop for laser which is used to drill holes through the backplane (e.g., prepreg) to connect metal 1 and metal 2 later.
  • These pads may be made of materials such as aluminum paste or silver paste. If the metallization and contact schemed is based on screen printing, the pads would not constitute as an extra tool as the pads may be formed as the second step in the metallization screen print. However, for PVD based
  • a screen print step will be required if the pads are needed. If drill stop pads are not utilized, then the underlying PVD or the paste must be capable of serving as the via drill stop.
  • the solar cell structures described herein may utilize a multi-layer metallization structure, such as a two-level metallization structure, comprising an on-cell base and emitter metallization first level metal (Ml) and a second level metal (M2) collecting power (voltage and current) from the first level metal (hence, completing the solar cell metallization) and which may also form cell to cell
  • a multi-layer metallization structure such as a two-level metallization structure, comprising an on-cell base and emitter metallization first level metal (Ml) and a second level metal (M2) collecting power (voltage and current) from the first level metal (hence, completing the solar cell metallization) and which may also form cell to cell
  • the second level metal may comprise an interdigitated pattern of base and emitter current collection fingers and optionally solar cell base and emitter busbars (for example, M2 base and emitter fingers extending from base and emitter busbars, respectively).
  • the first level metal (Ml) may comprise an interdigitated back contact metallization structure with relatively fine pitch interdigitated fingers (much finer pitch than the second level metal pitch) arranged orthogonal/perpendicular or in some instances parallel to the interdigitated fingers of M2.
  • a relatively thin electrically insulating backplane formed between Ml and M2 and attached to the solar cell provides solar cell structural support, Ml electrical insulation, and allows for solar cell fabrication (particularly M2 fabrication and solar cell frontside processing) processing improvement.
  • the backplane sheet may be a continuous flexible material closely CTE-matched with the solar cell semiconductor substrate material (e.g., crystalline silicon for silicon solar cells), laminated or otherwise attached to, for example, the back-contact / back-junction solar cell prior to completion of the remaining solar cell manufacturing process steps.
  • the solar cell semiconductor substrate material e.g., crystalline silicon for silicon solar cells
  • Ml may comprise interdigitated base and emitter lines (for instance, with base-emitter finger pitch of less than 2mm and in some instances less than 1mm) and M2 (in some instances with interdigitated fingers substantially orthogonal/perpendicular to Ml fingers and with a much coarser base-emitter pitch compared to Ml) serves as the electrical connector among Ml base and emitter lines (i.e., a busbarless Ml pattern while the optional cell busbars may be placed on the M2 pattern).
  • Ml may comprise interdigitated base and emitter lines (for instance, with base-emitter finger pitch of less than 2mm and in some instances less than 1mm)
  • M2 in some instances with interdigitated fingers substantially orthogonal/perpendicular to Ml fingers and with a much coarser base-emitter pitch compared to Ml) serves as the electrical connector among Ml base and emitter lines (i.e., a busbarless Ml pattern while the optional cell busbars may be placed on the M2 pattern).
  • the metal layers in the disclosed multi-level metal designs are separated by a dielectric or an electrically insulating layer, such as a resin/fiber based prepreg material or alternatively a suitable plastic or polymer based material, forming a continuous backplane for each of the plurality of solar cells in the solar cell array placed on the continuous backplane.
  • a dielectric or an electrically insulating layer such as a resin/fiber based prepreg material or alternatively a suitable plastic or polymer based material
  • the backplane should preferably be relatively closely CTE (Coefficient of Thermal Expansion) matched to the CTE of the semiconductor absorber (e.g., crystalline silicon) so as to minimize CTE mismatch stress or warpage effects during thermal processing - for example a specially formulated aramid fiber resin prepreg material may provide close CTE matching with silicon while providing flexibility, electrical insulating, thermal and chemical stability, and other desirable processing and reliability characteristics such as effective crack- free lamination.
  • M1/M2 interconnection structures include conductive material filled vias through the insulating layer (e.g., an insulating dielectric layer such as prepreg
  • backplane positioned between Ml and M2 - laminated or attached to the backsides of the solar cells after formation of the patterned M2 layer.
  • the solar cells provided may utilize a two-level metallization scheme comprising a preferably busbarless (although optional busbars may be used) first-level contact metallization (Ml) using a relatively thin patterned metal (e.g., thin aluminum formed by screen printing of an aluminum paste or inkjet printing of an aluminum ink, or alternatively plasma sputtering from an aluminum target followed by laser ablation or wet etch patterning) formed directly on the solar cell backside prior to backplane lamination, and a second level thin patterned metal M2 (e.g., comprising approximately 3 to 5 microns thick Al or alternatively, about one to several microns of copper, which may in either case be optionally capped with a solderable coating such as tin) formed after backplane lamination.
  • a relatively thin patterned metal e.g., thin aluminum formed by screen printing of an aluminum paste or inkjet printing of an aluminum ink, or alternatively plasma sputtering from an aluminum target followed by laser ablation or wet etch
  • the patterned M2 layer may also be formed by using plating or lamination and patterning of a high-conductivity metal foil (comprising copper or aluminum).
  • the Ml and M2 layers are separated by the backplane and interconnected at designated regions through conductive via plugs (conductive via plugs may be formed during M2 formation).
  • Ml has fine-pitch pattern and M2 preferably is orthogonal (or substantially perpendicular) to Ml and has coarse pitch pattern (hence, fewer base and emitter fingers compared to Ml).
  • Patterned M2 completes the cell-level electrical metallization and may also provide cell to cell electrical interconnections for a plurality of solar cells laminated to a continuous backplane - thus in some instances eliminating the need for separate cell to cell tabbing/bussing/soldering. Further, M2 may form array/module level bussing or interconnections when desired for array/module electrical interconnection design.
  • voltage and current scaling may relax and reduce M2 conductivity requirements and constraints. For example, in consideration with other factors, utilizing a thinner M2 metal (e.g., about 2 to 5 microns thick evaporated aluminum by PVD or about 1 to few microns of copper formed by plasma sputtering or evaporation) as compared to thicker M2 metallization (e.g., about 50 to 80 microns thick electroplated copper).
  • M2 metal e.g., about 2 to 5 microns thick evaporated aluminum by PVD or about 1 to few microns of copper formed by plasma sputtering or evaporation
  • thicker M2 metallization e.g., about 50 to 80 microns thick electroplated copper.
  • the thickness of Ml and M2 metallization layers may also be adjusted based on the number, dimensions, and shape of the interdigitated fingers on the Ml layer and M2 layer.
  • Ml is patterned with finer interdigitated fingers as compared to the interdigitated fingers of M2.
  • Structures and methods for forming isled solar cells having integrated backplane supported dual level metallization structure referred to as an iCell may be found in related U.S. Patent Pub. 2014/0370650 published Dec. 18, 2014, referenced previously.
  • Physically or regionally isolated isles i.e., the initial semiconductor substrate partitioned into a plurality of substrate isles supported on a shared continuous backplane
  • the resulting isles for instance, trench isolated from one another using trench isolation regions or cuts through the semiconductor substrate, for example using laser or mechanical scribing
  • a continuous backplane for example a flexible backplane such as an electrically insulating prepreg layer
  • the completed solar cell (referred to as a master cell or iCell) comprises a plurality of monolithically integrated isles/sub-cells/mini-cells, in some instances attached to a flexible backplane (e.g., one made of a prepreg materials, for example having a relatively good Coefficient of Thermal Expansion or CTE match to that of the semiconductor substrate material such as crystalline silicon), providing increased solar cell flexibility and pliability while suppressing or even eliminating micro-crack generation and crack propagation or breakage in the semiconductor substrate layer.
  • a flexible backplane e.g., one made of a prepreg materials, for example having a relatively good Coefficient of Thermal Expansion or CTE match to that of the semiconductor substrate material such as crystalline silicon
  • a flexible monolithically isled (or monolithically integrated group of isles) cell also called an iCell
  • a flexible monolithically isled (or monolithically integrated group of isles) cell provides improved cell planarity and relatively small or negligible cell bow throughout solar cell processing steps such as any optional semiconductor layer thinning etch, texture etch, post-texture clean, PECVD passivation and anti-reflection coating (ARC) processes (and in some processing embodiments also allows for sunny- side -up PECVD processing of the substrates due to mitigation or elimination of thermally-induced cell warpage), and final solar cell metallization.
  • ARC anti-reflection coating
  • cell structures and fabrication embodiments provided are applicable to various dual level metallization schemes utilizing a backplane and M2 metallization layer.
  • the solar cell base and emitter contact metallization pattern is formed directly on the cell backside, for instance using a thin layer of screen printed or inkjet printed or plasma sputtered (PVD) or evaporated aluminum (or aluminum silicon alloy or Al/NiV/Sn stack) material layer.
  • PVD screen printed or inkjet printed or plasma sputtered
  • evaporated aluminum or aluminum silicon alloy or Al/NiV/Sn stack
  • Ml defines the solar cell contact metallization pattern, for example fine-pitch interdigitated back-contact (IBC) conductor fingers defining the base and emitter regions of the IBC cell.
  • the Ml layer extracts the solar cell current and voltage (hence the solar cell power) and transfers the solar cell electrical power through the conductive via plugs formed in the backplane to the second level/layer of high-conductivity solar cell metallization (herein referred to as M2) formed after Ml .
  • M2 second level/layer of high-conductivity solar cell metallization
  • the conductive via plugs can be formed concurrently during the formation of the patterned M2 layer, for example after laser drilling of via holes in the backplane layer.
  • the backplane material attached to the backside of the solar cell(s) and placed between patterned Ml and M2 layers may be a thin (e.g., between approximately 25 microns and 1 mm and in some instances between approximately 25 microns and 250 microns) sheet of a polymeric material with sufficiently low coefficient of thermal expansion (CTE) which is closely matched to that of the semiconductor absorber layer in order to avoid causing excessive thermally induced stresses and warpage on the solar cell array.
  • CTE coefficient of thermal expansion
  • the backplane material should meet process integration requirements for the backend cell fabrication processes, in particular chemical resistance during wet texturing of the cell frontside and thermal stability during the PECVD deposition of the frontside passivation and anti-reflection coating (ARC) layer.
  • the electrically insulating backplane material should also meet the module-level lamination process and long-term reliability requirements. While various suitable polymeric (such as plastics, fluropolymers, prepregs, etc.) and suitable non-polymeric materials (such as glass, ceramics, etc.) may be used as the backplane material, backplane material choice depends on many considerations including, but not limited to, material cost, ease of process integration, reliability, pliability, mass density, etc.
  • prepreg is prepreg and more particularly an aramid fiber resin based prepreg.
  • a non-woven aramid fiber is particularly advantageous.
  • prepregs are reinforcing materials pre- impregnated with resin and ready to use to produce composite parts (prepregs may be used to produce composites faster and easier than wet lay-up systems).
  • Prepregs may be manufactured by combining reinforcement fibers or fabrics with specially formulated pre-catalyzed resins using equipment designed to ensure consistency. Inexpensive prepreg material is commonly used in printed circuit boards.
  • the backplane (e.g., prepreg sheet) may be attached to the solar cell backside using a vacuum laminator. Upon applying a combination of heat and pressure, the thin backplane (e.g., prepreg sheet) is permanently laminated or attached to the backside of the partially-processed (or even fully-processed) solar cell.
  • subsequent post-lamination fabrication process steps may include: (i) completion of the texture and passivation processes on the sunnysides (frontsides) of the solar cell, (ii) completion of the high conductivity metallization (M2) on the backside of the solar cell (which may comprise part of the solar cell backplane).
  • the high- conductivity metallization M2 layer (for example comprising aluminum, copper, or silver, with aluminum and/or copper being preferred compared to silver because of much lower material cost) comprising both the emitter and base polarities is formed on the laminated backplane attached to the backside of the solar cell.
  • a higher conductivity M2 layer is formed on the backplane.
  • Via holes in some instances up to hundreds or thousands of via holes per solar cell
  • may have diameters in some instances tapered) in the range of approximately 50 up to 500 microns (particularly in the diameter range of about 100 to 300 microns).
  • These via holes land on pre-specified landing pad regions of Ml for electrical connection between the patterned M2 and Ml layers through conductive plugs formed in these via holes.
  • the vias may be covered or at least partially filled with conductive metallization and M2 may be deposited in separate steps and in other instances M2 deposition at least partially covers or partially fills the vias in the same M2 deposition or formation step.
  • the patterned high-conductivity metallization layer M2 is formed (for example by plasma sputtering, plating, evaporation, or a combination thereof - using an M2 material comprising, for instance, aluminum, Al/NIV, Al/NiV/Sn, or copper or solder-coated copper).
  • the patterned M2 layer may be designed orthogonal to Ml - in other words rectangular or tapered M2 fingers substantially perpendicular to the Ml fingers. Because of this orthogonal transformation, the patterned interdigitated M2 layer may have far fewer and wider IBC fingers than the Ml layer (for instance, by a factor of about 10 to 50 fewer M2 fingers with respect to the Ml fingers). Hence, the M2 layer may be formed in a much coarser pattern with wider IBC fingers than the Ml layer.
  • Optional solar cell busbars may be positioned on the M2 layer, and not on the Ml layer (in other words a busbarless Ml), to eliminate electrical shading losses associated with on-cell busbars. As both the base and emitter
  • interconnections and busbars may be positioned on the M2 layer on the solar cell backside backplane, electrical access is provided to both the base and emitter terminals of the solar cell on the backplane from the backside of the solar cell.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Sustainable Development (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Electromagnetism (AREA)
  • Sustainable Energy (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Photovoltaic Devices (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)

Abstract

L'invention concerne des solutions de fabrication efficaces utilisant le dopage laser pour réaliser des cellules solaires à jonction arrière et contact arrière à haut rendement. Le procédé comprend les étapes consistant à déposer, sur un substrat semi-conducteur de type n, une source de dopage de type sur des fenêtres de contact de base formées, recuire le substrat semi-conducteur de type n pour former au moins une région dopée de base et appliquer un faisceau laser formant au moins un région dopée d'émetteur dans ledit substrat semi-conducteur de type n.
PCT/US2015/047837 2014-08-31 2015-08-31 Dopage laser pour la réalisation de cellules solaires à jonction arrière et contact arrière WO2016033614A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201462044312P 2014-08-31 2014-08-31
US62/044,312 2014-08-31

Publications (1)

Publication Number Publication Date
WO2016033614A1 true WO2016033614A1 (fr) 2016-03-03

Family

ID=55400757

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2015/047837 WO2016033614A1 (fr) 2014-08-31 2015-08-31 Dopage laser pour la réalisation de cellules solaires à jonction arrière et contact arrière

Country Status (1)

Country Link
WO (1) WO2016033614A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113035976A (zh) * 2021-03-17 2021-06-25 常州时创能源股份有限公司 硼掺杂选择性发射极及制法、硼掺杂选择性发射极电池

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120032310A1 (en) * 2010-08-06 2012-02-09 Q-Cells Se Production Process For A Semi-Conductor Device And Semi-Conductor Device
US20120305063A1 (en) * 2009-12-09 2012-12-06 Solexel, Inc. High-efficiency photovoltaic back-contact solar cell structures and manufacturing methods using thin planar semiconductor absorbers
WO2013149093A1 (fr) * 2012-03-28 2013-10-03 Solexel, Inc. Cellules solaires à contact arrière utilisant une métallisation par alliage à base d'aluminium

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120305063A1 (en) * 2009-12-09 2012-12-06 Solexel, Inc. High-efficiency photovoltaic back-contact solar cell structures and manufacturing methods using thin planar semiconductor absorbers
US20120032310A1 (en) * 2010-08-06 2012-02-09 Q-Cells Se Production Process For A Semi-Conductor Device And Semi-Conductor Device
WO2013149093A1 (fr) * 2012-03-28 2013-10-03 Solexel, Inc. Cellules solaires à contact arrière utilisant une métallisation par alliage à base d'aluminium

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113035976A (zh) * 2021-03-17 2021-06-25 常州时创能源股份有限公司 硼掺杂选择性发射极及制法、硼掺杂选择性发射极电池
CN113035976B (zh) * 2021-03-17 2023-01-17 常州时创能源股份有限公司 硼掺杂选择性发射极及制法、硼掺杂选择性发射极电池

Similar Documents

Publication Publication Date Title
US9911875B2 (en) Solar cell metallization
JP6328606B2 (ja) 背面接触型太陽光発電モジュールの半導体ウエハのセル及びモジュール処理
US9515217B2 (en) Monolithically isled back contact back junction solar cells
US9379258B2 (en) Fabrication methods for monolithically isled back contact back junction solar cells
US20170278991A1 (en) Multi-level solar cell metallization
US20160013335A1 (en) Active backplane for thin silicon solar cells
US20150194547A1 (en) Systems and methods for monolithically isled solar photovoltaic cells
US20150171230A1 (en) Fabrication methods for back contact solar cells
US20130213469A1 (en) High efficiency solar cell structures and manufacturing methods
US20130228221A1 (en) Manufacturing methods and structures for large-area thin-film solar cells and other semiconductor devices
US9461582B2 (en) Electrical parametric testing for back contact semiconductor solar cells
EP2071632B1 (fr) Cellule solaire à couche mince et son procédé de fabrication
US20170236954A1 (en) High efficiency solar cell structures and manufacturing methods
EP2742536A2 (fr) Modules et cellules photovoltaïques solaires à haut rendement utilisant des absorbeurs minces à semi-conducteur cristallin
WO2013102181A1 (fr) Métallisation de cellules solaires à plusieurs niveaux
US20140158193A1 (en) Structures and methods of formation of contiguous and non-contiguous base regions for high efficiency back-contact solar cells
WO2014127067A1 (fr) Photopiles à contact arrière et à jonction arrière à îlot monolithique utilisant des tranches massives
AU2016200610B2 (en) Structures and methods of formation of contiguous and non-contiguous base regions for high efficiency back-contact solar cells
WO2016036892A1 (fr) Métallisation de cellule solaire à double niveau possédant des barres omnibus métalliques de premier niveau
EP3111482A1 (fr) Contacts auto-alignés pour cellules solaires à contact arrière
WO2016033614A1 (fr) Dopage laser pour la réalisation de cellules solaires à jonction arrière et contact arrière
WO2014011260A2 (fr) Structures de cellule solaire haute performance et procédés de fabrication
US20150207002A1 (en) Monolithic solar cell arrays and fabrication methods
WO2015100392A2 (fr) Contacts auto-alignés pour des cellules solaires à jonction arrière et contact arrière à îlot monolithique

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15835881

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15835881

Country of ref document: EP

Kind code of ref document: A1