WO2016000324A1 - Procede et appareil pour mettre en oeuvre une synchronisation temporelle - Google Patents

Procede et appareil pour mettre en oeuvre une synchronisation temporelle Download PDF

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Publication number
WO2016000324A1
WO2016000324A1 PCT/CN2014/086863 CN2014086863W WO2016000324A1 WO 2016000324 A1 WO2016000324 A1 WO 2016000324A1 CN 2014086863 W CN2014086863 W CN 2014086863W WO 2016000324 A1 WO2016000324 A1 WO 2016000324A1
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WO
WIPO (PCT)
Prior art keywords
information
tod information
tod
synchronization
time
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PCT/CN2014/086863
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English (en)
Chinese (zh)
Inventor
秦川
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中兴通讯股份有限公司
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Publication of WO2016000324A1 publication Critical patent/WO2016000324A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter

Definitions

  • the present invention relates to the field of communications, and in particular, to a method and apparatus for implementing time synchronization.
  • the third-generation (3rd-Generation, 3G for short) standard specifies that the switching of the base station work, roaming, etc. all require precise time control. Time synchronization is a very important technical indicator for 3G network construction.
  • the base stations can be synchronized by the built-in Global Positioning System (GPS); the network nodes can be synchronized by GPS or 1588 protocol; then, for the internal devices of the network, such as between the main control and the line card, the main control How to synchronize the time with the master, what is simple and reliable, and easy to implement.
  • GPS Global Positioning System
  • the existing processing method is that the transmitting side simultaneously transmits the clock frequency signal, the synchronization signal, and the time information to the receiving side through the hardware medium, and the description is as follows:
  • the transmitting side sends a synchronization pulse to the receiving side to indicate that data transmission will start; on the second signal line, the transmitting side transmits a clock signal to the receiving side at a frequency greater than nHz, where n is greater than 1; On the third signal line, the transmitting side transmits the time value data to the receiving side according to the synchronization pulse state, and the receiving side performs the sampling of the time value data according to the synchronization pulse and the clock signal; after receiving the time value, the receiving side is based on the received time value. Correct the local clock.
  • the third signal line mentioned above transmits time information.
  • the existing design also transmits time synchronization messages through Ethernet or other data channels to obtain time information from the device.
  • the disadvantage of the above scheme is that the clock frequency signal, the synchronization signal, and the time information transmission are highly correlated in hardware. If any signal is interfered during the transmission process, the time obtained by the receiving side is wrong without any protection measures. , affecting the function; if the time data is transmitted through Ethernet or other data channels, it will increase the complexity inside the system.
  • the present invention provides a method and apparatus for implementing time synchronization to solve at least the above technical problem.
  • a method for implementing time synchronization including: acquiring, by a first device in a network device, Time of Data (TOD) information, where the TOD information carries a synchronization pulse and time Information: the first device sends the TOD information to a second device within the network device.
  • TOD Time of Data
  • the TOD information further carries at least one of the following information: a synchronization byte, where the synchronization byte is used to indicate that the second device stops parsing the TOD information when parsing the synchronization byte error; Check mark bit.
  • the method before the sending, by the first device, the TOD information to the second device, the method further includes: receiving a trigger signal generated by the software control enable; and receiving a pulse trigger signal generated by the first device at a timing;
  • the sending, by the first device, the TOD information to the second device comprises: sending, by the first device, the TOD information on a signal line.
  • the transmission frequency of the TOD information is not greater than the frequency of the clock signal generated locally by the second device, wherein the frequency of the clock signal is used to parse the TOD information.
  • a method for implementing time synchronization including: receiving, by a second device in a network device, TOD information from a first device, where the TOD information carries synchronization pulses and time information; The second device parses the TOD information.
  • the second device parses the TOD information, and the second device parses the TOD information according to a locally generated clock signal, where the sending frequency of the TOD information is not greater than locally generated by the second device.
  • the frequency of the clock signal is not greater than locally generated by the second device.
  • the TOD information further carries at least one of the following information: a synchronization byte, where the synchronization byte is used to indicate that the second device stops parsing the TOD information when parsing the synchronization byte error; Check mark bit.
  • a time synchronization implementation apparatus which is applied to a first device in a network device, and includes: an acquisition module, configured to acquire TOD information, where the TOD information carries a synchronization pulse and time information. And a sending module configured to send the TOD information to the second device.
  • a time synchronization implementation apparatus which is applied to a second device in a network device, and includes: a receiving module, configured to receive TOD information from the first device, where the TOD information carries Synchronization pulse and time information; an analysis module configured to parse the TOD information.
  • the present invention solves the technical problem that the first device in the network device sends the TOD information carrying the synchronization pulse and the time information to the second device, and solves the related problem that the reliability of the time synchronization solution is not high. Complex and other technical problems, simple and reliable.
  • FIG. 1 is a flow chart of a method for implementing time synchronization according to an embodiment of the present invention
  • FIG. 2 is a structural block diagram of an apparatus for implementing time synchronization according to an embodiment of the present invention
  • FIG. 3 is a flow chart of another method for implementing time synchronization according to an embodiment of the present invention.
  • FIG. 4 is a structural block diagram of another apparatus for implementing time synchronization according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a synchronization system according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a TOD information format according to an embodiment of the present invention.
  • FIG. 7 is a flow chart of parsing TOD information from a device in accordance with an embodiment of the present invention.
  • FIG. 1 is a flow chart of a method for implementing time synchronization according to an embodiment of the present invention. As shown in FIG. 1, the method includes steps S102-S104:
  • Step S102 The first device in the network device acquires TOD information, where the TOD information carries a synchronization pulse and time information.
  • Step S104 The first device sends the TOD information to the second device.
  • the first A signal line and a third signal line simplify the implementation and reduce the probability of low reliability caused by hardware and improve reliability.
  • the TOD information may be generated locally or may be obtained from a third-party device, but is not limited thereto.
  • the TOD information may further carry a synchronization byte, where the synchronization byte is used to instruct the second device to stop parsing the TOD information when parsing the synchronization byte error; and
  • the check mark bit is carried in the TOD information, for example, a parity bit.
  • the triggering manner of the step S104 is various, for example, the triggering signal generated by the software control enablement may be received, and the manner may be based on software control, for example, when the timing time is not reached, the triggering is enabled to increase the frequency of sending the TOD information;
  • the pulse trigger signal generated by the first device timing may be received, but is not limited thereto.
  • the first device may send the TOD information on one signal line.
  • the transmission frequency of the TOD information is not greater than the frequency of the clock signal generated locally by the second device, wherein the frequency of the clock signal is used to parse the TOD information.
  • the second signal line can be omitted.
  • a device for implementing time synchronization is further provided.
  • the device is applied to a first device in a network device, as shown in FIG. 2, and includes:
  • the obtaining module 20 is configured to obtain TOD information, where the TOD information carries a synchronization pulse and time information;
  • the sending module 22 is connected to the obtaining module 20 and configured to send the TOD information to the second device.
  • the reliability of time synchronization can also be improved, and the implementation complexity can be reduced.
  • the obtaining module 20 is located in the first processor.
  • the sending module 22 is located in the second processor; or the obtaining module 20 and the sending module 22 are both located in the same processor, but are not limited thereto.
  • the method includes:
  • Step S302 the second device in the network device receives TOD information from the first device, where the TOD information carries synchronization pulses and time information;
  • Step S304 the second device parses the TOD information.
  • the second device parses the TOD information according to the locally generated clock signal, and the sending frequency of the TOD information is not greater than the frequency of the clock signal generated locally by the second device. This further eliminates the second signal line mentioned in the related art.
  • the TOD information further carries at least one of the following information: a synchronization byte, where the synchronization byte is used to instruct the second device to stop parsing the TOD information when parsing the synchronization byte error. ; check mark.
  • another time synchronization implementation device is further provided, and the device is applied to the second device in the network device.
  • the device includes:
  • the receiving module 40 is configured to receive TOD information from the first device, where the TOD information carries synchronization pulses and time information;
  • the parsing module 42 is coupled to the receiving module 40 and configured to parse the TOD information.
  • the receiving module 40 is located in the first processor.
  • the parsing module 42 is located in the second processor; or the receiving module 40 and the parsing module 42 are both located in the same processor, but are not limited thereto.
  • This embodiment proposes a simple and reliable internal synchronization method for network devices.
  • the physical connection requires only one, and the method of transmitting relative to the three lines is simpler and more reliable, easy to transplant, and reduces system resources.
  • the master device (equivalent to the first device) transmits combined time information (TOD) to the slave device (corresponding to the second device) in a prescribed form, the information including synchronization bytes, synchronization pulses, time information, and Check the flag.
  • TOD time information
  • the composite time information actually contains the information transmitted by the first and third signal lines in the above three-wire transmission method; and the clock signal line transmitted by the second signal line can be simplified and omitted, and the clock signal and time information are maintained when transmitting.
  • the frequency is the same, and maintains a fixed phase relationship, which is convenient for sampling and recovering the time value data on the receiving side.
  • This embodiment omits the signal because a similar clock signal can be directly generated on the receiving side, and the composite TOD is received.
  • the information is parsed, self-corrected, and synchronized with the master device.
  • the software enable trigger is added to increase the frequency of the composite TOD, increase the number of times the slave device is synchronized, and thus improve the synchronization time of the slave device.
  • synchronous byte detection and 1 bit parity are added. If there is synchronization byte out of synchronization or verification error after device parsing, it will not self-correct, and the method of three-wire transmission is not These tests exist
  • Figure 6 shows the TOD message format, as shown in Figure 6, including the sync byte, sync pulse, time information, and check flag bits, all of which are transmitted to the slave device over a single signal line.
  • D5 in Fig. 6 is represented by binary, that is, 1101_0101, which represents a value.
  • the slave Since the BIT number and frequency of the composite TOD are customized, when the slave detects the rising edge of the sync pulse, it generates the same local clock as the composite TOD frequency, and generates a counter starting from 0 to recover the subsequent time information. prepare. In order to prevent the signal from being interfered during transmission, the sync byte detection and the 1-bit parity are added. If there is a sync byte out of sync or a check error after the device is parsed, it will not self-correct.
  • the most critical of the composite TOD signals is 80-bit time information, which includes 48-bit second information and 32-bit nanosecond information.
  • FIG. 7 shows the flow of parsing the TOD information from the device, as shown in FIG. 7, including the following processing steps:
  • Step S702 The rising edge of the signal triggers the slave device to perform composite TOD analysis (ie, determining whether the rising edge of the Tod_psync signal is valid).
  • Step S704 In order to prevent mixing of other error signals, a synchronization code is added to the composite TOD signal, and if the synchronization code is incorrect, the analysis is stopped (ie, it is determined whether the synchronization is effective).
  • Step S706 determining whether the TOD parsing is completed, and obtaining 80-bit accurate time information t1 by logical simple string processing.
  • Step S708 In order to prevent signal interference during transmission, a 1-bit parity is added, that is, whether the checksum is accurate.
  • Step 710 ⁇ t is the sum of the fixed delay ⁇ t1 of the serial signal itself and the fixed time overhead ⁇ t2 when the line card is parsed during the parsing process. Use t1 + ⁇ t to update the local time (as shown in Figure 6).
  • the above steps implement that the internal device time of the network device is synchronized with the master device.
  • the embodiment of the present invention achieves the following beneficial effects: instead of transmitting the synchronization pulse and time through the first signal line and the third signal line, the synchronization pulse and time information are carried in one TOD information.
  • the information therefore, omits the first signal line and the third signal line, thereby simplifying the implementation and reducing the probability of low reliability caused by hardware and improving reliability.
  • the second device parses the TOD information according to the locally generated clock signal, the transmission frequency of the TOD information is not greater than the frequency of the clock signal generated locally by the second device, and the second root mentioned in the related art may be further omitted.
  • Signal line since the second device parses the TOD information according to the locally generated clock signal, the transmission frequency of the TOD information is not greater than the frequency of the clock signal generated locally by the second device, and the second root mentioned in the related art may be further omitted.
  • a storage medium is further provided, wherein the software includes the above-mentioned software, including but not limited to: an optical disk, a floppy disk, a hard disk, an erasable memory, and the like.
  • modules or steps of the present invention described above can be implemented by a general-purpose computing device that can be centralized on a single computing device or distributed across a network of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein.
  • the steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps thereof are fabricated as a single integrated circuit module.
  • the invention is not limited to any specific combination of hardware and software.
  • the foregoing technical solution provided by the embodiment of the present invention solves the technical problem that the first device in the network device sends the TOD information carrying the synchronization pulse and the time information to the second device, and solves the related problem in the related art.
  • the reliability is not high, and the technical problems such as complexity are realized, and the implementation is simple and reliable.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

La présente invention concerne un procédé et un appareil pour mettre en oeuvre une synchronisation temporelle. Le procédé comprend les étapes suivantes : un premier dispositif parmi des dispositifs de réseau acquiert des informations de date/heure du jour (TOD), les informations de TOD comportant une impulsion de synchronisation et des informations temporelles; et le premier dispositif envoie les informations de TOD à un second dispositif. La solution technique fournie dans la présente invention permet de résoudre le problème d'une mise en oeuvre complexe et peu fiable des solutions de synchronisation temporelle de l'état de la technique, et d'assurer une mise en oeuvre simple et fiable.
PCT/CN2014/086863 2014-06-30 2014-09-18 Procede et appareil pour mettre en oeuvre une synchronisation temporelle WO2016000324A1 (fr)

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CN107786294B (zh) * 2017-09-22 2019-04-30 烽火通信科技股份有限公司 一种集中式1588的实现***及方法
WO2020147108A1 (fr) * 2019-01-18 2020-07-23 华为技术有限公司 Procédé et appareil de synchronisation temporelle
CN116566535A (zh) * 2023-07-12 2023-08-08 南京典格通信科技有限公司 卫星通信网络中硬件解析tod信息的装置与方法

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