WO2015188414A1 - 3d显示的像素插黑方法及使用该方法的电路 - Google Patents

3d显示的像素插黑方法及使用该方法的电路 Download PDF

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Publication number
WO2015188414A1
WO2015188414A1 PCT/CN2014/081438 CN2014081438W WO2015188414A1 WO 2015188414 A1 WO2015188414 A1 WO 2015188414A1 CN 2014081438 W CN2014081438 W CN 2014081438W WO 2015188414 A1 WO2015188414 A1 WO 2015188414A1
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Prior art keywords
pixel
transistor
pixels
gate
row
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PCT/CN2014/081438
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English (en)
French (fr)
Inventor
杜鹏
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深圳市华星光电技术有限公司
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Priority to US14/378,605 priority Critical patent/US20160232861A1/en
Publication of WO2015188414A1 publication Critical patent/WO2015188414A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/001—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background
    • G09G3/003—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background to produce spatial visual effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a pixel insertion method for 3D display and a circuit using the same. Background technique
  • Shutter-type 3D technology divides one frame of image into two by increasing the picture refresh rate, forming two sets of image frames corresponding to the left and right eyes, and the viewers watch through the shutter-like eyes.
  • the shutter type 3D technology when the left and right eye image screens of an image are alternately displayed, crosstalk problems are apt to occur.
  • the crosstalk problem is that the received left eye image contains the content of the right eye image, and the received right eye image contains the content of the left eye image, that is, the left and right eye images interfere with each other, resulting in an error in the formed 3D image.
  • the reasons for the formation of crosstalk mainly include the following two types: First, the screen display of the liquid crystal display device adopts a top-down sequential scanning mode.
  • the liquid crystal display device displays the left eye image
  • the left eye receives the left eye image
  • the left eye image scans to The last line, immediately after scanning the right eye image from the first line
  • the right eye begins to receive the right eye image, however, on the other lines of the LCD screen (from the second line to the most The next line) still maintains the left eye image of the previous field, so that the right eye image received by the right eye has a part of the left eye image.
  • the left eye image received by the left eye has a part of the right eye image, forming a left and right image. Eye image crosstalk.
  • the liquid crystal molecule deflection process requires a certain time, which is the liquid crystal response time.
  • the screen display of the liquid crystal display device adopts a sequential scanning mode from top to bottom scanning.
  • the left eye image receives the left eye image
  • the left eye image scans to the last line to complete the scanning, and then starts scanning from the first line.
  • the right eye image the right eye begins to receive the right eye image.
  • the driving voltage of the first row of liquid crystal cells needs to be changed, so that the deflection angle of the first row of liquid crystal cells changes.
  • the deflection of the liquid crystal cell needs a certain amount.
  • the liquid crystal response time, the received right eye image includes a process of changing from the left eye image to the right eye image, that is, in the liquid crystal response time, the right eye simultaneously receives the left eye image and the right eye image, thereby forming a left Eye and right eye image picture crosstalk.
  • crosstalk can be solved by inserting a black image between the left and right images.
  • a left eye picture ⁇ black picture ⁇ right eye picture ⁇ black picture LBRB
  • LBRB left eye picture
  • the image and the black image, the right eye simultaneously receives the right eye image and the black image, and since the black image is the background image, crosstalk does not occur with the normal image.
  • Black Insertion (BI) is commonly used in flat display devices to improve the display quality of dynamic images of display panels. It is used to insert black between continuous motion pictures and images.
  • the screen eliminates the integration effect of the human eye on the image, further improves the moving picture response timing (MPRT) that is often present in the dynamic view of the display panel, and improves the animation quality.
  • MPRT moving picture response timing
  • crosstalk can be solved by shortening the response time of the liquid crystal.
  • the commonly used black insertion method may be a signal in which a black screen is written from a data line to a pixel (Pixel) to achieve black insertion.
  • FIG. 1A is a schematic diagram of a commonly used black insertion circuit, including: a data line for providing a data signal (datall and a data line (Datall) are provided to provide a gate line of a scan signal (gate 11 common electrode (VCOM11 pixel transistor ( Trll pixel electrode (D11 storage capacitor (C stg ll and liquid crystal capacitor (C LC 11 ); the pixel transistor (Trll) includes a gate (gll X source (sll X drain (dll), the pixel transistor (Trll) a gate (g11) electrically connected to the gate line (Gate 11), a source (s11) of the pixel transistor (Tr11) electrically connected to the data line (Datall), the pixel transistor (Trll) The drain ( dll ) is electrically connected to
  • Another method of inserting black is to connect the pixel electrode of the pixel and the common electrode through a certain circuit structure (for example, TFT), and when the black screen needs to be inserted, the pixel electrode is discharged to the common electrode to realize a black image.
  • TFT a certain circuit structure
  • a data line providing a data signal (datall' and a data line (Datall') are provided to provide a gate line for scanning signals (Gatell'X control) Signal terminal, common electrode (VCOM11' pixel transistor ( ⁇ ⁇ X control transistor (T12, pixel electrode (Dir storage capacitor (C stg ll, and liquid crystal C LC 11,); the pixel transistor (Trl 1, ⁇ ⁇ Pole (gll' X source (sll' drain ( dir ), the control transistor ( T12 ' ) includes a gate ( gl2 ' source ( sl2 ' drain ( dir ); the gate of the pixel transistor ( ⁇ 1 ⁇ )
  • the pole (gll') is electrically connected to the gate line (Gatell'), the source (sll') of the pixel transistor (?1?) is electrically connected to the data line (Datall'), and the pixel transistor (Trll' The drain ( dll)
  • Another object of the present invention is to provide a circuit for using the pixel insertion method of the 3D display, in which a thin film transistor connected to a pixel electrode of a different polarity is turned on by a control signal to realize black screen display.
  • the present invention provides a pixel insertion method for 3D display, comprising: step 100, providing a plurality of data lines for providing data signals, a plurality of gate lines for providing scan signals, and a plurality of pixels (P) Each pixel is connected to one data line and one gate line, and the polarity of each pixel is opposite to the polarity of the upper, lower, left and right pixels adjacent thereto;
  • Step 200 providing a plurality of control transistors (T) to connect pixels of different polarities;
  • Step 300 providing a plurality of control signal terminals, electrically connected to the control transistor (T), applying a voltage to the control signal terminal, controlling the transistor (?) to be disconnected, applying a high voltage to the control signal terminal, and controlling the transistor ( ⁇ ) Conduction.
  • control transistor ( ⁇ ) is connected to the second ⁇ + 2 row pixel and the second ⁇ + 2 row pixel.
  • control transistor (?) connects the 2n+1th column pixels arranged in the same row with the 2nd + 2nd column pixels.
  • the pixel ( ⁇ ) in the step 100 can be divided into two regions, that is, a partition of the upper half and a partition of the lower half, and the partition of the upper half has the same polarity as the partition of the lower half.
  • control transistor (?) connects the partitions of the lower half of the mth row of pixels arranged in the same column with the partitions of the upper half of the m+1th row of pixels.
  • control transistor (T) When the control transistor (T) is turned on, the positive polarity pixel voltage is lowered, and the negative polarity pixel voltage is raised to finally reach the vicinity of the common electrode voltage.
  • the present invention also provides a circuit for using the pixel insertion method of the 3D display, comprising: a plurality of data lines (Data) for providing a data signal, a plurality of gate lines for providing a scan signal (a gate number of control signal terminals, a common electrode ( VCOM is a plurality of pixels (PX and several control transistors (T) defined by a data line (Data) and a gate line (P); each of the pixels is connected to a data line And a gate line, the pixel ( ⁇ ) includes a pixel transistor ( Tr ), a pixel electrode ( D ), a storage capacitor (C stg and a liquid crystal capacitor ( C LC ); the control transistor ( T ) includes a gate ( g ) a source (s), a drain (d), the pixel transistor (Tr) comprising a first gate (gl X first source (sl X first drain (dl);
  • a control transistor (T) is connected; a source (s) of the control transistor (T) is electrically connected to a pixel electrode (D) of the same second 2n+1 row of pixels, and the control transistor (T)
  • the drain (d) is electrically connected to the pixel electrode (D) of the 2n+2th row of pixels in the same column; the gate (g) of the control transistor (T) disposed in the same row is common to a certain control signal terminal Connection
  • the first gate ( gl ) of the pixel transistor ( Tr ) disposed in the same row of pixels is commonly connected to a certain gate line ( Gate ), and the first source of the pixel transistor ( Tr ) is disposed in the pixel of the same column ( Si) is connected in common to a certain data line (Date); the first drain (dl) of the pixel transistor (Tr) is electrically connected to the pixel electrode (D); the upper plate of the storage capacitor ( Cstg ) Connected to the upper plate of the liquid crystal capacitor (C LC ) and electrically connected to the pixel electrode ( D ) , the lower plate of the storage capacitor ( C stg ) is electrically connected to the common electrode ( VCOM ), and the liquid crystal capacitor ( The lower plate of C LC ) is electrically connected to the common electrode ( VCOM X
  • the control transistor (T) and the pixel transistor (Tr) are both thin film transistors.
  • the polarity of each pixel (P) is opposite to the polarity of the upper, lower, left, and right pixels adjacent thereto.
  • the present invention also provides a circuit for using the pixel insertion method of the 3D display, comprising: providing a plurality of data lines of a data signal (Data provides a plurality of gate lines of the scan signal (the gate number of the control signal terminals, the common electrode ( VCOM is a plurality of pixels (P' X and a plurality of control transistors (T' ) defined by a data line (Data) and a gate line ( Gate); each of the pixels is connected to one data line and one gate line,
  • the pixel (P') includes a pixel transistor (Tr' pixel electrode (D' storage capacitor ( Cstg , and liquid crystal capacitor (?);
  • the control transistor (T,) includes a gate (g' X source (s, X drain (d,), the pixel transistor (Tr') includes a first gate (gl' X first source (sl' X first drain (dl ');
  • the source (s') is electrically connected to the pixel electrode (D') of the second n+1 column of the same row, and the drain (d') of the control transistor (T') is electrically connected to the same row 2n+2 columns of pixel electrode electrodes (D');
  • the gates ( ⁇ ') of the control transistors ( ) arranged in the same row are connected in common with a certain control signal terminal;
  • pixel transistors arranged in pixels in the same row a first gate ( gl ' ) of Tr'
  • a pixel transistor (Tr' ) is disposed in a pixel of the same column a source ( sl ' ) is connected in common to a data line ( Data );
  • control transistor (T') and the pixel transistor (Tr') are both thin film transistors.
  • each pixel (P') is opposite to the polarity of the upper, lower, left, and right pixels adjacent thereto.
  • the present invention also provides a circuit for using the pixel insertion method of the 3D display, comprising: providing a plurality of data lines of a data signal (Data provides a plurality of gate lines of the scan signal (the gate number of the control signal terminals, the common electrode ( VCOM is a plurality of pixels (P") defined by a data line and a gate line, and a plurality of control transistors (T"); each of the pixels is connected to a data line and a gate line.
  • Data provides a plurality of gate lines of the scan signal (the gate number of the control signal terminals, the common electrode ( VCOM is a plurality of pixels (P") defined by a data line and a gate line, and a plurality of control transistors (T")
  • each of the pixels is connected to a data line and a gate line.
  • the control transistor (T") includes a gate (g"X source (s" drain (d”); the pixel (P") is divided into two regions, that is, a partition (P1") of the upper half and the lower half of the partition (P2 "); partition (P1 upper half of the” first pixel electrode (Dl ”)) in the bottom half of the partition (P 2") of the second pixel electrode (D2 The polarity of the "" is the same.
  • the partition (P1") of the upper half includes a first pixel transistor (Trl”) and a first pixel electrode (D1")
  • the lower portion partition (P 2 " ) includes a second pixel transistor (Tr2") and a second pixel electrode (D2");
  • the first pixel transistor (Trl") includes a gate (gl” ⁇ source (sl" drain (dl")
  • the second pixel transistor (Tr2") includes a gate (g2" source (s2"), a drain (d2”);
  • the drain ( dl" is electrically connected to the first pixel electrode ( D1 " ), and the drain ( d 2 " ) of the second pixel transistor (Tr 2 " ) is electrically connected to the second pixel electrode (D 2 ) "); arranged in the same row of pixels in the first pixel transistors (Trl” gate of) the (GL ') and the second pixel transistor (Tr 2 ") of (
  • the partition (P2") of the lower half of the pixel of the mth row of the same column and the partition (P1" of the upper half of the pixel of the m+1th row are connected by a control transistor (T"); the control transistor The source (s" of (T") is electrically connected to the pixel electrode (D2" of the partition (P2") of the lower half of the pixel of the mth row of the same column, and the drain of the control transistor (T") (d”) a pixel electrode (D1") electrically connected to a partition (P1") of the upper half of the pixel of the m+1th row; a gate of the control transistor (T”) disposed in the same row (g " ) with a certain control signal terminal common Connected.
  • the control transistor ( ⁇ " ⁇ first pixel transistor (Trl”) and the second pixel transistor (Tr2”) are thin film transistors.
  • the present invention provides a pixel insertion method for a 3D display and a circuit using the same, and redesigns the panel for the currently used inversion method (column inversion, line inversion, dot inversion) 3D inserts black.
  • the conventional inversion mode when the panel is normally displayed, the positive and negative polar pixels are each half.
  • the pixel electrodes of different polarities are turned on by the thin film transistor, and when the black insertion is required, the different signals are connected by the control signal.
  • the thin film transistor of the pixel electrode is turned on, so that the positive polarity pixel voltage is lowered, and the negative polarity pixel voltage is raised, and finally reaches the vicinity of the common electrode voltage, thereby realizing black screen display.
  • This way does not increase the load of the common electrode line, nor does it increase the power consumption of the entire panel.
  • the voltage between the source and the drain of the discharged thin film transistor is large (positive and negative pixel electrodes), and the discharge speed is also improved. .
  • Figure l a is the commonly used black-plug circuit structure diagram
  • Figure lb is another structural diagram of a black insertion circuit that is commonly used nowadays.
  • FIG. 2 is a flow chart of a method for inserting pixels in a 3D display according to the present invention
  • FIG. 3 is a circuit diagram of a first embodiment of a circuit using the method of the present invention.
  • FIG. 4 is a circuit diagram of a second embodiment of a circuit using the method of the present invention.
  • Figure 5 is a circuit diagram of a third embodiment of a circuit using the method of the present invention. detailed description
  • the present invention provides a pixel insertion method for a 3D display, including: Step 100: providing a plurality of data lines for providing data signals, a plurality of gate lines for providing scan signals, and a plurality of pixels (P) Each pixel is connected to one data line and one gate line, and each The polarity of each pixel is opposite to the polarity of the upper, lower, left and right pixels adjacent thereto; Step 200, providing a plurality of control transistors (T) to connect pixels of different polarities; Step 300, providing several control signals The terminal is electrically connected to the control transistor (T), the control signal terminal applies a voltage, the control transistor (?) is turned off, the control signal terminal applies a high voltage, and the control transistor (?) is turned on.
  • control transistor ( ⁇ ) is connected to the second ⁇ + 2 row pixel and the second ⁇ + 2 row pixel.
  • control transistor (?) connects the 2n+1th column pixels arranged in the same row with the 2nd + 2nd column pixels.
  • the pixel ( ⁇ ) in the step 100 can be divided into two regions, that is, a partition of the upper half and a partition of the lower half, and the partition of the upper half has the same polarity as the partition of the lower half.
  • control transistor (T) When the control transistor (T) is turned on, the positive polarity pixel voltage is lowered, and the negative polarity pixel voltage is raised to finally reach the vicinity of the common electrode voltage.
  • FIG. 3 is a circuit diagram of a first embodiment of a circuit for inserting black pixels using the 3D display according to the present invention. This is a dot inversion panel design. Positive sign ( + ) in Figure 3 And a minus sign ( - ) indicates the polarity of the pixel electrode voltage. Including: several data lines providing data signals
  • VCOM is defined by a plurality of pixels defined by a data line (Data) and a gate line (Gate) ( P), and a plurality of control transistors (T); each of the pixels is connected to a data line and a gate line, and the pixel (P) includes a pixel transistor (Tr), a pixel electrode (D), and a storage capacitor (C) Stg X and a liquid crystal capacitor (C LC ); the control transistor (T) includes a gate (g), a source (s), a drain (d), and the pixel transistor (Tr) includes a first gate (gl) X first source (sl X first drain (dl);
  • the first gate ( gl ) of the pixel transistor ( Tr ) disposed in the same row of pixels is commonly connected to a certain gate line ( Gate ), and the first source of the pixel transistor ( Tr ) is disposed in the pixel of the same column ( Si) is connected in common to a data line (Data); the first drain (dl) of the pixel transistor (Tr) is electrically connected to the pixel electrode (D); the upper plate of the storage capacitor ( Cstg ) versus The upper plate of the liquid crystal capacitor (C LC ) is electrically connected to the pixel electrode ( D ) , and the lower plate of the storage capacitor ( C stg ) is electrically connected to the common electrode ( VCOM ), and the liquid crystal capacitor (C The lower plate of LC ) is electrically connected to the common electrode (VCOM X
  • control transistor (T) and the pixel transistor (Tr) are both thin film transistors.
  • each pixel (P) is opposite to the polarity of the upper, lower, left and right pixels adjacent thereto.
  • the path indicated by the arrow in FIG. 3 is a current passing path when black is inserted, and flows from the positive pixel electrode to the negative pixel electrode, and the circuit of the present invention uses the pixel insertion method of the 3D display.
  • the working process is: when the left eye and the right eye are written, the control signal terminal is applied with a low voltage, and the control transistor (T) is turned off. When a black screen needs to be written, the control signal terminal is applied with a high voltage, and the control is performed. The transistor (T) is turned on.
  • the present invention and the existing pixel electrode discharge to the common electrode (VCOM) (please refer to FIG. 1b), firstly reduce the current on the common electrode (VCOM), thereby reducing the common electrode (VCOM) Power consumption, secondly, the potential of the common electrode (VCOM) is also more stable, which is conducive to the improvement of display quality.
  • the specific 3D pixel insertion method of the first embodiment of the present invention is:
  • Step 100 Providing a plurality of data lines providing data signals (Data ⁇ is a plurality of gate lines providing a scan signal (Gate and a plurality of pixels (P), and each pixel is connected to one data line and one gate line, and each one The polarity of the pixel is opposite to the polarity of the upper, lower, left and right pixels adjacent thereto;
  • Step 200 providing a plurality of control transistors (T), connecting the 2n+1 row pixels arranged in the same column with the 2n+2 rows of pixels;
  • Step 300 providing a plurality of control signal terminals, electrically connected to the control transistor (T), applying a voltage to the control signal terminal, controlling the transistor (?) to be disconnected, applying a high voltage to the control signal terminal, and controlling the transistor ( ⁇ ) Conduction.
  • FIG. 4 is a circuit diagram of a second embodiment of a circuit for using the pixel insertion method of the 3D display according to the present invention. This is also a dot reversed panel design.
  • the sign (+) and the minus sign (-) in Fig. 4 indicate the polarity of the pixel electrode voltage.
  • pixel includes a pixel transistor (Tr 'pixel electrode (D' storage capacitor C stg 'and the liquid crystal electrically C LC'); said control transistor (T ') includes a gate (g' X source (s 'drain (d')
  • the pixel transistor (Tr') includes a first gate ( gl' X first source ( sl ' first drain ( dl , );
  • control transistor (T') and the pixel transistor (Tr') are both thin film transistors.
  • each pixel (P') is the same as the polarity of the upper, lower, left and right pixels adjacent thereto opposite.
  • the path indicated by the arrow in FIG. 4 is a current passing path when black is inserted, and flows from the positive pixel electrode to the negative pixel electrode, and the circuit of the present invention uses the pixel insertion method of the 3D display.
  • the working process is: when the left eye and right eye images are written, the control signal terminal is applied with a low voltage, and the control transistor (T') is turned off. When a black screen needs to be written, the control signal terminal is applied with a high voltage.
  • VCOM common electrode
  • the specific 3D pixel insertion method of the second embodiment of the present invention is:
  • Step 100 ′ providing a plurality of data lines providing data signals (Data number of gate lines providing a scan signal ( Gate and a plurality of pixels ( P′ ), each pixel connecting one data line and one gate line, and each The polarity of one pixel is opposite to the polarity of the upper, lower, left and right pixels adjacent thereto;
  • Step 200' providing a plurality of control transistors (T'), and the 2n+1 column pixels arranged in the same row are connected to the 2n+2 column pixels;
  • Step 300' providing a plurality of control signal terminals, and electrically connecting with the control transistor (T') A low voltage is applied to the control signal terminal, the control transistor ( ⁇ ') is turned off, a high voltage is applied to the control signal terminal, and the control transistor (T') is turned on.
  • the same design method can also be used.
  • the pixel units in the liquid crystal pixel are often divided into two or more domains, and such a design can also be inserted by using the scheme of the present invention. black.
  • FIG. 5 is a circuit diagram of a third embodiment of a circuit for inserting black pixels using the 3D display according to the present invention. This is also a dot reversed panel design.
  • the path indicated by the arrow in Fig. 5 is the current passing path when black is inserted; the positive sign (+) and the negative sign (-) indicate the polarity of the pixel electrode voltage.
  • the method includes: a plurality of data lines (Data) for providing a data signal, a plurality of gate lines (gate) for providing a scan signal, a plurality of control signal terminals, and a common electrode (VCOM is composed of a data line (Data) and a gate line (Gate) a defined number of pixels (P" X and a plurality of control transistors (T"); the control transistor (T") includes a gate (g" X source (s" X drain (d"); each One pixel is connected to one data line and one gate line, and the pixel (P") is divided into two areas, that is, a partition (P1") of the upper half and a partition (P2") of the lower half; the upper half “the first - the pixel electrode (D1 partition (Pl)” portion) and the second pixel electrode (D 2 ”) of the lower half of the partition ( ⁇ ,) in the same polarity as the upper half of the partition.
  • Data data line
  • gate for providing a scan signal
  • the first pixel transistor (Trl) includes the first pixel transistor (Trl") and a first pixel electrode (D1")
  • the lower half of the partition (“ 2 ") includes a second pixel transistor (Tr2") and a second pixel electrode (D2");
  • the first pixel transistor (Trl") A gate (gl"), a source (si"), a drain (dl")
  • the second pixel transistor (Tr2") includes a gate (g2" X source (s2" drain (d2”) ;
  • drain (dl pixel of the first transistor (Trl)" is electrically connected to the first pixel electrode (D1 "), the second pixel transistor (Tr2 is” drain) of (d 2 ") electrically Connected to the second pixel electrode (D 2 ");
  • the partition (P2") of the lower half of the pixel of the mth row of the same column and the partition (P1" of the upper half of the pixel of the m+1th row are connected by a control transistor (T"); the control transistor The source (s" of (T") is electrically connected to the pixel electrode (D2" of the partition (P2") of the lower half of the pixel of the mth row of the same column, and the drain of the control transistor (T") (d”) a pixel electrode (D1") electrically connected to a partition (P1") of the upper half of the pixel of the m+1th row; a gate of the control transistor (T”) disposed in the same row (g " ) with a certain control signal terminal common Connected.
  • the control transistor ( ⁇ " ⁇ first pixel transistor (Trl”) and the second pixel transistor (Tr2”) are thin film transistors.
  • the circuit of the third embodiment of the present invention uses the pixel insertion method of the 3D display: when the left eye and right eye signals are written, the control signal terminal is applied with a low voltage, and the control transistor (T" is turned off.
  • the control signal terminal is applied with a high voltage, and the control transistor (T") is turned on, so that the positive polarity pixel voltage is lowered, and the negative polarity pixel voltage is raised, eventually tending to The common electrode voltage is used to display the black screen.
  • the specific 3D pixel insertion method of the third embodiment of the present invention is:
  • Step 100 providing a plurality of data lines (Data) for providing data signals, a plurality of gate lines (gates) for providing scanning signals, and a plurality of pixels (P"), each of which is connected with one data line and one gate a line, and the polarity of each pixel is opposite to the polarity of the upper, lower, left, and right pixels adjacent thereto; the pixel (P") is divided into a partition (P1") of the upper half and a partition of the lower half ( P2" );
  • Step 200 providing a number of control transistors (T") that will be placed in the same m-th line image a partition (P 2 " ) of the lower half of the prime is connected to a partition ( P1 " ) of the upper half of the pixel of the m+1th row;
  • Step 300 providing a plurality of control signal terminals, electrically connected to the control transistor (T"), applying a low voltage to the control signal terminal, turning off the control transistor (T"), applying a high voltage to the control signal terminal, and controlling The transistor (T") is turned on.
  • the present invention provides a pixel insertion method for a 3D display and a circuit using the same, and redesigns the 3D of the panel for the commonly used inversion method (column inversion, line inversion, dot inversion). Insert the black way.
  • the conventional inversion mode when the panel is normally displayed, the positive and negative polar pixels are each half.
  • the pixel electrodes of different polarities are turned on by the thin film transistor, and when the black insertion is required, the different signals are connected by the control signal.
  • the thin film transistor of the pixel electrode is turned on, so that the positive polarity pixel voltage is lowered, and the negative polarity pixel voltage is raised, and finally reaches the vicinity of the common electrode voltage, thereby realizing black screen display.

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Abstract

本发明提供一种3D显示的像素插黑方法，包括：提供数个提供数据信号的数据线、提供扫描信号的数个栅极线、及数个像素（P）；每一个像素连接一条数据线与一条栅极线，且每一个像素的极性与与其相邻的上下左右的像素的极性都是相反的；提供数个控制晶体管（T），将不同极性的像素连接；提供数个控制信号端，与控制晶体管（T）电性连接，所述控制信号端施加低电压，控制晶体管（T）断开，所述控制信号端施加高电压，控制晶体管（T）导通。这样的方式不会增加公共电极线路的负载，也不会增加整个面板的功率消耗，另外放电的薄膜晶体管源漏极之间的电压较大（正负像素电极），放电速度也会有所提高。本发明还提供使用该方法的电路。

Description

3D显示的像素插黑方法及使用该方法的电踣 技术领域
本发明涉及显示技术领域，尤其涉及一种 3D显示的像素插黑方法及使 用该方法的电路。 背景技术
最近 3D显示功能的需求增长非常迅速，快门式 3D技术通过提高画面 刷新率，再将一帧图像一分为二，形成对应左右眼的两组图像画面交错显 示，观众通过快门式眼睛观看后呈现出 3D的效果。 在快门式 3D技术中， 当图像的左右眼图像画面交替显示时，容易产生串扰（ Crosstalk )问题。 串 扰问题为：所接收的左眼图像中包含有右眼图像的内容，所接收的右眼图 像中包含有左眼图像的内容，即左右眼图像相互干扰，导致所形成的 3D图 像发生错误。
形成串扰的原因主要包括如下两种：第一、 液晶显示装置的屏幕显示 采用自上而下顺序扫描方式，当液晶显示装置显示左眼图像时，左眼接收 左眼图像，左眼图像扫描至最后一行，紧接着从第一行开始扫描右眼图像， 右眼开始接收右眼图像，然而，在液晶显示屏的其他行上（从第二行到最 后一行）仍然保持上一场的左眼图像，这样，右眼接收到的右眼图像中有 部分左眼图像，同理，左眼接收到的左眼图像中有部分右眼图像，形成左 右眼图像串扰。 第二、 液晶分子偏转过程需要一定时间，该时间即为液晶 响应时间。 液晶显示装置的屏幕显示采用自上向下扫描的顺序扫描方式， 当显示左眼图像时，左眼接收左眼图像，左眼图像扫描至最后一行完成扫 描时，紧接着从第一行开始扫描右眼图像，右眼开始接收右眼图像。 这样 , 第一行液晶单元从左眼图像向右眼图像变化时，第一行液晶单元的驱动电 压需发生变化，使第一行液晶单元偏转角度发生变化，然而，液晶单元的 偏转需要一定的液晶响应时间，则接收的右眼图像包含从左眼图像向右眼 图像变化的过程，也就是说，在该液晶响应时间中，右眼同时接收到左眼 画面和右眼画面，从而形成左眼和右眼图像画面串扰。
对于第一种原因的串扰，可通过在左右图像之间***黑色图像的方式 解决，例如可以采用左眼画面→黑画面→右眼画面→黑画面（ LBRB ) ,使 得左眼同时接收到左眼图像以及黑色图像，右眼同时接收到右眼图像以及 黑色图像，由于黑色图像为背景图像，则不会与正常图像发生串扰。 插黑 技术（ Black Insertion , BI )普遍使用在平面显示设备中，以改善显示面板 的动态影像的显示质量。 其是利用在连续的动态影像与影像之间，***黑 画面，以消除人眼对影像的积分效应 ( integration effect ) ,进一步改善显示 面板在动态景像中常有的动画拖景现象 ( moving picture response timing , MPRT ),提升动画质量。 对于第二种原因的串扰，可通过缩短液晶响应时 间的方式解决。
目前，常用的插黑方式可以是由数据线（ Data Line )向像素（ Pixel ) 中写入黑画面的信号，以实现插黑的目的。 请参阅图 la ,为现在常用的插 黑电路示意图，包括：提供数据信号的数据线（ Datall 与数据线（ Datall ) 交叉设置的提供扫描信号的栅极线（ Gate 11 公共电极（ VCOM11 像素 晶体管（ Trll 像素电极（ Dll 存储电容（ Cstgll 及液晶电容（ CLC11 )； 所述像素晶体管 (Trll )包括栅极 ( gll X源极（ sll X漏极（ dll ) ,所述 像素晶体管 (Trll )的栅极 (gll )电性连接于栅极线 ( Gate 11 ) ,所述像素 晶体管 (Trll )的源极 ( sll )电性连接于数据线 ( Datall ) ,所述像素晶体 管（ Trll )的漏极（ dll )电性连接于像素电极（ D11 ),所述存储电容（ Cstgll ) 的上极板与液晶电容（ CLC11 )的上极板连接后电性连接于像素电极（ D11 ), 所述存储电容 ( Cstgl 1 )的下极板电性连接于公共电极 ( VCOM11 ) ,所述液 晶电容（ CLC11 )的下极板电性连接于公共电极（ VCOM11 )；所述像素晶 体管（ Trll )为薄膜晶体管（ Thin Film Transistor , TFT )；图 la中箭头标注 的是黑色画面信号写入的路径。 但是，这种方式数据线上的电压切换频率 加快，会导致功耗升高，根据有关资料，采用这种方式的总功耗会增加 20 ~ 40%。
另外一种插黑方式是将像素的像素电极和公共电极通过某种电路结构 (例如 TFT )连接起来，在需要***黑画面时像素电极向公共电极放电，实 现黑画面。 请参阅图 lb ,为现在常用的另外一种插黑电路示意图，包括： 提供数据信号的数据线 ( Datall' 与数据线 ( Datall' )交叉设置的提供扫 描信号的栅极线（Gatell'X 控制信号端、 公共电极（ VCOM11' 像素晶 体管（ Ί ΙΓ X控制晶体管（ T12， 像素电极（ Dir 存储电容（ Cstgll， 及液晶电 CLC11， )；所述像素晶体管 ( Trl 1，庖括栅极 ( gll' X源极（ sll' 漏极（ dir ) ,所述控制晶体管 ( T12' )包括栅极 ( gl2' 源极 ( sl2' 漏 极（ dir )；所述像素晶体管（ ΊΥ1Γ )的栅极（ gll' )电性连接于栅极线 ( Gatell' ) ,所述像素晶体管（ Ί 1Γ )的源极（ sll' )电性连接于数据线 ( Datall' ) ,所述像素晶体管 ( Trll' )的漏极 ( dll' )电性连接于像素电极 ( Dll' ) ,所述存储电容（ Cstgll， )的上极板与液晶电容（ CLC11， )的上极 板连接后电性连接于像素电极（ Dll' ) ,所述存储电容（ Cstgir )的下极板 电性连接于公共电极 ( vcoMir ) ,所述液晶电容 ( cLCir )的下极板电性 连接于公共电极 ( VCOM11 ' )；所述控制晶体管 ( T12' )的源极 ( sl2' )电 性连接于像素电极 ( D11 ' ) ,所述控制晶体管 ( T12' )的栅极（ g12， )电性 连接于控制信号端，所述控制晶体管（ T12' )的漏极 ( dl2' )电性连接于公 共电极（ VCOM11 ' )；所述像素晶体管（ Ί 1 Γ )与控制晶体管（ Τ1Γ )均 为薄膜晶体管；图 lb中箭头标注的是像素点击漏电的路径。 但是，这种模 式工作时公共电极的负载较大，可能会影响显示品质。 发明内容
本发明的目的在于提供一种 3D显示的像素插黑方法，在不增加面板功 率消耗的情况下，实现 3D的插黑功能，也不会额外增加公共电极线路的负 载。
本发明的另一目的在于提供使用该 3D显示的像素插黑方法的电路，通 过控制信号使连接不同极性像素电极的薄膜晶体管导通，实现黑画面显示。
为实现上述目的，本发明提供一种 3D显示的像素插黑方法，包括： 步骤 100、提供数个提供数据信号的数据线、数个提供扫描信号的栅极 线、 及数个像素（ P ) ,每一个像素连接一条数据线与一条栅极线，且每一 个像素的极性与与其相邻的上下左右的像素的极性都是相反的；
步骤 200、 提供数个控制晶体管（ T ) ,将不同极性的像素连接； 步骤 300、 提供数个控制信号端，与控制晶体管 ( T )电性连接，所述 控制信号端施加 ί氐电压，控制晶体管（ Τ )断开，所述控制信号端施加高电 压，控制晶体管 ( Τ )导通。
所述步骤 200中控制晶体管 ( Τ )将配置在同一歹啲第 2η+1行像素与 第 2η+2行像素连接。
所述步骤 200中控制晶体管 ( Τ )将配置在同一行的第 2η+1列像素与 第 2η+2列像素连接。
所述步骤 100中像素（ Ρ )可分为两个区，即上半部分的分区与下半部 分的分区，所述上半部分的分区与下半部分的分区的极性相同。
所述步骤 200中控制晶体管（ Τ )将配置在同一列的第 m行像素的下半 部分的分区与第 m+1行像素的上半部分的分区连接。
所述控制晶体管 ( T )导通时，正极性像素电压降低，而负极性的像素 电压升高，最终达到公共电极电压附近。
本发明还提供使用该 3D显示的像素插黑方法的电路，包括：提供数据 信号的数个数据线（ Data )、 提供扫描信号的数个栅极线 ( Gate 数个控制 信号端、 公共电极（ VCOM 由数据线 ( Data )与栅极线 ( Gate ) P艮定的 数个像素（ P X 及数个控制晶体管（ T )；所述每一个像素连接一条数据线 与一条栅极线，所述像素（ Ρ )包括像素晶体管（ Tr )、 像素电极（ D )、 存 储电容 ( Cstg 及液晶电容 ( CLC )；所述控制晶体管 ( T )包括栅极 ( g )、 源极（ s )、 漏极（ d ) ,所述像素晶体管 ( Tr )包括第一栅极（ gl X 第一源 极（sl X 第一漏极（dl ) ;
配置在同一列的第 2n+l行像素与第 2n+2 ( n=0 , 1 , 2〜）行像素通过
—个控制晶体管（ T )连接；所述控制晶体管 ( T )的源极 ( s )电性连接于 同一歹啲第 2n+l行像素的像素电极（ D ) ,所述控制晶体管（ T )的漏极（ d ) 电性连接于同一列的第 2n+2行像素的像素电极 ( D ) ;所述配置在同一行的 控制晶体管 ( T )的栅极 ( g )与某一条控制信号端公共连接；
配置在同一行的像素中像素晶体管（ Tr )的第一栅极（ gl )与某一条 栅极线 ( Gate )公共连接，配置在同一列的像素中像素晶体管 ( Tr )的第一 源极 ( si )与某一条数据线 ( Date )公共连接；所述像素晶体管 ( Tr )的第 一漏极 ( dl )电性连接于像素电极（ D )；所述存储电容（ Cstg )的上极板与 液晶电容 ( CLC )的上极板连接后电性连接于像素电极（ D ) ,所述存储电容 ( Cstg )的下极板电性连接于公共电极 ( VCOM ) ,所述液晶电容 ( CLC )的 下极板电性连接于公共电极（ VCOM X
所述控制晶体管 ( T )与像素晶体管 ( Tr )均为薄膜晶体管。 所述每一像素（ P )的极性与与其相邻的上下左右的像素的极性都是相 反的。
本发明还提供一种使用该 3D显示的像素插黑方法的电路，包括：提供 数据信号的数个数据线 ( Data 提供扫描信号的数个栅极线 ( Gate 数个 控制信号端、 公共电极 ( VCOM 由数据线 ( Data )与栅极线 ( Gate )限 定的数个像素（ P' X 及数个控制晶体管（ T' )；所述每一个像素连接一条数 据线与一条栅极线，所述像素（ P' )包括像素晶体管（ Tr' 像素电极（ D' 存储电容（ Cstg， 及液晶电容（ Ο ，）;所述控制晶体管（ T，）包括栅极（ g' X 源极（ s， X 漏极（ d，），所述像素晶体管 ( Tr' )包括第一栅极 ( gl' X 第一 源极（sl' X 第一漏极（dl ' ) ;
配置在同一行的第 2n+l列像素与第 2η+2 ( η=0 , 1 , 2... )列像素通过 —个控制晶体管 ( T， )连接；所述控制晶体管 ( Τ， )的源极 ( s' )电性连接 于同一行的第 2n+l列像素的像素电极（ D' ) ,所述控制晶体管 ( T' )的漏 极（ d' )电性连接于同一行的第 2n+2列像素的像素电极（ D' )；所述配置 在同一行的控制晶体管 ( )的栅极 ( §' )与某一条控制信号端公共连接； 配置在同一行的像素中像素晶体管 ( Tr' )的第一栅极 ( gl ' )与某一条 栅极线（ Gate )公共连接；配置在同一列的像素中像素晶体管（ Tr' )的第 —源极 ( sl ' )与某一条数据线 ( Data )公共连接；所述像素晶体管 ( Tr' ) 的第一漏极（ dl，）电性连接于像素电极（ D，）；所述存储电容（ Cstg， )的上 极板与液晶电容 ( CLC' )的上极板连接后电性连接于像素电极（ D，），所述 存储电容 ( Cstg， )的下极板电性连接于公共电极（ VCOM ) ,所述液晶电容 ( CLC' )的下极板电性连接于公共电极 ( VCOM X
所述控制晶体管 ( T' )与像素晶体管（ Tr' )均为薄膜晶体管。
所述每一像素（ P' )的极性与与其相邻的上下左右的像素的极性都是相 反的。
本发明还提供一种使用该 3D显示的像素插黑方法的电路，包括：提供 数据信号的数个数据线 ( Data 提供扫描信号的数个栅极线 ( Gate 数个 控制信号端、 公共电极 ( VCOM 由数据线 ( Data )与栅极线 ( Gate )限 定的数个像素（ P" )、 及数个控制晶体管 ( T" )；所述每一个像素连接一条 数据线与一条栅极线，所述控制晶体管 ( T" )包括栅极（ g" X 源极 ( s" 漏极（ d" )；所述像素（ P" )分为两个区，即上半部分的分区（ P1 " )与下 半部分的分区（ P2" )；所述上半部分的分区（ P1 " )中的第一像素电极（ D1 " ) 与下半部分的分区（ P2" )中的第二像素电极 ( D2" )的极性相同。 所述上 半部分的分区（ P1 " )包括第一像素晶体管（ Trl " )与第一像素电极（ D1 " ) , 所述下半部分的分区（ P2" )包括第二像素晶体管 ( Tr2" )与第二像素电极 ( D2" )；所述第一像素晶体管（ Trl" )包括栅极（ gl" λ源极 ( sl" 漏 极（ dl" ) ,所述第二像素晶体管 ( Tr2" )包括栅极 ( g2" 源极 ( s2" )、 漏极（ d2" )；所述第一像素晶体管（ Trl" )的漏极（ dl" )电性连接于第一 像素电极（ D1" ) ,所述第二像素晶体管（ Tr2" )的漏极（ d2" )电性连接 于第二像素电极（ D2" )；配置于同一行的像素中第一像素晶体管（ Trl" ) 的栅极（ gl" )与第二像素晶体管（ Tr2" )的栅极（ g2" )与某一条栅极线 公共连接，配置在第 m ( m=l , 2... )行的像素中第一像素晶体管 ( Trl" ) 的源极 ( si" )与第二像素晶体管的源极 ( s2" )与某一条数据线公共连接 , 配置在第 m+1行的像素中第一像素晶体管（ Trl" )的源极（ si" ) 与第二 像素晶体管的源极（ s2" )与另一条数据线公共连接。
配置在同一列的第 m行像素的下半部分的分区（ P2" )与第 m+1行像 素的上半部分的分区（ P1" )通过一个控制晶体管 ( T" )连接；所述控制晶 体管（ T" )的源极（ s" )电性连接于同一列的第 m行像素下半部分的分区 ( P2" )的像素电极 ( D2" ) ,所述控制晶体管 ( T" )的漏极（ d" )电性连 接于同一歹啲第 m+1行像素上半部分的分区（ P1" )的像素电极（ D1" )； 配置在同一行的控制晶体管 ( T" )的栅极（ g" )与某一条控制信号端公共 连接。
所述控制晶体管（Τ" λ 第一像素晶体管（Trl" )、 及第二像素晶体管 ( Tr2" )均为薄膜晶体管。
所述每一像素（ P" )的极性与与其相邻的上下左右的像素的极性都是 相反的。
本发明的有益效果：本发明提供一种 3D显示的像素插黑方法及使用该 方法的电路，针对现在常用的反转方式（列反转，行反转，点反转 ) ,重新 设计面板的 3D插黑方式。在常用的反转方式中，面板正常显示时正负极性 像素各占一半，本发明将不同极性的像素电极用薄膜晶体管导通，在需要 进行插黑时，通过控制信号使连接不同极性像素电极的薄膜晶体管导通， 这样正极性像素电压降 ί氏，而负极性的像素电压升高，最终达到公共电极 电压附近，实现黑画面显示。 这样的方式不会增加公共电极线路的负载， 也不会增加整个面板的功率消耗，另外放电的薄膜晶体管源漏极之间的电 压较大 (正负像素电极 ) ,放电速度也会有所提高。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本 发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发 明加以限制。 附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明 的技术方案及其它有益效果显而易见。
附图中，
图 l a为现在常用的插黑电路结构图；
图 lb为现在常用的另外一种插黑电路结构图；
图 2为本发明 3D显示的像素插黑方法流程图；
图 3为本发明使用该方法的电路第一实施例的电路图；
图 4为本发明使用该方法的电路第二实施例的电路图；
图 5为本发明使用该方法的电路第三实施例的电路图。 具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明 的优选实施例及其附图进行详细描述。
请参阅图 2 ,本发明提供一种 3D显示的像素插黑方法，包括： 步骤 100、提供数个提供数据信号的数据线、数个提供扫描信号的栅极 线、 及数个像素（ P ) ,每一个像素连接一条数据线与一条栅极线，且每一 个像素的极性与与其相邻的上下左右的像素的极性都是相反的； 步骤 200、 提供数个控制晶体管（ T ) ,将不同极性的像素连接； 步骤 300、 提供数个控制信号端，与控制晶体管 ( T )电性连接，所述 控制信号端施加 ί氐电压，控制晶体管（ Τ )断开，所述控制信号端施加高电 压，控制晶体管 ( Τ )导通。
所述步骤 200中控制晶体管 ( Τ )将配置在同一歹啲第 2η+1行像素与 第 2η+2行像素连接。
所述步骤 200中控制晶体管 ( Τ )将配置在同一行的第 2η+1列像素与 第 2η+2列像素连接。
所述步骤 100中像素（ Ρ )可分为两个区，即上半部分的分区与下半部 分的分区，所述上半部分的分区与下半部分的分区的极性相同。
所述步骤 200中控制晶体管（ Τ )将配置在同一列的第 m行像素的下半 部分的分区与第 m+1 ( m=l , 2 , ... )行像素的上半部分的分区连接。
所述控制晶体管 ( T )导通时，正极性像素电压降低，而负极性的像素 电压升高，最终达到公共电极电压附近。
请参阅图 3 ,为本发明使用该 3D显示的像素插黑方法的电路第一实施 例的电路图，这是一个点反转（ Dot Inversion )的面板设计。图 3中正号（ + ) 和负号（ - )表示像素电极电压的极性。 包括：提供数据信号的数个数据线
( Data )、 提供扫描信号的数个栅极线（ Gate )、 数个控制信号端（ Control signal )、 公共电极 ( VCOM 由数据线（ Data )与栅极线 ( Gate )限定的 数个像素（ P )、 及数个控制晶体管（ T )；所述每一个像素连接一条数据线 与一条栅极线，所述像素（ P )包括像素晶体管（ Tr )、 像素电极（ D )、 存 储电容（ Cstg X 及液晶电容 ( CLC )；所述控制晶体管 ( T )包括栅极 ( g )、 源极（ s )、 漏极（ d ) ,所述像素晶体管 ( Tr )包括第一栅极（ gl X 第一源 极（sl X 第一漏极（dl ) ;
配置在同一列的第 2n+l行像素与第 2n+2 ( n=0 , 1 , 2〜）行像素通过 —个控制晶体管（ T )连接；所述控制晶体管 ( T )的源极 ( s )电性连接于 同一歹啲第 2n+l行像素的像素电极（ D ) ,所述控制晶体管 ( T )的漏极 ( d ) 电性连接于同一列的第 2n+2行像素的像素电极 ( D ) ;所述配置在同一行的 控制晶体管 ( T )的栅极 ( g )与某一条控制信号端公共连接；
配置在同一行的像素中像素晶体管（ Tr )的第一栅极（ gl )与某一条 栅极线 ( Gate )公共连接，配置在同一列的像素中像素晶体管 ( Tr )的第一 源极 ( si )与某一条数据线 ( Data )公共连接；所述像素晶体管 ( Tr )的第 一漏极 ( dl )电性连接于像素电极（ D )；所述存储电容（ Cstg )的上极板与 液晶电容 ( CLC )的上极板连接后电性连接于像素电极（ D ) ,所述存储电容 ( Cstg )的下极板电性连接于公共电极 ( VCOM ) ,所述液晶电容 ( CLC )的 下极板电性连接于公共电极 ( VCOM X
所述控制晶体管 ( T )与像素晶体管 ( Tr )均为薄膜晶体管。
所述每一像素（ P )的极性与与其相邻的上下左右的像素的极性都是相 反的。
具体地，图 3 中箭头所示的路径是插黑时的电流通过路径，从正极性 的像素电极流向负极性的像素电极，本发明使用该 3D显示的像素插黑方法 的电路第一实施例的工作过程为：在左眼和右眼画面写入时，控制信号端 加低电压，此时控制晶体管（ T )断开，当需要写入黑画面时，控制信号端 加上高电压，控制晶体管（ T )导通，由于同一列的第 2n+l行像素与第 2n+2 行像素的极性相反，所以正极性的像素的电压会逐渐降 ί氏，负极性的像素 的电压会逐渐升高，最终达到相同的电位，而且最终的电位和公共电极 ( VCOM )电压非常接近，面板呈现出黑画面。 本发明和现有的像素电极 放电至公共电极 ( VCOM )(请结合参阅图 lb )相比，首先是降低了公共电 极（ VCOM )上的电流，从而减小了在公共电极（ VCOM )上的功率消耗， 其次公共电极 ( VCOM )的电位也更加稳定，有利于显示品质的提升。 本发明第一实施例的具体 3D像素插黑方法为：
步骤 100、 提供数个提供数据信号的数据线（ Data λ 数个提供扫描信 号的栅极线 ( Gate 及数个像素（ P ) ,每一个像素连接一条数据线与一条 栅极线，且每一个像素的极性与与其相邻的上下左右的像素的极性都是相 反的；
步骤 200、 提供数个控制晶体管（ T ) ,将配置在同一列的第 2n+l行像 素与第 2n+2行像素连接；
步骤 300、 提供数个控制信号端，与控制晶体管 ( T )电性连接，所述 控制信号端施加 ί氐电压，控制晶体管（ Τ )断开，所述控制信号端施加高电 压，控制晶体管 ( Τ )导通。
对于行反转（ Row Inversion )的面板，也可以使用相同的设计方法。 请参阅图 4 ,为本发明使用该 3D显示的像素插黑方法的电路第二实施 例的电路图，这也是一个点反转的面板设计。 图 4中正号 ( + )和负号（ - ) 表示像素电极电压的极性。 包括：提供数据信号的数个数据线（ Data 提 供扫描信号的数个栅极线 ( Gate 数个控制信号端、 公共电极（ VCOM 由数据线 ( Data )与栅极线（ Gate )限定的数个像素（ P' )、 及数个控制晶 体管（ T' )；所述每一个像素连接一条数据线与一条栅极线，所述像素（ P' ) 包括像素晶体管( Tr' 像素电极( D' 存储电 Cstg' 及液晶电 CLC' )； 所述控制晶体管 ( T' )包括栅极 ( g' X 源极 ( s' 漏极（ d' ) ,所述像素晶 体管 ( Tr' )包括第一栅极 ( gl' X 第一源极 ( sl' 第一漏极（ dl，）；
配置在同一行的第 2n+l列像素与第 2η+2 ( η=0 , 1 , 2... )列像素通过 一个控制晶体管 ( T' )连接；所述控制晶体管（ T' )的源极 ( s' )电性连接 于同一行的第 2n+l列像素的像素电极（ D' ) ,所述控制晶体管 ( T' )的漏 极（ d' )电性连接于同一行的第 2n+2列像素的像素电极（ D' )；所述配置 在同一行的控制晶体管 ( T' )的栅极 ( g' )与某一条控制信号端公共连接； 配置在同一行的像素中像素晶体管 ( Tr' )的第一栅极 ( gl ' )与某一条 栅极线（ Gate )公共连接；配置在同一列的像素中像素晶体管（ Tr' )的第 —源极 ( si ' )与某一条数据线 ( Data )公共连接；所述像素晶体管 ( Tr' ) 的第一漏极（ dl，）电性连接于像素电极（ D，）；所述存储电容 ( Cstg， )的上 极板与液晶电容 ( CLC' )的上极板连接后电性连接于像素电极（ D，），所述 存储电容 ( Cstg， )的下极板电性连接于公共电极（ VCOM ) ,所述液晶电容 ( CLC' )的下极板电性连接于公共电极 ( VCOM X
所述控制晶体管 ( T' )与像素晶体管（ Tr' )均为薄膜晶体管。
所述每一像素（ P' )的极性与与其相邻的上下左右的像素的极性都是相 反的。
具体地，图 4中箭头所示的路径是插黑时的电流通过路径，从正极性 的像素电极流向负极性的像素电极，本发明使用该 3D显示的像素插黑方法 的电路第二实施例的工作过程为：在左眼和右眼画面写入时，控制信号端 加低电压，此时控制晶体管（ T' )断开，当需要写入黑画面时，控制信号 端加上高电压，此时控制晶体管（ T' )导通，由于同一行的第 2η+1列像素 与第 2η+2 ( η=0 , 1 , 2... )列像素的极性相反，所以正极性的像素的电压会 逐渐降 ί氏，负极性的像素的电压会逐渐升高，最终达到相同的电位，而且 最终的电位和公共电极 ( VCOM )电压非常接近，面板呈现出黑画面。
本发明第二实施例的具体 3D像素插黑方法为：
步骤 100'、 提供数个提供数据信号的数据线（ Data 数个提供扫描信 号的栅极线 ( Gate 及数个像素（ P' ) ,每一个像素连接一条数据线与一条 栅极线，且每一个像素的极性与与其相邻的上下左右的像素的极性都是相 反的；
步骤 200'、 提供数个控制晶体管（ T' ) ,配置在同一行的第 2n+l列像 素与第 2n+2列像素连接；
步骤 300'、 提供数个控制信号端，与控制晶体管（ T' )电性连接，所 述控制信号端施加低电压，控制晶体管（ τ' )断开，所述控制信号端施加 高电压，控制晶体管 ( T' )导通。
对于列反转 ( Column Inversion )的面板，也可以使用相同的设计方法。 在大尺寸的面板设计中，为了改善大视角色偏的问题，液晶像素中的 像素单元往往都分为两个或者多个区（ Domain ) ,这样的设计也可以采用本 发明的方案来进行插黑。
请参阅图 5 ,为本发明使用该 3D显示的像素插黑方法的电路第三实施 例的电路图，这也是一个点反转的面板设计。 图 5中箭头所示的路径是插 黑时的电流通过路径；正号（ + )和负号（ - )表示像素电极电压的极性。 包括：提供数据信号的数个数据线（ Data )、 提供扫描信号的数个栅极线 ( Gate )、 数个控制信号端、 公共电极 ( VCOM 由数据线 ( Data )与栅极 线（ Gate )限定的数个像素（ P" X 及数个控制晶体管（ T" )；所述控制晶 体管（ T" )包括栅极 ( g" X 源极（ s" X 漏极 ( d" )；所述每一个像素连接 一条数据线与一条栅极线，所述像素（ P" )分为两个区，即上半部分的分 区（ P1 " )与下半部分的分区（ P2" )；所述上半部分的分区（ P1 " )中的第 —像素电极 ( D1 " )与下半部分的分区（ ΡΓ， )中的第二像素电极（ D2" ) 的极性相同。 所述上半部分的分区（ P1 " )包括第一像素晶体管 ( Trl " )与 第一像素电极（ Dl" ) ,所述下半部分的分区（ Ρ2" )包括第二像素晶体管 ( Tr2" )与第二像素电极 ( D2" )；所述第一像素晶体管 ( Trl" )包括栅极 ( gl" )、 源极（ si" )、 漏极（ dl" ) ,所述第二像素晶体管 ( Tr2" )包括栅 极（ g2" X源极（ s2" 漏极（ d2" )；所述第一像素晶体管（ Trl" )的漏 极（ dl" )电性连接于第一像素电极（ D1" ) ,所述第二像素晶体管 ( Tr2" ) 的漏极（ d2" )电性连接于第二像素电极（ D2" )；配置于同一行的像素中 第一像素晶体管 ( Trl" )的栅极 ( gl" )与第二像素晶体管 ( Tr2" )的栅极 ( g2" )与某一条栅极线公共连接，配置在第 m ( m=l , 2... )行的像素中第 一像素晶体管（ Trl" )的源极（ si" )与第二像素晶体管的源极（ s2" )与 某一条数据线公共连接，配置在第 m+1行的像素中第一像素晶体管 ( Trl " ) 的源极（ si" ) 与第二像素晶体管的源极（ s2" )与另一条数据线公共连接。
配置在同一列的第 m行像素的下半部分的分区（ P2" )与第 m+1行像 素的上半部分的分区（ P1" )通过一个控制晶体管 ( T" )连接；所述控制晶 体管（ T" )的源极（ s" )电性连接于同一列的第 m行像素下半部分的分区 ( P2" )的像素电极 ( D2" ) ,所述控制晶体管 ( T" )的漏极（ d" )电性连 接于同一歹啲第 m+1行像素上半部分的分区（ P1" )的像素电极（ D1" )； 配置在同一行的控制晶体管 ( T" )的栅极（ g" )与某一条控制信号端公共 连接。
所述控制晶体管（Τ" λ 第一像素晶体管（Trl" )、 及第二像素晶体管 ( Tr2" )均为薄膜晶体管。
所述每一像素（ P" )的极性与与其相邻的上下左右的像素的极性都是 相反的。
具体地，本发明使用该 3D显示的像素插黑方法的电路第三实施例的工 作过程为：在写入左眼和右眼信号时，控制信号端加低电压，控制晶体管 ( T" )断开，像素正常充电。 当需要***黑画面时，控制信号端加高电压， 控制晶体管（ T" )导通，就能使正极性的像素电压降低，负极性的像素电 压升高，最终趋于公共电极电压，实现黑画面的显示。
本发明第三实施例的具体 3D像素插黑方法为：
步骤 100"、提供数个提供数据信号的数据线（ Data )、数个提供扫描信 号的栅极线（ Gate )、 及数个像素（ P" ) ,每一个像素连接一条数据线与一 条栅极线，且每一个像素的极性与与其相邻的上下左右的像素的极性都是 相反的；所述像素（ P" )分为上半部分的分区（ P1 " )与下半部分的分区 ( P2" )；
步骤 200"、 提供数个控制晶体管（ T" ) ,将配置在同一歹啲第 m行像 素的下半部分的分区（ P2" )与第 m+1行像素的上半部分的分区（ P1 " )连 接；
步骤 300"、 提供数个控制信号端，与控制晶体管 ( T" )电性连接，所 述控制信号端施加低电压，控制晶体管（ T" )断开，所述控制信号端施加 高电压，控制晶体管 ( T" )导通。
综上所述，本发明提供一种 3D显示的像素插黑方法及使用该方法的电 路，针对现在常用的反转方式（列反转，行反转，点反转 ) ,重新设计面板 的 3D插黑方式。在常用的反转方式中，面板正常显示时正负极性像素各占 一半，本发明将不同极性的像素电极用薄膜晶体管导通，在需要进行插黑 时，通过控制信号使连接不同极性像素电极的薄膜晶体管导通，这样正极 性像素电压降低，而负极性的像素电压升高，最终达到公共电极电压附近， 实现黑画面显示。 这样的方式不会增加公共电极线路的负载，也不会增加 整个面板的功率消耗，另外放电的薄膜晶体管源漏极之间的电压较大（正 负像素电极 ) ,放电速度也会有所提高。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术 方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形 都应属于本发明权利要求的保护范围。

Claims

杈 利 要 求
1、 一种 3D显示的像素插黑方法，包括：
步骤 100、提供数个提供数据信号的数据线、数个提供扫描信号的栅极 线、 及数个像素，每一个像素连接一条数据线与一条栅极线，且每一个像 素的极性与与其相邻的上下左右的像素的极性都是相反的；
步骤 200、 提供数个控制晶体管，将不同极性的像素连接；
步骤 300、提供数个控制信号端，与控制晶体管电性连接，所述控制信 号端施加低电压，控制晶体管断开，所述控制信号端施加高电压，控制晶 体管导通。
2、如权利要求 1所述的 3D显示的像素插黑方法，其中，所述步骤 200 中控制晶体管将配置在同一列的第 2n+l行像素与第 2n+2行像素连接。
3、如权利要求 1所述的 3D显示的像素插黑方法，其中，所述步骤 200 中控制晶体管将配置在同一行的第 2n+l列像素与第 2n+2列像素连接。
4、如权利要求 1所述的 3D显示的像素插黑方法，其中，所述步骤 100 中像素可分为两个区，即上半部分的分区与下半部分的分区，所述上半部 分的分区与下半部分的分区的极性相同。
5、如权利要求 4所述的 3D显示的像素插黑方法，其中，所述步骤 200 中控制晶体管将配置在同一列的第 m行像素的下半部分的分区与第 m+1行 像素的上半部分的分区连接。
6、 如权利要求 1所述的 3D显示的像素插黑方法，其中，所述控制晶 体管（ T )导通时，正极性像素电压降低，而负极性的像素电压升高，最终 达到公共电极电压附近。
7、 一种使用如权利要求 1所述的 3D显示的像素插黑方法的电路，包 括：提供数据信号的数个数据线、 提供扫描信号的数个栅极线、 数个控制 信号端、 公共电极、 由数据线与栅极线限定的数个像素、 及数个控制晶体 管；所述每一个像素连接一条数据线与一条栅极线，所述像素包括像素晶 体管、 像素电极、 存储电容、 及液晶电容；所述控制晶体管包括栅极、 源 极、 漏极，所述像素晶体管包括第一栅极、 第一源极、 第一漏极；
配置在同一列的第 2n+l行像素与第 2n+2行像素通过一个控制晶体管 连接；所述控制晶体管的源极电性连接于同一列的第 2n+l行像素的像素电 极 ,所述控制晶体管的漏极电性连接于同一列的第 2n+2行像素的像素电极； 所述配置在同一行的控制晶体管的栅极与某一条控制信号端公共连接； 配置在同一行的像素中像素晶体管的第一栅极与某一条栅极线公共连 接，配置在同一列的像素中像素晶体管的第一源极与某一条数据线公共连 接；所述像素晶体管的第一漏极电性连接于像素电极；所述存储电容的上 极板与液晶电容的上极板连接后电性连接于像素电极，所述存储电容的下 极板电性连接于公共电极，所述液晶电容的下极板电性连接于公共电极。
8、如权利要求 7所述的使用该 3D显示的像素插黑方法的电路，其中， 所述控制晶体管与像素晶体管均为薄膜晶体管。
9、如权利要求 7所述的使用该 3D显示的像素插黑方法的电路，其中， 所述每一像素的极性与与其相邻的上下左右的像素的极性都是相反的。
10、一种使用如权利要求 1所述的 3D显示的像素插黑方法的电路，包 括：提供数据信号的数个数据线、 提供扫描信号的数个栅极线、 数个控制 信号端、 公共电极、 由数据线与栅极线限定的数个像素、 及数个控制晶体 管；所述每一个像素连接一条数据线与一条栅极线，所述像素包括像素晶 体管、 像素电极、 存储电容、 及液晶电容；所述控制晶体管包括栅极、 源 极、 漏极，所述像素晶体管包括第一栅极、 第一源极、 第一漏极；
配置在同一行的第 2n+l列像素与第 2n+2列像素通过一个控制晶体管 连接；所述控制晶体管的源极电性连接于同一行的第 2n+l列像素的像素电 极 ,所述控制晶体管的漏极电性连接于同一行的第 2n+2列像素的像素电极； 所述配置在同一行的控制晶体管的栅极与某一条控制信号端公共连接； 配置在同一行的像素中像素晶体管的第一栅极与某一条栅极线公共连 接；配置在同一列的像素中像素晶体管的第一源极与某一条数据线公共连 接；所述像素晶体管的第一漏极电性连接于像素电极；所述存储电容的上 极板与液晶电容的上极板连接后电性连接于像素电极，所述存储电容的下 极板电性连接于公共电极，所述液晶电容的下极板电性连接于公共电极。
11、 如权利要求 10所述的使用该 3D显示的像素插黑方法的电路，其 中，所述控制晶体管与像素晶体管均为薄膜晶体管。
12、 如权利要求 10所述的使用该 3D显示的像素插黑方法的电路，其 中，所述每一像素的极性与与其相邻的上下左右的像素的极性都是相反的。
13、一种使用如权利要求 1所述的 3D显示的像素插黑方法的电路，包 括：提供数据信号的数个数据线、 提供扫描信号的数个栅极线、 数个控制 信号端、 公共电极、 由数据线与栅极线限定的数个像素、 及数个控制晶体 管；所述每一个像素连接一条数据线与一条栅极线；
所述控制晶体管包括栅极、 源极、 漏极；所述像素分为两个区，即上 半部分的分区与下半部分的分区；所述上半部分的分区中的第一像素电极 与下半部分的分区中的第二像素电极的极性相同；所述上半部分的分区包 括第一像素晶体管与第一像素电极，所述下半部分的分区包括第二像素晶 体管与第二像素电极；所述第一像素晶体管包括栅极、 源极、 漏极，所述 第二像素晶体管包括栅极、 源极、 漏极；所述第一像素晶体管的漏极电性 连接于第一像素电极，所述第二像素晶体管的漏极电性连接于第二像素电 极；
配置于同一行的像素中第一像素晶体管的栅极与第二像素晶体管的栅 极与某一条栅极线公共连接，配置在第 m行的像素中第一像素晶体管的源 极与第二像素晶体管的源极与某一条数据线公共连接，配置在第 m+1行的 像素中第一像素晶体管的源极与第二像素晶体管的源极与另一条数据线公 共连接；
配置在同一列的第 m行像素的下半部分的分区与第 m+1行像素的上半 部分的分区通过一个控制晶体管连接；所述控制晶体管的源极电性连接于 同一列的第 m行像素下半部分的分区的像素电极，所述控制晶体管的漏极 电性连接于同一列的第 m+1行像素上半部分的分区的像素电极；配置在同 一行的控制晶体管的栅极与某一条控制信号端公共连接。
14、 如权利要求 13所述的使用该 3D显示的像素插黑方法的电路，其 中，所述控制晶体管、 第一像素晶体管、 及第二像素晶体管均为薄膜晶体 管。
15、 如权利要求 13所述的使用该 3D显示的像素插黑方法的电路，其 中，所述每一像素的极性与与其相邻的上下左右的像素的极性都是相反的。
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