WO2015182257A1 - Flow rate sensor and method for manufacturing same - Google Patents

Flow rate sensor and method for manufacturing same Download PDF

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Publication number
WO2015182257A1
WO2015182257A1 PCT/JP2015/061031 JP2015061031W WO2015182257A1 WO 2015182257 A1 WO2015182257 A1 WO 2015182257A1 JP 2015061031 W JP2015061031 W JP 2015061031W WO 2015182257 A1 WO2015182257 A1 WO 2015182257A1
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WIPO (PCT)
Prior art keywords
insulating film
insulator
insulator part
region
thickness
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PCT/JP2015/061031
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French (fr)
Japanese (ja)
Inventor
佐久間　憲之
保夫 小野瀬
良介 土井
忍 田代
Original Assignee
日立オートモティブシステムズ株式会社
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Publication of WO2015182257A1 publication Critical patent/WO2015182257A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01F—MEASURING VOLUME, VOLUME FLOW, MASS FLOW OR LIQUID LEVEL; METERING BY VOLUME
    • G01F1/00—Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow
    • G01F1/68—Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow by using thermal effects
    • G01F1/684—Structural arrangements; Mounting of elements, e.g. in relation to fluid flow
    • G01F1/688—Structural arrangements; Mounting of elements, e.g. in relation to fluid flow using a particular type of heating, cooling or sensing element
    • G01F1/69—Structural arrangements; Mounting of elements, e.g. in relation to fluid flow using a particular type of heating, cooling or sensing element of resistive type
    • G01F1/692—Thin-film arrangements

Definitions

  • the present invention relates to a flow rate sensor, and relates to a flow rate sensor using a heating resistor.
  • thermal fluid flow sensors manufactured by micro electro mechanical systems (MEMS) technology using semiconductors that is, air flow sensors, can reduce manufacturing costs and can be driven with low power. It has been.
  • MEMS micro electro mechanical systems
  • a flow rate detection unit that includes a heating resistor and detects a flow rate of fluid
  • a control circuit unit that includes a circuit including a transistor and the like and controls the flow rate detection unit
  • a flow sensor that is a thermal fluid flow sensor
  • a flow rate detection unit and a control circuit unit are formed on the same substrate.
  • Patent Document 1 discloses a micromechanical flow sensor in which a measurement element and a circuit are integrated on a semiconductor substrate, and the measurement element is a film on an opening or a recess of the semiconductor substrate. The technology provided above is disclosed.
  • Patent Document 2 discloses that in a thermal sensor, a detection unit provided on a first laminated film provided above a semiconductor substrate, including a heating resistor, and a semiconductor substrate. There is disclosed a technology including a circuit unit that is provided and has a control circuit that controls a heating resistor.
  • the flow rate detection unit may have compressive stress. In such a case, the flow rate detection unit is easily bent, and thus the flow rate detection unit may be damaged.
  • the control circuit unit may have tensile stress. In such a case, the characteristics of the control circuit unit may vary due to variations in transistor characteristics of the transistors included in the control circuit unit or resistance characteristics of the wiring.
  • the present invention has a flow rate detection unit and a control circuit unit that are formed on the same substrate, and prevents the flow rate detection unit from being damaged and can prevent fluctuations in the characteristics of the control circuit unit. I will provide a.
  • a flow sensor is formed on a first main surface of a semiconductor substrate in a first region of the first main surface of the semiconductor substrate, and includes a flow rate detection unit that detects a flow rate of fluid, And a control circuit unit that is formed on the first main surface of the semiconductor substrate in the second region of the first main surface and controls the flow rate detection unit.
  • the flow rate detection unit includes a first insulator portion formed on the first main surface of the semiconductor substrate, a heating resistor formed so as to be in contact with the first insulator portion, and a first insulation in the first region. And a second insulator part formed on the body part.
  • the control circuit section includes a third insulator section formed on the first main surface of the semiconductor substrate in the second region, a circuit formed in the third insulator section for controlling the heating resistor, and a third insulation section. And a fourth insulator portion formed on the body portion.
  • the first insulator portion and the third insulator portion are made of silicon oxide, and the second insulator portion and the fourth insulator portion are made of silicon nitride.
  • the ratio of the thickness of the second insulator part to the thickness of the first insulator part is larger than the ratio of the thickness of the fourth insulator part to the thickness of the third insulator part.
  • the flow rate sensor manufacturing method forms a flow rate detection unit for detecting the flow rate of the fluid on the first main surface of the semiconductor substrate in the first region of the first main surface of the semiconductor substrate. And a step of forming a control circuit unit for controlling the flow rate detection unit on the first main surface of the semiconductor substrate in the second region of the first main surface of the semiconductor substrate.
  • the step of forming the flow rate detection unit includes the step of forming the first insulator portion on the first main surface of the semiconductor substrate, and the heating resistor so as to be in contact with the first insulator portion. And forming a second insulator part on the first insulator part.
  • the step of forming the control circuit portion includes a step of forming a third insulator portion on the first main surface of the semiconductor substrate in the second region, and a circuit for controlling the heating resistor in the third insulator portion. And forming a fourth insulator part on the third insulator part.
  • the first insulator portion and the third insulator portion are made of silicon oxide, and the second insulator portion and the fourth insulator portion are made of silicon nitride.
  • the ratio of the thickness of the second insulator part to the thickness of the first insulator part is larger than the ratio of the thickness of the fourth insulator part to the thickness of the third insulator part.
  • the flow rate detection unit is prevented from being damaged, and fluctuations in the characteristics of the control circuit unit are prevented. can do.
  • FIG. 3 is a plan view of a principal part showing an example of a flow sensor according to the first embodiment.
  • FIG. 3 is a cross-sectional view of a main part of the flow sensor according to the first embodiment.
  • 3 is a cross-sectional view of a main part of a sensor chip in the flow sensor according to Embodiment 1.
  • FIG. FIG. 3 is a schematic layout diagram of an air flow meter on which the flow sensor according to the first embodiment is mounted.
  • FIG. 6 is a manufacturing process flow chart showing a part of the manufacturing process of the flow sensor according to the first embodiment.
  • FIG. 3 is a cross-sectional view of a main part during the manufacturing process of the flow sensor according to the first embodiment.
  • FIG. 3 is a cross-sectional view of a main part during the manufacturing process of the flow sensor according to the first embodiment.
  • FIG. 3 is a cross-sectional view of a main part during the manufacturing process of the flow sensor according to the first embodiment.
  • FIG. 3 is a cross-sectional view of a main part during the manufacturing process of the flow sensor according to the first embodiment.
  • FIG. 3 is a cross-sectional view of a main part during the manufacturing process of the flow sensor according to the first embodiment.
  • FIG. 3 is a cross-sectional view of a main part during the manufacturing process of the flow sensor according to the first embodiment.
  • FIG. 3 is a cross-sectional view of a main part during the manufacturing process of the flow sensor according to the first embodiment.
  • FIG. 3 is a cross-sectional view of a main part during the manufacturing process of the flow sensor according to the first embodiment.
  • FIG. 3 is a cross-sectional view of a main part during the manufacturing process of the flow sensor according to the first embodiment.
  • FIG. 3 is a cross-sectional view of a main part during the manufacturing process of the flow sensor according to the first embodiment.
  • FIG. 6 is a cross-sectional view of a main part of a sensor chip in a flow sensor according to a second embodiment.
  • FIG. 10 is a manufacturing process flow chart showing a part of the manufacturing process of the flow sensor according to the second embodiment.
  • FIG. 10 is a cross-sectional view of a main part during the manufacturing process of the flow sensor according to the second embodiment.
  • FIG. 10 is a cross-sectional view of a main part during the manufacturing process of the flow sensor according to the second embodiment.
  • FIG. 10 is a cross-sectional view of a main part during the manufacturing process of the flow sensor according to the second embodiment.
  • FIG. 10 is a cross-sectional view of a main part of a sensor chip in a flow sensor according to a third embodiment.
  • FIG. 10 is a manufacturing process flow chart showing a part of the manufacturing process of the flow sensor according to the third embodiment.
  • FIG. 10 is a cross-sectional view of a main part during the manufacturing process of the flow sensor according to the third embodiment.
  • FIG. 10 is a cross-sectional view of a main part during the manufacturing process of the flow sensor according to the third embodiment.
  • the constituent elements are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.
  • the shapes, positional relationships, etc. of the components, etc. when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.
  • hatching may be omitted even in a cross-sectional view for easy viewing of the drawings. Further, even a plan view may be hatched to make the drawing easy to see.
  • the flow rate sensor of the present embodiment is a thermal fluid flow rate sensor that detects the flow rate of fluid using a heating resistor.
  • FIG. 1 is a main part plan view showing an example of a flow sensor according to the first embodiment.
  • FIG. 2 is a cross-sectional view of a main part of the flow sensor according to the first embodiment.
  • the flow sensor 1 has a lead frame 2, a sensor chip 3, a bonding wire 4, and a mold resin 5.
  • the lead frame 2 has a mounting portion 2a and an external terminal 2b.
  • a sensor chip 3 is mounted on the mounting portion 2a.
  • the external terminal 2 b is electrically connected to the sensor chip 3 by a bonding wire 4.
  • the lead frame 2 including the mounting portion 2a and the external terminal 2b is made of copper (Cu) or a copper (Cu) alloy.
  • the sensor chip 3 includes a semiconductor substrate 6, a flow rate detection unit 7, and a control circuit unit 8.
  • the semiconductor substrate 6 has a surface 6a as one main surface and a back surface 6b as the other main surface opposite to the surface 6a.
  • the semiconductor substrate 6 is made of, for example, single crystal silicon (Si).
  • the semiconductor substrate 6 is mounted on the mounting portion 2 a with the back surface 6 b of the semiconductor substrate 6 facing the mounting portion 2 a of the lead frame 2.
  • an insulating film 11 as an element isolation film made of, for example, silicon oxide is formed on the surface 6a of the semiconductor substrate 6. Yes.
  • An interlayer insulating film 12 made of, for example, silicon oxide is formed on the insulating film 11 in the regions AR1 and AR2.
  • An interlayer insulating film 13 made of, for example, silicon oxide is formed on the interlayer insulating film 12 in the regions AR1 and AR2.
  • An interlayer insulating film 14 made of, for example, silicon oxide is formed on the interlayer insulating film 13 in the regions AR1 and AR2.
  • an insulating film 15 made of, for example, silicon nitride is formed on the interlayer insulating film.
  • an insulating film 16 made of, for example, silicon oxide is formed on the insulating film 15.
  • the area AR2 may be arranged on one side of the area AR1, may be arranged on both sides including the one side and the other side of the area AR1, and the outer periphery of the area AR1. May be arranged so as to surround. Further, in the present specification, in the plan view, the term “when viewed from a direction perpendicular to the surface 6 a of the semiconductor substrate 6” is meant.
  • the flow rate detector 7 is formed on the surface 6a of the semiconductor substrate 6 in the area AR1 of the surface 6a of the semiconductor substrate 6, and detects the flow rate of fluid such as air.
  • the flow rate detection unit 7 includes an insulator part IP1, a heating resistor 17, and an insulator part IP2.
  • the insulator portion IP1 is formed on the surface 6a of the semiconductor substrate 6 in the region AR1.
  • the insulator part IP1 includes, for example, an insulating film 11a, an interlayer insulating film 12a, and an interlayer insulating film 13a.
  • the insulating film 11a is the region AR1 and is formed of a portion of the insulating film 11 formed on the surface 6a of the semiconductor substrate 6.
  • the interlayer insulating film 12a includes a portion of the interlayer insulating film 12 formed on the insulating film 11a.
  • the interlayer insulating film 13a is composed of a portion of the interlayer insulating film 13 formed on the interlayer insulating film 12a.
  • the heating resistor 17 is formed in contact with the insulator part IP1.
  • the heating resistor 17 heats the insulator part IP1 to a temperature higher than room temperature when the heating resistor 17 generates heat. Therefore, the heating resistor 17 may be formed only in thermal contact with the insulator part IP1.
  • the heating resistor 17 is made of, for example, polycrystalline silicon and is formed on the insulating film 11.
  • the interlayer insulating film 12 is formed on the insulating film 11 so as to cover the heating resistor 17. Yes. That is, the heating resistor 17 made of, for example, polycrystalline silicon is made of a conductive film 27a formed in the same layer as the conductive film 27a of the gate electrode 27 made of, for example, polycrystalline silicon in the control circuit unit 8 to be described later. Thereby, the heating resistor 17 and the gate electrode 27 can be formed by the same process.
  • the flow volume detection part 7 may have the upstream temperature sensing resistor 18 and the downstream temperature sensing resistor 19.
  • the upstream resistance temperature detector 18 and the downstream resistance temperature detector 19 are also formed so as to be in contact with the insulator part IP1 in the region AR1.
  • the upstream resistance temperature detector 18 and the downstream resistance temperature detector 19 are made of, for example, polycrystalline silicon and are formed on the insulating film 11, and the interlayer insulating film 12 is the upstream resistance temperature detector. 18 and the downstream resistance temperature detector 19 are formed on the insulating film 11.
  • the insulating film 16, the insulating film 15, and the interlayer insulating film 14 are formed with an opening OP1 that penetrates the insulating film 16, the insulating film 15, and the interlayer insulating film 14 and reaches the interlayer insulating film 13.
  • the insulator part IP1 is formed in the area AR1. That is, the insulator part IP1 is disposed in the region where the opening OP1 is formed. Therefore, the insulating film 11a is composed of a portion of the insulating film 11 located in the region where the opening OP1 is formed in plan view.
  • the interlayer insulating film 12a is composed of a portion of the interlayer insulating film 12 located in a region where the opening OP1 is formed in plan view.
  • the interlayer insulating film 13a is composed of a portion of the interlayer insulating film 13 located in a region where the opening OP1 is formed in plan view. In other words, the interlayer insulating film 13a includes the portion of the interlayer insulating film 13 exposed at the bottom of the opening OP1.
  • an insulating film 20 made of, for example, silicon nitride is formed on the inner wall of the opening OP1.
  • the insulator part IP2 is formed on the insulator part IP1 in the area AR1.
  • the insulator part IP2 includes an insulating film 20.
  • the insulating film 20 is formed on the interlayer insulating film 13a in the region AR1.
  • the sensor chip 3 has a hole TH1.
  • the hole TH1 reaches the insulator part IP1, that is, the flow rate detection part 7 through the semiconductor substrate 6 from the back surface 6b of the semiconductor substrate 6 in the region AR1.
  • a diaphragm structure DF1 composed of an insulator part IP1 and an insulator part IP2 is formed as an upper bottom part of the hole part TH1, and the flow rate detection part 7 is made of this diaphragm structure DF1.
  • the control circuit unit 8 is formed on the surface 6a of the semiconductor substrate 6 in the area AR2 of the surface 6a of the semiconductor substrate 6, and controls the flow rate detection unit 7.
  • the control circuit unit 8 includes an insulator part IP3, a control circuit CR1, and an insulator part IP4.
  • the insulator portion IP3 is formed on the surface 6a of the semiconductor substrate 6 in the region AR2.
  • the insulator part IP3 includes, for example, an insulating film 11b, an interlayer insulating film 12b, an interlayer insulating film 13b, and an interlayer insulating film 14b.
  • the insulating film 11b is formed of a portion of the insulating film 11 formed on the surface 6a of the semiconductor substrate 6 in the region AR2. That is, the insulating film 11b is formed in the same layer as the insulating film 11a.
  • the interlayer insulating film 12b includes a portion of the interlayer insulating film 12 formed on the insulating film 11b. That is, the interlayer insulating film 12b is formed in the same layer as the interlayer insulating film 12a.
  • the interlayer insulating film 13b includes a portion of the interlayer insulating film 13 formed on the interlayer insulating film 12b. That is, the interlayer insulating film 13b is formed in the same layer as the interlayer insulating film 13a. Therefore, the insulator part IP3 is formed in the same layer as the insulator part IP1.
  • the interlayer insulating film 14b is composed of a portion of the interlayer insulating film 14 formed on the interlayer insulating film 13b.
  • the insulating film 11b may not be formed in the same layer as the insulating film 11a
  • the interlayer insulating film 12b may not be formed in the same layer as the interlayer insulating film 12a
  • the interlayer insulating film 13b It may not be formed in the same layer as the interlayer insulating film 13a. That is, the insulator part IP3 may not be formed in the same layer as the insulator part IP1.
  • the control circuit CR1 is formed in the region AR2 so as to be covered with the insulator part IP3 or in the insulator part IP3.
  • the control circuit CR1 includes, for example, a transistor Tr, a plug 21, a wiring 22, a plug 23, and a wiring 24.
  • the transistor Tr is a region partitioned by an insulating film 11b as an element isolation film, and is formed of a MISFET (Metal Insulator Semiconductor Semiconductor Field Effect Transistor) formed on the surface 6a of the semiconductor substrate 6.
  • the transistor Tr includes a diffusion layer 25, a gate insulating film 26, a gate electrode 27, and a diffusion layer 28.
  • the diffusion layer 25 is formed on the surface 6 a side of the semiconductor substrate 6.
  • the gate insulating film 26 is formed on the diffusion layer 25.
  • the gate insulating film 26 is made of, for example, silicon oxide.
  • the gate electrode 27 is formed on the gate insulating film 26.
  • the gate electrode 27 is made of, for example, polycrystalline silicon.
  • the diffusion layer 28 is formed in alignment with the gate electrode 27 in the upper layer portion of the diffusion layer 25 located on both sides of the gate electrode 27.
  • the diffusion layer 28 functions as a source region or a drain region.
  • the diffusion layer 25 is made of silicon into which a p-type impurity such as boron (B) or an n-type impurity such as phosphorus (P) or arsenic (As) is introduced.
  • the diffusion layer 28 is made of silicon having a conductivity type opposite to the conductivity type of the diffusion layer 25 by introducing an n-type impurity such as phosphorus (P) or arsenic (As) or a p-type impurity such as boron (B). .
  • the plug 21 penetrates the interlayer insulating film 12b and is electrically connected to the diffusion layer 28 of the transistor Tr, for example.
  • the wiring 22 is formed on the interlayer insulating film 12 b and is electrically connected to the plug 21.
  • the interlayer insulating film 13 b is formed on the interlayer insulating film 12 b so as to cover the wiring 22.
  • the plug 23 penetrates the interlayer insulating film 13b and is electrically connected to the wiring 22.
  • the wiring 24 is formed on the interlayer insulating film 13 b and is electrically connected to the plug 23.
  • the interlayer insulating film 14 b is formed on the interlayer insulating film 13 b so as to cover the wiring 24.
  • the plug 21 and the plug 23 are made of, for example, a laminated film of a titanium nitride (TiN) film and a tungsten (W) film.
  • the wiring 22 and the wiring 24 are made of, for example, an aluminum (Al) alloy film.
  • the thickness of the wiring 22 and the wiring 24 can be set to, for example, about 400 to 800 nm.
  • the wiring 22a illustrated in FIG. 3 electrically connects the heating resistor 17 and the control circuit CR1.
  • the insulator part IP4 is formed on the insulator part IP3 in the area AR2.
  • the insulator part IP4 includes an insulating film 15b.
  • the insulating film 15b is made of the portion of the insulating film 15 formed on the interlayer insulating film 14b in the region AR2, and the portion of the insulating film 15 formed on the insulator portion IP3 in the region AR2.
  • the sensor chip 3 has an electrode pad 29 as an electrode.
  • the electrode pad 29 is formed in the same layer as the wiring 24 on the interlayer insulating film 13b in the region AR2.
  • the electrode pad 29 is electrically connected to the control circuit CR1 of the control circuit unit 8 by being electrically connected to the plug 23, for example.
  • the electrode pad 29 is made of, for example, an aluminum (Al) alloy film.
  • the insulating film 16, the insulating film 15, and the interlayer insulating film 14 are formed with an opening OP2 that penetrates the insulating film 16, the insulating film 15, and the interlayer insulating film 14 and reaches the electrode pad 29. That is, the opening OP ⁇ b> 2 passes through the insulator part IP ⁇ b> 4 and a part of the insulator part IP ⁇ b> 3 located on the electrode pad 29 and reaches the electrode pad 29. The electrode pad 29 is exposed at the bottom of the opening OP2.
  • the bonding wire 4 connects the electrode pad 29 and the external terminal 2 b of the lead frame 2.
  • the external terminal 2 b of the lead frame 2 is electrically connected to the outside of the flow sensor 1. Therefore, the electrode pad 29 is electrically connected to the outside of the flow sensor 1 through the bonding wire 4 and the external terminal 2 b of the lead frame 2.
  • the sensor chip 3 electrically connected to the lead frame 2 and the lead frame 2 are sealed by a resin mold using a mold resin 5 as a resin portion.
  • a hole TH2 is formed in a portion of the lead frame 2 that is disposed so as to overlap the hole TH1, that is, the mounting portion 2a, and the hole TH1 is formed via the hole TH2. It communicates with the outside of the flow sensor 1.
  • a mold resin 5 is formed so as to cover the surface of the sensor chip 3.
  • the mold resin 5 is formed on the insulating film 16. That is, in the region AR2, the mold resin 5 is formed on the insulator part IP4 via the insulating film 16, and is formed so as to cover the insulating film 16 and the insulator part IP4.
  • the thickness TP1 of the insulator part IP1 is smaller than the thickness TP3 of the insulator part IP3 formed in the same layer as the insulator part IP1, and the opening OP1 is formed in the region AR1.
  • the opening OP1 is not formed in the area outside the area AR1 including the area AR2.
  • the insulating film 20 is formed outside the region AR1 and on the end of the insulating film 15 on the region AR1 side via the insulating film 16. That is, the insulator part IP2 is continuously formed directly or via the insulating film 16 from the insulator part IP1 to the end of the insulator part IP4 on the region AR1 side.
  • the air flow path convex portion 54 (see FIG. 14 described later) of the molding die 51 (see FIG. 14 described later) is used as a sensor.
  • the air flow path convex portion 54 can be prevented from contacting the flow rate detection unit 7.
  • the hole TH1 is formed in the area AR1, that is, in the area where the insulator part IP1 is formed in a plan view, the end of the insulator part IP1 on the area AR2 side is the hole TH1. Therefore, the effect of preventing the contact is increased.
  • the end of the mold resin 5 on the region AR1 side is preferably on the insulator part IP4. Is located on the insulator part IP2 of the part formed through the insulating film 16. In such a case, the portion of the insulating film 16 and the insulator portion IP3 exposed from the insulator portion IP4 are further covered with the mold resin 5, so that the control circuit CR1 This has the effect of preventing corrosion of the wiring 24 and the like.
  • the groove part TR1 is formed on the surface of the mold resin 5 covering the sensor chip 3, and the flow rate detection part 7 is exposed.
  • the flow rate sensor 1 measures the temperature change when the temperature of the insulator part IP1 heated to a temperature higher than room temperature changes according to the flow rate of fluid such as air flowing in the groove part TR1 in the direction DR1 (see FIG. 1). The flow rate of the fluid is detected by measuring.
  • the mold resin 5 is formed so as to cover the back surface of the sensor chip 3 and the lead frame 2 in the area AR2 in plan view. Further, in a plan view, a groove portion TR2 is formed in the mold resin 5 that covers the back surface of the sensor chip 3 and the lead frame 2 in the area AR1, and the hole portion TH1 is formed in the upper bottom portion of the trench portion TR2 in the plan view.
  • the portion of the mounting portion 2a that is arranged so as to overlap with is exposed.
  • the hole portion TH2 is formed in the portion of the mounting portion 2a disposed so as to overlap the hole portion TH1 in plan view, and the hole portion TH1 is connected to the flow rate sensor via the hole portion TH2. 1 communicates with the outside.
  • the ratio of the thickness TP2 of the insulator part IP2 to the thickness TP1 of the insulator part IP1 is larger than the ratio of the thickness TP4 of the insulator part IP4 to the thickness TP3 of the insulator part IP3.
  • the insulator part IP2 can be adjusted to have a tensile stress.
  • the insulator part IP4 has a tensile stress smaller than the tensile stress of the insulator part IP2 by adjusting the film formation conditions when forming the insulator part IP4 made of, for example, silicon nitride, or Can be adjusted to have a compressive stress.
  • the insulator part IP1 has a tensile stress smaller than the tensile stress of the insulator part IP2, or It can be adjusted to have a compressive stress.
  • the insulator part IP3 has a tensile stress smaller than the tensile stress of the insulator part IP2, for example, by adjusting the film formation conditions when forming the insulator part IP3 made of silicon oxide, or It can be adjusted to have a compressive stress.
  • the ratio of the thickness TP2 of the insulator part IP2 to the thickness TP1 of the insulator part IP1 is larger than the ratio of the thickness TP4 of the insulator part IP4 to the thickness TP3 of the insulator part IP3, for example It can adjust so that the laminated body of insulator part IP3 and insulator part IP4 may have a tensile stress. Further, for example, the laminate of the insulator part IP3 and the insulator part IP4 has a tensile stress smaller than the tensile stress of the laminate of the insulator part IP1 and the insulator part IP2, or has a compressive stress. Can be adjusted.
  • the flow volume detection part 7 can be adjusted so that it may have a tensile stress. Or it can adjust so that the control circuit part 8 may have a tensile stress smaller than the tensile stress of the flow volume detection part 7, or may have a compressive stress.
  • the insulator part IP2 has a tensile stress.
  • Insulator part IP1, insulator part IP3, and insulator part IP4 have a tensile stress smaller than the tensile stress of insulator part IP2, or have a compressive stress.
  • the thickness TP2 of the insulator part IP2 is thicker than the thickness TP4 of the insulator part IP4.
  • the ratio of the thickness TP2 of the insulator part IP2 to the thickness TP1 of the insulator part IP1 is easily made larger than the ratio of the thickness TP4 of the insulator part IP4 to the thickness TP3 of the insulator part IP3. be able to.
  • the sum of the thickness TP1 of the insulator part IP1 and the thickness TP2 of the insulator part IP2 is greater than the sum of the thickness TP3 of the insulator part IP3 and the thickness TP4 of the insulator part IP4. small.
  • at least the thickness TP1 of the insulator part IP1 can be made thinner than the thickness TP3 of the insulator part IP3 formed in the same layer as the insulator part IP1.
  • the thickness TP3 of the insulator portion IP3 in the region partitioned by the insulating film 11b as the element isolation film is the thickness TP31
  • the thickness TP1 of the insulator portion IP1 is more preferable.
  • the ratio of the thickness TP2 of the insulator part IP2 to the thickness is larger than the ratio of the thickness TP4 of the insulator part IP4 to the thickness TP31 of the insulator part IP3.
  • the flow volume detection part 7 can be adjusted further easily so that it may have a tensile stress.
  • the control circuit unit 8 can be adjusted more easily so as to have a tensile stress smaller than the tensile stress of the flow rate detection unit 7 or a compressive stress.
  • the insulating film 16 since the thickness of the insulating film 16 is smaller than the thickness TP3 of the insulator part IP3 and the thickness TP4 of the insulator part IP4, the insulating film 16 has a compressive stress. Even in this case, the influence of the compressive stress of the insulating film 16 is small.
  • FIG. 4 is a schematic layout diagram of an air flow meter in which the flow sensor of the first embodiment is mounted.
  • FIG. 4 shows an arrangement when the flow sensor of the first embodiment is attached to an air passage as an intake passage of an internal combustion engine such as an automobile.
  • the air flow meter 31 includes a flow sensor 1, a support body 32, and a connecting portion 33.
  • the support 32 supports the flow sensor 1.
  • the connecting portion 33 electrically connects the external terminal 2 b of the lead frame 2 of the flow sensor 1 to the outside via the support body 32.
  • the flow sensor 1 is disposed in a sub-passage 35 provided in the air passage 34.
  • the intake air flows in the direction DR1 of the air flow indicated by the arrow in FIG. 4 or in the opposite direction depending on the conditions of the internal combustion engine.
  • FIG. 5 is a manufacturing process flow chart showing a part of the manufacturing process of the flow sensor according to the first embodiment.
  • 6 to 14 are cross-sectional views of relevant parts during the manufacturing process of the flow sensor according to the first embodiment.
  • the semiconductor substrate 6 is prepared (step S11 in FIG. 5).
  • a semiconductor substrate 6 having a front surface 6a as one main surface and a back surface 6b as the other main surface opposite to the front surface 6a is prepared.
  • the semiconductor substrate 6 is made of single crystal silicon (Si).
  • step S12 the insulator part IP1 and the insulator part IP3 are formed (step S12 in FIG. 5).
  • the insulator portion IP1 is formed on the surface 6a of the semiconductor substrate 6 in the region AR1 of the surface 6a of the semiconductor substrate 6, and the surface 6a of the semiconductor substrate 6 is formed.
  • the insulator part IP3 is formed on the surface 6a of the semiconductor substrate 6 in the same layer as the insulator part IP1.
  • the heating resistor 17 is formed so as to be in contact with the insulator part IP1, and the control circuit CR1 for controlling the heating resistor 17 is formed in the insulator part IP3.
  • the insulator part IP3 may not be formed in the same layer as the insulator part IP1.
  • an insulating film 41 made of silicon oxide is formed as an element isolation film on the surface 6a of the semiconductor substrate 6 in the regions AR1 and AR2.
  • the semiconductor substrate 6 is thermally oxidized in a high-temperature furnace to form the insulating film 41 made of silicon oxide on the surface 6a of the semiconductor substrate 6 in the regions AR1 and AR2. At this time, an insulating film 41 made of silicon oxide is also formed on the back surface 6 b of the semiconductor substrate 6.
  • an insulating film 42 made of silicon nitride is formed by low-pressure thermal CVD (Chemical Vapor Deposition) so as to cover the insulating film 41 formed on the surface 6a of the semiconductor substrate 6 in the regions AR1 and AR2. To do. At this time, the insulating film 42 made of silicon nitride is also formed on the back surface 6 b of the semiconductor substrate 6 so as to cover the insulating film 41.
  • the insulating film 42 and the insulating film 41 are patterned by using a photolithography method. Thereby, the insulating film 42 and the insulating film 41 formed on the surface 6a of the semiconductor substrate 6 are left in a part of the region AR2, and the other part of the region AR2 and the surface AR of the semiconductor substrate 6 in the region AR1. The formed insulating film 42 and insulating film 41 are removed. Next, by subjecting the semiconductor substrate 6 to thermal oxidation in a high temperature furnace body, the other part of the region AR2 and the part of the semiconductor substrate in which the insulating film 42 and the insulating film 41 are removed in the region AR1.
  • An insulating film 11 made of silicon oxide is formed on the surface 6a of 6 as an element isolation film.
  • the insulating film 11 has a compressive stress.
  • the insulating film 11 is thicker than the insulating film 41, for example.
  • the thickness of the insulating film 11 is, for example, about 200 to 500 nm. Further, the insulating film 11 can be a film having a compressive stress of about 100 MPa, for example.
  • the insulating film 11 is not formed on the front surface 6 a and the back surface 6 b of the semiconductor substrate 6 in a portion covered with the insulating film 42 and the insulating film 41. That is, the insulating film 42 and the insulating film 41 are used as a mask for selectively forming the insulating film 11 on the surface 6a of the semiconductor substrate 6 in the other part of the region AR2 and the region AR1.
  • the portion of the insulating film 11 formed on the surface 6a of the semiconductor substrate 6 in the region AR1 is referred to as an insulating film 11a, and the portion of the insulating film 11 formed on the surface 6a of the semiconductor substrate 6 in the region AR2. Is referred to as an insulating film 11b.
  • the heating resistor 17 is formed on the insulating film 11 so as to overlap the region AR1 in plan view, and the transistor Tr is formed in the region AR2.
  • the insulating film 42 and the insulating film 41 used as a mask for forming the insulating film 11 are removed.
  • a p-type impurity such as boron (B) or an n-type impurity such as phosphorus (P) or arsenic (As) is introduced into the surface 6a of the semiconductor substrate 6 in the region AR2.
  • the diffusion layer 25 is formed on the surface 6a of the semiconductor substrate 6 in a part of the region AR2 where the insulating film 11 is not formed.
  • the diffusion layer 25 is made of silicon having p-type or n-type conductivity.
  • the semiconductor substrate 6 is heat-treated in a high-temperature furnace to form an insulating film 26a made of silicon oxide on the diffusion layer 25 in the region AR2.
  • a conductor film 27a made of, for example, polycrystalline silicon is formed on the insulating film 11 and the insulating film 26a in the regions AR1 and AR2.
  • the conductor film 27a and the insulating film 26a are patterned using a photolithography method and a dry etching method.
  • the heating resistor 17 made of the conductor film 27a is formed so as to overlap the area AR1 in plan view, and the gate electrode 27 made of the conductor film 27a and the gate insulating film made of the insulating film 26a are formed in the area AR2. 26 is formed.
  • the heating resistor 17 forms a flow rate detector 7 (see FIG. 11 described later).
  • the thickness of the gate insulating film 26 varies depending on the resistance characteristics required for the heating resistor 17 included in the flow rate detection unit 7 and the transistor characteristics required for the transistor Tr included in the control circuit unit 8. For example, the thickness is about 5 to 50 nm, and the thicknesses of the gate electrode 27 and the heating resistor 17 are about 100 to 300 nm, for example.
  • phosphorus (P) or arsenic (As) is formed on the upper layer portion of the diffusion layer 25 located on both sides of the gate electrode 27 in the region AR ⁇ b> 2 by ion implantation.
  • N-type impurities or p-type impurities such as boron (B), that is, impurities having a conductivity type opposite to that of the diffusion layer 25 are introduced.
  • the diffusion layer 28 is formed on the surface 6a of the semiconductor substrate 6 in a part of the region AR2 where the insulating film 11 is not formed. That is, the diffusion layer 28 is formed in alignment with the gate electrode 27 in the upper layer portion of the diffusion layer 25 located on both sides of the gate electrode 27.
  • the diffusion layer 28 functions as a source region or a drain region.
  • the diffusion layer 28 is made of silicon having a conductivity type opposite to that of the diffusion layer 25.
  • a transistor Tr having the diffusion layer 25, the gate insulating film 26, the gate electrode 27, and the diffusion layer 28 is formed.
  • the transistor Tr forms a control circuit unit 8 (see FIG. 10 described later). In the example shown in FIG. 7, a plurality of transistors Tr are formed.
  • the impurity concentration of impurities introduced into the diffusion layer 25 or the diffusion layer 28, the thickness of the gate insulating film 26, and the material of the gate electrode 27 are changed.
  • the transistor manufacturing process described with reference to FIG. 7 is repeated. Thereby, a plurality of transistors Tr having different transistor characteristics can be formed.
  • an interlayer insulating film 12 is formed on the insulating film 11 or the surface 6a of the semiconductor substrate 6 in the regions AR1 and AR2, and the upper surface of the formed interlayer insulating film 12 is flattened. Turn into.
  • the interlayer insulating film 12 made of silicon oxide is formed by, for example, a plasma CVD method or a low temperature CVD method using plasma using TEOS (Tetra Ethoxy Silane) as a raw material. be able to.
  • TEOS Tetra Ethoxy Silane
  • an interlayer insulating film 12 containing boron (B) or phosphorus (P) can be formed as the interlayer insulating film 12.
  • the thickness of the interlayer insulating film 12 can be set to, for example, about 500 to 1000 nm.
  • the interlayer insulating film 12 can be a film having a compressive stress of about 100 MPa, for example.
  • the upper surface of the formed interlayer insulating film 12 can be planarized by a CMP (Chemical Mechanical Polishing) method or an etch back method.
  • CMP Chemical Mechanical Polishing
  • the interlayer insulating film 11a is covered with the interlayer insulating film 11a so as to cover a part of the heating resistor 17 in the area AR1 as shown in FIG.
  • An interlayer insulating film 12a made of the film 12 is formed.
  • an interlayer insulating film 12b made of the interlayer insulating film 12 is formed on the insulating film 11b in the same layer as the interlayer insulating film 12a so as to cover the other part of the heating resistor 17 in the region AR2.
  • an interlayer insulating film 12b made of the interlayer insulating film 12 is formed on the surface 6a of the semiconductor substrate 6 in the same layer as the interlayer insulating film 12a so as to cover the transistor Tr in the region AR2.
  • a plug 21 is formed.
  • the interlayer insulating film 12 penetrates the interlayer insulating film 12, and functions as the heating resistor 17, the gate electrode 27 of the transistor Tr, and the source region or the drain region.
  • a plurality of contact holes reaching each of the diffusion layers 28 are formed.
  • a titanium nitride (TiN) film is formed on the inner wall of each of the plurality of contact holes by sputtering or CVD.
  • a tungsten (W) film is formed so as to embed each of the plurality of contact holes.
  • each of the plurality of contact holes is filled with the metal film 21a made of, for example, a tungsten film and a titanium nitride film.
  • the metal film 21a made of, for example, a tungsten film and a titanium nitride film.
  • a portion of the metal film 21a located outside the contact hole is removed by an etch back method or a CMP method.
  • the interlayer insulating film 12 is made of the metal film 21a and penetrates the interlayer insulating film 12, and functions as the heating resistor 17, the gate electrode 27 of the transistor Tr, and the source region or the drain region. Plugs 21 reaching each of the diffusion layers 28 are formed.
  • the wiring 22 is formed.
  • a conductor film 22b made of, for example, an aluminum (Al) alloy film is formed on the interlayer insulating film 12 in the regions AR1 and AR2.
  • the thickness of the conductor film 22b can be set to, for example, about 400 to 800 nm.
  • the upper surface of the interlayer insulating film 12 may be sputter-etched with, for example, argon (Ar) gas.
  • Ar argon
  • a barrier metal film such as a titanium nitride film before forming an aluminum alloy film
  • a laminated film composed of two layers of a barrier metal film and an aluminum alloy film on the barrier metal film is formed.
  • the conductor film 22b may be formed.
  • another layer of a barrier metal film such as a titanium nitride film is formed on the aluminum alloy film to form a laminated film having three layers.
  • the conductor film 22b may be formed.
  • the thickness of the barrier metal film is preferably 200 nm or less.
  • a titanium nitride film is exemplified as the barrier metal film, a titanium tungsten (TiW) film, a titanium (Ti) film, or a stacked film of a titanium tungsten film and a titanium film can be used as the barrier metal film.
  • the heating resistor 17 is formed in the same layer as the gate electrode 27 and is made of polycrystalline silicon has been described as an example.
  • the heating resistor 17 may be formed in a layer different from the gate electrode 27, for example.
  • the heating resistor 17 has alpha tantalum ( ⁇ -Ta), titanium (Ti), tungsten (W), cobalt (Co), nickel (Ni), iron (Fe), niobium (Nb), hafnium (Hf). Further, it may be made of a metal film mainly composed of chromium (Cr) or zirconium (Zr). Alternatively, the heating resistor 17 may be made of a metal nitride compound such as tantalum nitride (TaN), molybdenum nitride (MoN), or tungsten nitride (WN). Alternatively, the heating resistor 17 may be made of a metal silicide compound such as molybdenum silicide (MoSi), cobalt silicide (CoSi), or nickel silicide (NiSi).
  • MoSi molybdenum silicide
  • CoSi cobalt silicide
  • NiSi nickel silicide
  • the conductive film 22b is patterned by using a photolithography method and a dry etching method or a wet etching method. As a result, as shown in FIG. 8, the wiring 22 made of the conductor film 22b is formed.
  • an interlayer insulating film 13 is formed on the interlayer insulating film 12 so as to cover the wiring 22 in the regions AR1 and AR2, and the upper surface of the formed interlayer insulating film 13 is flattened. Turn into.
  • the interlayer insulating film 13 made of silicon oxide is formed by, for example, plasma CVD or using TEOS as a raw material. It can be formed by a low temperature CVD method.
  • the thickness of the interlayer insulating film 13 can be set to, for example, about 500 to 1000 nm.
  • the interlayer insulating film 13 can be a film having a compressive stress of about 100 MPa, for example.
  • the upper surface of the formed interlayer insulating film 13 is subjected to the CMP method or the etch back method in the same manner as the step of planarizing the upper surface of the interlayer insulating film 12.
  • planarization can be performed.
  • an interlayer insulating film 13a made of the interlayer insulating film 13 is formed on the interlayer insulating film 12a in the region AR1, as shown in FIG.
  • an interlayer insulating film 13b made of the interlayer insulating film 13 is formed on the interlayer insulating film 12b in the same layer as the interlayer insulating film 13a so as to cover the wiring 22 in the region AR2.
  • a plug 23 is formed.
  • the plug 23 reaching the wiring 22 through the interlayer insulating film 13 is formed in the interlayer insulating film 13 in the region AR2.
  • the step of forming the plug 23 can be the same as the step of forming the plug 21.
  • the wiring 24 is formed.
  • the conductor film 24a made of, for example, an aluminum (Al) alloy film is formed on the interlayer insulating film 13 in the regions AR1 and AR2.
  • the conductor film 24a is patterned using a photolithography method and a dry etching method or a wet etching method.
  • the thickness of the conductor film 24a can be set to, for example, about 400 to 800 nm. As a result, as shown in FIG. 9, the wiring 24 made of the conductor film 24a is formed.
  • an electrode pad 29 made of the conductor film 24a is formed. Further, the control circuit CR1 including the transistor Tr, the plug 21, the wiring 22, the plug 23, and the wiring 24 is formed.
  • the interlayer insulating film 14 is formed on the interlayer insulating film 13 so as to cover the wiring 24 in the regions AR1 and AR2, and the upper surface of the formed interlayer insulating film 14 is flattened. Turn into.
  • the interlayer insulating film 14 made of silicon oxide is formed by, for example, plasma CVD or using TEOS as a raw material. It can be formed by a low temperature CVD method.
  • the thickness of the interlayer insulating film 14 can be set to, for example, about 300 to 1000 nm. Further, the interlayer insulating film 14 can be a film having a compressive stress of about 100 MPa, for example.
  • the upper surface of the formed interlayer insulating film 14 is subjected to the CMP method or the etch back method in the same manner as the step of flattening the upper surface of the interlayer insulating film 12.
  • planarization can be performed.
  • an interlayer insulating film 14a made of the interlayer insulating film 14 is formed on the interlayer insulating film 13a in the region AR1, as shown in FIG.
  • an interlayer insulating film 14b made of the interlayer insulating film 14 is formed in the same layer as the interlayer insulating film 14a on the interlayer insulating film 13b so as to cover the wiring 24 in the region AR2.
  • the insulating film 11a is the region AR1 and is formed of a portion of the insulating film 11 formed on the surface 6a of the semiconductor substrate 6.
  • the interlayer insulating film 12a includes a portion of the interlayer insulating film 12 formed on the insulating film 11a.
  • the interlayer insulating film 13a is composed of a portion of the interlayer insulating film 13 formed on the interlayer insulating film 12a.
  • the interlayer insulating film 14a includes a portion of the interlayer insulating film 14 formed on the interlayer insulating film 13a.
  • the insulator part IP3 including the insulating film 11b, the interlayer insulating film 12b, the interlayer insulating film 13b, and the interlayer insulating film 14b is formed.
  • the insulating film 11b is composed of a portion of the insulating film 11 formed on the surface 6a of the semiconductor substrate 6 in the region AR2.
  • the interlayer insulating film 12b includes a portion of the interlayer insulating film 12 formed on the insulating film 11b.
  • the interlayer insulating film 13b includes a portion of the interlayer insulating film 13 formed on the interlayer insulating film 12b.
  • the interlayer insulating film 14b includes a portion of the interlayer insulating film 14 formed on the interlayer insulating film 13b.
  • the insulating film 11b is formed in the same layer as the insulating film 11a.
  • the interlayer insulating film 12b is formed in the same layer as the interlayer insulating film 12a.
  • the interlayer insulating film 13b is formed in the same layer as the interlayer insulating film 13a. Therefore, the insulator part IP3 is formed in the same layer as the insulator part IP1.
  • the step of forming the insulator portion IP3 in the same layer as the insulator portion IP1 on the surface 6a of the semiconductor substrate 6 is performed in the region AR1 on the surface 6a of the semiconductor substrate 6 in the region AR1. You may carry out by the same process as the process of forming. Alternatively, the step of forming the insulator portion IP3 in the same layer as the insulator portion IP1 on the surface 6a of the semiconductor substrate 6 in the region AR2 is performed on the surface 6a of the semiconductor substrate 6 in the region AR1. You may perform by the process different from the process of forming.
  • the insulating film 15 is formed (step S13 in FIG. 5).
  • the insulating film 15 is formed on the insulator part IP1 and the insulator part IP3 in the area AR1 and the area AR2.
  • the insulating film 15 made of silicon nitride can be formed on the interlayer insulating film 14 by, for example, a low temperature CVD method using plasma.
  • the insulating film 15 is formed on the interlayer insulating film 14a in the region AR1, and is formed on the interlayer insulating film 14b in the region AR2.
  • the insulator part IP4 including the insulating film 15b is formed in the region AR2.
  • the insulating film 15b is composed of a portion of the insulating film 15 formed on the interlayer insulating film 14b, that is, on the insulator portion IP3.
  • the control circuit unit 8 including the insulator part IP3, the control circuit CR1, and the insulator part IP4 is formed on the surface 6a of the semiconductor substrate 6. That is, the process of forming the control circuit unit 8 includes a process of forming the insulator part IP3, a process of forming the control circuit CR1, and a process of forming the insulator part IP4.
  • the insulating film 15 is formed on the insulator portion IP1 in the same layer as the insulator portion IP4 including the insulating film 15b.
  • the insulating film 15 having a compressive stress of, for example, about 100 MPa can be formed by adjusting the bias voltage or the flow rate of the source gas and adjusting the film forming speed when forming the insulating film 15.
  • the thickness of the insulating film 15 can be set to about 600 to 1000 nm, for example.
  • the transistor Tr is prevented or suppressed from being damaged by the filler in the mold resin 5, and the wiring due to the stress of the mold resin 5 is prevented.
  • 24 or the wiring 22 can be prevented or suppressed from being damaged.
  • the insulating film 16 is formed (step S14 in FIG. 5).
  • the insulating film 16 is formed on the insulating film 15 in the regions AR1 and AR2.
  • the insulating film 16 made of silicon oxide can be formed by, for example, a plasma CVD method or a low temperature CVD method using TEOS as a raw material and plasma.
  • the insulating film 16 functions as an etching stopper for the insulating film 20 when the insulating film 20 made of silicon nitride is patterned by performing a process described with reference to FIG.
  • the thickness of the insulating film 16 can be set to about 100 to 500 nm, for example.
  • the opening OP1 is formed (step S15 in FIG. 5).
  • the insulating film 16, the insulating film 15, and the interlayer insulating film 14 are patterned in the area AR1 by using the photolithography method and the dry etching method.
  • the insulating film 16 is removed by etching.
  • the portion of the insulating film 15 from which the insulating film 16 has been removed is removed by etching.
  • the part of the interlayer insulating film 14 from which the insulating film 15 has been removed, that is, the interlayer insulating film 14a is removed by etching.
  • an opening OP1 that penetrates through the insulating film 16, the insulating film 15, and the interlayer insulating film 14 and reaches the interlayer insulating film 13 is formed in the region AR1.
  • the insulator part IP1 includes the insulating film 11a, the interlayer insulating film 12a, and the interlayer insulating film 13a, but does not include the interlayer insulating film 14a. Therefore, the thickness TP1 of the insulator part IP1 is thinner than the thickness TP3 of the insulator part IP3. Therefore, it can adjust so that the compressive stress of insulator part IP1 may become smaller than the compressive stress of insulator part IP2.
  • the insulating film 11a is composed of a portion of the insulating film 11 located in a region where the opening OP1 is formed in a plan view.
  • the interlayer insulating film 12a is composed of a portion of the interlayer insulating film 12 located in a region where the opening OP1 is formed in plan view.
  • the interlayer insulating film 13a is composed of a portion of the interlayer insulating film 13 located in a region where the opening OP1 is formed in plan view. In other words, the interlayer insulating film 13a includes the portion of the interlayer insulating film 13 exposed at the bottom of the opening OP1.
  • an opening OP2 that penetrates the insulating film 16, the insulating film 15, and the interlayer insulating film 14 and reaches the electrode pad 29 is formed in the region AR2.
  • the opening OP ⁇ b> 2 passes through the insulator part IP ⁇ b> 4 and the part of the insulator part IP ⁇ b> 3 located on the electrode pad 29 and reaches the electrode pad 29.
  • the electrode pad 29 is exposed at the bottom of the opening OP2.
  • the insulating film 20 is formed (step S16 in FIG. 5).
  • the insulating film 20 is formed on the insulator portion IP1 in the region AR1.
  • the insulating film 20 is formed on the insulator part IP1 and the insulating film 16 in the region AR1 and the region AR2.
  • the insulating film 20 made of silicon nitride can be formed on the insulator portion IP1 and the insulating film 16 by, for example, a low temperature CVD method using plasma.
  • the insulating film 20 is continuously formed from the portion of the insulator portion IP1 exposed at the bottom of the opening OP1 in the region AR1 to the insulating film 16 in the region AR2.
  • the insulating film 20 having a tensile stress of about 200 MPa can be formed by adjusting the bias voltage or the flow rate of the source gas and adjusting the film forming speed when forming the insulating film 20.
  • the thickness of the insulating film 20 can be set to about 800 to 2000 nm, for example.
  • the insulating film 20 is patterned in the region AR1 and the region AR2 by using a photolithography method and a dry etching method. As a result, the insulating film 20 in a portion formed on the insulator portion IP1 in the region AR1 and the end portion on the region AR1 side of the insulator portion IP4 in the region AR2 are formed via the insulating film 16. The remaining part of the insulating film 20 is left, and the other part of the insulating film 20 is removed.
  • the insulator portion IP2 including the insulating film 20 is formed in the region AR1.
  • the flow rate detection unit 7 including the insulator part IP1, the heating resistor 17, and the insulator part IP2 is formed on the surface 6a of the semiconductor substrate 6. That is, the process of forming the flow rate detection unit 7 includes a process of forming the insulator part IP1, a process of forming the heating resistor 17, and a process of forming the insulator part IP2.
  • the insulating film 20 is formed directly or continuously via the insulating film 16 over the insulator portion IP1 in the region AR1 and over the end of the insulator portion IP4 in the region AR2 on the region AR1 side.
  • the insulating film 15 made of silicon nitride is formed in the region AR1 and the region AR2, and then the insulating film 15 is removed and the insulating film 20 is formed in the region AR1, whereby the flow rate detector 7 and the control circuit are formed.
  • the insulator part IP2 or the insulator part IP4 made of silicon nitride is formed in any upper layer part of the part 8. Therefore, for example, the wiring 24 of the control circuit CR1 can be prevented or suppressed from corroding at the boundary between the flow rate detection unit 7 and the control circuit unit 8 or the like.
  • the insulating film 15 and the insulating film 16 are sequentially formed in the region AR1 and the region AR2, the insulating film 15 is removed and the insulating film 20 is formed in the region AR1, thereby forming the insulating film 20 in the region AR2. Since the insulating film 16 made of silicon oxide functions as an etching stopper when the insulating film 20 is etched, the processing accuracy can be improved.
  • the insulator part IP2 By adjusting the film formation conditions for forming the insulator part IP2 made of silicon nitride, the insulator part IP2 can be adjusted to have a tensile stress.
  • the insulator part IP4 By adjusting the film formation conditions when forming the insulator part IP4 made of silicon nitride, the insulator part IP4 has a tensile stress smaller than the tensile stress of the insulator part IP2, or It can be adjusted to have a compressive stress.
  • the flow volume detection part 7 can be adjusted so that it may have a tensile stress.
  • the control circuit unit 8 can be adjusted so as to have a tensile stress smaller than the tensile stress of the flow rate detection unit 7 or a compressive stress.
  • the insulator part IP2 has a tensile stress.
  • Insulator part IP1, insulator part IP3, and insulator part IP4 have a tensile stress smaller than the tensile stress of insulator part IP2, or have a compressive stress.
  • step S17 in FIG. 5 a hole TH1 is formed in the semiconductor substrate 6 at a portion located in the region where the opening OP1 is formed in the region AR1 in plan view.
  • an insulating film 43 is formed on the back surface 6 b of the semiconductor substrate 6.
  • the insulating film 43 made of silicon oxide can be formed by a low temperature CVD method using TEOS as a raw material and using plasma.
  • the insulating film 43 made of silicon nitride can be formed by a low temperature CVD method using plasma.
  • a resist pattern made of a resist film is formed by photolithography on the surface of the insulating film 43 formed on the back surface 6b of the semiconductor substrate 6 in the region AR1.
  • This resist pattern has an opening that reaches the insulating film 43 through the resist film at a portion located in a region where the opening OP1 is formed in plan view.
  • the portion of the insulating film 43 exposed at the opening of the resist pattern is removed by a dry etching method or a wet etching method.
  • the semiconductor substrate 6 is etched by a wet etching method, whereby a hole portion that penetrates the semiconductor substrate 6 from the back surface 6b of the semiconductor substrate 6 and reaches the insulator portion IP1.
  • Form TH1 is formed by a wet etching method using potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH) or an aqueous solution mainly containing potassium hydroxide or TMAH. To do.
  • KOH potassium hydroxide
  • TMAH tetramethylammonium hydroxide
  • a diaphragm structure DF1 including the insulator part IP1 and the insulator part IP2 is formed on the upper bottom part of the hole part TH1.
  • the hole portion TH1 is formed in a region of the region AR1 where the opening portion OP1 is formed in a plan view.
  • the insulating film in the portion located in the region where the hole TH1 is formed It is possible to prevent the air flow path convex portion 54 from coming into contact with 20. Therefore, when the sensor chip 3 is sealed with the mold resin 5 (see FIG. 2), the portion of the insulator portion IP1 or the insulator portion IP2 located in the region where the hole portion TH1 is formed is prevented from being damaged. can do.
  • the insulating film 43 may be a laminated film of a silicon oxide film and a silicon nitride film.
  • the insulating film 43 is formed on the back surface 6b of the semiconductor substrate 6. It is also possible to form the hole TH1 without forming it.
  • the region in which the hole portion TH1 is formed means the region in which the hole portion TH1 is formed in the upper bottom portion of the hole portion TH1, that is, the surface 6a of the semiconductor substrate 6.
  • the sensor chip 3 having the semiconductor substrate 6, the flow rate detection unit 7, and the control circuit unit 8 is formed.
  • the insulating film 43 may or may not be removed. Therefore, the illustration of the insulating film 43 is omitted even when the insulating film 43 is not removed.
  • the sensor chip 3 is mounted on the lead frame 2 (step S18 in FIG. 5).
  • the sensor chip 3 is mounted on the lead frame 2, and the sensor chip 3 is electrically connected to the external terminal 2b by the bonding wire 4.
  • the sensor chip 3 is sealed (step S19 in FIG. 5).
  • the sensor chip 3 is sealed with a resin mold using a mold 51 for molding.
  • the mold 51 for molding includes a molding space 52, a mold resin inlet 53, an air flow path convex portion 54, and a convex portion 55.
  • the sensor chip 3 and the lead frame 2 are arranged inside the molding space 52.
  • resin is filled into the molding space 52 from the mold resin inlet 53.
  • the sensor chip 3 and the lead frame 2 are sealed with a resin mold using the mold resin 5 (see FIG. 2).
  • the mold resin 5 adheres to the portion of the flow rate detection unit 7 that forms the diaphragm structure DF1, that is, the insulator unit IP2, the heat capacity of the flow rate detection unit 7 increases, for example.
  • the air flow path convex portion 54 is in close contact with the portion of the insulating portion IP2 formed on the insulating film 16 in the portion located on the end of the insulating portion IP4 on the region AR1 side, but the opening portion
  • the sensor chip 3 is disposed so that the air flow path convex portion 54 does not contact the portion of the insulator portion IP2 located on the insulator portion IP1 of the portion exposed at the bottom of the OP1.
  • the mold resin 5 can be prevented from adhering to the portion of the insulator portion IP2 located on the insulator portion IP1 exposed at the bottom of the opening OP1, and the flow rate of fluid such as air can be accurately controlled. Can be detected well.
  • the air flow path convex portion 54 comes into contact with a portion of the insulator portion IP2 located in the region where the hole portion TH1 is formed, the portion located in the region where the hole portion TH1 is formed. Insulator part IP1 or insulator part IP2 may be damaged.
  • the hole TH1 is formed in a region where the opening OP1 is formed in a plan view.
  • the sensor chip 3 is formed so that the air channel convex portion 54 does not contact the insulating film 20 in the portion located on the insulator portion IP1 in the portion exposed at the bottom of the opening OP1. Be placed.
  • the convex portion 55 is disposed on the opposite side of the air flow path convex portion 54 with the flow rate detecting portion 7, the sensor chip 3, and the lead frame 2 interposed therebetween.
  • the convex portion 55 is arranged so that the convex portion 55 comes into contact with the portion of the lead frame 2 located below the flow rate detecting portion 7. Is arranged.
  • the flow rate detector 7, the semiconductor substrate 6 and the lead frame 2 are sandwiched from above and below by the air flow path convex portion 54 and the convex portion 55, so that the air flow path convex portion 54 is connected to the insulator portion IP4. It is possible to reliably adhere to the portion of the insulator portion IP2 formed on the portion of the insulating film 16 located on the end portion on the region AR1 side.
  • a silicon oxide film formed on a semiconductor substrate made of single crystal silicon usually has a compressive stress because, for example, the thermal expansion coefficient of silicon oxide is smaller than the thermal expansion coefficient of silicon. Therefore, when the flow rate detection unit 7 includes the insulator portion IP1 made of silicon oxide, the flow rate detection unit 7 may have a compressive stress.
  • the flow rate detection unit 7 When the flow rate detection unit 7 has a compressive stress, the flow rate detection unit 7 is likely to be bent, so that the flow rate detection unit 7 may be damaged. Further, when the hole TH1 is formed in the semiconductor substrate 6 in the region where the flow rate detection unit 7 is formed, the flow rate detection unit 7 is more easily bent and the flow rate detection unit 7 is more likely to be damaged. Become.
  • the flow rate detection unit 7 has a tensile stress
  • the flow rate detection unit 7 is not easily bent and the flow rate detection unit 7 is less likely to be damaged.
  • the hole TH1 is formed in the semiconductor substrate 6 in the region where the flow rate detection unit 7 is formed, the flow rate detection unit 7 is not easily bent and the flow rate detection unit 7 is less likely to be damaged.
  • control circuit unit 8 may have tensile stress.
  • the electrical characteristics of the control circuit unit 8 may vary due to variations in transistor characteristics of the transistor Tr or resistance characteristics of the wiring 24 and the like.
  • the mold resin 5 formed so as to cover the control circuit unit 8 usually has a tensile stress. However, when the control circuit unit 8 has a tensile stress, the tensile stress in the control circuit unit 8 is not offset by the mold resin 5.
  • the absolute value of the internal stress in the control circuit unit 8 increases. As described above, when the absolute value of the internal stress in the control circuit unit 8 increases, the electrical characteristics of the control circuit unit 8 change due to the change in the transistor characteristics of the transistor Tr or the resistance characteristics of the wiring 24 and the like. There is a fear.
  • an extensible coating is provided to tension the film in which the measurement element is provided on the film, and the extensible coating is at least an active electronic component of the circuit. Do not cover part. For this reason, the reliability of the flow sensor can be increased by corroding the wiring at the boundary between the area where the extensible coating is provided and the area where the extensible coating is not provided, such as the boundary between the flow rate detection unit and the control circuit unit. May decrease.
  • the ratio of the thickness of the silicon nitride film to the silicon oxide film in the region where the detection unit is provided is equal to the silicon nitride film relative to the silicon oxide film in the region where the circuit unit is provided. Not greater than the thickness ratio.
  • the ratio of the thickness TP2 of the insulator part IP2 to the thickness TP1 of the insulator part IP1 is equal to the thickness TP4 of the insulator part IP4 to the thickness TP3 of the insulator part IP3. Greater than ratio.
  • a silicon oxide film formed on a semiconductor substrate made of single crystal silicon usually has a compressive stress.
  • the internal stress of the silicon nitride film is changed to tensile stress or compressive stress by adjusting the film formation conditions when forming the silicon nitride film. Can be adjusted.
  • the insulator part IP2 can be adjusted so as to have a tensile stress by adjusting the film formation conditions when forming the insulator part IP2 made of silicon nitride.
  • the insulator part IP4 has a tensile stress smaller than the tensile stress of the insulator part IP2, or It can be adjusted to have a compressive stress.
  • the flow rate detection unit 7 including the insulator part IP1 and the insulator part IP2 can be adjusted to have a tensile stress. Therefore, the flow rate detection unit 7 becomes difficult to bend, and the flow rate detection unit 7 can be prevented or suppressed from being damaged. Further, even when the hole portion TH1 is formed in the semiconductor substrate 6 in the area AR1, the flow rate detection unit 7 becomes difficult to bend, and damage to the flow rate detection unit 7 can be prevented or suppressed.
  • the control circuit unit 8 including the insulator part IP2 and the insulator part IP4 is adjusted so as to have a tensile stress smaller than the tensile stress of the flow rate detection unit 7, or to have a compressive stress. be able to.
  • the mold resin 5 formed so as to cover the control circuit unit 8 has a tensile stress.
  • the absolute value of the internal stress of the circuit unit 8 becomes small. Further, since the absolute value of the internal stress of the control circuit unit 8 is small, fluctuations in the electrical characteristics of the control circuit unit 8 can be prevented or suppressed.
  • any one of the insulator part IP2 and the insulator part IP4 made of silicon nitride is formed in any upper layer part of the flow rate detection part 7 and the control circuit part 8. . Therefore, compared to the technique described in Patent Document 1, it is possible to prevent or suppress the corrosion of the wiring 24 of the control circuit CR1 at the boundary between the flow rate detection unit 7 and the control circuit unit 8, for example. And the reliability of the flow sensor can be improved.
  • the thickness TP1 of the insulator part IP1 is thinner than the thickness TP3 of the insulator part IP3 formed in the same layer as the insulator part IP1, and the area AR1 has an opening.
  • the portion OP1 is formed, but the opening OP1 is not formed in a region outside the region AR1 including the region AR2.
  • the insulator part IP2 is continuously formed directly or via the insulating film 16 from the insulator part IP1 to the end of the insulator part IP4 on the region AR1 side.
  • the air flow path convex portion 54 of the mold molding die 51 is sensored so that the mold resin 5 does not flow into the flow rate detection unit 7.
  • the air flow path convex portion 54 can be prevented from coming into contact with the flow rate detection unit 7 as compared with the technique described in Patent Document 1 above. Therefore, the generation of cracks in the flow rate detection unit 7 or the breakage of the flow rate detection unit 7 can be prevented, the yield in manufacturing the flow rate sensor can be improved, and the reliability of the flow rate sensor can be improved.
  • the end of the mold resin 5 on the region AR1 side is located on the insulator part IP2 of the part formed on the insulator part IP4 with the insulating film 16 interposed therebetween.
  • the portion of the insulating film 16 and the insulating portion IP3 exposed from the insulating portion IP4 are further covered with the mold resin 5, so that the wiring of the control circuit CR1 is added to the effect of preventing the contact described above. The effect of preventing corrosion such as 24 is increased.
  • each element other than the sensor chip 3 and among the sensor chip 3, the insulator part IP1 and the insulator part IP2, and the insulator part IP1 and the insulator part IP2 about each element located below, it is common with each element in the flow sensor of Embodiment 1. Therefore, elements common to the elements of the flow sensor of the first embodiment are denoted by the same reference numerals as those of the flow sensor of the first embodiment, and the description thereof is omitted.
  • FIG. 15 is a cross-sectional view of a main part of the sensor chip in the flow sensor according to the second embodiment.
  • the sensor chip 3 includes a semiconductor substrate 6, a flow rate detection unit 7, and a control circuit unit 8.
  • the insulating film 11, the interlayer insulating film 12, the interlayer insulating film 13, the interlayer insulating film 14, and the insulating film 15 are formed on the surface 6a of the semiconductor substrate 6. ing.
  • the flow rate detection unit 7 is formed on the surface 6a of the semiconductor substrate 6 in the region AR1 of the surface 6a of the semiconductor substrate 6, and the insulator unit IP1.
  • the heating resistor 17 and the insulator part IP2 are included.
  • the insulator part IP1 is formed on the surface 6a of the semiconductor substrate 6 in the region AR1, and includes, for example, an insulating film 11a, an interlayer insulating film 12a, and an interlayer insulating film 13a.
  • an opening OP1 that penetrates the interlayer insulating film 14 and reaches the interlayer insulating film 13a is formed in the interlayer insulating film 14.
  • the insulator part IP1 is formed in the area AR1, and is disposed in the area where the opening OP1 is formed.
  • an insulating film 20 made of, for example, silicon nitride is formed on the insulator portion IP1.
  • the insulating film 16 (see FIG. 3) is not formed.
  • the insulating film 15 made of silicon nitride is formed on the insulating film 20 in the region AR1.
  • the insulator part IP2 is formed on the insulator part IP1 in the area AR1.
  • the insulator part IP2 includes an insulating film 20 and an insulating film 15a formed on the insulating film 20.
  • the insulating film 15 a is composed of a portion of the insulating film 15 formed on the insulating film 20.
  • control circuit portion 8 is formed on the surface 6a of the semiconductor substrate 6 in the region AR2 of the surface 6a of the semiconductor substrate 6, and the insulator portion IP3. And a control circuit CR1 and an insulator part IP4.
  • the insulator part IP3 is formed on the surface 6a of the semiconductor substrate 6 in the region AR2, and includes, for example, an insulating film 11b, an interlayer insulating film 12b, an interlayer insulating film 13b, and an interlayer insulating film 14b. .
  • the insulator part IP4 is formed on the insulator part IP3 in the area AR2.
  • the insulator part IP4 includes an insulating film 15b.
  • the insulating film 15b is composed of a portion of the insulating film 15 formed on the interlayer insulating film 14b in the region AR2.
  • the ratio of the thickness TP2 of the insulator portion IP2 to the thickness TP1 of the insulator portion IP1 is the ratio of the insulator portion IP4 to the thickness TP3 of the insulator portion IP3. It is larger than the ratio of the thickness TP4.
  • the insulator part IP2 includes an insulating film 20 and an insulating film 15a.
  • the insulating film 20 can be adjusted to have a tensile stress by adjusting the film forming conditions when forming the insulating film 20 made of, for example, silicon nitride.
  • the insulating film 15a has a tensile stress smaller than the tensile stress of the insulator part IP3 or is compressed by adjusting the film forming conditions when forming the insulating film 15a made of silicon nitride, for example. It can be adjusted to have a stress.
  • the insulator part IP2 can reduce the tensile stress.
  • the insulator part IP4 can be adjusted so as to have a tensile stress or a compressive stress smaller than the tensile stress of the insulator part IP2.
  • the insulator part IP1 has a tensile stress smaller than the tensile stress of the insulator part IP2, or It can be adjusted to have a compressive stress.
  • the insulator part IP3 has a tensile stress smaller than the tensile stress of the insulator part IP2, for example, by adjusting the film formation conditions when forming the insulator part IP3 made of silicon oxide, or It can be adjusted to have a compressive stress.
  • the flow rate detection unit 7 can be adjusted so as to have a tensile stress.
  • the control circuit unit 8 can be adjusted so as to have a tensile stress smaller than the tensile stress of the flow rate detection unit 7 or a compressive stress.
  • the thickness of the insulator part IP2 in the second embodiment can be made larger than the thickness of the insulator part IP2 in the first embodiment. Therefore, in the second embodiment, compared to the first embodiment, the insulator portion IP2 can be easily prevented or suppressed from being corroded by nitric oxide (NO x ) gas contained in the air. Can be easily improved.
  • NO x nitric oxide
  • the insulator part IP2 includes the insulating film 15a formed in the same layer as the insulating film 15b included in the insulator part IP4. Therefore, the thickness TP4 of the insulator part IP4 is larger than the thickness TP2 of the insulator part IP2.
  • the opening OP1 may not be formed.
  • FIG. 16 is a manufacturing process flow chart showing a part of the manufacturing process of the flow sensor according to the second embodiment.
  • 17 and 18 are fragmentary cross-sectional views of the flow rate sensor according to Embodiment 2 during the manufacturing process.
  • the semiconductor substrate 6 is prepared by performing the same steps (step S11 and step S12 in FIG. 16) as those shown in FIGS. 6 to 9 in the first embodiment, and the insulator portion IP1. And the insulator part IP3 is formed.
  • the opening OP1 is formed (step S23 in FIG. 16).
  • the interlayer insulating film 14 is patterned in the region AR1 by using a photolithography method and a dry etching method. That is, the interlayer insulating film 14 is removed by etching in the region AR1.
  • an opening OP1 that penetrates the interlayer insulating film 14 and reaches the interlayer insulating film 13 is formed in the region AR1.
  • the insulator part IP1 includes the insulating film 11a, the interlayer insulating film 12a, and the interlayer insulating film 13a, but does not include the interlayer insulating film 14a. That is, by forming the opening OP1, the thickness TP1 of the insulator part IP1 is made thinner than the thickness TP3 of the insulator part IP3. Therefore, it can adjust so that the compressive stress of insulator part IP1 may become smaller than the compressive stress of insulator part IP3.
  • step S24 in FIG. 16 the same process as the process described in the first embodiment with reference to FIG. 11 (step S16 of FIG. 5) is performed, and as shown in FIG. An insulating film 20 is formed thereon.
  • step S25 in FIG. 16 the same process as the process described in the first embodiment with reference to FIG. 10 (step S13 of FIG. 5) is performed, and as shown in FIG. 18, the regions AR1 and AR2 are insulated.
  • An insulating film 15 is formed on the film 20 and the interlayer insulating film 14.
  • the insulator portion IP2 including the insulating film 20 and the insulating film 15a is formed in the region AR1.
  • the insulating film 15 a is composed of a portion of the insulating film 15 formed on the insulating film 20.
  • the flow rate detection unit 7 including the insulator part IP1, the heating resistor 17, and the insulator part IP2 is formed on the surface 6a of the semiconductor substrate 6.
  • the insulator part IP4 including the insulating film 15b is formed in the region AR2.
  • the insulating film 15b is composed of a portion of the insulating film 15 formed on the interlayer insulating film 14b, that is, on the insulator portion IP3.
  • the control circuit unit 8 including the insulator part IP3, the control circuit CR1, and the insulator part IP4 is formed on the surface 6a of the semiconductor substrate 6.
  • steps S17 to S19 in FIG. 16 are performed to form the flow sensor of the second embodiment.
  • the insulating film 20 made of silicon nitride is formed and patterned. Therefore, it is necessary to form the insulating film 16 made of silicon oxide as an etching stopper for the insulating film 20 after forming the insulating film 15 and before forming the insulating film 20.
  • the insulating film 20 is formed and patterned before the insulating film 15 is formed.
  • the interlayer insulating film 14 made of silicon oxide functions as an etching stopper, it is not necessary to form the insulating film 16, and the number of steps of manufacturing the flow sensor can be reduced.
  • the second embodiment unlike the first embodiment, it is not necessary to form the opening OP1, and the number of steps of manufacturing the flow sensor can be reduced.
  • the flow sensor of the second embodiment also has the same characteristics as the flow sensor of the first embodiment. Therefore, the flow sensor of the second embodiment also has the same effect as the flow sensor of the first embodiment.
  • the insulator portion IP2 since the thickness of the insulator portion IP2 can be made larger than the thickness of the insulator portion IP2 in the first embodiment, the insulator portion is compared with the first embodiment. It is possible to easily prevent or suppress IP2 from being corroded by NO x gas or the like, and it is possible to easily improve the reliability of the flow sensor.
  • the insulator part IP4 includes an insulating film 15b different from the insulating film 20 of the insulator part IP2.
  • the insulator part IP4 includes the insulating film 20b formed in the same layer as the insulating film 20a of the insulator part IP2, and the thickness of the insulating film 20a is the insulating film. It is thicker than 20b.
  • FIG. 19 is a cross-sectional view of the main part of the sensor chip in the flow sensor according to the third embodiment.
  • the sensor chip 3 includes a semiconductor substrate 6, a flow rate detection unit 7, and a control circuit unit 8.
  • the insulating film 11, the interlayer insulating film 12, the interlayer insulating film 13, and the interlayer insulating film 14 are formed on the surface 6a of the semiconductor substrate 6 as in the first embodiment.
  • the flow rate detection unit 7 is formed on the surface 6a of the semiconductor substrate 6 in the region AR1 of the surface 6a of the semiconductor substrate 6, and the insulator unit IP1.
  • the heating resistor 17 and the insulator part IP2 are included.
  • the insulator part IP1 is formed on the surface 6a of the semiconductor substrate 6 in the region AR1, and includes, for example, an insulating film 11a and an interlayer insulating film 12a.
  • the insulating film 15 (see FIG. 2) and the insulating film 16 (see FIG. 2) are not formed.
  • the interlayer insulating film 14 and the interlayer insulating film 13 are formed with an opening OP1 that penetrates the interlayer insulating film 14 and the interlayer insulating film 13 and reaches the interlayer insulating film 12a.
  • the insulator part IP1 is formed in the area AR1, and is disposed in the area where the opening OP1 is formed.
  • an insulating film 20 made of, for example, silicon nitride is formed on the insulator portion IP1.
  • the insulator part IP2 includes an insulating film 20a.
  • the insulating film 20a includes a portion of the insulating film 20 formed on the insulator part IP1.
  • control circuit unit 8 is formed on the surface 6a of the semiconductor substrate 6 in the region AR2 of the surface 6a of the semiconductor substrate 6, and the insulator unit IP3. And a control circuit CR1 and an insulator part IP4.
  • the insulator part IP3 is formed on the surface 6a of the semiconductor substrate 6 in the region AR2, and includes, for example, an insulating film 11b, an interlayer insulating film 12b, an interlayer insulating film 13b, and an interlayer insulating film 14b.
  • the insulator part IP4 includes the insulating film 20b.
  • the insulating film 20b is composed of a portion of the insulating film 20 formed on the insulator portion IP3 in the region AR2. That is, the insulating film 20b is formed in the same layer as the insulating film 20a. Thereby, the insulating film 20b can be formed by the same process as the process of forming the insulating film 20a.
  • the thickness TP2 of the insulating film 20a is thicker than the thickness TP4 of the insulating film 20b.
  • the ratio of the thickness TP2 of the insulator portion IP2 to the thickness TP1 of the insulator portion IP1 is the ratio of the insulator portion IP4 to the thickness TP3 of the insulator portion IP3. It is larger than the ratio of the thickness TP4.
  • the insulating film 20a and the insulating film 20a are formed in the same layer by adjusting the film forming conditions when forming the insulating film 20 made of, for example, silicon nitride.
  • the insulating film 20b to be formed can be adjusted so as to have a tensile stress.
  • the thickness TP2 of the insulating film 20a is thicker than the thickness TP4 of the insulating film 20b. Therefore, it can adjust so that insulator part IP2 may have a tensile stress, and it can adjust so that insulator part IP4 may have a tensile stress smaller than the tensile stress of insulator part IP2.
  • the flow rate detection unit 7 can be adjusted so as to have a tensile stress. Further, the control circuit unit 8 can be adjusted so as to have a tensile stress smaller than the tensile stress of the flow rate detection unit 7 or a compressive stress.
  • the insulating film 20b formed in the same layer as the insulating film 20a included in the insulating part IP2 is included in the insulating part IP4. Therefore, when the insulator part IP2 has a tensile stress, the insulator part IP4 also has a tensile stress.
  • the opening OP1 penetrates through the interlayer insulating film 14 and the interlayer insulating film 13 and reaches the interlayer insulating film 12a. That is, in the third embodiment, the ratio of the thickness TP3 of the insulator portion IP3 to the thickness TP1 of the insulator portion IP1 is further increased as compared with the first embodiment. In such a case, the control circuit unit 8 can be easily adjusted so as to have a tensile stress or a compressive stress smaller than the tensile stress of the flow rate detection unit 7.
  • the ratio of the thickness TP2 of the insulator part IP2 to the thickness TP1 of the insulator part IP1 Is sufficiently larger than the ratio of the thickness TP4 of the insulator part IP4 to the thickness TP3 of the insulator part IP3.
  • the opening OP1 only needs to reach the interlayer insulating film 13 through the interlayer insulating film 14, and the opening OP1 does not reach the interlayer insulating film 12 through the interlayer insulating film 13. May be.
  • FIG. 20 is a manufacturing process flowchart showing a part of the manufacturing process of the flow sensor according to the third embodiment.
  • 21 and 22 are cross-sectional views of main parts during the manufacturing process of the flow sensor according to the third embodiment.
  • the semiconductor substrate 6 is prepared by performing the same processes (step S11 and step S12 in FIG. 20) as those shown in FIGS. 6 to 9 in the first embodiment, and the insulator portion IP1. And the insulator part IP3 is formed.
  • the opening OP1 is formed (step S33 in FIG. 20).
  • the interlayer insulating film 14 and the interlayer insulating film 13 are patterned in the region AR1 by using a photolithography method and a dry etching method.
  • the interlayer insulating film 14 is removed by etching.
  • the portion of the interlayer insulating film 13 from which the interlayer insulating film 14 has been removed is removed by etching.
  • an opening OP1 that penetrates the interlayer insulating film 14 and the interlayer insulating film 13 and reaches the interlayer insulating film 12 is formed.
  • the insulator part IP1 includes the insulating film 11a and the interlayer insulating film 12a, but the interlayer insulating film 13a (see FIG. 3) and the interlayer insulating film 14a (see FIG. 9). Will not be included. That is, by forming the opening OP1, the thickness TP1 of the insulator part IP1 is made thinner than the thickness TP3 of the insulator part IP3. Therefore, it can adjust so that the compressive stress of insulator part IP1 may become smaller than the compressive stress of insulator part IP3.
  • step S34 in FIG. 20 a part of the process described in the first embodiment with reference to FIG. 11 (step S16 of FIG. 5) is performed, and as shown in FIG. In the region AR2, the insulating film 20 is formed on the insulator part IP1 and the insulator part IP3.
  • step S35 in FIG. 20 the insulating film 20 is etched (step S35 in FIG. 20).
  • step S35 as shown in FIG. 22, the insulating film 20 is etched in the region AR2.
  • the insulating film 20 is half-etched in the region AR2.
  • an insulating film 20a made of the remaining insulating film 20 is formed in the region AR1, and a thickness TP4 thinner than the thickness TP2 of the insulating film 20a in the region AR1 is formed in the region AR2.
  • An insulating film 20b is formed.
  • the insulator part IP2 including the insulating film 20a is formed in the region AR1.
  • the flow rate detection unit 7 including the insulator part IP1, the heating resistor 17, and the insulator part IP2 is formed on the surface 6a of the semiconductor substrate 6.
  • the insulator part IP4 including the insulating film 20b is formed in the region AR2.
  • the control circuit unit 8 including the insulator part IP3, the control circuit CR1, and the insulator part IP4 is formed on the surface 6a of the semiconductor substrate 6.
  • steps S17 to S19 in FIG. 20 are performed to form the flow sensor of the third embodiment.
  • the insulating film 20b can be formed by the same process as the process of forming the insulating film 20a. Further, in the manufacturing process of the flow sensor according to the third embodiment, the insulating film 15 (see FIG. 3) and the insulating film 16 (see FIG. 3) are not formed. Therefore, in this Embodiment 3, compared with Embodiment 1, the number of processes of the flow sensor manufacturing process can be reduced.
  • the flow sensor of the third embodiment also has the same characteristics as the flow sensor of the first embodiment. Therefore, the flow sensor of the third embodiment also has the same effect as the flow sensor of the first embodiment.
  • the insulator part IP4 when the insulator part IP2 has a tensile stress, the insulator part IP4 also has a tensile stress. However, by increasing the ratio of the thickness TP3 of the insulator part IP3 to the thickness TP1 of the insulator part IP1, the control circuit unit 8 has a tensile stress smaller than the tensile stress of the flow rate detection part 7 or a compressive stress. It can be easily adjusted to have
  • the insulating film 20b can be formed by the same process as the process of forming the insulating film 20a, and the insulating film 15 (see FIG. 3) and the insulating film 16 (see FIG. 3) is not formed. Therefore, in this Embodiment 3, compared with Embodiment 1, the number of processes of the flow sensor manufacturing process can be reduced.
  • the present invention is effective when applied to a flow sensor.

Abstract

A flow rate sensor (1) has: an insulating material section (IP1) that is formed on a surface (6a) of a semiconductor substrate (6), said insulating material section being in a region (AR1); an insulating material section (IP2) that is formed on the insulating material section (IP1); an insulating material section (IP3) that is formed on the surface (6a) of the semiconductor substrate (6), said insulating material section being in a region (AR2); and an insulating material section (IP4) that is formed on the insulating material section (IP3). The insulating material section (IP1) and the insulating material section (IP3) are formed of silicon oxide, and the insulating material section (IP2) and the insulating material section (IP4) are formed of silicon nitride. The ratio of the thickness (TP2) of the insulating material section (IP2) with respect to the thickness (TP1) of the insulating material section (IP1) is larger than the ratio of the thickness (TP4) of the insulating material section (IP4) with respect to the thickness (TP3) of the insulating material section (IP3).

Description

流量センサおよびその製造方法Flow sensor and manufacturing method thereof
　本発明は流量センサに関し、発熱抵抗体を用いる流量センサに関する。 The present invention relates to a flow rate sensor, and relates to a flow rate sensor using a heating resistor.
　現在、自動車などの内燃機関の電子制御燃料噴射装置には、吸入空気量を測定する空気流量計が設けられている。そして、このような空気流量計に用いられる流体流量センサとしては、発熱抵抗体を用いる熱式流体流量センサが、質量空気量を直接検知できることから、主流となってきている。 Currently, electronically controlled fuel injection devices for internal combustion engines such as automobiles are provided with an air flow meter for measuring the intake air amount. And as a fluid flow sensor used in such an air flow meter, a thermal fluid flow sensor using a heating resistor has become mainstream because it can directly detect the mass air amount.
　この中では、半導体を用いた微小電気機械システム（Micro Electro Mechanical Systems；ＭＥＭＳ）技術により製造された熱式流体流量センサ、すなわちエアフローセンサが、製造コストを低減でき、低電力で駆動できることから、注目されてきた。 Among these, thermal fluid flow sensors manufactured by micro electro mechanical systems (MEMS) technology using semiconductors, that is, air flow sensors, can reduce manufacturing costs and can be driven with low power. It has been.
　このような熱式流体流量センサである流量センサとして、発熱抵抗体を含み、流体の流量を検出する流量検出部と、トランジスタなどからなる回路を含み、流量検出部を制御する制御回路部とが、互いに異なる基板上に形成されたものがある。このような場合、流量検出部が形成された流量検出基板と、制御回路部が形成された制御回路基板とを、ワイヤボンディングなどの方法により電気的に接続する必要がある。そのため、部品数が増加し、流量検出基板と制御回路基板とを組み立てる組立工程後に検査工程を追加して行うことにより製造工程の工程数が増加し、組立工程において不良が発生することにより歩留まりが低下するおそれがあり、製造コストが増加する。 As a flow rate sensor that is such a thermal fluid flow rate sensor, a flow rate detection unit that includes a heating resistor and detects a flow rate of fluid, and a control circuit unit that includes a circuit including a transistor and the like and controls the flow rate detection unit Some of them are formed on different substrates. In such a case, it is necessary to electrically connect the flow rate detection board on which the flow rate detection unit is formed and the control circuit board on which the control circuit unit is formed by a method such as wire bonding. Therefore, the number of parts increases, the number of manufacturing processes increases by performing an additional inspection process after the assembly process for assembling the flow rate detection board and the control circuit board, and the yield increases due to the occurrence of defects in the assembly process. There is a risk of lowering the manufacturing cost.
　一方、熱式流体流量センサである流量センサとして、流量検出部と、制御回路部と、が同一の基板上に形成されたものがある。このような場合、流量検出基板と制御回路基板とを、ワイヤボンディングなどの方法により電気的に接続する必要がない。そのため、部品数を減少させることができる。 On the other hand, as a flow sensor that is a thermal fluid flow sensor, there is one in which a flow rate detection unit and a control circuit unit are formed on the same substrate. In such a case, it is not necessary to electrically connect the flow rate detection board and the control circuit board by a method such as wire bonding. Therefore, the number of parts can be reduced.
　特表２００４－５１８１１９号公報（特許文献１）には、マイクロメカニカルフローセンサにおいて、半導体基板上に、測定素子と、回路とが集積され、測定素子が、半導体基板の開口部または凹部上の膜上に設けられる技術が、開示されている。 Japanese Patent Publication No. 2004-518119 (Patent Document 1) discloses a micromechanical flow sensor in which a measurement element and a circuit are integrated on a semiconductor substrate, and the measurement element is a film on an opening or a recess of the semiconductor substrate. The technology provided above is disclosed.
　特開２０１２－２０２７８６号公報（特許文献２）には、熱式センサにおいて、半導体基板の上方に設けられた第１積層膜上に設けられ、発熱抵抗体を含む検出部と、半導体基板上に設けられ、発熱抵抗体を制御する制御回路を有する回路部と、を有する技術が、開示されている。 Japanese Patent Laying-Open No. 2012-202786 (Patent Document 2) discloses that in a thermal sensor, a detection unit provided on a first laminated film provided above a semiconductor substrate, including a heating resistor, and a semiconductor substrate. There is disclosed a technology including a circuit unit that is provided and has a control circuit that controls a heating resistor.
特表２００４－５１８１１９号公報JP-T-2004-518119 特開２０１２－２０２７８６号公報JP 2012-202786 A
　上記した、同一の基板上に形成された流量検出部と制御回路部とを有する流量センサにおいて、流量検出部が圧縮応力を有することがある。このような場合、流量検出部が撓みやすくなるので、流量検出部が破損するおそれがある。 In the above-described flow rate sensor having the flow rate detection unit and the control circuit unit formed on the same substrate, the flow rate detection unit may have compressive stress. In such a case, the flow rate detection unit is easily bent, and thus the flow rate detection unit may be damaged.
　一方、流量検出部が引っ張り応力を有する場合には、流量検出部は撓みにくく、流量検出部が破損するおそれは少ない。ところが、流量検出部が引っ張り応力を有する場合には、制御回路部が引っ張り応力を有することがある。このような場合、制御回路部に含まれるトランジスタのトランジスタ特性、または、配線の抵抗特性が変動することなどにより、制御回路部の特性が変動するおそれがある。 On the other hand, when the flow rate detection unit has tensile stress, the flow rate detection unit is difficult to bend and the flow rate detection unit is less likely to be damaged. However, when the flow rate detection unit has tensile stress, the control circuit unit may have tensile stress. In such a case, the characteristics of the control circuit unit may vary due to variations in transistor characteristics of the transistors included in the control circuit unit or resistance characteristics of the wiring.
　そこで、本発明は、同一の基板上に形成された流量検出部と制御回路部とを有し、流量検出部の破損を防止し、制御回路部の特性の変動を防止することができる流量センサを提供する。 Therefore, the present invention has a flow rate detection unit and a control circuit unit that are formed on the same substrate, and prevents the flow rate detection unit from being damaged and can prevent fluctuations in the characteristics of the control circuit unit. I will provide a.
　代表的な実施の形態による流量センサは、半導体基板の第１主面の第１領域で、半導体基板の第１主面上に形成され、流体の流量を検出する流量検出部と、半導体基板の第１主面の第２領域で、半導体基板の第１主面上に形成され、流量検出部を制御する制御回路部と、を備える。流量検出部は、第１領域で、半導体基板の第１主面上に形成された第１絶縁体部と、第１絶縁体部と接触するように形成された発熱抵抗体と、第１絶縁体部上に形成された第２絶縁体部と、を有する。制御回路部は、第２領域で、半導体基板の第１主面上に形成された第３絶縁体部と、第３絶縁体部内に形成され、発熱抵抗体を制御する回路と、第３絶縁体部上に形成された第４絶縁体部と、を有する。第１絶縁体部および第３絶縁体部は、酸化シリコンからなり、第２絶縁体部および第４絶縁体部は、窒化シリコンからなる。第１絶縁体部の厚さに対する第２絶縁体部の厚さの比は、第３絶縁体部の厚さに対する第４絶縁体部の厚さの比よりも大きい。 A flow sensor according to a representative embodiment is formed on a first main surface of a semiconductor substrate in a first region of the first main surface of the semiconductor substrate, and includes a flow rate detection unit that detects a flow rate of fluid, And a control circuit unit that is formed on the first main surface of the semiconductor substrate in the second region of the first main surface and controls the flow rate detection unit. The flow rate detection unit includes a first insulator portion formed on the first main surface of the semiconductor substrate, a heating resistor formed so as to be in contact with the first insulator portion, and a first insulation in the first region. And a second insulator part formed on the body part. The control circuit section includes a third insulator section formed on the first main surface of the semiconductor substrate in the second region, a circuit formed in the third insulator section for controlling the heating resistor, and a third insulation section. And a fourth insulator portion formed on the body portion. The first insulator portion and the third insulator portion are made of silicon oxide, and the second insulator portion and the fourth insulator portion are made of silicon nitride. The ratio of the thickness of the second insulator part to the thickness of the first insulator part is larger than the ratio of the thickness of the fourth insulator part to the thickness of the third insulator part.
　また、代表的な実施の形態による流量センサの製造方法は、半導体基板の第１主面の第１領域で、半導体基板の第１主面上に、流体の流量を検出する流量検出部を形成する工程と、半導体基板の第１主面の第２領域で、半導体基板の第１主面上に、流量検出部を制御する制御回路部を形成する工程と、を備える。流量検出部を形成する工程は、第１領域で、半導体基板の第１主面上に、第１絶縁体部を形成する工程と、第１絶縁体部と接触するように、発熱抵抗体を形成する工程と、第１絶縁体部上に、第２絶縁体部を形成する工程と、を有する。制御回路部を形成する工程は、第２領域で、半導体基板の第１主面上に、第３絶縁体部を形成する工程と、第３絶縁体部内に、発熱抵抗体を制御する回路を形成する工程と、第３絶縁体部上に、第４絶縁体部を形成する工程と、を有する。第１絶縁体部および第３絶縁体部は、酸化シリコンからなり、第２絶縁体部および第４絶縁体部は、窒化シリコンからなる。第１絶縁体部の厚さに対する第２絶縁体部の厚さの比は、第３絶縁体部の厚さに対する第４絶縁体部の厚さの比よりも大きい。 In addition, the flow rate sensor manufacturing method according to the representative embodiment forms a flow rate detection unit for detecting the flow rate of the fluid on the first main surface of the semiconductor substrate in the first region of the first main surface of the semiconductor substrate. And a step of forming a control circuit unit for controlling the flow rate detection unit on the first main surface of the semiconductor substrate in the second region of the first main surface of the semiconductor substrate. In the first region, the step of forming the flow rate detection unit includes the step of forming the first insulator portion on the first main surface of the semiconductor substrate, and the heating resistor so as to be in contact with the first insulator portion. And forming a second insulator part on the first insulator part. The step of forming the control circuit portion includes a step of forming a third insulator portion on the first main surface of the semiconductor substrate in the second region, and a circuit for controlling the heating resistor in the third insulator portion. And forming a fourth insulator part on the third insulator part. The first insulator portion and the third insulator portion are made of silicon oxide, and the second insulator portion and the fourth insulator portion are made of silicon nitride. The ratio of the thickness of the second insulator part to the thickness of the first insulator part is larger than the ratio of the thickness of the fourth insulator part to the thickness of the third insulator part.
　代表的な実施の形態によれば、同一の基板上に形成された流量検出部と制御回路部とを有する流量センサにおいて、流量検出部の破損を防止し、制御回路部の特性の変動を防止することができる。 According to a typical embodiment, in a flow sensor having a flow rate detection unit and a control circuit unit formed on the same substrate, the flow rate detection unit is prevented from being damaged, and fluctuations in the characteristics of the control circuit unit are prevented. can do.
実施の形態１の流量センサの一例を示す要部平面図である。FIG. 3 is a plan view of a principal part showing an example of a flow sensor according to the first embodiment. 実施の形態１の流量センサの要部断面図である。FIG. 3 is a cross-sectional view of a main part of the flow sensor according to the first embodiment. 実施の形態１の流量センサにおけるセンサチップの要部断面図である。3 is a cross-sectional view of a main part of a sensor chip in the flow sensor according to Embodiment 1. FIG. 実施の形態１の流量センサが実装された空気流量計の概略配置図である。FIG. 3 is a schematic layout diagram of an air flow meter on which the flow sensor according to the first embodiment is mounted. 実施の形態１の流量センサの製造工程の一部を示す製造プロセスフロー図である。FIG. 6 is a manufacturing process flow chart showing a part of the manufacturing process of the flow sensor according to the first embodiment. 実施の形態１の流量センサの製造工程中の要部断面図である。FIG. 3 is a cross-sectional view of a main part during the manufacturing process of the flow sensor according to the first embodiment. 実施の形態１の流量センサの製造工程中の要部断面図である。FIG. 3 is a cross-sectional view of a main part during the manufacturing process of the flow sensor according to the first embodiment. 実施の形態１の流量センサの製造工程中の要部断面図である。FIG. 3 is a cross-sectional view of a main part during the manufacturing process of the flow sensor according to the first embodiment. 実施の形態１の流量センサの製造工程中の要部断面図である。FIG. 3 is a cross-sectional view of a main part during the manufacturing process of the flow sensor according to the first embodiment. 実施の形態１の流量センサの製造工程中の要部断面図である。FIG. 3 is a cross-sectional view of a main part during the manufacturing process of the flow sensor according to the first embodiment. 実施の形態１の流量センサの製造工程中の要部断面図である。FIG. 3 is a cross-sectional view of a main part during the manufacturing process of the flow sensor according to the first embodiment. 実施の形態１の流量センサの製造工程中の要部断面図である。FIG. 3 is a cross-sectional view of a main part during the manufacturing process of the flow sensor according to the first embodiment. 実施の形態１の流量センサの製造工程中の要部断面図である。FIG. 3 is a cross-sectional view of a main part during the manufacturing process of the flow sensor according to the first embodiment. 実施の形態１の流量センサの製造工程中の要部断面図である。FIG. 3 is a cross-sectional view of a main part during the manufacturing process of the flow sensor according to the first embodiment. 実施の形態２の流量センサにおけるセンサチップの要部断面図である。FIG. 6 is a cross-sectional view of a main part of a sensor chip in a flow sensor according to a second embodiment. 実施の形態２の流量センサの製造工程の一部を示す製造プロセスフロー図である。FIG. 10 is a manufacturing process flow chart showing a part of the manufacturing process of the flow sensor according to the second embodiment. 実施の形態２の流量センサの製造工程中の要部断面図である。FIG. 10 is a cross-sectional view of a main part during the manufacturing process of the flow sensor according to the second embodiment. 実施の形態２の流量センサの製造工程中の要部断面図である。FIG. 10 is a cross-sectional view of a main part during the manufacturing process of the flow sensor according to the second embodiment. 実施の形態３の流量センサにおけるセンサチップの要部断面図である。FIG. 10 is a cross-sectional view of a main part of a sensor chip in a flow sensor according to a third embodiment. 実施の形態３の流量センサの製造工程の一部を示す製造プロセスフロー図である。FIG. 10 is a manufacturing process flow chart showing a part of the manufacturing process of the flow sensor according to the third embodiment. 実施の形態３の流量センサの製造工程中の要部断面図である。FIG. 10 is a cross-sectional view of a main part during the manufacturing process of the flow sensor according to the third embodiment. 実施の形態３の流量センサの製造工程中の要部断面図である。FIG. 10 is a cross-sectional view of a main part during the manufacturing process of the flow sensor according to the third embodiment.
　以下の実施の形態においては便宜上その必要があるときは、複数のセクションまたは実施の形態に分割して説明するが、特に明示した場合を除き、それらはお互いに無関係なものではなく、一方は他方の一部または全部の変形例、詳細、補足説明等の関係にある。 In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.
　また、以下の実施の形態において、要素の数等（個数、数値、量、範囲等を含む）に言及する場合、特に明示した場合および原理的に明らかに特定の数に限定される場合等を除き、その特定の数に限定されるものではなく、特定の数以上でも以下でもよい。 Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.
　さらに、以下の実施の形態において、その構成要素（要素ステップ等も含む）は、特に明示した場合および原理的に明らかに必須であると考えられる場合等を除き、必ずしも必須のものではないことはいうまでもない。同様に、以下の実施の形態において、構成要素等の形状、位置関係等に言及するときは、特に明示した場合および原理的に明らかにそうでないと考えられる場合等を除き、実質的にその形状等に近似または類似するもの等を含むものとする。このことは、上記数値および範囲についても同様である。 Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.
　以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の機能を有する部材には同一の符号を付し、その繰り返しの説明は省略する。また、以下の実施の形態では、特に必要なとき以外は同一または同様な部分の説明を原則として繰り返さない。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.
　さらに、実施の形態で用いる図面においては、断面図であっても図面を見やすくするためにハッチングを省略する場合もある。また、平面図であっても図面を見やすくするためにハッチングを付す場合もある。 Furthermore, in the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view for easy viewing of the drawings. Further, even a plan view may be hatched to make the drawing easy to see.
　また、以下の実施の形態において、Ａ～Ｂとして範囲を示す場合には、特に明示した場合を除き、Ａ以上Ｂ以下を示すものとする。 Also, in the following embodiments, when ranges are indicated as A to B, A to B are indicated unless otherwise specified.
　（実施の形態１）
　本発明の一実施の形態である流量センサを、図面を参照して説明する。本実施の形態の流量センサは、発熱抵抗体を用いて流体の流量を検出する熱式流体流量センサである。 (Embodiment 1)
A flow sensor according to an embodiment of the present invention will be described with reference to the drawings. The flow rate sensor of the present embodiment is a thermal fluid flow rate sensor that detects the flow rate of fluid using a heating resistor.
　＜流量センサ＞
　図１は、実施の形態１の流量センサの一例を示す要部平面図である。図２は、実施の形態１の流量センサの要部断面図である。図３は、実施の形態１の流量センサにおけるセンサチップの要部断面図である。図２および図３は、図１のＡ－Ａ線に沿った断面図である。 <Flow sensor>
FIG. 1 is a main part plan view showing an example of a flow sensor according to the first embodiment. FIG. 2 is a cross-sectional view of a main part of the flow sensor according to the first embodiment. FIG. 3 is a cross-sectional view of a main part of the sensor chip in the flow sensor according to the first embodiment. 2 and 3 are cross-sectional views taken along the line AA in FIG.
　図１および図２に示すように、流量センサ１は、リードフレーム２と、センサチップ３と、ボンディングワイヤ４と、モールド樹脂５と、を有する。 As shown in FIGS. 1 and 2, the flow sensor 1 has a lead frame 2, a sensor chip 3, a bonding wire 4, and a mold resin 5.
　リードフレーム２は、搭載部２ａと、外部端子２ｂとを有する。搭載部２ａには、センサチップ３が搭載されている。外部端子２ｂは、ボンディングワイヤ４により、センサチップ３と電気的に接続されている。搭載部２ａと、外部端子２ｂとを含め、リードフレーム２は、銅（Ｃｕ）または銅（Ｃｕ）合金からなる。 The lead frame 2 has a mounting portion 2a and an external terminal 2b. A sensor chip 3 is mounted on the mounting portion 2a. The external terminal 2 b is electrically connected to the sensor chip 3 by a bonding wire 4. The lead frame 2 including the mounting portion 2a and the external terminal 2b is made of copper (Cu) or a copper (Cu) alloy.
　図１～図３に示すように、センサチップ３は、半導体基板６と、流量検出部７と、制御回路部８と、を有する。 1 to 3, the sensor chip 3 includes a semiconductor substrate 6, a flow rate detection unit 7, and a control circuit unit 8.
　半導体基板６は、一方の主面としての表面６ａと、表面６ａと反対側の、他方の主面としての裏面６ｂと、を有する。半導体基板６は、例えば単結晶シリコン（Ｓｉ）からなる。半導体基板６は、半導体基板６の裏面６ｂがリードフレーム２の搭載部２ａと対向した状態で、搭載部２ａ上に搭載されている。 The semiconductor substrate 6 has a surface 6a as one main surface and a back surface 6b as the other main surface opposite to the surface 6a. The semiconductor substrate 6 is made of, for example, single crystal silicon (Si). The semiconductor substrate 6 is mounted on the mounting portion 2 a with the back surface 6 b of the semiconductor substrate 6 facing the mounting portion 2 a of the lead frame 2.
　半導体基板６の表面６ａの領域ＡＲ１、および、半導体基板６の表面６ａの領域ＡＲ２で、半導体基板６の表面６ａ上には、例えば酸化シリコンからなる素子分離膜としての絶縁膜１１が形成されている。領域ＡＲ１および領域ＡＲ２で、絶縁膜１１上には、例えば酸化シリコンからなる層間絶縁膜１２が形成されている。領域ＡＲ１および領域ＡＲ２で、層間絶縁膜１２上には、例えば酸化シリコンからなる層間絶縁膜１３が形成されている。領域ＡＲ１および領域ＡＲ２で、層間絶縁膜１３上には、例えば酸化シリコンからなる層間絶縁膜１４が形成されている。領域ＡＲ２で、層間絶縁膜１４上には、例えば窒化シリコンからなる絶縁膜１５が形成されている。領域ＡＲ２で、絶縁膜１５上には、例えば酸化シリコンからなる絶縁膜１６が形成されている。 In the region AR1 of the surface 6a of the semiconductor substrate 6 and the region AR2 of the surface 6a of the semiconductor substrate 6, an insulating film 11 as an element isolation film made of, for example, silicon oxide is formed on the surface 6a of the semiconductor substrate 6. Yes. An interlayer insulating film 12 made of, for example, silicon oxide is formed on the insulating film 11 in the regions AR1 and AR2. An interlayer insulating film 13 made of, for example, silicon oxide is formed on the interlayer insulating film 12 in the regions AR1 and AR2. An interlayer insulating film 14 made of, for example, silicon oxide is formed on the interlayer insulating film 13 in the regions AR1 and AR2. In the region AR2, an insulating film 15 made of, for example, silicon nitride is formed on the interlayer insulating film. In the region AR2, an insulating film 16 made of, for example, silicon oxide is formed on the insulating film 15.
　なお、平面視において、領域ＡＲ２は、領域ＡＲ１の一方の側に配置されていてもよく、領域ＡＲ１の一方の側と他方の側を含めた両側に配置されていてもよく、領域ＡＲ１の外周を囲むように配置されていてもよい。また、本願明細書では、平面視において、とは、半導体基板６の表面６ａに垂直な方向から視た場合を意味する。 In a plan view, the area AR2 may be arranged on one side of the area AR1, may be arranged on both sides including the one side and the other side of the area AR1, and the outer periphery of the area AR1. May be arranged so as to surround. Further, in the present specification, in the plan view, the term “when viewed from a direction perpendicular to the surface 6 a of the semiconductor substrate 6” is meant.
　流量検出部７は、半導体基板６の表面６ａの領域ＡＲ１で、半導体基板６の表面６ａ上に形成されており、空気などの流体の流量を検出する。流量検出部７は、絶縁体部ＩＰ１と、発熱抵抗体１７と、絶縁体部ＩＰ２と、を有する。 The flow rate detector 7 is formed on the surface 6a of the semiconductor substrate 6 in the area AR1 of the surface 6a of the semiconductor substrate 6, and detects the flow rate of fluid such as air. The flow rate detection unit 7 includes an insulator part IP1, a heating resistor 17, and an insulator part IP2.
　絶縁体部ＩＰ１は、領域ＡＲ１で、半導体基板６の表面６ａ上に形成されている。絶縁体部ＩＰ１は、例えば、絶縁膜１１ａと、層間絶縁膜１２ａと、層間絶縁膜１３ａと、を含む。絶縁膜１１ａは、領域ＡＲ１で、半導体基板６の表面６ａ上に形成された部分の絶縁膜１１からなる。層間絶縁膜１２ａは、絶縁膜１１ａ上に形成された部分の層間絶縁膜１２からなる。層間絶縁膜１３ａは、層間絶縁膜１２ａ上に形成された部分の層間絶縁膜１３からなる。 The insulator portion IP1 is formed on the surface 6a of the semiconductor substrate 6 in the region AR1. The insulator part IP1 includes, for example, an insulating film 11a, an interlayer insulating film 12a, and an interlayer insulating film 13a. The insulating film 11a is the region AR1 and is formed of a portion of the insulating film 11 formed on the surface 6a of the semiconductor substrate 6. The interlayer insulating film 12a includes a portion of the interlayer insulating film 12 formed on the insulating film 11a. The interlayer insulating film 13a is composed of a portion of the interlayer insulating film 13 formed on the interlayer insulating film 12a.
　発熱抵抗体１７は、絶縁体部ＩＰ１と接触するように形成されている。発熱抵抗体１７は、発熱抵抗体１７が発熱することにより、絶縁体部ＩＰ１を室温よりも高い温度に加熱する。したがって、発熱抵抗体１７は、絶縁体部ＩＰ１と熱的に接触するように形成されているだけでもよい。 The heating resistor 17 is formed in contact with the insulator part IP1. The heating resistor 17 heats the insulator part IP1 to a temperature higher than room temperature when the heating resistor 17 generates heat. Therefore, the heating resistor 17 may be formed only in thermal contact with the insulator part IP1.
　好適には、発熱抵抗体１７は、例えば多結晶シリコンからなり、絶縁膜１１上に形成されており、層間絶縁膜１２は、発熱抵抗体１７を覆うように、絶縁膜１１上に形成されている。すなわち、例えば多結晶シリコンからなる発熱抵抗体１７は、後述する制御回路部８の、例えば多結晶シリコンからなるゲート電極２７の導体膜２７ａと同層に形成された導体膜２７ａからなる。これにより、発熱抵抗体１７と、ゲート電極２７とを、同一の工程により形成することができる。 Preferably, the heating resistor 17 is made of, for example, polycrystalline silicon and is formed on the insulating film 11. The interlayer insulating film 12 is formed on the insulating film 11 so as to cover the heating resistor 17. Yes. That is, the heating resistor 17 made of, for example, polycrystalline silicon is made of a conductive film 27a formed in the same layer as the conductive film 27a of the gate electrode 27 made of, for example, polycrystalline silicon in the control circuit unit 8 to be described later. Thereby, the heating resistor 17 and the gate electrode 27 can be formed by the same process.
　なお、図１において、二点鎖線で示すように、流量検出部７は、上流側測温抵抗体１８と、下流側測温抵抗体１９と、を有してもよい。上流側測温抵抗体１８および下流側測温抵抗体１９も、発熱抵抗体１７と同様に、領域ＡＲ１で、絶縁体部ＩＰ１と接触するように形成されている。好適には、上流側測温抵抗体１８および下流側測温抵抗体１９は、例えば多結晶シリコンからなり、絶縁膜１１上に形成されており、層間絶縁膜１２は、上流側測温抵抗体１８および下流側測温抵抗体１９を覆うように、絶縁膜１１上に形成されている。 In addition, in FIG. 1, as shown with a dashed-two dotted line, the flow volume detection part 7 may have the upstream temperature sensing resistor 18 and the downstream temperature sensing resistor 19. FIG. Similarly to the heating resistor 17, the upstream resistance temperature detector 18 and the downstream resistance temperature detector 19 are also formed so as to be in contact with the insulator part IP1 in the region AR1. Preferably, the upstream resistance temperature detector 18 and the downstream resistance temperature detector 19 are made of, for example, polycrystalline silicon and are formed on the insulating film 11, and the interlayer insulating film 12 is the upstream resistance temperature detector. 18 and the downstream resistance temperature detector 19 are formed on the insulating film 11.
　領域ＡＲ１で、絶縁膜１６、絶縁膜１５および層間絶縁膜１４には、絶縁膜１６、絶縁膜１５および層間絶縁膜１４を貫通して層間絶縁膜１３に達する開口部ＯＰ１が形成されている。 In the region AR1, the insulating film 16, the insulating film 15, and the interlayer insulating film 14 are formed with an opening OP1 that penetrates the insulating film 16, the insulating film 15, and the interlayer insulating film 14 and reaches the interlayer insulating film 13.
　絶縁体部ＩＰ１は、領域ＡＲ１で、形成されている。すなわち、絶縁体部ＩＰ１は、開口部ＯＰ１が形成された領域内に、配置されている。したがって、絶縁膜１１ａは、平面視において、開口部ＯＰ１が形成された領域内に位置する部分の絶縁膜１１からなる。層間絶縁膜１２ａは、平面視において、開口部ＯＰ１が形成された領域内に位置する部分の層間絶縁膜１２からなる。層間絶縁膜１３ａは、平面視において、開口部ＯＰ１が形成された領域内に位置する部分の層間絶縁膜１３からなる。言い換えれば、層間絶縁膜１３ａは、開口部ＯＰ１の底部に露出した部分の層間絶縁膜１３からなる。 The insulator part IP1 is formed in the area AR1. That is, the insulator part IP1 is disposed in the region where the opening OP1 is formed. Therefore, the insulating film 11a is composed of a portion of the insulating film 11 located in the region where the opening OP1 is formed in plan view. The interlayer insulating film 12a is composed of a portion of the interlayer insulating film 12 located in a region where the opening OP1 is formed in plan view. The interlayer insulating film 13a is composed of a portion of the interlayer insulating film 13 located in a region where the opening OP1 is formed in plan view. In other words, the interlayer insulating film 13a includes the portion of the interlayer insulating film 13 exposed at the bottom of the opening OP1.
　領域ＡＲ１で、開口部ＯＰ１の内壁には、例えば窒化シリコンからなる絶縁膜２０が形成されている。 In the region AR1, an insulating film 20 made of, for example, silicon nitride is formed on the inner wall of the opening OP1.
　絶縁体部ＩＰ２は、領域ＡＲ１で、絶縁体部ＩＰ１上に形成されている。絶縁体部ＩＰ２は、絶縁膜２０を含む。絶縁膜２０は、領域ＡＲ１で、層間絶縁膜１３ａ上に形成されている。 The insulator part IP2 is formed on the insulator part IP1 in the area AR1. The insulator part IP2 includes an insulating film 20. The insulating film 20 is formed on the interlayer insulating film 13a in the region AR1.
　本実施の形態１では、センサチップ３は、孔部ＴＨ１を有する。孔部ＴＨ１は、領域ＡＲ１で、半導体基板６の裏面６ｂから半導体基板６を貫通して絶縁体部ＩＰ１、すなわち流量検出部７に達する。孔部ＴＨ１の上底部として、絶縁体部ＩＰ１と、絶縁体部ＩＰ２と、からなるダイヤフラム構造ＤＦ１が形成され、流量検出部７は、このダイヤフラム構造ＤＦ１からなる。これにより、流量検出部７の熱容量を、小さくすることができ、発熱抵抗体１７が発熱することにより、室温よりも高い温度に加熱された絶縁体部ＩＰ１の温度が、図２を用いて後述する溝部ＴＲ１を流れる空気などの流体の流量に応じて変化する際の温度変化を、精度よく測定することができる。 In the first embodiment, the sensor chip 3 has a hole TH1. The hole TH1 reaches the insulator part IP1, that is, the flow rate detection part 7 through the semiconductor substrate 6 from the back surface 6b of the semiconductor substrate 6 in the region AR1. A diaphragm structure DF1 composed of an insulator part IP1 and an insulator part IP2 is formed as an upper bottom part of the hole part TH1, and the flow rate detection part 7 is made of this diaphragm structure DF1. Thereby, the heat capacity of the flow rate detection unit 7 can be reduced, and the temperature of the insulator part IP1 heated to a temperature higher than room temperature due to the heat generation of the heating resistor 17 will be described later with reference to FIG. The temperature change at the time of changing according to the flow rate of the fluid such as the air flowing through the groove portion TR1 can be accurately measured.
　制御回路部８は、半導体基板６の表面６ａの領域ＡＲ２で、半導体基板６の表面６ａ上に形成されており、流量検出部７を制御する。制御回路部８は、絶縁体部ＩＰ３と、制御回路ＣＲ１と、絶縁体部ＩＰ４と、を有する。 The control circuit unit 8 is formed on the surface 6a of the semiconductor substrate 6 in the area AR2 of the surface 6a of the semiconductor substrate 6, and controls the flow rate detection unit 7. The control circuit unit 8 includes an insulator part IP3, a control circuit CR1, and an insulator part IP4.
　絶縁体部ＩＰ３は、領域ＡＲ２で、半導体基板６の表面６ａ上に形成されている。絶縁体部ＩＰ３は、例えば、絶縁膜１１ｂと、層間絶縁膜１２ｂと、層間絶縁膜１３ｂと、層間絶縁膜１４ｂと、を含む。 The insulator portion IP3 is formed on the surface 6a of the semiconductor substrate 6 in the region AR2. The insulator part IP3 includes, for example, an insulating film 11b, an interlayer insulating film 12b, an interlayer insulating film 13b, and an interlayer insulating film 14b.
　絶縁膜１１ｂは、領域ＡＲ２で、半導体基板６の表面６ａ上に形成された部分の絶縁膜１１からなる。すなわち、絶縁膜１１ｂは、絶縁膜１１ａと同層に形成されている。層間絶縁膜１２ｂは、絶縁膜１１ｂ上に形成された部分の層間絶縁膜１２からなる。すなわち、層間絶縁膜１２ｂは、層間絶縁膜１２ａと同層に形成されている。層間絶縁膜１３ｂは、層間絶縁膜１２ｂ上に形成された部分の層間絶縁膜１３からなる。すなわち、層間絶縁膜１３ｂは、層間絶縁膜１３ａと同層に形成されている。したがって、絶縁体部ＩＰ３は、絶縁体部ＩＰ１と同層に形成されている。また、層間絶縁膜１４ｂは、層間絶縁膜１３ｂ上に形成された部分の層間絶縁膜１４からなる。 The insulating film 11b is formed of a portion of the insulating film 11 formed on the surface 6a of the semiconductor substrate 6 in the region AR2. That is, the insulating film 11b is formed in the same layer as the insulating film 11a. The interlayer insulating film 12b includes a portion of the interlayer insulating film 12 formed on the insulating film 11b. That is, the interlayer insulating film 12b is formed in the same layer as the interlayer insulating film 12a. The interlayer insulating film 13b includes a portion of the interlayer insulating film 13 formed on the interlayer insulating film 12b. That is, the interlayer insulating film 13b is formed in the same layer as the interlayer insulating film 13a. Therefore, the insulator part IP3 is formed in the same layer as the insulator part IP1. The interlayer insulating film 14b is composed of a portion of the interlayer insulating film 14 formed on the interlayer insulating film 13b.
　なお、絶縁膜１１ｂは、絶縁膜１１ａと同層に形成されていなくてもよく、層間絶縁膜１２ｂは、層間絶縁膜１２ａと同層に形成されていなくてもよく、層間絶縁膜１３ｂは、層間絶縁膜１３ａと同層に形成されていなくてもよい。すなわち、絶縁体部ＩＰ３は、絶縁体部ＩＰ１と同層に形成されていなくてもよい。 Note that the insulating film 11b may not be formed in the same layer as the insulating film 11a, the interlayer insulating film 12b may not be formed in the same layer as the interlayer insulating film 12a, and the interlayer insulating film 13b It may not be formed in the same layer as the interlayer insulating film 13a. That is, the insulator part IP3 may not be formed in the same layer as the insulator part IP1.
　制御回路ＣＲ１は、領域ＡＲ２で、絶縁体部ＩＰ３に覆われるように形成されているか、絶縁体部ＩＰ３内に形成されている。制御回路ＣＲ１は、例えば、トランジスタＴｒと、プラグ２１と、配線２２と、プラグ２３と、配線２４と、を含む。 The control circuit CR1 is formed in the region AR2 so as to be covered with the insulator part IP3 or in the insulator part IP3. The control circuit CR1 includes, for example, a transistor Tr, a plug 21, a wiring 22, a plug 23, and a wiring 24.
　トランジスタＴｒは、素子分離膜としての絶縁膜１１ｂにより区画された領域で、半導体基板６の表面６ａに形成されたＭＩＳＦＥＴ（Metal Insulator Semiconductor Field Effect Transistor）からなる。トランジスタＴｒは、拡散層２５と、ゲート絶縁膜２６と、ゲート電極２７と、拡散層２８と、を有する。拡散層２５は、半導体基板６の表面６ａ側に形成されている。ゲート絶縁膜２６は、拡散層２５上に形成されている。ゲート絶縁膜２６は、例えば酸化シリコンからなる。ゲート電極２７は、ゲート絶縁膜２６上に形成されている。ゲート電極２７は、例えば多結晶シリコンからなる。拡散層２８は、ゲート電極２７を挟んで両側に位置する拡散層２５の上層部に、ゲート電極２７と整合して形成されている。拡散層２８は、ソース領域またはドレイン領域として機能する。 The transistor Tr is a region partitioned by an insulating film 11b as an element isolation film, and is formed of a MISFET (Metal Insulator Semiconductor Semiconductor Field Effect Transistor) formed on the surface 6a of the semiconductor substrate 6. The transistor Tr includes a diffusion layer 25, a gate insulating film 26, a gate electrode 27, and a diffusion layer 28. The diffusion layer 25 is formed on the surface 6 a side of the semiconductor substrate 6. The gate insulating film 26 is formed on the diffusion layer 25. The gate insulating film 26 is made of, for example, silicon oxide. The gate electrode 27 is formed on the gate insulating film 26. The gate electrode 27 is made of, for example, polycrystalline silicon. The diffusion layer 28 is formed in alignment with the gate electrode 27 in the upper layer portion of the diffusion layer 25 located on both sides of the gate electrode 27. The diffusion layer 28 functions as a source region or a drain region.
　拡散層２５は、例えばホウ素（Ｂ）などのｐ型不純物またはリン（Ｐ）もしくはヒ素（Ａｓ）などのｎ型不純物が導入されたシリコンからなる。拡散層２８は、例えばリン（Ｐ）もしくはヒ素（Ａｓ）などのｎ型不純物またはホウ素（Ｂ）などのｐ型不純物が導入され、拡散層２５の導電型と反対の導電型を有するシリコンからなる。 The diffusion layer 25 is made of silicon into which a p-type impurity such as boron (B) or an n-type impurity such as phosphorus (P) or arsenic (As) is introduced. The diffusion layer 28 is made of silicon having a conductivity type opposite to the conductivity type of the diffusion layer 25 by introducing an n-type impurity such as phosphorus (P) or arsenic (As) or a p-type impurity such as boron (B). .
　プラグ２１は、層間絶縁膜１２ｂを貫通して、例えばトランジスタＴｒの拡散層２８と電気的に接続されている。配線２２は、層間絶縁膜１２ｂ上に形成されており、プラグ２１と電気的に接続されている。層間絶縁膜１３ｂは、配線２２を覆うように、層間絶縁膜１２ｂ上に形成されている。プラグ２３は、層間絶縁膜１３ｂを貫通して、配線２２と電気的に接続されている。配線２４は、層間絶縁膜１３ｂ上に形成されており、プラグ２３と電気的に接続されている。層間絶縁膜１４ｂは、配線２４を覆うように、層間絶縁膜１３ｂ上に形成されている。プラグ２１およびプラグ２３は、例えば窒化チタン（ＴｉＮ）膜とタングステン（Ｗ）膜との積層膜からなる。配線２２および配線２４は、例えばアルミニウム（Ａｌ）合金膜からなる。配線２２および配線２４の厚さを、例えば４００～８００ｎｍ程度とすることができる。また、例えば図３に示す配線２２ａは、発熱抵抗体１７と制御回路ＣＲ１とを、電気的に接続する。 The plug 21 penetrates the interlayer insulating film 12b and is electrically connected to the diffusion layer 28 of the transistor Tr, for example. The wiring 22 is formed on the interlayer insulating film 12 b and is electrically connected to the plug 21. The interlayer insulating film 13 b is formed on the interlayer insulating film 12 b so as to cover the wiring 22. The plug 23 penetrates the interlayer insulating film 13b and is electrically connected to the wiring 22. The wiring 24 is formed on the interlayer insulating film 13 b and is electrically connected to the plug 23. The interlayer insulating film 14 b is formed on the interlayer insulating film 13 b so as to cover the wiring 24. The plug 21 and the plug 23 are made of, for example, a laminated film of a titanium nitride (TiN) film and a tungsten (W) film. The wiring 22 and the wiring 24 are made of, for example, an aluminum (Al) alloy film. The thickness of the wiring 22 and the wiring 24 can be set to, for example, about 400 to 800 nm. Further, for example, the wiring 22a illustrated in FIG. 3 electrically connects the heating resistor 17 and the control circuit CR1.
　絶縁体部ＩＰ４は、領域ＡＲ２で、絶縁体部ＩＰ３上に形成されている。絶縁体部ＩＰ４は、絶縁膜１５ｂを含む。絶縁膜１５ｂは、領域ＡＲ２で、層間絶縁膜１４ｂ上に形成された部分の絶縁膜１５からなり、領域ＡＲ２で、絶縁体部ＩＰ３上に形成された部分の絶縁膜１５からなる。 The insulator part IP4 is formed on the insulator part IP3 in the area AR2. The insulator part IP4 includes an insulating film 15b. The insulating film 15b is made of the portion of the insulating film 15 formed on the interlayer insulating film 14b in the region AR2, and the portion of the insulating film 15 formed on the insulator portion IP3 in the region AR2.
　本実施の形態１では、センサチップ３は、電極としての電極パッド２９を有する。電極パッド２９は、領域ＡＲ２で、層間絶縁膜１３ｂ上に、配線２４と同層に形成されている。電極パッド２９は、例えばプラグ２３と電気的に接続されることにより、制御回路部８の制御回路ＣＲ１と電気的に接続されている。電極パッド２９は、例えばアルミニウム（Ａｌ）合金膜からなる。 In the first embodiment, the sensor chip 3 has an electrode pad 29 as an electrode. The electrode pad 29 is formed in the same layer as the wiring 24 on the interlayer insulating film 13b in the region AR2. The electrode pad 29 is electrically connected to the control circuit CR1 of the control circuit unit 8 by being electrically connected to the plug 23, for example. The electrode pad 29 is made of, for example, an aluminum (Al) alloy film.
　領域ＡＲ２で、絶縁膜１６、絶縁膜１５および層間絶縁膜１４には、絶縁膜１６、絶縁膜１５および層間絶縁膜１４を貫通して電極パッド２９に達する開口部ＯＰ２が形成されている。すなわち、開口部ＯＰ２は、絶縁体部ＩＰ４、および、電極パッド２９上に位置する部分の絶縁体部ＩＰ３を貫通して、電極パッド２９に達する。開口部ＯＰ２の底部には、電極パッド２９が露出している。 In the region AR2, the insulating film 16, the insulating film 15, and the interlayer insulating film 14 are formed with an opening OP2 that penetrates the insulating film 16, the insulating film 15, and the interlayer insulating film 14 and reaches the electrode pad 29. That is, the opening OP <b> 2 passes through the insulator part IP <b> 4 and a part of the insulator part IP <b> 3 located on the electrode pad 29 and reaches the electrode pad 29. The electrode pad 29 is exposed at the bottom of the opening OP2.
　電極パッド２９には、ボンディングワイヤ４の一端が接続されており、ボンディングワイヤ４の他端は、リードフレーム２の外部端子２ｂと接続されている。したがって、ボンディングワイヤ４は、電極パッド２９と、リードフレーム２の外部端子２ｂとを接続する。また、リードフレーム２の外部端子２ｂは、流量センサ１の外部と電気的に接続される。したがって、電極パッド２９は、ボンディングワイヤ４およびリードフレーム２の外部端子２ｂを介して、流量センサ１の外部と電気的に接続される。 One end of the bonding wire 4 is connected to the electrode pad 29, and the other end of the bonding wire 4 is connected to the external terminal 2 b of the lead frame 2. Therefore, the bonding wire 4 connects the electrode pad 29 and the external terminal 2 b of the lead frame 2. The external terminal 2 b of the lead frame 2 is electrically connected to the outside of the flow sensor 1. Therefore, the electrode pad 29 is electrically connected to the outside of the flow sensor 1 through the bonding wire 4 and the external terminal 2 b of the lead frame 2.
　このようにしてリードフレーム２と電気的に接続されたセンサチップ３、および、リードフレーム２は、樹脂部としてのモールド樹脂５を用いた樹脂モールドにより封止されている。なお、平面視において、孔部ＴＨ１と重なるように配置された部分のリードフレーム２、すなわち搭載部２ａには、孔部ＴＨ２が形成されており、孔部ＴＨ１は、孔部ＴＨ２を介して，流量センサ１の外部と連通している。 Thus, the sensor chip 3 electrically connected to the lead frame 2 and the lead frame 2 are sealed by a resin mold using a mold resin 5 as a resin portion. In a plan view, a hole TH2 is formed in a portion of the lead frame 2 that is disposed so as to overlap the hole TH1, that is, the mounting portion 2a, and the hole TH1 is formed via the hole TH2. It communicates with the outside of the flow sensor 1.
　領域ＡＲ２では、センサチップ３の表面を覆うように、モールド樹脂５が形成されている。領域ＡＲ２では、モールド樹脂５は、絶縁膜１６上に形成されている。すなわち、領域ＡＲ２では、モールド樹脂５は、絶縁体部ＩＰ４上に、絶縁膜１６を介して形成されており、絶縁膜１６および絶縁体部ＩＰ４を覆うように、形成されている。 In the area AR2, a mold resin 5 is formed so as to cover the surface of the sensor chip 3. In the region AR2, the mold resin 5 is formed on the insulating film 16. That is, in the region AR2, the mold resin 5 is formed on the insulator part IP4 via the insulating film 16, and is formed so as to cover the insulating film 16 and the insulator part IP4.
　好適には、絶縁体部ＩＰ１の厚さＴＰ１は、絶縁体部ＩＰ１と同層に形成された絶縁体部ＩＰ３の厚さＴＰ３よりも薄く、領域ＡＲ１で、開口部ＯＰ１が形成されているが、領域ＡＲ２を含めて、領域ＡＲ１の外部の領域では、開口部ＯＰ１が形成されていない。そして、絶縁膜２０は、領域ＡＲ１の外部の領域で、絶縁膜１５の領域ＡＲ１側の端部上に、絶縁膜１６を介して形成されている。すなわち、絶縁体部ＩＰ２は、絶縁体部ＩＰ１上から、絶縁体部ＩＰ４の領域ＡＲ１側の端部上にかけて、直接または絶縁膜１６を介して、連続的に形成されている。これにより、制御回路部８を覆うようにモールド樹脂５を形成するために、モールド成型用金型５１（後述する図１４参照）の空気流路用凸部５４（後述する図１４参照）をセンサチップ３に接触させる際に、空気流路用凸部５４（後述する図１４参照）が流量検出部７に接触することを防止することができる。 Preferably, the thickness TP1 of the insulator part IP1 is smaller than the thickness TP3 of the insulator part IP3 formed in the same layer as the insulator part IP1, and the opening OP1 is formed in the region AR1. The opening OP1 is not formed in the area outside the area AR1 including the area AR2. The insulating film 20 is formed outside the region AR1 and on the end of the insulating film 15 on the region AR1 side via the insulating film 16. That is, the insulator part IP2 is continuously formed directly or via the insulating film 16 from the insulator part IP1 to the end of the insulator part IP4 on the region AR1 side. Thereby, in order to form the mold resin 5 so as to cover the control circuit portion 8, the air flow path convex portion 54 (see FIG. 14 described later) of the molding die 51 (see FIG. 14 described later) is used as a sensor. When contacting the chip 3, the air flow path convex portion 54 (see FIG. 14 described later) can be prevented from contacting the flow rate detection unit 7.
　そして、孔部ＴＨ１が、平面視において、領域ＡＲ１内、すなわち、絶縁体部ＩＰ１が形成された領域内に形成されている場合、絶縁体部ＩＰ１の領域ＡＲ２側の端部が、孔部ＴＨ１の形成された領域の外部に位置することになるので、上記した接触の防止の効果が大きくなる。 When the hole TH1 is formed in the area AR1, that is, in the area where the insulator part IP1 is formed in a plan view, the end of the insulator part IP1 on the area AR2 side is the hole TH1. Therefore, the effect of preventing the contact is increased.
　あるいは、モールド樹脂５が、絶縁体部ＩＰ４および絶縁体部ＩＰ２を覆うように、形成されている場合には、好適には、モールド樹脂５の領域ＡＲ１側の端部は、絶縁体部ＩＰ４上に絶縁膜１６を介して形成された部分の絶縁体部ＩＰ２上に位置する。このような場合、絶縁体部ＩＰ４から露出した部分の絶縁膜１６および絶縁体部ＩＰ３が、さらに、モールド樹脂５に覆われることになるので、上記した接触の防止の効果に加え、制御回路ＣＲ１の配線２４などの腐食を防止する効果を有する。 Alternatively, when the mold resin 5 is formed so as to cover the insulator part IP4 and the insulator part IP2, the end of the mold resin 5 on the region AR1 side is preferably on the insulator part IP4. Is located on the insulator part IP2 of the part formed through the insulating film 16. In such a case, the portion of the insulating film 16 and the insulator portion IP3 exposed from the insulator portion IP4 are further covered with the mold resin 5, so that the control circuit CR1 This has the effect of preventing corrosion of the wiring 24 and the like.
　一方、領域ＡＲ１では、センサチップ３を覆うモールド樹脂５の表面には、溝部ＴＲ１が形成されており、流量検出部７が露出している。流量センサ１は、室温よりも高い温度に加熱された絶縁体部ＩＰ１の温度が、溝部ＴＲ１を方向ＤＲ１（図１参照）に流れる空気などの流体の流量に応じて変化する際の温度変化を、測定することにより、流体の流量を検出する。 On the other hand, in the area AR1, the groove part TR1 is formed on the surface of the mold resin 5 covering the sensor chip 3, and the flow rate detection part 7 is exposed. The flow rate sensor 1 measures the temperature change when the temperature of the insulator part IP1 heated to a temperature higher than room temperature changes according to the flow rate of fluid such as air flowing in the groove part TR1 in the direction DR1 (see FIG. 1). The flow rate of the fluid is detected by measuring.
　なお、平面視において、領域ＡＲ２で、センサチップ３の裏面およびリードフレーム２を覆うように、モールド樹脂５が形成されている。また、平面視において、領域ＡＲ１で、センサチップ３の裏面およびリードフレーム２を覆うモールド樹脂５には、溝部ＴＲ２が形成されており、溝部ＴＲ２の上底部には、平面視において、孔部ＴＨ１と重なるように配置された部分の搭載部２ａが露出している。前述したように、平面視において、孔部ＴＨ１と重なるように配置された部分の搭載部２ａには、孔部ＴＨ２が形成されており、孔部ＴＨ１は、孔部ＴＨ２を介して，流量センサ１の外部と連通している。 Note that the mold resin 5 is formed so as to cover the back surface of the sensor chip 3 and the lead frame 2 in the area AR2 in plan view. Further, in a plan view, a groove portion TR2 is formed in the mold resin 5 that covers the back surface of the sensor chip 3 and the lead frame 2 in the area AR1, and the hole portion TH1 is formed in the upper bottom portion of the trench portion TR2 in the plan view. The portion of the mounting portion 2a that is arranged so as to overlap with is exposed. As described above, the hole portion TH2 is formed in the portion of the mounting portion 2a disposed so as to overlap the hole portion TH1 in plan view, and the hole portion TH1 is connected to the flow rate sensor via the hole portion TH2. 1 communicates with the outside.
　本実施の形態１では、絶縁体部ＩＰ１の厚さＴＰ１に対する絶縁体部ＩＰ２の厚さＴＰ２の比は、絶縁体部ＩＰ３の厚さＴＰ３に対する絶縁体部ＩＰ４の厚さＴＰ４の比よりも大きい。 In the first embodiment, the ratio of the thickness TP2 of the insulator part IP2 to the thickness TP1 of the insulator part IP1 is larger than the ratio of the thickness TP4 of the insulator part IP4 to the thickness TP3 of the insulator part IP3. .
　例えば窒化シリコンからなる絶縁体部ＩＰ２を成膜する際の成膜条件を調整することにより、絶縁体部ＩＰ２が引っ張り応力を有するように、調整することができる。同様に、例えば窒化シリコンからなる絶縁体部ＩＰ４を成膜する際の成膜条件を調整することにより、絶縁体部ＩＰ４が、絶縁体部ＩＰ２の引っ張り応力よりも小さい引っ張り応力を有するか、または、圧縮応力を有するように、調整することができる。 For example, by adjusting the film formation conditions when forming the insulator part IP2 made of silicon nitride, the insulator part IP2 can be adjusted to have a tensile stress. Similarly, the insulator part IP4 has a tensile stress smaller than the tensile stress of the insulator part IP2 by adjusting the film formation conditions when forming the insulator part IP4 made of, for example, silicon nitride, or Can be adjusted to have a compressive stress.
　また、例えば酸化シリコンからなる絶縁体部ＩＰ１を成膜する際の成膜条件を調整することにより、絶縁体部ＩＰ１が、絶縁体部ＩＰ２の引っ張り応力よりも小さい引っ張り応力を有するか、または、圧縮応力を有するように、調整することができる。さらに、例えば酸化シリコンからなる絶縁体部ＩＰ３を成膜する際の成膜条件を調整することにより、絶縁体部ＩＰ３が、絶縁体部ＩＰ２の引っ張り応力よりも小さい引っ張り応力を有するか、または、圧縮応力を有するように、調整することができる。 Further, for example, by adjusting the film formation conditions when forming the insulator part IP1 made of silicon oxide, the insulator part IP1 has a tensile stress smaller than the tensile stress of the insulator part IP2, or It can be adjusted to have a compressive stress. Furthermore, the insulator part IP3 has a tensile stress smaller than the tensile stress of the insulator part IP2, for example, by adjusting the film formation conditions when forming the insulator part IP3 made of silicon oxide, or It can be adjusted to have a compressive stress.
　したがって、絶縁体部ＩＰ１の厚さＴＰ１に対する絶縁体部ＩＰ２の厚さＴＰ２の比が、絶縁体部ＩＰ３の厚さＴＰ３に対する絶縁体部ＩＰ４の厚さＴＰ４の比よりも大きい場合には、例えば絶縁体部ＩＰ３と絶縁体部ＩＰ４との積層体が、引っ張り応力を有するように、調整することができる。また、例えば絶縁体部ＩＰ３と絶縁体部ＩＰ４との積層体が、絶縁体部ＩＰ１と絶縁体部ＩＰ２との積層体の引っ張り応力よりも小さい引っ張り応力を有するか、または、圧縮応力を有するように、調整することができる。これにより、流量検出部７が、引っ張り応力を有するように、調整することができる。または、制御回路部８が、流量検出部７の引っ張り応力よりも小さい引っ張り応力を有するか、または、圧縮応力を有するように、調整することができる。 Therefore, when the ratio of the thickness TP2 of the insulator part IP2 to the thickness TP1 of the insulator part IP1 is larger than the ratio of the thickness TP4 of the insulator part IP4 to the thickness TP3 of the insulator part IP3, for example It can adjust so that the laminated body of insulator part IP3 and insulator part IP4 may have a tensile stress. Further, for example, the laminate of the insulator part IP3 and the insulator part IP4 has a tensile stress smaller than the tensile stress of the laminate of the insulator part IP1 and the insulator part IP2, or has a compressive stress. Can be adjusted. Thereby, the flow volume detection part 7 can be adjusted so that it may have a tensile stress. Or it can adjust so that the control circuit part 8 may have a tensile stress smaller than the tensile stress of the flow volume detection part 7, or may have a compressive stress.
　好適には、絶縁体部ＩＰ２は、引っ張り応力を有する。また、絶縁体部ＩＰ１、絶縁体部ＩＰ３および絶縁体部ＩＰ４は、絶縁体部ＩＰ２の引っ張り応力よりも小さい引っ張り応力を有するか、または、圧縮応力を有する。 Preferably, the insulator part IP2 has a tensile stress. Insulator part IP1, insulator part IP3, and insulator part IP4 have a tensile stress smaller than the tensile stress of insulator part IP2, or have a compressive stress.
　好適には、絶縁体部ＩＰ２の厚さＴＰ２は、絶縁体部ＩＰ４の厚さＴＰ４よりも厚い。これにより、絶縁体部ＩＰ１の厚さＴＰ１に対する絶縁体部ＩＰ２の厚さＴＰ２の比を、絶縁体部ＩＰ３の厚さＴＰ３に対する絶縁体部ＩＰ４の厚さＴＰ４の比よりも、容易に大きくすることができる。 Preferably, the thickness TP2 of the insulator part IP2 is thicker than the thickness TP4 of the insulator part IP4. Thereby, the ratio of the thickness TP2 of the insulator part IP2 to the thickness TP1 of the insulator part IP1 is easily made larger than the ratio of the thickness TP4 of the insulator part IP4 to the thickness TP3 of the insulator part IP3. be able to.
　また、好適には、絶縁体部ＩＰ１の厚さＴＰ１と絶縁体部ＩＰ２の厚さＴＰ２との和は、絶縁体部ＩＰ３の厚さＴＰ３と絶縁体部ＩＰ４の厚さＴＰ４との和よりも小さい。これにより、少なくとも、絶縁体部ＩＰ１の厚さＴＰ１は、絶縁体部ＩＰ１と同層に形成された絶縁体部ＩＰ３の厚さＴＰ３よりも薄くすることができる。 Preferably, the sum of the thickness TP1 of the insulator part IP1 and the thickness TP2 of the insulator part IP2 is greater than the sum of the thickness TP3 of the insulator part IP3 and the thickness TP4 of the insulator part IP4. small. Thereby, at least the thickness TP1 of the insulator part IP1 can be made thinner than the thickness TP3 of the insulator part IP3 formed in the same layer as the insulator part IP1.
　なお、領域ＡＲ２のうち、素子分離膜としての絶縁膜１１ｂで区画された領域内における絶縁体部ＩＰ３の厚さＴＰ３を厚さＴＰ３１とすると、さらに好適には、絶縁体部ＩＰ１の厚さＴＰ１に対する絶縁体部ＩＰ２の厚さＴＰ２の比は、絶縁体部ＩＰ３の厚さＴＰ３１に対する絶縁体部ＩＰ４の厚さＴＰ４の比よりも大きい。これにより、流量検出部７が、引っ張り応力を有するように、さらに容易に調整することができる。また、制御回路部８が、流量検出部７の引っ張り応力よりも小さい引っ張り応力を有するか、または、圧縮応力を有するように、さらに容易に調整することができる。 In the region AR2, if the thickness TP3 of the insulator portion IP3 in the region partitioned by the insulating film 11b as the element isolation film is the thickness TP31, the thickness TP1 of the insulator portion IP1 is more preferable. The ratio of the thickness TP2 of the insulator part IP2 to the thickness is larger than the ratio of the thickness TP4 of the insulator part IP4 to the thickness TP31 of the insulator part IP3. Thereby, the flow volume detection part 7 can be adjusted further easily so that it may have a tensile stress. Further, the control circuit unit 8 can be adjusted more easily so as to have a tensile stress smaller than the tensile stress of the flow rate detection unit 7 or a compressive stress.
　また、本実施の形態１では、絶縁膜１６の厚さは、絶縁体部ＩＰ３の厚さＴＰ３、および、絶縁体部ＩＰ４の厚さＴＰ４に比べて小さいので、絶縁膜１６が圧縮応力を有する場合でも、絶縁膜１６の圧縮応力の影響は、小さい。 In the first embodiment, since the thickness of the insulating film 16 is smaller than the thickness TP3 of the insulator part IP3 and the thickness TP4 of the insulator part IP4, the insulating film 16 has a compressive stress. Even in this case, the influence of the compressive stress of the insulating film 16 is small.
　＜空気流量計＞
　図４は、実施の形態１の流量センサが実装された空気流量計の概略配置図である。図４は、実施の形態１の流量センサが、自動車などの内燃機関の吸気通路としての空気通路に取り付けられた場合の配置を示す。 <Air flow meter>
FIG. 4 is a schematic layout diagram of an air flow meter in which the flow sensor of the first embodiment is mounted. FIG. 4 shows an arrangement when the flow sensor of the first embodiment is attached to an air passage as an intake passage of an internal combustion engine such as an automobile.
　図４に示すように、空気流量計３１は、流量センサ１と、支持体３２と、連結部３３と、を有する。支持体３２は、流量センサ１を支持する。連結部３３は、流量センサ１のリードフレーム２の外部端子２ｂを、支持体３２を介して外部と電気的に接続する。流量センサ１は、空気通路３４の内部に設けられた副通路３５の内部に配置される。吸気空気は、内燃機関の条件によって、図４の矢印で示された空気流の方向ＤＲ１、またはこれとは逆の方向に流れる。 As shown in FIG. 4, the air flow meter 31 includes a flow sensor 1, a support body 32, and a connecting portion 33. The support 32 supports the flow sensor 1. The connecting portion 33 electrically connects the external terminal 2 b of the lead frame 2 of the flow sensor 1 to the outside via the support body 32. The flow sensor 1 is disposed in a sub-passage 35 provided in the air passage 34. The intake air flows in the direction DR1 of the air flow indicated by the arrow in FIG. 4 or in the opposite direction depending on the conditions of the internal combustion engine.
　＜流量センサの製造工程＞
　図５は、実施の形態１の流量センサの製造工程の一部を示す製造プロセスフロー図である。図６～図１４は、実施の形態１の流量センサの製造工程中の要部断面図である。 <Manufacturing process of flow sensor>
FIG. 5 is a manufacturing process flow chart showing a part of the manufacturing process of the flow sensor according to the first embodiment. 6 to 14 are cross-sectional views of relevant parts during the manufacturing process of the flow sensor according to the first embodiment.
　まず、半導体基板６を準備する（図５のステップＳ１１）。このステップＳ１１の工程では、図６に示すように、一方の主面としての表面６ａと、表面６ａと反対側の、他方の主面としての裏面６ｂと、を有する半導体基板６を準備する。半導体基板６は、単結晶シリコン（Ｓｉ）からなる。 First, the semiconductor substrate 6 is prepared (step S11 in FIG. 5). In the step S11, as shown in FIG. 6, a semiconductor substrate 6 having a front surface 6a as one main surface and a back surface 6b as the other main surface opposite to the front surface 6a is prepared. The semiconductor substrate 6 is made of single crystal silicon (Si).
　次に、絶縁体部ＩＰ１および絶縁体部ＩＰ３を形成する（図５のステップＳ１２）。このステップＳ１２の工程では、図６～図９に示すように、半導体基板６の表面６ａの領域ＡＲ１で、半導体基板６の表面６ａ上に絶縁体部ＩＰ１を形成し、半導体基板６の表面６ａの領域ＡＲ２で、半導体基板６の表面６ａ上に、絶縁体部ＩＰ１と同層に、絶縁体部ＩＰ３を形成する。このステップＳ１２の工程では、発熱抵抗体１７を、絶縁体部ＩＰ１と接触するように形成し、絶縁体部ＩＰ３内に、発熱抵抗体１７を制御する制御回路ＣＲ１を形成する。なお、絶縁体部ＩＰ３を、絶縁体部ＩＰ１と同層に形成しなくてもよい。 Next, the insulator part IP1 and the insulator part IP3 are formed (step S12 in FIG. 5). In the process of step S12, as shown in FIGS. 6 to 9, the insulator portion IP1 is formed on the surface 6a of the semiconductor substrate 6 in the region AR1 of the surface 6a of the semiconductor substrate 6, and the surface 6a of the semiconductor substrate 6 is formed. In the region AR2, the insulator part IP3 is formed on the surface 6a of the semiconductor substrate 6 in the same layer as the insulator part IP1. In step S12, the heating resistor 17 is formed so as to be in contact with the insulator part IP1, and the control circuit CR1 for controlling the heating resistor 17 is formed in the insulator part IP3. The insulator part IP3 may not be formed in the same layer as the insulator part IP1.
　まず、図６に示すように、領域ＡＲ１および領域ＡＲ２で、半導体基板６の表面６ａ上に、素子分離膜として、酸化シリコンからなる絶縁膜４１を形成する。 First, as shown in FIG. 6, an insulating film 41 made of silicon oxide is formed as an element isolation film on the surface 6a of the semiconductor substrate 6 in the regions AR1 and AR2.
　まず、半導体基板６を高温の炉体中で熱酸化処理することにより、領域ＡＲ１および領域ＡＲ２で、半導体基板６の表面６ａに、酸化シリコンからなる絶縁膜４１を形成する。このとき、半導体基板６の裏面６ｂにも、酸化シリコンからなる絶縁膜４１が形成される。次に、領域ＡＲ１および領域ＡＲ２で、半導体基板６の表面６ａに形成された絶縁膜４１を覆うように、低圧熱ＣＶＤ（Chemical Vapor Deposition）法を用いて、窒化シリコンからなる絶縁膜４２を形成する。このとき、半導体基板６の裏面６ｂでも、絶縁膜４１を覆うように、窒化シリコンからなる絶縁膜４２が形成される。 First, the semiconductor substrate 6 is thermally oxidized in a high-temperature furnace to form the insulating film 41 made of silicon oxide on the surface 6a of the semiconductor substrate 6 in the regions AR1 and AR2. At this time, an insulating film 41 made of silicon oxide is also formed on the back surface 6 b of the semiconductor substrate 6. Next, an insulating film 42 made of silicon nitride is formed by low-pressure thermal CVD (Chemical Vapor Deposition) so as to cover the insulating film 41 formed on the surface 6a of the semiconductor substrate 6 in the regions AR1 and AR2. To do. At this time, the insulating film 42 made of silicon nitride is also formed on the back surface 6 b of the semiconductor substrate 6 so as to cover the insulating film 41.
　次に、図６に示すように、フォトリソグラフィ法を用いて、絶縁膜４２および絶縁膜４１のパターニングを行う。これにより、領域ＡＲ２の一部で、半導体基板６の表面６ａに形成された絶縁膜４２および絶縁膜４１を残し、領域ＡＲ２の他の部分、および、領域ＡＲ１で、半導体基板６の表面６ａに形成された絶縁膜４２および絶縁膜４１を除去する。次に、半導体基板６を高温の炉体中で熱酸化処理することにより、領域ＡＲ２の他の部分、および、領域ＡＲ１であって、絶縁膜４２および絶縁膜４１が除去された部分の半導体基板６の表面６ａ上に、素子分離膜として、酸化シリコンからなる絶縁膜１１を形成する。絶縁膜１１は、圧縮応力を有する。絶縁膜１１は、例えば絶縁膜４１などに比べて厚い。絶縁膜１１の厚さは、例えば２００～５００ｎｍ程度である。また、絶縁膜１１を、例えば１００ＭＰａ程度の圧縮応力を有する膜とすることができる。 Next, as shown in FIG. 6, the insulating film 42 and the insulating film 41 are patterned by using a photolithography method. Thereby, the insulating film 42 and the insulating film 41 formed on the surface 6a of the semiconductor substrate 6 are left in a part of the region AR2, and the other part of the region AR2 and the surface AR of the semiconductor substrate 6 in the region AR1. The formed insulating film 42 and insulating film 41 are removed. Next, by subjecting the semiconductor substrate 6 to thermal oxidation in a high temperature furnace body, the other part of the region AR2 and the part of the semiconductor substrate in which the insulating film 42 and the insulating film 41 are removed in the region AR1. An insulating film 11 made of silicon oxide is formed on the surface 6a of 6 as an element isolation film. The insulating film 11 has a compressive stress. The insulating film 11 is thicker than the insulating film 41, for example. The thickness of the insulating film 11 is, for example, about 200 to 500 nm. Further, the insulating film 11 can be a film having a compressive stress of about 100 MPa, for example.
　なお、絶縁膜４２および絶縁膜４１に覆われた部分の半導体基板６の表面６ａおよび裏面６ｂには、絶縁膜１１は形成されない。すなわち、絶縁膜４２および絶縁膜４１は、領域ＡＲ２の他の部分、および、領域ＡＲ１で、半導体基板６の表面６ａ上に、選択的に絶縁膜１１を形成するためのマスクとして用いられる。また、領域ＡＲ１で、半導体基板６の表面６ａ上に形成された部分の絶縁膜１１を、絶縁膜１１ａと称し、領域ＡＲ２で、半導体基板６の表面６ａ上に形成された部分の絶縁膜１１を、絶縁膜１１ｂと称する。 Note that the insulating film 11 is not formed on the front surface 6 a and the back surface 6 b of the semiconductor substrate 6 in a portion covered with the insulating film 42 and the insulating film 41. That is, the insulating film 42 and the insulating film 41 are used as a mask for selectively forming the insulating film 11 on the surface 6a of the semiconductor substrate 6 in the other part of the region AR2 and the region AR1. The portion of the insulating film 11 formed on the surface 6a of the semiconductor substrate 6 in the region AR1 is referred to as an insulating film 11a, and the portion of the insulating film 11 formed on the surface 6a of the semiconductor substrate 6 in the region AR2. Is referred to as an insulating film 11b.
　次に、図７に示すように、平面視において、領域ＡＲ１と重なるように、絶縁膜１１上に、発熱抵抗体１７を形成し、領域ＡＲ２で、トランジスタＴｒを形成する。 Next, as shown in FIG. 7, the heating resistor 17 is formed on the insulating film 11 so as to overlap the region AR1 in plan view, and the transistor Tr is formed in the region AR2.
　まず、図７に示すように、絶縁膜１１を形成するためのマスクとして用いられた絶縁膜４２および絶縁膜４１を除去する。次に、イオン注入法を用いて、領域ＡＲ２で、半導体基板６の表面６ａに、ホウ素（Ｂ）などのｐ型不純物またはリン（Ｐ）もしくはヒ素（Ａｓ）などのｎ型不純物を導入する。これにより、領域ＡＲ２の一部であって、絶縁膜１１が形成されていない部分の半導体基板６の表面６ａに、拡散層２５を形成する。拡散層２５は、ｐ型またはｎ型の導電型を有するシリコンからなる。 First, as shown in FIG. 7, the insulating film 42 and the insulating film 41 used as a mask for forming the insulating film 11 are removed. Next, using an ion implantation method, a p-type impurity such as boron (B) or an n-type impurity such as phosphorus (P) or arsenic (As) is introduced into the surface 6a of the semiconductor substrate 6 in the region AR2. Thereby, the diffusion layer 25 is formed on the surface 6a of the semiconductor substrate 6 in a part of the region AR2 where the insulating film 11 is not formed. The diffusion layer 25 is made of silicon having p-type or n-type conductivity.
　次に、図７に示すように、半導体基板６を高温の炉体中で熱処理することにより、領域ＡＲ２で、拡散層２５上に、酸化シリコンからなる絶縁膜２６ａを形成する。次に、領域ＡＲ１および領域ＡＲ２で、絶縁膜１１上および絶縁膜２６ａ上に、例えば多結晶シリコンからなる導体膜２７ａを形成する。次に、フォトリソグラフィ法およびドライエッチング法を用いて、導体膜２７ａおよび絶縁膜２６ａのパターニングを行う。これにより、平面視において、領域ＡＲ１と重なるように、導体膜２７ａからなる発熱抵抗体１７を形成し、領域ＡＲ２で、導体膜２７ａからなるゲート電極２７、および、絶縁膜２６ａからなるゲート絶縁膜２６を形成する。発熱抵抗体１７は、流量検出部７（後述する図１１参照）を形成する。 Next, as shown in FIG. 7, the semiconductor substrate 6 is heat-treated in a high-temperature furnace to form an insulating film 26a made of silicon oxide on the diffusion layer 25 in the region AR2. Next, a conductor film 27a made of, for example, polycrystalline silicon is formed on the insulating film 11 and the insulating film 26a in the regions AR1 and AR2. Next, the conductor film 27a and the insulating film 26a are patterned using a photolithography method and a dry etching method. Thus, the heating resistor 17 made of the conductor film 27a is formed so as to overlap the area AR1 in plan view, and the gate electrode 27 made of the conductor film 27a and the gate insulating film made of the insulating film 26a are formed in the area AR2. 26 is formed. The heating resistor 17 forms a flow rate detector 7 (see FIG. 11 described later).
　なお、流量検出部７に含まれる発熱抵抗体１７に要求される抵抗特性、および、制御回路部８に含まれるトランジスタＴｒに要求されるトランジスタ特性によっても異なるが、ゲート絶縁膜２６の厚さは、例えば５～５０ｎｍ程度であり、ゲート電極２７および発熱抵抗体１７の厚さは、例えば１００～３００ｎｍ程度である。 The thickness of the gate insulating film 26 varies depending on the resistance characteristics required for the heating resistor 17 included in the flow rate detection unit 7 and the transistor characteristics required for the transistor Tr included in the control circuit unit 8. For example, the thickness is about 5 to 50 nm, and the thicknesses of the gate electrode 27 and the heating resistor 17 are about 100 to 300 nm, for example.
　次に、図７に示すように、イオン注入法を用いて、領域ＡＲ２で、ゲート電極２７を挟んで両側に位置する拡散層２５の上層部に、例えばリン（Ｐ）もしくはヒ素（Ａｓ）などのｎ型不純物またはホウ素（Ｂ）などのｐ型不純物、すなわち拡散層２５の導電型と反対の導電型の不純物を導入する。これにより、領域ＡＲ２の一部であって、絶縁膜１１が形成されていない部分の半導体基板６の表面６ａに、拡散層２８を形成する。すなわち、拡散層２８は、ゲート電極２７を挟んで両側に位置する拡散層２５の上層部に、ゲート電極２７と整合して形成される。拡散層２８は、ソース領域またはドレイン領域として機能する。拡散層２８は、拡散層２５の導電型と反対の導電型を有するシリコンからなる。これにより、拡散層２５と、ゲート絶縁膜２６と、ゲート電極２７と、拡散層２８と、を有するトランジスタＴｒが形成される。トランジスタＴｒは、制御回路部８（後述する図１０参照）を形成する。図７に示す例では、複数のトランジスタＴｒが形成される。 Next, as shown in FIG. 7, for example, phosphorus (P) or arsenic (As) is formed on the upper layer portion of the diffusion layer 25 located on both sides of the gate electrode 27 in the region AR <b> 2 by ion implantation. N-type impurities or p-type impurities such as boron (B), that is, impurities having a conductivity type opposite to that of the diffusion layer 25 are introduced. Thus, the diffusion layer 28 is formed on the surface 6a of the semiconductor substrate 6 in a part of the region AR2 where the insulating film 11 is not formed. That is, the diffusion layer 28 is formed in alignment with the gate electrode 27 in the upper layer portion of the diffusion layer 25 located on both sides of the gate electrode 27. The diffusion layer 28 functions as a source region or a drain region. The diffusion layer 28 is made of silicon having a conductivity type opposite to that of the diffusion layer 25. As a result, a transistor Tr having the diffusion layer 25, the gate insulating film 26, the gate electrode 27, and the diffusion layer 28 is formed. The transistor Tr forms a control circuit unit 8 (see FIG. 10 described later). In the example shown in FIG. 7, a plurality of transistors Tr are formed.
　なお、複数のトランジスタＴｒの各々に要求されるトランジスタ特性を変える場合は、拡散層２５または拡散層２８に導入される不純物の不純物濃度、ゲート絶縁膜２６の厚さ、ゲート電極２７の材料を変更しながら、図７を用いて説明したトランジスタの製造工程を繰り返す。これにより、互いに異なるトランジスタ特性を有する複数のトランジスタＴｒを形成することができる。 When changing the transistor characteristics required for each of the plurality of transistors Tr, the impurity concentration of impurities introduced into the diffusion layer 25 or the diffusion layer 28, the thickness of the gate insulating film 26, and the material of the gate electrode 27 are changed. However, the transistor manufacturing process described with reference to FIG. 7 is repeated. Thereby, a plurality of transistors Tr having different transistor characteristics can be formed.
　次に、図８に示すように、領域ＡＲ１および領域ＡＲ２で、絶縁膜１１上または半導体基板６の表面６ａ上に、層間絶縁膜１２を形成し、形成された層間絶縁膜１２の上面を平坦化する。 Next, as shown in FIG. 8, an interlayer insulating film 12 is formed on the insulating film 11 or the surface 6a of the semiconductor substrate 6 in the regions AR1 and AR2, and the upper surface of the formed interlayer insulating film 12 is flattened. Turn into.
　この層間絶縁膜１２を形成する工程では、酸化シリコンからなる層間絶縁膜１２を、例えばプラズマＣＶＤ法により、または、ＴＥＯＳ（Tetra Ethoxy Silane）を原料とし、プラズマを用いた低温ＣＶＤ法により、形成することができる。あるいは、層間絶縁膜１２として、例えばホウ素（Ｂ）またはリン（Ｐ）を含む層間絶縁膜１２を形成することができる。層間絶縁膜１２の厚さを、例えば５００～１０００ｎｍ程度とすることができる。また、層間絶縁膜１２を、例えば１００ＭＰａ程度の圧縮応力を有する膜とすることができる。 In the step of forming the interlayer insulating film 12, the interlayer insulating film 12 made of silicon oxide is formed by, for example, a plasma CVD method or a low temperature CVD method using plasma using TEOS (Tetra Ethoxy Silane) as a raw material. be able to. Alternatively, as the interlayer insulating film 12, for example, an interlayer insulating film 12 containing boron (B) or phosphorus (P) can be formed. The thickness of the interlayer insulating film 12 can be set to, for example, about 500 to 1000 nm. Further, the interlayer insulating film 12 can be a film having a compressive stress of about 100 MPa, for example.
　また、形成された層間絶縁膜１２の上面を平坦化する工程では、形成された層間絶縁膜１２の上面を、ＣＭＰ（Chemical Mechanical Polishing）法またはエッチバック法により、平坦化することができる。 In the step of planarizing the upper surface of the formed interlayer insulating film 12, the upper surface of the formed interlayer insulating film 12 can be planarized by a CMP (Chemical Mechanical Polishing) method or an etch back method.
　このようにして、平坦化された層間絶縁膜１２を形成することにより、図８に示すように、領域ＡＲ１で、発熱抵抗体１７の一部を覆うように、絶縁膜１１ａ上に、層間絶縁膜１２からなる層間絶縁膜１２ａが形成される。また、領域ＡＲ２で、発熱抵抗体１７の他の部分を覆うように、絶縁膜１１ｂ上に、層間絶縁膜１２ａと同層に、層間絶縁膜１２からなる層間絶縁膜１２ｂが形成される。さらに、領域ＡＲ２で、トランジスタＴｒを覆うように、半導体基板６の表面６ａ上に、層間絶縁膜１２ａと同層に、層間絶縁膜１２からなる層間絶縁膜１２ｂが形成される。 By forming the planarized interlayer insulating film 12 in this manner, the interlayer insulating film 11a is covered with the interlayer insulating film 11a so as to cover a part of the heating resistor 17 in the area AR1 as shown in FIG. An interlayer insulating film 12a made of the film 12 is formed. In addition, an interlayer insulating film 12b made of the interlayer insulating film 12 is formed on the insulating film 11b in the same layer as the interlayer insulating film 12a so as to cover the other part of the heating resistor 17 in the region AR2. Further, an interlayer insulating film 12b made of the interlayer insulating film 12 is formed on the surface 6a of the semiconductor substrate 6 in the same layer as the interlayer insulating film 12a so as to cover the transistor Tr in the region AR2.
　次に、図８に示すように、プラグ２１を形成する。このプラグ２１を形成する工程では、領域ＡＲ２で、層間絶縁膜１２に、層間絶縁膜１２を貫通して、発熱抵抗体１７、トランジスタＴｒのゲート電極２７、および、ソース領域またはドレイン領域として機能する拡散層２８の各々に達する複数のコンタクト孔を形成する。次に、例えば窒化チタン（ＴｉＮ）膜を、複数のコンタクト孔の各々の内壁に、スパッタ法またはＣＶＤ法により形成する。次に、例えばタングステン（Ｗ）膜を、複数のコンタクト孔の各々を埋め込むように、形成する。これにより、複数のコンタクト孔の各々の内部は、例えばタングステン膜および窒化チタン膜からなる金属膜２１ａにより埋め込まれる。次に、コンタクト孔の外部に位置する部分の金属膜２１ａを、エッチバック法またはＣＭＰ法により除去する。 Next, as shown in FIG. 8, a plug 21 is formed. In the step of forming the plug 21, in the region AR2, the interlayer insulating film 12 penetrates the interlayer insulating film 12, and functions as the heating resistor 17, the gate electrode 27 of the transistor Tr, and the source region or the drain region. A plurality of contact holes reaching each of the diffusion layers 28 are formed. Next, for example, a titanium nitride (TiN) film is formed on the inner wall of each of the plurality of contact holes by sputtering or CVD. Next, for example, a tungsten (W) film is formed so as to embed each of the plurality of contact holes. Thereby, the inside of each of the plurality of contact holes is filled with the metal film 21a made of, for example, a tungsten film and a titanium nitride film. Next, a portion of the metal film 21a located outside the contact hole is removed by an etch back method or a CMP method.
　これにより、領域ＡＲ２で、層間絶縁膜１２に、金属膜２１ａからなり、層間絶縁膜１２を貫通して、発熱抵抗体１７、トランジスタＴｒのゲート電極２７、および、ソース領域またはドレイン領域として機能する拡散層２８の各々に達するプラグ２１が形成される。 Thus, in the region AR2, the interlayer insulating film 12 is made of the metal film 21a and penetrates the interlayer insulating film 12, and functions as the heating resistor 17, the gate electrode 27 of the transistor Tr, and the source region or the drain region. Plugs 21 reaching each of the diffusion layers 28 are formed.
　次に、図８に示すように、配線２２を形成する。この配線２２を形成する工程では、領域ＡＲ１および領域ＡＲ２で、層間絶縁膜１２上に、例えばアルミニウム（Ａｌ）合金膜からなる導体膜２２ｂを形成する。導体膜２２ｂの厚さを、例えば４００～８００ｎｍ程度とすることができる。 Next, as shown in FIG. 8, the wiring 22 is formed. In the step of forming the wiring 22, a conductor film 22b made of, for example, an aluminum (Al) alloy film is formed on the interlayer insulating film 12 in the regions AR1 and AR2. The thickness of the conductor film 22b can be set to, for example, about 400 to 800 nm.
　なお、導体膜２２ｂを形成する前に、例えばアルゴン（Ａｒ）ガスにより、層間絶縁膜１２の上面を、スパッタエッチングしてもよい。これにより、コンタクト孔内に埋め込まれた金属膜２１ａからなるプラグ２１と、導体膜２２ｂとを、電気的に低抵抗で接触させることができる。 In addition, before forming the conductor film 22b, the upper surface of the interlayer insulating film 12 may be sputter-etched with, for example, argon (Ar) gas. As a result, the plug 21 made of the metal film 21a embedded in the contact hole and the conductor film 22b can be brought into electrical contact with low resistance.
　あるいは、例えばアルミニウム合金膜を形成する前に、例えば窒化チタン膜などのバリア金属膜を形成することにより、バリア金属膜と、バリア金属膜上のアルミニウム合金膜との２層からなる積層膜としての導体膜２２ｂを形成してもよい。または、バリア金属膜と、バリア金属膜上のアルミニウム合金膜とに加え、アルミニウム合金膜上に例えば窒化チタン膜などのバリア金属膜をさらにもう１層形成することにより、３層からなる積層膜としての導体膜２２ｂを形成してもよい。これらの方法により、プラグ２１と、導体膜２２ｂとを、さらに確実に電気的に低抵抗で接触させることができる。 Alternatively, for example, by forming a barrier metal film such as a titanium nitride film before forming an aluminum alloy film, a laminated film composed of two layers of a barrier metal film and an aluminum alloy film on the barrier metal film is formed. The conductor film 22b may be formed. Alternatively, in addition to the barrier metal film and the aluminum alloy film on the barrier metal film, another layer of a barrier metal film such as a titanium nitride film is formed on the aluminum alloy film to form a laminated film having three layers. The conductor film 22b may be formed. By these methods, the plug 21 and the conductor film 22b can be more reliably brought into electrical contact with low resistance.
　なお、バリア金属膜の厚さは、２００ｎｍ以下であることが望ましい。また、バリア金属膜として窒化チタン膜を例示したが、バリア金属膜として、チタンタングステン（ＴｉＷ）膜、チタン（Ｔｉ）膜、または、チタンタングステン膜とチタン膜との積層膜を用いることができる。 Note that the thickness of the barrier metal film is preferably 200 nm or less. Although a titanium nitride film is exemplified as the barrier metal film, a titanium tungsten (TiW) film, a titanium (Ti) film, or a stacked film of a titanium tungsten film and a titanium film can be used as the barrier metal film.
　なお、本実施の形態１では、発熱抵抗体１７が、ゲート電極２７と同層に形成され、多結晶シリコンからなる場合を例示して説明した。しかし、発熱抵抗体１７が、例えばゲート電極２７とは異なる層に形成されてもよい。 In the first embodiment, the case where the heating resistor 17 is formed in the same layer as the gate electrode 27 and is made of polycrystalline silicon has been described as an example. However, the heating resistor 17 may be formed in a layer different from the gate electrode 27, for example.
　また、発熱抵抗体１７が、アルファタンタル（α-Ｔａ）、チタン（Ｔｉ）、タングステン（Ｗ）、コバルト（Ｃｏ）、ニッケル（Ｎｉ）、鉄（Ｆｅ）、ニオブ（Ｎｂ）、ハフニウム（Ｈｆ）、クロム（Ｃｒ）またはジルコニウム（Ｚｒ）を主成分とする金属膜からなるものであってもよい。あるいは、発熱抵抗体１７が、窒化タンタル（ＴａＮ）、窒化モリブデン（ＭｏＮ）または窒化タングステン（ＷＮ）などの金属窒化化合物からなるものであってもよい。あるいは、発熱抵抗体１７が、モリブデンシリサイド（ＭｏＳｉ)、コバルトシリサイド（ＣｏＳｉ）またはニッケルシリサイド（ＮｉＳｉ）などの金属シリサイド化合物からなるものであってもよい。 Further, the heating resistor 17 has alpha tantalum (α-Ta), titanium (Ti), tungsten (W), cobalt (Co), nickel (Ni), iron (Fe), niobium (Nb), hafnium (Hf). Further, it may be made of a metal film mainly composed of chromium (Cr) or zirconium (Zr). Alternatively, the heating resistor 17 may be made of a metal nitride compound such as tantalum nitride (TaN), molybdenum nitride (MoN), or tungsten nitride (WN). Alternatively, the heating resistor 17 may be made of a metal silicide compound such as molybdenum silicide (MoSi), cobalt silicide (CoSi), or nickel silicide (NiSi).
　次に、フォトリソグラフィ法、および、ドライエッチング法またはウェットエッチング法を用いて、導体膜２２ｂをパターニングする。これにより、図８に示すように、導体膜２２ｂからなる配線２２を形成する。 Next, the conductive film 22b is patterned by using a photolithography method and a dry etching method or a wet etching method. As a result, as shown in FIG. 8, the wiring 22 made of the conductor film 22b is formed.
　次に、図９に示すように、領域ＡＲ１および領域ＡＲ２で、配線２２を覆うように、層間絶縁膜１２上に、層間絶縁膜１３を形成し、形成された層間絶縁膜１３の上面を平坦化する。 Next, as shown in FIG. 9, an interlayer insulating film 13 is formed on the interlayer insulating film 12 so as to cover the wiring 22 in the regions AR1 and AR2, and the upper surface of the formed interlayer insulating film 13 is flattened. Turn into.
　この層間絶縁膜１３を形成する工程では、層間絶縁膜１２を形成する工程と同様に、酸化シリコンからなる層間絶縁膜１３を、例えばプラズマＣＶＤ法により、または、ＴＥＯＳを原料とし、プラズマを用いた低温ＣＶＤ法により、形成することができる。層間絶縁膜１３の厚さを、例えば５００～１０００ｎｍ程度とすることができる。また、層間絶縁膜１３を、例えば１００ＭＰａ程度の圧縮応力を有する膜とすることができる。 In the step of forming the interlayer insulating film 13, as in the step of forming the interlayer insulating film 12, the interlayer insulating film 13 made of silicon oxide is formed by, for example, plasma CVD or using TEOS as a raw material. It can be formed by a low temperature CVD method. The thickness of the interlayer insulating film 13 can be set to, for example, about 500 to 1000 nm. The interlayer insulating film 13 can be a film having a compressive stress of about 100 MPa, for example.
　また、形成された層間絶縁膜１３の上面を平坦化する工程では、層間絶縁膜１２の上面を平坦化する工程と同様に、形成された層間絶縁膜１３の上面を、ＣＭＰ法またはエッチバック法により、平坦化することができる。 Further, in the step of planarizing the upper surface of the formed interlayer insulating film 13, the upper surface of the formed interlayer insulating film 13 is subjected to the CMP method or the etch back method in the same manner as the step of planarizing the upper surface of the interlayer insulating film 12. Thus, planarization can be performed.
　このようにして、平坦化された層間絶縁膜１３を形成することにより、図９に示すように、領域ＡＲ１で、層間絶縁膜１２ａ上に、層間絶縁膜１３からなる層間絶縁膜１３ａが形成される。また、領域ＡＲ２で、配線２２を覆うように、層間絶縁膜１２ｂ上に、層間絶縁膜１３ａと同層に、層間絶縁膜１３からなる層間絶縁膜１３ｂが形成される。 By forming the flattened interlayer insulating film 13 in this way, an interlayer insulating film 13a made of the interlayer insulating film 13 is formed on the interlayer insulating film 12a in the region AR1, as shown in FIG. The Further, an interlayer insulating film 13b made of the interlayer insulating film 13 is formed on the interlayer insulating film 12b in the same layer as the interlayer insulating film 13a so as to cover the wiring 22 in the region AR2.
　次に、図９に示すように、プラグ２３を形成する。このプラグ２３を形成する工程では、領域ＡＲ２で、層間絶縁膜１３に、層間絶縁膜１３を貫通して、配線２２に達するプラグ２３を形成する。このプラグ２３を形成する工程は、プラグ２１を形成する工程と同様にすることができる。 Next, as shown in FIG. 9, a plug 23 is formed. In the step of forming the plug 23, the plug 23 reaching the wiring 22 through the interlayer insulating film 13 is formed in the interlayer insulating film 13 in the region AR2. The step of forming the plug 23 can be the same as the step of forming the plug 21.
　次に、図９に示すように、配線２４を形成する。この配線２４を形成する工程は、配線２２を形成する工程と同様に、領域ＡＲ１および領域ＡＲ２で、層間絶縁膜１３上に、例えばアルミニウム（Ａｌ）合金膜からなる導体膜２４ａを形成した後、フォトリソグラフィ法、および、ドライエッチング法またはウェットエッチング法を用いて、導体膜２４ａをパターニングする。導体膜２４ａの厚さを、例えば４００～８００ｎｍ程度とすることができる。これにより、図９に示すように、導体膜２４ａからなる配線２４を形成する。 Next, as shown in FIG. 9, the wiring 24 is formed. In the step of forming the wiring 24, as in the step of forming the wiring 22, the conductor film 24a made of, for example, an aluminum (Al) alloy film is formed on the interlayer insulating film 13 in the regions AR1 and AR2. The conductor film 24a is patterned using a photolithography method and a dry etching method or a wet etching method. The thickness of the conductor film 24a can be set to, for example, about 400 to 800 nm. As a result, as shown in FIG. 9, the wiring 24 made of the conductor film 24a is formed.
　なお、このとき、導体膜２４ａからなる電極パッド２９が形成される。また、トランジスタＴｒ、プラグ２１、配線２２、プラグ２３および配線２４を含む制御回路ＣＲ１が形成される。 At this time, an electrode pad 29 made of the conductor film 24a is formed. Further, the control circuit CR1 including the transistor Tr, the plug 21, the wiring 22, the plug 23, and the wiring 24 is formed.
　次に、図９に示すように、領域ＡＲ１および領域ＡＲ２で、配線２４を覆うように、層間絶縁膜１３上に、層間絶縁膜１４を形成し、形成された層間絶縁膜１４の上面を平坦化する。 Next, as shown in FIG. 9, the interlayer insulating film 14 is formed on the interlayer insulating film 13 so as to cover the wiring 24 in the regions AR1 and AR2, and the upper surface of the formed interlayer insulating film 14 is flattened. Turn into.
　この層間絶縁膜１４を形成する工程では、層間絶縁膜１２を形成する工程と同様に、酸化シリコンからなる層間絶縁膜１４を、例えばプラズマＣＶＤ法により、または、ＴＥＯＳを原料とし、プラズマを用いた低温ＣＶＤ法により、形成することができる。層間絶縁膜１４の厚さを、例えば３００～１０００ｎｍ程度とすることができる。また、層間絶縁膜１４を、例えば１００ＭＰａ程度の圧縮応力を有する膜とすることができる。 In the step of forming the interlayer insulating film 14, as in the step of forming the interlayer insulating film 12, the interlayer insulating film 14 made of silicon oxide is formed by, for example, plasma CVD or using TEOS as a raw material. It can be formed by a low temperature CVD method. The thickness of the interlayer insulating film 14 can be set to, for example, about 300 to 1000 nm. Further, the interlayer insulating film 14 can be a film having a compressive stress of about 100 MPa, for example.
　また、形成された層間絶縁膜１４の上面を平坦化する工程では、層間絶縁膜１２の上面を平坦化する工程と同様に、形成された層間絶縁膜１４の上面を、ＣＭＰ法またはエッチバック法により、平坦化することができる。 Further, in the step of flattening the upper surface of the formed interlayer insulating film 14, the upper surface of the formed interlayer insulating film 14 is subjected to the CMP method or the etch back method in the same manner as the step of flattening the upper surface of the interlayer insulating film 12. Thus, planarization can be performed.
　このようにして、平坦化された層間絶縁膜１４を形成することにより、図９に示すように、領域ＡＲ１で、層間絶縁膜１３ａ上に、層間絶縁膜１４からなる層間絶縁膜１４ａが形成される。また、領域ＡＲ２で、配線２４を覆うように、層間絶縁膜１３ｂ上に、層間絶縁膜１４ａと同層に、層間絶縁膜１４からなる層間絶縁膜１４ｂが形成される。 By forming the flattened interlayer insulating film 14 in this way, an interlayer insulating film 14a made of the interlayer insulating film 14 is formed on the interlayer insulating film 13a in the region AR1, as shown in FIG. The Further, an interlayer insulating film 14b made of the interlayer insulating film 14 is formed in the same layer as the interlayer insulating film 14a on the interlayer insulating film 13b so as to cover the wiring 24 in the region AR2.
　絶縁膜１１を形成する工程から、層間絶縁膜１４を形成する工程までの工程を行うことにより、領域ＡＲ１で、絶縁膜１１ａと、層間絶縁膜１２ａと、層間絶縁膜１３ａと、層間絶縁膜１４ａと、を含む絶縁体部ＩＰ１が形成される。絶縁膜１１ａは、領域ＡＲ１で、半導体基板６の表面６ａ上に形成された部分の絶縁膜１１からなる。層間絶縁膜１２ａは、絶縁膜１１ａ上に形成された部分の層間絶縁膜１２からなる。層間絶縁膜１３ａは、層間絶縁膜１２ａ上に形成された部分の層間絶縁膜１３からなる。層間絶縁膜１４ａは、層間絶縁膜１３ａ上に形成された部分の層間絶縁膜１４からなる。 By performing the steps from the step of forming the insulating film 11 to the step of forming the interlayer insulating film 14, in the region AR1, the insulating film 11a, the interlayer insulating film 12a, the interlayer insulating film 13a, and the interlayer insulating film 14a Insulator part IP1 is formed. The insulating film 11a is the region AR1 and is formed of a portion of the insulating film 11 formed on the surface 6a of the semiconductor substrate 6. The interlayer insulating film 12a includes a portion of the interlayer insulating film 12 formed on the insulating film 11a. The interlayer insulating film 13a is composed of a portion of the interlayer insulating film 13 formed on the interlayer insulating film 12a. The interlayer insulating film 14a includes a portion of the interlayer insulating film 14 formed on the interlayer insulating film 13a.
　また、領域ＡＲ２で、絶縁膜１１ｂと、層間絶縁膜１２ｂと、層間絶縁膜１３ｂと、層間絶縁膜１４ｂと、を含む絶縁体部ＩＰ３が形成される。絶縁膜１１ｂは、領域ＡＲ２で、半導体基板６の表面６ａ上に形成された部分の絶縁膜１１からなる。層間絶縁膜１２ｂは、絶縁膜１１ｂ上に形成された部分の層間絶縁膜１２からなる。層間絶縁膜１３ｂは、層間絶縁膜１２ｂ上に形成された部分の層間絶縁膜１３からなる。層間絶縁膜１４ｂは、層間絶縁膜１３ｂ上に形成された部分の層間絶縁膜１４からなる。 Further, in the region AR2, the insulator part IP3 including the insulating film 11b, the interlayer insulating film 12b, the interlayer insulating film 13b, and the interlayer insulating film 14b is formed. The insulating film 11b is composed of a portion of the insulating film 11 formed on the surface 6a of the semiconductor substrate 6 in the region AR2. The interlayer insulating film 12b includes a portion of the interlayer insulating film 12 formed on the insulating film 11b. The interlayer insulating film 13b includes a portion of the interlayer insulating film 13 formed on the interlayer insulating film 12b. The interlayer insulating film 14b includes a portion of the interlayer insulating film 14 formed on the interlayer insulating film 13b.
　絶縁膜１１ｂは、絶縁膜１１ａと同層に形成される。層間絶縁膜１２ｂは、層間絶縁膜１２ａと同層に形成される。層間絶縁膜１３ｂは、層間絶縁膜１３ａと同層に形成される。したがって、絶縁体部ＩＰ３は、絶縁体部ＩＰ１と同層に形成される。 The insulating film 11b is formed in the same layer as the insulating film 11a. The interlayer insulating film 12b is formed in the same layer as the interlayer insulating film 12a. The interlayer insulating film 13b is formed in the same layer as the interlayer insulating film 13a. Therefore, the insulator part IP3 is formed in the same layer as the insulator part IP1.
　なお、領域ＡＲ２で、半導体基板６の表面６ａ上に、絶縁体部ＩＰ１と同層に絶縁体部ＩＰ３を形成する工程は、領域ＡＲ１で、半導体基板６の表面６ａ上に、絶縁体部ＩＰ１を形成する工程と同一の工程により、行ってもよい。あるいは、領域ＡＲ２で、半導体基板６の表面６ａ上に、絶縁体部ＩＰ１と同層に絶縁体部ＩＰ３を形成する工程は、領域ＡＲ１で、半導体基板６の表面６ａ上に、絶縁体部ＩＰ１を形成する工程と異なる工程により、行ってもよい。 In the region AR2, the step of forming the insulator portion IP3 in the same layer as the insulator portion IP1 on the surface 6a of the semiconductor substrate 6 is performed in the region AR1 on the surface 6a of the semiconductor substrate 6 in the region AR1. You may carry out by the same process as the process of forming. Alternatively, the step of forming the insulator portion IP3 in the same layer as the insulator portion IP1 on the surface 6a of the semiconductor substrate 6 in the region AR2 is performed on the surface 6a of the semiconductor substrate 6 in the region AR1. You may perform by the process different from the process of forming.
　次に、絶縁膜１５を形成する（図５のステップＳ１３）。このステップＳ１３の工程では、図１０に示すように、領域ＡＲ１および領域ＡＲ２で、絶縁体部ＩＰ１上、および、絶縁体部ＩＰ３上に、絶縁膜１５を形成する。具体的には、例えばプラズマを用いた低温ＣＶＤ法により、層間絶縁膜１４上に、窒化シリコンからなる絶縁膜１５を形成することができる。絶縁膜１５は、領域ＡＲ１で、層間絶縁膜１４ａ上に形成され、領域ＡＲ２で、層間絶縁膜１４ｂ上に形成される。 Next, the insulating film 15 is formed (step S13 in FIG. 5). In the process of step S13, as shown in FIG. 10, the insulating film 15 is formed on the insulator part IP1 and the insulator part IP3 in the area AR1 and the area AR2. Specifically, the insulating film 15 made of silicon nitride can be formed on the interlayer insulating film 14 by, for example, a low temperature CVD method using plasma. The insulating film 15 is formed on the interlayer insulating film 14a in the region AR1, and is formed on the interlayer insulating film 14b in the region AR2.
　このとき、領域ＡＲ２で、絶縁膜１５ｂを含む絶縁体部ＩＰ４が形成される。絶縁膜１５ｂは、層間絶縁膜１４ｂ上、すなわち、絶縁体部ＩＰ３上に形成された部分の絶縁膜１５からなる。また、領域ＡＲ２で、半導体基板６の表面６ａ上に、絶縁体部ＩＰ３と、制御回路ＣＲ１と、絶縁体部ＩＰ４と、を有する制御回路部８が、形成される。すなわち、制御回路部８を形成する工程は、絶縁体部ＩＰ３を形成する工程と、制御回路ＣＲ１を形成する工程と、絶縁体部ＩＰ４を形成する工程と、を有する。 At this time, the insulator part IP4 including the insulating film 15b is formed in the region AR2. The insulating film 15b is composed of a portion of the insulating film 15 formed on the interlayer insulating film 14b, that is, on the insulator portion IP3. In the region AR2, the control circuit unit 8 including the insulator part IP3, the control circuit CR1, and the insulator part IP4 is formed on the surface 6a of the semiconductor substrate 6. That is, the process of forming the control circuit unit 8 includes a process of forming the insulator part IP3, a process of forming the control circuit CR1, and a process of forming the insulator part IP4.
　一方、領域ＡＲ１では、絶縁体部ＩＰ１上に、絶縁膜１５ｂを含む絶縁体部ＩＰ４と同層に、絶縁膜１５が形成される。 On the other hand, in the region AR1, the insulating film 15 is formed on the insulator portion IP1 in the same layer as the insulator portion IP4 including the insulating film 15b.
　例えばバイアス電圧または原料ガスの流量を調整し、絶縁膜１５を成膜する際の成膜速度を調整することにより、例えば１００ＭＰａ程度の圧縮応力を有する絶縁膜１５を形成することができる。また、絶縁膜１５の厚さを、例えば６００～１０００ｎｍ程度とすることができる。 For example, the insulating film 15 having a compressive stress of, for example, about 100 MPa can be formed by adjusting the bias voltage or the flow rate of the source gas and adjusting the film forming speed when forming the insulating film 15. Further, the thickness of the insulating film 15 can be set to about 600 to 1000 nm, for example.
　これにより、センサチップ３をモールド樹脂５（図２参照）により封止する際に、モールド樹脂５中のフィラーによるトランジスタＴｒに損傷が与えられることを防止または抑制し、モールド樹脂５の応力により配線２４または配線２２に損傷が与えられることを防止または抑制することができる。あるいは、モールド樹脂５を透過した外部の水分により配線２４または配線２２が腐食することを防止または抑制することができる。 Thereby, when the sensor chip 3 is sealed with the mold resin 5 (see FIG. 2), the transistor Tr is prevented or suppressed from being damaged by the filler in the mold resin 5, and the wiring due to the stress of the mold resin 5 is prevented. 24 or the wiring 22 can be prevented or suppressed from being damaged. Alternatively, it is possible to prevent or suppress the wiring 24 or the wiring 22 from being corroded by external moisture that has passed through the mold resin 5.
　次に、絶縁膜１６を形成する（図５のステップＳ１４）。このステップＳ１４の工程では、図１０に示すように、領域ＡＲ１および領域ＡＲ２で、絶縁膜１５上に、絶縁膜１６を形成する。具体的には、例えばプラズマＣＶＤ法により、または、ＴＥＯＳを原料とし、プラズマを用いた低温ＣＶＤ法により、酸化シリコンからなる絶縁膜１６を、形成することができる。絶縁膜１６は、後述する図１１を用いて説明する工程を行って、窒化シリコンからなる絶縁膜２０をパターニングする際に、絶縁膜２０のエッチングストッパとして機能する。また、絶縁膜１６の厚さを、例えば１００～５００ｎｍ程度とすることができる。 Next, the insulating film 16 is formed (step S14 in FIG. 5). In step S14, as shown in FIG. 10, the insulating film 16 is formed on the insulating film 15 in the regions AR1 and AR2. Specifically, the insulating film 16 made of silicon oxide can be formed by, for example, a plasma CVD method or a low temperature CVD method using TEOS as a raw material and plasma. The insulating film 16 functions as an etching stopper for the insulating film 20 when the insulating film 20 made of silicon nitride is patterned by performing a process described with reference to FIG. Further, the thickness of the insulating film 16 can be set to about 100 to 500 nm, for example.
　次に、開口部ＯＰ１を形成する（図５のステップＳ１５）。このステップＳ１５の工程では、図１０に示すように、領域ＡＲ１で、フォトリソグラフィ法およびドライエッチング法を用いて、絶縁膜１６、絶縁膜１５および層間絶縁膜１４をパターニングする。まず、領域ＡＲ１で、絶縁膜１６をエッチングして除去する。次に、領域ＡＲ１で、絶縁膜１６が除去された部分の絶縁膜１５をエッチングして除去する。次に、領域ＡＲ１で、絶縁膜１５が除去された部分の層間絶縁膜１４、すなわち層間絶縁膜１４ａをエッチングして除去する。これにより、図１０に示すように、領域ＡＲ１で、絶縁膜１６、絶縁膜１５および層間絶縁膜１４を貫通して層間絶縁膜１３に達する開口部ＯＰ１を形成する。 Next, the opening OP1 is formed (step S15 in FIG. 5). In the step S15, as shown in FIG. 10, the insulating film 16, the insulating film 15, and the interlayer insulating film 14 are patterned in the area AR1 by using the photolithography method and the dry etching method. First, in the region AR1, the insulating film 16 is removed by etching. Next, in the region AR1, the portion of the insulating film 15 from which the insulating film 16 has been removed is removed by etching. Next, in the region AR1, the part of the interlayer insulating film 14 from which the insulating film 15 has been removed, that is, the interlayer insulating film 14a is removed by etching. Thereby, as shown in FIG. 10, an opening OP1 that penetrates through the insulating film 16, the insulating film 15, and the interlayer insulating film 14 and reaches the interlayer insulating film 13 is formed in the region AR1.
　このようにして開口部ＯＰ１を形成することにより、絶縁体部ＩＰ１は、絶縁膜１１ａ、層間絶縁膜１２ａおよび層間絶縁膜１３ａを含むが、層間絶縁膜１４ａを含まないものとなる。したがって、絶縁体部ＩＰ１の厚さＴＰ１が、絶縁体部ＩＰ３の厚さＴＰ３よりも薄くなる。そのため、絶縁体部ＩＰ１の圧縮応力が、絶縁体部ＩＰ２の圧縮応力よりも小さくなるように、調整することができる。 By forming the opening OP1 in this way, the insulator part IP1 includes the insulating film 11a, the interlayer insulating film 12a, and the interlayer insulating film 13a, but does not include the interlayer insulating film 14a. Therefore, the thickness TP1 of the insulator part IP1 is thinner than the thickness TP3 of the insulator part IP3. Therefore, it can adjust so that the compressive stress of insulator part IP1 may become smaller than the compressive stress of insulator part IP2.
　また、このとき、絶縁膜１１ａは、平面視において、開口部ＯＰ１が形成された領域内に位置する部分の絶縁膜１１からなる。層間絶縁膜１２ａは、平面視において、開口部ＯＰ１が形成された領域内に位置する部分の層間絶縁膜１２からなる。層間絶縁膜１３ａは、平面視において、開口部ＯＰ１が形成された領域内に位置する部分の層間絶縁膜１３からなる。言い換えれば、層間絶縁膜１３ａは、開口部ＯＰ１の底部に露出した部分の層間絶縁膜１３からなる。 Further, at this time, the insulating film 11a is composed of a portion of the insulating film 11 located in a region where the opening OP1 is formed in a plan view. The interlayer insulating film 12a is composed of a portion of the interlayer insulating film 12 located in a region where the opening OP1 is formed in plan view. The interlayer insulating film 13a is composed of a portion of the interlayer insulating film 13 located in a region where the opening OP1 is formed in plan view. In other words, the interlayer insulating film 13a includes the portion of the interlayer insulating film 13 exposed at the bottom of the opening OP1.
　なお、図１０に示すように、領域ＡＲ２で、絶縁膜１６、絶縁膜１５および層間絶縁膜１４を貫通して電極パッド２９に達する開口部ＯＰ２を形成する。開口部ＯＰ２は、絶縁体部ＩＰ４、および、電極パッド２９上に位置する部分の絶縁体部ＩＰ３を貫通して、電極パッド２９に達する。そして、電極パッド２９は、開口部ＯＰ２の底部に露出する。 As shown in FIG. 10, an opening OP2 that penetrates the insulating film 16, the insulating film 15, and the interlayer insulating film 14 and reaches the electrode pad 29 is formed in the region AR2. The opening OP <b> 2 passes through the insulator part IP <b> 4 and the part of the insulator part IP <b> 3 located on the electrode pad 29 and reaches the electrode pad 29. The electrode pad 29 is exposed at the bottom of the opening OP2.
　次に、絶縁膜２０を形成する（図５のステップＳ１６）。このステップＳ１６の工程では、図１１に示すように、領域ＡＲ１で、絶縁体部ＩＰ１上に、絶縁膜２０を形成する。 Next, the insulating film 20 is formed (step S16 in FIG. 5). In the step S16, as shown in FIG. 11, the insulating film 20 is formed on the insulator portion IP1 in the region AR1.
　まず、図１１に示すように、領域ＡＲ１および領域ＡＲ２で、絶縁体部ＩＰ１上、および、絶縁膜１６上に、絶縁膜２０を形成する。具体的には、例えばプラズマを用いた低温ＣＶＤ法により、絶縁体部ＩＰ１上、および、絶縁膜１６上に、窒化シリコンからなる絶縁膜２０を形成することができる。絶縁膜２０は、領域ＡＲ１において開口部ＯＰ１の底部に露出した部分の絶縁体部ＩＰ１上から、領域ＡＲ２における絶縁膜１６上にかけて、連続的に形成される。 First, as shown in FIG. 11, the insulating film 20 is formed on the insulator part IP1 and the insulating film 16 in the region AR1 and the region AR2. Specifically, the insulating film 20 made of silicon nitride can be formed on the insulator portion IP1 and the insulating film 16 by, for example, a low temperature CVD method using plasma. The insulating film 20 is continuously formed from the portion of the insulator portion IP1 exposed at the bottom of the opening OP1 in the region AR1 to the insulating film 16 in the region AR2.
　例えばバイアス電圧または原料ガスの流量を調整し、絶縁膜２０を成膜する際の成膜速度を調整することにより、例えば２００ＭＰａ程度の引っ張り応力を有する絶縁膜２０を形成することができる。また、絶縁膜２０の厚さを、例えば８００～２０００ｎｍ程度とすることができる。 For example, the insulating film 20 having a tensile stress of about 200 MPa can be formed by adjusting the bias voltage or the flow rate of the source gas and adjusting the film forming speed when forming the insulating film 20. Further, the thickness of the insulating film 20 can be set to about 800 to 2000 nm, for example.
　次に、図１１に示すように、フォトリソグラフィ法およびドライエッチング法を用いて、領域ＡＲ１および領域ＡＲ２で、絶縁膜２０をパターニングする。これにより、領域ＡＲ１で、絶縁体部ＩＰ１上に形成された部分の絶縁膜２０、および、領域ＡＲ２で、絶縁体部ＩＰ４の領域ＡＲ１側の端部上に絶縁膜１６を介して形成された部分の絶縁膜２０を残し、それ以外の部分の絶縁膜２０を除去する。 Next, as shown in FIG. 11, the insulating film 20 is patterned in the region AR1 and the region AR2 by using a photolithography method and a dry etching method. As a result, the insulating film 20 in a portion formed on the insulator portion IP1 in the region AR1 and the end portion on the region AR1 side of the insulator portion IP4 in the region AR2 are formed via the insulating film 16. The remaining part of the insulating film 20 is left, and the other part of the insulating film 20 is removed.
　このとき、領域ＡＲ１で、絶縁膜２０を含む絶縁体部ＩＰ２が形成される。また、領域ＡＲ１で、半導体基板６の表面６ａ上に、絶縁体部ＩＰ１と、発熱抵抗体１７と、絶縁体部ＩＰ２と、を有する流量検出部７が、形成される。すなわち、流量検出部７を形成する工程は、絶縁体部ＩＰ１を形成する工程と、発熱抵抗体１７を形成する工程と、絶縁体部ＩＰ２を形成する工程と、を有する。 At this time, the insulator portion IP2 including the insulating film 20 is formed in the region AR1. In the region AR1, the flow rate detection unit 7 including the insulator part IP1, the heating resistor 17, and the insulator part IP2 is formed on the surface 6a of the semiconductor substrate 6. That is, the process of forming the flow rate detection unit 7 includes a process of forming the insulator part IP1, a process of forming the heating resistor 17, and a process of forming the insulator part IP2.
　なお、絶縁膜２０は、領域ＡＲ１における絶縁体部ＩＰ１上から、領域ＡＲ２における絶縁体部ＩＰ４の領域ＡＲ１側の端部上にかけて、直接または絶縁膜１６を介して連続的に形成される。 Note that the insulating film 20 is formed directly or continuously via the insulating film 16 over the insulator portion IP1 in the region AR1 and over the end of the insulator portion IP4 in the region AR2 on the region AR1 side.
　このように、領域ＡＲ１および領域ＡＲ２で、窒化シリコンからなる絶縁膜１５を形成した後、領域ＡＲ１で、絶縁膜１５を除去して絶縁膜２０を形成することにより、流量検出部７および制御回路部８のいずれの上層部にも、窒化シリコンからなる絶縁体部ＩＰ２および絶縁体部ＩＰ４のいずれかが形成される。したがって、例えば流量検出部７と、制御回路部８との境界部などで、制御回路ＣＲ１の配線２４などが腐食することを防止または抑制することができる。 As described above, the insulating film 15 made of silicon nitride is formed in the region AR1 and the region AR2, and then the insulating film 15 is removed and the insulating film 20 is formed in the region AR1, whereby the flow rate detector 7 and the control circuit are formed. In any upper layer part of the part 8, either the insulator part IP2 or the insulator part IP4 made of silicon nitride is formed. Therefore, for example, the wiring 24 of the control circuit CR1 can be prevented or suppressed from corroding at the boundary between the flow rate detection unit 7 and the control circuit unit 8 or the like.
　また、領域ＡＲ１および領域ＡＲ２で、絶縁膜１５および絶縁膜１６を順次形成した後、領域ＡＲ１で、絶縁膜１５を除去して絶縁膜２０を形成することにより、領域ＡＲ２で、窒化シリコンからなる絶縁膜２０をエッチングする際に、酸化シリコンからなる絶縁膜１６がエッチングストッパとして機能するため、加工精度を向上させることができる。 In addition, after the insulating film 15 and the insulating film 16 are sequentially formed in the region AR1 and the region AR2, the insulating film 15 is removed and the insulating film 20 is formed in the region AR1, thereby forming the insulating film 20 in the region AR2. Since the insulating film 16 made of silicon oxide functions as an etching stopper when the insulating film 20 is etched, the processing accuracy can be improved.
　窒化シリコンからなる絶縁体部ＩＰ２を成膜する際の成膜条件を調整することにより、絶縁体部ＩＰ２が引っ張り応力を有するように、調整することができる。同様に、窒化シリコンからなる絶縁体部ＩＰ４を成膜する際の成膜条件を調整することにより、絶縁体部ＩＰ４が、絶縁体部ＩＰ２の引っ張り応力よりも小さい引っ張り応力を有するか、または、圧縮応力を有するように、調整することができる。これにより、流量検出部７が、引っ張り応力を有するように、調整することができる。また、制御回路部８が、流量検出部７の引っ張り応力よりも小さい引っ張り応力を有するか、または、圧縮応力を有するように、調整することができる。 By adjusting the film formation conditions for forming the insulator part IP2 made of silicon nitride, the insulator part IP2 can be adjusted to have a tensile stress. Similarly, by adjusting the film formation conditions when forming the insulator part IP4 made of silicon nitride, the insulator part IP4 has a tensile stress smaller than the tensile stress of the insulator part IP2, or It can be adjusted to have a compressive stress. Thereby, the flow volume detection part 7 can be adjusted so that it may have a tensile stress. Further, the control circuit unit 8 can be adjusted so as to have a tensile stress smaller than the tensile stress of the flow rate detection unit 7 or a compressive stress.
　好適には、絶縁体部ＩＰ２は、引っ張り応力を有する。また、絶縁体部ＩＰ１、絶縁体部ＩＰ３および絶縁体部ＩＰ４は、絶縁体部ＩＰ２の引っ張り応力よりも小さい引っ張り応力を有するか、または、圧縮応力を有する。 Preferably, the insulator part IP2 has a tensile stress. Insulator part IP1, insulator part IP3, and insulator part IP4 have a tensile stress smaller than the tensile stress of insulator part IP2, or have a compressive stress.
　次に、孔部ＴＨ１を形成する（図５のステップＳ１７）。このステップＳ１７では、図１２に示すように、平面視において、領域ＡＲ１のうち、開口部ＯＰ１が形成された領域内に位置する部分で、半導体基板６に、孔部ＴＨ１を形成する。 Next, the hole TH1 is formed (step S17 in FIG. 5). In this step S17, as shown in FIG. 12, a hole TH1 is formed in the semiconductor substrate 6 at a portion located in the region where the opening OP1 is formed in the region AR1 in plan view.
　まず、図１２に示すように、半導体基板６の裏面６ｂに、絶縁膜４３を形成する。例えばＴＥＯＳを原料とし、プラズマを用いた低温ＣＶＤ法により、酸化シリコンからなる絶縁膜４３を形成することができる。あるいは、プラズマを用いた低温ＣＶＤ法により、窒化シリコンからなる絶縁膜４３を形成することができる。 First, as shown in FIG. 12, an insulating film 43 is formed on the back surface 6 b of the semiconductor substrate 6. For example, the insulating film 43 made of silicon oxide can be formed by a low temperature CVD method using TEOS as a raw material and using plasma. Alternatively, the insulating film 43 made of silicon nitride can be formed by a low temperature CVD method using plasma.
　次に、図１２に示すように、領域ＡＲ１のうち、半導体基板６の裏面６ｂに形成された絶縁膜４３の表面に、フォトリソグラフィ法により、レジスト膜からなるレジストパターンを形成する。このレジストパターンは、平面視において、開口部ＯＰ１が形成された領域内に位置する部分で、レジスト膜を貫通して絶縁膜４３に達する開口部を有する。次に、レジストパターンの開口部に露出した部分の絶縁膜４３を、ドライエッチング法またはウェットエッチング法により除去する。次に、残された絶縁膜４３をマスクとして用いて、半導体基板６をウェットエッチング法によりエッチングすることにより、半導体基板６の裏面６ｂから半導体基板６を貫通して絶縁体部ＩＰ１に達する孔部ＴＨ１を形成する。具体的には、水酸化カリウム（ＫＯＨ）もしくは水酸化テトラメチルアンモニウム（Tetramethylammonium hydroxide；ＴＭＡＨ）、または、水酸化カリウムもしくはＴＭＡＨを主成分とする水溶液を用いたウェットエッチング法により、孔部ＴＨ１を形成する。これにより、孔部ＴＨ１の上底部には、絶縁体部ＩＰ１と、絶縁体部ＩＰ２とからなるダイヤフラム構造ＤＦ１が形成される。 Next, as shown in FIG. 12, a resist pattern made of a resist film is formed by photolithography on the surface of the insulating film 43 formed on the back surface 6b of the semiconductor substrate 6 in the region AR1. This resist pattern has an opening that reaches the insulating film 43 through the resist film at a portion located in a region where the opening OP1 is formed in plan view. Next, the portion of the insulating film 43 exposed at the opening of the resist pattern is removed by a dry etching method or a wet etching method. Next, by using the remaining insulating film 43 as a mask, the semiconductor substrate 6 is etched by a wet etching method, whereby a hole portion that penetrates the semiconductor substrate 6 from the back surface 6b of the semiconductor substrate 6 and reaches the insulator portion IP1. Form TH1. Specifically, the hole TH1 is formed by a wet etching method using potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH) or an aqueous solution mainly containing potassium hydroxide or TMAH. To do. Thus, a diaphragm structure DF1 including the insulator part IP1 and the insulator part IP2 is formed on the upper bottom part of the hole part TH1.
　好適には、孔部ＴＨ１は、領域ＡＲ１のうち、平面視において、開口部ＯＰ１が形成された領域内に、形成されている。これにより、後述する図１４を用いて説明するように、センサチップ３をモールド樹脂５（図２参照）により封止する際に、孔部ＴＨ１が形成された領域内に位置する部分の絶縁膜２０に空気流路用凸部５４が接触することを防止することができる。そのため、センサチップ３をモールド樹脂５（図２参照）により封止する際に、孔部ＴＨ１が形成された領域内に位置する部分の絶縁体部ＩＰ１または絶縁体部ＩＰ２が破損することを防止することができる。 Preferably, the hole portion TH1 is formed in a region of the region AR1 where the opening portion OP1 is formed in a plan view. As a result, as will be described with reference to FIG. 14 described later, when the sensor chip 3 is sealed with the mold resin 5 (see FIG. 2), the insulating film in the portion located in the region where the hole TH1 is formed It is possible to prevent the air flow path convex portion 54 from coming into contact with 20. Therefore, when the sensor chip 3 is sealed with the mold resin 5 (see FIG. 2), the portion of the insulator portion IP1 or the insulator portion IP2 located in the region where the hole portion TH1 is formed is prevented from being damaged. can do.
　絶縁膜４３は、酸化シリコン膜と窒化シリコン膜との積層膜であってもよい。また、絶縁膜２０のパターニングが終了した段階で、水酸化カリウムまたはＴＭＡＨによりウェットエッチングされない膜が半導体基板６の裏面６ｂに形成されている場合には、半導体基板６の裏面６ｂに絶縁膜４３を形成せずに、孔部ＴＨ１を形成することもできる。 The insulating film 43 may be a laminated film of a silicon oxide film and a silicon nitride film. When the patterning of the insulating film 20 is completed, if a film that is not wet etched by potassium hydroxide or TMAH is formed on the back surface 6b of the semiconductor substrate 6, the insulating film 43 is formed on the back surface 6b of the semiconductor substrate 6. It is also possible to form the hole TH1 without forming it.
　また、孔部ＴＨ１がウェットエッチングにより形成された場合、半導体基板６の裏面６ｂにおける孔部ＴＨ１の面積は、半導体基板６の表面６ａにおける孔部ＴＨ１の面積よりも、広くなる。このような場合には、孔部ＴＨ１が形成された領域とは、孔部ＴＨ１の上底部、すなわち半導体基板６の表面６ａにおいて孔部ＴＨ１が形成された領域を意味する。 When the hole TH1 is formed by wet etching, the area of the hole TH1 on the back surface 6b of the semiconductor substrate 6 is larger than the area of the hole TH1 on the front surface 6a of the semiconductor substrate 6. In such a case, the region in which the hole portion TH1 is formed means the region in which the hole portion TH1 is formed in the upper bottom portion of the hole portion TH1, that is, the surface 6a of the semiconductor substrate 6.
　このようにして、図１２に示すように、半導体基板６と、流量検出部７と、制御回路部８と、を有する、センサチップ３が形成される。なお、以後の工程において、絶縁膜４３は、除去されてもよく、除去されなくてもよいので、絶縁膜４３が除去されない場合でも、絶縁膜４３の図示を省略する。 In this way, as shown in FIG. 12, the sensor chip 3 having the semiconductor substrate 6, the flow rate detection unit 7, and the control circuit unit 8 is formed. Note that in the subsequent steps, the insulating film 43 may or may not be removed. Therefore, the illustration of the insulating film 43 is omitted even when the insulating film 43 is not removed.
　次に、センサチップ３をリードフレーム２に搭載する（図５のステップＳ１８）。このステップＳ１８の工程では、図１３に示すように、センサチップ３をリードフレーム２に搭載し、センサチップ３をボンディングワイヤ４により外部端子２ｂと電気的に接続する。 Next, the sensor chip 3 is mounted on the lead frame 2 (step S18 in FIG. 5). In the step S18, as shown in FIG. 13, the sensor chip 3 is mounted on the lead frame 2, and the sensor chip 3 is electrically connected to the external terminal 2b by the bonding wire 4.
　次に、センサチップ３を封止する（図５のステップＳ１９）。このステップＳ１９の工程では、図１４に示すように、センサチップ３を、モールド成型用金型５１を用いた樹脂モールドにより封止する。モールド成型用金型５１は、モールド成型用空間５２と、モールド樹脂流入口５３と、空気流路用凸部５４と、凸部５５と、を有する。モールド成型用空間５２の内部に、センサチップ３およびリードフレーム２を配置する。そして、モールド樹脂流入口５３からモールド成型用空間５２の内部に樹脂を充填する。これにより、センサチップ３およびリードフレーム２を、モールド樹脂５（図２参照）を用いた樹脂モールドにより封止する。 Next, the sensor chip 3 is sealed (step S19 in FIG. 5). In the step S19, as shown in FIG. 14, the sensor chip 3 is sealed with a resin mold using a mold 51 for molding. The mold 51 for molding includes a molding space 52, a mold resin inlet 53, an air flow path convex portion 54, and a convex portion 55. The sensor chip 3 and the lead frame 2 are arranged inside the molding space 52. Then, resin is filled into the molding space 52 from the mold resin inlet 53. Thereby, the sensor chip 3 and the lead frame 2 are sealed with a resin mold using the mold resin 5 (see FIG. 2).
　図１４に示すように、空気流路用凸部５４は、センサチップ３およびリードフレーム２がモールド成型用空間５２の内部に配置されたとき、空気流路用凸部５４が流量検出部７に接触するように、配置されている。これにより、モールド樹脂流入口５３からモールド成型用空間５２の内部にモールド樹脂５（図２参照）を充填する際に、流量検出部７とモールド成型用金型５１との間にモールド樹脂５が流れ込まないようにすることができる。そのため、図２に示したように、流量検出部７上に位置する部分のモールド樹脂５に、モールド樹脂５を貫通して流量検出部７に達する溝部ＴＲ１が形成され、流量検出部７は、溝部ＴＲ１の底部に露出する。したがって、溝部ＴＲ１に沿って空気が流れやすくなり、流量検出部７の周辺で、空気の流れが乱されないようにすることができる。 As shown in FIG. 14, when the sensor chip 3 and the lead frame 2 are disposed inside the molding space 52, the air flow path convex portion 54 is formed on the flow rate detection unit 7. It is arranged to come into contact. As a result, when the mold resin 5 (see FIG. 2) is filled into the mold molding space 52 from the mold resin inlet 53, the mold resin 5 is interposed between the flow rate detection unit 7 and the mold mold 51. It can be prevented from flowing in. Therefore, as shown in FIG. 2, a groove TR1 that penetrates the mold resin 5 and reaches the flow rate detection unit 7 is formed in a portion of the mold resin 5 located on the flow rate detection unit 7. It is exposed at the bottom of the trench part TR1. Therefore, it becomes easy for air to flow along the groove part TR1, and it is possible to prevent the air flow from being disturbed around the flow rate detection part 7.
　また、流量検出部７のうちダイヤフラム構造ＤＦ１を形成する部分、すなわち、絶縁体部ＩＰ２にモールド樹脂５（図２参照）が付着すると、例えば流量検出部７の熱容量が大きくなることなどにより、空気などの流体の流量を精度よく検出できないおそれがある。そのため、絶縁体部ＩＰ４の領域ＡＲ１側の端部上に位置する部分の絶縁膜１６上に形成された部分の絶縁体部ＩＰ２には、空気流路用凸部５４が密着するが、開口部ＯＰ１の底部に露出した部分の絶縁体部ＩＰ１上に位置する部分の絶縁体部ＩＰ２には、空気流路用凸部５４が接触しないように、センサチップ３が配置される。これにより、開口部ＯＰ１の底部に露出した部分の絶縁体部ＩＰ１上に位置する部分の絶縁体部ＩＰ２にモールド樹脂５が付着することを防止することができ、空気などの流体の流量を精度よく検出することができる。 Further, when the mold resin 5 (see FIG. 2) adheres to the portion of the flow rate detection unit 7 that forms the diaphragm structure DF1, that is, the insulator unit IP2, the heat capacity of the flow rate detection unit 7 increases, for example. There is a possibility that the flow rate of fluid such as cannot be accurately detected. Therefore, the air flow path convex portion 54 is in close contact with the portion of the insulating portion IP2 formed on the insulating film 16 in the portion located on the end of the insulating portion IP4 on the region AR1 side, but the opening portion The sensor chip 3 is disposed so that the air flow path convex portion 54 does not contact the portion of the insulator portion IP2 located on the insulator portion IP1 of the portion exposed at the bottom of the OP1. As a result, the mold resin 5 can be prevented from adhering to the portion of the insulator portion IP2 located on the insulator portion IP1 exposed at the bottom of the opening OP1, and the flow rate of fluid such as air can be accurately controlled. Can be detected well.
　ただし、平面視において、孔部ＴＨ１が形成された領域内に位置する部分の絶縁体部ＩＰ２に、空気流路用凸部５４が接触すると、孔部ＴＨ１が形成された領域内に位置する部分の絶縁体部ＩＰ１または絶縁体部ＩＰ２が破損するおそれがある。本実施の形態１では、好適には、孔部ＴＨ１は、平面視において、開口部ＯＰ１が形成された領域内に形成されている。また、前述したように、開口部ＯＰ１の底部に露出した部分の絶縁体部ＩＰ１上に位置する部分の絶縁膜２０には、空気流路用凸部５４が接触しないように、センサチップ３が配置される。これにより、孔部ＴＨ１が形成された領域内に位置する部分の絶縁体部ＩＰ２に、空気流路用凸部５４が接触することを防止することができ、孔部ＴＨ１が形成された領域内に位置する部分の絶縁体部ＩＰ１または絶縁体部ＩＰ２が破損することを防止することができる。 However, in plan view, when the air flow path convex portion 54 comes into contact with a portion of the insulator portion IP2 located in the region where the hole portion TH1 is formed, the portion located in the region where the hole portion TH1 is formed. Insulator part IP1 or insulator part IP2 may be damaged. In the first embodiment, preferably, the hole TH1 is formed in a region where the opening OP1 is formed in a plan view. Further, as described above, the sensor chip 3 is formed so that the air channel convex portion 54 does not contact the insulating film 20 in the portion located on the insulator portion IP1 in the portion exposed at the bottom of the opening OP1. Be placed. Thereby, it is possible to prevent the air flow path convex portion 54 from coming into contact with a portion of the insulator portion IP2 located in the region where the hole portion TH1 is formed, and within the region where the hole portion TH1 is formed. It is possible to prevent the insulator part IP1 or the insulator part IP2 located in the portion from being damaged.
　凸部５５は、流量検出部７、センサチップ３およびリードフレーム２を挟んで空気流路用凸部５４と反対側に配置されている。凸部５５は、センサチップ３およびリードフレーム２がモールド成型用空間５２の内部に配置されたとき、流量検出部７の下方に位置する部分のリードフレーム２に凸部５５が接触するように、配置されている。これにより、流量検出部７、半導体基板６およびリードフレーム２が、空気流路用凸部５４と凸部５５とにより、上下から挟まれるため、空気流路用凸部５４を、絶縁体部ＩＰ４の領域ＡＲ１側の端部上に位置する部分の絶縁膜１６上に形成された部分の絶縁体部ＩＰ２に、確実に密着させることができる。 The convex portion 55 is disposed on the opposite side of the air flow path convex portion 54 with the flow rate detecting portion 7, the sensor chip 3, and the lead frame 2 interposed therebetween. When the sensor chip 3 and the lead frame 2 are arranged inside the molding space 52, the convex portion 55 is arranged so that the convex portion 55 comes into contact with the portion of the lead frame 2 located below the flow rate detecting portion 7. Is arranged. As a result, the flow rate detector 7, the semiconductor substrate 6 and the lead frame 2 are sandwiched from above and below by the air flow path convex portion 54 and the convex portion 55, so that the air flow path convex portion 54 is connected to the insulator portion IP4. It is possible to reliably adhere to the portion of the insulator portion IP2 formed on the portion of the insulating film 16 located on the end portion on the region AR1 side.
　＜流量検出部および制御回路部における絶縁体部の内部応力＞
　単結晶シリコンからなる半導体基板上に形成された酸化シリコン膜は、例えば酸化シリコンの熱膨張係数がシリコンの熱膨張係数よりも小さいことなどにより、通常、圧縮応力を有する。したがって、流量検出部７が、酸化シリコンからなる絶縁体部ＩＰ１を有する場合、流量検出部７は、圧縮応力を有することがある。 <Internal stress of insulator in flow rate detector and control circuit>
A silicon oxide film formed on a semiconductor substrate made of single crystal silicon usually has a compressive stress because, for example, the thermal expansion coefficient of silicon oxide is smaller than the thermal expansion coefficient of silicon. Therefore, when the flow rate detection unit 7 includes the insulator portion IP1 made of silicon oxide, the flow rate detection unit 7 may have a compressive stress.
　流量検出部７が、圧縮応力を有する場合、流量検出部７が撓みやすくなるので、流量検出部７が破損するおそれがある。また、流量検出部７が形成された領域内で半導体基板６に孔部ＴＨ１が形成されている場合には、流量検出部７がさらに撓みやすくなり、流量検出部７が破損するおそれがさらに高くなる。 When the flow rate detection unit 7 has a compressive stress, the flow rate detection unit 7 is likely to be bent, so that the flow rate detection unit 7 may be damaged. Further, when the hole TH1 is formed in the semiconductor substrate 6 in the region where the flow rate detection unit 7 is formed, the flow rate detection unit 7 is more easily bent and the flow rate detection unit 7 is more likely to be damaged. Become.
　一方、流量検出部７が引っ張り応力を有する場合には、流量検出部７は撓みにくく、流量検出部７が破損するおそれは少ない。また、流量検出部７が形成された領域内で半導体基板６に孔部ＴＨ１が形成されている場合でも、流量検出部７は撓みにくく、流量検出部７が破損するおそれは少ない。 On the other hand, when the flow rate detection unit 7 has a tensile stress, the flow rate detection unit 7 is not easily bent and the flow rate detection unit 7 is less likely to be damaged. Even when the hole TH1 is formed in the semiconductor substrate 6 in the region where the flow rate detection unit 7 is formed, the flow rate detection unit 7 is not easily bent and the flow rate detection unit 7 is less likely to be damaged.
　ところが、流量検出部７が引っ張り応力を有する場合には、制御回路部８が引っ張り応力を有することがある。制御回路部８が引っ張り応力を有する場合、トランジスタＴｒのトランジスタ特性、または、配線２４などの抵抗特性が変動することなどにより、制御回路部８の電気的特性が変動するおそれがある。 However, when the flow rate detection unit 7 has tensile stress, the control circuit unit 8 may have tensile stress. When the control circuit unit 8 has tensile stress, the electrical characteristics of the control circuit unit 8 may vary due to variations in transistor characteristics of the transistor Tr or resistance characteristics of the wiring 24 and the like.
　制御回路部８を覆うように形成されたモールド樹脂５は、通常、引っ張り応力を有するが、制御回路部８が引っ張り応力を有する場合、制御回路部８における引っ張り応力はモールド樹脂５により相殺されず、制御回路部８における内部応力の絶対値が大きくなる。このように、制御回路部８における内部応力の絶対値が大きくなると、トランジスタＴｒのトランジスタ特性、または、配線２４などの抵抗特性が変動することなどにより、制御回路部８の電気的特性が変動するおそれがある。 The mold resin 5 formed so as to cover the control circuit unit 8 usually has a tensile stress. However, when the control circuit unit 8 has a tensile stress, the tensile stress in the control circuit unit 8 is not offset by the mold resin 5. The absolute value of the internal stress in the control circuit unit 8 increases. As described above, when the absolute value of the internal stress in the control circuit unit 8 increases, the electrical characteristics of the control circuit unit 8 change due to the change in the transistor characteristics of the transistor Tr or the resistance characteristics of the wiring 24 and the like. There is a fear.
　上記特許文献１に記載された技術では、膜上に測定素子が設けられているその膜を緊張させるために、伸長性コーティングが設けられるが、その伸長性コーティングは、回路の能動電子部品の少なくとも一部を覆わない。そのため、例えば流量検出部と、制御回路部との境界部など、伸長性コーティングが設けられる領域と、伸長性コーティングが設けられない領域との境界において配線が腐食するなどして、流量センサの信頼性が低下するおそれがある。 In the technique described in the above-mentioned Patent Document 1, an extensible coating is provided to tension the film in which the measurement element is provided on the film, and the extensible coating is at least an active electronic component of the circuit. Do not cover part. For this reason, the reliability of the flow sensor can be increased by corroding the wiring at the boundary between the area where the extensible coating is provided and the area where the extensible coating is not provided, such as the boundary between the flow rate detection unit and the control circuit unit. May decrease.
　また、上記特許文献１に記載された技術では、制御回路部８を覆うようにモールド樹脂５を形成する場合、流量検出部７にモールド樹脂５が流入しないように、モールド成型用金型５１の空気流路用凸部５４を流量検出部７に接触させる際に、流量検出部７にクラックが発生するなど、流量検出部７が破損するおそれがある。そのため、流量センサの製造時の歩留まりが低下するか、または、流量センサの信頼性が低下するおそれがある。 In the technique described in Patent Document 1, when the mold resin 5 is formed so as to cover the control circuit unit 8, the mold mold 51 is arranged so that the mold resin 5 does not flow into the flow rate detection unit 7. When the air flow path convex portion 54 is brought into contact with the flow rate detection unit 7, the flow rate detection unit 7 may be damaged, for example, a crack may be generated in the flow rate detection unit 7. Therefore, there is a possibility that the yield at the time of manufacturing the flow sensor is lowered, or the reliability of the flow sensor is lowered.
　なお、上記特許文献２に記載された技術では、検出部が設けられた領域における酸化シリコン膜に対する窒化シリコン膜の厚さの比は、回路部が設けられた領域における酸化シリコン膜に対する窒化シリコン膜の厚さの比よりも大きくない。 In the technique described in Patent Document 2, the ratio of the thickness of the silicon nitride film to the silicon oxide film in the region where the detection unit is provided is equal to the silicon nitride film relative to the silicon oxide film in the region where the circuit unit is provided. Not greater than the thickness ratio.
　＜本実施の形態の主要な特徴と効果＞
　本実施の形態１の流量センサ１では、絶縁体部ＩＰ１の厚さＴＰ１に対する絶縁体部ＩＰ２の厚さＴＰ２の比は、絶縁体部ＩＰ３の厚さＴＰ３に対する絶縁体部ＩＰ４の厚さＴＰ４の比よりも大きい。 <Main features and effects of the present embodiment>
In the flow sensor 1 according to the first embodiment, the ratio of the thickness TP2 of the insulator part IP2 to the thickness TP1 of the insulator part IP1 is equal to the thickness TP4 of the insulator part IP4 to the thickness TP3 of the insulator part IP3. Greater than ratio.
　前述したように、単結晶シリコンからなる半導体基板上に形成された酸化シリコン膜は、通常、圧縮応力を有する。一方、単結晶シリコンからなる半導体基板上に形成された窒化シリコン膜は、窒化シリコン膜を成膜する際の成膜条件を調整することにより、窒化シリコン膜の内部応力が引っ張り応力または圧縮応力になるように、調整することができる。 As described above, a silicon oxide film formed on a semiconductor substrate made of single crystal silicon usually has a compressive stress. On the other hand, in a silicon nitride film formed on a semiconductor substrate made of single crystal silicon, the internal stress of the silicon nitride film is changed to tensile stress or compressive stress by adjusting the film formation conditions when forming the silicon nitride film. Can be adjusted.
　したがって、窒化シリコンからなる絶縁体部ＩＰ２を成膜する際の成膜条件を調整することにより、絶縁体部ＩＰ２が引っ張り応力を有するように、調整することができる。同様に、窒化シリコンからなる絶縁体部ＩＰ４を成膜する際の成膜条件を調整することにより、絶縁体部ＩＰ４が、絶縁体部ＩＰ２の引っ張り応力よりも小さい引っ張り応力を有するか、または、圧縮応力を有するように、調整することができる。 Therefore, the insulator part IP2 can be adjusted so as to have a tensile stress by adjusting the film formation conditions when forming the insulator part IP2 made of silicon nitride. Similarly, by adjusting the film formation conditions when forming the insulator part IP4 made of silicon nitride, the insulator part IP4 has a tensile stress smaller than the tensile stress of the insulator part IP2, or It can be adjusted to have a compressive stress.
　これにより、領域ＡＲ１で、絶縁体部ＩＰ１および絶縁体部ＩＰ２を含む流量検出部７が、引っ張り応力を有するように、調整することができる。そのため、流量検出部７が撓みにくくなり、流量検出部７が破損することを防止または抑制することができる。また、領域ＡＲ１で、半導体基板６に孔部ＴＨ１が形成されている場合でも、流量検出部７は撓みにくくなり、流量検出部７の破損を防止または抑制することができる。 Thereby, in the area AR1, the flow rate detection unit 7 including the insulator part IP1 and the insulator part IP2 can be adjusted to have a tensile stress. Therefore, the flow rate detection unit 7 becomes difficult to bend, and the flow rate detection unit 7 can be prevented or suppressed from being damaged. Further, even when the hole portion TH1 is formed in the semiconductor substrate 6 in the area AR1, the flow rate detection unit 7 becomes difficult to bend, and damage to the flow rate detection unit 7 can be prevented or suppressed.
　一方、領域ＡＲ２で、絶縁体部ＩＰ２および絶縁体部ＩＰ４を含む制御回路部８が、流量検出部７の引っ張り応力よりも小さい引っ張り応力を有するか、または、圧縮応力を有するように、調整することができる。このように、制御回路部８が圧縮応力を有する場合には、制御回路部８を覆うように形成されたモールド樹脂５が引っ張り応力を有するため、制御回路部８の圧縮応力が相殺され、制御回路部８の内部応力の絶対値が小さくなる。また、制御回路部８の内部応力の絶対値が小さいため、制御回路部８の電気的特性の変動を防止または抑制することができる。 On the other hand, in the area AR2, the control circuit unit 8 including the insulator part IP2 and the insulator part IP4 is adjusted so as to have a tensile stress smaller than the tensile stress of the flow rate detection unit 7, or to have a compressive stress. be able to. Thus, when the control circuit unit 8 has a compressive stress, the mold resin 5 formed so as to cover the control circuit unit 8 has a tensile stress. The absolute value of the internal stress of the circuit unit 8 becomes small. Further, since the absolute value of the internal stress of the control circuit unit 8 is small, fluctuations in the electrical characteristics of the control circuit unit 8 can be prevented or suppressed.
　また、本実施の形態１の流量センサでは、流量検出部７および制御回路部８のいずれの上層部にも、窒化シリコンからなる絶縁体部ＩＰ２および絶縁体部ＩＰ４のいずれかが形成されている。したがって、上記特許文献１に記載された技術に比べ、例えば流量検出部７と、制御回路部８との境界部などで、制御回路ＣＲ１の配線２４などが腐食することを防止または抑制することができ、流量センサの信頼性を向上させることができる。 In the flow rate sensor of the first embodiment, any one of the insulator part IP2 and the insulator part IP4 made of silicon nitride is formed in any upper layer part of the flow rate detection part 7 and the control circuit part 8. . Therefore, compared to the technique described in Patent Document 1, it is possible to prevent or suppress the corrosion of the wiring 24 of the control circuit CR1 at the boundary between the flow rate detection unit 7 and the control circuit unit 8, for example. And the reliability of the flow sensor can be improved.
　あるいは、本実施の形態１の流量センサでは、絶縁体部ＩＰ１の厚さＴＰ１は、絶縁体部ＩＰ１と同層に形成された絶縁体部ＩＰ３の厚さＴＰ３よりも薄く、領域ＡＲ１で、開口部ＯＰ１が形成されているが、領域ＡＲ２を含めて、領域ＡＲ１の外部の領域では、開口部ＯＰ１が形成されていない。そして、絶縁体部ＩＰ２は、絶縁体部ＩＰ１上から、絶縁体部ＩＰ４の領域ＡＲ１側の端部上にかけて、直接または絶縁膜１６を介して、連続的に形成されている。 Alternatively, in the flow rate sensor of the first embodiment, the thickness TP1 of the insulator part IP1 is thinner than the thickness TP3 of the insulator part IP3 formed in the same layer as the insulator part IP1, and the area AR1 has an opening. The portion OP1 is formed, but the opening OP1 is not formed in a region outside the region AR1 including the region AR2. The insulator part IP2 is continuously formed directly or via the insulating film 16 from the insulator part IP1 to the end of the insulator part IP4 on the region AR1 side.
　これにより、制御回路部８を覆うようにモールド樹脂５を形成するために、流量検出部７にモールド樹脂５が流入しないように、モールド成型用金型５１の空気流路用凸部５４をセンサチップ３に接触させる際に、上記特許文献１に記載された技術に比べ、空気流路用凸部５４が流量検出部７に接触することを防止することができる。そのため、流量検出部７におけるクラックの発生、または、流量検出部７の破損を防止することができ、流量センサの製造時の歩留まりを向上させ、流量センサの信頼性を向上させることができる。 As a result, in order to form the mold resin 5 so as to cover the control circuit unit 8, the air flow path convex portion 54 of the mold molding die 51 is sensored so that the mold resin 5 does not flow into the flow rate detection unit 7. When contacting the chip 3, the air flow path convex portion 54 can be prevented from coming into contact with the flow rate detection unit 7 as compared with the technique described in Patent Document 1 above. Therefore, the generation of cracks in the flow rate detection unit 7 or the breakage of the flow rate detection unit 7 can be prevented, the yield in manufacturing the flow rate sensor can be improved, and the reliability of the flow rate sensor can be improved.
　好適には、モールド樹脂５の領域ＡＲ１側の端部が、絶縁体部ＩＰ４上に絶縁膜１６を介して形成された部分の絶縁体部ＩＰ２上に位置する。この場合、絶縁体部ＩＰ４から露出した部分の絶縁膜１６および絶縁体部ＩＰ３が、さらに、モールド樹脂５に覆われることになるので、上記した接触の防止の効果に加え、制御回路ＣＲ１の配線２４などの腐食を防止する効果が大きくなる。 Preferably, the end of the mold resin 5 on the region AR1 side is located on the insulator part IP2 of the part formed on the insulator part IP4 with the insulating film 16 interposed therebetween. In this case, the portion of the insulating film 16 and the insulating portion IP3 exposed from the insulating portion IP4 are further covered with the mold resin 5, so that the wiring of the control circuit CR1 is added to the effect of preventing the contact described above. The effect of preventing corrosion such as 24 is increased.
　（実施の形態２）
　実施の形態１の流量センサでは、絶縁膜１５を形成した後、絶縁膜２０を形成するため、絶縁膜１５と絶縁膜２０とが重なる部分では、絶縁膜２０は、絶縁膜１５よりも上方に形成されていた。一方、実施の形態２の流量センサでは、絶縁膜２０を形成した後、絶縁膜１５を形成するため、絶縁膜１５と絶縁膜２０とが重なる部分では、絶縁膜１５は、絶縁膜２０よりも上方に形成されている。 (Embodiment 2)
In the flow rate sensor of the first embodiment, since the insulating film 20 is formed after the insulating film 15 is formed, the insulating film 20 is located above the insulating film 15 in a portion where the insulating film 15 and the insulating film 20 overlap. Was formed. On the other hand, in the flow rate sensor according to the second embodiment, since the insulating film 15 is formed after the insulating film 20 is formed, the insulating film 15 is larger than the insulating film 20 in the portion where the insulating film 15 and the insulating film 20 overlap. It is formed above.
　本実施の形態２の流量センサのうち、センサチップ３以外の各要素、および、センサチップ３のうち、絶縁体部ＩＰ１および絶縁体部ＩＰ２、ならびに、絶縁体部ＩＰ１および絶縁体部ＩＰ２よりも下方に位置する各要素については、実施の形態１の流量センサにおける各要素と共通である。したがって、実施の形態１の流量センサの各要素と共通の要素については、実施の形態１の流量センサにおける符号と同一の符号を付し、その説明を省略する。 Of the flow rate sensor of the second embodiment, each element other than the sensor chip 3 and among the sensor chip 3, the insulator part IP1 and the insulator part IP2, and the insulator part IP1 and the insulator part IP2 About each element located below, it is common with each element in the flow sensor of Embodiment 1. Therefore, elements common to the elements of the flow sensor of the first embodiment are denoted by the same reference numerals as those of the flow sensor of the first embodiment, and the description thereof is omitted.
　＜流量センサ＞
　図１５は、実施の形態２の流量センサにおけるセンサチップの要部断面図である。図１５に示すように、センサチップ３は、半導体基板６と、流量検出部７と、制御回路部８と、を有する。 <Flow sensor>
FIG. 15 is a cross-sectional view of a main part of the sensor chip in the flow sensor according to the second embodiment. As shown in FIG. 15, the sensor chip 3 includes a semiconductor substrate 6, a flow rate detection unit 7, and a control circuit unit 8.
　本実施の形態２でも、実施の形態１と同様に、半導体基板６の表面６ａ上には、絶縁膜１１、層間絶縁膜１２、層間絶縁膜１３、層間絶縁膜１４および絶縁膜１５が形成されている。 Also in the second embodiment, as in the first embodiment, the insulating film 11, the interlayer insulating film 12, the interlayer insulating film 13, the interlayer insulating film 14, and the insulating film 15 are formed on the surface 6a of the semiconductor substrate 6. ing.
　本実施の形態２でも、実施の形態１と同様に、流量検出部７は、半導体基板６の表面６ａの領域ＡＲ１で、半導体基板６の表面６ａ上に形成されており、絶縁体部ＩＰ１と、発熱抵抗体１７と、絶縁体部ＩＰ２と、を有する。 Also in the second embodiment, as in the first embodiment, the flow rate detection unit 7 is formed on the surface 6a of the semiconductor substrate 6 in the region AR1 of the surface 6a of the semiconductor substrate 6, and the insulator unit IP1. The heating resistor 17 and the insulator part IP2 are included.
　絶縁体部ＩＰ１は、領域ＡＲ１で、半導体基板６の表面６ａ上に形成されており、例えば、絶縁膜１１ａと、層間絶縁膜１２ａと、層間絶縁膜１３ａと、を含む。領域ＡＲ１で、層間絶縁膜１４には、層間絶縁膜１４を貫通して層間絶縁膜１３ａに達する開口部ＯＰ１が形成されている。また、絶縁体部ＩＰ１は、領域ＡＲ１で形成されており、開口部ＯＰ１が形成された領域内に、配置されている。また、領域ＡＲ１で、絶縁体部ＩＰ１上には、例えば窒化シリコンからなる絶縁膜２０が形成されている。 The insulator part IP1 is formed on the surface 6a of the semiconductor substrate 6 in the region AR1, and includes, for example, an insulating film 11a, an interlayer insulating film 12a, and an interlayer insulating film 13a. In the region AR1, an opening OP1 that penetrates the interlayer insulating film 14 and reaches the interlayer insulating film 13a is formed in the interlayer insulating film 14. The insulator part IP1 is formed in the area AR1, and is disposed in the area where the opening OP1 is formed. In the region AR1, an insulating film 20 made of, for example, silicon nitride is formed on the insulator portion IP1.
　一方、本実施の形態２では、実施の形態１と異なり、絶縁膜１６（図３参照）は形成されていない。また、例えば窒化シリコンからなる絶縁膜１５は、領域ＡＲ１では、絶縁膜２０上に形成されている。 On the other hand, in the second embodiment, unlike the first embodiment, the insulating film 16 (see FIG. 3) is not formed. For example, the insulating film 15 made of silicon nitride is formed on the insulating film 20 in the region AR1.
　絶縁体部ＩＰ２は、領域ＡＲ１で、絶縁体部ＩＰ１上に形成されている。絶縁体部ＩＰ２は、絶縁膜２０と、絶縁膜２０上に形成された絶縁膜１５ａを含む。絶縁膜１５ａは、絶縁膜２０上に形成された部分の絶縁膜１５からなる。 The insulator part IP2 is formed on the insulator part IP1 in the area AR1. The insulator part IP2 includes an insulating film 20 and an insulating film 15a formed on the insulating film 20. The insulating film 15 a is composed of a portion of the insulating film 15 formed on the insulating film 20.
　本実施の形態２でも、実施の形態１と同様に、制御回路部８は、半導体基板６の表面６ａの領域ＡＲ２で、半導体基板６の表面６ａ上に形成されており、絶縁体部ＩＰ３と、制御回路ＣＲ１と、絶縁体部ＩＰ４と、を有する。 Also in the second embodiment, as in the first embodiment, the control circuit portion 8 is formed on the surface 6a of the semiconductor substrate 6 in the region AR2 of the surface 6a of the semiconductor substrate 6, and the insulator portion IP3. And a control circuit CR1 and an insulator part IP4.
　絶縁体部ＩＰ３は、領域ＡＲ２で、半導体基板６の表面６ａ上に形成されており、例えば、絶縁膜１１ｂと、層間絶縁膜１２ｂと、層間絶縁膜１３ｂと、層間絶縁膜１４ｂと、を含む。 The insulator part IP3 is formed on the surface 6a of the semiconductor substrate 6 in the region AR2, and includes, for example, an insulating film 11b, an interlayer insulating film 12b, an interlayer insulating film 13b, and an interlayer insulating film 14b. .
　絶縁体部ＩＰ４は、領域ＡＲ２で、絶縁体部ＩＰ３上に形成されている。絶縁体部ＩＰ４は、絶縁膜１５ｂを含む。絶縁膜１５ｂは、領域ＡＲ２で、層間絶縁膜１４ｂ上に形成された部分の絶縁膜１５からなる。 The insulator part IP4 is formed on the insulator part IP3 in the area AR2. The insulator part IP4 includes an insulating film 15b. The insulating film 15b is composed of a portion of the insulating film 15 formed on the interlayer insulating film 14b in the region AR2.
　本実施の形態２でも、実施の形態１と同様に、絶縁体部ＩＰ１の厚さＴＰ１に対する絶縁体部ＩＰ２の厚さＴＰ２の比は、絶縁体部ＩＰ３の厚さＴＰ３に対する絶縁体部ＩＰ４の厚さＴＰ４の比よりも大きい。 Also in the second embodiment, as in the first embodiment, the ratio of the thickness TP2 of the insulator portion IP2 to the thickness TP1 of the insulator portion IP1 is the ratio of the insulator portion IP4 to the thickness TP3 of the insulator portion IP3. It is larger than the ratio of the thickness TP4.
　絶縁体部ＩＰ２は、絶縁膜２０と、絶縁膜１５ａと、を含む。しかし、例えば窒化シリコンからなる絶縁膜２０を成膜する際の成膜条件を調整することにより、絶縁膜２０が引っ張り応力を有するように、調整することができる。同様に、例えば窒化シリコンからなる絶縁膜１５ａを成膜する際の成膜条件を調整することにより、絶縁膜１５ａが、絶縁体部ＩＰ３の引っ張り応力よりも小さい引っ張り応力を有するか、または、圧縮応力を有するように、調整することができる。 The insulator part IP2 includes an insulating film 20 and an insulating film 15a. However, the insulating film 20 can be adjusted to have a tensile stress by adjusting the film forming conditions when forming the insulating film 20 made of, for example, silicon nitride. Similarly, the insulating film 15a has a tensile stress smaller than the tensile stress of the insulator part IP3 or is compressed by adjusting the film forming conditions when forming the insulating film 15a made of silicon nitride, for example. It can be adjusted to have a stress.
　したがって、例えば絶縁膜２０の厚さと絶縁膜１５ａの厚さとを調整するか、または、絶縁膜２０の内部応力と絶縁膜１５ａの内部応力とを調整することにより、絶縁体部ＩＰ２が引っ張り応力を有し、絶縁体部ＩＰ４が、絶縁体部ＩＰ２の引っ張り応力よりも小さい引っ張り応力、または、圧縮応力を有するように、調整することができる。 Therefore, for example, by adjusting the thickness of the insulating film 20 and the thickness of the insulating film 15a, or by adjusting the internal stress of the insulating film 20 and the internal stress of the insulating film 15a, the insulator part IP2 can reduce the tensile stress. And the insulator part IP4 can be adjusted so as to have a tensile stress or a compressive stress smaller than the tensile stress of the insulator part IP2.
　また、例えば酸化シリコンからなる絶縁体部ＩＰ１を成膜する際の成膜条件を調整することにより、絶縁体部ＩＰ１が、絶縁体部ＩＰ２の引っ張り応力よりも小さい引っ張り応力を有するか、または、圧縮応力を有するように、調整することができる。さらに、例えば酸化シリコンからなる絶縁体部ＩＰ３を成膜する際の成膜条件を調整することにより、絶縁体部ＩＰ３が、絶縁体部ＩＰ２の引っ張り応力よりも小さい引っ張り応力を有するか、または、圧縮応力を有するように、調整することができる。 Further, for example, by adjusting the film formation conditions when forming the insulator part IP1 made of silicon oxide, the insulator part IP1 has a tensile stress smaller than the tensile stress of the insulator part IP2, or It can be adjusted to have a compressive stress. Furthermore, the insulator part IP3 has a tensile stress smaller than the tensile stress of the insulator part IP2, for example, by adjusting the film formation conditions when forming the insulator part IP3 made of silicon oxide, or It can be adjusted to have a compressive stress.
　したがって、本実施の形態２でも、実施の形態１と同様に、流量検出部７が、引っ張り応力を有するように、調整することができる。また、制御回路部８が、流量検出部７の引っ張り応力よりも小さい引っ張り応力を有するか、または、圧縮応力を有するように、調整することができる。 Therefore, in the second embodiment, similarly to the first embodiment, the flow rate detection unit 7 can be adjusted so as to have a tensile stress. Further, the control circuit unit 8 can be adjusted so as to have a tensile stress smaller than the tensile stress of the flow rate detection unit 7 or a compressive stress.
　本実施の形態２における絶縁体部ＩＰ２の厚さを、実施の形態１における絶縁体部ＩＰ２の厚さよりも厚くすることができる。したがって、本実施の形態２では、実施の形態１に比べ、絶縁体部ＩＰ２が空気に含まれる酸化窒素（ＮＯｘ）ガスなどにより腐食することを、容易に防止または抑制することができ、信頼性を容易に向上させることができる。 The thickness of the insulator part IP2 in the second embodiment can be made larger than the thickness of the insulator part IP2 in the first embodiment. Therefore, in the second embodiment, compared to the first embodiment, the insulator portion IP2 can be easily prevented or suppressed from being corroded by nitric oxide (NO x ) gas contained in the air. Can be easily improved.
　なお、本実施の形態２では、絶縁体部ＩＰ４に含まれる絶縁膜１５ｂと同層に形成された絶縁膜１５ａが、絶縁体部ＩＰ２に含まれる。そのため、絶縁体部ＩＰ４の厚さＴＰ４は、絶縁体部ＩＰ２の厚さＴＰ２よりも大きくなる。 In the second embodiment, the insulator part IP2 includes the insulating film 15a formed in the same layer as the insulating film 15b included in the insulator part IP4. Therefore, the thickness TP4 of the insulator part IP4 is larger than the thickness TP2 of the insulator part IP2.
　このような場合、絶縁体部ＩＰ１の厚さＴＰ１が、絶縁体部ＩＰ３の厚さＴＰ３と等しくても、絶縁体部ＩＰ１の厚さＴＰ１に対する絶縁体部ＩＰ２の厚さＴＰ２の比は、絶縁体部ＩＰ３の厚さＴＰ３に対する絶縁体部ＩＰ４の厚さＴＰ４の比よりも十分大きくなる。したがって、本実施の形態２では、実施の形態１と異なり、開口部ＯＰ１が形成されなくてもよい。 In such a case, even if the thickness TP1 of the insulator part IP1 is equal to the thickness TP3 of the insulator part IP3, the ratio of the thickness TP2 of the insulator part IP2 to the thickness TP1 of the insulator part IP1 is This is sufficiently larger than the ratio of the thickness TP4 of the insulator part IP4 to the thickness TP3 of the body part IP3. Therefore, in the second embodiment, unlike the first embodiment, the opening OP1 may not be formed.
　＜流量センサの製造工程＞
　図１６は、実施の形態２の流量センサの製造工程の一部を示す製造プロセスフロー図である。図１７および図１８は、実施の形態２の流量センサの製造工程中の要部断面図である。 <Manufacturing process of flow sensor>
FIG. 16 is a manufacturing process flow chart showing a part of the manufacturing process of the flow sensor according to the second embodiment. 17 and 18 are fragmentary cross-sectional views of the flow rate sensor according to Embodiment 2 during the manufacturing process.
　本実施の形態２でも、実施の形態１で図６～図９に示した工程と同様の工程（図１６のステップＳ１１およびステップＳ１２）を行って、半導体基板６を準備し、絶縁体部ＩＰ１および絶縁体部ＩＰ３を形成する。 Also in the second embodiment, the semiconductor substrate 6 is prepared by performing the same steps (step S11 and step S12 in FIG. 16) as those shown in FIGS. 6 to 9 in the first embodiment, and the insulator portion IP1. And the insulator part IP3 is formed.
　次に、本実施の形態２では、実施の形態１と異なり、開口部ＯＰ１を形成する（図１６のステップＳ２３）。このステップＳ２３の工程では、図１７に示すように、フォトリソグラフィ法およびドライエッチング法を用いて、領域ＡＲ１において、層間絶縁膜１４をパターニングする。すなわち、領域ＡＲ１で、層間絶縁膜１４をエッチングして除去する。これにより、図１７に示すように、領域ＡＲ１で、層間絶縁膜１４を貫通して層間絶縁膜１３に達する開口部ＯＰ１を形成する。 Next, in the second embodiment, unlike the first embodiment, the opening OP1 is formed (step S23 in FIG. 16). In the step S23, as shown in FIG. 17, the interlayer insulating film 14 is patterned in the region AR1 by using a photolithography method and a dry etching method. That is, the interlayer insulating film 14 is removed by etching in the region AR1. As a result, as shown in FIG. 17, an opening OP1 that penetrates the interlayer insulating film 14 and reaches the interlayer insulating film 13 is formed in the region AR1.
　このようにして開口部ＯＰ１を形成することにより、絶縁体部ＩＰ１は、絶縁膜１１ａ、層間絶縁膜１２ａおよび層間絶縁膜１３ａを含むが、層間絶縁膜１４ａを含まないものとなる。すなわち、開口部ＯＰ１を形成することにより、絶縁体部ＩＰ１の厚さＴＰ１を、絶縁体部ＩＰ３の厚さＴＰ３よりも薄くすることになる。そのため、絶縁体部ＩＰ１の圧縮応力が、絶縁体部ＩＰ３の圧縮応力よりも小さくなるように、調整することができる。 By forming the opening OP1 in this way, the insulator part IP1 includes the insulating film 11a, the interlayer insulating film 12a, and the interlayer insulating film 13a, but does not include the interlayer insulating film 14a. That is, by forming the opening OP1, the thickness TP1 of the insulator part IP1 is made thinner than the thickness TP3 of the insulator part IP3. Therefore, it can adjust so that the compressive stress of insulator part IP1 may become smaller than the compressive stress of insulator part IP3.
　次に、絶縁膜２０を形成する（図１６のステップＳ２４）。このステップＳ２４の工程では、実施の形態１で図１１を用いて説明した工程（図５のステップＳ１６）と同様の工程を行って、図１７に示すように、領域ＡＲ１で、絶縁体部ＩＰ１上に、絶縁膜２０を形成する。 Next, the insulating film 20 is formed (step S24 in FIG. 16). In the process of step S24, the same process as the process described in the first embodiment with reference to FIG. 11 (step S16 of FIG. 5) is performed, and as shown in FIG. An insulating film 20 is formed thereon.
　次に、絶縁膜１５を形成する（図１６のステップＳ２５）。このステップＳ２５の工程では、実施の形態１で図１０を用いて説明した工程（図５のステップＳ１３）と同様の工程を行って、図１８に示すように、領域ＡＲ１および領域ＡＲ２で、絶縁膜２０上および層間絶縁膜１４上に、絶縁膜１５を形成する。 Next, the insulating film 15 is formed (step S25 in FIG. 16). In the process of step S25, the same process as the process described in the first embodiment with reference to FIG. 10 (step S13 of FIG. 5) is performed, and as shown in FIG. 18, the regions AR1 and AR2 are insulated. An insulating film 15 is formed on the film 20 and the interlayer insulating film 14.
　このとき、領域ＡＲ１で、絶縁膜２０と、絶縁膜１５ａとを含む絶縁体部ＩＰ２が形成される。絶縁膜１５ａは、絶縁膜２０上に形成された部分の絶縁膜１５からなる。また、領域ＡＲ１で、半導体基板６の表面６ａ上に、絶縁体部ＩＰ１と、発熱抵抗体１７と、絶縁体部ＩＰ２と、を有する流量検出部７が、形成される。 At this time, the insulator portion IP2 including the insulating film 20 and the insulating film 15a is formed in the region AR1. The insulating film 15 a is composed of a portion of the insulating film 15 formed on the insulating film 20. In the region AR1, the flow rate detection unit 7 including the insulator part IP1, the heating resistor 17, and the insulator part IP2 is formed on the surface 6a of the semiconductor substrate 6.
　一方、領域ＡＲ２で、絶縁膜１５ｂを含む絶縁体部ＩＰ４が形成される。絶縁膜１５ｂは、層間絶縁膜１４ｂ上、すなわち、絶縁体部ＩＰ３上に形成された部分の絶縁膜１５からなる。また、領域ＡＲ２で、半導体基板６の表面６ａ上に、絶縁体部ＩＰ３と、制御回路ＣＲ１と、絶縁体部ＩＰ４と、を有する制御回路部８が、形成される。 On the other hand, the insulator part IP4 including the insulating film 15b is formed in the region AR2. The insulating film 15b is composed of a portion of the insulating film 15 formed on the interlayer insulating film 14b, that is, on the insulator portion IP3. In the region AR2, the control circuit unit 8 including the insulator part IP3, the control circuit CR1, and the insulator part IP4 is formed on the surface 6a of the semiconductor substrate 6.
　その後、実施の形態１で図１２～図１４を用いて説明した工程と同様の工程（図１６のステップＳ１７～ステップＳ１９）を行って、本実施の形態２の流量センサが形成される。 Thereafter, the same processes (steps S17 to S19 in FIG. 16) as those described in the first embodiment with reference to FIGS. 12 to 14 are performed to form the flow sensor of the second embodiment.
　前述した実施の形態１の流量センサの製造工程では、窒化シリコンからなる絶縁膜１５を形成した後、窒化シリコンからなる絶縁膜２０を形成してパターニングする。そのため、絶縁膜１５を形成した後、絶縁膜２０を形成する前に、絶縁膜２０のエッチングストッパとして、酸化シリコンからなる絶縁膜１６を形成する必要がある。 In the manufacturing process of the flow sensor of the first embodiment described above, after the insulating film 15 made of silicon nitride is formed, the insulating film 20 made of silicon nitride is formed and patterned. Therefore, it is necessary to form the insulating film 16 made of silicon oxide as an etching stopper for the insulating film 20 after forming the insulating film 15 and before forming the insulating film 20.
　一方、本実施の形態２の流量センサの製造工程では、絶縁膜１５を形成する前に、絶縁膜２０を形成してパターニングする。この場合、酸化シリコンからなる層間絶縁膜１４がエッチングストッパとして機能するため、絶縁膜１６を形成する必要がなく、流量センサの製造工程の工程数を削減することができる。 On the other hand, in the manufacturing process of the flow sensor according to the second embodiment, the insulating film 20 is formed and patterned before the insulating film 15 is formed. In this case, since the interlayer insulating film 14 made of silicon oxide functions as an etching stopper, it is not necessary to form the insulating film 16, and the number of steps of manufacturing the flow sensor can be reduced.
　なお、前述したように、本実施の形態２では、実施の形態１と異なり、開口部ＯＰ１を形成する必要がなく、流量センサの製造工程の工程数を、削減することができる。 As described above, in the second embodiment, unlike the first embodiment, it is not necessary to form the opening OP1, and the number of steps of manufacturing the flow sensor can be reduced.
　＜本実施の形態の主要な特徴と効果＞
　本実施の形態２の流量センサも、実施の形態１の流量センサが有する特徴と同様の特徴を有する。したがって、本実施の形態２の流量センサも、実施の形態１の流量センサが有する効果と同様の効果を有する。 <Main features and effects of the present embodiment>
The flow sensor of the second embodiment also has the same characteristics as the flow sensor of the first embodiment. Therefore, the flow sensor of the second embodiment also has the same effect as the flow sensor of the first embodiment.
　それに加えて、本実施の形態２では、絶縁体部ＩＰ２の厚さを、実施の形態１における絶縁体部ＩＰ２の厚さよりも厚くすることができるので、実施の形態１に比べ、絶縁体部ＩＰ２がＮＯｘガスなどにより腐食することを、容易に防止または抑制することができ、流量センサの信頼性を容易に向上させることができる。 In addition, in the second embodiment, since the thickness of the insulator portion IP2 can be made larger than the thickness of the insulator portion IP2 in the first embodiment, the insulator portion is compared with the first embodiment. It is possible to easily prevent or suppress IP2 from being corroded by NO x gas or the like, and it is possible to easily improve the reliability of the flow sensor.
　また、本実施の形態２では、実施の形態１に比べ、絶縁膜１６を形成する必要がなく、流量センサの製造工程の工程数を削減することができる。また、開口部ＯＰ１を形成する必要がなく、流量センサの製造工程の工程数を、削減することができる。
　（実施の形態３） Further, in the second embodiment, it is not necessary to form the insulating film 16 as compared with the first embodiment, and the number of steps of manufacturing the flow sensor can be reduced. Moreover, it is not necessary to form the opening OP1, and the number of steps of the flow sensor manufacturing process can be reduced.
(Embodiment 3)
　実施の形態１の流量センサでは、絶縁体部ＩＰ４は、絶縁体部ＩＰ２の絶縁膜２０と異なる絶縁膜１５ｂを含んでいた。一方、実施の形態３の流量センサでは、絶縁体部ＩＰ４は、絶縁体部ＩＰ２の絶縁膜２０ａと同層に形成された絶縁膜２０ｂを含んでおり、絶縁膜２０ａの厚さは、絶縁膜２０ｂの厚さよりも厚い。 In the flow sensor of the first embodiment, the insulator part IP4 includes an insulating film 15b different from the insulating film 20 of the insulator part IP2. On the other hand, in the flow rate sensor of the third embodiment, the insulator part IP4 includes the insulating film 20b formed in the same layer as the insulating film 20a of the insulator part IP2, and the thickness of the insulating film 20a is the insulating film. It is thicker than 20b.
　本実施の形態３の流量センサのうち、センサチップ３以外の各要素、および、センサチップ３のうち、絶縁体部ＩＰ１および絶縁体部ＩＰ２、ならびに、絶縁体部ＩＰ１および絶縁体部ＩＰ２よりも下方に位置する各要素については、実施の形態１の流量センサにおける各要素と共通である。したがって、実施の形態１の流量センサの各要素と共通の要素については、実施の形態１の流量センサにおける符号と同一の符号を付し、その説明を省略する。 Of the flow rate sensor according to the third embodiment, each element other than the sensor chip 3, and among the sensor chip 3, the insulator part IP1 and the insulator part IP2, and the insulator part IP1 and the insulator part IP2 About each element located below, it is common with each element in the flow sensor of Embodiment 1. Therefore, elements common to the elements of the flow sensor of the first embodiment are denoted by the same reference numerals as those of the flow sensor of the first embodiment, and the description thereof is omitted.
　＜流量センサ＞
　図１９は、実施の形態３の流量センサにおけるセンサチップの要部断面図である。図１９に示すように、センサチップ３は、半導体基板６と、流量検出部７と、制御回路部８と、を有する。 <Flow sensor>
FIG. 19 is a cross-sectional view of the main part of the sensor chip in the flow sensor according to the third embodiment. As shown in FIG. 19, the sensor chip 3 includes a semiconductor substrate 6, a flow rate detection unit 7, and a control circuit unit 8.
　本実施の形態３でも、実施の形態１と同様に、半導体基板６の表面６ａ上には、絶縁膜１１、層間絶縁膜１２、層間絶縁膜１３および層間絶縁膜１４が形成されている。 Also in the third embodiment, the insulating film 11, the interlayer insulating film 12, the interlayer insulating film 13, and the interlayer insulating film 14 are formed on the surface 6a of the semiconductor substrate 6 as in the first embodiment.
　本実施の形態３でも、実施の形態１と同様に、流量検出部７は、半導体基板６の表面６ａの領域ＡＲ１で、半導体基板６の表面６ａ上に形成されており、絶縁体部ＩＰ１と、発熱抵抗体１７と、絶縁体部ＩＰ２と、を有する。絶縁体部ＩＰ１は、領域ＡＲ１で、半導体基板６の表面６ａ上に形成されており、例えば、絶縁膜１１ａと、層間絶縁膜１２ａとを含む。 Also in the third embodiment, similarly to the first embodiment, the flow rate detection unit 7 is formed on the surface 6a of the semiconductor substrate 6 in the region AR1 of the surface 6a of the semiconductor substrate 6, and the insulator unit IP1. The heating resistor 17 and the insulator part IP2 are included. The insulator part IP1 is formed on the surface 6a of the semiconductor substrate 6 in the region AR1, and includes, for example, an insulating film 11a and an interlayer insulating film 12a.
　一方、本実施の形態３では、実施の形態１と異なり、絶縁膜１５（図２参照）および絶縁膜１６（図２参照）は形成されていない。また、領域ＡＲ１で、層間絶縁膜１４および層間絶縁膜１３には、層間絶縁膜１４および層間絶縁膜１３を貫通して層間絶縁膜１２ａに達する開口部ＯＰ１が形成されている。また、絶縁体部ＩＰ１は、領域ＡＲ１で形成されており、開口部ＯＰ１が形成された領域内に、配置されている。 On the other hand, in the third embodiment, unlike the first embodiment, the insulating film 15 (see FIG. 2) and the insulating film 16 (see FIG. 2) are not formed. In the region AR1, the interlayer insulating film 14 and the interlayer insulating film 13 are formed with an opening OP1 that penetrates the interlayer insulating film 14 and the interlayer insulating film 13 and reaches the interlayer insulating film 12a. The insulator part IP1 is formed in the area AR1, and is disposed in the area where the opening OP1 is formed.
　また、領域ＡＲ１で、絶縁体部ＩＰ１上には、例えば窒化シリコンからなる絶縁膜２０が、形成されている。絶縁体部ＩＰ２は、絶縁膜２０ａを含む。絶縁膜２０ａは、絶縁体部ＩＰ１上に形成された部分の絶縁膜２０からなる。 In the region AR1, an insulating film 20 made of, for example, silicon nitride is formed on the insulator portion IP1. The insulator part IP2 includes an insulating film 20a. The insulating film 20a includes a portion of the insulating film 20 formed on the insulator part IP1.
　本実施の形態３でも、実施の形態１と同様に、制御回路部８は、半導体基板６の表面６ａの領域ＡＲ２で、半導体基板６の表面６ａ上に形成されており、絶縁体部ＩＰ３と、制御回路ＣＲ１と、絶縁体部ＩＰ４と、を有する。絶縁体部ＩＰ３は、領域ＡＲ２で、半導体基板６の表面６ａ上に形成されており、例えば、絶縁膜１１ｂと、層間絶縁膜１２ｂと、層間絶縁膜１３ｂと、層間絶縁膜１４ｂと、を含む。 Also in the third embodiment, as in the first embodiment, the control circuit unit 8 is formed on the surface 6a of the semiconductor substrate 6 in the region AR2 of the surface 6a of the semiconductor substrate 6, and the insulator unit IP3. And a control circuit CR1 and an insulator part IP4. The insulator part IP3 is formed on the surface 6a of the semiconductor substrate 6 in the region AR2, and includes, for example, an insulating film 11b, an interlayer insulating film 12b, an interlayer insulating film 13b, and an interlayer insulating film 14b. .
　一方、本実施の形態３では、実施の形態１と異なり、絶縁体部ＩＰ４は、絶縁膜２０ｂを含む。絶縁膜２０ｂは、領域ＡＲ２で、絶縁体部ＩＰ３上に形成された部分の絶縁膜２０からなる。すなわち、絶縁膜２０ｂは、絶縁膜２０ａと同層に形成されている。これにより、絶縁膜２０ｂを、絶縁膜２０ａを形成する工程と同一の工程により、形成することができる。また、絶縁膜２０ａの厚さＴＰ２は、絶縁膜２０ｂの厚さＴＰ４よりも厚い。 On the other hand, in the third embodiment, unlike in the first embodiment, the insulator part IP4 includes the insulating film 20b. The insulating film 20b is composed of a portion of the insulating film 20 formed on the insulator portion IP3 in the region AR2. That is, the insulating film 20b is formed in the same layer as the insulating film 20a. Thereby, the insulating film 20b can be formed by the same process as the process of forming the insulating film 20a. The thickness TP2 of the insulating film 20a is thicker than the thickness TP4 of the insulating film 20b.
　本実施の形態３でも、実施の形態１と同様に、絶縁体部ＩＰ１の厚さＴＰ１に対する絶縁体部ＩＰ２の厚さＴＰ２の比は、絶縁体部ＩＰ３の厚さＴＰ３に対する絶縁体部ＩＰ４の厚さＴＰ４の比よりも大きい。 Also in the third embodiment, as in the first embodiment, the ratio of the thickness TP2 of the insulator portion IP2 to the thickness TP1 of the insulator portion IP1 is the ratio of the insulator portion IP4 to the thickness TP3 of the insulator portion IP3. It is larger than the ratio of the thickness TP4.
　本実施の形態３では、実施の形態１と異なり、例えば窒化シリコンからなる絶縁膜２０を成膜する際の成膜条件を調整することにより、絶縁膜２０ａ、および、絶縁膜２０ａと同層に形成される絶縁膜２０ｂが引っ張り応力を有するように、調整することができる。また、絶縁膜２０ａの厚さＴＰ２が、絶縁膜２０ｂの厚さＴＰ４よりも厚い。したがって、絶縁体部ＩＰ２が引っ張り応力を有するように、調整することができ、絶縁体部ＩＰ４が、絶縁体部ＩＰ２の引っ張り応力よりも小さい引っ張り応力を有するように、調整することができる。 In the third embodiment, unlike the first embodiment, the insulating film 20a and the insulating film 20a are formed in the same layer by adjusting the film forming conditions when forming the insulating film 20 made of, for example, silicon nitride. The insulating film 20b to be formed can be adjusted so as to have a tensile stress. Further, the thickness TP2 of the insulating film 20a is thicker than the thickness TP4 of the insulating film 20b. Therefore, it can adjust so that insulator part IP2 may have a tensile stress, and it can adjust so that insulator part IP4 may have a tensile stress smaller than the tensile stress of insulator part IP2.
　したがって、本実施の形態３でも、実施の形態１と同様に、流量検出部７が、引っ張り応力を有するように、調整することができる。また、制御回路部８が、流量検出部７の引っ張り応力よりも小さい引っ張り応力を有するか、または、圧縮応力を有するように、調整することができる。 Therefore, in the third embodiment, as in the first embodiment, the flow rate detection unit 7 can be adjusted so as to have a tensile stress. Further, the control circuit unit 8 can be adjusted so as to have a tensile stress smaller than the tensile stress of the flow rate detection unit 7 or a compressive stress.
　本実施の形態３では、絶縁体部ＩＰ２に含まれる絶縁膜２０ａと同層に形成された絶縁膜２０ｂが、絶縁体部ＩＰ４に含まれる。そのため、絶縁体部ＩＰ２が引っ張り応力を有する場合、絶縁体部ＩＰ４も引っ張り応力を有する。 In the present third embodiment, the insulating film 20b formed in the same layer as the insulating film 20a included in the insulating part IP2 is included in the insulating part IP4. Therefore, when the insulator part IP2 has a tensile stress, the insulator part IP4 also has a tensile stress.
　しかし、本実施の形態３では、実施の形態１と異なり、図１９に示すように、開口部ＯＰ１は、層間絶縁膜１４および層間絶縁膜１３を貫通して層間絶縁膜１２ａに達する。すなわち、本実施の形態３では、絶縁体部ＩＰ１の厚さＴＰ１に対する絶縁体部ＩＰ３の厚さＴＰ３の比が、実施の形態１に比べ、さらに大きくなる。このような場合、制御回路部８が、流量検出部７の引っ張り応力よりも小さい引っ張り応力、または、圧縮応力を有するように、容易に調整することができる。 However, in the third embodiment, unlike the first embodiment, as shown in FIG. 19, the opening OP1 penetrates through the interlayer insulating film 14 and the interlayer insulating film 13 and reaches the interlayer insulating film 12a. That is, in the third embodiment, the ratio of the thickness TP3 of the insulator portion IP3 to the thickness TP1 of the insulator portion IP1 is further increased as compared with the first embodiment. In such a case, the control circuit unit 8 can be easily adjusted so as to have a tensile stress or a compressive stress smaller than the tensile stress of the flow rate detection unit 7.
　なお、例えば絶縁体部ＩＰ２の厚さＴＰ２と、絶縁体部ＩＰ４の厚さＴＰ４との差が十分大きい場合には、絶縁体部ＩＰ１の厚さＴＰ１に対する絶縁体部ＩＰ２の厚さＴＰ２の比は、絶縁体部ＩＰ３の厚さＴＰ３に対する絶縁体部ＩＰ４の厚さＴＰ４の比よりも十分大きくなる。このような場合には、開口部ＯＰ１は、層間絶縁膜１４を貫通して層間絶縁膜１３に達するだけでよく、開口部ＯＰ１が、層間絶縁膜１３を貫通して層間絶縁膜１２に達しなくてもよい。 For example, when the difference between the thickness TP2 of the insulator part IP2 and the thickness TP4 of the insulator part IP4 is sufficiently large, the ratio of the thickness TP2 of the insulator part IP2 to the thickness TP1 of the insulator part IP1 Is sufficiently larger than the ratio of the thickness TP4 of the insulator part IP4 to the thickness TP3 of the insulator part IP3. In such a case, the opening OP1 only needs to reach the interlayer insulating film 13 through the interlayer insulating film 14, and the opening OP1 does not reach the interlayer insulating film 12 through the interlayer insulating film 13. May be.
　＜流量センサの製造工程＞
　図２０は、実施の形態３の流量センサの製造工程の一部を示す製造プロセスフロー図である。図２１および図２２は、実施の形態３の流量センサの製造工程中の要部断面図である。 <Manufacturing process of flow sensor>
FIG. 20 is a manufacturing process flowchart showing a part of the manufacturing process of the flow sensor according to the third embodiment. 21 and 22 are cross-sectional views of main parts during the manufacturing process of the flow sensor according to the third embodiment.
　本実施の形態３でも、実施の形態１で図６～図９に示した工程と同様の工程（図２０のステップＳ１１およびステップＳ１２）を行って、半導体基板６を準備し、絶縁体部ＩＰ１および絶縁体部ＩＰ３を形成する。 Also in the third embodiment, the semiconductor substrate 6 is prepared by performing the same processes (step S11 and step S12 in FIG. 20) as those shown in FIGS. 6 to 9 in the first embodiment, and the insulator portion IP1. And the insulator part IP3 is formed.
　次に、本実施の形態３では、実施の形態１と異なり、開口部ＯＰ１を形成する（図２０のステップＳ３３）。このステップＳ３３の工程では、図２１に示すように、フォトリソグラフィ法およびドライエッチング法を用いて、領域ＡＲ１において、層間絶縁膜１４および層間絶縁膜１３をパターニングする。まず、領域ＡＲ１で、層間絶縁膜１４をエッチングして除去する。次に、領域ＡＲ１で、層間絶縁膜１４が除去された部分の層間絶縁膜１３をエッチングして除去する。これにより、図２１に示すように、領域ＡＲ１で、層間絶縁膜１４および層間絶縁膜１３を貫通して層間絶縁膜１２に達する開口部ＯＰ１を形成する。 Next, in the third embodiment, unlike the first embodiment, the opening OP1 is formed (step S33 in FIG. 20). In the step S33, as shown in FIG. 21, the interlayer insulating film 14 and the interlayer insulating film 13 are patterned in the region AR1 by using a photolithography method and a dry etching method. First, in the region AR1, the interlayer insulating film 14 is removed by etching. Next, in the region AR1, the portion of the interlayer insulating film 13 from which the interlayer insulating film 14 has been removed is removed by etching. Thereby, as shown in FIG. 21, in the area AR1, an opening OP1 that penetrates the interlayer insulating film 14 and the interlayer insulating film 13 and reaches the interlayer insulating film 12 is formed.
　このようにして開口部ＯＰ１を形成することにより、絶縁体部ＩＰ１は、絶縁膜１１ａおよび層間絶縁膜１２ａを含むが、層間絶縁膜１３ａ（図３参照）および層間絶縁膜１４ａ（図９参照）を含まないものとなる。すなわち、開口部ＯＰ１を形成することにより、絶縁体部ＩＰ１の厚さＴＰ１を、絶縁体部ＩＰ３の厚さＴＰ３よりも薄くすることになる。そのため、絶縁体部ＩＰ１の圧縮応力が、絶縁体部ＩＰ３の圧縮応力よりも小さくなるように、調整することができる。 By forming the opening OP1 in this way, the insulator part IP1 includes the insulating film 11a and the interlayer insulating film 12a, but the interlayer insulating film 13a (see FIG. 3) and the interlayer insulating film 14a (see FIG. 9). Will not be included. That is, by forming the opening OP1, the thickness TP1 of the insulator part IP1 is made thinner than the thickness TP3 of the insulator part IP3. Therefore, it can adjust so that the compressive stress of insulator part IP1 may become smaller than the compressive stress of insulator part IP3.
　次に、絶縁膜２０を形成する（図２０のステップＳ３４）。このステップＳ３４の工程では、実施の形態１で図１１を用いて説明した工程（図５のステップＳ１６）の一部の工程と同様の工程を行って、図２１に示すように、領域ＡＲ１および領域ＡＲ２で、絶縁体部ＩＰ１上および絶縁体部ＩＰ３上に、絶縁膜２０を形成する。 Next, the insulating film 20 is formed (step S34 in FIG. 20). In the process of step S34, a part of the process described in the first embodiment with reference to FIG. 11 (step S16 of FIG. 5) is performed, and as shown in FIG. In the region AR2, the insulating film 20 is formed on the insulator part IP1 and the insulator part IP3.
　次に、絶縁膜２０をエッチングする（図２０のステップＳ３５）。このステップＳ３５の工程では、図２２に示すように、領域ＡＲ２で、絶縁膜２０をエッチングする。このとき、領域ＡＲ２で、絶縁膜２０をハーフエッチングする。これにより、図２１に示すように、領域ＡＲ１で、残された絶縁膜２０からなる絶縁膜２０ａが形成され、領域ＡＲ２で、領域ＡＲ１における絶縁膜２０ａの厚さＴＰ２よりも薄い厚さＴＰ４を有する絶縁膜２０ｂが形成される。 Next, the insulating film 20 is etched (step S35 in FIG. 20). In step S35, as shown in FIG. 22, the insulating film 20 is etched in the region AR2. At this time, the insulating film 20 is half-etched in the region AR2. As a result, as shown in FIG. 21, an insulating film 20a made of the remaining insulating film 20 is formed in the region AR1, and a thickness TP4 thinner than the thickness TP2 of the insulating film 20a in the region AR1 is formed in the region AR2. An insulating film 20b is formed.
　このとき、領域ＡＲ１で、絶縁膜２０ａを含む絶縁体部ＩＰ２が形成される。また、領域ＡＲ１で、半導体基板６の表面６ａ上に、絶縁体部ＩＰ１と、発熱抵抗体１７と、絶縁体部ＩＰ２と、を有する流量検出部７が、形成される。 At this time, the insulator part IP2 including the insulating film 20a is formed in the region AR1. In the region AR1, the flow rate detection unit 7 including the insulator part IP1, the heating resistor 17, and the insulator part IP2 is formed on the surface 6a of the semiconductor substrate 6.
　一方、領域ＡＲ２で、絶縁膜２０ｂを含む絶縁体部ＩＰ４が形成される。また、領域ＡＲ２で、半導体基板６の表面６ａ上に、絶縁体部ＩＰ３と、制御回路ＣＲ１と、絶縁体部ＩＰ４と、を有する制御回路部８が、形成される。 On the other hand, the insulator part IP4 including the insulating film 20b is formed in the region AR2. In the region AR2, the control circuit unit 8 including the insulator part IP3, the control circuit CR1, and the insulator part IP4 is formed on the surface 6a of the semiconductor substrate 6.
　その後、実施の形態１で図１２～図１４を用いて説明した工程と同様の工程（図２０のステップＳ１７～ステップＳ１９）を行って、本実施の形態３の流量センサが形成される。 Thereafter, the same processes (steps S17 to S19 in FIG. 20) as those described in the first embodiment with reference to FIGS. 12 to 14 are performed to form the flow sensor of the third embodiment.
　本実施の形態３の流量センサの製造工程では、絶縁膜２０ｂを、絶縁膜２０ａを形成する工程と同一の工程により、形成することができる。また、本実施の形態３の流量センサの製造工程では、絶縁膜１５（図３参照）および絶縁膜１６（図３参照）を形成しない。そのため、本実施の形態３では、実施の形態１に比べ、流量センサの製造工程の工程数を削減することができる。 In the manufacturing process of the flow sensor according to the third embodiment, the insulating film 20b can be formed by the same process as the process of forming the insulating film 20a. Further, in the manufacturing process of the flow sensor according to the third embodiment, the insulating film 15 (see FIG. 3) and the insulating film 16 (see FIG. 3) are not formed. Therefore, in this Embodiment 3, compared with Embodiment 1, the number of processes of the flow sensor manufacturing process can be reduced.
　＜本実施の形態の主要な特徴と効果＞
　本実施の形態３の流量センサも、実施の形態１の流量センサが有する特徴と同様の特徴を有する。したがって、本実施の形態３の流量センサも、実施の形態１の流量センサが有する効果と同様の効果を有する。 <Main features and effects of the present embodiment>
The flow sensor of the third embodiment also has the same characteristics as the flow sensor of the first embodiment. Therefore, the flow sensor of the third embodiment also has the same effect as the flow sensor of the first embodiment.
　本実施の形態３では、絶縁体部ＩＰ２が引っ張り応力を有する場合、絶縁体部ＩＰ４も引っ張り応力を有する。しかし、絶縁体部ＩＰ１の厚さＴＰ１に対する絶縁体部ＩＰ３の厚さＴＰ３の比を大きくすることにより、制御回路部８が、流量検出部７の引っ張り応力よりも小さい引っ張り応力、または、圧縮応力を有するように、容易に調整することができる。 In the third embodiment, when the insulator part IP2 has a tensile stress, the insulator part IP4 also has a tensile stress. However, by increasing the ratio of the thickness TP3 of the insulator part IP3 to the thickness TP1 of the insulator part IP1, the control circuit unit 8 has a tensile stress smaller than the tensile stress of the flow rate detection part 7 or a compressive stress. It can be easily adjusted to have
　また、本実施の形態３の流量センサの製造工程では、絶縁膜２０ｂを、絶縁膜２０ａを形成する工程と同一の工程により、形成することができ、絶縁膜１５（図３参照）および絶縁膜１６（図３参照）を形成しない。そのため、本実施の形態３では、実施の形態１に比べ、流量センサの製造工程の工程数を削減することができる。 Further, in the manufacturing process of the flow sensor of the third embodiment, the insulating film 20b can be formed by the same process as the process of forming the insulating film 20a, and the insulating film 15 (see FIG. 3) and the insulating film 16 (see FIG. 3) is not formed. Therefore, in this Embodiment 3, compared with Embodiment 1, the number of processes of the flow sensor manufacturing process can be reduced.
　以上、本発明者によってなされた発明をその実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。 As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.
　本発明は、流量センサに適用して有効である。 The present invention is effective when applied to a flow sensor.
　１　流量センサ
　２　リードフレーム
　２ａ　搭載部
　２ｂ　外部端子
　３　センサチップ
　４　ボンディングワイヤ
　５　モールド樹脂
　６　半導体基板
　６ａ　表面
　６ｂ　裏面
　７　流量検出部
　８　制御回路部
１１、１１ａ、１１ｂ　絶縁膜
１２、１２ａ、１２ｂ、１３、１３ａ、１３ｂ、１４、１４ａ、１４ｂ　層間絶縁膜
１５、１５ａ、１５ｂ、１６、２０、２０ａ、２０ｂ、２６ａ　絶縁膜
１７　発熱抵抗体
１８　上流側測温抵抗体
１９　下流側測温抵抗体
２１、２３　プラグ
２１ａ　金属膜
２２、２２ａ、２４　配線
２２ｂ、２４ａ、２７ａ　導体膜
２５、２８　拡散層
２６　ゲート絶縁膜
２７　ゲート電極
２９　電極パッド
３１　空気流量計
３２　支持体
３３　連結部
３４　空気通路
３５　副通路
４１～４３　絶縁膜
５１　モールド成型用金型
５２　モールド成型用空間
５３　モールド樹脂流入口
５４　空気流路用凸部
５５　凸部
ＡＲ１、ＡＲ２　領域
ＣＲ１　制御回路
ＤＦ１　ダイヤフラム構造
ＤＲ１　方向
ＩＰ１～ＩＰ４　絶縁体部
ＯＰ１、ＯＰ２　開口部
ＴＨ１、ＴＨ２　孔部
ＴＰ１～ＴＰ３、ＴＰ３１、ＴＰ４　厚さ
Ｔｒ　トランジスタ
ＴＲ１、ＴＲ２　溝部 DESCRIPTION OF SYMBOLS 1 Flow sensor 2 Lead frame 2a Mounting part 2b External terminal 3 Sensor chip 4 Bonding wire 5 Mold resin 6 Semiconductor substrate 6a Front surface 6b Back surface 7 Flow detection part 8 Control circuit parts 11, 11a, 11b Insulating films 12, 12a, 12b, 13 , 13a, 13b, 14, 14a, 14b Interlayer insulating films 15, 15a, 15b, 16, 20, 20a, 20b, 26a Insulating film 17 Heating resistor 18 Upstream temperature sensing resistor 19 Downstream temperature sensing resistor 21, 23 Plug 21a Metal film 22, 22a, 24 Wiring 22b, 24a, 27a Conductive film 25, 28 Diffusion layer 26 Gate insulating film 27 Gate electrode 29 Electrode pad 31 Air flow meter 32 Support body 33 Connecting portion 34 Air passage 35 Sub passage 41 43 Insulating film 51 Molding mold 52 Molding space 53 Mold resin Inlet 54 Air channel convex part 55 Convex part AR1, AR2 Region CR1 Control circuit DF1 Diaphragm structure DR1 Direction IP1 to IP4 Insulator part OP1, OP2 Opening part TH1, TH2 Hole parts TP1 to TP3, TP31, TP4 Thickness Tr Transistor TR1, TR2 Groove

Claims (15)

  1. 　第１主面と、前記第１主面と反対側の第２主面とを有する半導体基板と、
    　前記半導体基板の前記第１主面の第１領域で、前記半導体基板の前記第１主面上に形成され、流体の流量を検出する流量検出部と、
    　前記半導体基板の前記第１主面の第２領域で、前記半導体基板の前記第１主面上に形成され、前記流量検出部を制御する制御回路部と、
    　を備え、
    　前記流量検出部は、
    　前記第１領域で、前記半導体基板の前記第１主面上に形成された第１絶縁体部と、
    　前記第１絶縁体部と接触するように形成された発熱抵抗体と、
    　前記第１絶縁体部上に形成された第２絶縁体部と、
    　を有し、
    　前記制御回路部は、
    　前記第２領域で、前記半導体基板の前記第１主面上に形成された第３絶縁体部と、
    　前記第３絶縁体部内に形成され、前記発熱抵抗体を制御する回路と、
    　前記第３絶縁体部上に形成された第４絶縁体部と、
    　を有し、
    　前記第１絶縁体部および前記第３絶縁体部は、酸化シリコンからなり、
    　前記第２絶縁体部および前記第４絶縁体部は、窒化シリコンからなり、
    　前記第１絶縁体部の厚さに対する前記第２絶縁体部の厚さの比は、前記第３絶縁体部の厚さに対する前記第４絶縁体部の厚さの比よりも大きい、流量センサ。     A semiconductor substrate having a first main surface and a second main surface opposite to the first main surface;
    A flow rate detection unit that is formed on the first main surface of the semiconductor substrate in a first region of the first main surface of the semiconductor substrate and detects a flow rate of fluid;
    A control circuit unit that is formed on the first main surface of the semiconductor substrate in the second region of the first main surface of the semiconductor substrate and controls the flow rate detection unit;
    With
    The flow rate detector
    A first insulator portion formed on the first main surface of the semiconductor substrate in the first region;
    A heating resistor formed in contact with the first insulator portion;
    A second insulator portion formed on the first insulator portion;
    Have
    The control circuit unit is
    A third insulator formed on the first main surface of the semiconductor substrate in the second region;
    A circuit that is formed in the third insulator portion and controls the heating resistor;
    A fourth insulator portion formed on the third insulator portion;
    Have
    The first insulator part and the third insulator part are made of silicon oxide,
    The second insulator part and the fourth insulator part are made of silicon nitride,
    A flow rate sensor in which the ratio of the thickness of the second insulator part to the thickness of the first insulator part is larger than the ratio of the thickness of the fourth insulator part to the thickness of the third insulator part. .
  2. 　請求項１記載の流量センサにおいて、
    　前記第２絶縁体部は、引っ張り応力を有し、
    　前記第１絶縁体部、前記第３絶縁体部および前記第４絶縁体部は、前記第２絶縁体部の引っ張り応力よりも小さい引っ張り応力、または、圧縮応力を有する、流量センサ。     The flow sensor according to claim 1, wherein
    The second insulator part has a tensile stress,
    The flow rate sensor, wherein the first insulator part, the third insulator part, and the fourth insulator part have a tensile stress or a compressive stress smaller than a tensile stress of the second insulator part.
  3. 　請求項１記載の流量センサにおいて、
    　前記第２絶縁体部の厚さは、前記第４絶縁体部の厚さよりも厚い、流量センサ。     The flow sensor according to claim 1, wherein
    The flow rate sensor, wherein the second insulator part is thicker than the fourth insulator part.
  4. 　請求項１記載の流量センサにおいて、
    　前記第３絶縁体部は、前記第１絶縁体部と同層に形成され、
    　前記第１絶縁体部の厚さは、前記第３絶縁体部の厚さよりも薄く、
    　前記第２絶縁体部は、前記第１絶縁体部上から、前記第４絶縁体部の前記第１領域側の端部上にかけて形成されている、流量センサ。     The flow sensor according to claim 1, wherein
    The third insulator part is formed in the same layer as the first insulator part,
    The thickness of the first insulator portion is thinner than the thickness of the third insulator portion,
    The flow rate sensor, wherein the second insulator part is formed from the first insulator part to an end of the fourth insulator part on the first region side.
  5. 　請求項４記載の流量センサにおいて、
    　前記半導体基板の前記第２主面から前記半導体基板を貫通して前記第１絶縁体部に達する孔部を有し、
    　前記孔部は、平面視において、前記第１絶縁体部が形成された領域内に形成されている、流量センサ。     The flow sensor according to claim 4, wherein
    A hole extending from the second main surface of the semiconductor substrate to the first insulator through the semiconductor substrate;
    The hole is a flow rate sensor formed in a region where the first insulator is formed in a plan view.
  6. 　請求項４記載の流量センサにおいて、
    　前記第２領域で、前記第４絶縁体部および前記第２絶縁体部を覆うように形成された樹脂部を有し、
    　前記樹脂部の前記第１領域側の端部は、前記第４絶縁体部上に形成された部分の前記第２絶縁体部上に位置する、流量センサ。     The flow sensor according to claim 4, wherein
    A resin portion formed to cover the fourth insulator portion and the second insulator portion in the second region;
    An end of the resin portion on the first region side is a flow rate sensor located on the second insulator portion of a portion formed on the fourth insulator portion.
  7. 　請求項１記載の流量センサにおいて、
    　前記第１絶縁体部の厚さと前記第２絶縁体部の厚さとの和は、前記第３絶縁体部の厚さと前記第４絶縁体部の厚さとの和よりも小さい、流量センサ。     The flow sensor according to claim 1, wherein
    The sum of the thickness of the first insulator part and the thickness of the second insulator part is smaller than the sum of the thickness of the third insulator part and the thickness of the fourth insulator part.
  8. 　請求項１記載の流量センサにおいて、
    　前記第２絶縁体部は、
    　前記第１絶縁体部上に形成された第１絶縁膜と、
    　前記第１絶縁膜上に形成された第２絶縁膜と、
    　からなり、
    　前記第２絶縁膜は、前記第１絶縁膜上に、前記第４絶縁体部と同層に形成されており、
    　前記第１絶縁膜および前記第２絶縁膜は、窒化シリコンからなる、流量センサ。     The flow sensor according to claim 1, wherein
    The second insulator part is
    A first insulating film formed on the first insulator portion;
    A second insulating film formed on the first insulating film;
    Consists of
    The second insulating film is formed on the first insulating film in the same layer as the fourth insulator part,
    The flow rate sensor, wherein the first insulating film and the second insulating film are made of silicon nitride.
  9. 　請求項１記載の流量センサにおいて、
    　前記第４絶縁体部は、前記第２絶縁体部と同層に形成されており、
    　前記第４絶縁体部の厚さは、前記第２絶縁体部の厚さよりも薄い、流量センサ。     The flow sensor according to claim 1, wherein
    The fourth insulator part is formed in the same layer as the second insulator part,
    The flow rate sensor, wherein the fourth insulator part is thinner than the second insulator part.
  10. 　請求項４記載の流量センサにおいて、
    　前記第４絶縁体部上に形成された第３絶縁膜を有し、
    　前記第３絶縁膜は、酸化シリコンからなり、
    　前記第２絶縁体部は、前記第１絶縁体部上から、前記第３絶縁膜の前記第１領域側の端部上にかけて形成されている、流量センサ。     The flow sensor according to claim 4, wherein
    A third insulating film formed on the fourth insulator portion;
    The third insulating film is made of silicon oxide,
    The flow rate sensor, wherein the second insulator portion is formed from the first insulator portion to an end portion of the third insulating film on the first region side.
  11. 　請求項１記載の流量センサにおいて、
    　前記第３絶縁体部内に形成され、前記発熱抵抗体と前記回路とを電気的に接続する配線と、
    　前記第３絶縁体部内に形成され、前記回路と電気的に接続された電極と、
    　前記第４絶縁体部、および、前記電極上に位置する部分の前記第３絶縁体部を貫通して、前記電極に達する開口部と、
    　を有し、
    　前記開口部に露出した前記電極は、前記流量センサの外部と電気的に接続される、流量センサ。     The flow sensor according to claim 1, wherein
    A wiring formed in the third insulator portion and electrically connecting the heating resistor and the circuit;
    An electrode formed in the third insulator portion and electrically connected to the circuit;
    An opening that reaches the electrode through the fourth insulator and the third insulator of the portion located on the electrode;
    Have
    The electrode exposed at the opening is electrically connected to the outside of the flow sensor.
  12. 　（ａ）第１主面と、前記第１主面と反対側の第２主面とを有する半導体基板を準備する工程、
    　（ｂ）前記半導体基板の前記第１主面の第１領域で、前記半導体基板の前記第１主面上に、流体の流量を検出する流量検出部を形成する工程、
    　（ｃ）前記半導体基板の前記第１主面の第２領域で、前記半導体基板の前記第１主面上に、前記流量検出部を制御する制御回路部を形成する工程、
    　を備え、
    　前記（ｂ）工程は、
    　（ｄ）前記第１領域で、前記半導体基板の前記第１主面上に、第１絶縁体部を形成する工程、
    　（ｅ）前記第１絶縁体部と接触するように、発熱抵抗体を形成する工程、
    　（ｆ）前記第１絶縁体部上に、第２絶縁体部を形成する工程、
    　を有し、
    　前記（ｃ）工程は、
    　（ｇ）前記第２領域で、前記半導体基板の前記第１主面上に、第３絶縁体部を形成する工程、
    　（ｈ）前記第３絶縁体部内に、前記発熱抵抗体を制御する回路を形成する工程、
    　（ｉ）前記第３絶縁体部上に、第４絶縁体部を形成する工程、
    　を有し、
    　前記第１絶縁体部および前記第３絶縁体部は、酸化シリコンからなり、
    　前記第２絶縁体部および前記第４絶縁体部は、窒化シリコンからなり、
    　前記第１絶縁体部の厚さに対する前記第２絶縁体部の厚さの比は、前記第３絶縁体部の厚さに対する前記第４絶縁体部の厚さの比よりも大きい、流量センサの製造方法。     (A) preparing a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface;
    (B) forming a flow rate detection unit for detecting a flow rate of fluid on the first main surface of the semiconductor substrate in the first region of the first main surface of the semiconductor substrate;
    (C) forming a control circuit unit for controlling the flow rate detection unit on the first main surface of the semiconductor substrate in the second region of the first main surface of the semiconductor substrate;
    With
    The step (b)
    (D) forming a first insulator portion on the first main surface of the semiconductor substrate in the first region;
    (E) forming a heating resistor so as to be in contact with the first insulator portion;
    (F) forming a second insulator portion on the first insulator portion;
    Have
    The step (c)
    (G) forming a third insulator portion on the first main surface of the semiconductor substrate in the second region;
    (H) forming a circuit for controlling the heating resistor in the third insulator portion;
    (I) forming a fourth insulator part on the third insulator part;
    Have
    The first insulator part and the third insulator part are made of silicon oxide,
    The second insulator part and the fourth insulator part are made of silicon nitride,
    A flow rate sensor in which the ratio of the thickness of the second insulator part to the thickness of the first insulator part is larger than the ratio of the thickness of the fourth insulator part to the thickness of the third insulator part. Manufacturing method.
  13. 　請求項１２記載の流量センサの製造方法において、
    　前記（ｄ）工程は、
    　（ｄ１）前記第１領域で、前記半導体基板の前記第１主面上に、前記第３絶縁体部と同層に、前記第１絶縁体部を形成する工程、
    　（ｄ２）前記第１絶縁体部をエッチングすることにより、前記第１絶縁体部の厚さを、前記第３絶縁体部の厚さよりも薄くする工程、
    　を含み、
    　前記（ｆ）工程は、
    　（ｆ１）前記第１絶縁体部上に、第１絶縁膜を形成する工程、
    　（ｆ２）前記第１絶縁膜上に、第２絶縁膜を形成することにより、前記第１絶縁膜と前記第２絶縁膜とからなる前記第２絶縁体部を形成する工程、
    　を含み、
    　前記（ｆ２）工程では、前記第１絶縁膜上に、前記第４絶縁体部と同層に、前記第２絶縁膜を形成し、
    　前記第１絶縁膜および前記第２絶縁膜は、窒化シリコンからなる、流量センサの製造方法。     In the manufacturing method of the flow sensor according to claim 12,
    The step (d)
    (D1) forming the first insulator portion in the same region as the third insulator portion on the first main surface of the semiconductor substrate in the first region;
    (D2) a step of etching the first insulator portion to make the thickness of the first insulator portion thinner than the thickness of the third insulator portion;
    Including
    The step (f)
    (F1) forming a first insulating film on the first insulator portion;
    (F2) forming the second insulator portion including the first insulating film and the second insulating film by forming a second insulating film on the first insulating film;
    Including
    In the step (f2), the second insulating film is formed on the first insulating film in the same layer as the fourth insulator portion,
    The method for manufacturing a flow sensor, wherein the first insulating film and the second insulating film are made of silicon nitride.
  14. 　請求項１２記載の流量センサの製造方法において、
    　前記（ｄ）工程は、
    　（ｄ３）前記第１領域で、前記半導体基板の前記第１主面上に、前記第３絶縁体部と同層に、前記第１絶縁体部を形成する工程、
    　（ｄ４）前記第１絶縁体部をエッチングすることにより、前記第１絶縁体部の厚さを、前記第３絶縁体部の厚さよりも薄くする工程、
    　を含み、
    　前記（ｉ）工程は、
    　（ｉ１）前記第３絶縁体部上に、前記第２絶縁体部と同層に、前記第４絶縁体部を形成する工程、
    　（ｉ２）前記第４絶縁体部をエッチングすることにより、前記４絶縁体部の厚さを、前記第２絶縁体部の厚さよりも薄くする工程、
    　を含む、流量センサの製造方法。     In the manufacturing method of the flow sensor according to claim 12,
    The step (d)
    (D3) forming the first insulator portion in the same region as the third insulator portion on the first main surface of the semiconductor substrate in the first region;
    (D4) a step of etching the first insulator portion to make the thickness of the first insulator portion thinner than the thickness of the third insulator portion;
    Including
    The step (i)
    (I1) forming the fourth insulator part on the third insulator part in the same layer as the second insulator part;
    (I2) a step of etching the fourth insulator part to make the thickness of the four insulator parts thinner than the thickness of the second insulator part;
    A method for manufacturing a flow sensor, comprising:
  15. 　請求項１２記載の流量センサの製造方法において、
    　前記（ｄ）工程は、
    　（ｄ５）前記第１領域で、前記半導体基板の前記第１主面上に、前記第３絶縁体部と同層に、前記第１絶縁体部を形成する工程、
    　（ｄ６）前記第１絶縁体部上に、前記第４絶縁体部と同層に、第３絶縁膜を形成する工程、
    　（ｄ７）前記第３絶縁膜をエッチングして除去する工程、
    　（ｄ８）前記第３絶縁膜が除去された部分の前記第１絶縁体部をエッチングすることにより、前記第１絶縁体部の厚さを、前記第３絶縁体部の厚さよりも薄くする工程、
    　を含む、流量センサの製造方法。
          In the manufacturing method of the flow sensor according to claim 12,
    The step (d)
    (D5) forming the first insulator portion in the same region as the third insulator portion on the first main surface of the semiconductor substrate in the first region;
    (D6) forming a third insulating film on the first insulator portion in the same layer as the fourth insulator portion;
    (D7) etching and removing the third insulating film;
    (D8) The step of making the thickness of the first insulator portion thinner than the thickness of the third insulator portion by etching the first insulator portion in the portion where the third insulating film is removed. ,
    A method for manufacturing a flow sensor, comprising:
PCT/JP2015/061031 2014-05-28 2015-04-08 Flow rate sensor and method for manufacturing same WO2015182257A1 (en)

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US20070231942A1 (en) * 2001-01-10 2007-10-04 Vanha Ralph S Micromechanical flow sensor with tensile coating
EP2348292A1 (en) * 2010-01-13 2011-07-27 Sensirion AG Sensor device
JP2012202786A (en) * 2011-03-25 2012-10-22 Hitachi Automotive Systems Ltd Thermal type sensor and method for manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070231942A1 (en) * 2001-01-10 2007-10-04 Vanha Ralph S Micromechanical flow sensor with tensile coating
EP2348292A1 (en) * 2010-01-13 2011-07-27 Sensirion AG Sensor device
JP2012202786A (en) * 2011-03-25 2012-10-22 Hitachi Automotive Systems Ltd Thermal type sensor and method for manufacturing the same

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