WO2015171811A2 - Sram memory cells with 1 to 10 bits of single ended, potential line combination, nonvolatile data - Google Patents

Sram memory cells with 1 to 10 bits of single ended, potential line combination, nonvolatile data Download PDF

Info

Publication number
WO2015171811A2
WO2015171811A2 PCT/US2015/029530 US2015029530W WO2015171811A2 WO 2015171811 A2 WO2015171811 A2 WO 2015171811A2 US 2015029530 W US2015029530 W US 2015029530W WO 2015171811 A2 WO2015171811 A2 WO 2015171811A2
Authority
WO
WIPO (PCT)
Prior art keywords
latch
sram
cells
cell
nonvolatile
Prior art date
Application number
PCT/US2015/029530
Other languages
French (fr)
Other versions
WO2015171811A3 (en
Inventor
John Yit FONG
Original Assignee
Fong John Yit
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fong John Yit filed Critical Fong John Yit
Publication of WO2015171811A2 publication Critical patent/WO2015171811A2/en
Publication of WO2015171811A3 publication Critical patent/WO2015171811A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G11C14/0009—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a DRAM cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line

Definitions

  • the present invention relates to semiconductor chips that include a bit line word line matrix static random access memory (SRAM) memory cells with 1 or 2 or 3 or 4 physically separate latch power contacts from other matrix SRAM cells.
  • SRAM static random access memory
  • the SRAM cell with physically separate latch power contacts is encoded with 1 to 10 bits of single ended, potential line combination, nonvolatile data.
  • potential line combination, nonvolatile data can be made rewriteable using a soft programming line and the use of programmable resistance memory elements such as phase change memory (PCM) or resistive RAM (ReRAM) elements in supplying said SRAM latch power terminals.
  • PCM phase change memory
  • ReRAM resistive RAM
  • dark silicon dual supply drivers can be utilized for constructive purposes rather than simply power savings to provide SRAM power line switching for reading out nonvolatile data bits stored.
  • Dark silicon dual supply drivers are disclosed in references to Markoff entitled “Faster Chips May Come More Slowly", the New York Times, reprinted in the Dallas Morning News, quoting Doug Burger of Microsoft Research, Aug. 1 , 2011 , p. 4D; and Hadi et al. reference entitled “Dark Silicon & the End of Multicore Scaling", Proceedings of the 38 th International Symposium on Computer Architecture (ISCA 2011 ), June 4-8, 2011 . This is better than simply using rapidly growing "dark silicon” for one purpose only to prevent excessive microchip current leakage.
  • the invention provides a way to make a computer system dramatically faster as well as dramatically drop its power requirements.
  • the invention does so by providing the nonvolatile computer instructions and data normally needed from far away external nonvolatile memory like flash memory and stores them within multi-core processor cache memory cells themselves.
  • Nonvolatile data moving within a cache SRAM cell into its own self moves very fast with not much power.
  • Bistable latch memory cells able to store volatile data and their complement simultaneously are many and varied in form. Examples comprise and are not limited to: flip-flops such as set reset, JK, toggle, and equivalent that may be asynchronous, clocked, master-slave, etc. found within counters, registers, dividers, and such. Other examples comprise static random access memory (SRAM) cells with transistors ranging from 4, 5, 6, 7, 8, to 10 or more, with single ended or differential inputs or outputs, single ports to multi- ports, found within registers, register files, cache memories, and the like.
  • SRAM static random access memory
  • SRAM cells are generally described in the sample prior art combined schematics of FIG.1A, B, and C referenced and included in entirety from sources The. References include the article by Boleky, entitled “High Performance CMOS Memories Using Silicon-On- Sapphire Technology", April 1972 IEEE Journal of Solid-State Circuits Conference, see figure 10, p.142 of pp. 135-145; the article by T. Hirose, et al entitled “A 20-ns 4-Mb CMOS SRAM with Hierarchical Word Decoding Architecture", October 1990 IEEE Journal of Solid-State Circuits Conference, see Fig. 6, p. 1070 of pp.1068-1074; and U.S. Patent 5,461 ,338, to Hirayama.
  • FIG. 1A shows a SRAM cell, 10, repeated throughout a typical memory array.
  • a more than 40 year Industry practice is to allow only 1 coupling combination of the pair of latch positive power terminals to 1 positive supply like VDD shown and to allow only 1 coupling combination of the pair of latch negative power terminals to 1 negative supply line like GND also shown.
  • These short circuit couplings of latch power terminal pairs occur within the memory cell as well as external within a memory array power grid.
  • the loads, 3, and, 2, and drivers, 1 , and, 0, employed can vary from field effect transistor, depletion mode transistor, thin film transistor, diode, Schottky barrier diode, FinFET, tri-gate, CNT carbon nanotube, resistor, programmable resistor like memristor, phase change memory, solid electrolyte, resistive RAM, floating gate, efuse, or equivalent or composites of 16_23 " T° connect the volatile data node, Q1 , to bit line 1 , BL1 , and the complementary data node, Q0, to a possible bit line 0, BL0, pass gates, 4, and, 5, respectively, which can be positive or negative transistors or even diodes can be used.
  • Bit Line column precharge, 17, has pull up transistors, 15, and, 16, that are low voltage level, chip enabled ( /CE ) to positively charge up BL1 and BL0 before bit lines, BL1 , and, BL0, are differentially read.
  • Word line, WL is row activated by word line decoder, 14, where word line CMOS driver, 12, and, 11 , drive the word line and pass gate inputs, 4, and, 5, high and "on”.
  • Differential data, BL1 , and, BL0 are distinguished as a logic "1 " or "0" by sense amplifier, 22, which is turned on using, SE, sense enable ⁇ .
  • Memory array power
  • VDD, and, GND are full active "on” or reduced for memory sleep by power switches, 18, and, 19, that are also back gate biased to help reduce power switch leakage in sleep mode.
  • FIG. 2A and 2B a schematic and chip layout, of a small aspect ratio (SAR) 6 transistor CMOS SRAM cell typifies the latch memory cell that has dominated single and multi-core processor cache memory for the last decade.
  • SAR small aspect ratio
  • FIG. 2A schematic and 2B cell layout that both latch loads have their power terminals, T3 and T2, shorted to the same supply, VDD.
  • the latch drivers, 31 , and, 30, have their latch power terminals, T1 and TO, with only 1 coupling combination ie. shorted to the same named supply, VSS. See reference 28 especially FIG.
  • FIG. 3 The 3 dimensional transistor SRAM cells by IBM in 2010 is shown in FIG. 3.
  • FIG. 5B and 5C which shows scanning electron microscope (SEM) views of small aspect ratio (SAR) 3 dimensional (3D) Tri-Gate, static random access memory (SRAM) cells.
  • FIG. 5A like other prior art industry practice, the "latch load power terminals" for devices, P3 and P2, are short circuited together into a single positive supply, VDD, or, VCS, for cell stability.
  • the "latch driver power terminals" for, NO and N1 are also short circuited together like in prior art with, GND. Furthermore, in FIG. 5B and 5C the source/drain diffusion loads (shown) and their metal power terminal contacts between next neighbor SRAM cells are merged, shared, or integrated. Please see where the arrows in FIG. 5B and 5C with accompanying text are pointed at.”
  • the small aspect ratio (SAR) layout will differ in at least 1 or 2 latch power terminal metal contacts and their associated source/drain diffusions "not being shared” or “physically separate” within a SRAM cell, as well as between next neighbor SRAM cells.
  • An industry typical static random access memory (SRAM) or latch memory cell stores 1 differential, bistable, volatile data bit.
  • the invention latch cell comprises 2 differential latch loads both sharing 1 upper supply, ie. typically VDD, and 2 differential latch driver transistors both sharing 1 negative supply, ie. typically ground (GND).
  • VDD voltage supply
  • GND ground
  • nv coupling to the latch should be differential i.e. 2 couplings
  • nv storage elements should also be differential i.e. 2 nonvolatile elements.
  • An additional, 2 nd latch device coupled to 1 single ended, selective electrical connection with a 2 nd bus, encodes or programs: B [[LOG 2 (M)]] + [[LOG 2 (N)]], nonvolatile bits per 2 single ended, selectively supplied latch devices.
  • dual supply drivers can, if completely separate said buses are employed, preset or clear entire blocks of sequentially ordered word lines and bit lines of latch memory cells rather than individually writing each word line one at a time.
  • these SRAM or latch cells can be made nonvolatile rewritable by the addition of:(a) variable resistance memory elements within the series electrical connections between the bus potential lines and each latch power terminal being supplied, and
  • a soft programmed variable resistance memory element (b) a soft programmed variable resistance memory element, a soft programming line (SPL), to allow for connecting to these bus potential lines + ie. PCM memory element combinations for programming then for disconnecting from once programmed.
  • SPL soft programming line
  • nonvolatile data in ie. a nonvolatile SRAM array can be much greater than if shared power contacts had been used between neighboring cells.
  • DPL double patterning lithography
  • SIT sidewall image transfer
  • EUV extended ultraviolet light lithography
  • ebeam lithography etc.
  • vertical channel transistor latch memory cell layouts are more conducive to introducing physically separate latch power contacts with little or no cell area growth.
  • new cell layouts are shown that leverage word line to latch load gate or word line to latch driver gate couplings that remove the need for more difficult polysilicon to polysilicon spacing by removing the need for physical spaces to be inserted between poly lines.
  • FIG. 4A schematic & FIG. 4B cell layout drawings disclose SAR SRAM FIG. 4A schematic & FIG. 4B cell layout drawings; Ohbayashi, et al. article enttiled "A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits", 2006 Symposium on VLSI, see FIG. 1 SEM SAR SRAM cell layout & FIG. 2 SEM SAR straight diffusion cell layout with loads, drivers, & access transistors pointed out; Karl, et al. "A 4.6GHz 162Mb SRAM Design in 22nm Tri-Gate CMOS", 2012 ISSCC, assigned to Intel, discloses in FIG. 13.1 .1 SEM of high density 1 fin & 2 fin SAR SRAM cells plus FIG.
  • SRAM static random access memory
  • PU latch pull up
  • PD pull down
  • PU latch pull ups
  • PD pull downs
  • BL bit lines
  • WL word lines
  • PD pull downs
  • Another objective of the invention is to provide separate and interlocked positive and/or negative supply contacts with next neighbor SRAM cells within a memory array allowing for higher density nonvolatile data storage without the need to grow SRAM cell area.
  • Another object of the invention is to provide a SRAM with multi-bit nonvolatile data storage for at least a differential pair of SRAM latch PUs or PDs via selective coupling and encoding of nonvolatile data.
  • a memory device for storing 1 to 10 bits of single ended, potential line combination, nonvolatile data including a bit lines (BL), word lines (WL) memory array essentially of complementary, field effect transistor (FET) latch SRAM cells.
  • the latch transistors are selected from the group consisting of fully cross-coupled complementary FETs; P and N channel fully cross-coupled FETs; 3 dimensional fully cross- coupled complementary FETs; and 3 dimensional positive metal oxide latch transistor (PMOS), a negative metal oxide latch transistor (NMOS) fully cross-coupled complementary FETs.
  • the complementary field effect transistor is selected from the group consisting of FinFET transistors and Tri-Gate transistors.
  • each SRAM cell For each L potential lines there is a corresponding 1 to said L, said SRAM cells each selectively coupled to said 1 to said L potential lines, implementing each nonvolatile data and said selective encoding.
  • the latch PU or PD device are N separate, interlocked contacts.
  • the semiconductor memory chip further may include at least, L, M, P, and Q sets of said potential lines, a bit lines (BL), word lines (WL) memory array mainly of fully cross-coupled, complementary, field effect transistor (FET) Latch, SRAM cells , where all the latch pull ups
  • the set of potential lines there is a corresponding 1 to the L, M,
  • SRAM cells respectively each selectively coupled to said 1 to said L, M, P, and Q sets of potential lines, implementing each nonvolatile data said selective encoding.
  • the latch PU or PD device are N separate, interlocked said contacts.
  • said B 10 data bit(s) or digit(s) of nonvolatile data + 1 volatile bit of normal SRAM data.
  • SRAM cells respectively each selectively coupled to said 1 to said M and N sets of potential lines, implementing each nonvolatile data said selective encoding.
  • the differential pair of latch PUs or PD device(s) are said N separate, interlocked said contacts.
  • SRAM static random access memory
  • FET field effect transistor
  • latch pull-downs rather than the latch pull-ups above may instead be encoded with "single ended supplied" nonvolatile data.
  • This above nonvolatile data storage in said M & N SRAM cells can be constrained even further to wide SRAM adjacent to other 1 s sharing bit line contacts that also implement the above described "single ended supplied" nonvolatile data.
  • These wide SRAM cells would be approximately 2 transistors in length by at least 4 transistors in width. But even more unusual from wide SRAM cell to adjacent wide SRAM cells these cells would have at least 1 to 2 latch power contacts physically separate from adjacent SRAM cell(s) even though sharing bit line contacts between neighbor cells.
  • These possible dependent invention embodiments are better implemented to reduce both leakage power and cell area using FinFET, Tri-Gate, or equivalent SRAM cells.
  • a said matrix SRAM cell physically shares a 1 st & 2nd bit line contact with a 1 st & 2nd neighbor SRAM cells respectively. Yet unusually this matrix SRAM cell has 1 or 2 latch device power contacts physically separate from any other latch power contacts. This physical separation is made possible by these 1 or 2 latch devices being made laterally offset rather than substantially mounted upon or above any other SRAM cell transistor.
  • this matrix SRAM cell and its 1 st and 2nd neighbor cells have 4 transistor diffus-on tracks or the like substantially in a 1 st direction & 2 word line polysilicon tracks or the like substantially in a 2 nd direction. These can employ planar or vertical channel transistors, etc.
  • 6 transistor diffusion tracks or the like are employed. These 6 diffusion tracks, for modern cell power needs, employ vertical channel transistors that may be FinFET, Tri-gate, or the like or equivalent in nature.
  • word line polysilicon lines can, instead, run directly into gates of driver transistors without poly to poly separation and, in fact, that can actually help reduce SRAM cell leakage during word line "off' times, shutting off those driver gates & their current leakage when "off'.
  • DPL double patterning lithography
  • These bus lines can be shared with other matrix SRAM cells to reduce or minimize the # of lines needed as well as to then take advantage of the freed up cell area to make these potential lines even wider for lower resistance and faster response.
  • this SRAM invention can be limited to and combined with the first SRAM invention above where the cell layout has 1 or 2 physically separate latch power contacts, even with shared bit lines or share bit line contacts between next store neighbor SRAM cells.
  • the number of transistor diffusion tracks or the like can be limited to 4 or 6 aligned substantially in a 1 st direction with 2 word line, polysilicon tracks or the like aligned substantially in a 2 nd direction.
  • single ended nonvolatile data storage can be more than using differential coupling for the same # of potential lines used.
  • single ended nonvolatile data storage can be used in series of physically consecutive next neighbor SRAM cells using shared latch power contacts, but due to short circuit conflicts, differential coupling can not be used for every consecutive next neighbor SRAM cells where shared latch power contacts are employed.
  • At least 1 differential bus of potential lines supports a bit line, word line matrix of SRAM cells, to store differential nonvolatile data.
  • a consecutive series of next store neighbor to next store neighbor said matrix SRAM cells, each with all of its latch power contacts shared with neighboring SRAM cells is made to unusually store differential nonvolatile data.
  • the key is that every other cell, not every cell, of a series of next store neighbor SRAM cells has a pair of latch driver power contacts or pair of latch load power contacts coupled to some differential bus, wherein short circuit conflict between differential buses is, hence, prevented.
  • This above nonvolatile data storage in said M and N and P and optionally Q SRAM cells can be constrained even further to wide SRAM cells adjacent to other 1 s sharing bit line contacts that also implement the above described "single ended supplied" nonvolatile data.
  • These wide SRAM cells would be approximately 2 transistors in length by at least 4 transistors in width. But even more unusual from wide SRAM cell to adjacent wide SRAM cells these cells would have at least 3 to 4 latch power contacts physically separate from adjacent wide SRAM cell(s) sharing bit line contacts with neighbor cells.
  • These possible dependent invention embodiments are better implemented to reduce both leakage power and cell area using FinFET, Tri-Gate, or equivalent SRAM cells.
  • a said matrix SRAM cell physically shares a 1 st and 2nd bit line contact with a 1 st and 2nd neighbor SRAM cells respectively. Yet unusually this matrix SRAM cell has 3 or 4 latch device power contacts physically separate from any other latch power contacts. This physical separation is made possible by these 3 or 4 latch devices being made laterally offset rather than substantially mounted upon or above any other SRAM cell transistor.
  • this matrix SRAM cell and its 1 st and 2nd neighbor cells have 6 or 8 transistor diffusion tracks or the like substantially in a 1 st direction and 2 word line polysilicon tracks or the like substantially in a 2nd direction.
  • These 6 or 8 diffusion tracks for modern cell low power needs, employ vertical channel transistors that may be FinFET, Tri-gate, or the like or equivalent.
  • word line polysilicon lines can, instead, run directly into gates of driver transistors without poly to poly separation and, in fact, that can actually help reduce SRAM cell leakage during word line "off' times, shutting off those driver gates & their current leakage when "off'.
  • DPL double patterning lithography
  • These bus lines can be shared with other matrix SRAM to reduce # of lines needed as well as to take advantage of the freed up cell area to make these potential lines wider for lower resistance & faster response.
  • this SRAM invention can be limited to and combined with the first SRAM invention above where the cell layout has 3 or 4 physically separate latch power contacts, even with shared bit lines or share bit line contacts between next store neighbor SRAM cells.
  • the number of transistor diffusion tracks or the like can be limited to 6 or 8 aligned substantially in a 1 st direction with 2 word line, polysilicon tracks or the like aligned substantially in a 2 nd direction.
  • single ended nonvolatile data storage can be more than using differential coupling for the same # of potential lines used.
  • single ended nonvolatile data storage can be used in series of physically consecutive next neighbor SRAM cells using shared latch power contacts, but due to short circuit conflicts, differential coupling cannot be used for every consecutive next neighbor SRAM cells where shared latch power contacts are employed.
  • FIG. 1A illustrates a 1972 prior art, CMOS SRAM, static random access memory, array whose cells have a pair of positive and negative supply terminals, each pair, shorted electrically within cells & within memory arrays, the shorting, representing a more than 40 year industry practice;
  • FIG. 1 B is a SRAM differential sense amplifier;
  • FIG. 1 C (Prior Art) are lower supply sleep or full on power switches.
  • FIG. 2A and B shows a 2001 SRAM cell schematic and layout repeating the 40 year industry practice of electrically shorting SRAM cell positive supply terminals together and SRAM negative supply terminals together plus introducing a decade of Small Aspect Ratio (SAR) SRAM cell layouts where SRAM cell transistor diffusions all face the same direction for better manufacturing and least area ie. lithographically symmetric.
  • SAR Small Aspect Ratio
  • FIG. 3 shows a 2010, 3 dimensional transistor SRAM array schematic again continuing the 40 year industry practice of shorting SRAM cell VDD supplies together and GND supplies together within cells and within arrays.
  • FIG. 4 shows a nonvolatile programming table telling the # of supply/programming bus potential lines, "m", and "n” needed to program a latch memory cell with a specific # of binary digits.
  • FIG. 4 also shows which supply/programming bus potential lines should be "selectively supplied” to by the set reset memory cell to store a specific nonvolatile binary value are listed.
  • FIG. 5A is a schematic of a 2012, Intel 3D, 6 transistor SRAM cell, which following industry practice, shorts the latch load power terminals to 1 positive supply and shorts the latch driver power terminals to 1 negative supply.
  • FIG. 5B is a 2012 high density cell (HDC) layout of an Intel 3D, "single fin” , 6 transistor SRAM cell, which following industry practice, merges, integrates, and so shorts together its latch load power terminal source/drain diffusions with the next neighbor SRAM cell's latch load power terminal source/drain diffusions.
  • FIG. 5A is a schematic of a 2012, Intel 3D, 6 transistor SRAM cell, which following industry practice, shorts the latch load power terminals to 1 positive supply and shorts the latch driver power terminals to 1 negative supply.
  • FIG. 5B is a 2012 high density cell (HDC) layout of an Intel 3D, "single fin” , 6 transistor SRAM cell, which following industry practice, merges, integrates, and so shorts together its latch load power terminal
  • HDC high density cell
  • FIG. 6 is an example schematic of, 3 or more, 3D transistor, interlocked SRAM cells, each selectively supplying a "single latch power terminal" to 1 potential line of a supply- programming bus, V, of 2, 4, 8, 16, or more potential lines, thereby, encoding or storing 1 , 2, 3, 4, or more nonvolatile bits of data within said cells.
  • FIG. 7 is an example schematic of, 3 or more, 3D transistor, interlocked SRAM cells, storing 2 nonvolatile bits of data, "per pair of latch power terminals".
  • FIG. 8 is an example schematic of, 3 or more, 3D transistor, interlocked SRAM cells, storing 3 nonvolatile bits of data, "per pair of latch power terminals".
  • FIG. 9 is example schematic embodiments of, 3 or more, 3D transistor, interlocked SRAM cells, storing 4, 5, or 6 bits of nonvolatile data, per pair of latch power terminals based on programmed or selective supplying.
  • FIG. 10 is a 2 example truth table sequences, 55A and 55B, to read out 2 stored nonvolatile data digits separately when stored in a single latch power terminal; 2 example truth table sequences, 56A and 56B, to read out 3 stored nonvolatile data digits separately when stored in a single latch power terminal.
  • FIG.1 1 is a 2 example truth table sequences, 12A and 12B, to read out 4 stored nonvolatile data digits separately when stored in a single latch power terminal.
  • FIG. 12 is a 2 example truth table sequences, T1 -8 and T9-12, to read out 2 stored nonvolatile data digits separately when stored in a pair of latch power terminals.
  • FIG. 13 is a 2 example truth table sequences, 13A and 13B, to read out 3 stored nonvolatile data digits separately when stored in a pair of latch power terminals.
  • FIG. 14 is a 2 example truth table sequences, 14A and 14B, to read out 4 stored nonvolatile data digits separately when stored in a pair of latch power terminals.
  • FIG. 15 is a 2 example truth table sequences, 15A and 15B, to read out 5 stored nonvolatile data digits separately when stored in a pair of latch power terminals.
  • FIG. 16 is a 2 example truth table sequences, 16A and 16B, to read out 6 stored nonvolatile data digits separately when stored in a pair of latch power terminals.
  • FIG. 17 explains, for one embodiment, a generalized flowchart method of how to read out nonvolatile data digits stored in a multi-bit nonvolatile set reset memory.
  • FIG. 19 shows a series of exemplary invention chip layout embodiments of 1 of the best modes, a double pattern lithography (DPL), interlocked, 1 to 6 nonvolatile bit, multi-fin, 3D, 6 transistor, SRAM memory cells.
  • This layout example shows vertical channel transistor diffusions, silicon epitaxy, and double patterned poly-silicon and source/drain contacts. Note that ultra thin body (UTB) planar transistors are an alternative approach.
  • FIG. 20 illustrates one embodiment of the contact, metal 1 , and via 1 layers of the 2 interlocked cells begun in Fig. 19.
  • FIG. 21 illustrates one embodiment of the metal 2 and via 2 layers of the 2 interlocked cells begun in Fig. 19.
  • FIG. 22 illustrates one embodiment of the metal 3 and via 3 layers of the 2 interlocked cells begun in Fig. 19.
  • FIG. 23 illustrates one embodiment of the metal 4 and via 4 layers of the 2 interlocked cells begun in Fig. 19.
  • FIG. 24 illustrates 1 embodiment of metal 5, via 5, and above example mask programmed connections for controlling supply/nonvolatile programming buses like VDD1 and VDDO to selectively supply not only SRAM latch power but also nonvolatile encoded data to interlocked SRAM cells as in FIG. 19 in order to store within these cells 1 to 6 bit nonvolatile numbers.
  • FIG. 25 is an example embodiment of a series of interlocked latch memory cells, each with 1 same latch power terminal, selectively supplied by a different V bus potential line to store different 1 to 4 bit nonvolatile numbers per latch memory cell or more.
  • FIG. 33 shows an alternative to FIG. 19 with a 1 to 6 nonvolatile bit, SRAM memory cell or, bistable memory cell implementation, instead, using the word line signal, WL, coupled to a latch 3D FinFET transistor gate.
  • FIG. 34 shows an alternative to FIG. 19 with a 1 to 6 nonvolatile bit, SRAM memory cell or, bistable memory cell implementation, instead, using planar transistors, rather than 3 dimensional or vertical channel transistors.
  • FIG. 35 shows in detail what happens to the FIG. 33 3D FinFET SRAM with word line coupled latch load transistors that are modulated by a word line turning "on” and "off'.
  • FIG. 36 shows much of next store neighbor memory cells 70s and 71 s , their Metal 1 , Vial , and Metal 2 mask layers, from FIG. 20 and 21 , first with an additional cell 70s added below them. Next, these 3 cells are copied & basically mirrored about a Y axis parallel to bit line 0, BLO, to create additional cells, 70s, 71 s, and again cell 70s. The result is a matrix of 3 memory cells tall (ie. 3 word lines tall) by 2 cells wide.
  • FIG. 37 shows much of the Via3, Metal 3, and Via4 layers of cells 70s and 71 s from FIG. 35 in this matrix of 3 memory cells tall by 2 cells wide. Essentially, there are shown 3 word lines of memory cells tall by 2 complementary bit line pairs of memory cells wide.
  • FIG. directly below shows how to build a Soft Programming Line (SPL) structure for program connecting a V[*] potential line bus to a SRAM latch power terminal using Phase Change Memory (PCM) elements.
  • SPL Soft Programming Line
  • PCM Phase Change Memory
  • PCM Phase Change Memory
  • FIG. 38 a prior art known two next neighbor, 6T Dual Fin FinFET SRAM cells, and their layout with shared positive and negative supply contacts an diffusions shared.
  • FIG. 39 and FIG. 40 illustrate prior art shared latch power contacts for 6T SRAM cells.
  • FIG. 41 to FIG. 48 shows step by step how to create one of the invention embodiments: next neighbor SRAM cells where 1 pair of latch pull up (PU) transistors or load devices have been mirrored or flipped so that the resulting next neighbor SRAM cells can now have "separate and interlocked" supply contacts allowing for independent single ended, selective coupling for storing independent nonvolatile encoded data in each individual latch pull up (PU) .
  • PU latch pull up
  • FIG. 49 shows a nonvolatile programming table telling the # of supply/programming bus potential lines, "J", “K”, “M”, and optionally “N”, to program 3 or 4 of each latch memory cell's latch loads & latch drivers with a specific # of binary digits.
  • FIG. 49 also shows which supply/programming bus potential lines should be "selectively coupled" to by the latch cell to store a specific nonvolatile binary #.
  • FIG.50 is a schematic of a series of 3 or more, preferred mode, 3D SRAM cells, with source/drain diffusion power terminals, fully interlocked or physically offset yet both sharing the same cell border that depending on the # of potential lines used ie. j, k, m, and n, can each store a, B, # of bits of nonvolatile data where, B, is 1 value selected from the group consisting of 3b to 10b or more.
  • FIG. 51 is a preferred mode, bit line contact sharing, fully interlocked, series of 3D
  • SRAM cells storing "3 nonvolatile bits” via 3 latch power terminals selectively driven by potential lines in 3 supply/programming buses V, P, and Gnd.
  • FIG. 52 is a preferred mode, bit line contact sharing, fully interlocked, series of 3D
  • SRAM cells storing "4 nonvolatile bits" via 4 latch power terminals selectively driven by potential lines in 4 supply/programming buses V, P, Gnd, and L.
  • FIG. 53 is a preferred mode, bit line contact sharing, fully interlocked, series of 3D SRAM cells storing "5 nonvolatile bits” via 3 latch power terminals selectively driven by potential lines in 3 supply/programming buses V, P, Gnd, and L.
  • FIG. 54 is preferred mode, bit line contact sharing, fully interlocked, series of 3D SRAM cells storing "6 nonvolatile bits” via 4 latch power terminals selectively driven by potential lines in 4 supply/programming buses V, P, Gnd, and L.
  • FIG. 55 is a preferred mode, bit line contact sharing, fully interlocked, series of 3D SRAM cells storing "7 nonvolatile bits" via 4 latch power terminals selectively driven by potential lines in 4 supply/programming buses V, P, Gnd, and L.
  • FIG. 56 is a preferred mode, bit line contact sharing, fully interlocked, series of 3D SRAM cells storing "8 nonvolatile bits" via 4 latch power terminals selectively driven by potential lines in 4 supply/programming buses V, P, Gnd, and L.
  • FIG. 57 is a preferred mode, bit line contact sharing, fully interlocked, series of 3D SRAM cells storing "9 nonvolatile bits" via 4 latch power terminals selectively driven by potential lines in 4 supply/programming buses V, P, Gnd, and L.
  • FIG. 58 are preferred mode, bit line contact sharing, fully interlocked, series of 3D SRAM cells storing "10 nonvolatile bits" via 4 latch power terminals selectively driven by potential lines in 4 supply/programming buses V, P, Gnd, and L.
  • FIG. 59 is one possible embodiment flowchart, for reading out nonvolatile data digits, 1 bit at a time, stored within a latch load or latch driver, single ended, selectively driven by a bus of J, K, M, or N potential lines.
  • FIG. 60 is a timing diagram chart using FIG. 59's flowchart to read out the 3 bits of nonvolatile data stored within the FIG. 51 cells 1 10 and 1 1 1 one bit at a time.
  • FIG. 61 is a timing diagram chart using FIG. 59's flowchart to read out the 4 bits of nonvolatile data stored within the FIG. 52 cells 120 and 121 one bit at a time.
  • FIG. 62 and 63 is a timing diagram chart using FIG. 59's flowchart to read out the 5 bits of nonvolatile data stored within the FIG. 53 cells 130 and 131 one bit at a time.
  • FIG. 64 and 65 is a timing diagram chart using FIG. 59's flowchart to read out the 6 bits of nonvolatile data stored within the FIG. 54 cells 140 and 141 one bit at a time.
  • FIG. 66 and 67 is a timing diagram chart using FIG. 59's flowchart to read out the 7 bits of nonvolatile data stored within the FIG. 55 cells 150 and 151 one bit at a time.
  • FIG. 68 and 69 is a timing diagram chart using FIG. 59's flowchart to read out the 8 bits of nonvolatile data stored within the FIG. 56 cells 160 and 161 one bit at a time.
  • FIG. 70 and 71 is a timing diagram chart using FIG. 59's flowchart to read out the 9 bits of nonvolatile data stored within the FIG. 57 cells 170 and 171 one bit at a time.
  • FIG. 72 and 73 are timing diagram charts using FIG. 59's flowchart to read out the 10 bits of nonvolatile data stored within the FIG. 58 cells 180 and 181 one bit at a time.
  • FIG. 74 is one embodiment of 2 fully interlocked latch memory cell layouts with shared bit line contacts, where all 4 latch power terminals can be independently programmed to store like up to 10 nonvolatile data bits or more.
  • Each photo mask exposure like for contacts are depicted by one set of semiconductor contacts drawn with thick bold lines while another set of semiconductor contacts are drawn with thin lines to suggest 1 embodiment of 2 different double patterning masks to create cell contacts.
  • FIG. 75 is one embodiment of the contact and metal 1 layers for cells 190s and 191 s.
  • FIG. 76 is one embodiment of the vial and metal 2 layers for cells 190s and 191 s.
  • FIG. 77 is one embodiment of the via2 and metal 3 layers for cells 190s and 191 s.
  • FIG. 78 is one embodiment of the via3 and metal 4 layers for cells 190s and 191 s.
  • FIG. 79 are embodiments of via and metal layers for cells 190s and 191 s that can be used for selective driving by supply/programming buses, Gnd, and, L, in "3 bit or greater" nonvolatile latch memory cell implementations.
  • FIG. 80 are embodiments of via and metal layers for cells 190s and191 s that can be used for selective drivin by supply/programming buses, V, and, P, in "3 bit or greater" nonvolatile latch memory cell implementations.
  • FIG. 81 is a very wide, small aspect ratio (SAR) SRAM embodiment of 2 fully interlocked latch memory cells.
  • SAR small aspect ratio
  • long pass gate diffusions are implemented.
  • Double patterning lithography (DPL) or extended ultra violet (EUV) lithography are recommended if 0 cell area growth is desired.
  • DPL double patterning lithography
  • EUV extended ultra violet
  • FIG. 82 is the same layout as FIG. 81 except separate, rather than shared bit line contacts, are used.
  • FIG. 81 and 82 are wider than, and shorter in height than, SAR-like SRAM embodiments of SRAM cells whose 4 latch power terminals are all physically separate, independently accessible for nv programming like up to 10 bits or more.
  • FIG. 83 one example of supply/programming drivers, blocks 210s and 21 1 s, that can be used for both programming of nonvolatile latch memory cell data plus used for "dark silicon” applications like memory standby, hibernation, and total shutdown for leakage current control especially in billion transistor plus microchips.
  • FIG. 84 to FIG. 85 show how to build a Soft Programming Line (SPL) structure for program connecting a V[*] potential line bus to a SRAM latch power terminal using Phase Change Memory (PCM) elements.
  • SPL Soft Programming Line
  • PCM Phase Change Memory
  • FIG. 86 to FIG. 88 explain the steps to soft program connect a SRAM Latch Power Terminal to a V[*] potential line bus using a Soft Programming Line (SPL) then how to soft disconnect
  • FIG. 89 (another variation of FIG. 74) where a 6T SRAM with 4 Separate Latch Power Contacts, uses 6 transistor diffusion tracks in a 1 st direction and 2 word line, polysilicon tracks in a 2 nd direction.
  • FIG. 90 show Low Voltage, Writeable, 4 Separate Latch Power Contacts, 6T SRAM using 8 transistor, diffusion tracks in a 1 st direction & 2 word line, polysilicon tracks in a 2 nd direction.
  • WL "1 " or "on”
  • both driver transistors are at least 1 ⁇ 4 "on”, whichever of the two PMOS pull-up or load device or transistor is “on” will be weakened but not overcome. So, now, if a write data signal desires to pull that PMOS pull-up down to "0", it has an easier time.
  • FIG. 91 show Low Voltage, Writeable, 4 Shared Latch Power Contacts, 6T SRAM using 8 transistor, diffusion tracks in a 1 st direction and 2 word line, polysilicon tracks in a 2 nd direction. (Unlike FIG. 90 whose additional average cell area provides physically separate latch power contacts that can then be utilized to store single ended, potential line combination, nonvolatile data, these 6T SRAM cells focus more on smaller cell size without the ultimate in potential line combination nv data & focuses on low voltage, writeable and small cell size.)
  • FIG. 92 to 105 illustrate how to take the 6T SRAM using 8 transistor diffusion tracks with shared positive and negative supply contacts between next neighbor cells and create "separate and interlocked" said supply contacts so that direct injection of computer instructions into one cell do not affect adjacent cells. This also results in much higher data storage density.
  • SAR small aspect ratio.
  • SRAM static random access memory
  • inverter- There are various embodiments of an inverter that may be used in the invention. Basically, a simple inverter is a series circuit of an upper supply like a positive power supply like VDD connected to at least one load's 1 st terminal. Typical loads fall into various categories such as a type of resistor, diode, transistor, or programmable element. The 2 nd terminal of at least one said load electrically represents the inverter's output node. This output is a normally a digitally interpreted output with a logic "1 " or logic "0" as the usual final desired steady state output value after a new inverter electrical input is received.
  • This inverter's output node is also represented by and electrically shorted to a driver transistor's 2 nd terminal.
  • the driver transistor is usually a voltage controlled switch like a type of field effect transistor (FET).
  • FET field effect transistor
  • the driver transistor's 1 st terminal is then ususually connected to a lower supply like ground (GND).
  • GND ground
  • a voltage input to the inverter is normally presented to the driver transistor's input like a gate terminal. If the load is ie. a field effect transistor then it too will receive a gate terminal input signal.
  • the inverter voltage input signal is normally interpreted as a logic "1 " or logic "0" value.
  • the inverter's voltage output will be an opposite digital logic value to whatever was presented on the input.
  • the inverter output would be a logic “1 “ or “high” output, if a logic “1 “ or digitally interpreted “high” were an input to the inverter, the inverter output would be a logic "0” or “low” output.
  • More complex inverters can be constructed out of NAND gates or NOR gates as well.
  • latch - a digital memory cell storing bistable, volatile, digitally interpreted data like a logic "1 " or logic "0".
  • Simple latches are basically a pair of cross-coupled inverters constructed of a pair of typically 1 load plus 1 driver inverters. However, latches can also be constructed of a plural # of loads and drivers within cross-coupled, SR or Set Reset NAND gates or cross-coupled, Set Reset NOR gates, which are then if included with a clock input become a flip-flop.
  • This bistable, volatile, cross-coupled memory cell stores 1 bit of binary data which optional may have an asynchronous or clocked input or inputs for setting and resetting the memory cell's digital state.
  • Examples include: cross-coupled inverters, cross-coupled NAND gates, cross-coupled NOR gates, and the like or equivalent.
  • pass transistors, inverters, NAND gates, NOR gates may also be: pass transistors, inverters, NAND gates, NOR gates, that may be clocked or asynchronous for allowing inputs to change the digital state of the memory cell.
  • Examples providing latches with set reset capabilities include: cross-coupled NAND or NOR gates with asynchronous set and reset inputs, D and SR clocked latches; D, SR, JK, Toggle clock edge triggered flip-flops, SRAM cells of all types, etc.
  • the set reset inputs are surprisingly provided through the cross-coupled inverter's latch power terminals.
  • latch device- is specifically referring to 1 latch load or 1 latch driver.
  • the latch device can be, for example, a resistor, a diode, a schottky barrier diode, a transistor, a one time programmable fuse, a programmable memory element like a memristor, a phase change memory element (PCM), the like, or equivalent, etc.
  • a latch memory cell made of cross- coupled inverters will comprise typically 2 latch loads and 2 latch drivers or, in other words, 4 latch devices.
  • selectively driven - refers to a microchip manufacturer or a user having made a personalized choice between two or more different lines of a bus of potential lines to choose from for supplying an electrically driven signal for a bistable latch load or bistable latch driver power contact to receive.
  • the driving signal could be a fixed supply line or power line.
  • the driving signal could be a driver circuit output capable of transmitting at least 2 different digital values like a logic "1 " or logic "0", etc.
  • the personal choice or programming could have been accomplished by "mask programming" at the chip factory or foundry for which bus potential line to electrically connect or couple to.
  • the personal choice could be delayed until after the microchip has been completely manufactured and even programmed within the final system or "field programmable” by electrically pulling on only the desired bus potential line for driving that latch cell to a required programming current level to like set or reset a programmable memory element like: a phase change memory (PCM) element, or a resistive random access memory (ReRAM) element like a metal oxide, or a solid electrolyte, or a memristor, efuse, etc.
  • PCM phase change memory
  • ReRAM resistive random access memory
  • selectively supplied refers to a microchip manufacturer or a user having made a personalized choice between 2 or more different lines of a bus of potential lines to choose from for supplying an electrically driven signal for a bistable latch load or bistable latch driver power contact to receive.
  • the supplying signal could be a fixed supply line or power line.
  • the supplying signal could be a driver circuit output capable of transmitting at least 2 different digital values like a logic "1 " or logic "0", etc.
  • the personal choice or programming could have been accomplished by "mask programming" at the chip factory or foundry for which bus potential line to electrically connect or couple to.
  • the personal choice could be delayed until after the microchip has been completely manufactured and even programmed within the final system or "field programmable” by electrically pulling on only the desired bus potential line for supplying that latch cell to a required programming current level to like set or reset a programmable memory element like: a phase change memory (PCM) element, or a resistive random access memory (ReRAM) element like a metal oxide, or a solid electrolyte, or a memristor, efuse, etc.
  • PCM phase change memory
  • ReRAM resistive random access memory
  • B [[log 2 N]], binary bit or bits per 1 latch load or per 1 latch driver, where the mathematical function, [[ ]] , is the greatest integer function.
  • a single ended, selectively supplied nonvolatile data uses a 2 step process to read out encoded or stored data:
  • a selectively supplied latch load must have a means of presetting its storage node before read out of nonvolatile data encoded to its upper supply terminal like VDD.
  • a selectively supplied latch driver must have a means of pre-clearing its storage node before read out of nonvolatile data encoded to its lower supply terminal like GND.
  • This presetting or pre-clearing of storage nodes can be accomplished by the addition of SRAM pass transistors for performing the same, or through the use of latch loads or latch drivers driven by 2 potential line buses sharing no electrically common potential lines so that ie. one bus can has all its potential lines toggled so that the latch is forced to preset or preclear.
  • Step 2 a selectively supplied latch load or latch driver assigned bus lines should be pulsed low or high according to the nonvolatile data bit to be read out.
  • the invention flow charts show greater details. This illustrates not only how to build or make the invention and it also explains how to operate such an invention to obtain the unexpected result of increased encoding and storage of data.
  • the invention two step process as described above and in the flow chart with example timing diagrams accompanying them, provide detailed instructions on how to operate i.e. a nonvolatile SRAM by first presetting or pre- clearing followed by pulsing of appropriate bus lines for reading out "single ended" encoded, nonvolatile data.
  • differential programmed couplings are"dependent” not “independent” to one another.
  • latch power terminal 1 and 2 are differentially coupled to power supplies VDD1 and VDD2 respectively to store a "0" nonvolatile data bit then to store a "1 " nonvolatile data bit
  • latch power terminals 1 and 2 must be conversely differentially coupled to VDD2 and VDD1 , respectively.
  • 2 interconnect couplings must change each time 1 bit is changed from a "0" logic state to a "1 " state and vice versa. contacts physically separate- a phrase used herein with other similar versions of the same phrase indicating that 2 latch loads or 2 latch drivers have their semiconductor power contacts or substrate contacts physically offset from one another ie.
  • some type of insulation like silicon dioxide or field oxide is physically and electrically isolating these 2 latch load power contacts or 2 latch load driver power contacts away from each other. They may be made on the same chip layer but are physically offset from one another. Furthermore, not only are these contacts physically offset from each other and insulated from each other but their underlying source/drain diffusion they electrical connect to are also physically offset and electrically insulated from each other as well. Specifically, this physical and electrical isolation is on the substrate contact and transistor diffusion layers. However, the metal 1 and above layers are custom selectable or programmable by the factory or user.
  • each power contact has the freedom to be single ended, selectively electrically supplied by its own bus potential line or supply/nonvolatile programming line that can be the same or totally independent of its sister latch power contact.
  • the single ended electrical connections can provide more than 1 nonvolatile bit storage whereas prior art differential ended electrical connections have been shown to store only 1 nonvolatile bit.
  • latch load or latch driver power contact pairs are, "physically shared", between next store neighbor latch cells like SRAM cells are forced to share their nonvolatile data storage capability between adjoining cells which is half the data storage density possible verses if latch power contacts between next store neighbor cells are "physically separate.”
  • next store neighbor is a phrase referring to 2 same type memory cells like ie. 2 latch cells or like ie. 2 SRAM cells physically adjacent to each other without any other same type cell between them. Furthermore, if ie. 2 latch cells or ie. 2 SRAM cells are specifically indicated then these 2 next store neighbor SRAM cells will either electrically connect to at least a same bit line or electrically connect to a same word line, again, without any same type cell between them also electrically connected to the same bit line or the same word line.
  • next store neighbor cells or a group of next store neighbor cells can be formed as well.
  • each individual cell must have at least 1 same type cell physically adjacent to it without any same type cell between.
  • latch cells or SRAM cells are referred to, each individual cell must electrically connect to either a same word line or a same bit line as the next store neighbor cell.
  • interlocked refers to at least 2 next store neighbor, latch memory cells with pass gates with a shared bit line contact between these cells on call it side "A".
  • a 1 st latch memory cell has a latch load or latch driver transistor power contact physically separate from any other latch power contact.
  • a 2 latch memory cell also has a latch load or latch driver transistor power contact physically separate from any other latch power contact.
  • bistable latch memory cell programming table listed in FIG. 4 documents a sample listing of programmed, personalized bistable latch memory cells, specifically their "latch power terminal” or “terminals”, “selectively supplied by” single or dual supply-programming buses or simply potential line buses of, n, or, n and m, potential line structures (ie. structures can include interconnect lines, contacts, vias, and the like)
  • B [[ log2[ n] ]] for, n , being a non-power of 2 #, where the function, [[ ]] represents the greatest integer function.
  • Hard encoding means the selective, personalized, or programmed “interconnect” coupling that can be used in a semiconductor chip process which can include ie. metal wiring, polysilicon wiring, vias, contacts, and the like.
  • Soft encoding is also implied in this invention since resistive RAM, phase change memory, memristor, conductive bridge RAM, solid electrolyte, electrical fuse, etc. elements can be employed to accomplish the coupling desired as well.
  • Encoded values are interpreted for personal preference sake, ie. 1 of many possible embodiments, as follows. If a latch power terminal on the "true side” or “non-inverted output side” of a bistable latch memory cell were coupled to say potential line, 012, then the nonvolatile number stored in that latch memory cell we will interpret in personal preference to be the same or non-inverted value stored, 012- On the other hand, if a latch power terminal on the "complement side” or “inverted output side” of a bistable latch memory cell were coupled to say potential line, 1012 then the nonvolatile number stored in that bistable latch memory cell we will interpret, in personal preference, as saying the inverse is being stored or, OI O2 ⁇
  • FIG. 4 is applied in the upcoming bistable latch memory cell examples, FIG. 6, storing 1 , 2, 3, and 4 nonvolatile bits using a "single" latch power terminal per cell “selectively supplied” or encoded, and in FIG. 7 to 9, bistable latch memories storing: 2, 3, 4, 5, and 6 nonvolatile bits using 2 latch power terminals per cell both "selectively supplied” or so encoded.
  • M a bistable latch memory cell
  • k the identifying # of a bistable latch memory within a group of same like cells
  • B # of nonvolatile bits or binary digits stored within said bistable latch memory
  • [B-1 :0] indexes or addresses of each binary digit stored either:
  • a set of, n, and a set of, m, potential lines in a bistable latch memory cell can "share up to one potential line".
  • bistable latch memory cells storing 1 to 6 nonvolatile bits within either a single latch power terminal or a pair of latch power terminals are shown in FIG. 6, 7, 8, and 9.
  • Example 1 Cells with 1 Latch Power Terminal Storing 1 , 2, 4 and 8 Nonvolatile Bits
  • FIG. 6 a series of "single latch power terminal", selectively supplied, bistable latch memory cells, 55, 56, and 57.
  • FIG. 4 nonvolatile programming table lines: (a) A to B, (b) 3 to 6, (c) 11 to 18, and (d) 19 to 28,
  • the memory cell column of 3 "interlocked” * latch memory cells, with a, V, supply- program bus of, n 2, 4, 8 and 16, potential line structures, respectively, stores the following nonvolatile data within cells: 55, 56, & 57 as follows:
  • FIG. 9 a series of bistable latch memory cells, 66, 67, and 68.
  • potential line structures program coupled to, seen in switches, S12 to S17, of FIG. 9, the resulting, 4 bit nonvolatile numbers stored in cells, 66, 67, and 68 are:
  • FIG. 9 a series of bistable latch memory cells, 66, 67, and 68.
  • potential line structures program coupled to, seen in switches, S12 to S17, of FIG. 9, the resulting, 5 bit nonvolatile numbers stored in cells, 66, 67, and 68 are:
  • Example 6 Cells with 2 Latch Power Terminals Storing 6 Nonvolatile Bits Respectively
  • FIG. 9 a series of bistable latch memory cells, 66, 67, and 68.
  • potential line structures program coupled to, seen in switches, S12 to S17, of FIG. 9, the resulting, 6 bit nonvolatile numbers stored in cells, 66, 67, and 68 are:
  • the supply-programming buses, V, and, P provide normal operating power or are switched on and off to read out or release nonvolatile data like stored in cells, 55 through 68 into their respective volatile memory nodes, Q1 , and, Q0, using like circuit block, 72, or program switches, coupled to, VQ through V N and, PQ through P n _-
  • these program switches can be as simple as a single switch like using only a single transistor per supply-programming line, like only using NFET transistors, M m ⁇ to
  • MQ shown in circuit, 72, where a program switch "on” shorts a supply-programming line to a supply rail or virtual supply rail, achieving a 1 st logic state, and a program switch "off' or “float” might allow a memory cell's own internal current leakage to approach the opposite supply rail or virtual supply rail representing a 2 nd logic state.
  • a 2 nd example for these program switches can be a complete inverter for, instead, solidly supplying both logic states, like any inverter drivers, A n to AQ, shown in circuit block, 72, or specifically CMOS inverter drivers if both PFET transistors, MP m _i , through, MPrj, as well as, NFET transistors, M m ⁇ to MQ, are included.
  • a 3 rd example could be a series of larger and larger inverters building up to a final set of drivers, A n to AQ, allowing gradual drive build up of either logic state.
  • a 4 th example could be a decoder like a tree decoder ending in inverter drivers.
  • These and like circuits are all possible implementations for supplying the supply-program buses, V, and, P, for nonvolatile data read out. DARK SILICON SWITCHES FOR SLEEP OR HIBERNATION
  • a surprising constructive use of necessary, but unwanted power switches, or dark switches discussed in the background of invention can become multi-purpose, being leveraged to, first, serve as “supply/programming switches” as just discussed above for constructively reading out multi-bit nonvolatile data stored in bistable latch memories, as well, secondly, functioning as “dark silicon switches” providing but providing limited power to sections of large microchips to sleep or hibernate large memory arrays of circuit partitions without losing data. This is where the shown, Pbias- an d, Nbj as , would be modulated to controlled more accurately for sleep or hibernation modes.
  • the SRAM preset or preclear Method is based on pairs of supply/nonvolatile programming buses like VDD1 & VDDO in FIG. 6 to 9 that share 1 supply line in common so that fewer supply lines are required resulting in wider supply lines.
  • the steps follow the read flowchart FIG. 17 (please see!) & also read following:
  • (1 ) latch memory cells are 1 st initialized by turning SRAM word lines: WLO, WL1 , &
  • VDD1 and VDDO bus potential lines or supply/nonvolatile programming lines providing power to these latch memory cells' power contacts are binary coded based on typically the decoding logic coupled to their dual supply drivers, or the processor bus lines that drive them, or etc. These binary coded bus lines following the FIG. 17 flow chart are then pulsed "1 " or "0" based on the nonvolatile binary digit to be read.
  • VDD1 or VDDO bus supply/nonvolatile programming lines are then returned to
  • the 1 st or 2 nd Bus Preset or Preclear Method can be used for pairs of supply/nonvolatile programming buses like VDD1 & VDDO in FIG. 6 to 9 that are completely separate ie. no shared potential lines between 1 st & 2 nd buses.
  • the steps follow the read flowchart FIG. 17 (please read!) & generally are the following:
  • (1 ) latch memory cells in this case, are 1 st initialized by pulsing either all the 1 st bus supply lines or 2 nd bus supply lines.
  • the direction of the pulse ie. a "1 " or a "0" will be opposite the 1 st bus or 2 nd bus steady state voltage for providing normal latch memory cell power.
  • This pulsing of the entire 1 st or 2 nd bus supply lines will preset or preclear the latch memory cell.
  • latch load power terminals are made “1”
  • latch driver power terminals are made “low”.
  • V & 1 bit P supply-programming buses, whose potential lines, ie. are each coded as: O2 and 12- Timing Diagrams to Read Out 3 bit Nonvolatile Data
  • bistable latch memory cells of FIG. 8 we find that 3 bit data is stored within a "pair of latch load power terminals" of each of the memory cells, 63, 64, and 65. Following Read
  • FIG. 17 we can read FIG. 8's timing diagram table FIG. 14 and see that times
  • M65[2:0] 1012 , using a 2 bit, V & 1 bit P supply-programming buses, whose potential lines, ie. are each coded as:
  • bistable latch memory cells of FIG. 9 we find that 4 bit data is stored within a "pair of latch load power terminals" of each of the memory cells, 66, 67, and 68. Following Read
  • FIG. 17 we can read FIG. 9's timing diagram table FIG. 15 and see that times
  • T1 to T16 and times, T17 to T24, describe in detail the 2 different methods just discussed in section 10 above to read out the memory cell data stored:
  • V & 2 bit P supply-programming buses, whose potential lines, ie. are each coded as: OO2, 012> I O2- and, 11 2-
  • FIG. 9 In the bistable latch memory cells of FIG. 9 we find that 5 bit data is stored within a pair of latch load power terminals" of each of the memory cells, 66, 67, and 68. Following Read Flowchart, FIG. 17 , we can read FIG. 9's timing diagram table FIG. 16 and see that times, T1 to T20, and times, T21 to T30, describe in detail the 2 different methods just discussed in section 10 above to read out the memory cell data stored:
  • V & 2 bit P supply-programming buses, whose potential lines, ie. are coded as:
  • FIG. 9 we find that 6 bit data is stored within a "pair of latch load power terminals" of each of the memory cells, 66, 67, and 68.
  • FIG. 17 we can read FIG. 9's timing diagram table of FIG. 17 and see that times, T1 to T24, and times, T25 to T36, describe in detail the 2 different methods just discussed in section 10 above to read out the memory cell data stored:
  • V & 3 bit P supply-programming buses, whose potential lines, ie. are coded as:
  • FIG. 18A and 18B as another option displays the timing diagram table information in a timing diagram form, instead, for FIG. 7 cell 61 where nonvolatile 2b data is read out 1 digit or 1 bit at a time.
  • FIG. 25 is optional and is included if programmed memory elements if, for example, resistance variable memory elements ie. phase change memory (PCM) elements ie. GST (see Biblio 33 & 34 ) are used in FIG. 24 and up.
  • PCM phase change memory
  • FIG. 19 to 24 illustrate in detail, one of the implementations of 1 to 6 bit nonvolatile bistable latches as "interlocked", small aspect ratio (SAR), 3D, CMOS, 1 and 2 fin, 6 transistor SRAM cells, 70s, and 71 s, that with VDD1 and VDDO or 1 st and 2 nd bus supply/nonvolatile programming lines on metal layers shown in higher drawing layers, are able to electrically drive a pair of latch power terminals for single ended, selectively storing verses differentially storing 1 to 6 nonvolatile bits of data.
  • SRAM cells, 70s, and 71 s are one set of possible interlocked layout embodiments of schematic substrate cells, 66s, and, 67s, from FIG. 9.
  • FIG. 19 specifically shows the substrate level, "interlocked" SRAM cells, 70s, and, 71 s, and their vertical channel, 3 dimensional, N and P diffusion, transistors with polysilicon local interconnect, with contacts to upper metal layers.
  • the CMOS inverter supplies the true side, bit line 1 , BL1 , through pass gate, N5, is made up of dual fin NMOS driver, N1 a and N1 b, and PMOS load, P3.
  • the cross-coupled CMOS inverter supplies the complement side, bit line 0, BLO, through pass gate, N4, is made up of NMOS driver, NOa and NOb, and PMOS load, P2.
  • FIG. 19 to 24 the transistor diffusion and interconnect metal layers of SRAM cells like, 70, and, 71 , unlike industry practice in IBM FIG. 3 and Intel FIG. 5, are kept physically separate at the transistor diffusion, power contact, & metal layer levels (see FIG. 19) allowing personalized programming or selective electrically supplying from the upper metal layer VDD1 & VDDO bus potential lines to the lower level, substrate, latch power contacts VDD3, VDD2, VDD1 , & VDDO.
  • latch power contacts physically separate and physically independent, would seemingly increase SRAM cell area significantly with no apparent benefit.
  • latch power contacts, VDD1 and VDDO are interlocked or physically offset along SRAM 70's and SRAM 71 's shared cell border..
  • the inventions use of interlocking latch power terminals of neighboring SRAM cells has the potential advantage to keep SRAM cell area the same, even with the added benefit of integrating multi-bit nonvolatile data storage capability within a memory cell.
  • FIG. 19 shows word line polysilicon lines or gating like in pass transistors, N5 & N4, which come very close to latch feedback polysilicon lines or gating like in load transistors, P2 & P3. This is the distance labeled, d1 .
  • power contacts, VDD2 & VDDO also come very close to stretch contacts, Q1 & Q0, in adjacent SRAM cells. This is the distance labeled, d2.
  • This cell layout invention embodiment can be made possible by double patterning lithography (DPL) extended ultraviolet lithography (EUV), etc.
  • DPL double patterning lithography
  • EUV extended ultraviolet lithography
  • FIG. 34 A second SRAM cell layout solution is in FIG. 34.
  • word line and latch feedback polysilicon lines are instead separated by the manufacturing of double gate, vertical channel, transistors in between them. This is the short distance labeled, d3 .
  • a third SRAM cell layout solution uses planar transistors is shown in FIG. 35. Highlighted is the challenge of manufacturing local metal interconnect and polysilicon word line and latch feedback gating. Again, as in FIG. 19 manufacturing methods such as double patterning lithography (DPL), extended ultraviolet light (EUV) lithography, ebeam lithography, etc. are various means to accomplish the manufacturing of the three SRAM layouts just discussed above.
  • DPL double patterning lithography
  • EUV extended ultraviolet light
  • FIG. 20 shows the metal 1 and via 1 layers of two, interlocked, 3D, transistor, SRAM cells.
  • metal 1 is used to construct the complementary, volatile memory nodes, Q1 , and, Q0.
  • FIG. 21 shows the metal 2 layer lines to transmit word line signals, WLO, and, WL1 .
  • FIG. 22 shows the metal 3 layer lines to transmit SRAM cell differential input/output data, BL1 , and, BLO, plus a common ground array line, GND.
  • FIG. 23 shows the metal 4 layer lines to vertically align the latch power terminal pairs, VDD1 and VDDO, and, VDD3 and VDD2, with memory cell, 70s, and, 71 s, cell edges all in preparation for selective electrical supplying from later metal layers.
  • FIG. 24 shows metal 5 and above metal and via layers used for bus potential line, selective electrical supplying of positive latch power terminal pair, VDD1 and VDDO, and positive latch power terminal pair, VDD3 and VDD2, with VDD1 and VDDO supply-nonvolatile programming bus lines on metal 5 and up. Notice that the memory cell, 70s, and, 71 s, substrate level cell borders are smaller than the, 70, and, 71 , upper metal layer cell borders. This is because the, VDD1 , and, VDDO, supply-program bus potential lines are shared between neighboring substrate level cells.
  • Soft programming lines can be provided for programming the VDD1 or VDD1 & VDDO bus line, soft programmable memory elements shown as "programmed connections" in layers of FIG. 24 ie. resistance variable memory elements ie. phase change memory (PCM) ie. GST or ReRAM like metal oxides, etc.
  • a soft programming line can connect to and soft program connections of FIG. 24.
  • these FIG. 24 "programmed connections” can be hard mask programmed with some conductor or metal electrical connection, or can be fuse programmed with large soft programming line voltages applied.
  • Another invention embodiment is for multi-memory cells or series of memory cells or "k" number of memory cells.
  • Each of said "k” memory cells has a pair of latch load or latch driver power terminals with its own set or pair of, unique or different program coupling combinations with one or more same supply-side, supply-program buses like, V, and, P, shown in the next series of drawings storing multiple bits of nonvolatile data.
  • Drawing examples including "k” memory cells each uniquely program coupled to store different, nonvolatile, binary numbers of 1 to 6 bits per cell are demonstrated in FIG. 26, 27, 28, 29, 30, 31 , 32, and 33.
  • k memory cells invention embodiments are based on different values for “k memory cells” and whether 1 or 2 supply-program buses like, V, and, P, used in drawings FIG. 26, 27, 28, 29, 30, 31 , 32, and 33 are used to program couple nonvolatile data values into these "k” memory cells.
  • k memory cells “n”, “n+m”, and “nxm” for cells storing 1 to 6 nonvolatile bits are examples and not to be taken as the only possible examples. Many other combinations and lists of cells are not given below.
  • FIG 34. shows an alternative to FIG. 19 with a 1 to 6 nonvolatile bit, SRAM memory cell or, bistable memory cell implementation, instead, using the word line signal, WL, coupled to a latch transistor gate(s).
  • the embodiment shown is the word line, WL, to the P pull-up transistor gate which weakens the P pull-up when word line is "1 " or "on” allowing a "0" to more easily be written into said SRAM cell or bistable memory since the pass gate as shown has double gates or 2 current channels to, for example, overcome or defeat a P pull-up with only 1 gate "on” or only 1 current channel.
  • FIG. 35 shows an alternative to FIG. 19 with a 1 to 6 nonvolatile bit, SRAM memory memory cell or, bistable memory cell implementation, instead, using planar transistors, , rather than 3 dimensional or vertical channel transistors, specifically showing the following microchip manufacturing layers of:substrate, diffusion, polysilicon, contact, & metal 1 lines for local interconnect.
  • FIG. 36 explains in more pictorial detail what happens to FIG. 34 when the word line is "on” and "off.
  • the SRAM cell word line is "0" or “Off and this makes the P pull-up latch load transistors, with a dynamic Vtp, low in threshold voltage and so strong. This helps, therefore, during SRAM cell non-use, or standby mode, more stable and immune to noise.
  • the write margin of the SRAM is, therefore, improved.
  • FIG. 36 only shows parts of Metal 1 , Vial , and Metal 2 mask layers so as to reveal how the word lines, WLO, WL1 , and WL2, are connected.
  • the 3 SRAM cells tall of, 70s, 71 s ,and 70s are copied and mirrored about a Y axis that would be parallel to a bit line, BLO, through these 3 cells.
  • Another 3 cells tall are created: 70s, 71 s, and 70s, in FIG. 36.
  • FIG. 37 shows how the complementary bit line pair of, BL1 , &, BLO, plus pair, BL1 , &, BLO, are connected.
  • an example of next store neighbor SRAM memory cells are shown as either a matrix of 3 cells tall by 3 cells wide, or 3 word lines of cells tall by 2 complementary bit line pairs of cells wide.
  • Soft Programming Line for Programming, Bus Selectively Supplied, Variable Resistance Memory Electrically Connected, Latch Power Terminal Structure(s) making 1 to 6 Bit.
  • the SRAM cell latch power terminals ie. VDD1 & VDDO seen in FIG. 19 to 24 selectively supplied with voltages from the VDD1 bus of, N, potential lines & VDDO bus of,
  • M potential lines, seen in FIG. 24's upper metal mask layers can be electrically connected in many possible ways.
  • Hard mask programmed electrical connections, fuse connections, variable resistance memory element connections like using phase change memory (PCM), ReRAM elements like metal oxides, etc. are all within the scope of the invention.
  • FIG. 38 and 39 show how to build a latch cell with a soft programming line (SPL) structure for program connecting and disconnecting V[*] bus potential lines to a SRAM cell latch power terminal using phase change memory (PCM) elements.
  • SPL soft programming line
  • PCM phase change memory
  • This structure is soft programmed to allow PCM or GST memory elements to encode the attached latch or SRAM memory cell with: 1 bit, 2 bit, or more, potential line combination, nonvolatile bit(s).
  • FIG. 40 to FIG. 42 show steps to soft program connect a specific SRAM cell and its targeted SRAM Latch Power Terminal to a V[*] potential line bus.
  • PCM phase change memories
  • SPL soft programming line
  • FIG. 49 shows a schematic of specially paired, next neighbor, latch memory cells, 100s with 101 s, etc. which share common bit lines, but keep their positive latch power terminal contacts V3, V2, V1 , and V0, “physically separate”, and so “physically independent” as well as negative latch power terminal contacts G3, G2, G1 , and GO, “physically separate”, & so “physically independent” to allow for nonvolatile data programming and storage.
  • cells 100s with 101 s, etc. allow each latch power terminal the freedom, or "physical independence” to be “selectively driven” or “programmed to different supply/programming lines", but within an restricted set of potential lines, or buses, for each specific latch power terminal to choose from.
  • positive latch power terminals, V3, and, V1 can be individually and selectively driven by a potential line within the positive supply bus, V[ J-1 :0 ] through some coupling means like, S1 and S5.
  • negative latch power terminals, G3, and, G1 can be individually and selectively driven by a potential line within the negative or ground supply bus, Gnd[ M-1 :0 ] through some coupling means like, S3 and S7.
  • positive latch power terminals, V2, and, V0 can be individually and selectively driven or programmed by a potential line within the positive supply bus, P[ K-1 :0 ] through some coupling means like, S2 and S6.
  • BLO or "bit line 0 output side”
  • negative latch power terminals, G2, and, GO can be individually and selectively driven or programmed by a potential line within the negative or ground supply bus, L[ N-1 :0 ] through some coupling means like, S4 and S8.
  • Coupled means comprise, and are not limited to: mask manufactured vias or interconnect, via fuses that could be field or factory programmed, programmable resistive means like ReRAM elements, memristors, phase change memories, conductive bridge RAM elements, solid electrolyte memories, or the like.
  • the memory cell layout areas are keep the same, in spite of separating latch power terminals, one invention novelty meshes latch memory cells like, 100s and 101 s, with vertical channel transistors of "different number of fins".
  • cell, 100s can use “N” vertical channel pull down transistors with 2 fins or “dual fins” for faster memory read performance, however cell, 101 s, instead, would then offset, interlock, or mesh with cell, 100s, by either using "N” vertical channel pull down transistors with only 1 fin or a “single fin” per transistor or else cell, 101 s, will use “dual fin” N pull-down transistors, but with the cell height shorter and the cell width wider for a parallel diffusion cell layout.
  • latch "N” channel pull down transistors, NO, N1 , N10, and N11 are all, 3 dimensional, vertical channel transistors.
  • latch "P” channel pull up transistors, P2, P3, P12, and P13 are all, 3 dimensional, vertical channel transistors.
  • the equation defining the # of nonvolatile data bits stored by a latch cell is expanded to include at least "3" latch power contacts "selectively driven”, “personalized” or “programmed” to 3 potential lines of 3 supply/programming buses like:
  • V[J-1 ,0], P[K-1 ,0], and Gnd[M-1 ,0], respectively, is given as:
  • the equation can be further defined by the # of nonvolatile data bits stored by a latch memory cell with at least "4" latch power contacts "selectively driven” or “programmed” to 4 potential lines of 4 supply/nv programming buses like: V[J-1 ,0], P[K-1 ,0], Gnd[M-1 ,0], and L[N-1 ,0], respectively is given as:
  • FIG. 50 defines how to program or selectively drive the different positive latch power contacts, V3 to V0, and, G3 to GO, of memory cells, 100s, 101 s, etc. to different supply/programming buses of, "J, K, & M", or , "J, K, M, & N", number of potential lines in order to store 3 to 10 bits of nonvolatile data with the specific binary values listed in each row of the table.
  • FIG. 51 through FIG. 58 show specific memory cell pairs programmed to store specific binary values: 3, 4, 5, 6, 7, 8, 9, and 10 bit numbers using latch memory cell pairs, 110s & 111 s through 180s, 181 s.
  • FIG. 59 The sequential process to read each individual nonvolatile bit or digit hidden or stored within each of the latch memory cells of, FIG. 51 through FIG. 58, is described in the flow chart of FIG. 59.
  • the FIG. 59 flow chart is for latch memory cells with 3 to 4 physically separate latch power contacts accessible.
  • latch power terminals are not restricted to being only found within the cell substrate latch loads or drivers.
  • An alternative allows for 3 dimensional latch loads or drivers manufactured above the cell substrate level that tap directly off of the latch data terminals.
  • Example timing diagrams are listed in table format rather than timing diagram format, for reading each of the "nonvolatile digits" or “NVD[cell #]", stored in the 3, 4, 5, 6, 7, 8, 9, and 10 bit nonvolatile, latch memory cell schematics of, FIG. 51 through FIG. 58, and described in the timing tables rather than timing diagrams shown in FIG. 60 to FIG. 73. These all follow the nonvolatile data read out flowchart described in FIG. 59.
  • Example chip layouts of 3 to 10 bit nonvolatile, latch memory cell pair with physically separate positive and negative latch power terminals, two, 3D, vertical channel, SAR SRAM cells, are detailed in FIG. 74 to 80.
  • These process layers to manufacture cells 190 and 191 include their transistors plus interconnect layers, are symbolically drawn in the schematic of FIG. 49.
  • FIG. 74 is the latch cell layout embodiment for a dual fin, vertical channel, transistor latch layout interlocked with a single fin, vertical channel, transistor latch layout.
  • schematic transistors N5, N4, N15, and N14 represent cell layout pass transistors in the SRAM cell layouts 190s and 191 s.
  • Transistor schematic symbols, P3, P2, P13, and P12 represent latch loads in the SRAM cell layouts 190s and 191 s.
  • Transistor schematic symbols, NOa, NOb, N1 a, N1 b represent dual fin latch drivers for the SRAM cell layout 190s.
  • transistor schematic symbols, N11 and N10 represent single fin latch drivers for the SRAM cell layout 191 s.
  • the separate (+) positive latch power contact pair and separate (-) negative latch power contact pair can be identified as follows:
  • latch power terminal pairs as well as any other latch driver or load devices added to the bistable storage nodes, Q1 , and, Q0, are manufactured physically separate or physically independent to allow "independent programming” or “selective driving” to, generally, different supply/programming lines or potential lines for storing different values of nonvolatile data. """sharing of up to 1 potential line between different sets of supply/programming line buses is possible as long as the total # of supply/programming lines is 3 or greater.”
  • offset refers to a generic physical separation of latch power terminal, substrate contacts, of neighboring cells in any direction.
  • Interlocked in this patent refers to latch power terminal, substrate contacts, specifically separated or “physically offset” from each other along the cell substrate border like in FIG. 74 for V1 and V2.
  • neighboring latch memory cells are either “partially interlocked” meaning “1 pair” of latch power terminals are physically offset along the cell borders from other pairs of latch power terminals in adjacent cells, or the neighboring latch memory cells are “fully interlocked” meaning both positive and negative latch power terminal pairs are interlocked or physically offset along the cell borders with an adjacent cells.
  • the "best mode” cell layouts of neighboring cells accomplish “partial” or “full interlocking” without increasing the substrate area occupied by a normal latch memory cell.
  • the word line, polysilicon to polysilicon, line end to line end separation can be as small as the thickness of a 3D vertical channel pass transistor as demonstrated by highlighted distances, d1 , and, d2, shown in FIG. 74.
  • the latch devices, N11 & N10 are gate coupled to the word line, WL1 .
  • Means of achieving minimal to no cell area growth in spite of "physically separating latch power contacts” include: use of vertical channel or 3 dimensional transistors, like double gate devices; with word line to latch device coupling; use of double patterning lithography (DPL); use of extended ultraviolet (EUV) lithography; creation of a new cell layout where not only are all SRAM cell diffusions are in parallel, but they are all physically separate and none are series aligned. All so that different polysilicon line endpoints or metal 1 line endpoints can come into closer proximity than a single mask lithography process would normally allow.
  • DPL double patterning lithography
  • EUV extended ultraviolet
  • FIG. 74 for substrate, negative & positive diffusion, polysilicon, and contact layers
  • FIG. 75 for contact & metal 1 layers
  • FIG. 76 for vial , & metal 2 for memory cell word lines, WL0, and, WL1
  • FIG. 77 for via2, & metal 3 for memory cell bit lines or data lines, BL1 & BL0, where BL1 is the true output and BL0 is the complement output
  • FIG. 74 for substrate, negative & positive diffusion, polysilicon, and contact layers
  • FIG. 75 for contact & metal 1 layers
  • FIG. 76 for vial , & metal 2 for memory cell word lines, WL0, and, WL1
  • FIG. 77 for via2, & metal 3 for memory cell bit lines or data lines, BL1 & BL0, where BL1 is the true output and BL0 is the complement output
  • FIG. 74 for substrate, negative & positive diffusion, polysilicon, and contact layers
  • FIG. 75 for contact & metal 1 layers
  • FIG. 78 for via3, & metal 4 in one example embodiment to align V & G latch power terminals for subsequent metal layer program coupling;
  • FIG. 79 for vias 4 to 5, and metal layers 5 to 6 in one example embodiment for Gnd and L supply/programming lines selectively driven from negative latch power terminals, G;
  • FIG. 80 for vias 6 to 10, and metal layers 7 to 11 in one example embodiment for V and P supply/programming lines selectively driven from positive latch power terminals, V.
  • FIG. 74 SRAM cell layout has various possible variations to achieve READ & WRITE Margins. Let us consider the single fin, N pull-down cell, 191 s, which is the more challenging design case.
  • P13 & P12 pull-ups are strengthened with a small, Vtp, so that latch cell data is more stable.
  • FIG. 81 shows the layout of 2 next store neighbor, vertical channel, static random access memory (SRAM) cells with 1 shared bit line contact, BL1 , between these adjacent cells, plus complementary shared bit line contacts, BLO, with adjacent, SRAM cells, not shown, but located just above and just below these 2 cells.
  • SRAM static random access memory
  • FIG. 81 layout is similar to the FIG. 74 two small aspect ratio (SAR) SRAM embodiments of 2 fully interlocked, single fin, and double fin, vertical channel transistor, latch memory cell pair.
  • both cell 208s and 209s have both dual fin pull downs. Let us consider 2 different possible layout configurations of cell 209s and the impact on the SRAM READ & WRITE MARGINS.
  • Double Patterning Lithography (DPL) or extended ultra violet (EUV) lithography33 are recommended if zero cell area growth is desired.
  • double patterning bold wide lined, square contact symbols contrasted with narrow lined, square contact symbols are shown in the layout drawing, preferably, recommending to pattern a 1 st set of contacts in a 1 st photo mask exposure pass & a 2 nd set of, close proximity, contacts in a 2 nd photo mask exposure pass.
  • This latch memory cell pair layout has each cell with 4 latch device, power contacts independently accessible for nonvolatile selective drivin to store like up to 10 bits or more per cell.
  • the desired zero cell area growth is further attained by modifying the normal SAR SRAM layout or normal parallel diffusion SRAM cell layout.
  • FIG. 83 shows 1 schematic example of blocks, 210s & 211 s, of the supply/programming drivers, that can be used for (1 ) supplying power to maintain memory block, bistable, volatile, latch data; (2) for "dark silicon” or low power memory block operations like: memory standby, hibernation, shutdown, etc.; and (3) for nonvolatile programming bus lines.
  • dual supply, driver, switch banks 210s and 211 s can be leveraged for not just electrical current and supply power control via ie. preferably long length, low leakage, transistors like, MQ to and M PQ to M P ⁇ but can be modulated like in timing tables,
  • FIG. 60 to FIG. 73 for storing and recalling multiple bits of nonvolatile data per latch memory cell.
  • SPL Soft Programming Line
  • the SRAM cell latch power terminals i.e. V1 and VO seen in FIG. 74 selectively supplied with voltages from the V1 bus of, N, potential lines and VO bus, of, M, potential lines, seen in FIG. 58's upper metal mask layers, can be electrically connected in many possible ways. Hard mask programmed electrical connections, fuse connections, variable resistance memory element connections like using phase change memory (PCM), ReRAM elements like metal oxides, etc. are all possible and are within the scope of the invention.
  • PCM phase change memory
  • FIG. 83 and 84 show how to build a latch cell with a soft programming line (SPL) structure for program connecting and disconnecting V[*] bus potential lines to a SRAM cell latch power terminal using phase change memory (PCM) elements.
  • SPL soft programming line
  • PCM phase change memory
  • This structure is soft programmed to allow PCM or GST memory elements to encode the attached latch or SRAM memory cell with 1 bit, 2 bit or more, potential line combination, nonvolatile bit(s).
  • FIG. 85 to FIG. 86 illustrate the steps for soft program connect to a specific SRAM cell and is targeted SRAM Latch Power Terminal to a V[*] potential line bus. These figures provide background on variable resistance memories and specifically phase change memories (PCM).
  • PCM phase change memories
  • VSET or Vcrystallize voltage the voltage at which a (VRESET or Vamorphous state) or else a (VSET or Vcrystallize voltage) are never reached in these other, for example, memory row SRAM or latch cells so these stay unaffected.
  • SPL programming lines need not be row focused but can be 1 st direction with V[*] bus potential lines as a 2 nd direction.
  • FIG. 86 to FIG. 88 explain the steps to soft program connect a SRAM Latch Power Terminal to a V[*] potential line bus using a Soft Programming Line (SPL) then how to soft disconnect.
  • FIG. 89 is another variation of FIG. 74 where a 6T SRAM with 4 Separate Latch Power Contacts, uses 6 transistor diffusion tracks in a 1 st direction and 2 word line, polysilicon tracks in a 2 nd direction.
  • FIG. 90 show Low Voltage, Writeable, 4 Separate Latch Power Contacts, 6T SRAM using 8 transistor, diffusion tracks in a 1 st direction & 2 word line, polysilicon tracks in a 2 nd direction.
  • WL "1 " or "on”
  • both driver transistors are at least 1 ⁇ 4 "on”, whichever of the two PMOS pull-up or load device or transistor is “on” will be weakened but not overcome. So, now, if a write data signal desires to pull that PMOS pull-up down to "0", it has an easier time.
  • FIG. 91 show Low Voltage, Writeable, 4 Shared Latch Power Contacts, 6T SRAM using 8 transistor, diffusion tracks in a 1 st direction and 2 word line, polysilicon tracks in a 2 nd direction. (Unlike FIG. 90 whose additional average cell area provides physically separate latch power contacts that can then be utilized to store single ended, potential line combination, nonvolatile data, these 6T SRAM cells focus more on smaller cell size without the ultimate in potential line combination nv data & focuses on low voltage, writeable and small cell size.)
  • FIG. 92 to 105 illustrate how to take the 6T SRAM using 8 transistor diffusion tracks with shared positive and negative supply contacts between next neighbor cells and create "separate and interlocked" said supply contacts so that direct injection of computer instructions into one cell do not affect adjacent cells. This also results in much higher data storage density.

Abstract

A memory device for storing 1 to 10 bits of single ended, potential line combination, nonvolatile data including a bit lines (BL), word lines (WL) memory array essentially of complementary, field effect transistor (FET) latch SRAM cells; wherein the latch transistor has positive or negative supply contact such that the SRAM cell has at least N = 1 unshared, separate and interlocked latch transistor positive or negative supply contact with any of the next neighbor SRAM cells.

Description

SRAM MEMORY CELLS WITH 1 TO 10 BITS OF SINGLE ENDED, POTENTIAL LINE COMBINATION, NONVOLATILE DATA
FIELD OF THE INVENTION
The present invention relates to semiconductor chips that include a bit line word line matrix static random access memory (SRAM) memory cells with 1 or 2 or 3 or 4 physically separate latch power contacts from other matrix SRAM cells. In particular, the SRAM cell with physically separate latch power contacts is encoded with 1 to 10 bits of single ended, potential line combination, nonvolatile data. Such potential line combination, nonvolatile data can be made rewriteable using a soft programming line and the use of programmable resistance memory elements such as phase change memory (PCM) or resistive RAM (ReRAM) elements in supplying said SRAM latch power terminals.
BACKGROUND OF THE INVENTION
Today's computers have rapidly shrunk in size from room-sized mainframes, to desktops, to laptops, to Apple iPads, and near release of Google glasses to consumers. This invention seeks to overcome much of the cost, power, and speed problems anticipated with deploying wearable computers like Apple's (see U.S. Patent No 8,212,859) and Google's eye glass computers (see reference to Barak entitled "Google, Unveils Project Glass .." EETimes, 4/5/2012). By leveraging 3D transistorsi or equivalent solutions, in new ways, we can bring from quite a distance afar, traditionally off-chip, nonvolatile memory code, and easily mount at least 1 to 6 nonvolatile data bits vertically on top single, 1 bit, SRAM memory cells. (See references to Shimpi, entitled "Intel Announces First 22nm 3D Tri-Gate Transistors, Shipping in 2H 2011 ", www.AnandTech.com, May 4, 2011 and http://www.intel.com/lntel Reinvents Transistors Using New 3-D Structure Intel Newsroom > News Stories > 2011 > May > 04).
Further, "dark silicon" dual supply drivers can be utilized for constructive purposes rather than simply power savings to provide SRAM power line switching for reading out nonvolatile data bits stored. Dark silicon dual supply drivers are disclosed in references to Markoff entitled "Faster Chips May Come More Slowly", the New York Times, reprinted in the Dallas Morning News, quoting Doug Burger of Microsoft Research, Aug. 1 , 2011 , p. 4D; and Hadi et al. reference entitled "Dark Silicon & the End of Multicore Scaling", Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011 ), June 4-8, 2011 . This is better than simply using rapidly growing "dark silicon" for one purpose only to prevent excessive microchip current leakage.
However, eye glass and wearable computers need a dramatic drop in current computer system power needs to be commercially possible. The invention provides a way to make a computer system dramatically faster as well as dramatically drop its power requirements. The invention does so by providing the nonvolatile computer instructions and data normally needed from far away external nonvolatile memory like flash memory and stores them within multi-core processor cache memory cells themselves. Nonvolatile data moving within a cache SRAM cell into its own self moves very fast with not much power.
Bistable latch memory cells able to store volatile data and their complement simultaneously are many and varied in form. Examples comprise and are not limited to: flip-flops such as set reset, JK, toggle, and equivalent that may be asynchronous, clocked, master-slave, etc. found within counters, registers, dividers, and such. Other examples comprise static random access memory (SRAM) cells with transistors ranging from 4, 5, 6, 7, 8, to 10 or more, with single ended or differential inputs or outputs, single ports to multi- ports, found within registers, register files, cache memories, and the like.
These examples are represented by the following references: Terman article entitled, "MOSFET Memory Circuits", Proceedings of the IEEE, Vol. 59, No. 7, July 1971 , pp.1044- 105 discussing loadless 4 transistor (4T) NMOS SRAM, transistor (6T) NMOS SRAM, 6 transistor CMOS SRAM and memory address decoder drivers, word lines, bit lines, andsense amplifiers; U.S. Patent 3,535,699 to Gaensslen; Noda article entitled "A Loadless CMOS Four-Transistor SRAM Cell in a 0.18-um Logic Technology", IEEE Transactions on Electron Devices, Vol. 48, No. 12, December 2001 , pp. 2851 -282855, disclosing a 2 PMOS pass gate 2 NMOS drive transistor SRAM; U.S. Patent 6,731 ,533 to Deng et al. disclosing a 4 transistor SRAM with N pass gates and PMOS loads; U.S. Patent 3,521 ,242 to Katz disclosing 5 transistor CMOS SRAM with PMOS pass gate , and 6 transistor CMOS SRAM with PMOS pass gates; U.S. Patent 3,644,907 to Gricchi disclosing 5 transistor CMOS SRAM with NMOS pass gate, and 5 transistor CMOS SRAM with PMOS pass gate; Ping-Wei Wang, et al, "Methods and Apparatus for SRAM Bit Cell with Low Standby Current, Low Supply Voltage and High Speed", 2011 U.S. Patent Application Publication, see 8 transistor CMOS FinFET SRAM schematic and cell layout with shorted VDD terminals and shorted GND terminals figure 4 and 5, see 10 transistor CMOS SRAM; and the Suzuki, et.al . article entitled, "A Stable SRAM Cell Design Against Simultaneously R/W Disturbed Access", 2006 Symposium on VLSI Circuits, disclosing 8 transistor CMOS SRAM layout and schematic and 7 transistor CMOS SRAM layout and schematic.
SRAM cells are generally described in the sample prior art combined schematics of FIG.1A, B, and C referenced and included in entirety from sources The. References include the article by Boleky, entitled "High Performance CMOS Memories Using Silicon-On- Sapphire Technology", April 1972 IEEE Journal of Solid-State Circuits Conference, see figure 10, p.142 of pp. 135-145; the article by T. Hirose, et al entitled "A 20-ns 4-Mb CMOS SRAM with Hierarchical Word Decoding Architecture", October 1990 IEEE Journal of Solid-State Circuits Conference, see Fig. 6, p. 1070 of pp.1068-1074; and U.S. Patent 5,461 ,338, to Hirayama.
FIG. 1A shows a SRAM cell, 10, repeated throughout a typical memory array. Of interest are the positive power terminal pair, T3, and, T2, and negative power terminal pair, T1 , and, TO, of the cross-coupled latch with loads, 3, and, 2, and drivers, 1 , and, 0. A more than 40 year Industry practice is to allow only 1 coupling combination of the pair of latch positive power terminals to 1 positive supply like VDD shown and to allow only 1 coupling combination of the pair of latch negative power terminals to 1 negative supply line like GND also shown. These short circuit couplings of latch power terminal pairs occur within the memory cell as well as external within a memory array power grid.
The loads, 3, and, 2, and drivers, 1 , and, 0, employed can vary from field effect transistor, depletion mode transistor, thin film transistor, diode, Schottky barrier diode, FinFET, tri-gate, CNT carbon nanotube, resistor, programmable resistor like memristor, phase change memory, solid electrolyte, resistive RAM, floating gate, efuse, or equivalent or composites of 16_23" T° connect the volatile data node, Q1 , to bit line 1 , BL1 , and the complementary data node, Q0, to a possible bit line 0, BL0, pass gates, 4, and, 5, respectively, which can be positive or negative transistors or even diodes can be used.
Other references include U.S. Patent 4,096,584 to Owen et al. which discloses 6T SRAM with depletion load FETs, shorted VDD terminals, shorted GND terminals, for a SRAM memory array, figure 1 : T. Masuhara, "A High-Performance N-Channel MOS-LSI using Depletion-Type Load Elements", ISSCC 1971 , pp. 12-13, see figure; the Ootani, et al, article entitled "A 4-Mb CMOS SRAM with a PMOS Thin-Film-Transistor Load Cell", IEEE Journal of Solid-State Circuits, Vol. 25, No. 5, October 1990, see figure 1 ; the Walker, et al article entitled, "Four-Transistor Static CMOS Memory Cells", 1977 International Electron Devices Meeting, pp. 402-405, see figure 2; U.S. Patent 5,021 ,849 to Pfiester et al. disclosing 4 transistor NMOS SRAM with diode loads figure 1 , see diodes built on top of polysilicon gates figure 2; U.S. Patent 3,609,712, to Dennard disclosing 4 transistor 2 resistor load SRAM in figure 2; U.S. Patent 5,265,047 to Leung et al. disclosing 4 transistor, 2 resistor load SRAM with shorted VCCs and GNDs fig 1 , and 2 port 4 transistor 2 resistor load SRAM with 2 word lines and single ended sense amplifier fig 3; and the article by Richardson, et al entitled. "A Trench Transistor Cross-Point DRAM Cell", 1985 IEDM, pp.714-717.
Bit Line column precharge, 17, has pull up transistors, 15, and, 16, that are low voltage level, chip enabled ( /CE ) to positively charge up BL1 and BL0 before bit lines, BL1 , and, BL0, are differentially read. Word line, WL, is row activated by word line decoder, 14, where word line CMOS driver, 12, and, 11 , drive the word line and pass gate inputs, 4, and, 5, high and "on". Differential data, BL1 , and, BL0, are distinguished as a logic "1 " or "0" by sense amplifier, 22, which is turned on using, SE, sense enable^. Memory array power,
VDD, and, GND, are full active "on" or reduced for memory sleep by power switches, 18, and, 19, that are also back gate biased to help reduce power switch leakage in sleep mode.
FIG. 2A and 2B, a schematic and chip layout, of a small aspect ratio (SAR) 6 transistor CMOS SRAM cell typifies the latch memory cell that has dominated single and multi-core processor cache memory for the last decade. Continuing the industry practice of only 1 coupling combination ie. short circuit coupling the latch load devices, 33, and, 32, we see in FIG. 2A schematic and 2B cell layout that both latch loads have their power terminals, T3 and T2, shorted to the same supply, VDD. Similarly, the latch drivers, 31 , and, 30, have their latch power terminals, T1 and TO, with only 1 coupling combination ie. shorted to the same named supply, VSS. See reference 28 especially FIG. 2A to see that the PMOS loads, 33 & 32, their power terminals, T3 & T2, are electrically shorted together. Furthermore, the SAR SRAM layouts of next neighbor cells in the same memory column share the same VDD and GND source/drain diffusion pads in order to minimize memory array cell area. This can be seen in reference 29 and the scanning electron memory (SEM) scans of FIG.1 and FIG. 2 for both SAR SRAM cell layouts with a conventional SRAM cell layout and one with a straight diffusion SRAM cell layout. This industry trend continues today where both (A) short circuit coupling latch load power terminal pairs and latch driver power terminal pairs for SRAM memory cells plus (B) integrating or merging together source/drain power terminals of loads and drivers transistors in next neighbor memory cells within a memory array.
(A) The 3 dimensional transistor SRAM cells by IBM in 2010 is shown in FIG. 3. The repeated pattern of the SRAM cells, 50, 51 , 52, & 53, is shown having their positive power pins, T3, and, T2, with only 1 coupling combination ie. short circuit coupled together locally and globally to 1 VDD while their negative power pins, T1 , and, TO, have only 1 coupling combination ie. short circuit coupled locally and globally to one GND.
(B) The 3 dimensional SRAM cells manufactured in 2012 by Inte^rj is illustrated in FIG.
5B and 5C which shows scanning electron microscope (SEM) views of small aspect ratio (SAR) 3 dimensional (3D) Tri-Gate, static random access memory (SRAM) cells. The FIG. 5B SRAM cell has a drawn gain of BETA=1 for "single fin" driver transistors & the FIG. 5C cell has a drawn gain of BETA=2 based on "dual fin" driver transistors, with of course gain variable by other means like differences in "ion implantation" as well. In the Intel SRAM cell schematic, FIG. 5A., like other prior art industry practice, the "latch load power terminals" for devices, P3 and P2, are short circuited together into a single positive supply, VDD, or, VCS, for cell stability. Also, the "latch driver power terminals" for, NO and N1 , are also short circuited together like in prior art with, GND. Furthermore, in FIG. 5B and 5C the source/drain diffusion loads (shown) and their metal power terminal contacts between next neighbor SRAM cells are merged, shared, or integrated. Please see where the arrows in FIG. 5B and 5C with accompanying text are pointed at."
The small aspect ratio (SAR) layout will differ in at least 1 or 2 latch power terminal metal contacts and their associated source/drain diffusions "not being shared" or "physically separate" within a SRAM cell, as well as between next neighbor SRAM cells.
An industry typical static random access memory (SRAM) or latch memory cell stores 1 differential, bistable, volatile data bit. The invention latch cell comprises 2 differential latch loads both sharing 1 upper supply, ie. typically VDD, and 2 differential latch driver transistors both sharing 1 negative supply, ie. typically ground (GND). If one desired to integrate nonvolatile (nv) data storage within a latch cell, since the latch itself by nature is differential, the nv coupling to the latch should be differential i.e. 2 couplings, plus the number of differential nonvolatile (nv) storage elements should also be differential i.e. 2 nonvolatile elements.
Mathematically speaking a 1 st latch device is single ended, selective driven by a said 1 st bus, encodes or programs: B=[[LOG2(N)]], nonvolatile (nv) bit(s) per 1 latch device.
When said 1 st supply/programming bus has, N, potential lines to select from where, N, is an integer power of 2 like 2, 4, 8, 16, etc. then 1 b, 2b, 3b, and 4b nv data result.
An additional, 2nd latch device coupled to 1 single ended, selective electrical connection with a 2nd bus, encodes or programs: B= [[LOG2(M)]] + [[LOG2(N)]], nonvolatile bits per 2 single ended, selectively supplied latch devices.
Additionally the invention includes where B = 3 to 9 nonvolatile bits per SRAM cell where: B = [[LOG2(M)]] + [[LOG2(N)]] + [[LOG2(P)]] nonvolatile bits where M=2 to 8, N=2 to 8, P=2 to 8 or > bus potential lines. Additionally, the invention includes where B = 4 to 10 nonvolatile bits per SRAM cell where: B = [[ LOG2(M) ]] + [[ LOG2(N) ]] + [[
LOG2(P) ]] + [[ LOG2(Q) ]] nonvolatile bits where M=2 to 8, N=2 to 8, P=2 to 4, Q=2 to 4 or > bus potential lines.
First, for the single ended approach verses the alternative, there is 1 single ended electrical connection + 1 latch device stores 1 nonvolatile data bits else, 2 differential electrical connections + 2 latch devices store 1 nonvolatile data bit.
Alternatively, for the single ended approach verses the alternative, there are 4 single ended electrical connections + 4 latch devices stores 4 nonvolatile data bits minimum else 4 differential electrical connections + 4 latch devices stores 2 nonvolatile data bits minimum. Second, in both embodiments, read speed of single ended, selectively supplied, nonvolatile data is novelly trans-formed from relatively slow to fast by the latch cell itself to electrically transform slow single ended nonvolatile signals to differential, high speed, bistable, volatile latch cell outputs.
Third, in both embodiments, even when single ended electrical connections are mask program encoded, once electrically transformed into volatile differential data within a SRAM cell, the mask programmed data can now be updated, modified, and even corrected.
Fourth, dual supply drivers can, if completely separate said buses are employed, preset or clear entire blocks of sequentially ordered word lines and bit lines of latch memory cells rather than individually writing each word line one at a time.
Fifth, these SRAM or latch cells can be made nonvolatile rewritable by the addition of:(a) variable resistance memory elements within the series electrical connections between the bus potential lines and each latch power terminal being supplied, and
(b) a soft programmed variable resistance memory element, a soft programming line (SPL), to allow for connecting to these bus potential lines + ie. PCM memory element combinations for programming then for disconnecting from once programmed.
Sixth, repeating an important point, physically separate, latch power contacts do not dilute or diminish the nonvolatile data encoded and so stored in them by sharing with adjacent SRAM cells. So total potential line combination, nonvolatile data in ie. a nonvolatile SRAM array can be much greater than if shared power contacts had been used between neighboring cells.
Seventh, new manufacturing capabilities like double patterning lithography (DPL), sidewall image transfer (SIT), extended ultraviolet light lithography (EUV), ebeam lithography, etc. can be employed to achieve some of the poly to poly separations possibly desired.
Eighth, vertical channel transistor latch memory cell layouts are more conducive to introducing physically separate latch power contacts with little or no cell area growth. For example, new cell layouts are shown that leverage word line to latch load gate or word line to latch driver gate couplings that remove the need for more difficult polysilicon to polysilicon spacing by removing the need for physical spaces to be inserted between poly lines.
Other representative prior art includes U.S. Patent 7,038,925 to Ohbayashi discloses in figure 4A-D a SAR SRAM cell schematic and layout; Rajiiv Joshi, et al article entitled "Invited", 2010 23rd International Conference on VLSI Design, disclose in fig 7 a schematic of row-based back gate biasing scheme for double gate FinFET SRAM; Tsu-Jae King Liu, et al. article entitled "SRAM Cell Design Considerations for SOI Technology", 2009 IEEE SOI Conference, discloses in figure 6 table, SRAM cell layout design rules; Gordon E. Moore, "No Exponential is Forever...", Plenary Speech, ISSCC 2003; U.S. Patent 7,038,925 to Ohbayashi et. al. disclose SAR SRAM FIG. 4A schematic & FIG. 4B cell layout drawings; Ohbayashi, et al. article enttiled "A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits", 2006 Symposium on VLSI, see FIG. 1 SEM SAR SRAM cell layout & FIG. 2 SEM SAR straight diffusion cell layout with loads, drivers, & access transistors pointed out; Karl, et al. "A 4.6GHz 162Mb SRAM Design in 22nm Tri-Gate CMOS...", 2012 ISSCC, assigned to Intel, discloses in FIG. 13.1 .1 SEM of high density 1 fin & 2 fin SAR SRAM cells plus FIG. 13.1 .1 schematic; Clevenger, entitled "Phase Change Material Structures", 2007 IBM Patent app, see Fig. 1 , 1 st electrode 102, a tantalum nitride (TaN) heater layer 120, phase change material 110, 2nd electrode contact 130, and 2nd electrode 104; Bedeschi, et al. article entitled"...Phase- Change Memory", 2008 ISSCC, pp. 428-429, see FIG. 23.52.2; Wong, et al.article entitled "Phase Change Memory: a comprehensive & thorough review...", 2010 Proceedings of the IEEE, Vol. 98, No. 12, pp.2201 -2227, Fig. 2 & discussion p.2202; Wong, et al. "Progress of Phase Change Memory (PCM) & Resistive Switching Random Access Memory (RRAM), 2011 3rd International IEEE Memory Workshop;U.S. Patent Publication 2011/0032747 A1 , to Yoon discloses variable resistance memory devices; U.S. Patent 6,423,621 to Doan et al. , assigned to Micron Technology, discloses in Fig. 15, lower electrode or tip 114 which may be polysilicon, chalcogenide memory 120, optional conductive barrier 128, upper electrode 122 which may be titanium nitride, ΤΊΝ; Horiguchi, et al.in an article entitled
"...0.1 urn2 6T-SRAM Cells ... Double Gate Patterning...EUV Lithography...", 2010 Symposium VLSI, pp.23-24.
The invention is an advantage over the current technology in the provision of a static random access memory (SRAM) cell with at least N=1 latch pull up (PU) or pull down (PD) is single ended, selectively coupled to 1 of L potential lines wherein single or multi-bit nonvolatile data is selectively encoded within said SRAM cell wherein said encoding can be interpreted as B = [[ LOG2(said L) ]] nonvolatile data bit(s) or binary digit(s) in addition to said SRAM cell's own inherent 1 volatile bit of data stored.
A general objective of the invention is to provide a SRAM cell with its N=1 , 2, 3, and/or 4 said latch pull ups (PU) or pull downs (PD) each selectively coupled to at least 1 , 2, 3, and/or 4 sets of potential lines, L, M, P, and/or Q so that single to multi-bit nonvolatile data may be thereby single ended, selectively encoded within each said PU and/or PD wherein a nonvolatile storage of at least 1 to 10 data bits or binary digits per said SRAM cell is provided in addition to the SRAM's normal at least 1 volatile data bit.
Another objective of the invention is to provide a SRAM cell is provided within a bit lines (BL), word lines (WL) memory array of mainly said SRAM cells, its N=1 , 2, 3, and/or 4 said latch pull ups (PU) or pull downs (PD) with a separate & interlocked positive or negative supply contact(s) with next neighbor said SRAM cell(s), said SRAM cells existing on all its 4 sides to allow for individualized direct injection of nonvolatile computer instructions and/or data directly into its said PU(s) and/or PD(s) from the power structure generally seen as above where said separation can surprisingly or normally contradictory allow for much greater data storage density yet can still keep said SRAM cell area the same.
Yet another objective A SRAM cell is provided with at least N=1 pair of SRAM, latch differential pull ups (PU) or pull downs (PD) selectively coupled to 1 of L>= 4 potential lines wherein multi-bit nonvolatile data is selectively encoded for a pair of differential PUs or PDs.
An objective of the invention is to provide a SRAM cell with N=1 , 2, 3, and/or 4 latch pull up and/or pull down devices with single ended, selectively coupled, single bit or multi-bit nonvolatile data.
Another objective of the invention is to provide separate and interlocked positive and/or negative supply contacts with next neighbor SRAM cells within a memory array allowing for higher density nonvolatile data storage without the need to grow SRAM cell area.
Another object of the invention is to provide a SRAM with multi-bit nonvolatile data storage for at least a differential pair of SRAM latch PUs or PDs via selective coupling and encoding of nonvolatile data.
SUMMARY OF THE INVENTION
In the present invention, these purposes, as well as others are provided by a memory device for storing 1 to 10 bits of single ended, potential line combination, nonvolatile data including a bit lines (BL), word lines (WL) memory array essentially of complementary, field effect transistor (FET) latch SRAM cells. Wherein the latch transistor has positive or negative supply contact such that the SRAM cell has at least N = 1 unshared, separate and interlocked latch transistor positive or negative supply contact with any of the next neighbor SRAM cells.
The latch transistors are selected from the group consisting of fully cross-coupled complementary FETs; P and N channel fully cross-coupled FETs; 3 dimensional fully cross- coupled complementary FETs; and 3 dimensional positive metal oxide latch transistor (PMOS), a negative metal oxide latch transistor (NMOS) fully cross-coupled complementary FETs.
The complementary field effect transistor (FET) is selected from the group consisting of FinFET transistors and Tri-Gate transistors.
The memory device can have N=2 said latch power or ground contacts; N=3 said latch power or ground contacts; or N=4 said latch power or ground contacts.
In an alternate embodiment of the invention a semiconductor memory chip is provided made of at least, L=2, potential lines; a bit lines (BL), word lines (WL) memory array mainly of fully cross-coupled, complementary, field effect transistor (FET) latch, SRAM cells. Wherein the SRAM cells comprise a latch pull up (PU) or pull down (PD) single ended, selectively coupled to one of said lines; wherein said latch pull up or pull down is selectively encoded to store data, where, B = [[ LOG (said L=2) ]] =1 nonvolatile data bit or digit
2
stored for a said latch PU or PD; wherein said SRAM cell can store a combined 1 volatile + said encoded nonvolatile data of: B= [[ LOG ( said L=2 ) ]] + 1 = 2 data bits or digits per
2
SRAM cell.
When L=4 the latch pull up or pull down is selectively encoded to store data, where B =
[[ LOG (said L=4) ]] = 2 nonvolatile data bits or digits stored for a said latch PU or PD;
2
wherein said SRAM cell can store a combined 1 volatile plus said encoded nonvolatile data of: B= [[ LOG ( said L=4 ) ]] + 1 = 3 data bits or digits per SRAM cell. When L=8 the
2
latch pull up or pull down is selectively encoded to store data, where B = [[ LOG (said L=8)
2
]] = 3 nonvolatile data bits or digits stored for a said latch PU or PD; wherein said SRAM cell can store a combined 1 volatile plus said encoded nonvolatile data of: B= [[ LOG ( said L=8
2
) ]] + 1 = 4 data bits or digits per SRAM cell.
For each L potential lines there is a corresponding 1 to said L, said SRAM cells each selectively coupled to said 1 to said L potential lines, implementing each nonvolatile data and said selective encoding. In preferred embodiments the latch PU or PD device are N separate, interlocked contacts.
The semiconductor memory chip further may include at least, L, M, P, and Q sets of said potential lines, a bit lines (BL), word lines (WL) memory array mainly of fully cross-coupled, complementary, field effect transistor (FET) Latch, SRAM cells , where all the latch pull ups
(PU) & pull downs (PD) are each single ended, selectively coupled to 1 of said sets of said potential lines respectively. The latch pull ups and pull downs are each selectively encoded and combined store: B = [[ LOG ( said L ) ]] + [[ LOG ( said M ) ]] + [[ LOG ( said P ) ]] + [[
2 2 2 LOG ( said Q ) ]] or sB data bit(s) or digit(s) of nonvolatile data + 1 volatile bit of SRAM 2
data.
In another embodiment, the set of potential lines, there is a corresponding 1 to the L, M,
P, and Q said SRAM cells respectively each selectively coupled to said 1 to said L, M, P, and Q sets of potential lines, implementing each nonvolatile data said selective encoding.
The latch PU or PD device are N separate, interlocked said contacts.
The semiconductor memory chip may further include at least, said L=4, said M=4, said
P=8, and said Q=8 sets of said potential lines, said bit lines (BL), word lines (WL) memory array mainly of fully cross-coupled, complementary, field effect transistor (FET) Latch, SRAM cells. Where all said latch pull ups (PU) and pull downs (PD) are each single ended, selectively coupled to 1 of said sets of said potential lines respectively; wherein said latch pull ups and pull downs are each selectively encoded and combined store:B = [[ LOG (
2 said L=4 ) ]] + [[ LOG ( said M=4 ) ]] + [[ LOG ( said P=8 ) ]] + [[ LOG ( said Q=8 ) ]] or
2 2 2
said B = 10 data bit(s) or digit(s) of nonvolatile data + 1 volatile bit of normal SRAM data.
The invention also provides a memory device including at least, L=4, potential lines; a bit lines (BL), word lines (WL) memory array essentially of fully cross-coupled, complementary, field effect transistor (FET) Latch, SRAM cells. Wherein the SRAM cells comprise a differential said pair of pull ups (PU) or pull downs (PD) are selectively coupled to 2 of said L potential lines; wherein said pair of PUs or PDs are selectively encoded and store: B = [[ LOG (said L=2) ]] + [[ LOG (said L=2) ]] =2 nonvolatile data bits or digits
2 2
stored for a said differential pair of said latch PUs or PDs.
Where at least said, L = 6 potential lines or M+N = 4+2, sets of potential lines and wherein a said differential said pair of PUs or PDs are selectively coupledjo said M and N sets of potential lines respectively; wherein said pair of PUs or PDs are selectively encoded and store: B = [[ LOG (said M=4) ]] + [[ LOG (said N=2) ]] = 3 nonvolatile data bits or digits
2 2
stored for a said differential pair of said latch PUs or PDs.
Where at least said, L = 8 potential lines or M+N = 4+4, sets of potential lines;wherein a said differential said pair of PUs or PDs are selectively coupled to said M and N sets of potential lines respectively; wherein said pair of PUs or PDs are selectively encoded and store: B =[[ LOG (said M=4) ]] + [[ LOG (said N=4) ]] = 4 nonvolatile data bits or digits 2 2
stored for a said differential pair of said latch PUs or PDs.
Where at least said, L = 16 potential lines or M+N = 8+8, sets of potential lines; wherein a said differential said pair of PUs or PDs are selectively coupled to said M & N sets of potential lines respectively; wherein said pair of PUs or PDs are selectively encoded and store: B = [[ LOG (said M=8) ]] + [[ LOG (said N=8) ]] = 6 nonvolatile data bits or digits
2 2
stored for a said differential pair of said latch PUs or PDs.
For each said set of potential lines there is a corresponding 1 to said M and N said
SRAM cells respectively each selectively coupled to said 1 to said M and N sets of potential lines, implementing each nonvolatile data said selective encoding. In a preferred embodiment the differential pair of latch PUs or PD device(s) are said N separate, interlocked said contacts.
The invention also provides an array of static random access memory (SRAM) cells for storing 1 to 10 bits of single ended, potential line combination, nonvolatile data comprising essentially of complementary, field effect transistor (FET) latch SRAM cells; wherein said latch transistor has positive or negative supply contact such that said SRAM cell has at least N = 1 unshared, separate and interlocked said latch transistor positive or negative supply contact with any of said next neighbor SRAM cells.
For a latch cell like a SRAM cell has at least 1 or 2 latch, pull-ups or latch pull-downs, that may be encoded with and so store 1 to 6 bits of single ended, verses differential, said latch device(s) to M>=2 and N >=1 potential lines, combination, nonvolatile data. As dependent invention embodiments, this is further limited to FinFET, Tri-Gate, or equivalent SRAM cells, within a bit line, word line, matrix of said SRAM cells, that unsually has 1 or 2 separate said latch device connections verses shared between neighboring cells, for fully implementing each of said M>=2 and N >=1 potential lines, combinations, ie. said nonvolatile data is not shared and hence not diluted by sharing nonvolatile data between adjacent cells. For a basic understanding see the possible abstract below, but better see invention descriptions section, drawings, detailed description, and especially yet to be drafted patent claims in the yet to be filed non-provisional patent application follow-on.
A semiconductor chip including (1 ) a 1 st and 2nd sets of, M and N, potential lines, respectively, which might share up to 1 said potential line at most; and where at least M=2 and N=1 to begin at; (2) a set of M and N latch cells, each latch cell comprising 2 cross- coupled inverters made up of a 1 st and 2nd latch pull-ups; and a 1 st and 2nd latch pull- downs; complementary VOLATILE data; where said pull-ups' source or drain terminals are physically separate verses connected; where said 1 st pull-ups are supplied by different 1 s of said 1 st set of potential lines; where said 2nd pull-ups are supplied by different 1 s of said 2nd set of potential lines if said N>1 ; where said 1 st & 2nd pull-ups are supplied or programmed independently of each other; hence said 1 st & 2nd pull-ups are "single ended" rather than "differential ended" coupled; wherein said M & N SRAM cells with said 1 st & 2nd pull-ups are encoded with & so store B=LOG2(M) + LOG2(N) bits of "single ended supplied", said latch devices to 1 of saind M and possibly said N combination, nonvolatile (nv) data in addtion to and simultaneously with the standard said SRAM volatile data.
On the other hand, the latch pull-downs rather than the latch pull-ups above may instead be encoded with "single ended supplied" nonvolatile data.
This above nonvolatile data storage in said M & N SRAM cells can be constrained even further to wide SRAM adjacent to other 1 s sharing bit line contacts that also implement the above described "single ended supplied" nonvolatile data. These wide SRAM cells would be approximately 2 transistors in length by at least 4 transistors in width. But even more unusual from wide SRAM cell to adjacent wide SRAM cells these cells would have at least 1 to 2 latch power contacts physically separate from adjacent SRAM cell(s) even though sharing bit line contacts between neighbor cells. These possible dependent invention embodiments are better implemented to reduce both leakage power and cell area using FinFET, Tri-Gate, or equivalent SRAM cells.
In the context of a bit line, word line, matrix of SRAM cells, a said matrix SRAM cell physically shares a 1 st & 2nd bit line contact with a 1 st & 2nd neighbor SRAM cells respectively. Yet unusually this matrix SRAM cell has 1 or 2 latch device power contacts physically separate from any other latch power contacts. This physical separation is made possible by these 1 or 2 latch devices being made laterally offset rather than substantially mounted upon or above any other SRAM cell transistor.
In an alternate embodiment this matrix SRAM cell and its 1 st and 2nd neighbor cells have 4 transistor diffus-on tracks or the like substantially in a 1 st direction & 2 word line polysilicon tracks or the like substantially in a 2nd direction. These can employ planar or vertical channel transistors, etc. In a second embodiment 6 transistor diffusion tracks or the like are employed. These 6 diffusion tracks, for modern cell power needs, employ vertical channel transistors that may be FinFET, Tri-gate, or the like or equivalent in nature.
An extra embodiment involves polysilicon to polysilicon or the like physical separation which can be made as 1 option using double patterning lithography (DPL) or as shown in patent drawings, word line polysilicon lines can, instead, run directly into gates of driver transistors without poly to poly separation and, in fact, that can actually help reduce SRAM cell leakage during word line "off' times, shutting off those driver gates & their current leakage when "off'.
Another SRAM invention is also in the context of a bit line, word line matrix of SRAM cells. Here the focus is on SRAM latch power contacts, at least 1 or 2 of them, either physically shared or physically separate from other latch power contacts, that are single ended, selectively supplied by a first bus of N=2 or more potential lines or to a second bus of M=2 or more potential lines. These bus lines can be shared with other matrix SRAM cells to reduce or minimize the # of lines needed as well as to then take advantage of the freed up cell area to make these potential lines even wider for lower resistance and faster response. These programmed couplings encode these SRAM cells with either: For 1 bus: B= [[LOG2(M=2 potential lines or more)]] = 1 b or more of SRAM latch power contact, single ended supplied, potential line combination, nonvolatile data. For 2 buses: [[LOG2(M=2 or more)]] + [[LOG2(N=2 or more)]] = 2b or more of SRAM latch power contact, single ended supplied, potential line combination, nonvolatile data. (Note the math function [[ ]] is the greatest integer function)
As a follow-up dependent embodiment to this SRAM invention with single ended nonvolatile data storage, this can be limited to and combined with the first SRAM invention above where the cell layout has 1 or 2 physically separate latch power contacts, even with shared bit lines or share bit line contacts between next store neighbor SRAM cells. For each SRAM cell the number of transistor diffusion tracks or the like can be limited to 4 or 6 aligned substantially in a 1 st direction with 2 word line, polysilicon tracks or the like aligned substantially in a 2nd direction.
Of importance, using physically separate latch power contacts can achieve double the nonvolatile data storage verses using shared latch power contacts. Further, single ended nonvolatile data storage can be more than using differential coupling for the same # of potential lines used. Furthermore, single ended nonvolatile data storage can be used in series of physically consecutive next neighbor SRAM cells using shared latch power contacts, but due to short circuit conflicts, differential coupling can not be used for every consecutive next neighbor SRAM cells where shared latch power contacts are employed.
Hence, since differential coupling to store nonvolatile data in consecutive cells with shared latch power contacts is prevented due to short circuit conflict another independent invention embodiment is as follows. At least 1 differential bus of potential lines supports a bit line, word line matrix of SRAM cells, to store differential nonvolatile data. A consecutive series of next store neighbor to next store neighbor said matrix SRAM cells, each with all of its latch power contacts shared with neighboring SRAM cells is made to unusually store differential nonvolatile data. The key is that every other cell, not every cell, of a series of next store neighbor SRAM cells has a pair of latch driver power contacts or pair of latch load power contacts coupled to some differential bus, wherein short circuit conflict between differential buses is, hence, prevented.
In an alternate embodiment, for a latch cell like a SRAM cell has, at least 3 or 4 latch, pull-ups and latch pull-downs, are provided that may be encoded with and so store 3 to 10 bits of single ended, verses differential, said latch device(s) to M>=2, N>=2, and Q>=2 potential lines, combination, nonvolatile data. As dependent invention embodiments, this is further limited to FinFET, Tri-Gate, or equivalent SRAM cells, within a bit line, word line, matrix of said SRAM cells, that unsually has 3 or 4 separate said latch device connections verses shared between neighboring cells, for fully implementing each of said M, N, and Q >= 2 potential lines, combinations, i.e.. said nonvolatile data is not shared and hence not diluted by sharing nonvolatile data between adjacent cells.
The SRAM cell is preferably made up of at least a (1 )1 st and 2nd and 3rd sets of, M and N and Q, potential lines, respectively, which might share up to 1 said potential line at most; and where at least M=2 and N=1 and Q=2 to begin at; (2) a set of M and N and Q latch cells, each latch cell comprising: 2 cross-coupled inverters made up of a 1 st and 2nd latch pull-ups; and a 1 st and 2nd latch pull-downs; complementary VOLATILE data; where said pull-ups' source or drain terminals are physically separate verses connected; where said 1 st pull-ups are supplied by different 1 s of the 1 st set of potential lines; where said 2nd pull-ups are supplied by different 1 s of the 2nd set of potential lines; where said 1 st pull-downs are supplied by different 1 s of the 3rd set of potential lines; where said 1 st and 2nd pull-ups and 1 pull-downs are supplied independently of each other; hence said 1 st and 2nd pull-ups and 1 st pull-downs are "single ended" rather than "differential ended" coupled; wherein said M & N and Q SRAM cells containing said 1 st and 2nd pull-ups & said 1 st pull-downs are, therefore, encoded with & so store: B = LOG2(M) + LOG2(N) + LOG2(P) bits of "Single Ended Supplied", latch device to 1 of M and N and P potential lines, combination, Nonvolatile (nv) Data in addition to and simultaneously with the standard said SRAM VOLATILE data.
This is also expanded to latch cells like said SRAM cells with not just 3 but to those with all 4 of its latch devices, pull-ups & pull-downs encoded & so storing nonvolatile data like: B = LOG2(M) + LOG2(N) + LOG2(P) + LOG2(Q) bits of "single ended supplied" , latch device to 1 of M and N and P and Q potential lines, combination, Nonvolatile (nv) Data utilizing an additional 4th set of, Q, potential lines, and where at least Q=2 to begin at. On the other hand, another possible embodiment are more latch pull-downs rather than latch pull-ups (as described above) may instead be encoded with said "single ended supplied" nonvolatile data.
This above nonvolatile data storage in said M and N and P and optionally Q SRAM cells can be constrained even further to wide SRAM cells adjacent to other 1 s sharing bit line contacts that also implement the above described "single ended supplied" nonvolatile data. These wide SRAM cells would be approximately 2 transistors in length by at least 4 transistors in width. But even more unusual from wide SRAM cell to adjacent wide SRAM cells these cells would have at least 3 to 4 latch power contacts physically separate from adjacent wide SRAM cell(s) sharing bit line contacts with neighbor cells. These possible dependent invention embodiments are better implemented to reduce both leakage power and cell area using FinFET, Tri-Gate, or equivalent SRAM cells.
This above nonvolatile data storage in like SRAM cells can be constrained even further to ultra wide SRAM cells adjacent to other 1 s sharing bit line contacts. These ultra wide SRAM cells would be approximately 1 .5 transistor in length by at least 6 transistors in width. But even more unusual from ultra wide SRAM cell to adjacent ultra wide SRAM cell these cells would have at least 3 to 4 latch power contacts physically separate from adjacent ultra wide SRAM cell(s) sharing bit line contacts between neighbor cells. These possible dependent invention embodiments are better implemented to reduce both leakage power and cell area using FinFET, Tri-Gate, or equivalent SRAM cells. In the context of a bit lines, word lines, matrix of SRAM cells, a said matrix SRAM cell physically shares a 1 st and 2nd bit line contact with a 1 st and 2nd neighbor SRAM cells respectively. Yet unusually this matrix SRAM cell has 3 or 4 latch device power contacts physically separate from any other latch power contacts. This physical separation is made possible by these 3 or 4 latch devices being made laterally offset rather than substantially mounted upon or above any other SRAM cell transistor.
In one embodiment this matrix SRAM cell and its 1 st and 2nd neighbor cells have 6 or 8 transistor diffusion tracks or the like substantially in a 1 st direction and 2 word line polysilicon tracks or the like substantially in a 2nd direction. These 6 or 8 diffusion tracks, for modern cell low power needs, employ vertical channel transistors that may be FinFET, Tri-gate, or the like or equivalent. Furthermore, the 6 diffusion track cells & their neighbors can be made BETA=2 for one and the other BETA=1 to fit these cells together without latch power contacts being constrained into being shared between SRAM cells for the purpose of minimizing cell area.
An extra embodiment involves polysilicon to polysilicon or the like physical separation which can be made as 1 option using double patterning lithography (DPL) or as shown in patent drawings, word line polysilicon lines can, instead, run directly into gates of driver transistors without poly to poly separation and, in fact, that can actually help reduce SRAM cell leakage during word line "off' times, shutting off those driver gates & their current leakage when "off'.
Another SRAM invention is also in the context of a bit line, word line matrix of SRAM cells. Here the focus is on SRAM latch power contacts, 3 or 4 of them physically separate from other latch power contacts, that are single ended, selectively supplied by a 1 st , 2nd, 3rd, and optionally 4th bus of M=2 , N=2, P=2, and optionally Q=2 or more potential lines respectively. These bus lines can be shared with other matrix SRAM to reduce # of lines needed as well as to take advantage of the freed up cell area to make these potential lines wider for lower resistance & faster response. These programmed couplings encode these SRAM cells with either: (3 buses) B = [[LOG2(M)]] + [[LOG2(N)]] + [[LOG2(P)]] = 3b or more of SRAM latch power contact, single ended supplied, potential line combination, nonvolatile data, (4 buses) B = [[ LOG2(M) ]] + [[ LOG2(N) ]] + [[ LOG2(P) ]] + [[ LOG2(Q) ]] = 2b or more of SRAM latch power contact, single ended supplied, potential line combination, nonvolatile data, the math function [[ ]] is the greatest integer function. As a follow-up dependent embodiment to this SRAM invention with single ended nonvolatile data storage, this can be limited to and combined with the first SRAM invention above where the cell layout has 3 or 4 physically separate latch power contacts, even with shared bit lines or share bit line contacts between next store neighbor SRAM cells. For each SRAM cell the number of transistor diffusion tracks or the like can be limited to 6 or 8 aligned substantially in a 1 st direction with 2 word line, polysilicon tracks or the like aligned substantially in a 2nd direction.
Of importance, using physically separate latch power contacts can achieve double the nonvolatile data storage verses using shared latch power contacts. Further, single ended nonvolatile data storage can be more than using differential coupling for the same # of potential lines used. Furthermore, single ended nonvolatile data storage can be used in series of physically consecutive next neighbor SRAM cells using shared latch power contacts, but due to short circuit conflicts, differential coupling cannot be used for every consecutive next neighbor SRAM cells where shared latch power contacts are employed.
Other objects, features and advantages of the present invention will be apparent when the detailed description of the preferred embodiments of the invention are considered with reference to the drawings, which should be construed in an illustrative and not limiting sense.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A (Prior Art) illustrates a 1972 prior art, CMOS SRAM, static random access memory, array whose cells have a pair of positive and negative supply terminals, each pair, shorted electrically within cells & within memory arrays, the shorting, representing a more than 40 year industry practice; FIG. 1 B (Prior Art) is a SRAM differential sense amplifier; FIG. 1 C (Prior Art) are lower supply sleep or full on power switches.
FIG. 2A and B (Prior Art) shows a 2001 SRAM cell schematic and layout repeating the 40 year industry practice of electrically shorting SRAM cell positive supply terminals together and SRAM negative supply terminals together plus introducing a decade of Small Aspect Ratio (SAR) SRAM cell layouts where SRAM cell transistor diffusions all face the same direction for better manufacturing and least area ie. lithographically symmetric.
FIG. 3 (Prior Art) shows a 2010, 3 dimensional transistor SRAM array schematic again continuing the 40 year industry practice of shorting SRAM cell VDD supplies together and GND supplies together within cells and within arrays. FIG. 4 (Prior Art) shows a nonvolatile programming table telling the # of supply/programming bus potential lines, "m", and "n" needed to program a latch memory cell with a specific # of binary digits. FIG. 4 also shows which supply/programming bus potential lines should be "selectively supplied" to by the set reset memory cell to store a specific nonvolatile binary value are listed.
FIG. 5A (Prior Art) is a schematic of a 2012, Intel 3D, 6 transistor SRAM cell, which following industry practice, shorts the latch load power terminals to 1 positive supply and shorts the latch driver power terminals to 1 negative supply. FIG. 5B (Prior Art) is a 2012 high density cell (HDC) layout of an Intel 3D, "single fin" , 6 transistor SRAM cell, which following industry practice, merges, integrates, and so shorts together its latch load power terminal source/drain diffusions with the next neighbor SRAM cell's latch load power terminal source/drain diffusions. FIG. 5C ("Prior Art") is a 2012 high density cell (HDC) layout of an Intel 3D, "dual fin" 6 transistor SRAM cell, which following industry practice, merges, integrates, & so shorts together its latch load power terminal source/drain diffusions with the next neighbor SRAM cell's latch load power terminal source/drain diffusions.
FIG. 6 is an example schematic of, 3 or more, 3D transistor, interlocked SRAM cells, each selectively supplying a "single latch power terminal" to 1 potential line of a supply- programming bus, V, of 2, 4, 8, 16, or more potential lines, thereby, encoding or storing 1 , 2, 3, 4, or more nonvolatile bits of data within said cells.
FIG. 7 is an example schematic of, 3 or more, 3D transistor, interlocked SRAM cells, storing 2 nonvolatile bits of data, "per pair of latch power terminals".
FIG. 8 is an example schematic of, 3 or more, 3D transistor, interlocked SRAM cells, storing 3 nonvolatile bits of data, "per pair of latch power terminals".
FIG. 9 is example schematic embodiments of, 3 or more, 3D transistor, interlocked SRAM cells, storing 4, 5, or 6 bits of nonvolatile data, per pair of latch power terminals based on programmed or selective supplying.
FIG. 10 is a 2 example truth table sequences, 55A and 55B, to read out 2 stored nonvolatile data digits separately when stored in a single latch power terminal; 2 example truth table sequences, 56A and 56B, to read out 3 stored nonvolatile data digits separately when stored in a single latch power terminal. FIG.1 1 is a 2 example truth table sequences, 12A and 12B, to read out 4 stored nonvolatile data digits separately when stored in a single latch power terminal.
FIG. 12 is a 2 example truth table sequences, T1 -8 and T9-12, to read out 2 stored nonvolatile data digits separately when stored in a pair of latch power terminals.
FIG. 13 is a 2 example truth table sequences, 13A and 13B, to read out 3 stored nonvolatile data digits separately when stored in a pair of latch power terminals.
FIG. 14 is a 2 example truth table sequences, 14A and 14B, to read out 4 stored nonvolatile data digits separately when stored in a pair of latch power terminals.
FIG. 15 is a 2 example truth table sequences, 15A and 15B, to read out 5 stored nonvolatile data digits separately when stored in a pair of latch power terminals.
FIG. 16 is a 2 example truth table sequences, 16A and 16B, to read out 6 stored nonvolatile data digits separately when stored in a pair of latch power terminals.
FIG. 17 explains, for one embodiment, a generalized flowchart method of how to read out nonvolatile data digits stored in a multi-bit nonvolatile set reset memory.
FIG. 18A and B shows 2 sample timing diagrams for reading out nonvolatile, pre-stored data, 1 digit at a time, within latch memory cell, 61 , of FIG. 7, having 2 encoded, nv data bits and n=m=1 potential line structures per V and P buses.
FIG. 19 shows a series of exemplary invention chip layout embodiments of 1 of the best modes, a double pattern lithography (DPL), interlocked, 1 to 6 nonvolatile bit, multi-fin, 3D, 6 transistor, SRAM memory cells. This layout example shows vertical channel transistor diffusions, silicon epitaxy, and double patterned poly-silicon and source/drain contacts. Note that ultra thin body (UTB) planar transistors are an alternative approach.
FIG. 20 illustrates one embodiment of the contact, metal 1 , and via 1 layers of the 2 interlocked cells begun in Fig. 19.
FIG. 21 illustrates one embodiment of the metal 2 and via 2 layers of the 2 interlocked cells begun in Fig. 19.
FIG. 22 illustrates one embodiment of the metal 3 and via 3 layers of the 2 interlocked cells begun in Fig. 19.
FIG. 23 illustrates one embodiment of the metal 4 and via 4 layers of the 2 interlocked cells begun in Fig. 19.
FIG. 24 illustrates 1 embodiment of metal 5, via 5, and above example mask programmed connections for controlling supply/nonvolatile programming buses like VDD1 and VDDO to selectively supply not only SRAM latch power but also nonvolatile encoded data to interlocked SRAM cells as in FIG. 19 in order to store within these cells 1 to 6 bit nonvolatile numbers.
FIG. 25 is an example embodiment of a series of interlocked latch memory cells, each with 1 same latch power terminal, selectively supplied by a different V bus potential line to store different 1 to 4 bit nonvolatile numbers per latch memory cell or more.
FIG. 26 an example embodiment of a series of 4=n+m=n*m interlocked set reset memory cells, each with 2 latch power terminals, selectively supplied by different, V, &, P, bus supply/programming lines, or potential lines for storing all combinations of 2b nonvolatile numbers per latch memory cell.
FIG.27 an example of a series of 6 = n+m interlocked latch memory cells, each with 2 latch power terminals, selectively supplied by different, V, and, P, bus supply/ programming lines of n=4 and m=2 potential lines for storing different 3b nonvolatile numbers per latch memory cell.
FIG.28 an example of a series of 8 = nxm interlocked latch memory cells, each with 2 latch power terminals, selectively supplyed by different, V, &, P, bus supply programming lines of n=4 and m=2 potential lines for storing all combinations of 3b nonvolatile numbers per latch memory cell.
FIG. 29 an example of a series of 8 = n+m interlocked latch memory cells, each with 2 latch power terminals, selectively supplied by different, V, and, P, bus supply programming lines of n=4 and m=4 potential lines for storing different 4b nonvolatile numbers per latch memory cell.
FIG. 30 and 31 are an example embodiment of a series of 16 = nxm interlocked set reset memory cells, each with 2 latch power terminals, selectively supplied by different, V, and, P, bus supply programming lines of n=4 and m=4 potential lines for storing all combinations of 4b nonvolatile numbers per latch memory cell.
FIG. 32 is an example embodiment of a series of n+m and nxm interlocked set reset memory cells, each cell with 2 latch power terminals, selectively supplied by different, V, and P, bus supply programming lines, (n=8 and m=4) or (n=8 & m=8), potential lines for storing different 5 or 6 bit nv numbers per latch memory cell. FIG. 33 shows an alternative to FIG. 19 with a 1 to 6 nonvolatile bit, SRAM memory cell or, bistable memory cell implementation, instead, using the word line signal, WL, coupled to a latch 3D FinFET transistor gate.
FIG. 34 shows an alternative to FIG. 19 with a 1 to 6 nonvolatile bit, SRAM memory cell or, bistable memory cell implementation, instead, using planar transistors, rather than 3 dimensional or vertical channel transistors.
FIG. 35 shows in detail what happens to the FIG. 33 3D FinFET SRAM with word line coupled latch load transistors that are modulated by a word line turning "on" and "off'.
FIG. 36 shows much of next store neighbor memory cells 70s and 71 s , their Metal 1 , Vial , and Metal 2 mask layers, from FIG. 20 and 21 , first with an additional cell 70s added below them. Next, these 3 cells are copied & basically mirrored about a Y axis parallel to bit line 0, BLO, to create additional cells, 70s, 71 s, and again cell 70s. The result is a matrix of 3 memory cells tall (ie. 3 word lines tall) by 2 cells wide.
FIG. 37 shows much of the Via3, Metal 3, and Via4 layers of cells 70s and 71 s from FIG. 35 in this matrix of 3 memory cells tall by 2 cells wide. Essentially, there are shown 3 word lines of memory cells tall by 2 complementary bit line pairs of memory cells wide.
The FIG. directly below shows how to build a Soft Programming Line (SPL) structure for program connecting a V[*] potential line bus to a SRAM latch power terminal using Phase Change Memory (PCM) elements. The result is that the SRAM is encoded with 1 b, 2b, or > rewriteable, nvonvolatile, data bits.
Soft Programming Line, SPL, for Writing Rewriteable V Bus & P Bus
Phase Change Memory (PCM) Connections
A. F ro nt Vi ew: B. S id e Vi e w:
Figure imgf000023_0002
d
Figure imgf000023_0001
) FIG. 38 a prior art known two next neighbor, 6T Dual Fin FinFET SRAM cells, and their layout with shared positive and negative supply contacts an diffusions shared.
FIG. 39 and FIG. 40 illustrate prior art shared latch power contacts for 6T SRAM cells.
FIG. 41 to FIG. 48 shows step by step how to create one of the invention embodiments: next neighbor SRAM cells where 1 pair of latch pull up (PU) transistors or load devices have been mirrored or flipped so that the resulting next neighbor SRAM cells can now have "separate and interlocked" supply contacts allowing for independent single ended, selective coupling for storing independent nonvolatile encoded data in each individual latch pull up (PU) .
FIG. 49 shows a nonvolatile programming table telling the # of supply/programming bus potential lines, "J", "K", "M", and optionally "N", to program 3 or 4 of each latch memory cell's latch loads & latch drivers with a specific # of binary digits. FIG. 49 also shows which supply/programming bus potential lines should be "selectively coupled" to by the latch cell to store a specific nonvolatile binary #.
Schematic of 3 to 10 Bit, Nonvolatile, 3 Dimensional Transistor, SRAM Cells
FIG.50 is a schematic of a series of 3 or more, preferred mode, 3D SRAM cells, with source/drain diffusion power terminals, fully interlocked or physically offset yet both sharing the same cell border that depending on the # of potential lines used ie. j, k, m, and n, can each store a, B, # of bits of nonvolatile data where, B, is 1 value selected from the group consisting of 3b to 10b or more.
EXAMPLES OF 3. 4 10 bit Nonvolatile latch memory cells
FIG. 51 is a preferred mode, bit line contact sharing, fully interlocked, series of 3D
SRAM cells storing "3 nonvolatile bits" via 3 latch power terminals selectively driven by potential lines in 3 supply/programming buses V, P, and Gnd.
FIG. 52 is a preferred mode, bit line contact sharing, fully interlocked, series of 3D
SRAM cells storing "4 nonvolatile bits" via 4 latch power terminals selectively driven by potential lines in 4 supply/programming buses V, P, Gnd, and L.
FIG. 53 is a preferred mode, bit line contact sharing, fully interlocked, series of 3D SRAM cells storing "5 nonvolatile bits" via 3 latch power terminals selectively driven by potential lines in 3 supply/programming buses V, P, Gnd, and L. FIG. 54 is preferred mode, bit line contact sharing, fully interlocked, series of 3D SRAM cells storing "6 nonvolatile bits" via 4 latch power terminals selectively driven by potential lines in 4 supply/programming buses V, P, Gnd, and L.
FIG. 55 is a preferred mode, bit line contact sharing, fully interlocked, series of 3D SRAM cells storing "7 nonvolatile bits" via 4 latch power terminals selectively driven by potential lines in 4 supply/programming buses V, P, Gnd, and L.
FIG. 56 is a preferred mode, bit line contact sharing, fully interlocked, series of 3D SRAM cells storing "8 nonvolatile bits" via 4 latch power terminals selectively driven by potential lines in 4 supply/programming buses V, P, Gnd, and L.
FIG. 57 is a preferred mode, bit line contact sharing, fully interlocked, series of 3D SRAM cells storing "9 nonvolatile bits" via 4 latch power terminals selectively driven by potential lines in 4 supply/programming buses V, P, Gnd, and L.
FIG. 58 are preferred mode, bit line contact sharing, fully interlocked, series of 3D SRAM cells storing "10 nonvolatile bits" via 4 latch power terminals selectively driven by potential lines in 4 supply/programming buses V, P, Gnd, and L.
Flow Chart For Reading Nonvolatile Data
FIG. 59 is one possible embodiment flowchart, for reading out nonvolatile data digits, 1 bit at a time, stored within a latch load or latch driver, single ended, selectively driven by a bus of J, K, M, or N potential lines.
Read Timing Diagrams For 3 to 10 Bit Nonvolatile Set Reset Memories
FIG. 60 is a timing diagram chart using FIG. 59's flowchart to read out the 3 bits of nonvolatile data stored within the FIG. 51 cells 1 10 and 1 1 1 one bit at a time.
FIG. 61 is a timing diagram chart using FIG. 59's flowchart to read out the 4 bits of nonvolatile data stored within the FIG. 52 cells 120 and 121 one bit at a time.
FIG. 62 and 63 is a timing diagram chart using FIG. 59's flowchart to read out the 5 bits of nonvolatile data stored within the FIG. 53 cells 130 and 131 one bit at a time.
FIG. 64 and 65 is a timing diagram chart using FIG. 59's flowchart to read out the 6 bits of nonvolatile data stored within the FIG. 54 cells 140 and 141 one bit at a time.
FIG. 66 and 67 is a timing diagram chart using FIG. 59's flowchart to read out the 7 bits of nonvolatile data stored within the FIG. 55 cells 150 and 151 one bit at a time.
FIG. 68 and 69 is a timing diagram chart using FIG. 59's flowchart to read out the 8 bits of nonvolatile data stored within the FIG. 56 cells 160 and 161 one bit at a time. FIG. 70 and 71 is a timing diagram chart using FIG. 59's flowchart to read out the 9 bits of nonvolatile data stored within the FIG. 57 cells 170 and 171 one bit at a time.
FIG. 72 and 73 are timing diagram charts using FIG. 59's flowchart to read out the 10 bits of nonvolatile data stored within the FIG. 58 cells 180 and 181 one bit at a time.
Cell Layout Layers To Manufacture Preferred, 3 to 10 Bit,
Nonvolatile, 3D, Small Aspect Ratio (SAR), SRAM Memory Cells
FIG. 74 is one embodiment of 2 fully interlocked latch memory cell layouts with shared bit line contacts, where all 4 latch power terminals can be independently programmed to store like up to 10 nonvolatile data bits or more. Cell 190s, has dual fin pull downs, N1 a & b and NOa & b for Beta = 2 read out of data, while the other interlocked power terminal, cell
191 s, has only 1 fin pull downs, for data read out. Substrate, N and P diffusion, polysilicon, and contact layers are shown. Double Patterning Lithography (DPL) or Extended Ultra
Violet (EUV) lithography are recommended. Each photo mask exposure like for contacts are depicted by one set of semiconductor contacts drawn with thick bold lines while another set of semiconductor contacts are drawn with thin lines to suggest 1 embodiment of 2 different double patterning masks to create cell contacts.
FIG. 75 is one embodiment of the contact and metal 1 layers for cells 190s and 191 s.
FIG. 76 is one embodiment of the vial and metal 2 layers for cells 190s and 191 s.
FIG. 77 is one embodiment of the via2 and metal 3 layers for cells 190s and 191 s.
FIG. 78 is one embodiment of the via3 and metal 4 layers for cells 190s and 191 s.
FIG. 79 are embodiments of via and metal layers for cells 190s and 191 s that can be used for selective driving by supply/programming buses, Gnd, and, L, in "3 bit or greater" nonvolatile latch memory cell implementations.
FIG. 80 are embodiments of via and metal layers for cells 190s and191 s that can be used for selective drivin by supply/programming buses, V, and, P, in "3 bit or greater" nonvolatile latch memory cell implementations.
FIG. 81 is a very wide, small aspect ratio (SAR) SRAM embodiment of 2 fully interlocked latch memory cells. In order to share bit line contacts, long pass gate diffusions are implemented. Both Cell 200s and 201 s have dual fin pull downs for Beta = 2 read out with N diffusion pass gates for data read out. Double patterning lithography (DPL) or extended ultra violet (EUV) lithography are recommended if 0 cell area growth is desired. For example, bold wide lined square contact symbols contrasted with narrow lined square contact symbols can be used to pattern 1 set of contacts in a 1 photo mask exposure pass and a 2nd set of contacts in a 2nd photo mask exposure pass.
FIG. 82 is the same layout as FIG. 81 except separate, rather than shared bit line contacts, are used.
FIG. 81 and 82 are wider than, and shorter in height than, SAR-like SRAM embodiments of SRAM cells whose 4 latch power terminals are all physically separate, independently accessible for nv programming like up to 10 bits or more. Wonderfully, these cells exhibit dual fin pull-downs for a BETA=2 Read Margin, and for the bottom cell, 201 s and 206s, with the word line, WL, controlling not only the pass gates but also 2 latch transistor gates, a BETA=1 .5 WriteMargin is obtained. Because the cell is even shorter than the normal SAR SRAM layout, even with the greater cell width, zero cell area growth is possible even with the integration of 10 nonvolatile bit storage.
FIG. 83 one example of supply/programming drivers, blocks 210s and 21 1 s, that can be used for both programming of nonvolatile latch memory cell data plus used for "dark silicon" applications like memory standby, hibernation, and total shutdown for leakage current control especially in billion transistor plus microchips.
FIG. 84 to FIG. 85 show how to build a Soft Programming Line (SPL) structure for program connecting a V[*] potential line bus to a SRAM latch power terminal using Phase Change Memory (PCM) elements. The result is that the SRAM is encoded with 1 b, 2b, or > rewriteable, nvonvolatile, data bits.
FIG. 86 to FIG. 88 explain the steps to soft program connect a SRAM Latch Power Terminal to a V[*] potential line bus using a Soft Programming Line (SPL) then how to soft disconnect
FIG. 89 (another variation of FIG. 74) where a 6T SRAM with 4 Separate Latch Power Contacts, uses 6 transistor diffusion tracks in a 1 st direction and 2 word line, polysilicon tracks in a 2nd direction.
FIG. 90 show Low Voltage, Writeable, 4 Separate Latch Power Contacts, 6T SRAM using 8 transistor, diffusion tracks in a 1 st direction & 2 word line, polysilicon tracks in a 2nd direction. (Writeable at low voltage because when the word line, WL = "1 " or "on", it in turn, also turns on 1 gate of each of the two SRAM cell 4 gated driver transistors. Since both driver transistors are at least ¼ "on", whichever of the two PMOS pull-up or load device or transistor is "on" will be weakened but not overcome. So, now, if a write data signal desires to pull that PMOS pull-up down to "0", it has an easier time. Hence, a lower power supply voltage, writeable 6T SRAM is created. Note, due to this problem of low supply voltage, writeability, some chip manufactures, like IBM of note, have abandoned the 6T transistor SRAM and are, instead, using embedded DRAM as their computer processor chip local high speed memory. Som other manufactures have left the 6T SRAM to pursue the much larger, cell area, 8T transistor SRAM as well when low voltage operation is required.)
FIG. 91 show Low Voltage, Writeable, 4 Shared Latch Power Contacts, 6T SRAM using 8 transistor, diffusion tracks in a 1 st direction and 2 word line, polysilicon tracks in a 2nd direction. (Unlike FIG. 90 whose additional average cell area provides physically separate latch power contacts that can then be utilized to store single ended, potential line combination, nonvolatile data, these 6T SRAM cells focus more on smaller cell size without the ultimate in potential line combination nv data & focuses on low voltage, writeable and small cell size.)
FIG. 92 to 105 illustrate how to take the 6T SRAM using 8 transistor diffusion tracks with shared positive and negative supply contacts between next neighbor cells and create "separate and interlocked" said supply contacts so that direct injection of computer instructions into one cell do not affect adjacent cells. This also results in much higher data storage density. DETAILED DESCRIPTION OF THE INVENTION
The specification, examples and figures used in this detailed description of the invention are to be considered only sample implementations of many possible invention embodiments and are not to be construed as invention limitations or limiting the invention's scope except as defined by the attached claims.
This application claims the benefit of U.S. provisional application nos. 61 /992,741 and 61/992,773 filed May 13, 2014, which are incorporated herein in its entirety by reference.
The Applicants PCT application entitled "DRAM Cells Storing Volatile and Nonvolatile Data" which claims priority of provisional application 61/989,766 filed May 7, 2014; and PCT application entitled "4 Bit Nonvolatile Embedded DRAM" which claims priority of provisional application 61/994,254 filed May 16, 2014; and PCT application entitled "1 to 3 Bit Storage Node Rectifier or 2 to 3 Bit NV like VR or FG to Potential Line Combination NV Memory Cells and Systems (4 BIT NV Flash or VR Memory)" which also claims priority of provisional application 61/994,254 filed May 16, 2014 are all being filed simultaneously with the present application and all three applications are hereby incorporated herein by reference in its entirety.
The following terms and phrases are used throughout the specification and have the meanings assigned thereto, unless specified otherwise.
1 .. [[ ]] is the mathematical symbol for the greatest integer function or also known as the ceiling function that rounds a decimal # input to the closest integer value that is greater than the # inputted. For example the greatest integer just above 1 .3 is 2, then expressed mathematically as: [[ 1 .3 ]] = 2. The greatest integer just above 2.5 is 3, then expressed mathematically as: [[ 2.5 ]] = 3.
2. SAR = small aspect ratio. A patent term specifically describing a static random access memory (SRAM) cell layout where the latch loads, latch drivers, and pass transistor or transistors are generally in 4 parallel transistor diffusion paths facing the same chip direction so that the cell is inherently long on 1 axis but short on the perpendicular axis.
3. bus - a set of potential lines.
4. different - the term "different" in reference to a "potential line" does not mean a potential line is physically wider, or electrically lower in resistance. This is not a difference in size or electrical performance. It specifically refers to a "different selection" ie. there are, M, different bus potential lines to choose from where ie. M=2 or greater.
5. nv - abrreviation used in this patent for the term, "nonvolatile".
6. inverter- There are various embodiments of an inverter that may be used in the invention. Basically, a simple inverter is a series circuit of an upper supply like a positive power supply like VDD connected to at least one load's 1 st terminal. Typical loads fall into various categories such as a type of resistor, diode, transistor, or programmable element. The 2nd terminal of at least one said load electrically represents the inverter's output node. This output is a normally a digitally interpreted output with a logic "1 " or logic "0" as the usual final desired steady state output value after a new inverter electrical input is received. This inverter's output node is also represented by and electrically shorted to a driver transistor's 2nd terminal. The driver transistor is usually a voltage controlled switch like a type of field effect transistor (FET). The driver transistor's 1 st terminal is then ususually connected to a lower supply like ground (GND). A voltage input to the inverter is normally presented to the driver transistor's input like a gate terminal. If the load is ie. a field effect transistor then it too will receive a gate terminal input signal. The inverter voltage input signal is normally interpreted as a logic "1 " or logic "0" value. The inverter's voltage output will be an opposite digital logic value to whatever was presented on the input. So if a logic "0" or digitally interpreted "low" were an input to the inverter, the inverter output would be a logic "1 " or "high" output, if a logic "1 " or digitally interpreted "high" were an input to the inverter, the inverter output would be a logic "0" or "low" output. More complex inverters can be constructed out of NAND gates or NOR gates as well.
7. latch - a digital memory cell storing bistable, volatile, digitally interpreted data like a logic "1 " or logic "0". Simple latches are basically a pair of cross-coupled inverters constructed of a pair of typically 1 load plus 1 driver inverters. However, latches can also be constructed of a plural # of loads and drivers within cross-coupled, SR or Set Reset NAND gates or cross-coupled, Set Reset NOR gates, which are then if included with a clock input become a flip-flop.
This bistable, volatile, cross-coupled memory cell stores 1 bit of binary data which optional may have an asynchronous or clocked input or inputs for setting and resetting the memory cell's digital state. Examples include: cross-coupled inverters, cross-coupled NAND gates, cross-coupled NOR gates, and the like or equivalent. Optionally for setting and resetting these devices and their like and equivalents just mentioned there may also be: pass transistors, inverters, NAND gates, NOR gates, that may be clocked or asynchronous for allowing inputs to change the digital state of the memory cell. Examples providing latches with set reset capabilities include: cross-coupled NAND or NOR gates with asynchronous set and reset inputs, D and SR clocked latches; D, SR, JK, Toggle clock edge triggered flip-flops, SRAM cells of all types, etc. In the present invention the set reset inputs are surprisingly provided through the cross-coupled inverter's latch power terminals.
8. latch device- is specifically referring to 1 latch load or 1 latch driver. The latch device can be, for example, a resistor, a diode, a schottky barrier diode, a transistor, a one time programmable fuse, a programmable memory element like a memristor, a phase change memory element (PCM), the like, or equivalent, etc. A latch memory cell made of cross- coupled inverters will comprise typically 2 latch loads and 2 latch drivers or, in other words, 4 latch devices.
9. selectively driven - refers to a microchip manufacturer or a user having made a personalized choice between two or more different lines of a bus of potential lines to choose from for supplying an electrically driven signal for a bistable latch load or bistable latch driver power contact to receive. The driving signal could be a fixed supply line or power line. The driving signal could be a driver circuit output capable of transmitting at least 2 different digital values like a logic "1 " or logic "0", etc. The personal choice or programming could have been accomplished by "mask programming" at the chip factory or foundry for which bus potential line to electrically connect or couple to. The personal choice could be delayed until after the microchip has been completely manufactured and even programmed within the final system or "field programmable" by electrically pulling on only the desired bus potential line for driving that latch cell to a required programming current level to like set or reset a programmable memory element like: a phase change memory (PCM) element, or a resistive random access memory (ReRAM) element like a metal oxide, or a solid electrolyte, or a memristor, efuse, etc.
10. selectively supplied -refers to a microchip manufacturer or a user having made a personalized choice between 2 or more different lines of a bus of potential lines to choose from for supplying an electrically driven signal for a bistable latch load or bistable latch driver power contact to receive. The supplying signal could be a fixed supply line or power line. The supplying signal could be a driver circuit output capable of transmitting at least 2 different digital values like a logic "1 " or logic "0", etc. The personal choice or programming could have been accomplished by "mask programming" at the chip factory or foundry for which bus potential line to electrically connect or couple to. The personal choice could be delayed until after the microchip has been completely manufactured and even programmed within the final system or "field programmable" by electrically pulling on only the desired bus potential line for supplying that latch cell to a required programming current level to like set or reset a programmable memory element like: a phase change memory (PCM) element, or a resistive random access memory (ReRAM) element like a metal oxide, or a solid electrolyte, or a memristor, efuse, etc.
11 . ""single ended, selectively supplied" - 1 selected or chosen, electrical connection from 1 potential line of a bus of, N, or more potential lines electrically supplying 1 bistable latch load or 1 bistable latch driver power contact can encode, B bits of nonvolatile data calculated as: B = [[log2N]], binary bit or bits per 1 latch load or per 1 latch driver, where the mathematical function, [[ ]] , is the greatest integer function. A bistable latch with 2 latch loads or 2 latch drivers could, therefore, accommodate 2 different "single ended, selectively supplied, latch loads or latch drivers" so encoding: B = [[log2N]] + [[log2M]], binary bit or bits per 2 latch loads or 2 latch drivers, or combination thereof.
A single ended, selectively supplied nonvolatile data uses a 2 step process to read out encoded or stored data:
Step 1 , a selectively supplied latch load must have a means of presetting its storage node before read out of nonvolatile data encoded to its upper supply terminal like VDD. Else, a selectively supplied latch driver must have a means of pre-clearing its storage node before read out of nonvolatile data encoded to its lower supply terminal like GND. This presetting or pre-clearing of storage nodes can be accomplished by the addition of SRAM pass transistors for performing the same, or through the use of latch loads or latch drivers driven by 2 potential line buses sharing no electrically common potential lines so that ie. one bus can has all its potential lines toggled so that the latch is forced to preset or preclear.
Step 2, a selectively supplied latch load or latch driver assigned bus lines should be pulsed low or high according to the nonvolatile data bit to be read out. The invention flow charts show greater details. This illustrates not only how to build or make the invention and it also explains how to operate such an invention to obtain the unexpected result of increased encoding and storage of data. Thus the invention two step process, as described above and in the flow chart with example timing diagrams accompanying them, provide detailed instructions on how to operate i.e. a nonvolatile SRAM by first presetting or pre- clearing followed by pulsing of appropriate bus lines for reading out "single ended" encoded, nonvolatile data.
12. "differential, selectively supplied" - 2 selected or chosen, electrical connections from 2 differential potential lines each electrically supplying 2 bistable latch loads or 2 bistable latch driver power contacts, or combination of, is required and only encodes, B = 1 , bit of nonvolatile data per 2 latch loads or 2 latch drivers or a combination of, where the mathematical function, [[ ]] , is the greatest integer function. Again, 2 selected, electrically driven connections to 2 bistable latch loads, drivers, or combination of, is required and only encodes and hence only stores, B = 1 , bit of nonvolatile data.
In contrast, to the single ended approach, a "differential, selectively driven" approach, theoretically, requires, 1 st, a minimum of 2 potential lines selected not 1 line alone. 2nd, these lines must be "differential" meaning they must act as binary complements of each other. For example, if one line is pulsed "low" the other line must remain "high". Similarly, if one line is pulsed "high" the other must remain "low" . These selected potential lines are, therefore, "dependent" upon one another not "independent" or "free to be programmed separately" as single ended programmed lines are.
Worse, a "differential, selectively driven" approach, theoretically, due to this dependency limitation can only store, B=1 , nonvolatile data bit per pair of latch loads or drivers.
Repeating, again, a patent phrase meaning, 2, selective electrical connections from, 2, latch loads or, 2, driver power terminals to 2 different bus potential lines can encode or store, only 1 , nonvolatile data bit per latch power terminal pair.
These differential programmed couplings are"dependent" not "independent" to one another. For example, if latch power terminal 1 and 2 are differentially coupled to power supplies VDD1 and VDD2 respectively to store a "0" nonvolatile data bit then to store a "1 " nonvolatile data bit, latch power terminals 1 and 2 must be conversely differentially coupled to VDD2 and VDD1 , respectively. So, 2 interconnect couplings must change each time 1 bit is changed from a "0" logic state to a "1 " state and vice versa. contacts physically separate- a phrase used herein with other similar versions of the same phrase indicating that 2 latch loads or 2 latch drivers have their semiconductor power contacts or substrate contacts physically offset from one another ie. some type of insulation like silicon dioxide or field oxide is physically and electrically isolating these 2 latch load power contacts or 2 latch load driver power contacts away from each other. They may be made on the same chip layer but are physically offset from one another. Furthermore, not only are these contacts physically offset from each other and insulated from each other but their underlying source/drain diffusion they electrical connect to are also physically offset and electrically insulated from each other as well. Specifically, this physical and electrical isolation is on the substrate contact and transistor diffusion layers. However, the metal 1 and above layers are custom selectable or programmable by the factory or user.
The advantage of the invention power contacts being physically separate, is that for a said latch load or latch driver power contact pair, each power contact has the freedom to be single ended, selectively electrically supplied by its own bus potential line or supply/nonvolatile programming line that can be the same or totally independent of its sister latch power contact. The single ended electrical connections can provide more than 1 nonvolatile bit storage whereas prior art differential ended electrical connections have been shown to store only 1 nonvolatile bit.
Another advantage of the power contacts being physically separate between next store neighbor latch cells like SRAM cells is that nonvolatile data storage capability is not shared with an adjoining cell and diluted, hence, potentially double the nonvolatile data storage density is possible.
If 2 cells are next store neighbor SRAM cells with both differentially coupled to store nonvolatile data, there are certain nonvolatile encodings that both with shared latch contacts cannot achieve or store because they would be in conflict. This prevents or blocks next store neighbor SRAM cells from both storing differentially coupled nonvolatile data if just 1 of the latch power contacts to be used for differential coupled nonvolatile storage is shared between the 2 SRAM cells.
14. power contacts physically shared - is a phrase meaning latch load or latch driver power contact pairs are, "physically shared", between next store neighbor latch cells like SRAM cells are forced to share their nonvolatile data storage capability between adjoining cells which is half the data storage density possible verses if latch power contacts between next store neighbor cells are "physically separate."
15. "next store neighbor" is a phrase referring to 2 same type memory cells like ie. 2 latch cells or like ie. 2 SRAM cells physically adjacent to each other without any other same type cell between them. Furthermore, if ie. 2 latch cells or ie. 2 SRAM cells are specifically indicated then these 2 next store neighbor SRAM cells will either electrically connect to at least a same bit line or electrically connect to a same word line, again, without any same type cell between them also electrically connected to the same bit line or the same word line.
Now a series of next store neighbor cells or a group of next store neighbor cells can be formed as well. In this case, for each cell in this group or series of, each individual cell must have at least 1 same type cell physically adjacent to it without any same type cell between. Again, when latch cells or SRAM cells are referred to, each individual cell must electrically connect to either a same word line or a same bit line as the next store neighbor cell.
16. "interlocked" refers to at least 2 next store neighbor, latch memory cells with pass gates with a shared bit line contact between these cells on call it side "A". On that side "A" a 1 st latch memory cell has a latch load or latch driver transistor power contact physically separate from any other latch power contact. Also on that side "A" a 2 latch memory cell also has a latch load or latch driver transistor power contact physically separate from any other latch power contact. These 1 st and 2nd latch memory cells are interlocked.
Nonvolatile Programming Table
The bistable latch memory cell programming table listed in FIG. 4 documents a sample listing of programmed, personalized bistable latch memory cells, specifically their "latch power terminal" or "terminals", "selectively supplied by" single or dual supply-programming buses or simply potential line buses of, n, or, n and m, potential line structures (ie. structures can include interconnect lines, contacts, vias, and the like) The surprising result of these latch power terminal or terminals to supply bus combinations is that latch memory cells, like within SRAM memory arrays, are now provided the "numerical capacity to encode, or represent and hence store" at least B = 1 to 6 nonvolatile data bits or binary digits of data storage per SRAM cell plus the actual binary values or numbers stored.
The numberof binary nonvolatile bits stored per bistable latch memory cell are calculated in the following situations as follows. For bistable latch memories with a "1 latch power terminal" selectively supplied by one line of a supply-programming bus of, n, potential lines, thus making, C=n, coupling combinations, we calculate the # of binary nonvolatile digits encoded, so represented, and hence stored per such cell as:
(1 ) B = log2[ C ] = log2[n], for, n , being a power of 2 # , or
B = [[ log2[ n] ]] for, n , being a non-power of 2 #, where the function, [[ ]] represents the greatest integer function. For bistable latch memories, like SRAM, with "2 latch power terminals" selectively supplied by different supply-programming buses of, n and m, potential lines, create, C= n x m, different coupling combinations. We calculate the # of binary nonvolatile digits encoded and so stored per such cell as:
(2) B = log2[ C ] = log2[nxm ], for, n & m, powers of 2 #s, or
B = [[ log2- n ] ]] + [[ log2- m ] ]] for, n & m, non-power of 2 #s, where, [[ ]], represents the greatest integer function or ceiling function.
These "coupling combinations" described above can with just interconnect alone "hard encode" these bistable latch memory cells with the "numerical capacity" to represent and hence store different nonvolatile numbers. One of the ways of assigning numerical values to these "different coupling combinations" is to assign 1 by 1 each of the, for example, n, potential lines of an ie. V bus, and each of the, for example, m, potential lines of an ie. P bus, with an sequentially increasing binary value starting from 0, for example:
n=2 then potential lines are sequentially valued as O2, & I 2;
n=4 then potential lines are sequentially valued as OO2, 012, I O2, & 112;
n=8 then potential lines are sequentially valued as OOO2, 0012, 0102, 0112,
1002, 1012, 1102, & 1112 etc. "Hard encoding" means the selective, personalized, or programmed "interconnect" coupling that can be used in a semiconductor chip process which can include ie. metal wiring, polysilicon wiring, vias, contacts, and the like. "Soft encoding" is also implied in this invention since resistive RAM, phase change memory, memristor, conductive bridge RAM, solid electrolyte, electrical fuse, etc. elements can be employed to accomplish the coupling desired as well.
Encoded values are interpreted for personal preference sake, ie. 1 of many possible embodiments, as follows. If a latch power terminal on the "true side" or "non-inverted output side" of a bistable latch memory cell were coupled to say potential line, 012, then the nonvolatile number stored in that latch memory cell we will interpret in personal preference to be the same or non-inverted value stored, 012- On the other hand, if a latch power terminal on the "complement side" or "inverted output side" of a bistable latch memory cell were coupled to say potential line, 1012 then the nonvolatile number stored in that bistable latch memory cell we will interpret, in personal preference, as saying the inverse is being stored or, OI O2■
The programming table, FIG. 4 is applied in the upcoming bistable latch memory cell examples, FIG. 6, storing 1 , 2, 3, and 4 nonvolatile bits using a "single" latch power terminal per cell "selectively supplied" or encoded, and in FIG. 7 to 9, bistable latch memories storing: 2, 3, 4, 5, and 6 nonvolatile bits using 2 latch power terminals per cell both "selectively supplied" or so encoded.
For notation purposes throughout this specification, the following is defined:
(3) Mk[B-1 :0] to mean:
M = a bistable latch memory cell;
k = the identifying # of a bistable latch memory within a group of same like cells;
like the # of a SRAM cell within a memory column of same like SRAM cells; B = # of nonvolatile bits or binary digits stored within said bistable latch memory;
[B-1 :0] = indexes or addresses of each binary digit stored either:
(a) within a single latch power terminal coupling of a said bistable latch memory
cell whose value is non-inverted when stored on the "true side" or inverted when stored on the "complement side"; or
(b) within the "true side" latch power terminal coupling concatenated with the
inverted value(s) stored on the "complement side" latch power terminal coupling.
As an assumption used limitation in the upcoming examples and in this specification, a set of, n, and a set of, m, potential lines in a bistable latch memory cell can "share up to one potential line".
Examples of bistable latch memory cells storing 1 to 6 nonvolatile bits within either a single latch power terminal or a pair of latch power terminals are shown in FIG. 6, 7, 8, and 9.
Example 1 - Cells with 1 Latch Power Terminal Storing 1 , 2, 4 and 8 Nonvolatile Bits
See FIG. 6 a series of "single latch power terminal", selectively supplied, bistable latch memory cells, 55, 56, and 57. Following the FIG. 4 nonvolatile programming table lines: (a) A to B, (b) 3 to 6, (c) 11 to 18, and (d) 19 to 28,
The memory cell column of 3 "interlocked" * latch memory cells, with a, V, supply- program bus of, n = 2, 4, 8 and 16, potential line structures, respectively, stores the following nonvolatile data within cells: 55, 56, & 57 as follows:
(4) M55[0] = 12 or M55[1 :0] =012 ; M56[2:0] =0102 ; & M57[3:0] = 11102 .
storing 2, 3, and 4 nonvolatile binary bits, respectively. In the case of memory cell, 57, that even though 4 bits are required to list all programming values from Programming Table lines, 19 to 28, of FIG. 4, not all possible binary values between, 19 to 28, are utilized.
Example 2- Cells with 2 Latch Power Terminals Storing 2 Nonvolatile Bits
See FIG. 7 a series of "2 latch power terminals" selectively supplied, bistable latch memory cells, 60, 61 , and 62. Following the FIG. 4 Nonvolatile Programming Table lines:
1 to 2, we see that this memory cell column of 3 "inter-locked" bistable latch memory cells, with a, V, supply-programming bus of, n=2, potential lines, and a, P, supply- programming bus of, n=2, potential lines, respectively, stores the following nonvolatile data within cells: 60, 61 , & 62 as follows: (5) M60[1 :0] = 002 ; M61 [1 :0] =012 ; and Mg2[1 :0] = 102 ,
storing, 2, nonvolatile binary bits per cell respectively.
Example 3 - Cells with 2 Latch Power Terminals Storing 3 Nonvolatile Bits
See FIG. 8 a series of "2 latch power terminals" selectively supplied, bistable latch memory cells, 63, 64, and 65. Following the FIG. 4 Nonvolatile Programming Table lines:
7 to 10, we see that this memory cell column of 3 "inter-locked" latch memory cells, with a, V, supply-programming bus of, n=4, potential lines, and a, P, supply-programming bus of, n=2, potential lines, respectively, stores the following nonvolatile data within cells:
63, 64, and 65 as follows:
(6) M63[2:0] =0002 ; M64[2:0] =0112 ; and M65[2:0] =1012 ,
storing, 3, nonvolatile binary bits per cell respectively.
Example 4 -Cells with 2 Latch Power Terminals Storing 4 Nonvolatile Bits Respectively
See FIG. 9 a series of bistable latch memory cells, 66, 67, and 68. Following lines, 29 to 32, of the nonvolatile programming table of, FIG. 4, we see that in FIG. 9, this memory cell column of 3 interlocked, bistable latch memory cells, with a, V, supply-program bus of, n=4, potential line structures, and a, P, supply-program bus of, m=4, potential line structures, respectively, selectively stores, B=4 = lc^tnxm], bit nonvolatile binary numbers within each memory cell 66, 67, and 68. Based on the specific binary coding of the, V and P bus, potential line structures, program coupled to, seen in switches, S12 to S17, of FIG. 9, the resulting, 4 bit nonvolatile numbers stored in cells, 66, 67, and 68 are:
(7) M66[3:0] = 00112 ; Mg7[3:0] = 01102 ; and M68[3:0] =11002 .
Example 5 - Cells with 2 Latch Power Terminals Storing 5 Nonvolatile Bits Respectively
See FIG. 9 a series of bistable latch memory cells, 66, 67, and 68. Following lines, 33 through 40, of the nonvolatile programming table of, FIG. 4, we see that in FIG. 9, this memory cell column of 3 interlocked, bistable latch memory cells, with a, V, supply-program bus of, n=8 , potential line structures, and a, P, supply-program bus of, m=4, potential line structures selectively stores, B=5
Figure imgf000038_0001
bit nonvolatile binary numbers within each memory cell 66, 67, and 68. Based on the specific binary coding of the, V and P bus, potential line structures, program coupled to, seen in switches, S12 to S17, of FIG. 9, the resulting, 5 bit nonvolatile numbers stored in cells, 66, 67, and 68 are:
(8) Mfi6[4:0] =000112 ; Mfi7[4:0] = 001102 ; and Mfi8[4:0] =111002 . Example 6 - Cells with 2 Latch Power Terminals Storing 6 Nonvolatile Bits Respectively
See FIG. 9 a series of bistable latch memory cells, 66, 67, and 68. Following lines, 41 through 48 of the nonvolatile programming table of, FIG. 4, we see that in FIG. 9, the memory cell column of 3 interlocked, bistable latch memory cells, with a, V, supply-program bus of, n=8 potential line structures, and a, P, supply-program bus of, m=8, potential line structures selectively stores, B=6 =log2[nxm], bit nonvolatile binary numbers within each memory cell 66, 67, and 68. Based on the specific binary coding of the, V and P bus, potential line structures, program coupled to, seen in switches, S12 to S17, of FIG. 9, the resulting, 6 bit nonvolatile numbers stored in cells, 66, 67, and 68 are:
(9) M66[5:0] =0001112 ; M67[5:0] =0011102 ; and M68[5:0] = 1110002.
Reading Nonvolatile Data 1 Bit at a Time with Dark Silicon
In FIG. 6 to FIG. 9, the supply-programming buses, V, and, P, provide normal operating power or are switched on and off to read out or release nonvolatile data like stored in cells, 55 through 68 into their respective volatile memory nodes, Q1 , and, Q0, using like circuit block, 72, or program switches, coupled to, VQ through VN and, PQ through Pn_-| . As a
1st example, these program switches can be as simple as a single switch like using only a single transistor per supply-programming line, like only using NFET transistors, Mm ^ to
MQ, shown in circuit, 72, where a program switch "on" shorts a supply-programming line to a supply rail or virtual supply rail, achieving a 1 st logic state, and a program switch "off' or "float" might allow a memory cell's own internal current leakage to approach the opposite supply rail or virtual supply rail representing a 2nd logic state. A 2nd example for these program switches can be a complete inverter for, instead, solidly supplying both logic states, like any inverter drivers, An to AQ, shown in circuit block, 72, or specifically CMOS inverter drivers if both PFET transistors, MPm_i , through, MPrj, as well as, NFET transistors, Mm ^ to MQ, are included.
A 3rd example, not shown, could be a series of larger and larger inverters building up to a final set of drivers, An to AQ, allowing gradual drive build up of either logic state.
A 4th example could be a decoder like a tree decoder ending in inverter drivers. These and like circuits are all possible implementations for supplying the supply-program buses, V, and, P, for nonvolatile data read out. DARK SILICON SWITCHES FOR SLEEP OR HIBERNATION
A surprising constructive use of necessary, but unwanted power switches, or dark switches discussed in the background of invention, can become multi-purpose, being leveraged to, first, serve as "supply/programming switches" as just discussed above for constructively reading out multi-bit nonvolatile data stored in bistable latch memories, as well, secondly, functioning as "dark silicon switches" providing but providing limited power to sections of large microchips to sleep or hibernate large memory arrays of circuit partitions without losing data. This is where the shown, Pbias- and, Nbjas, would be modulated to controlled more accurately for sleep or hibernation modes.
Two Methods to Read Out 1 Digit At a Time Nonvolatile Latch Power Terminal Coupled Data
Sequential steps to read out multi-bit nonvolatile data within bistable latch memory cells, 55 to 68, in FIG. 6 to 9 using switching block, 72, with 2 voltage supply drivers just described above, are explained in the Read Flowchart FIG. 17 and working examples given in timing diagram tables FIG. 11 to FIG. 17, These timing tables outline 2 different methods to read out nonvolatile, latch power terminal coupled, cell data, into each cell's, Q1 , &, Q0, volatile complementary memory.
A. The SRAM preset or preclear Method is based on pairs of supply/nonvolatile programming buses like VDD1 & VDDO in FIG. 6 to 9 that share 1 supply line in common so that fewer supply lines are required resulting in wider supply lines. The steps follow the read flowchart FIG. 17 (please see!) & also read following:
(1 ) latch memory cells are 1 st initialized by turning SRAM word lines: WLO, WL1 , &
WL2 first "on" then writing bit line data, BL[1 :0] to these cells for preseting or preclearing.
(2) The VDD1 and VDDO bus potential lines or supply/nonvolatile programming lines providing power to these latch memory cells' power contacts, are binary coded based on typically the decoding logic coupled to their dual supply drivers, or the processor bus lines that drive them, or etc. These binary coded bus lines following the FIG. 17 flow chart are then pulsed "1 " or "0" based on the nonvolatile binary digit to be read.
(3) VDD1 or VDDO bus supply/nonvolatile programming lines are then returned to
their normal supply-side state ie. like latch load power terminals are returned to a "high" & latch driver transistor power terminals are returned to a "low".
B. The 1 st or 2nd Bus Preset or Preclear Method can be used for pairs of supply/nonvolatile programming buses like VDD1 & VDDO in FIG. 6 to 9 that are completely separate ie. no shared potential lines between 1 st & 2nd buses. The steps follow the read flowchart FIG. 17 (please read!) & generally are the following:
(1 ) latch memory cells, in this case, are 1 st initialized by pulsing either all the 1 st bus supply lines or 2nd bus supply lines. The direction of the pulse ie. a "1 " or a "0" will be opposite the 1 st bus or 2nd bus steady state voltage for providing normal latch memory cell power. For more detail, again see the flowchart of FIG. 17.
This pulsing of the entire 1 st or 2nd bus supply lines will preset or preclear the latch memory cell.
(2) Each 1 st or 2nd bus supply/nonvolatile programming lines or potential lines are
next pulsed "1 " or "0" based on the specific nonvolatile binary digit to be read out.
(3) 1 st and 2nd bus supply/nonvolatile programming lines are then returned to their
normal steady state voltage to support latch memory cell volatile data storage, for example, latch load power terminals are made "1 " & latch driver power terminals are made "low".
Timing Diagrams to Read Out 2, 3 and 4 bit Nonvolatile Data
In the bistable latch memory cells of FIG. 6 we find that 1 , 2, 3, and 4 bit data are stored within a "single latch power terminal" of each of the memory cells, 55, 56, and 57. Following Read Flowchart, FIG. 17 we can read the timing diagram table of FIG. 11 and see that times, T1 to T4, and times, T5 to T8, describe in detail the 2 different methods discussed above to read out the memory cell data stored: M55[0] = 12 > and M55[1 :0] = 012 . using a 1 & 2 bit, V supply-programming bus, the potential lines each, like coded as: 02 & 2 or 002. 01 2, 102, and, 112-
Following Read Flowchart, FIG. 17 shows that also, in FIG. 11 , times, T9 to T14, and times, T15 to T20, describe in detail the 2 different methods just discussed above to read out the memory cell data stored: M56[2:0] = 0102, using a 3 bit, V supply-programming bus, the potential lines each, like coded as:
0002, OOI 2- 0102. 011 2- 002 > 1012- 02' 111 2.
Following Read Flowchart, FIG. 17 we can see further, in FIG. 12, times, T21 to T28, and times, T29 to T36, describe in detail the 2 different methods just discussed in section 10 above to read out the memory cell data stored: M57[3:0] = 11102- using a 4 bit, V supply-programming bus, the potential lines, like coded as:
OOOO2, OOOI 2- 00102, OOI I 2- 01002, OI OI 2- 01102, OII I 2- 10002, 10012, 10102, 10112, 1 1002, 11012, 11102, 11112-
Timing Diagrams to Read Out 2 bit Nonvolatile Data
In the bistable latch memory cells of FIG. 13 we find that 2 bit data is stored within a "pair of latch load power terminals" of each of the memory cells, 60, 61 , and 62. Following Read Flowchart, FIG. 17, we can read schematic FIG. 7's timing diagram table FIG. 13 and see that times, T1 to T8, and times, T9 to T12, describe in detail the 2 different methods just discussed in section 10 above to read out the memory cell data stored: ΜβθΠ ^Ο] = 002 ;
M61 [1 :0] = 012 ; M62[1 :0] = 102,
using a 1 bit, V & 1 bit P supply-programming buses, whose potential lines, ie. are each coded as: O2 and 12- Timing Diagrams to Read Out 3 bit Nonvolatile Data
In the bistable latch memory cells of FIG. 8 we find that 3 bit data is stored within a "pair of latch load power terminals" of each of the memory cells, 63, 64, and 65. Following Read
Flowchart, FIG. 17 ,we can read FIG. 8's timing diagram table FIG. 14 and see that times,
T1 to T12, and times, T13 to T18, describe in detail the 2 different methods just discussed above to read out the memory cell data stored: Μβ3[2:0] = 0002 ; Μβ4[2:0] = 0112 ;
M65[2:0] = 1012 , using a 2 bit, V & 1 bit P supply-programming buses, whose potential lines, ie. are each coded as:
OO2- 012- I O2- and, 112; and O2 ,12. respectively.
Timing Diagrams to Read Out 4 bit Nonvolatile Data
In the bistable latch memory cells of FIG. 9 we find that 4 bit data is stored within a "pair of latch load power terminals" of each of the memory cells, 66, 67, and 68. Following Read
Flowchart, FIG. 17, we can read FIG. 9's timing diagram table FIG. 15 and see that times,
T1 to T16, and times, T17 to T24, describe in detail the 2 different methods just discussed in section 10 above to read out the memory cell data stored:
M66[3:0] = 00112; M67[3:0] = 01102 ; M68[3:0] = 11002.
using a 2 bit, V & 2 bit P supply-programming buses, whose potential lines, ie. are each coded as: OO2, 012> I O2- and, 11 2-
Timing Diagrams to Read Out 5 bit Nonvolatile Data
In the bistable latch memory cells of FIG. 9 we find that 5 bit data is stored within a pair of latch load power terminals" of each of the memory cells, 66, 67, and 68. Following Read Flowchart, FIG. 17 , we can read FIG. 9's timing diagram table FIG. 16 and see that times, T1 to T20, and times, T21 to T30, describe in detail the 2 different methods just discussed in section 10 above to read out the memory cell data stored:
M66[4:0] = 00011 2 ; 67[4:0] = OOH O2 ; M68. :0] = 111002.
using a 3 bit, V & 2 bit P supply-programming buses, whose potential lines, ie. are coded as:
0002, OOI 2- 0102. 011 2. 1002. 101 2. 02- 111 2- and
OO2- 01 2- 102. and, 112 - respectively.
Timing Diagrams to Read Out 6 bit Nonvolatile Data
In the latch memory cells of FIG. 9 we find that 6 bit data is stored within a "pair of latch load power terminals" of each of the memory cells, 66, 67, and 68. Following Read Flowchart, FIG. 17, we can read FIG. 9's timing diagram table of FIG. 17 and see that times, T1 to T24, and times, T25 to T36, describe in detail the 2 different methods just discussed in section 10 above to read out the memory cell data stored:
M66[5:0j = 000111 ; M67.5:0] = OOI H O2; M68.5:0] = I H OOO2.
using a 3 bit, V & 3 bit P supply-programming buses, whose potential lines, ie. are coded as:
0002, 0012. 0102. 011 2. 1002. 101 2. 02- 111 2- and,
0002, 0012. 0102. 011 . 100 . 101 . 110 . 111 . respectively.
Sample Timing Diagrams
FIG. 18A and 18B as another option displays the timing diagram table information in a timing diagram form, instead, for FIG. 7 cell 61 where nonvolatile 2b data is read out 1 digit or 1 bit at a time.
A Cell Layout of 3D, Interlocked SRAM cells
A series of microchip mask layer drawings, of the invention just discussed above, are shown in detail in FIG. 19, 20, 21 , 22, 23, to 24. FIG. 25 is optional and is included if programmed memory elements if, for example, resistance variable memory elements ie. phase change memory (PCM) elements ie. GST (see biblio 33 & 34 ) are used in FIG. 24 and up.
FIG. 19 to 24 illustrate in detail, one of the implementations of 1 to 6 bit nonvolatile bistable latches as "interlocked", small aspect ratio (SAR), 3D, CMOS, 1 and 2 fin, 6 transistor SRAM cells, 70s, and 71 s, that with VDD1 and VDDO or 1 st and 2nd bus supply/nonvolatile programming lines on metal layers shown in higher drawing layers, are able to electrically drive a pair of latch power terminals for single ended, selectively storing verses differentially storing 1 to 6 nonvolatile bits of data. SRAM cells, 70s, and 71 s, are one set of possible interlocked layout embodiments of schematic substrate cells, 66s, and, 67s, from FIG. 9.
FIG. 19 specifically shows the substrate level, "interlocked" SRAM cells, 70s, and, 71 s, and their vertical channel, 3 dimensional, N and P diffusion, transistors with polysilicon local interconnect, with contacts to upper metal layers. The CMOS inverter supplies the true side, bit line 1 , BL1 , through pass gate, N5, is made up of dual fin NMOS driver, N1 a and N1 b, and PMOS load, P3. The cross-coupled CMOS inverter supplies the complement side, bit line 0, BLO, through pass gate, N4, is made up of NMOS driver, NOa and NOb, and PMOS load, P2. The gain of the SRAM cell for supplying the bit lines is set at Beta = 2 counting transistor fins only. For example, pass gate transistors are single fin shown here, but "drive" transistors, for this example, are dual fin for double or 2 times the drive (note cell gain can be adjusted as well using different ion implantations in load and driver transistors)(so single fin drivers N1 & NO, can be substituted for the dual fin versions with the use of different ion implants in load & drivers to instead obtain a Beta=2 gain)
Of special interest, in FIG. 19 to 24 the transistor diffusion and interconnect metal layers of SRAM cells like, 70, and, 71 , unlike industry practice in IBM FIG. 3 and Intel FIG. 5, are kept physically separate at the transistor diffusion, power contact, & metal layer levels (see FIG. 19) allowing personalized programming or selective electrically supplying from the upper metal layer VDD1 & VDDO bus potential lines to the lower level, substrate, latch power contacts VDD3, VDD2, VDD1 , & VDDO. These latch power contacts, physically separate and physically independent, would seemingly increase SRAM cell area significantly with no apparent benefit. For example, in FIG. 19 latch power contacts, VDD1 and VDDO, are interlocked or physically offset along SRAM 70's and SRAM 71 's shared cell border.. However, these, now, physically independent, power contacts, also including, VDD3 & VDD2, can be selectively supplied, or independently programmed to supply nonvolatile programming buses, VDD1 , and, VDDO, on upper metal layers. This independence of power terminal program coupling results in, potentially double or 2 times more the nonvolatile memory storage capability verses if these power terminals had had to share not only supply-program contacts between memory cells, but also, as a result, would have to share the nonvolatile data attached to them as well. By breaking free from industry practices of 1 st shared latch power contacts and 2nd shared power lines we get not only 1 st nonvolatile data storage capability, but 2nd maximum nonvolatile data storage capability within these memory cells.
Surprisingly, the inventions use of interlocking latch power terminals of neighboring SRAM cells has the potential advantage to keep SRAM cell area the same, even with the added benefit of integrating multi-bit nonvolatile data storage capability within a memory cell.
This is accomplished by one SRAM cell layout solution illustrated in FIG. 19 which shows word line polysilicon lines or gating like in pass transistors, N5 & N4, which come very close to latch feedback polysilicon lines or gating like in load transistors, P2 & P3. This is the distance labeled, d1 . Similarly, on the contact and metal layers, power contacts, VDD2 & VDDO, also come very close to stretch contacts, Q1 & Q0, in adjacent SRAM cells. This is the distance labeled, d2. This cell layout invention embodiment can be made possible by double patterning lithography (DPL) extended ultraviolet lithography (EUV), etc.
A second SRAM cell layout solution is in FIG. 34. Looking at FIG. 34, word line and latch feedback polysilicon lines are instead separated by the manufacturing of double gate, vertical channel, transistors in between them. This is the short distance labeled, d3 . The word line here when "1 " = "on" or "high" weakens the P pull-up latch loads, P2 & P3, during SRAM cell access so that SRAM write margin is greatly improved. When the word line is "0" = "off' or "low" then the P pull-up latch loads are strengthened and the stability of the SRAM during standby to maintain stored digital data is also strengthened.
A third SRAM cell layout solution uses planar transistors is shown in FIG. 35. Highlighted is the challenge of manufacturing local metal interconnect and polysilicon word line and latch feedback gating. Again, as in FIG. 19 manufacturing methods such as double patterning lithography (DPL), extended ultraviolet light (EUV) lithography, ebeam lithography, etc. are various means to accomplish the manufacturing of the three SRAM layouts just discussed above.
Metal or Programmed Connection Layers for Interlocked Cells
FIG. 20 shows the metal 1 and via 1 layers of two, interlocked, 3D, transistor, SRAM cells. For SRAM cell 70s and 71 s, metal 1 is used to construct the complementary, volatile memory nodes, Q1 , and, Q0. FIG. 21 shows the metal 2 layer lines to transmit word line signals, WLO, and, WL1 . FIG. 22 shows the metal 3 layer lines to transmit SRAM cell differential input/output data, BL1 , and, BLO, plus a common ground array line, GND. FIG. 23 shows the metal 4 layer lines to vertically align the latch power terminal pairs, VDD1 and VDDO, and, VDD3 and VDD2, with memory cell, 70s, and, 71 s, cell edges all in preparation for selective electrical supplying from later metal layers. Finally, FIG. 24 shows metal 5 and above metal and via layers used for bus potential line, selective electrical supplying of positive latch power terminal pair, VDD1 and VDDO, and positive latch power terminal pair, VDD3 and VDD2, with VDD1 and VDDO supply-nonvolatile programming bus lines on metal 5 and up. Notice that the memory cell, 70s, and, 71 s, substrate level cell borders are smaller than the, 70, and, 71 , upper metal layer cell borders. This is because the, VDD1 , and, VDDO, supply-program bus potential lines are shared between neighboring substrate level cells.
Soft Programming Line Layer for Soft Programming of Bus Connections
Soft programming lines (SPL) can be provided for programming the VDD1 or VDD1 & VDDO bus line, soft programmable memory elements shown as "programmed connections" in layers of FIG. 24 ie. resistance variable memory elements ie. phase change memory (PCM) ie. GST or ReRAM like metal oxides, etc. A soft programming line can connect to and soft program connections of FIG. 24. Of course, optionally, these FIG. 24 "programmed connections" can be hard mask programmed with some conductor or metal electrical connection, or can be fuse programmed with large soft programming line voltages applied.
"K" Memory Cells Encoded By Unigue Coupling Combinations
Another invention embodiment is for multi-memory cells or series of memory cells or "k" number of memory cells. Each of said "k" memory cells has a pair of latch load or latch driver power terminals with its own set or pair of, unique or different program coupling combinations with one or more same supply-side, supply-program buses like, V, and, P, shown in the next series of drawings storing multiple bits of nonvolatile data. Drawing examples including "k" memory cells each uniquely program coupled to store different, nonvolatile, binary numbers of 1 to 6 bits per cell are demonstrated in FIG. 26, 27, 28, 29, 30, 31 , 32, and 33.
These "k memory cells" invention embodiments are based on different values for "k memory cells" and whether 1 or 2 supply-program buses like, V, and, P, used in drawings FIG. 26, 27, 28, 29, 30, 31 , 32, and 33 are used to program couple nonvolatile data values into these "k" memory cells.
CASE 1 : "k memory cells" = "n" or like the total # of supply-program bus lines for the, V, supply-program bus. A. So, each of these "k=n memory cells" is uniquely program coupled to a different one of said, n, supply-program bus lines.
CASE 2: "k memory cells" = "n + m", or like the combined total of the, V, and, P, supply- program bus lines, "m" > 1 . A. "n" of these "k=n+m memory cells" is each uniquely program coupled to a different one of said, n, supply-program bus lines. B.A separate "m" of these "k=n+m memory cells" is each uniquely program coupled to a different one of said, m, supply-program bus lines.
CASE 3: "k memory cells" = "nxm", or the total # of binary combinations of two supply- program buses like the, V, and, P, buses, "m" > 1 . So, each of the "k=nxm memory cells" is uniquely program coupled to a different pair of said, n, and, m, supply-program bus lines. FIG. 25, demonstrates, k=n , latch memory cells utilizing all "selective combinations" or latch power terminal programmings for a single latch power terminal for storage of 1 bit, 2 bit, 3 bit, 4 bit, or more nonvolatile #s ie. k=2, k=4, k=8, k=16, or k=2Abits respectively.
FIG. 26, demonstrates, n=2, m=2, for k= n+m = nxm =4, latch memory cells utilizing all "selective combinations" or latch power terminal programmings for two latch power terminals for storage of 2 nonvolatile bit #s.
FIG. 27, demonstrates, n = 4. m =2, for k = n+m = 6, latch memory cells utilizing the minimum # of "selective combinations" or latch power terminal programmings for two latch power terminals for storage of 3 nonvolatile bit #s.
FIG. 28, demonstrates, n = 4. m =2, for k = nxm = 9, latch memory cells utilizing all "selective combinations" or latch power terminal programmings for two latch power terminals for storage of 3 nonvolatile bit #s.
FIG. 29, demonstrates, n = 4. m =4, for k = n+m = 8 latch memory cells utilizing the minimum # of "selective combinations" or latch power terminal programmings for two latch power terminals for storage of 4 nonvolatile bit #s.
FIG. 30, and 31 , demonstrates,, n = 4. m =4, for k = nxm = 16 latch memory cells utilizing alTselective combinations" or latch power terminal programmings for two latch power terminals for storage of 4 nonvolatile bit #s.
FIG. 32, demonstrates, n = 8. m =8, or more, for k = nxm = 64 latch memory cells OR MORE utilizing all "selective combinations" or latch power terminal programmings for two latch power terminals for storage of 6 nonvolatile bit #s.
The examples of "k memory cells" = "n", "n+m", and "nxm" for cells storing 1 to 6 nonvolatile bits are examples and not to be taken as the only possible examples. Many other combinations and lists of cells are not given below.
FIG 34. shows an alternative to FIG. 19 with a 1 to 6 nonvolatile bit, SRAM memory cell or, bistable memory cell implementation, instead, using the word line signal, WL, coupled to a latch transistor gate(s). For example, the embodiment shown is the word line, WL, to the P pull-up transistor gate which weakens the P pull-up when word line is "1 " or "on" allowing a "0" to more easily be written into said SRAM cell or bistable memory since the pass gate as shown has double gates or 2 current channels to, for example, overcome or defeat a P pull-up with only 1 gate "on" or only 1 current channel. Hence, write margin is a BETA=2 with, potentially, 2 current channels pulling down fighting theoretically, 1 current channel pulling up.
FIG. 35 shows an alternative to FIG. 19 with a 1 to 6 nonvolatile bit, SRAM memory memory cell or, bistable memory cell implementation, instead, using planar transistors, , rather than 3 dimensional or vertical channel transistors, specifically showing the following microchip manufacturing layers of:substrate, diffusion, polysilicon, contact, & metal 1 lines for local interconnect.
FIG. 36 explains in more pictorial detail what happens to FIG. 34 when the word line is "on" and "off. In the top cell layout, the SRAM cell word line is "0" or "Off and this makes the P pull-up latch load transistors, with a dynamic Vtp, low in threshold voltage and so strong. This helps, therefore, during SRAM cell non-use, or standby mode, more stable and immune to noise. However, in the bottom SRAM cell layout, the word line has been switched "on" = "1 " and so in case of a SRAM write operation, the word line "on" signal makes the dynamic Vtp of the P pull-up latch loads large or, in other words, advantageously weakens these P pull-ups. The write margin of the SRAM is, therefore, improved.
Next Store Neighbor, Memory Cells
Next Store Neighbor memory cells are shown in FIG. 36 and FIG. 37.
First, the memory cells, 70s and 71 s, from FIG. 20 and 21 are considered as the original "next store neighbor" SRAM memory cells to begin with. Next a copy of SRAM cell, 70s, is placed below these 2 cells as seen. These 3 cells tall or 3 word lines of cells tall are then, 70s, 71 s, and 70s. FIG. 36 only shows parts of Metal 1 , Vial , and Metal 2 mask layers so as to reveal how the word lines, WLO, WL1 , and WL2, are connected.
Next, the 3 SRAM cells tall of, 70s, 71 s ,and 70s, are copied and mirrored about a Y axis that would be parallel to a bit line, BLO, through these 3 cells. Another 3 cells tall are created: 70s, 71 s, and 70s, in FIG. 36.
Second, parts of the Via3, Metal 3, and Via4 layers of this matrix of cells are shown in FIG. 37. This then reveals how the complementary bit line pair of, BL1 , &, BLO, plus pair, BL1 , &, BLO, are connected. In summary, an example of next store neighbor SRAM memory cells are shown as either a matrix of 3 cells tall by 3 cells wide, or 3 word lines of cells tall by 2 complementary bit line pairs of cells wide.
Soft Programming Line (SPL) for Programming, Bus Selectively Supplied, Variable Resistance Memory Electrically Connected, Latch Power Terminal Structure(s) making 1 to 6 Bit. Read Writeable NV SRAM cells
The SRAM cell latch power terminals" ie. VDD1 & VDDO seen in FIG. 19 to 24 selectively supplied with voltages from the VDD1 bus of, N, potential lines & VDDO bus of,
M , potential lines, seen in FIG. 24's upper metal mask layers can be electrically connected in many possible ways. Hard mask programmed electrical connections, fuse connections, variable resistance memory element connections like using phase change memory (PCM), ReRAM elements like metal oxides, etc. are all within the scope of the invention.
FIG. 38 and 39, show how to build a latch cell with a soft programming line (SPL) structure for program connecting and disconnecting V[*] bus potential lines to a SRAM cell latch power terminal using phase change memory (PCM) elements. This structure is soft programmed to allow PCM or GST memory elements to encode the attached latch or SRAM memory cell with: 1 bit, 2 bit, or more, potential line combination, nonvolatile bit(s).
FIG. 40 to FIG. 42, show steps to soft program connect a specific SRAM cell and its targeted SRAM Latch Power Terminal to a V[*] potential line bus. For background on variable resistance memories and specifically phase change memories (PCM) please see and include in entirety from the bibliography references: 35, 36, 37, 38. Note that to program one SRAM or latch cell's nonvolatile data one at a time, the other soft programming lines (SPL) are held at an intermediate voltage like VDD=1V shown so that a (VRESET or Vamorphous state) or else a (VSET or Vcrystallize voltage) are never reached in these other, for example, memory row SRAM or latch cells so these stay unaffected.
Note that once such an SRAM ie. row is programmed or encoded with nonvolatile data, its
GST connections through its attached soft programming line (SPL) are purposefully made amorphous or open circuited or RESET state so that an already programmed row is isolated by high resistance from and so is unaffected by programming of other SRAM cell ie. rows still yet to be programmed. SPL programming lines need not be row focused but can be 1 st direction with V[*] bus potential lines as a 2nd direction.
3b - 10b, Nonvolatile Latch Memory Cells Schematics
FIG. 49 shows a schematic of specially paired, next neighbor, latch memory cells, 100s with 101 s, etc. which share common bit lines, but keep their positive latch power terminal contacts V3, V2, V1 , and V0, "physically separate", and so "physically independent" as well as negative latch power terminal contacts G3, G2, G1 , and GO, "physically separate", & so "physically independent" to allow for nonvolatile data programming and storage. So, unlike prior art latch memory cells with all positive latch power terminals shorted to a single positive supply and with all negative latch power terminals shorted to a single negative or ground supply, cells 100s with 101 s, etc. allow each latch power terminal the freedom, or "physical independence" to be "selectively driven" or "programmed to different supply/programming lines", but within an restricted set of potential lines, or buses, for each specific latch power terminal to choose from.
For example, on the, BL1 , or, "bit line 1 output side", positive latch power terminals, V3, and, V1 , can be individually and selectively driven by a potential line within the positive supply bus, V[ J-1 :0 ] through some coupling means like, S1 and S5. Also, on the, BL1 , or , "bit line 1 output side", negative latch power terminals, G3, and, G1 , can be individually and selectively driven by a potential line within the negative or ground supply bus, Gnd[ M-1 :0 ] through some coupling means like, S3 and S7.
On the, BL0, or "bit line 0 output side", positive latch power terminals, V2, and, V0, can be individually and selectively driven or programmed by a potential line within the positive supply bus, P[ K-1 :0 ] through some coupling means like, S2 and S6. Similarly, on the, BLO, or "bit line 0 output side", negative latch power terminals, G2, and, GO, can be individually and selectively driven or programmed by a potential line within the negative or ground supply bus, L[ N-1 :0 ] through some coupling means like, S4 and S8.
These "coupling means" mentioned comprise, and are not limited to: mask manufactured vias or interconnect, via fuses that could be field or factory programmed, programmable resistive means like ReRAM elements, memristors, phase change memories, conductive bridge RAM elements, solid electrolyte memories, or the like.
Preferably the memory cell layout areas are keep the same, in spite of separating latch power terminals, one invention novelty meshes latch memory cells like, 100s and 101 s, with vertical channel transistors of "different number of fins". For example, cell, 100s, can use "N" vertical channel pull down transistors with 2 fins or "dual fins" for faster memory read performance, however cell, 101 s, instead, would then offset, interlock, or mesh with cell, 100s, by either using "N" vertical channel pull down transistors with only 1 fin or a "single fin" per transistor or else cell, 101 s, will use "dual fin" N pull-down transistors, but with the cell height shorter and the cell width wider for a parallel diffusion cell layout. Other issues to keep zero cell area increase, in the preferred mode, may also be solved by using vertical channel transistors that allow "double gates" which in turn allow different polysilicon lines to come within close proximity of each other without actually ever electrically shorting together due to 3D vertical channels physically separating these different polysilicon lines.
This is seen in the preferred schematic embodiments of cells, 100s, to, 101 s. For example, latch "N" channel pull down transistors, NO, N1 , N10, and N11 are all, 3 dimensional, vertical channel transistors. Similarly, latch "P" channel pull up transistors, P2, P3, P12, and P13 are all, 3 dimensional, vertical channel transistors.
Equations for the # of Binary Bits or Digits Stored per latch memory cell
The equation defining the # of nonvolatile data bits stored by a latch cell is expanded to include at least "3" latch power contacts "selectively driven", "personalized" or "programmed" to 3 potential lines of 3 supply/programming buses like:
V[J-1 ,0], P[K-1 ,0], and Gnd[M-1 ,0], respectively, is given as:
(1 ) B = log2[ C ] = log2[ J x K x M ], for, J, K, & M, powers of 2 #s, or
B = [[ log2(J) ]] x [[ log2(K) ]] x [[ log2(M) ]] for, J, K, & M, non-power of 2 #s, where, [[ ]] , represents the greatest integer function or ceiling function.
The equation can be further defined by the # of nonvolatile data bits stored by a latch memory cell with at least "4" latch power contacts "selectively driven" or "programmed" to 4 potential lines of 4 supply/nv programming buses like: V[J-1 ,0], P[K-1 ,0], Gnd[M-1 ,0], and L[N-1 ,0], respectively is given as:
(2) B = log2[ C ] = log2[ J x K x M x N ], for, J, K, M, & N, powers of 2 #s, or
B = [[ log2[ J ] ]] x [[ log2[ K ] ]] x [[ log2[ M ] ]] x [[ log2[ N ] ]]
for, J, K, M, & N, non-power of 2 #s, where, [[ ]] , represents the greatest integer function or ceiling function.
Programming Table, and Timing Tables
FIG. 50 defines how to program or selectively drive the different positive latch power contacts, V3 to V0, and, G3 to GO, of memory cells, 100s, 101 s, etc. to different supply/programming buses of, "J, K, & M", or , "J, K, M, & N", number of potential lines in order to store 3 to 10 bits of nonvolatile data with the specific binary values listed in each row of the table.
To demonstrate the usage of the FIG. 50 nonvolatile programming table, FIG. 51 through FIG. 58, show specific memory cell pairs programmed to store specific binary values: 3, 4, 5, 6, 7, 8, 9, and 10 bit numbers using latch memory cell pairs, 110s & 111 s through 180s, 181 s.
The sequential process to read each individual nonvolatile bit or digit hidden or stored within each of the latch memory cells of, FIG. 51 through FIG. 58, is described in the flow chart of FIG. 59. The FIG. 59 flow chart is for latch memory cells with 3 to 4 physically separate latch power contacts accessible.
These latch power terminals are not restricted to being only found within the cell substrate latch loads or drivers. An alternative allows for 3 dimensional latch loads or drivers manufactured above the cell substrate level that tap directly off of the latch data terminals.)
Example timing diagrams, are listed in table format rather than timing diagram format, for reading each of the "nonvolatile digits" or "NVD[cell #]", stored in the 3, 4, 5, 6, 7, 8, 9, and 10 bit nonvolatile, latch memory cell schematics of, FIG. 51 through FIG. 58, and described in the timing tables rather than timing diagrams shown in FIG. 60 to FIG. 73. These all follow the nonvolatile data read out flowchart described in FIG. 59.
Latch Memory Cell Physical Mask Layouts
Example chip layouts of 3 to 10 bit nonvolatile, latch memory cell pair with physically separate positive and negative latch power terminals, two, 3D, vertical channel, SAR SRAM cells, are detailed in FIG. 74 to 80. These process layers to manufacture cells 190 and 191 , include their transistors plus interconnect layers, are symbolically drawn in the schematic of FIG. 49. 190 and 191 are manufacturing implementations of schematic cells 100 and 101 where, 190s, 191 s, 100s, and 101 s, would specifically indicate the "s" = semiconductor substrate layers of the design.
The transistor schematic numbering used in the SRAM cells, 100s & 101 s, in the FIG. 49 schematic and their transistor cell layout counterparts in FIG. 74 are the same. FIG. 74 is the latch cell layout embodiment for a dual fin, vertical channel, transistor latch layout interlocked with a single fin, vertical channel, transistor latch layout. For identification purposes, schematic transistors N5, N4, N15, and N14 represent cell layout pass transistors in the SRAM cell layouts 190s and 191 s. Transistor schematic symbols, P3, P2, P13, and P12 represent latch loads in the SRAM cell layouts 190s and 191 s. Transistor schematic symbols, NOa, NOb, N1 a, N1 b, represent dual fin latch drivers for the SRAM cell layout 190s. And transistor schematic symbols, N11 and N10, represent single fin latch drivers for the SRAM cell layout 191 s.
Also, when examining the 3 to 10 nonvolatile bit schematic of FIG. 49 and cell layouts, of FIG. 74, the separate (+) positive latch power contact pair and separate (-) negative latch power contact pair can be identified as follows:
Separate Pair of Separate Pair of
Memory Positive Latch Negative Latch
Cell Power Contacts Power Contacts
190s V3, V2 G3, G2
191 s V1 , V0 G1 , G0
These latch power terminal pairs, as well as any other latch driver or load devices added to the bistable storage nodes, Q1 , and, Q0, are manufactured physically separate or physically independent to allow "independent programming" or "selective driving" to, generally, different supply/programming lines or potential lines for storing different values of nonvolatile data. """sharing of up to 1 potential line between different sets of supply/programming line buses is possible as long as the total # of supply/programming lines is 3 or greater."
Meaning of "Interlocked" or "offset" or "partially interlocked" For definition purposes, the term "offset" herein refers to a generic physical separation of latch power terminal, substrate contacts, of neighboring cells in any direction. However, the term "Interlocked" in this patent refers to latch power terminal, substrate contacts, specifically separated or "physically offset" from each other along the cell substrate border like in FIG. 74 for V1 and V2. So, in the preferred embodiment or "best mode", neighboring latch memory cells are either "partially interlocked" meaning "1 pair" of latch power terminals are physically offset along the cell borders from other pairs of latch power terminals in adjacent cells, or the neighboring latch memory cells are "fully interlocked" meaning both positive and negative latch power terminal pairs are interlocked or physically offset along the cell borders with an adjacent cells. Of great importance, the "best mode" cell layouts of neighboring cells accomplish "partial" or "full interlocking" without increasing the substrate area occupied by a normal latch memory cell. One way to recognize this feature is that the word line, polysilicon to polysilicon, line end to line end separation, can be as small as the thickness of a 3D vertical channel pass transistor as demonstrated by highlighted distances, d1 , and, d2, shown in FIG. 74. This is done in FIG. 74 using word line to latch device coupling. For example, in FIG. 74 the latch devices, N11 & N10, are gate coupled to the word line, WL1 .
Minimal to No Cell Area Growth
Means of achieving minimal to no cell area growth in spite of "physically separating latch power contacts" include: use of vertical channel or 3 dimensional transistors, like double gate devices; with word line to latch device coupling; use of double patterning lithography (DPL); use of extended ultraviolet (EUV) lithography; creation of a new cell layout where not only are all SRAM cell diffusions are in parallel, but they are all physically separate and none are series aligned. All so that different polysilicon line endpoints or metal 1 line endpoints can come into closer proximity than a single mask lithography process would normally allow.
Preferred mode cell layouts, of the interconnect layers of these "fully interlocked", 3 to 10 bit nonvolatile, latch memory cells, 100s & 101 s, etc. in FIG. 49 are shown in: FIG. 74 for substrate, negative & positive diffusion, polysilicon, and contact layers; FIG. 75 for contact & metal 1 layers; FIG. 76 for vial , & metal 2 for memory cell word lines, WL0, and, WL1 ; FIG. 77 for via2, & metal 3 for memory cell bit lines or data lines, BL1 & BL0, where BL1 is the true output and BL0 is the complement output; FIG. 78for via3, & metal 4 in one example embodiment to align V & G latch power terminals for subsequent metal layer program coupling; FIG. 79 for vias 4 to 5, and metal layers 5 to 6 in one example embodiment for Gnd and L supply/programming lines selectively driven from negative latch power terminals, G; FIG. 80 for vias 6 to 10, and metal layers 7 to 11 in one example embodiment for V and P supply/programming lines selectively driven from positive latch power terminals, V.
Word Line Coupled to Latch Driver verses Coupled to Latch Pull-Up
The FIG. 74 SRAM cell layout has various possible variations to achieve READ & WRITE Margins. Let us consider the single fin, N pull-down cell, 191 s, which is the more challenging design case.
A 1 s* embodiment of the cell, 191 s, layout uses word line, WL1 , coupled to one gate of double gate, N pull-downs, N11 & N10. In this case when WL1 = "on" then N11 pulling down against pass transistor, N15, pulling up creating a border line Read Margin = 1 . However, different ion implantations can be used on the pass and pull-down N transistors to create an acceptable Beta > 1 like Beta =2 (READ MARGIN).
A 2nd embodiment of cell, 191 s, switches N11 & P13 as well as N10 with P12. This switch allows WL1 = "1 " = "on" to dynamically weaken the P13 & P12 pull-ups with a large, Vtp, so that a Write Margin=1 .5 or greater is obtainable. When WL1 = "0" = "off' then the reverse is true. P13 & P12 pull-ups are strengthened with a small, Vtp, so that latch cell data is more stable.
Alternative Layout - Fully Interlocked, Dual Fin, 6T SRAM Cell Layout
FIG. 81 shows the layout of 2 next store neighbor, vertical channel, static random access memory (SRAM) cells with 1 shared bit line contact, BL1 , between these adjacent cells, plus complementary shared bit line contacts, BLO, with adjacent, SRAM cells, not shown, but located just above and just below these 2 cells.
This FIG. 81 layout is similar to the FIG. 74 two small aspect ratio (SAR) SRAM embodiments of 2 fully interlocked, single fin, and double fin, vertical channel transistor, latch memory cell pair. However, both cell 208s and 209s have both dual fin pull downs. Let us consider 2 different possible layout configurations of cell 209s and the impact on the SRAM READ & WRITE MARGINS.
A 1 s* embodiment of the SRAM cell 209s layout shows word line, WL1 , directly coupled to N pull-downs, N11 & N10. In this case when WL1 = "on" then N11 pulling down against pass transistor, N15, pulling up creates a Read Margin = 2. However, Write Margin = 1 so different ion implantations are needed to make this margin much larger.
A 2nd embodiment switches N11 & P13 as well as N10 with with P12. This switch allows WL1 = "1 " = "on" to weaken the P13 & P12 pull-ups so that a Write Margin=1 .5 or greater is obtainable ie. a dynamic Vtp. Read Margin is a healthy 2 with dual fin N pull-downs.
Double Patterning Lithography (DPL) or extended ultra violet (EUV) lithography33 are recommended if zero cell area growth is desired. For example, using double patterning, bold wide lined, square contact symbols contrasted with narrow lined, square contact symbols are shown in the layout drawing, preferably, recommending to pattern a 1 st set of contacts in a 1 st photo mask exposure pass & a 2nd set of, close proximity, contacts in a 2nd photo mask exposure pass. This latch memory cell pair layout has each cell with 4 latch device, power contacts independently accessible for nonvolatile selective drivin to store like up to 10 bits or more per cell. The desired zero cell area growth is further attained by modifying the normal SAR SRAM layout or normal parallel diffusion SRAM cell layout. Here in FIG. 81 the pass transistors, N4, N5, N15, & N14, transistor diffusions are moved from being physically in-line with the pull-down transistor diffusions to being in parallel to them. Hence, this parallel diffusion cell layout has all SRAM transistor diffusions separated & in parallel. Because of this physical configuration, the SRAM cell is wider than the normal SAR SRAM layout. But unlike the normal SAR SRAM layout, this cell height is further shortened. This extra width, but with shorter height, parallel diffusion, SRAM cell layout has these benefits. First, all latch power contacts, even for dual fin, pull-down transistors are all physically separate & physically independent for nv programming. Second, because the cell height was shortened while cell width was increased, there is basically zero cell area growth despite the cell's new ability to provide 4 physically independent, latch power contacts.
Supply / Nonvolatile Programming Lines Dual Supply Driver Circuitry
FIG. 83 shows 1 schematic example of blocks, 210s & 211 s, of the supply/programming drivers, that can be used for (1 ) supplying power to maintain memory block, bistable, volatile, latch data; (2) for "dark silicon" or low power memory block operations like: memory standby, hibernation, shutdown, etc.; and (3) for nonvolatile programming bus lines. So, dual supply, driver, switch banks 210s and 211 s can be leveraged for not just electrical current and supply power control via ie. preferably long length, low leakage, transistors like, MQ to and M PQ to M P^ but can be modulated like in timing tables,
FIG. 60 to FIG. 73 for storing and recalling multiple bits of nonvolatile data per latch memory cell.
Soft Programming Line (SPL) for Programming, Bus Selectively Supplied, Variable Resistance MemorvElectricallv Connnected, Latch Power Terminal Structure(s)
making 1 to 6 Bit, Read Writeable NV SRAM cells Possible
The SRAM cell latch power terminals i.e. V1 and VO seen in FIG. 74 selectively supplied with voltages from the V1 bus of, N, potential lines and VO bus, of, M, potential lines, seen in FIG. 58's upper metal mask layers, can be electrically connected in many possible ways. Hard mask programmed electrical connections, fuse connections, variable resistance memory element connections like using phase change memory (PCM), ReRAM elements like metal oxides, etc. are all possible and are within the scope of the invention.
FIG. 83 and 84, show how to build a latch cell with a soft programming line (SPL) structure for program connecting and disconnecting V[*] bus potential lines to a SRAM cell latch power terminal using phase change memory (PCM) elements. This structure is soft programmed to allow PCM or GST memory elements to encode the attached latch or SRAM memory cell with 1 bit, 2 bit or more, potential line combination, nonvolatile bit(s).
FIG. 85 to FIG. 86 illustrate the steps for soft program connect to a specific SRAM cell and is targeted SRAM Latch Power Terminal to a V[*] potential line bus. These figures provide background on variable resistance memories and specifically phase change memories (PCM).
To program one SRAM or latch cell's nonvolatile data one at a time, the other soft programming lines (SPL) are held at an intermediate voltage like VDD=1V shown so that a (VRESET or Vamorphous state) or else a (VSET or Vcrystallize voltage) are never reached in these other, for example, memory row SRAM or latch cells so these stay unaffected. Note that once such an SRAM ie. row is programmed or encoded with nonvolatile data, its GST connections through its attached soft programming line (SPL) are purposefully made amorphous or open circuited or RESET state so that an already programmed row is isolated by high resistance from and so is unaffected by programming of other SRAM cell ie. rows still yet to be programmed. SPL programming lines need not be row focused but can be 1 st direction with V[*] bus potential lines as a 2nd direction.
FIG. 86 to FIG. 88 explain the steps to soft program connect a SRAM Latch Power Terminal to a V[*] potential line bus using a Soft Programming Line (SPL) then how to soft disconnect. FIG. 89 is another variation of FIG. 74 where a 6T SRAM with 4 Separate Latch Power Contacts, uses 6 transistor diffusion tracks in a 1 st direction and 2 word line, polysilicon tracks in a 2nd direction.
FIG. 90 show Low Voltage, Writeable, 4 Separate Latch Power Contacts, 6T SRAM using 8 transistor, diffusion tracks in a 1 st direction & 2 word line, polysilicon tracks in a 2nd direction. (Writeable at low voltage because when the word line, WL = "1 " or "on", it in turn, also turns on 1 gate of each of the two SRAM cell 4 gated driver transistors. Since both driver transistors are at least ¼ "on", whichever of the two PMOS pull-up or load device or transistor is "on" will be weakened but not overcome. So, now, if a write data signal desires to pull that PMOS pull-up down to "0", it has an easier time. Hence, a lower power supply voltage, writeable 6T SRAM is created. Note, due to this problem of low supply voltage, writeability, some chip manufactures, like IBM of note, have abandoned the 6T transistor SRAM and are, instead, using embedded DRAM as their computer processor chip local high speed memory. Som other manufactures have left the 6T SRAM to pursue the much larger, cell area, 8T transistor SRAM as well when low voltage operation is required.)
FIG. 91 show Low Voltage, Writeable, 4 Shared Latch Power Contacts, 6T SRAM using 8 transistor, diffusion tracks in a 1 st direction and 2 word line, polysilicon tracks in a 2nd direction. (Unlike FIG. 90 whose additional average cell area provides physically separate latch power contacts that can then be utilized to store single ended, potential line combination, nonvolatile data, these 6T SRAM cells focus more on smaller cell size without the ultimate in potential line combination nv data & focuses on low voltage, writeable and small cell size.)
FIG. 92 to 105 illustrate how to take the 6T SRAM using 8 transistor diffusion tracks with shared positive and negative supply contacts between next neighbor cells and create "separate and interlocked" said supply contacts so that direct injection of computer instructions into one cell do not affect adjacent cells. This also results in much higher data storage density.
The foregoing description of various and preferred embodiments of the present invention has been provided for purposes of illustration only, and it is understood that numerous modifications, variations and alterations may be made without departing from the scope and spirit of the invention as set forth in the following claims.

Claims

1 . A memory device for storing 1 to 10 bits of single ended, potential line combination, nonvolatile data comprising:
a bit lines (BL), word lines (WL) memory array essentially of complementary, field effect transistor (FET) latch SRAM cells;
wherein said latch transistor has positive or negative supply contact such that said SRAM cell has at least N = 1 unshared, separate and interlocked said latch transistor positive or negative supply contact with any of said next neighbor SRAM cells.
2. The memory device according to Claim 1 , wherein said latch transistors are selected from the group consisting of fully cross-coupled complementary FETs; P and N channel fully cross-coupled FETs; 3 dimensional fully cross-coupled complementary FETs; and 3 dimensional positive metal oxide latch transistor (PMOS), a negative metal oxide latch transistor (NMOS) fully cross-coupled complementary FETs.
3. The memory device according to Claim 1 , wherein said complementary field effect transistor (FET) is selected from the group consisting of FinFET transistors and Tri- Gate transistors.
4. The memory device according to Claim 1 , wherein said N=2 said latch power or ground contacts.
5. The memory device according to Claim 1 , wherein said N=3 said latch power or ground contacts.
6. The memory device according to Claim 1 , wherein said N=4 said latch power or ground contacts.
7. A semiconductor memory chip comprising:
at least, L=2, potential lines;
a bit lines (BL), word lines (WL) memory array mainly of fully cross-coupled, complementary, field effect transistor (FET) latch, SRAM cells; wherein said SRAM cells comprise a latch pull up (PU) or pull down (PD) single ended, selectively coupled to one of said lines; wherein said latch pull up or pull down is selectively encoded to store data, where, B = [[ LOG (said L=2) ]] = 1
2
nonvolatile data bit or digit stored for a said latch PU or PD; wherein said SRAM cell can store a combined 1 volatile + said encoded nonvolatile data of: B= [[ LOG ( said
2
L=2 ) ]] + 1 = 2 data bits or digits per SRAM cell.
8. The semiconductor memory chip according to Claim 7, further comprising L=4
wherein said latch pull up or pull down is selectively encoded to store data, where B = [[ LOG (said L=4) ]] = 2 nonvolatile data bits or digits stored for a said latch PU or
2
PD; wherein said SRAM cell can store a combined 1 volatile plus said encoded nonvolatile data of: B= [[ LOG ( said L=4 ) ]] + 1 = 3 data bits or digits per SRAM
2
cell.
9. The semiconductor memory chip according to Claim 7, further comprising L=8
wherein said latch pull up or pull down is selectively encoded to store data, where B
= [[ LOG (said L=8) ]] = 3 nonvolatile data bits or digits stored for a said latch PU or
2
PD; wherein said SRAM cell can store a combined 1 volatile plus said encoded nonvolatile data of: B= [[ LOG ( said L=8 ) ]] + 1 = 4 data bits or digits per SRAM
2
cell.
10. The semiconductor memory chip according to Claim 7, wherein for each said L potential lines there is a corresponding 1 to said L, said SRAM cells each selectively coupled to said 1 to said L potential lines, implementing each nonvolatile data and said selective encoding.
1 1 . The semiconductor memory chip according to Claim 7, wherein said latch PU or PD device are N separate, interlocked said contacts.
12. The semiconductor memory chip according to Claim 7, further comprising:
at least, L, M, P, and Q sets of said potential lines, a bit lines (BL), word lines (WL) memory array mainly of fully cross-coupled, complementary, field effect transistor
(FET) Latch, SRAM cells , where all said latch pull ups (PU) & pull downs (PD) are each single ended, selectively coupled to 1 of said sets of said potential lines respectively; wherein said latch pull ups and pull downs are each selectively encoded and combined store: B = [[ LOG ( said L ) ]] + [[ LOG ( said M ) ]] + [[
2 2
LOG ( said P ) ]] + [[ LOG ( said Q ) ]] orsaid B data bit(s) or digit(s) of nonvolatile 2 2
data + 1 volatile bit of SRAM data.
13. The semiconductor memory chip according to Claim 12, wherein for each said set of potential lines there is a corresponding 1 to said L, M, P, and Q said SRAM cells respectively each selectively coupled to said 1 to said L, M, P, and Q sets of potential lines, implementing each nonvolatile data said selective encoding.
14. The semiconductor memory chip according to Claim 13, wherein said latch PU or PD device are N separate, interlocked said contacts.
15. The semiconductor memory chip according to claim 12, further comprising:
at least, said L=4, said M=4, said P=8, and said Q=8 sets of said potential lines, said bit lines (BL), word lines (WL) memory array mainly of fully cross-coupled, complementary, field effect transistor (FET) Latch, SRAM cells , where all said latch pull ups (PU) and pull downs (PD) are each single ended, selectively coupled to 1 of said sets of said potential lines respectively; wherein said latch pull ups and pull downs are each selectively encoded and combined store:
B = [[ LOG ( said L=4 ) ]] + [[ LOG ( said M=4 ) ]] + [[ LOG ( said P=8 ) ]] + [[
2 2 2
LOG ( said Q=8 ) ]] or said B = 10 data bit(s) or digit(s) of nonvolatile data + 1 2
volatile bit of normal SRAM data.
16. A memory device comprising: at least, L=4, potential lines;
a bit lines (BL), word lines (WL) memory array essentially of fully cross-coupled, complementary, field effect transistor (FET) Latch, SRAM cells;
wherein said SRAM cells comprise a differential said pair of pull ups (PU) or pull downs (PD) are selectively coupled to 2 of said L potential lines; wherein said pair of
PUs or PDs are selectively encoded and store: B = [[ LOG (said L=2) ]] + [[
2
LOG (said L=2) ]] = 2 nonvolatile data bits or digits stored for a said differential pair 2
of said latch PUs or PDs.
17. The memory device according to Claim 16, wherein
at least said, L = 6 potential lines or M+N = 4+2, sets of potential lines;
wherein a said differential said pair of PUs or PDs are selectively coupledjo said M and N sets of potential lines respectively; wherein said pair of PUs or PDs are selectively encoded and store: B = [[ LOG (said M=4) ]] + [[ LOG (said N=2) ]] = 3
2 2
nonvolatile data bits or digits stored for a said differential pair of said latch PUs or
PDs.
18. The memory device according to Claim 16, wherein at least said, L = 8 potential lines or M+N = 4+4, sets of potential lines; wherein a said differential said pair of PUs or
PDs are selectively coupled to said M and N sets of potential lines respectively; wherein said pair of PUs or PDs are selectively encoded and store: B =[[ LOG (said
2
M=4) ]] + [[ LOG (said N=4) ]] = 4 nonvolatile data bits or digits stored for a said
2
differential pair of said latch PUs or PDs.
19. The memory device according to Claim 16, wherein at least said, L = 16 potential lines or M+N = 8+8, sets of potential lines; wherein a said differential said pair of PUs or PDs are selectively coupled to said M & N sets of potential lines respectively; wherein said pair of PUs or PDs are selectively encoded and store: B = [[ LOG (said
2 M=8) ]] + [[ LOG (said N=8) ]] = 6 nonvolatile data bits or digits stored for a said 2
differential pair of said latch PUs or PDs.
20. The memory device according to Claim 16, wherein for each said set of potential lines there is a corresponding 1 to said M and N said SRAM cells respectively each selectively coupled to said 1 to said M and N sets of potential lines, implementing each nonvolatile data said selective encoding.
21 . The memory device according to Claim 16, wherein, wherein said differential pair of said latch PUs or PD device(s) are said N separate, interlocked said contacts.
22. An array of static random access memory (SRAM) cells for storing 1 to 10 bits of single ended, potential line combination, nonvolatile data comprising essentially of complementary, field effect transistor (FET) latch SRAM cells; wherein said latch transistor has positive or negative supply contact such that said SRAM cell has at least N = 1 unshared, separate and interlocked said latch transistor positive or negative supply contact with any of said next neighbor SRAM cells.
PCT/US2015/029530 2014-05-07 2015-05-06 Sram memory cells with 1 to 10 bits of single ended, potential line combination, nonvolatile data WO2015171811A2 (en)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US201461989766P 2014-05-07 2014-05-07
US61/989,766 2014-05-07
US201461992741P 2014-05-13 2014-05-13
US201461992773P 2014-05-13 2014-05-13
US61/992,741 2014-05-13
US61/992,773 2014-05-13
US201461994254P 2014-05-16 2014-05-16
US61/994,254 2014-05-16

Publications (2)

Publication Number Publication Date
WO2015171811A2 true WO2015171811A2 (en) 2015-11-12
WO2015171811A3 WO2015171811A3 (en) 2015-12-30

Family

ID=54392923

Family Applications (4)

Application Number Title Priority Date Filing Date
PCT/US2015/029352 WO2015171683A1 (en) 2014-05-07 2015-05-06 4 bit nonvolatile embedded dram
PCT/US2015/029348 WO2015171680A1 (en) 2014-05-07 2015-05-06 Dram cells storing volatile and nonvolatile data
PCT/US2015/029353 WO2015171684A1 (en) 2014-05-07 2015-05-06 4 bit nonvolatile flash or variable resistance memory
PCT/US2015/029530 WO2015171811A2 (en) 2014-05-07 2015-05-06 Sram memory cells with 1 to 10 bits of single ended, potential line combination, nonvolatile data

Family Applications Before (3)

Application Number Title Priority Date Filing Date
PCT/US2015/029352 WO2015171683A1 (en) 2014-05-07 2015-05-06 4 bit nonvolatile embedded dram
PCT/US2015/029348 WO2015171680A1 (en) 2014-05-07 2015-05-06 Dram cells storing volatile and nonvolatile data
PCT/US2015/029353 WO2015171684A1 (en) 2014-05-07 2015-05-06 4 bit nonvolatile flash or variable resistance memory

Country Status (1)

Country Link
WO (4) WO2015171683A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019066964A1 (en) * 2017-09-29 2019-04-04 Intel Corporation 1s-1c dram with a non-volatile cbram element
CN110266303B (en) * 2019-07-17 2023-04-28 重庆线易电子科技有限责任公司 Refreshing circuit, refreshing method, chip and data transmission system

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4611309A (en) * 1984-09-24 1986-09-09 Advanced Micro Devices, Inc. Non-volatile dynamic RAM cell
US5331188A (en) * 1992-02-25 1994-07-19 International Business Machines Corporation Non-volatile DRAM cell
JP2846822B2 (en) * 1994-11-28 1999-01-13 モトローラ株式会社 Non-volatile memory having multi-bit-capable cells having two-layer floating gate structure and method of programming the same
JP3863330B2 (en) * 1999-09-28 2006-12-27 株式会社東芝 Nonvolatile semiconductor memory
US6556487B1 (en) * 2000-09-20 2003-04-29 Cypress Semiconductor Corp. Non-volatile static memory cell
US7031182B2 (en) * 2000-11-28 2006-04-18 Beigel Michael L Rectifying charge storage memory circuit
US6404686B1 (en) * 2001-01-26 2002-06-11 International Business Machines Corporation High performance, low cell stress, low power, SOI CMOS latch-type sensing method and apparatus
US6574134B1 (en) * 2002-01-18 2003-06-03 Macronix International Co., Ltd. Non-volatile ferroelectric capacitor memory circuit having nondestructive read capability
US6917078B2 (en) * 2002-08-30 2005-07-12 Micron Technology Inc. One transistor SOI non-volatile random access memory cell
DE10361718A1 (en) * 2003-08-22 2005-03-17 Hynix Semiconductor Inc., Ichon Apparatus and method for controlling nonvolatile DRAM
US7164608B2 (en) * 2004-07-28 2007-01-16 Aplus Flash Technology, Inc. NVRAM memory cell architecture that integrates conventional SRAM and flash cells
US7391642B2 (en) * 2005-01-25 2008-06-24 Intel Corporation Multilevel programming of phase change memory cells
JP2006294103A (en) * 2005-04-07 2006-10-26 Matsushita Electric Ind Co Ltd Semiconductor memory apparatus
US7292485B1 (en) * 2006-07-31 2007-11-06 Freescale Semiconductor, Inc. SRAM having variable power supply and method therefor
US8159868B2 (en) * 2008-08-22 2012-04-17 Zeno Semiconductor, Inc. Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating
US7839672B1 (en) * 2006-12-18 2010-11-23 Marvell International Ltd. Phase change memory array circuits and methods of manufacture
US8391078B2 (en) * 2008-02-12 2013-03-05 Chip Memory Technology, Inc. Method and apparatus of operating a non-volatile DRAM
US7885110B2 (en) * 2008-03-25 2011-02-08 Rao G R Mohan Random access memory with CMOS-compatible nonvolatile storage element and parallel storage capacitor
JP5044586B2 (en) * 2009-02-24 2012-10-10 株式会社東芝 Semiconductor memory device
US8116149B2 (en) * 2009-04-14 2012-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Circuit and method for small swing memory signals
US8370709B2 (en) * 2009-04-16 2013-02-05 Micron Technology, Inc. Multiple-level memory cells and error detection
US8536029B1 (en) * 2012-06-21 2013-09-17 International Business Machines Corporation Nanowire FET and finFET

Also Published As

Publication number Publication date
WO2015171683A1 (en) 2015-11-12
WO2015171684A1 (en) 2015-11-12
WO2015171680A1 (en) 2015-11-12
WO2015171811A3 (en) 2015-12-30

Similar Documents

Publication Publication Date Title
US10672467B2 (en) High voltage switching circuitry for a cross-point array
US20180144790A1 (en) Semiconductor device
JP5146695B2 (en) Semiconductor memory device
US8665637B2 (en) Semiconductor memory
US7852661B2 (en) Write-assist SRAM cell
US7957176B2 (en) Semiconductor memory device with improved resistance to disturbance and improved writing characteristic
JPH10208481A (en) Low voltage cmossram
JP2004259352A (en) Semiconductor storage device
WO2009138739A2 (en) Source controlled sram
CN110047534B (en) Memory device associated with SRAM memory plane and nonvolatile memory plane hardened for accidental flip
WO2010137198A1 (en) Semiconductor memory device
US20100208512A1 (en) Semiconductor memory device provided with resistance change element
CN106558334B (en) SRAM memory cell, SRAM memory and control method thereof
JP2005276315A (en) Method for using semiconductor integrated circuit and semiconductor integrated circuit
WO2015171811A2 (en) Sram memory cells with 1 to 10 bits of single ended, potential line combination, nonvolatile data
US10062419B2 (en) Digtial circuit structures
US10395700B1 (en) Integrated level translator
US20150310909A1 (en) Optimization of circuit layout area of a memory device
JP2009026376A (en) Storage circuit
TWI805219B (en) Non-volatile static random access memory
CN117995243A (en) Eflash bit line driving circuit and memory chip

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15789622

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15789622

Country of ref document: EP

Kind code of ref document: A2