WO2015170845A1 - Low-voltage differential signalling transmitter - Google Patents

Low-voltage differential signalling transmitter Download PDF

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Publication number
WO2015170845A1
WO2015170845A1 PCT/KR2015/004147 KR2015004147W WO2015170845A1 WO 2015170845 A1 WO2015170845 A1 WO 2015170845A1 KR 2015004147 W KR2015004147 W KR 2015004147W WO 2015170845 A1 WO2015170845 A1 WO 2015170845A1
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WIPO (PCT)
Prior art keywords
voltage
pull
driving
switching element
terminal
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PCT/KR2015/004147
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French (fr)
Korean (ko)
Inventor
김태우
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(주) 픽셀플러스
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Priority to CN201580026933.0A priority Critical patent/CN106416077B/en
Publication of WO2015170845A1 publication Critical patent/WO2015170845A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements

Definitions

  • the present invention relates to low voltage differential signal transmitters and, more particularly, to low voltage differential signal transmitters having an output resistance characteristic insensitive to process variations.
  • a video display device receives a video signal (Audio / Video signal) from airwaves, cables, and other external devices (VCR, DVD, etc.), processes the video signal to output the video signal, and processes the video signal to the video signal processing main body. It is composed of a display panel (Display pannel) for displaying the displayed image on the screen. In this case, the display panel and the image signal processing main body may be formed in one piece, or may be separately separated from each other.
  • the display panel and the video signal processing body generally transmit video signals using a Low Voltage Differential Signal (LVDS) interface.
  • the LVDS interface is a transmission method for sending digital information to a flat panel display at high speed through copper wire.
  • low voltage (LV) that is, low voltage means that the LVDS uses a voltage lower than the standard voltage.
  • the LVDS interface is in the spotlight as a solution for such high-speed data transmission.
  • LVDS interfaces are widely used in laptop computers because fewer wires can be used between the motherboard and the panel.
  • this technology is being used between the image scaler and the panel of a large number of self-contained flat panel displays.
  • LVDS interface method is more noise-resistant than conventional single-ended signal method, easier signal termination than pECL (pseudo-emitter coupled logic) signal, and high speed transmission and reception of Gbps or more. This is a possible serial communication method.
  • the LVDS interface uses a low voltage, an electromagnetic interference (EMI) is reduced and power consumption is reduced. Due to these advantages, the LVDS interface is applied to various fields such as data transfer between boards as well as data transfer between boards.
  • EMI electromagnetic interference
  • the present invention has been made to solve the above-mentioned conventional problems, and an object thereof is to enable a low voltage differential signal transmitter to have an output resistance characteristic insensitive to process changes.
  • a low voltage differential signal transmitter includes a plurality of pre-drivers, and drives a positive input signal and a negative input signal to drive a plurality of drive signals having a pull-up voltage level and a plurality of drive signals having a pull-down voltage level.
  • An input driver for outputting a;
  • a voltage generator for regulating a power supply voltage to generate a first driving voltage;
  • a plurality of switching elements selectively turned on by the plurality of driving signals, wherein the first driving voltage is selectively supplied to the differential output stage, and the turn-on resistances of the plurality of switching elements are controlled by the pull-up voltage level and the pull-down voltage level.
  • a main drive to be adjusted.
  • the present invention prevents the reflection of a signal that may occur while the transmission speed of the signal increases at high speed by matching the characteristic with the characteristic impedance of the transmission line so as not to be affected by the variation of the semiconductor manufacturing process, and transmits a signal without distortion. Provide the effect of doing so.
  • FIG. 1 is a conceptual diagram of a low voltage differential signal transmitter according to an embodiment of the present invention.
  • FIG. 2 is a detailed circuit diagram of the transmitter of FIG.
  • FIG. 3 is a detailed block diagram of the pull-up control unit of FIG.
  • FIG. 4 is a detailed block diagram of the pull-down control unit of FIG.
  • FIG. 5 is another embodiment of the transmitter of FIG.
  • FIG. 6 is a detailed configuration diagram of the pull-up control unit of FIG. 5.
  • FIG. 6 is a detailed configuration diagram of the pull-up control unit of FIG. 5.
  • FIG. 7 is a detailed configuration diagram illustrating the pull-down control unit of FIG. 5.
  • FIG. 7 is a detailed configuration diagram illustrating the pull-down control unit of FIG. 5.
  • FIG. 8 is an operation timing diagram relating to the transmitter of FIG.
  • FIG. 1 is a conceptual diagram of a low voltage differential signal transmitter according to an embodiment of the present invention.
  • the low voltage differential signal transmitter is a circuit capable of high speed operation, low current consumption, and low electromagnetic interference (EMI).
  • the low voltage differential signal transmitter has a high speed such as an image sensor, a liquid crystal display driver chip (LDI: LCD driver IC), and communication. It is used in the field requiring data transmission.
  • LDM liquid crystal display driver chip
  • the low voltage differential signal transmitter includes a transmitter 100, a transmission line 200, a receiver 300, and termination resistors 400 and 500.
  • the transmitter 100 receives data through an input terminal.
  • Data input to the transmitter 100 is transmitted to the receiver 300 in a differential manner through the transmission line 200.
  • the potential difference between the two transmission paths is generated based on the data input through the transmitter 100, thereby generating a differential signal.
  • the receiver 300 converts the differential signal received through the transmission line 200 to a CMOS level and outputs it through an output terminal.
  • Each transmission line 200 has the same electrical characteristics, and forms a balanced transmission path so that one signal can be transmitted through two transmission paths.
  • a termination resistor 400 is connected to an input terminal of the receiver 300.
  • a termination resistor 500 for impedance matching may be additionally connected to the output terminal side of the transmitter 100.
  • FIG. 2 is a detailed circuit diagram of the transmitter 100 of FIG. 1.
  • the transmitter 100 includes an input driver 110, a voltage generator 120, a main driver 130, and differential output terminals DN and DP.
  • the input driver 110 includes a plurality of pre-drivers D1 to D4.
  • the pre-drivers D1 and D3 are drivers for driving the pull-up end of the main driver 130, and the pre-drivers D2 and D4 are drivers for driving the pull-down end of the main driver 130.
  • the pre-driver D1 pre-drives the positive input signal INP to the pull-up voltage Vrup to generate the driving voltage VP1.
  • the pre-driver D2 pre-drives the positive input signal INP to the pull-down voltage Vrdn to generate the driving voltage VP2.
  • the pre-driver D3 pre-drives the negative input signal INN to the pull-up voltage Vrup to generate the driving voltage VN1.
  • the pre-driver D4 pre-drives the negative input signal INN to the pull-down voltage Vrdn to generate the driving voltage VN2.
  • the pre-drivers D1 and D3 are driven by the pull-up voltage Vrup, and the pre-drivers D2 and D4 are driven by the pull-down voltage Vrdn.
  • the voltage generator 120 generates the driving voltage Vreg of the main driver 130 by regulating the power supply voltage VDD.
  • the voltage generator 120 supplies the generated driving voltage Vreg to the switching elements M1 and M2 of the main driver 130.
  • the main driver 130 includes a plurality of switching elements M1 to M4.
  • the switching elements M1 to M4 may be formed of field effect transistors (FETs).
  • the switching elements M1 and M3 are connected in series between the application terminal of the driving voltage Vreg and the ground GND voltage terminal.
  • the driving voltage VP1 is applied to the switching element M1 through the gate terminal
  • the driving voltage VN2 is applied to the switching element M3 through the gate terminal.
  • the switching elements M2 and M4 are connected in series between the application terminal of the driving voltage Vreg and the ground GND voltage terminal.
  • the driving voltage VN1 is applied to the switching element M2 through the gate terminal
  • the driving voltage VP2 is applied to the switching element M4 through the gate terminal.
  • the number of pre-drivers D1 to D4 corresponds to the number of switching elements M1 to M4 provided in the main driver 130. That is, the pre-drivers D1 to D4 individually drive control the switching elements M1 to M4. When the number of switching elements M1 to M4 is changed, the number of switching elements M1 to M4 may be changed to correspond to the number of pre-drivers D1 to D4.
  • the common connection node of the switching elements M1 and M3 is connected to the differential output terminal DP, and the common connection node of the switching elements M2 and M4 is connected to the differential output terminal DN.
  • the differential output terminals DN and DP are connected to the transmission line 200.
  • the turn-on resistance of the switching elements M1 to M4 becomes the output resistance of the transmitter 100.
  • the turn-on resistance of the switching elements M1 to M4 is determined by the pullup voltage Vrup and the pulldown voltage Vrdn.
  • the transmitter 100 having such a configuration individually adjusts output voltages VP1, VP2, VN1 and VN2 of the pre-drivers D1 to D4 for driving the switching elements M1 to M4 provided in the main driver 130. Accordingly, the turn-on resistance of the switching elements M1 to M4 of the main driver 130 can be kept constant.
  • the switching elements M1 and M4 are turned on. Then, the driving voltage Vreg output from the voltage generator 120 is output to the differential output terminal DP through the switching element M1.
  • the output signal of the differential output terminal DP is input to the differential output terminal DN through the termination resistor 400 through the transmission line 200 and output to the ground voltage GND terminal through the switching element M4.
  • the driving voltages VN1 and VN2 have polarities opposite to those of the driving voltages VP1 and VP2.
  • the driving voltages VP1 and VP2 are high, the driving voltages VN1 and VN2 are turned low, and the switching elements M2 and M3 are turned off.
  • the switching elements M2 and M3 are turned on. Accordingly, the driving voltage Vreg is output to the differential output terminal DN through the switching element M2.
  • the output signal of the differential output terminal DN is input to the differential output terminal DP via the termination resistor 400 through the transmission line 200 and output to the ground voltage GND terminal through the switching element M3.
  • the current flowing from the driving voltage Vreg to the ground voltage GND becomes (Vreg-GND) / ((M2 turn-on resistance) + (termination resistor) + (M3 turn-on resistance)).
  • this current is called Iref
  • the voltage across the differential output DN becomes Vreg-Iref * (M2 turn-on resistance) and the voltage across the differential output DP is GND + Iref * (M3 turn-on resistance).
  • the driving voltages VN1 and VN2 are high, the driving voltages VP1 and VP2 are turned low so that the switching elements M1 and M4 are turned off.
  • FIG. 3 is a detailed block diagram of the pull-up control unit 111 of FIG. 2.
  • the pull-up control unit 111 generates the pull-up voltage Vrup supplied to the pre-drivers D1 and D3.
  • the pull-up control unit 111 includes a high voltage generator 112, a voltage generator 113, an amplifier 114, a constant current source 115, a switching element M5, and a pull-up voltage generator PU.
  • the high voltage generator 112 generates a high voltage Vhigh corresponding to the power supply voltage VDD and supplies it to the amplifier 114.
  • the voltage generator 113 generates the driving voltage Vreg2 by regulating the power supply voltage VDD and supplies it to the switching element M5.
  • the driving voltage Vreg2 may have the same voltage level as the driving voltage Vreg.
  • the amplifier 114 outputs the pull-up driving signal VPU by comparing and amplifying the high voltage Vhigh and the feedback voltage Vfeedh in response to the power supply voltage VDD. That is, the amplifier 114 receives the high voltage Vhigh through the positive input terminal and the feedback voltage Vfeedh through the negative input terminal.
  • the constant current source 115 is connected between the switching element M5 and the ground GND voltage terminal, so that the constant current Iref corresponding to the feedback voltage Vfeedh flows.
  • the pull-up voltage generation unit PU regulates the pull-up driving signal VPU in response to the power supply voltage VDD to generate a pull-up voltage Vrup and supplies it to the pre-drivers D1 and D3.
  • the switching element M5 is connected between the driving voltage Vreg2 applying terminal and the constant current source 115 to receive the pull-up driving signal VPU through the gate terminal.
  • the switching element M5 is a replica having the same size and the same layout as the switching elements M1 and M2 of FIG. 2. Here, it is assumed that the switching elements M1 and M2 have the same size and the same layout.
  • the gain (DC gain) of the amplifier 114 is sufficiently large (for example, 60 dB or more)
  • the level of the pull-up drive signal VPU is adjusted so that the feedback voltage Vfeedh is equal to the value of the high voltage Vhigh.
  • the turn on resistance of the switching element M5 becomes (Vreg2-Vhigh) / Iref.
  • the pull-up voltage generator PU generates the pull-up voltage Vrup by regulating the adjusted pull-up driving signal VPU.
  • the pull-up voltage generator PU supplies the generated pull-up voltage Vrup to power of the pre-drivers D1 and D3.
  • the pre-drivers D1 and D3 receiving the pull-up voltage Vrup as the power supply voltage control the driving of the switching elements M1 and M2 according to the driving voltages VP1 and VN1.
  • the high state voltages of the driving voltages VP1 and VN1 become the pull-up voltage Vrup level.
  • the turn-on resistance value when the pull-up voltage Vrup is applied to the switching elements M1 and M2 of the main driver 130 is the same as the turn-on resistance value of the switching element M5, resulting in (Vreg2-Vhigh) / Iref.
  • the driving voltage Vreg2 preferably has a voltage level higher than the high voltage Vhigh.
  • the switching element M1 by the high voltage Vhigh and the constant current source 115 generated based on the switching element M5, the amplifier 114, and the band gap voltage corresponding to the process change of the switching elements M1 and M2. Since the level of the pullup voltage Vrup is adjusted so that the output resistance of M2 is constant, the turn-on resistance values of the switching elements M1 and M2 are not affected by the process change.
  • FIG. 4 is a detailed configuration diagram illustrating the pull-down control unit 116 of FIG. 2.
  • the pulldown control unit 116 generates a pulldown voltage Vrdn supplied to the pre drivers D2 and D4.
  • the pull-down controller 116 includes a low voltage generator 117, an amplifier 118, a constant current source 119, a switching element M6, and a pull-down voltage generator PD.
  • the low voltage generator 117 generates the low voltage Vlow in response to the power supply voltage VDD and supplies it to the amplifier 118.
  • the amplifier 118 compares and amplifies the low voltage Vlow and the feedback voltage Vfeedl in response to the power supply voltage VDD, and outputs a pull-down driving signal VPD. That is, the amplifier 118 receives the low voltage Vlow through the negative input terminal and the feedback voltage Vfeedl through the positive input terminal.
  • the constant current source 119 is connected between the supply voltage VDD applying stage and the switching element M6 so that the constant current Iref corresponding to the feedback voltage Vfeedl flows.
  • the pull-down voltage generator PD generates a pull-down voltage Vrdn by regulating the pull-down driving signal VPD in response to the power supply voltage VDD and supplies it to the pre-drivers D2 and D4.
  • the switching element M6 is connected between the constant current source 119 and the ground GND voltage terminal, and the pull-down driving signal VPD is applied through the gate terminal.
  • the switching element M6 is a replica having the same size and the same layout as the switching elements M3 and M4 of FIG. 2. Here, it is assumed that the switching elements M3 and M4 have the same size and the same layout.
  • the gain (DC gain) of the amplifier 118 is sufficiently large (for example, 60 dB or more), the level of the pull-down drive signal VPD is adjusted so that the feedback voltage Vfeedl is equal to the value of the low voltage Vlow. At this time, the turn on resistance of the switching element M6 becomes Vlow / Iref.
  • the pull-down voltage generator PD generates the pull-down voltage Vrdn by regulating the adjusted pull-down driving signal VPD.
  • the pull-down voltage generator PD supplies the generated pull-down voltage Vrdn to power of the pre-drivers D2 and D4.
  • the pre-drivers D2 and D4 which receive the pull-down voltage Vrdn as the power supply voltage, control the driving of the switching elements M3 and M4 according to the driving voltages VP2 and VN2. In other words, the high state voltages of the driving voltages VP2 and VN2 become the pull-down voltage Vrdn level.
  • the turn-on resistance value when the pull-down voltage Vrdn is applied to the switching elements M3 and M4 of the main driver 130 is the same as the turn-on resistance value of the switching element M6, resulting in Vlow / Iref.
  • 5 is another embodiment of the transmitter 100 of FIG.
  • the transmitter 100_1 includes an input driver 110_1, a voltage generator 120_1, a main driver 130_1, and differential output terminals DN and DP. 5 has the same structure as the embodiment of FIG. However, it is different from FIG. 2 in that the main driver 130_1 includes resistors R1 to R4 for preventing electrostatic discharge (ESD).
  • ESD electrostatic discharge
  • a resistor R1 is connected between the switching element M1 and the differential output terminal DP.
  • a resistor R2 is connected between the switching element M2 and the differential output terminal DN.
  • a resistor R3 is connected between the switching element M3 and the differential output terminal DP.
  • a resistor R4 is connected between the switching element M4 and the differential output terminal DN. That is, the resistors R2 and R4 are connected between the differential output terminal DN and the switching elements M2 and M4, and the resistors R1 and R3 are connected between the differential output terminal DP and the switching elements M1 and M3.
  • the differential output terminals DP and DN are interfaces that connect the inside and the outside of the semiconductor chip, which may cause electrostatic discharge (ESD) problems in the differential output terminals DP and DN.
  • ESD electrostatic discharge
  • the resistors R1 to R4 are connected to the differential output terminals DP and DN connected to the transmission line 200.
  • the sum of the turn-on resistances of the switching elements M1 to M4 and the resistances of the resistors R1 to R4 becomes the output resistance of the transmitter 100_1.
  • the turn-on resistance of the switching elements M1 to M4 is determined by the pullup voltage Vrup and the pulldown voltage Vrdn.
  • the voltage across the differential output terminals DP, DN and the constant current sources 115 and 119 is the resistance value of the resistors R1 to R4 for the ESD of the main driver 130_1 to the transistor turn on resistances of the switching elements M1 to M4.
  • FIG. 6 is a detailed block diagram of the pull-up control unit 111_1 of FIG. 5.
  • FIG. 6 has the same structure as that in FIG. 3, but differs from FIG. 3 in that a resistor R5 is further provided between the switching element M5 and the constant current source 115.
  • the gain (DC gain) of the amplifier 114 is sufficiently large (for example, 60 dB or more)
  • the level of the pull-up drive signal VPU is adjusted so that the feedback voltage Vfeedh is equal to the value of the high voltage Vhigh.
  • the sum of the turn on resistance of the switching element M5 and the resistance R5 becomes (Vreg2-Vhigh) / Iref.
  • the pull-up voltage generator PU generates the pull-up voltage Vrup by regulating the adjusted pull-up driving signal VPU.
  • the pull-up voltage generator PU supplies the generated pull-up voltage Vrup to power of the pre-drivers D1 and D3.
  • the pre-drivers D1 and D3 receiving the pull-up voltage Vrup as the power supply voltage control the driving of the switching elements M1 and M2 according to the driving voltages VP1 and VN1.
  • the high state voltages of the driving voltages VP1 and VN1 become the pull-up voltage Vrup level.
  • the driving voltage Vreg2 preferably has a voltage level higher than the high voltage Vhigh.
  • the high voltage Vhigh and the constant current source generated based on the switching element M5, the resistor R5, the amplifier 114, and the bandgap voltage are copied in response to the process change of the switching elements M1, M2 and the resistors R1, R2.
  • the level of the pull-up voltage Vrup is adjusted so that the turn-on resistances of the switching elements M1 and M2 and the sum of the resistors R1 and R2 are constant, so the sum of the turn-on resistances of the switching elements M1 and M2 and the resistors R1 and R2 is processed. It is not affected by change.
  • FIG. 7 is a detailed configuration diagram illustrating the pull-down control unit 116_1 of FIG. 5.
  • FIG. 7 has the same structure as that of FIG. 4, it is different from FIG. 4 to further include a resistor R6 between the switching element M6 and the constant current source 119.
  • the gain (DC gain) of the amplifier 118 is sufficiently large (for example, 60 dB or more), the level of the pull-down drive signal VPD is adjusted so that the feedback voltage Vfeedl is equal to the value of the low voltage Vlow. At this time, the sum of the turn on resistance of the switching element M6 and the resistor R6 becomes Vlow / Iref.
  • the pull-down voltage generator PD generates the pull-down voltage Vrdn by regulating the adjusted pull-down driving signal VPD.
  • the pull-down voltage generator PD supplies the generated pull-down voltage Vrdn to power of the pre-drivers D2 and D4.
  • the pre-drivers D2 and D4 which receive the pull-down voltage Vrdn as the power supply voltage, control the driving of the switching elements M3 and M4 according to the driving voltages VP2 and VN2. In other words, the high state voltages of the driving voltages VP2 and VN2 become the pull-down voltage Vrdn level.
  • the pull-down voltage Vrdn When the pull-down voltage Vrdn is applied to the switching elements M3 and M4 of the main driver 130, the sum of the turn-on resistance and the resistors R3 and R4 is equal to the sum of the turn-on resistance and the resistance R6 of the switching element M6, and thus Vlow / It becomes Iref.
  • the low voltage Vlow and the constant current source generated based on the switching element M6, the resistor R6, the amplifier 118, and the bandgap voltage are copied in response to the process change of the switching elements M3, M4 and the resistors R3, R4.
  • the level of the pull-down voltage Vrdn is adjusted so that the turn-on resistance of the switching elements M3 and M4 and the sum of the resistors R3 and R4 are constant by 119, the sum of the turn-on resistance of the switching elements M3 and M4 and the resistors R3 and R4 is processed. It is not affected by change.
  • 8 is an operation timing diagram for the transmitter 100 according to the embodiment of the present invention.
  • the positive input signal INP and the negative input signal INN swing between the power supply voltage VDD and the ground voltage GND level.
  • the positive input signal INP and the negative input signal INN have opposite phases.
  • the driving voltages VP1 and VN1 swing between the level of the pullup voltage Vrup and the ground voltage GND.
  • the driving voltages VP2 and VN2 swing between the pull-down voltage Vrdn and the ground voltage GND.
  • the driving voltages VP1 and VP2 have phases opposite to those of the driving voltages VN1 and VN2.
  • the differential output stages DN and DP which are outputs of the transmitter 100, swing between the levels of the high voltage Vhigh and the low voltage Vlow.
  • the high voltage Vhigh is Vreg-Iref * (M1 turn on resistance) or Vreg-Iref * (M2 trun on resistance).
  • the low voltage Vlow becomes GND + Iref * (M4 turn-on resistor) or GND + Iref * (M3 turn-on resistor).
  • GND is 0V
  • the low voltage Vlow is either Iref * (M4 turn on resistance) or Iref * (M3 turn on resistance).
  • the MIPI Mobile Industry Processor Interface
  • LCD driver ICs LCD driver ICs
  • image sensors for mobile phones
  • the termination resistor 300 uses 100 ohms.
  • the current Iref should be 2 mA and the turn-on resistance of each transistor M1-M4 should be 50 ohm, and the characteristic impedance matching of the transmission line 200 is also satisfied. Done. At this time, the output resistance of the transmitter 100 is 50 ohm.
  • the sum of the turn-on resistance of each transistor M1 to M4 and the resistance R for ESD should be 50 ohm.
  • the turn-on resistance of the transistors M1 to M4 or the resistance R for ESD are highly dependent on the variation in the semiconductor manufacturing process, and thus the output resistance of the transmitter 100 when a variation occurs in the semiconductor manufacturing process. Will affect directly.
  • the output resistance specifications are as low as 40 ohms and as high as 62.5 ohms.
  • the characteristic impedance matching of the transmission line 200 may not be properly performed, thereby causing reflection in the signal transmission, causing distortion in the signal transmitted at a higher speed.
  • the switching elements M1 to M4 and the resistors R1 to R4 for the ESD are generated based on the copies M5, M6, resistors R5, R6 and the bandgap voltage.
  • the level of the pull-up voltage Vrup and the pull-down voltage Vrdn is controlled by the high voltage Vhigh, the low voltage Vlow and the constant current sources 115 and 119 and the amplifiers 114 and 118, so that the turn-on resistance values of the switching elements M1 to M4, or R to R4 The sum will not be affected by process changes.

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Abstract

The present invention relates to a low-voltage differential signalling transmitter, more particularly to the technology that enables the low-voltage differential transmitter to have output resistance characteristics that are insensitive to process variation. The present invention comprises: an input drive unit comprising a plurality of pre-drivers for outputting a plurality of drive signals having a pull-up voltage level by driving positive input signals and negative input signals, and a plurality of drive signals having a pull-down voltage level; a voltage generator for regulating a power supply voltage and generating a first drive voltage; and a main drive unit comprising a plurality of switching devices that are selectively turned on by the plurality of drive signals to selectively supply the first drive voltage to a differential output terminal, wherein the turn-on resistance of the plurality of switching devices is controlled by the pull-up voltage level and the pull-down voltage level.

Description

저전압 차동 신호 전송기Low voltage differential signal transmitter
본 발명은 저전압 차동 신호 전송기에 관한 것으로서, 특히, 저전압 차동 신호 전송기가 공정 변화에 둔감한 출력저항 특성을 가질 수 있도록 하는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to low voltage differential signal transmitters and, more particularly, to low voltage differential signal transmitters having an output resistance characteristic insensitive to process variations.
일반적으로 영상디스플레이장치는 공중파, 케이블 및 기타 외부 장치(VCR, DVD 등)로부터 영상신호(Audio/Video signal)를 수신하고, 이를 영상 처리하여 출력하는 영상신호처리 본체와, 영상신호처리 본체에서 처리된 영상을 화면에 디스플레이시키는 디스플레이 패널(Display pannel)로 구성된다. 이때, 디스플레이 패널과 영상신호처리 본체는, 일체형으로 구성될 수도 있으며, 각각 개별적으로 분리되어 구성될 수 있다.In general, a video display device receives a video signal (Audio / Video signal) from airwaves, cables, and other external devices (VCR, DVD, etc.), processes the video signal to output the video signal, and processes the video signal to the video signal processing main body. It is composed of a display panel (Display pannel) for displaying the displayed image on the screen. In this case, the display panel and the image signal processing main body may be formed in one piece, or may be separately separated from each other.
또한, 디스플레이 패널과 영상신호처리 본체는 일반적으로 저전압 차동 신호(Low Voltage Differential Signal : LVDS) 인터페이스를 이용하여 영상신호를 전송한다. LVDS 인터페이스라 함은 디지털 정보를 구리선을 통해 고속으로 평판 디스플레이에 보내기 위한 전송 방법이다. 여기서, LV(low voltage) 즉, 저전압이라는 것은 LVDS가 표준 전압보다 낮은 전압을 사용한다는 의미이다. In addition, the display panel and the video signal processing body generally transmit video signals using a Low Voltage Differential Signal (LVDS) interface. The LVDS interface is a transmission method for sending digital information to a flat panel display at high speed through copper wire. Here, low voltage (LV), that is, low voltage means that the LVDS uses a voltage lower than the standard voltage.
최근 고속 데이터 생성 및 처리에 대한 요구가 증대됨에 따라, 한 지점에서 다른 지점으로 데이터를 전송하는 능력이 전체 시스템 성능을 판가름하는 척도가 되고 있다. 이러한 고속 데이터 전송을 위한 솔루션으로 LVDS 인터페이스가 각광받고 있다.As the demand for high-speed data generation and processing in recent years has increased, the ability to transfer data from one point to another has become a measure of overall system performance. The LVDS interface is in the spotlight as a solution for such high-speed data transmission.
이러한 LVDS 인터페이스는 마더보드와 패널 사이에서 보다 적은 수의 전선이 사용될 수 있기 때문에 랩 탑 컴퓨터에서 광범위하게 사용된다. 또한, 이 기술은 많은 수의 자립형 평판 디스플레이의 이미지 스케일러와 패널 사이에서도 사용되고 있는 실정이다.These LVDS interfaces are widely used in laptop computers because fewer wires can be used between the motherboard and the panel. In addition, this technology is being used between the image scaler and the panel of a large number of self-contained flat panel displays.
LVDS 인터페이스 방식은 기존의 싱글 엔드 신호(Single-Ended Signal)를 이용한 방법보다 잡음에 강하고, pECL(pseudo-Emitter Coupled Logic) 신호를 이용한 방법보다 신호 종단 처리(Signal Termiantion)가 쉽고, Gbps 이상의 초고속 송수신이 가능한 직렬 통신(Serial Communication) 방법이다.LVDS interface method is more noise-resistant than conventional single-ended signal method, easier signal termination than pECL (pseudo-emitter coupled logic) signal, and high speed transmission and reception of Gbps or more. This is a possible serial communication method.
또한, LVDS 인터페이스는 낮은 전압을 사용하기 때문에 전자파 장애(Electro Magnetic Interference :EMI)가 줄어들고, 소비 전력이 감소한다는 장점이 있다. 이러한 장점으로 인하여 LVDS 인터페이스는 칩(Chip) 간 데이터 전송뿐만 아니라, 보드(Board) 간 데이터 전송 등 다양한 분야에 적용되고 있다.In addition, since the LVDS interface uses a low voltage, an electromagnetic interference (EMI) is reduced and power consumption is reduced. Due to these advantages, the LVDS interface is applied to various fields such as data transfer between boards as well as data transfer between boards.
본 발명은 전술한 종래의 문제점을 해결하기 위하여 창출된 것으로, 저전압 차동 신호 전송기가 공정 변화에 둔감한 출력저항 특성을 가질 수 있도록 하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object thereof is to enable a low voltage differential signal transmitter to have an output resistance characteristic insensitive to process changes.
본 발명의 실시예에 따른 저전압 차동 신호 전송기는, 복수의 프리 드라이버를 포함하고, 정입력신호와 부입력신호를 구동하여 풀업전압 레벨을 갖는 복수의 구동신호와 풀다운전압 레벨을 갖는 복수의 구동신호를 출력하는 입력 구동부; 전원전압을 레귤레이팅하여 제 1구동전압을 생성하는 전압 발생기; 및 복수의 구동신호에 의해 선택적으로 턴 온 되는 복수의 스위칭 소자를 포함하여 제 1구동전압을 차동 출력단에 선택적으로 공급하고, 복수의 스위칭 소자의 턴 온 저항이 풀업 전압 레벨과 풀다운전압 레벨에 의해 조정되는 메인 구동부를 포함하는 것을 특징으로 한다. A low voltage differential signal transmitter according to an embodiment of the present invention includes a plurality of pre-drivers, and drives a positive input signal and a negative input signal to drive a plurality of drive signals having a pull-up voltage level and a plurality of drive signals having a pull-down voltage level. An input driver for outputting a; A voltage generator for regulating a power supply voltage to generate a first driving voltage; And a plurality of switching elements selectively turned on by the plurality of driving signals, wherein the first driving voltage is selectively supplied to the differential output stage, and the turn-on resistances of the plurality of switching elements are controlled by the pull-up voltage level and the pull-down voltage level. And a main drive to be adjusted.
본 발명은 전송선로의 특성 임피던스와의 정합(Matching) 특성이 반도체 제조 공정의 편차에 영향을 받지 않도록 하여 신호의 전송 속도가 고속으로 가면서 발생할 수 있는 신호의 반사를 방지하고 왜곡 없는 신호를 전송할 수 있도록 하는 효과를 제공한다. The present invention prevents the reflection of a signal that may occur while the transmission speed of the signal increases at high speed by matching the characteristic with the characteristic impedance of the transmission line so as not to be affected by the variation of the semiconductor manufacturing process, and transmits a signal without distortion. Provide the effect of doing so.
아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.
도 1은 본 발명의 실시예에 따른 저전압 차동 신호 전송기에 관한 개념도. 1 is a conceptual diagram of a low voltage differential signal transmitter according to an embodiment of the present invention.
도 2는 도 1의 송신기에 관한 상세 회로도. 2 is a detailed circuit diagram of the transmitter of FIG.
도 3은 도 2의 풀업 제어부에 관한 상세 구성도. 3 is a detailed block diagram of the pull-up control unit of FIG.
도 4는 도 2의 풀다운 제어부에 관한 상세 구성도. 4 is a detailed block diagram of the pull-down control unit of FIG.
도 5는 도 1의 송신기에 관한 다른 실시예. 5 is another embodiment of the transmitter of FIG.
도 6은 도 5의 풀업 제어부에 관한 상세 구성도. FIG. 6 is a detailed configuration diagram of the pull-up control unit of FIG. 5. FIG.
도 7은 도 5의 풀다운 제어부에 관한 상세 구성도. FIG. 7 is a detailed configuration diagram illustrating the pull-down control unit of FIG. 5. FIG.
도 8은 도 1의 송신기에 관한 동작 타이밍도.8 is an operation timing diagram relating to the transmitter of FIG.
이하, 첨부한 도면을 참조하여 본 발명의 실시예에 대해 상세히 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.
도 1은 본 발명의 실시예에 따른 저전압 차동 신호 전송기에 관한 개념도이다. 1 is a conceptual diagram of a low voltage differential signal transmitter according to an embodiment of the present invention.
저전압 차동 신호 전송기는 고속 동작이 가능하고 낮은 전류 소모 및 낮은 전자기적 간섭(EMI : Electromagnetic Interference) 특성을 갖는 회로로서, 이미지 센서, 액정표시장치 구동칩(LDI : LCD Driver IC) 및 통신 등 고속의 데이터 전송을 필요로 하는 분야에서 사용되고 있다.The low voltage differential signal transmitter is a circuit capable of high speed operation, low current consumption, and low electromagnetic interference (EMI). The low voltage differential signal transmitter has a high speed such as an image sensor, a liquid crystal display driver chip (LDI: LCD driver IC), and communication. It is used in the field requiring data transmission.
저전압 차동 신호 전송기는 송신기(100), 전송선로(200), 수신기(300), 터미네이션 저항(400, 500)을 포함한다. The low voltage differential signal transmitter includes a transmitter 100, a transmission line 200, a receiver 300, and termination resistors 400 and 500.
송신기(100)는 입력단자를 통해 데이터를 입력받는다. 송신기(100)로 입력되는 데이터는 전송선로(200)을 통해 차동(Differential)으로 수신기(300) 측으로 전송된다. 송신기(100)를 통해 입력되는 데이터에 기초하여 두 전송로 사이의 전위차를 생성하고 이로써 차동 신호를 생성한다. 그리고, 수신기(300)는 전송선로(200)를 통해 수신된 차동 신호를 CMOS 레벨로 변환하여 출력단자를 통해 출력한다. The transmitter 100 receives data through an input terminal. Data input to the transmitter 100 is transmitted to the receiver 300 in a differential manner through the transmission line 200. The potential difference between the two transmission paths is generated based on the data input through the transmitter 100, thereby generating a differential signal. In addition, the receiver 300 converts the differential signal received through the transmission line 200 to a CMOS level and outputs it through an output terminal.
송신기(100)와 수신기(300)는 전송선로(200)를 통해 연결된다. 각각의 전송선로(200)는 전기적 특성이 동일하며, 평형 전송로를 형성하여 2개의 전송로를 통해 1개의 신호를 전송할 수 있도록 한다. The transmitter 100 and the receiver 300 are connected through the transmission line 200. Each transmission line 200 has the same electrical characteristics, and forms a balanced transmission path so that one signal can be transmitted through two transmission paths.
그리고, 신호의 전송 과정에서 반사를 없애기 위해 전송선로(200)의 임피던스를 정합 시키도록 한다. 이를 위해, 수신기(300)의 입력 단에 터미네이션(Termination) 저항(400)을 연결한다. 또한, 송신기(100)의 출력단 측에 임피던스 정합을 위한 터미네이션(Termination) 저항(500)을 추가 적으로 연결할 수도 있다.And, in order to eliminate the reflection in the transmission process of the signal to match the impedance of the transmission line 200. To this end, a termination resistor 400 is connected to an input terminal of the receiver 300. In addition, a termination resistor 500 for impedance matching may be additionally connected to the output terminal side of the transmitter 100.
도 2는 도 1의 송신기(100)에 관한 상세 회로도이다. FIG. 2 is a detailed circuit diagram of the transmitter 100 of FIG. 1.
송신기(100)는 입력 구동부(110), 전압 발생기(120), 메인 구동부(130) 및 차동 출력단 DN, DP를 포함한다. The transmitter 100 includes an input driver 110, a voltage generator 120, a main driver 130, and differential output terminals DN and DP.
여기서, 입력 구동부(110)는 복수의 프리 드라이버 D1~D4를 포함한다. 프리 드라이버 D1, D3은 메인 구동부(130)의 풀업단을 구동하기 위한 구동부이고, 프리 드라이버 D2, D4는 메인 구동부(130)의 풀다운단을 구동하기 위한 구동부이다. Here, the input driver 110 includes a plurality of pre-drivers D1 to D4. The pre-drivers D1 and D3 are drivers for driving the pull-up end of the main driver 130, and the pre-drivers D2 and D4 are drivers for driving the pull-down end of the main driver 130.
프리 드라이버 D1는 정입력신호 INP를 풀업전압 Vrup으로 프리 구동하여 구동전압 VP1을 생성한다. 프리 드라이버 D2는 정입력신호 INP를 풀다운전압 Vrdn으로 프리 구동하여 구동전압 VP2을 생성한다. 프리 드라이버 D3는 부입력신호 INN를 풀업전압 Vrup으로 프리 구동하여 구동전압 VN1을 생성한다. 프리 드라이버 D4는 부입력신호 INN를 풀다운전압 Vrdn으로 프리 구동하여 구동전압 VN2을 생성한다.The pre-driver D1 pre-drives the positive input signal INP to the pull-up voltage Vrup to generate the driving voltage VP1. The pre-driver D2 pre-drives the positive input signal INP to the pull-down voltage Vrdn to generate the driving voltage VP2. The pre-driver D3 pre-drives the negative input signal INN to the pull-up voltage Vrup to generate the driving voltage VN1. The pre-driver D4 pre-drives the negative input signal INN to the pull-down voltage Vrdn to generate the driving voltage VN2.
즉, 프리 드라이버 D1, D3는 풀업전압 Vrup으로 구동되고, 프리 드라이버 D2, D4는 풀다운전압 Vrdn으로 구동된다. That is, the pre-drivers D1 and D3 are driven by the pull-up voltage Vrup, and the pre-drivers D2 and D4 are driven by the pull-down voltage Vrdn.
전압 발생기(120)는 전원전압 VDD을 레귤레이팅하여 메인 구동부(130)의 구동전압 Vreg을 생성한다. 전압 발생기(120)는 생성된 구동전압 Vreg을 메인 구동부(130)의 스위칭 소자 M1, M2에 공급한다. The voltage generator 120 generates the driving voltage Vreg of the main driver 130 by regulating the power supply voltage VDD. The voltage generator 120 supplies the generated driving voltage Vreg to the switching elements M1 and M2 of the main driver 130.
메인 구동부(130)는 복수의 스위칭 소자 M1~M4를 포함한다. 스위칭 소자 M1~M4는 FET(field effect transistor)로 이루어질 수 있다. The main driver 130 includes a plurality of switching elements M1 to M4. The switching elements M1 to M4 may be formed of field effect transistors (FETs).
여기서, 스위칭 소자 M1, M3는 구동전압 Vreg의 인가단과 그라운드 GND 전압단 사이에 직렬 연결된다. 스위칭 소자 M1는 게이트 단자를 통해 구동전압 VP1이 인가되고, 스위칭 소자 M3는 게이트 단자를 통해 구동전압 VN2가 인가된다. 그리고, 스위칭 소자 M2, M4는 구동전압 Vreg의 인가단과 그라운드 GND 전압단 사이에 직렬 연결된다. 스위칭 소자 M2는 게이트 단자를 통해 구동전압 VN1이 인가되고, 스위칭 소자 M4는 게이트 단자를 통해 구동전압 VP2가 인가된다.Here, the switching elements M1 and M3 are connected in series between the application terminal of the driving voltage Vreg and the ground GND voltage terminal. The driving voltage VP1 is applied to the switching element M1 through the gate terminal, and the driving voltage VN2 is applied to the switching element M3 through the gate terminal. The switching elements M2 and M4 are connected in series between the application terminal of the driving voltage Vreg and the ground GND voltage terminal. The driving voltage VN1 is applied to the switching element M2 through the gate terminal, and the driving voltage VP2 is applied to the switching element M4 through the gate terminal.
도 2의 실시예에서 프리 드라이버 D1~D4의 개수는 메인 구동부(130)에 구비된 스위칭 소자 M1~M4의 개수와 대응된다. 즉, 프리 드라이버 D1~D4는 스위칭 소자 M1~M4를 개별적으로 구동 제어한다. 스위칭 소자 M1~M4의 개수가 변경되는 경우 프리 드라이버 D1~D4의 개수와 이와 대응되도록 변경될 수 있다. In the embodiment of FIG. 2, the number of pre-drivers D1 to D4 corresponds to the number of switching elements M1 to M4 provided in the main driver 130. That is, the pre-drivers D1 to D4 individually drive control the switching elements M1 to M4. When the number of switching elements M1 to M4 is changed, the number of switching elements M1 to M4 may be changed to correspond to the number of pre-drivers D1 to D4.
그리고, 스위칭 소자 M1, M3의 공통 연결노드는 차동 출력단 DP과 연결되고, 스위칭 소자 M2, M4의 공통 연결노드는 차동 출력단 DN과 연결된다. 차동 출력단 DN, DP는 전송선로(200)와 연결된다. The common connection node of the switching elements M1 and M3 is connected to the differential output terminal DP, and the common connection node of the switching elements M2 and M4 is connected to the differential output terminal DN. The differential output terminals DN and DP are connected to the transmission line 200.
스위칭 소자 M1~M4의 턴 온 저항은 송신기(100)의 출력저항이 된다. 그리고, 스위칭 소자 M1~M4의 턴 온 저항은 풀업전압 Vrup, 풀다운전압 Vrdn에 의해 결정된다. The turn-on resistance of the switching elements M1 to M4 becomes the output resistance of the transmitter 100. The turn-on resistance of the switching elements M1 to M4 is determined by the pullup voltage Vrup and the pulldown voltage Vrdn.
이러한 구성을 갖는 송신기(100)는 메인 구동부(130)에 구비된 스위칭 소자 M1~M4를 구동하기 위한 프리 드라이버 D1~D4의 출력 전압(VP1, VP2, VN1, VN2)을 개별적으로 조절한다. 이에 따라, 메인 구동부(130)의 스위칭 소자 M1~M4의 턴 온 저항을 일정하게 유지할 수 있도록 한다. The transmitter 100 having such a configuration individually adjusts output voltages VP1, VP2, VN1 and VN2 of the pre-drivers D1 to D4 for driving the switching elements M1 to M4 provided in the main driver 130. Accordingly, the turn-on resistance of the switching elements M1 to M4 of the main driver 130 can be kept constant.
예를 들어, 구동전압 VP1가 풀업전압 Vrup이고, 구동전압 VP2가 풀다운전압 Vrdn 레벨일 때, 스위칭 소자 M1, M4가 턴 온 된다. 그러면, 전압 발생기(120)에서 출력된 구동전압 Vreg은 스위칭 소자 M1를 통하여 차동 출력단 DP로 출력된다. 그리고, 차동 출력단 DP의 출력신호는 전송선로(200)를 통해 터미네이션(Termination) 저항(400)을 거쳐 차동 출력단 DN으로 입력되고 스위칭 소자 M4를 통해 그라운드 전압 GND 단으로 출력된다. For example, when the driving voltage VP1 is the pull-up voltage Vrup and the driving voltage VP2 is the pull-down voltage Vrdn level, the switching elements M1 and M4 are turned on. Then, the driving voltage Vreg output from the voltage generator 120 is output to the differential output terminal DP through the switching element M1. The output signal of the differential output terminal DP is input to the differential output terminal DN through the termination resistor 400 through the transmission line 200 and output to the ground voltage GND terminal through the switching element M4.
이때, 구동전압 Vreg에서 그라운드 전압 GND 단으로 흐르는 전류는 (Vreg-GND)/((M1 턴 온 저항)+(터미네이션 저항)+(M4 턴 온 저항))이 된다. 이 전류를 Iref 라고 할 때, 차동 출력단 DP에 걸리는 전압은 Vreg-Iref*(M1 턴 온 저항)이 되고 차동 출력단 DN에 걸리는 전압은 GND+Iref*(M4 턴 온 저항)이 된다.At this time, the current flowing from the driving voltage Vreg to the ground voltage GND terminal becomes (Vreg-GND) / ((M1 turn-on resistance) + (termination resistor) + (M4 turn-on resistance)). When this current is called Iref, the voltage across the differential output DP becomes Vreg-Iref * (M1 turn-on resistance) and the voltage across the differential output DN becomes GND + Iref * (M4 turn-on resistance).
여기서, 구동전압 VN1, VN2는 구동전압 VP1, VP2와 반대의 극성을 가지며, 구동전압 VP1, VP2가 하이 상태일 때 구동전압 VN1, VN2이 로우 상태가 되어 스위칭 소자 M2, M3가 턴 오프 된다. Here, the driving voltages VN1 and VN2 have polarities opposite to those of the driving voltages VP1 and VP2. When the driving voltages VP1 and VP2 are high, the driving voltages VN1 and VN2 are turned low, and the switching elements M2 and M3 are turned off.
반면에, 구동전압 VN1, VN2이 하이 상태일 때, 스위칭 소자 M2, M3이 턴 온 된다. 이에 따라, 구동전압 Vreg은 스위칭 소자 M2를 통하여 차동 출력단 DN으로 출력된다. 그리고, 차동 출력단 DN의 출력신호는 전송선로(200)를 통해 터미네이션 저항(400)을 거쳐 차동 출력단 DP으로 입력되고 스위칭 소자 M3을 통해 그라운드 전압 GND 단으로 출력된다.On the other hand, when the driving voltages VN1 and VN2 are high, the switching elements M2 and M3 are turned on. Accordingly, the driving voltage Vreg is output to the differential output terminal DN through the switching element M2. The output signal of the differential output terminal DN is input to the differential output terminal DP via the termination resistor 400 through the transmission line 200 and output to the ground voltage GND terminal through the switching element M3.
이때, 구동전압 Vreg에서 그라운드 전압 GND로 흐르는 전류는 (Vreg-GND)/((M2 턴 온 저항)+(터미네이션 저항)+(M3 턴 온 저항))이 된다. 이 전류를 Iref 라고 할 때, 차동 출력단 DN에 걸리는 전압은 Vreg-Iref*(M2 턴 온 저항)이 되고 차동 출력단 DP에 걸리는 전압은 GND+Iref*(M3 턴 온 저항)이 된다. At this time, the current flowing from the driving voltage Vreg to the ground voltage GND becomes (Vreg-GND) / ((M2 turn-on resistance) + (termination resistor) + (M3 turn-on resistance)). When this current is called Iref, the voltage across the differential output DN becomes Vreg-Iref * (M2 turn-on resistance) and the voltage across the differential output DP is GND + Iref * (M3 turn-on resistance).
여기서, 구동전압 VN1, VN2가 하이 상태일 때 구동전압 VP1, VP2이 로우 상태가 되어 스위칭 소자 M1, M4가 턴 오프 된다.Here, when the driving voltages VN1 and VN2 are high, the driving voltages VP1 and VP2 are turned low so that the switching elements M1 and M4 are turned off.
도 3은 도 2의 풀업 제어부(111)에 관한 상세 구성도이다. 3 is a detailed block diagram of the pull-up control unit 111 of FIG. 2.
풀업 제어부(111)는 프리 드라이버 D1, D3에 공급되는 풀업전압 Vrup을 생성한다. 이러한 풀업 제어부(111)는 고전압 발생기(112), 전압 발생기(113), 증폭기(114), 정전류원(115), 스위칭 소자 M5 및 풀업전압 생성부 PU를 포함한다. The pull-up control unit 111 generates the pull-up voltage Vrup supplied to the pre-drivers D1 and D3. The pull-up control unit 111 includes a high voltage generator 112, a voltage generator 113, an amplifier 114, a constant current source 115, a switching element M5, and a pull-up voltage generator PU.
여기서, 고전압 발생기(112)는 전원전압 VDD에 대응하여 고전압 Vhigh을 생성하고 증폭기(114)에 공급한다. 전압 발생기(113)는 전원전압 VDD을 레귤레이팅하여 구동전압 Vreg2을 생성하고 스위칭 소자 M5에 공급한다. 여기서, 구동전압 Vreg2는 구동전압 Vreg와 동일한 전압 레벨을 가질 수 있다. Here, the high voltage generator 112 generates a high voltage Vhigh corresponding to the power supply voltage VDD and supplies it to the amplifier 114. The voltage generator 113 generates the driving voltage Vreg2 by regulating the power supply voltage VDD and supplies it to the switching element M5. Here, the driving voltage Vreg2 may have the same voltage level as the driving voltage Vreg.
증폭기(114)는 전원전압 VDD에 대응하여 고전압 Vhigh과 피드백 전압 Vfeedh을 비교 및 증폭하여 풀업 구동신호 VPU를 출력한다. 즉, 증폭기(114)는 플러스 입력단을 통해 고전압 Vhigh을 입력받고, 마이너스 입력단을 통해 피드백 전압 Vfeedh을 입력받는다. The amplifier 114 outputs the pull-up driving signal VPU by comparing and amplifying the high voltage Vhigh and the feedback voltage Vfeedh in response to the power supply voltage VDD. That is, the amplifier 114 receives the high voltage Vhigh through the positive input terminal and the feedback voltage Vfeedh through the negative input terminal.
또한, 정전류원(115)은 스위칭 소자 M5와 그라운드 GND 전압단 사이에 연결되어 피드백 전압 Vfeedh에 대응하는 정전류 Iref가 흐른다. 또한, 풀업전압 생성부 PU는 전원전압 VDD에 대응하여 풀업 구동신호 VPU를 레귤레이팅하여 풀업전압 Vrup을 생성하고 프리 드라이버 D1, D3에 공급한다. In addition, the constant current source 115 is connected between the switching element M5 and the ground GND voltage terminal, so that the constant current Iref corresponding to the feedback voltage Vfeedh flows. In addition, the pull-up voltage generation unit PU regulates the pull-up driving signal VPU in response to the power supply voltage VDD to generate a pull-up voltage Vrup and supplies it to the pre-drivers D1 and D3.
또한, 그리고, 스위칭 소자 M5는 구동전압 Vreg2 인가단과 정전류원(115) 사이에 연결되어 게이트 단자를 통해 풀업 구동신호 VPU가 인가된다. 스위칭 소자 M5는 도 2의 스위칭 소자 M1,M2와 동일한 크기와 동일한 레이아웃(Layout)을 가지는 복사본(Replica)이다. 여기서, 스위칭 소자 M1, M2는 서로 동일한 크기와 동일한 레이아웃(Layout)을 갖는 것을 가정한다.In addition, the switching element M5 is connected between the driving voltage Vreg2 applying terminal and the constant current source 115 to receive the pull-up driving signal VPU through the gate terminal. The switching element M5 is a replica having the same size and the same layout as the switching elements M1 and M2 of FIG. 2. Here, it is assumed that the switching elements M1 and M2 have the same size and the same layout.
만약, 증폭기(114)의 이득(DC gain)이 충분히 클 경우(예를 들면, 60dB이상), 피드백 전압 Vfeedh이 고전압 Vhigh의 값과 같아지도록 풀업 구동신호 VPU의 레벨이 조절된다. 이때, 스위칭 소자 M5의 턴 온(trun on) 저항은 (Vreg2 - Vhigh) / Iref 가 된다.If the gain (DC gain) of the amplifier 114 is sufficiently large (for example, 60 dB or more), the level of the pull-up drive signal VPU is adjusted so that the feedback voltage Vfeedh is equal to the value of the high voltage Vhigh. At this time, the turn on resistance of the switching element M5 becomes (Vreg2-Vhigh) / Iref.
풀업전압 생성부 PU는 이렇게 조절된 풀업 구동신호 VPU를 레귤레이팅하여 풀업전압 Vrup을 생성한다. 풀업전압 생성부 PU는 생성된 풀업전압 Vrup을 프리 드라이버 D1, D3의 전원으로 공급한다. The pull-up voltage generator PU generates the pull-up voltage Vrup by regulating the adjusted pull-up driving signal VPU. The pull-up voltage generator PU supplies the generated pull-up voltage Vrup to power of the pre-drivers D1 and D3.
풀업전압 Vrup를 전원전압으로 입력받는 프리 드라이버 D1, D3는 구동전압 VP1, VN1에 따라 스위칭 소자 M1, M2의 구동을 제어하게 된다. 즉, 구동전압 VP1, VN1의 하이 상태 전압은 풀업전압 Vrup 레벨이 된다. The pre-drivers D1 and D3 receiving the pull-up voltage Vrup as the power supply voltage control the driving of the switching elements M1 and M2 according to the driving voltages VP1 and VN1. In other words, the high state voltages of the driving voltages VP1 and VN1 become the pull-up voltage Vrup level.
메인 구동부(130)의 스위칭 소자 M1, M2에 풀업전압 Vrup이 인가될 때의 턴 온 저항값은 스위칭 소자 M5의 턴 온 저항값과 동일하여, (Vreg2-Vhigh) / Iref가 된다. 이때, 구동전압 Vreg2은 고전압 Vhigh 보다 높은 전압 레벨을 갖는 것이 바람직하다. The turn-on resistance value when the pull-up voltage Vrup is applied to the switching elements M1 and M2 of the main driver 130 is the same as the turn-on resistance value of the switching element M5, resulting in (Vreg2-Vhigh) / Iref. At this time, the driving voltage Vreg2 preferably has a voltage level higher than the high voltage Vhigh.
본 발명의 실시예에서 스위칭 소자 M1, M2의 공정변화에 대응하여 복사본인 스위칭 소자 M5와 증폭기(114), 밴드갭전압을 기초로 생성되어 지는 고전압 Vhigh 및 정전류원(115)에 의해 스위칭 소자 M1, M2의 출력저항이 일정하도록 풀업전압 Vrup의 레벨이 조절되므로 스위칭 소자 M1, M2의 턴 온 저항값은 공정변화에 영향을 받지 않게 된다.In the embodiment of the present invention, the switching element M1 by the high voltage Vhigh and the constant current source 115 generated based on the switching element M5, the amplifier 114, and the band gap voltage corresponding to the process change of the switching elements M1 and M2. Since the level of the pullup voltage Vrup is adjusted so that the output resistance of M2 is constant, the turn-on resistance values of the switching elements M1 and M2 are not affected by the process change.
도 4는 도 2의 풀다운 제어부(116)에 관한 상세 구성도이다. 4 is a detailed configuration diagram illustrating the pull-down control unit 116 of FIG. 2.
풀다운 제어부(116)는 프리 드라이버 D2, D4에 공급되는 풀다운전압 Vrdn을 생성한다. 이러한 풀다운 제어부(116)는 저전압 발생기(117), 증폭기(118), 정전류원(119), 스위칭 소자 M6 및 풀다운전압 생성부 PD를 포함한다. The pulldown control unit 116 generates a pulldown voltage Vrdn supplied to the pre drivers D2 and D4. The pull-down controller 116 includes a low voltage generator 117, an amplifier 118, a constant current source 119, a switching element M6, and a pull-down voltage generator PD.
여기서, 저전압 발생기(117)는 전원전압 VDD에 대응하여 저전압 Vlow을 생성하고 증폭기(118)에 공급한다. 증폭기(118)는 전원전압 VDD에 대응하여 저전압 Vlow과 피드백 전압 Vfeedl을 비교 및 증폭하여 풀다운 구동신호 VPD를 출력한다. 즉, 증폭기(118)는 마이너스 입력단을 통해 저전압 Vlow을 입력받고, 플러스 입력단을 통해 피드백 전압 Vfeedl을 입력받는다. Here, the low voltage generator 117 generates the low voltage Vlow in response to the power supply voltage VDD and supplies it to the amplifier 118. The amplifier 118 compares and amplifies the low voltage Vlow and the feedback voltage Vfeedl in response to the power supply voltage VDD, and outputs a pull-down driving signal VPD. That is, the amplifier 118 receives the low voltage Vlow through the negative input terminal and the feedback voltage Vfeedl through the positive input terminal.
또한, 정전류원(119)은 전원전압 VDD 인가단과 스위칭 소자 M6 사이에 연결되어 피드백 전압 Vfeedl에 대응하는 정전류 Iref가 흐른다. 또한, 풀다운전압 생성부 PD는 전원전압 VDD에 대응하여 풀다운 구동신호 VPD를 레귤레이팅하여 풀다운전압 Vrdn을 생성하고 프리 드라이버 D2, D4에 공급한다.In addition, the constant current source 119 is connected between the supply voltage VDD applying stage and the switching element M6 so that the constant current Iref corresponding to the feedback voltage Vfeedl flows. In addition, the pull-down voltage generator PD generates a pull-down voltage Vrdn by regulating the pull-down driving signal VPD in response to the power supply voltage VDD and supplies it to the pre-drivers D2 and D4.
그리고, 스위칭 소자 M6는 정전류원(119)과 그라운드 GND 전압단 사이에 연결되어 게이트 단자를 통해 풀다운 구동신호 VPD가 인가된다. 스위칭 소자 M6는 도 2의 스위칭 소자 M3,M4와 동일한 크기와 동일한 레이아웃(Layout)을 가지는 복사본(Replica)이다. 여기서, 스위칭 소자 M3, M4는 서로 동일한 크기와 동일한 레이아웃(Layout)을 갖는 것을 가정한다.The switching element M6 is connected between the constant current source 119 and the ground GND voltage terminal, and the pull-down driving signal VPD is applied through the gate terminal. The switching element M6 is a replica having the same size and the same layout as the switching elements M3 and M4 of FIG. 2. Here, it is assumed that the switching elements M3 and M4 have the same size and the same layout.
만약, 증폭기(118)의 이득(DC gain)이 충분히 클 경우(예를 들면, 60dB이상), 피드백 전압 Vfeedl이 저전압 Vlow의 값과 같아지도록 풀다운 구동신호 VPD의 레벨이 조절된다. 이때, 스위칭 소자 M6의 턴 온(trun on) 저항은 Vlow / Iref 가 된다.If the gain (DC gain) of the amplifier 118 is sufficiently large (for example, 60 dB or more), the level of the pull-down drive signal VPD is adjusted so that the feedback voltage Vfeedl is equal to the value of the low voltage Vlow. At this time, the turn on resistance of the switching element M6 becomes Vlow / Iref.
풀다운전압 생성부 PD는 이렇게 조절된 풀다운 구동신호 VPD를 레귤레이팅하여 풀다운전압 Vrdn을 생성한다. 풀다운전압 생성부 PD는 생성된 풀다운전압 Vrdn을 프리 드라이버 D2, D4의 전원으로 공급한다. The pull-down voltage generator PD generates the pull-down voltage Vrdn by regulating the adjusted pull-down driving signal VPD. The pull-down voltage generator PD supplies the generated pull-down voltage Vrdn to power of the pre-drivers D2 and D4.
풀다운전압 Vrdn를 전원전압으로 입력받는 프리 드라이버 D2, D4는 구동전압 VP2, VN2에 따라 스위칭 소자 M3, M4의 구동을 제어하게 된다. 즉, 구동전압 VP2, VN2의 하이 상태 전압은 풀다운전압 Vrdn 레벨이 된다. The pre-drivers D2 and D4, which receive the pull-down voltage Vrdn as the power supply voltage, control the driving of the switching elements M3 and M4 according to the driving voltages VP2 and VN2. In other words, the high state voltages of the driving voltages VP2 and VN2 become the pull-down voltage Vrdn level.
메인 구동부(130)의 스위칭 소자 M3, M4에 풀다운전압 Vrdn이 인가될 때의 턴 온 저항값은 스위칭 소자 M6의 턴 온 저항값과 동일하여, Vlow / Iref가 된다. 본 발명의 실시예에서 스위칭 소자 M3, M4의 공정변화에 대응하여 복사본인 스위칭 소자 M6와 증폭기(118) 및 밴드갭전압을 기초로 생성되어지는 저전압 Vlow 및 정전류원(119)에 의해 스위칭 소자 M3, M4의 출력 저항이 일정하도록 풀다운전압 Vrdn의 레벨이 조절되므로 스위칭 소자 M3, M4의 턴 온 저항값은 공정변화에 영향을 받지 않게 된다.The turn-on resistance value when the pull-down voltage Vrdn is applied to the switching elements M3 and M4 of the main driver 130 is the same as the turn-on resistance value of the switching element M6, resulting in Vlow / Iref. In the embodiment of the present invention, the switching element M3 by the low voltage Vlow and the constant current source 119 generated based on the switching element M6, the amplifier 118, and the band gap voltage corresponding to the process change of the switching elements M3 and M4. Since the level of the pull-down voltage Vrdn is adjusted so that the output resistance of M4 is constant, the turn-on resistance values of the switching elements M3 and M4 are not affected by the process change.
도 5는 도 1의 송신기(100)에 관한 다른 실시예이다. 5 is another embodiment of the transmitter 100 of FIG.
도 5의 실시예에 따른 송신기(100_1)는 입력 구동부(110_1), 전압 발생기(120_1), 메인 구동부(130_1) 및 차동 출력단 DN, DP를 포함한다. 도 5의 실시예는 도 2의 실시예와 동일한 구조를 가진다. 다만, 메인 구동부(130_1)에 ESD(Electro Static Discharge)를 방지하기 위한 저항 R1~R4를 포함하는 것이 도 2와 상이하다. The transmitter 100_1 according to the embodiment of FIG. 5 includes an input driver 110_1, a voltage generator 120_1, a main driver 130_1, and differential output terminals DN and DP. 5 has the same structure as the embodiment of FIG. However, it is different from FIG. 2 in that the main driver 130_1 includes resistors R1 to R4 for preventing electrostatic discharge (ESD).
스위칭 소자 M1와 차동 출력단 DP 사이에는 저항 R1이 연결된다. 그리고, 스위칭 소자 M2와 차동 출력단 DN 사이에는 저항 R2이 연결된다. 그리고, 스위칭 소자 M3와 차동 출력단 DP 사이에는 저항 R3이 연결된다. 또한, 스위칭 소자 M4와 차동 출력단 DN 사이에는 저항 R4이 연결된다. 즉, 차동 출력단 DN과 스위칭 소자 M2, M4 사이에 저항 R2, R4를 연결하고, 차동 출력단 DP와 스위칭 소자 M1, M3 사이에 저항 R1, R3을 연결한다. A resistor R1 is connected between the switching element M1 and the differential output terminal DP. A resistor R2 is connected between the switching element M2 and the differential output terminal DN. A resistor R3 is connected between the switching element M3 and the differential output terminal DP. In addition, a resistor R4 is connected between the switching element M4 and the differential output terminal DN. That is, the resistors R2 and R4 are connected between the differential output terminal DN and the switching elements M2 and M4, and the resistors R1 and R3 are connected between the differential output terminal DP and the switching elements M1 and M3.
차동 출력단 DP, DN은 반도체 칩 내부와 외부를 연결하는 접속점(Interface)으로서 차동 출력단 DP, DN에 ESD(Electro Static Discharge) 문제가 생길 수 있다. 이러한 경우를 대비하고자 전송선로(200)와 연결되는 차동 출력단 DP, DN에 저항 R1~R4을 연결한다. The differential output terminals DP and DN are interfaces that connect the inside and the outside of the semiconductor chip, which may cause electrostatic discharge (ESD) problems in the differential output terminals DP and DN. In order to prepare for this case, the resistors R1 to R4 are connected to the differential output terminals DP and DN connected to the transmission line 200.
스위칭 소자 M1~M4의 턴 온 저항과 저항 R1~R4의 저항값을 합한 값이 송신기(100_1)의 출력저항이 된다. 그리고, 스위칭 소자 M1~M4의 턴 온 저항은 풀업전압 Vrup, 풀다운전압 Vrdn에 의해 결정된다. The sum of the turn-on resistances of the switching elements M1 to M4 and the resistances of the resistors R1 to R4 becomes the output resistance of the transmitter 100_1. The turn-on resistance of the switching elements M1 to M4 is determined by the pullup voltage Vrup and the pulldown voltage Vrdn.
차동 출력단 DP,DN과 정전류원(115, 119)에 걸리는 전압은 각 스위칭 소자 M1~M4의 트랜지스터 턴 온(turn on) 저항에 메인 구동부(130_1)의 ESD를 위한 저항 R1~R4의 저항값(R)을 더하면 된다. 즉, 스위칭 소자 M1과 저항 R1을 통한 출력 저항의 경우 (스위칭 소자 M1의 턴 온 저항 + 저항 R1의 저항값 R)이 된다.The voltage across the differential output terminals DP, DN and the constant current sources 115 and 119 is the resistance value of the resistors R1 to R4 for the ESD of the main driver 130_1 to the transistor turn on resistances of the switching elements M1 to M4. You can add R). That is, in the case of the output resistance through the switching element M1 and the resistor R1, it becomes (the turn-on resistance of the switching element M1 + the resistance value R of the resistance R1).
도 6은 도 5의 풀업 제어부(111_1)에 관한 상세 구성도이다. 6 is a detailed block diagram of the pull-up control unit 111_1 of FIG. 5.
도 6의 실시예는 도 3과 동일한 구조를 갖지만, 스위칭 소자 M5과 정전류원(115) 사이에 저항 R5을 더 구비하는 것이 도 3과 서로 상이하다. The embodiment of FIG. 6 has the same structure as that in FIG. 3, but differs from FIG. 3 in that a resistor R5 is further provided between the switching element M5 and the constant current source 115.
만약, 증폭기(114)의 이득(DC gain)이 충분히 클 경우(예를 들면, 60dB이상), 피드백 전압 Vfeedh이 고전압 Vhigh의 값과 같아지도록 풀업 구동신호 VPU의 레벨이 조절된다. 이때, 스위칭 소자 M5의 턴 온(trun on) 저항과 저항 R5의 합은 (Vreg2 - Vhigh) / Iref 가 된다.If the gain (DC gain) of the amplifier 114 is sufficiently large (for example, 60 dB or more), the level of the pull-up drive signal VPU is adjusted so that the feedback voltage Vfeedh is equal to the value of the high voltage Vhigh. At this time, the sum of the turn on resistance of the switching element M5 and the resistance R5 becomes (Vreg2-Vhigh) / Iref.
풀업전압 생성부 PU는 이렇게 조절된 풀업 구동신호 VPU를 레귤레이팅하여 풀업전압 Vrup을 생성한다. 풀업전압 생성부 PU는 생성된 풀업전압 Vrup을 프리 드라이버 D1, D3의 전원으로 공급한다. The pull-up voltage generator PU generates the pull-up voltage Vrup by regulating the adjusted pull-up driving signal VPU. The pull-up voltage generator PU supplies the generated pull-up voltage Vrup to power of the pre-drivers D1 and D3.
풀업전압 Vrup를 전원전압으로 입력받는 프리 드라이버 D1, D3는 구동전압 VP1, VN1에 따라 스위칭 소자 M1, M2의 구동을 제어하게 된다. 즉, 구동전압 VP1, VN1의 하이 상태 전압은 풀업전압 Vrup 레벨이 된다. The pre-drivers D1 and D3 receiving the pull-up voltage Vrup as the power supply voltage control the driving of the switching elements M1 and M2 according to the driving voltages VP1 and VN1. In other words, the high state voltages of the driving voltages VP1 and VN1 become the pull-up voltage Vrup level.
메인 구동부(130)의 스위칭 소자 M1, M2에 풀업전압 Vrup이 인가될 때의 턴 온 저항과 각 저항 R1, R2의 합은, 스위칭 소자 M5의 턴 온 저항과 저항 R5의 합과 동일하여, (Vreg2-Vhigh) / Iref가 된다. 이때, 구동전압 Vreg2은 고전압 Vhigh 보다 높은 전압 레벨을 갖는 것이 바람직하다. 본 발명의 실시예에서 스위칭 소자 M1, M2 및 저항 R1, R2의 공정변화에 대응하여 복사본인 스위칭 소자 M5와 저항 R5, 증폭기(114), 밴드갭전압을 기초로 생성되어지는 고전압 Vhigh 및 정전류원(115)에 의해 스위칭 소자 M1, M2의 턴 온 저항 및 저항 R1, R2의 합이 일정하도록 풀업전압 Vrup의 레벨이 조절되므로 스위칭 소자 M1, M2의 턴 온 저항과 저항 R1, R2의 합은 공정변화에 영향을 받지 않게 된다.When the pull-up voltage Vrup is applied to the switching elements M1 and M2 of the main driver 130, the sum of the turn-on resistance and the resistors R1 and R2 is equal to the sum of the turn-on resistance and the resistance R5 of the switching element M5, Vreg2-Vhigh) / Iref. At this time, the driving voltage Vreg2 preferably has a voltage level higher than the high voltage Vhigh. In the embodiment of the present invention, the high voltage Vhigh and the constant current source generated based on the switching element M5, the resistor R5, the amplifier 114, and the bandgap voltage are copied in response to the process change of the switching elements M1, M2 and the resistors R1, R2. By 115, the level of the pull-up voltage Vrup is adjusted so that the turn-on resistances of the switching elements M1 and M2 and the sum of the resistors R1 and R2 are constant, so the sum of the turn-on resistances of the switching elements M1 and M2 and the resistors R1 and R2 is processed. It is not affected by change.
도 7은 도 5의 풀다운 제어부(116_1)에 관한 상세 구성도이다. FIG. 7 is a detailed configuration diagram illustrating the pull-down control unit 116_1 of FIG. 5.
도 7의 실시예는 도 4와 동일한 구조를 갖지만, 스위칭 소자 M6과 정전류원(119) 사이에 저항 R6을 더 구비하는 것이 도 4와 서로 상이하다. Although the embodiment of FIG. 7 has the same structure as that of FIG. 4, it is different from FIG. 4 to further include a resistor R6 between the switching element M6 and the constant current source 119.
만약, 증폭기(118)의 이득(DC gain)이 충분히 클 경우(예를 들면, 60dB이상), 피드백 전압 Vfeedl이 저전압 Vlow의 값과 같아지도록 풀다운 구동신호 VPD의 레벨이 조절된다. 이때, 스위칭 소자 M6의 턴 온(trun on) 저항과 저항 R6의 합은 Vlow / Iref 가 된다.If the gain (DC gain) of the amplifier 118 is sufficiently large (for example, 60 dB or more), the level of the pull-down drive signal VPD is adjusted so that the feedback voltage Vfeedl is equal to the value of the low voltage Vlow. At this time, the sum of the turn on resistance of the switching element M6 and the resistor R6 becomes Vlow / Iref.
풀다운전압 생성부 PD는 이렇게 조절된 풀다운 구동신호 VPD를 레귤레이팅하여 풀다운전압 Vrdn을 생성한다. 풀다운전압 생성부 PD는 생성된 풀다운전압 Vrdn을 프리 드라이버 D2, D4의 전원으로 공급한다. The pull-down voltage generator PD generates the pull-down voltage Vrdn by regulating the adjusted pull-down driving signal VPD. The pull-down voltage generator PD supplies the generated pull-down voltage Vrdn to power of the pre-drivers D2 and D4.
풀다운전압 Vrdn를 전원전압으로 입력받는 프리 드라이버 D2, D4는 구동전압 VP2, VN2에 따라 스위칭 소자 M3, M4의 구동을 제어하게 된다. 즉, 구동전압 VP2, VN2의 하이 상태 전압은 풀다운전압 Vrdn 레벨이 된다. The pre-drivers D2 and D4, which receive the pull-down voltage Vrdn as the power supply voltage, control the driving of the switching elements M3 and M4 according to the driving voltages VP2 and VN2. In other words, the high state voltages of the driving voltages VP2 and VN2 become the pull-down voltage Vrdn level.
메인 구동부(130)의 스위칭 소자 M3, M4에 풀다운전압 Vrdn이 인가될 때의 턴 온 저항과 저항 R3, R4의 합은, 스위칭 소자 M6의 턴 온 저항과 저항 R6의 합과 동일하여, Vlow / Iref가 된다. 본 발명의 실시예에서 스위칭 소자 M3, M4 및 저항 R3, R4의 공정 변화에 대응하여 복사본인 스위칭 소자 M6과 저항 R6, 증폭기(118), 밴드갭전압을 기초로 생성되어 지는 저전압 Vlow 및 정전류원(119)에 의해 스위칭 소자 M3, M4의 턴 온 저항 및 저항 R3, R4의 합이 일정하도록 풀다운전압 Vrdn의 레벨이 조절되므로 스위칭 소자 M3, M4의 턴 온 저항과 저항 R3, R4의 합은 공정변화에 영향을 받지 않게 된다.When the pull-down voltage Vrdn is applied to the switching elements M3 and M4 of the main driver 130, the sum of the turn-on resistance and the resistors R3 and R4 is equal to the sum of the turn-on resistance and the resistance R6 of the switching element M6, and thus Vlow / It becomes Iref. In the embodiment of the present invention, the low voltage Vlow and the constant current source generated based on the switching element M6, the resistor R6, the amplifier 118, and the bandgap voltage are copied in response to the process change of the switching elements M3, M4 and the resistors R3, R4. Since the level of the pull-down voltage Vrdn is adjusted so that the turn-on resistance of the switching elements M3 and M4 and the sum of the resistors R3 and R4 are constant by 119, the sum of the turn-on resistance of the switching elements M3 and M4 and the resistors R3 and R4 is processed. It is not affected by change.
도 8은 본 발명의 실시예에 따른 송신기(100)에 관한 동작 타이밍도이다. 8 is an operation timing diagram for the transmitter 100 according to the embodiment of the present invention.
정입력신호 INP와 부입력신호 INN은 전원전압 VDD과 그라운드 전압 GND 레벨 사이에서 스윙한다. 여기서, 정입력신호 INP와 부입력신호 INN는 서로 반대의 위상을 갖는다. The positive input signal INP and the negative input signal INN swing between the power supply voltage VDD and the ground voltage GND level. Here, the positive input signal INP and the negative input signal INN have opposite phases.
구동전압 VP1, VN1은 풀업전압 Vrup과 그라운드 전압 GND의 레벨 사이에서 스윙한다. 그리고, 구동전압 VP2, VN2는 풀다운전압 Vrdn과 그라운드 전압 GND의 레벨 사이에서 스윙한다. 여기서, 구동전압 VP1, VP2는 구동전압 VN1, VN2와 서로 반대의 위상을 갖는다. 그리고, 송신기(100)의 출력인 차동 출력단 DN, DP은 고전압 Vhigh과 저전압 Vlow의 레벨 사이에서 스윙하는 것을 볼 수 있다.The driving voltages VP1 and VN1 swing between the level of the pullup voltage Vrup and the ground voltage GND. The driving voltages VP2 and VN2 swing between the pull-down voltage Vrdn and the ground voltage GND. Here, the driving voltages VP1 and VP2 have phases opposite to those of the driving voltages VN1 and VN2. In addition, it can be seen that the differential output stages DN and DP, which are outputs of the transmitter 100, swing between the levels of the high voltage Vhigh and the low voltage Vlow.
여기서, 고전압 Vhigh는 Vreg-Iref * (M1 턴 온 저항) 또는 Vreg-Iref * (M2 trun on 저항) 이다. 그리고, 저전압 Vlow는 GND+Iref * (M4 턴 온 저항) 또는 GND+Iref * (M3 턴 온 저항)이 된다. 통상적으로, GND는 0V이므로 저전압 Vlow는 Iref * (M4 턴 온 저항) 또는 Iref * (M3 턴 온 저항)이 된다.Here, the high voltage Vhigh is Vreg-Iref * (M1 turn on resistance) or Vreg-Iref * (M2 trun on resistance). Then, the low voltage Vlow becomes GND + Iref * (M4 turn-on resistor) or GND + Iref * (M3 turn-on resistor). Typically, GND is 0V, so the low voltage Vlow is either Iref * (M4 turn on resistance) or Iref * (M3 turn on resistance).
예를 들어, LDI(LCD Driver IC)나 휴대폰용 이미지 센서 등에 사용되는 MIPI(Mobile Industry Processor Interface)의 경우 구동전압 Vreg는 400mv, 고전압 Vhigh는 300mV, 저전압 Vlow는 100mV가 표준규격이다. 그리고, 터미네이션(Termination) 저항(300)을 100ohm을 사용하게 된다. For example, the MIPI (Mobile Industry Processor Interface) used in LCD driver ICs (LDIs) and image sensors for mobile phones has a standard specification of 400 mV for driving voltage, 300 mV for high voltage Vhigh, and 100 mV for low voltage Vlow. The termination resistor 300 uses 100 ohms.
이에 따라, 이 사양을 만족하기 위해서 전류(Iref)는 2mA가 되고 각 트랜지스터(M1~M4)의 턴 온(turn on) 저항은 50ohm이 되어야 하며, 이때 전송라인(200)의 특성 임피던스 정합도 만족하게 된다. 이때, 송신기(100)의 출력 저항은 50ohm이 된다.Accordingly, in order to satisfy this specification, the current Iref should be 2 mA and the turn-on resistance of each transistor M1-M4 should be 50 ohm, and the characteristic impedance matching of the transmission line 200 is also satisfied. Done. At this time, the output resistance of the transmitter 100 is 50 ohm.
또한, 도 5의 실시예의 경우에는 각 트랜지스터(M1~M4)의 턴 온(turn-on) 저항과 ESD를 위한 저항(R)의 합이 50ohm이 되어야 한다. 그런데, 트랜지스터(M1~M4)의 턴 온(turn-on) 저항이나 ESD를 위한 저항(R)은 반도체 제조공정 편차에 의존도가 커서 반도체 제조 공정에 편차가 생길 경우, 송신기(100)의 출력 저항에 직접적으로 영향을 주게 된다.In addition, in the case of the embodiment of FIG. 5, the sum of the turn-on resistance of each transistor M1 to M4 and the resistance R for ESD should be 50 ohm. However, the turn-on resistance of the transistors M1 to M4 or the resistance R for ESD are highly dependent on the variation in the semiconductor manufacturing process, and thus the output resistance of the transmitter 100 when a variation occurs in the semiconductor manufacturing process. Will affect directly.
MIPI의 경우 출력 저항 규격이 최저 40ohm이고 최고 62.5ohm 인데 제조 공정의 편차 비율은 이를 훨씬 상회 하므로 규격을 벗어나게 된다. 뿐만 아니라, 전송라인(200)의 특성임피던스 정합도 제대로 이루어 지지 않게 되어 신호 전송에 반사가 생겨 신호가 고속으로 갈수록 전송되는 신호에 왜곡이 생기게 된다.In the case of MIPI, the output resistance specifications are as low as 40 ohms and as high as 62.5 ohms. In addition, the characteristic impedance matching of the transmission line 200 may not be properly performed, thereby causing reflection in the signal transmission, causing distortion in the signal transmitted at a higher speed.
이를 위해, 본 발명의 실시예에서는 스위칭 소자 M1~M4 및 ESD를 위한 저항 R1~R4들의 공정변화에 대응하여 이들의 복사본인 M5, M6, 저항 R5, R6 및 밴드갭전압을 기초로 생성되어 지는 고전압 Vhigh, 저전압 Vlow와 정전류원(115, 119) 및 증폭기(114, 118)에 의해 풀업전압 Vrup, 풀다운전압 Vrdn의 레벨이 조절되므로 스위칭 소자 M1~M4의 턴 온 저항값 또는 이와 R~R4의 합은 공정변화에 영향을 받지 않게 된다.To this end, in an embodiment of the present invention, corresponding to the process changes of the switching elements M1 to M4 and the resistors R1 to R4 for the ESD, they are generated based on the copies M5, M6, resistors R5, R6 and the bandgap voltage. The level of the pull-up voltage Vrup and the pull-down voltage Vrdn is controlled by the high voltage Vhigh, the low voltage Vlow and the constant current sources 115 and 119 and the amplifiers 114 and 118, so that the turn-on resistance values of the switching elements M1 to M4, or R to R4 The sum will not be affected by process changes.

Claims (15)

  1. 복수의 프리 드라이버를 포함하고, 정입력신호와 부입력신호를 구동하여 풀업전압 레벨을 갖는 복수의 구동신호와 풀다운전압 레벨을 갖는 복수의 구동신호를 출력하는 입력 구동부; An input driver including a plurality of pre-drivers and driving a positive input signal and a negative input signal to output a plurality of drive signals having a pull-up voltage level and a plurality of drive signals having a pull-down voltage level;
    전원전압을 레귤레이팅하여 제 1구동전압을 생성하는 전압 발생기; 및A voltage generator for regulating a power supply voltage to generate a first driving voltage; And
    상기 복수의 구동신호에 의해 선택적으로 턴 온 되는 복수의 스위칭 소자를 포함하여 상기 제 1구동전압을 차동 출력단에 선택적으로 공급하고, 상기 복수의 스위칭 소자의 턴 온 저항이 상기 풀업 전압 레벨과 상기 풀다운전압 레벨에 의해 조정되는 메인 구동부를 포함하는 것을 특징으로 하는 저전압 차동 신호 전송기.A plurality of switching elements selectively turned on by the plurality of driving signals, wherein the first driving voltage is selectively supplied to a differential output terminal, and turn-on resistances of the plurality of switching elements are supplied to the pull-up voltage level and the pull-down; A low voltage differential signal transmitter comprising a main driver regulated by a voltage level.
  2. 제 1항에 있어서, 상기 입력 구동부는 The method of claim 1, wherein the input driver
    상기 풀업 전압 레벨에 따라 상기 메인 구동부의 풀업단을 구동하기 위한 제 1 및 제 2구동신호를 출력하는 제 1 및 제 2프리 드라이버; First and second pre-drivers for outputting first and second driving signals for driving the pull-up end of the main driver in accordance with the pull-up voltage level;
    상기 풀다운 전압 레벨에 따라 상기 메인 구동부의 풀다운단을 구동하기 위한 제 3 및 제 4구동신호를 출력하는 제 3 및 제 4프리 드라이버를 포함하는 것을 특징으로 하는 저전압 차동 신호 전송기. And a third and fourth pre-drivers for outputting third and fourth driving signals for driving the pull-down end of the main driving unit according to the pull-down voltage level.
  3. 제 2항에 있어서, 상기 메인 구동부는 The method of claim 2, wherein the main drive unit
    상기 제 1구동전압의 인가단과 제 1차동 출력단 사이에 연결되어 상기 제 1구동신호에 의해 동작하는 제 1스위칭 소자; A first switching element connected between the application terminal of the first driving voltage and the first differential output terminal and operated by the first driving signal;
    상기 제 1구동전압의 인가단과 제 2차동 출력단 사이에 연결되어 상기 제 2구동신호에 의해 동작하는 제 2스위칭 소자; A second switching element connected between the application terminal of the first driving voltage and the second differential output terminal and operated by the second driving signal;
    상기 제 1차동 출력단과 그라운드 전압단 사이에 연결되어 상기 제 4구동신호에 의해 동작하는 제 3스위칭 소자; A third switching element connected between the first differential output terminal and the ground voltage terminal and operated by the fourth driving signal;
    상기 제 2차동 출력단과 상기 그라운드 전압단 사이에 연결되어 상기 제 3구동신호에 의해 동작하는 제 4스위칭 소자를 포함하는 것을 특징으로 하는 저전압 차동 신호 전송기. And a fourth switching element connected between the second differential output terminal and the ground voltage terminal and operated by the third driving signal.
  4. 제 3항에 있어서, 상기 제 1스위칭 소자와 상기 제 2스위칭 소자는 동일한 크기를 갖는 것을 특징으로 하는 저전압 차동 신호 전송기.4. The low voltage differential signal transmitter of claim 3, wherein the first switching element and the second switching element have the same size.
  5. 제 3항에 있어서, 상기 제 3스위칭 소자와 상기 제 4스위칭 소자는 동일한 크기를 갖는 것을 특징으로 하는 저전압 차동 신호 전송기.4. The low voltage differential signal transmitter of claim 3, wherein the third switching element and the fourth switching element have the same size.
  6. 제 2항에 있어서, 상기 제 1구동신호와 상기 제 3구동신호는 상기 제 2구동신호, 상기 제 4구동신호와 반대 위상을 갖는 것을 특징으로 하는 저전압 차동 신호 전송기.The low voltage differential signal transmitter of claim 2, wherein the first driving signal and the third driving signal have a phase opposite to that of the second driving signal and the fourth driving signal.
  7. 제 1항에 있어서, 상기 메인 구동부는 상기 복수의 스위칭 소자와 상기 차동 출력단 사이에 각각 연결된 복수의 저항을 더 포함하는 것을 특징으로 하는 저전압 차동 신호 전송기. The low voltage differential signal transmitter of claim 1, wherein the main driver further comprises a plurality of resistors respectively connected between the plurality of switching elements and the differential output terminal.
  8. 제 1항에 있어서, 상기 복수의 프리 드라이버의 개수는 상기 복수의 스위칭 소자의 개수와 대응되는 것을 특징으로 하는 저전압 차동 신호 전송기. The low voltage differential signal transmitter of claim 1, wherein the number of the plurality of pre-drivers corresponds to the number of the plurality of switching elements.
  9. 제 1항에 있어서, The method of claim 1,
    상기 풀업전압을 생성하여 상기 입력 구동부에 공급하는 풀업 제어부; 및 A pull-up control unit generating the pull-up voltage and supplying the pull-up voltage to the input driver; And
    상기 풀다운전압을 생성하여 상기 입력 구동부에 공급하는 풀다운 제어부를 더 포함하는 것을 특징으로 하는 저전압 차동 신호 전송기. And a pull-down control unit generating the pull-down voltage and supplying the pull-down voltage to the input driver.
  10. 제 9항에 있어서, 상기 풀업 제어부는 The method of claim 9, wherein the pull-up control unit
    전원전압을 레귤레이팅하여 고전압을 생성하는 고전압 발생기; A high voltage generator for generating a high voltage by regulating a power supply voltage;
    제 2구동전압을 생성하는 전압 발생기; A voltage generator for generating a second driving voltage;
    상기 고전압과 피드백 전압을 비교 및 증폭하는 제 1증폭기; A first amplifier for comparing and amplifying the high voltage and the feedback voltage;
    상기 제 2구동전압의 인가단과 상기 피드백 전압의 출력단 사이에 연결되어 상기 제 1증폭기의 출력에 의해 선택적으로 턴 온 되는 제 5스위칭 소자; A fifth switching device connected between the application terminal of the second driving voltage and the output terminal of the feedback voltage and selectively turned on by the output of the first amplifier;
    상기 제 5스위칭 소자와 그라운드 전압단 사이에 연결된 제 1정전류원; 및 A first constant current source connected between the fifth switching element and a ground voltage terminal; And
    상기 제 1증폭기의 출력에 대응하여 상기 풀업전압 레벨을 조정하는 풀업전압 생성부를 포함하는 것을 특징으로 하는 저전압 차동 신호 전송기. And a pull-up voltage generator for adjusting the pull-up voltage level in response to the output of the first amplifier.
  11. 제 10항에 있어서, 상기 제 5스위칭 소자는 상기 메인 구동부의 풀업단 스위칭 소자와 동일한 크기를 갖는 것을 특징으로 하는 저전압 차동 신호 전송기. The low voltage differential signal transmitter of claim 10, wherein the fifth switching device has the same size as the pull-up switching device of the main driver.
  12. 제 10항에 있어서, 상기 제 5스위칭 소자와 상기 제 1정전류원 사이에 연결된 제 1저항을 더 포함하는 것을 특징으로 하는 저전압 차동 신호 전송기. 11. The low voltage differential signal transmitter of claim 10, further comprising a first resistor coupled between the fifth switching element and the first constant current source.
  13. 제 9항에 있어서, 상기 풀다운 제어부는 The method of claim 9, wherein the pull-down control unit
    전원전압을 레귤레이팅하여 저전압을 생성하는 저전압 발생기; A low voltage generator for regulating a supply voltage to produce a low voltage;
    상기 저전압과 피드백 전압을 비교 및 증폭하는 제 2증폭기; A second amplifier for comparing and amplifying the low voltage and the feedback voltage;
    그라운드 전압단과 상기 피드백 전압의 출력단 사이에 연결되어 상기 제 2증폭기의 출력에 의해 선택적으로 턴 온 되는 제 6스위칭 소자; A sixth switching element connected between a ground voltage terminal and an output terminal of the feedback voltage and selectively turned on by an output of the second amplifier;
    상기 제 6스위칭 소자와 상기 전원전압의 인가단 사이에 연결된 제 2정전류원; 및 A second constant current source connected between the sixth switching element and the supply terminal of the power supply voltage; And
    상기 제 2증폭기의 출력에 대응하여 상기 풀다운전압 레벨을 조정하는 풀다운전압 생성부를 포함하는 것을 특징으로 하는 저전압 차동 신호 전송기. And a pull-down voltage generator for adjusting the pull-down voltage level in response to the output of the second amplifier.
  14. 제 13항에 있어서, 상기 제 6스위칭 소자는 상기 메인 구동부의 풀다운단 스위칭 소자와 동일한 크기를 갖는 것을 특징으로 하는 저전압 차동 신호 전송기. The low voltage differential signal transmitter of claim 13, wherein the sixth switching element has the same size as the pull-down switching element of the main driver.
  15. 제 13항에 있어서, 상기 제 6스위칭 소자와 상기 제 2정전류원 사이에 연결된 제 2저항을 더 포함하는 것을 특징으로 하는 저전압 차동 신호 전송기.14. The low voltage differential signal transmitter of claim 13, further comprising a second resistor coupled between the sixth switching element and the second constant current source.
PCT/KR2015/004147 2014-05-08 2015-04-27 Low-voltage differential signalling transmitter WO2015170845A1 (en)

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