WO2015165214A1

WO2015165214A1 - Device and method for image deinterlacing, and computer storage medium

Info

Publication number: WO2015165214A1
Application number: PCT/CN2014/088138
Authority: WO
Inventors: 高峰
Original assignee: 深圳市中兴微电子技术有限公司
Priority date: 2014-04-30
Filing date: 2014-10-08
Publication date: 2015-11-05
Also published as: CN105025241A; CN105025241B

Abstract

Disclosed are a device and method for image deinterlacing, and a computer storage medium. The method comprises: determining, according to a received deinterlacing mode instruction, a deinterlacing mode for image data to be processed, performing deinterlacing processing on the image data to be processed by using a deinterlacing logic corresponding to the determined deinterlacing mode, and closing deinterlacing logics other than the deinterlacing logic corresponding to the determined deinterlacing mode.

Description

一种图像去隔行装置、方法及计算机存储介质Image deinterlacing device, method and computer storage medium

技术领域Technical field

本发明涉及图像处理技术领域，尤其涉及一种图像去隔行装置、方法及计算机存储介质。The present invention relates to the field of image processing technologies, and in particular, to an image deinterlacing apparatus, method, and computer storage medium.

背景技术Background technique

在图像处理技术领域中，去隔行技术可将隔行图像视频序列转换为逐行图像视频序列，以消除隔行视频序列的缺陷，提高画面的清晰度。目前，广泛采用的去隔行方法包括：线性去隔行算法(Linear Deinterlacing Algorithm)、非线性去隔行算法(Nonlinear Deinterlaeing Algorithm)、运动自适应去隔行算法(Motion Adaptive Deinterlacing Algorithm)以及运动补偿算法。其中，线性去隔行算法和非线性去隔行算法较为简单，但是，对于剧烈运动视频图像的去隔行处理效果不太理想；而运动自适应去隔行算法和运动补偿算法相对复杂，硬件消耗较多，对于剧烈运动视频图像的去隔行处理效果要优于线性去隔行算法和非线性去隔行算法。In the field of image processing technology, deinterlacing technology can convert interlaced image video sequences into progressive video sequences to eliminate the defects of interlaced video sequences and improve the sharpness of the image. At present, widely used deinterlacing methods include: Linear Deinterlacing Algorithm, Nonlinear Deinterlaeing Algorithm, Motion Adaptive Deinterlacing Algorithm, and Motion Compensation Algorithm. Among them, the linear deinterlacing algorithm and the nonlinear deinterlacing algorithm are relatively simple, but the deinterlacing processing effect on the strenuous motion video image is not ideal; while the motion adaptive deinterlacing algorithm and the motion compensation algorithm are relatively complex, and the hardware consumes more. The deinterlacing effect of the strenuous motion video image is better than the linear deinterlacing algorithm and the nonlinear deinterlacing algorithm.

目前，去隔行装置仅适用于固定的运动场景，从而不利于去隔行装置的广泛使用。Currently, de-interlacing devices are only suitable for fixed motion scenes, which is not conducive to the widespread use of de-interlacing devices.

发明内容Summary of the invention

针对现有技术存在的问题，本发明实施例提供一种图像去隔行装置、方法及计算机存储介质。In an embodiment of the present invention, an image deinterlacing apparatus, a method, and a computer storage medium are provided.

本发明实施例提供了一种图像去隔行装置，所述装置包括：配置模块及去隔行模块；其中，An embodiment of the present invention provides an image deinterlacing device, where the device includes: a configuration module and a deinterlacing module;

所述配置模块，配置为根据接收的去隔行模式指令，确定待处理图像数据的去隔行模式；The configuration module is configured to determine an image to be processed according to the received deinterlace mode instruction Deinterlace mode of data;

所述去隔行模块，配置为采用配置模块确定的去隔行模式对应的去隔行逻辑对所述待处理图像数据进行去隔行处理，并关闭除所述确定的去隔行模式对应的去隔行逻辑外的其它去隔行逻辑。The deinterlacing module is configured to deinterlace the image data to be processed by deinterlacing logic corresponding to the deinterlacing mode determined by the configuration module, and close the deinterlacing logic corresponding to the determined deinterlacing mode. Other deinterlacing logic.

上述方案中，所述配置模块，配置为：根据接收的去隔行模式指令，将去隔行寄存器进行相应去隔行模式的指示配置；In the above solution, the configuration module is configured to perform, according to the received deinterlace mode instruction, the deinterlace register to perform an indication of the corresponding deinterlace mode;

相应地，所述去隔行模块，配置为根据所述去隔行寄存器的指示配置，采用对应的去隔行逻辑对所述待处理图像数据进行去隔行处理，并关闭除所述确定的去隔行模式对应的去隔行逻辑外的其它去隔行逻辑。Correspondingly, the deinterlacing module is configured to deinterlace the image data to be processed by using corresponding deinterlacing logic according to the indication configuration of the deinterlace register, and close the deinterlacing mode corresponding to the determined deinterlacing mode. Deinterlacing logic other than deinterlacing logic.

上述方案中，所述配置模块，还配置为：In the foregoing solution, the configuration module is further configured to:

根据待处理图像数据的长和宽，在分辨率寄存器中对待处理图像数据的分辨率进行配置；并在使能寄存器中配置用于使能所述去隔行模块的第一使能信号。The resolution of the image data to be processed is configured in the resolution register according to the length and width of the image data to be processed; and the first enable signal for enabling the deinterlacing module is configured in the enable register.

上述方案中，所述配置模块，还配置为当确定的去隔行模式对应的去隔行逻辑为带有运动检测的四场去隔行逻辑时，在使能寄存器中配置用于使能所述去隔行模块的第一使能信号之前，在阈值寄存器中配置第一阈值以及第二阈值；所述第一阈值以及第二阈值用于判断像素是处于运动状态或静止状态。In the above solution, the configuration module is further configured to: when the deinterlace logic corresponding to the deinterlace mode is determined to be four-field deinterlacing logic with motion detection, configured in the enable register to enable the deinterlacing Before the first enable signal of the module, the first threshold and the second threshold are configured in the threshold register; the first threshold and the second threshold are used to determine whether the pixel is in a motion state or a stationary state.

上述方案中，所述配置模块，还配置为当一帧图像数据处理完毕，且后续还有图像数据需要处理时，在中断寄存器中配置用于清除中断信号的第二使能信号，并重新对分辨率寄存器进行配置，或者重新对分辨率寄存器和阈值寄存器进行配置。In the above solution, the configuration module is further configured to: when one frame of image data is processed, and subsequent image data needs to be processed, configure a second enable signal for clearing the interrupt signal in the interrupt register, and re-pair The resolution registers are configured or the resolution registers and threshold registers are reconfigured.

上述方案中，所述装置还包括：顶层模块、及同步模块；其中，In the above solution, the device further includes: a top module, and a synchronization module; wherein

所述顶层模块，配置为提供所述装置与外部连接的输入输出接口；The top layer module is configured to provide an input and output interface of the device and an external connection;

所述同步模块，配置为将所述配置模块配置的各寄存器的参数同步至所述去隔行模块。The synchronization module is configured to synchronize parameters of each register configured by the configuration module to The deinterlacing module.

上述方案中，所述同步模块，配置为：将各寄存器的时钟通过握手信号同步为所述去隔行模块的工作时钟。In the above solution, the synchronization module is configured to synchronize the clock of each register by the handshake signal to the working clock of the deinterlacing module.

上述方案中，所述去隔行模块，还配置为采用随机存取存储器(ram，random access memory)复用的方式，对所述待处理图像数据进行去隔行处理。In the above solution, the deinterlacing module is further configured to perform deinterlacing processing on the image data to be processed by using a random access memory (ram) multiplexing method.

本发明实施例还提供了一种图像去隔行方法，所述方法包括：An embodiment of the present invention further provides an image deinterlacing method, where the method includes:

根据接收的去隔行模式指令，确定待处理图像数据的去隔行模式；Deinterlacing the image data to be processed according to the received deinterlace mode command;

采用确定的去隔行模式对应的去隔行逻辑对所述待处理图像数据进行去隔行处理，并关闭除所述确定的去隔行模式对应的去隔行逻辑外的其它去隔行逻辑。Deinterlacing the image data to be processed by de-interlacing logic corresponding to the determined deinterlacing mode, and turning off deinterlacing logic other than the deinterlacing logic corresponding to the determined deinterlacing mode.

上述方案中，所述根据接收的去隔行模式指令，确定待处理图像数据的去隔行模式，包括：In the above solution, the deinterlacing mode of the image data to be processed is determined according to the received deinterlacing mode instruction, including:

根据接收的去隔行模式指令，将去隔行寄存器进行相应去隔行模式的指示配置，确定待处理图像数据的去隔行模式；De-interlacing the deinterlace mode according to the received de-interlace mode instruction, and determining the de-interlaced mode of the image data to be processed;

相应地，根据所述去隔行寄存器的指示配置，采用对应的去隔行逻辑对所述待处理图像数据进行去隔行处理，并关闭除所述确定的去隔行模式对应的去隔行逻辑外的其它去隔行逻辑。Correspondingly, according to the indication configuration of the deinterlace register, deinterlacing the image data to be processed by using corresponding deinterlacing logic, and turning off the deinterlacing logic corresponding to the determined deinterlacing mode Interlaced logic.

上述方案中，在所述确定的去隔行模式对应的去隔行逻辑对所述待处理图像数据进行去隔行处理，并关闭除所述确定的去隔行模式对应的去隔行逻辑外的其它去隔行逻辑之前，所述方法还包括：In the above solution, the deinterlacing logic corresponding to the determined deinterlacing mode deinterlaces the image data to be processed, and turns off deinterlacing logic other than the deinterlacing logic corresponding to the determined deinterlacing mode. Previously, the method further includes:

上述方案中，当确定的去隔行模式对应的去隔行逻辑为带有运动检测的四场去隔行逻辑时，在使能寄存器中配置用于使能所述去隔行模块的第一使能信号之前，所述方法还包括：In the above solution, when the de-interlaced mode determined by the deinterlacing mode is determined to have motion detection The method further includes: before configuring the first enable signal for enabling the deinterlacing module in the enable register.

在阈值寄存器中配置第一阈值以及第二阈值；所述第一阈值以及第二阈值用于判断像素是处于运动状态或静止状态。A first threshold and a second threshold are configured in the threshold register; the first threshold and the second threshold are used to determine whether the pixel is in a motion state or a stationary state.

上述方案中，当一帧图像数据处理完毕，且后续还有图像数据需要处理时，所述方法还包括：In the above solution, when one frame of image data is processed, and the image data needs to be processed subsequently, the method further includes:

在中断寄存器中配置用于清除中断信号的第二使能信号，并重新对分辨率寄存器进行配置，或者重新对分辨率寄存器和阈值寄存器进行配置。A second enable signal for clearing the interrupt signal is configured in the interrupt register, and the resolution register is reconfigured or the resolution register and threshold register are reconfigured.

上述方案中，配置完各寄存器，且在所述确定的去隔行模式对应的去隔行逻辑对所述待处理图像数据进行去隔行处理，并关闭除所述确定的去隔行模式对应的去隔行逻辑外的其它去隔行逻辑之前，所述方法还包括：In the above solution, each register is configured, and the deinterlacing logic corresponding to the determined deinterlacing mode performs deinterlacing processing on the image data to be processed, and turns off deinterlacing logic corresponding to the determined deinterlacing mode. Before the other deinterlacing logic, the method further includes:

将配置的各寄存器的参数同步至图像去隔行装置的去隔行模块。Synchronize the parameters of the configured registers to the deinterlacing module of the image deinterlacer.

上述方案中，所述将配置的各寄存器的参数同步至去隔行处理的装置的去隔行模块，为：In the above solution, the deinterlacing module that synchronizes the parameters of the configured registers to the deinterlacing device is:

将各寄存器的时钟通过握手信号同步为所述去隔行模块的工作时钟。The clocks of the respective registers are synchronized by the handshake signal to the operating clock of the deinterlacing module.

上述方案中，在对所述待处理图像进行去隔行处理时，所述方法还包括：采用ram复用的方式，对所述待处理图像数据进行去隔行处理。In the above solution, when the image to be processed is deinterlaced, the method further includes: deinterlacing the image data to be processed by using ram multiplexing.

上述方案中，所述采用ram复用的方式，对所述待处理图像数据进行去隔行处理，包括：In the above solution, the ram multiplexing method is used to perform deinterlacing processing on the image data to be processed, including:

在不使能去隔行模式下，ram配置为存储待处理数据，以使非同步输入的数据进行同步输出；In the de-interlace mode, the ram is configured to store the data to be processed, so that the asynchronous input data is synchronously output;

在场内去隔行模式或带有运动检测的四场去隔行模式下，所述ram，配置为存储待处理图像数据中的第N行图像数据及待处理图像数据中的第N-1行图像数据，以使在场内去隔行模式对应的去隔行逻辑或带有运动检测的四场去隔行模式对应的去隔行逻辑对所述待处理图像数据进行相应的去隔行处理。In the inter-bank deinterlacing mode or the four-field deinterlacing mode with motion detection, the ram is configured to store the Nth line image data in the image data to be processed and the N-1th line image data in the image data to be processed. The deinterlacing logic corresponding to the deinterlacing logic corresponding to the interlaced mode in the field or the deinterlacing logic corresponding to the four-field deinterlacing mode with motion detection is correspondingly performed on the image data to be processed. Interlaced processing.

本发明实施例提供的图像去隔行装置、方法及计算机存储介质，根据接收的去隔行模式指令，确定待处理图像数据的去隔行模式，采用确定的去隔行模式对应的去隔行逻辑对所述待处理图像数据进行去隔行处理，并关闭除所述确定的去隔行模式对应的去隔行逻辑外的其它去隔行逻辑；如此，用户可以在不同的运动场景下自行配置去隔行模式，从而使该装置适用于更多场景。The image deinterlacing apparatus, method and computer storage medium provided by the embodiments of the present invention determine a deinterlacing mode of image data to be processed according to the received deinterlacing mode instruction, and use the deinterlacing logic corresponding to the determined deinterlacing mode to Processing the image data for deinterlacing processing, and turning off deinterlacing logic other than the deinterlacing logic corresponding to the determined deinterlacing mode; thus, the user can configure the deinterlacing mode in different motion scenarios, thereby making the device Suitable for more scenes.

附图说明DRAWINGS

在附图(其不一定是按比例绘制的)中，相似的附图标记可在不同的视图中描述相似的部件。具有不同字母后缀的相似附图标记可表示相似部件的不同示例。附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。In the drawings, which are not necessarily to scale, the Like reference numerals with different letter suffixes may indicate different examples of similar components. The drawings generally illustrate the various embodiments discussed herein by way of example and not limitation.

图1为本发明实施例一提供的一种图像去隔行装置结构示意图；1 is a schematic structural diagram of an image deinterlacing apparatus according to Embodiment 1 of the present invention;

图2为本发明实施例一提供的另一种图像去隔行装置结构示意图；FIG. 2 is a schematic structural diagram of another image deinterlacing apparatus according to Embodiment 1 of the present invention; FIG.

图3为本发明实施例一提供的去隔行模块的结构示意图；3 is a schematic structural diagram of a deinterlacing module according to Embodiment 1 of the present invention;

图4为本发明实施例一、二提供的不使能去隔行模式下无数据输入时的数据流向示意图；4 is a schematic diagram of data flow when no data is input in an de-interlaced mode according to

Embodiments

1 and 2 of the present invention;

图5为本发明实施例一、二提供的不使能去隔行模式下，向通道1中输入一个单位的图像数据时的数据流向示意图；5 is a schematic diagram of data flow when inputting one unit of image data into the channel 1 in the de-interlace mode according to the first embodiment of the present invention;

图6为本发明实施例一、二提供的不使能去隔行模式下，向通道1中输入两个单位的图像数据、向通道2中输入一个单位的图像数据时的数据流向示意图；FIG. 6 is a schematic diagram of data flow when inputting two units of image data into the channel 1 and inputting one unit of image data into the channel 2 in the de-interlace mode according to the first embodiment of the present invention;

图7为本发明实施例一、二提供的不使能去隔行模式下通过通道1及通道2同步输出数据时的数据流向示意图；FIG. 7 is a schematic diagram of data flow when data is synchronously outputted through channel 1 and channel 2 in a de-interlaced mode according to

Embodiments

1 and 2 of the present invention;

图8为本发明实施例一、二提供的去隔行逻辑模式开启时的数据流向示意图；FIG. 8 is a flow of data when the deinterlacing logic mode is turned on according to the first embodiment of the present invention. schematic diagram;

图9为本发明实施例一、二提供的行平均插值方法示意图；FIG. 9 is a schematic diagram of a row average interpolation method according to

Embodiments

1 and 2 of the present invention; FIG.

图10为本发明实施例一、二提供的带有运动检测的四场去隔行方法示意图；10 is a schematic diagram of a four-field deinterlacing method with motion detection according to

Embodiments

1 and 2 of the present invention;

图11为本发明实施例二提供的图像去隔行的方法流程示意图。FIG. 11 is a schematic flowchart of a method for deinterlacing an image according to Embodiment 2 of the present invention.

具体实施方式Detailed ways

在本发明的各种实施例中，根据接收的去隔行模式指令，确定待处理图像数据的去隔行模式，采用确定的去隔行模式对应的去隔行逻辑对所述待处理图像数据进行去隔行处理，并关闭除所述确定的去隔行模式对应的去隔行逻辑外的其它去隔行逻辑。In various embodiments of the present invention, determining a deinterlacing mode of image data to be processed according to the received deinterlacing mode instruction, deinterlacing the image data to be processed by deinterlacing logic corresponding to the determined deinterlacing mode And turning off deinterlacing logic other than the deinterlacing logic corresponding to the determined deinterlacing mode.

下面通过附图及具体实施例对本发明的技术方案做进一步的详细说明。The technical solution of the present invention will be further described in detail below through the accompanying drawings and specific embodiments.

实施例一 Embodiment 1

本实施例提供一种图像去隔行装置，如图1所示，所述装置包括：配置模块11、去隔行模块12；其中；The embodiment provides an image deinterlacing device. As shown in FIG. 1 , the device includes: a configuration module 11 and a deinterlacing module 12;

所述配置模块11，配置为根据接收的去隔行模式指令，确定待处理图像数据的去隔行模式；The configuration module 11 is configured to determine a deinterlace mode of the image data to be processed according to the received deinterlace mode instruction;

所述去隔行模块12，配置为采用配置模块11确定的去隔行模式对应的去隔行逻辑对所述待处理图像数据进行去隔行处理，并关闭除所述确定的去隔行模式对应的去隔行逻辑外的其它去隔行逻辑。The deinterlacing module 12 is configured to deinterlace the image data to be processed by deinterlacing logic corresponding to the deinterlacing mode determined by the configuration module 11, and turn off the deinterlacing logic corresponding to the determined deinterlacing mode. Other deinterlacing logic.

这里，所述配置模块11，具体配置为根据接收的去隔行模式指令，将去隔行寄存器进行相应去隔行模式的指示配置；Here, the configuration module 11 is specifically configured to perform an indication configuration of the deinterlace mode in the deinterlace mode according to the received deinterlace mode instruction;

相应地，所述去隔行模块12，配置为根据所述去隔行寄存器的指示配置，采用对应的去隔行逻辑对所述待处理图像数据进行去隔行处理，并关闭除所述确定的去隔行模式对应的去隔行逻辑外的其它去隔行逻辑。 Correspondingly, the deinterlacing module 12 is configured to deinterlace the image data to be processed by using corresponding deinterlacing logic according to the indication configuration of the deinterlace register, and turn off the deinterlacing mode except the determined Corresponding deinterlacing logic other than deinterlacing logic.

实际应用时，本发明实施例提供的图像去隔行装置中可以内置有三个去隔行逻辑，分别为：不使能去隔行逻辑、场内去隔行逻辑以及带有运动检测的四场去隔行逻辑；其中，不使能去隔行逻辑的功能是：将非同步输入的待处理图像数据进行同步输出；场内去隔行逻辑的功能是：分别对输入的待处理图像数据的Y分量及UV分量进行场内去隔行逻辑处理；带有运动检测的四场去隔行逻辑的功能是：分别对输入的待处理图像数据的Y分量及UV分量进行四场去隔行逻辑处理。In an actual application, the image deinterlacing device provided by the embodiment of the present invention may have three deinterlacing logics, namely: deinterlacing logic, intra-field deinterlacing logic, and four-field deinterlacing logic with motion detection; The function of not enabling the deinterlacing logic is: synchronously outputting the image data to be processed that is not synchronously input; the function of the deinterlacing logic in the field is: respectively performing the Y component and the UV component of the input image data to be processed. Internal deinterlacing logic processing; the function of the four-field deinterlacing logic with motion detection is to perform four-field deinterlacing logic processing on the Y component and the UV component of the input image data to be processed, respectively.

相应地，当接收的去隔行模式指令为不使能去隔行模式指示时，所述配置模块11可以根据接收的去隔行模式指令，将所述去隔行模式寄存器的状态位指令配置为00，从而实现对所述去隔行寄存器的去隔行模式的指示配置，以便向所述去隔行模块12表明待处理图像数据的去隔行模式为不使能去隔行模式；当接收的去隔行模式指令为场内去隔行模式指示时，所述配置模块11可以根据接收的去隔行模式指令，将所述去隔行模式寄存器的状态位指令配置为01，从而实现对所述去隔行寄存器的去隔行模式的指示配置，以便向所述去隔行模块12表明待处理图像数据的去隔行模式为场内去隔行模式；当接收的去隔行模式指令为带有运动检测的四场去隔行模式指示时，所述配置模块11可以根据接收的去隔行模式指令，将所述去隔行模式寄存器的状态位指令配置为10，从而实现对所述去隔行寄存器的去隔行模式的指示配置，以便向所述去隔行模块12表明待处理图像数据的去隔行模式为四场去隔行模式；其中，所述去隔行模式寄存器还可以预留一个状态位指令11，以便后续扩展应用。Correspondingly, when the received deinterlace mode instruction is to disable the deinterlace mode indication, the configuration module 11 may configure the status bit instruction of the deinterlace mode register to 00 according to the received deinterlace mode instruction, thereby Implementing an indication configuration of the deinterlace mode of the deinterlacing register to indicate to the deinterlacing module 12 that the deinterlacing mode of the image data to be processed is not deinterlacing mode; when the received deinterlacing mode instruction is in-field When the deinterlace mode is instructed, the configuration module 11 may configure the status bit instruction of the deinterlace mode register to be 01 according to the received deinterlace mode instruction, thereby implementing the indication configuration of the deinterlace mode of the deinterlace register. In order to indicate to the deinterlacing module 12 that the deinterlacing mode of the image data to be processed is an intra-field deinterlacing mode; when the received deinterlacing mode command is a four-field deinterlacing mode indication with motion detection, the configuration module 11 may configure the status bit instruction of the deinterlace mode register to 10 according to the received deinterlace mode instruction, thereby Implementing an indication configuration of the deinterlace mode of the deinterlace register to indicate to the deinterlacing module 12 that the deinterlacing mode of the image data to be processed is a four-field deinterlacing mode; wherein the deinterlacing mode register is further A status bit instruction 11 is left for subsequent expansion of the application.

这里，所述去隔行模块12采用所述配置模块11确定的去隔行模式对应的去隔行逻辑对所述待处理图像数据进行去隔行处理，并关闭除所述确定的去隔行模式对应的去隔行逻辑外的其它去隔行逻辑之前，所述配置模块11还需要对各寄存器的相关信息进行配置，以便所述去隔行模块12能采用相应的去隔行逻辑对所述待处理数据进行去隔行处理；所述配置模块11需要配置的各寄存器的相关信息，具体可以包括：Here, the deinterlacing module 12 deinterlaces the image data to be processed by deinterlacing logic corresponding to the deinterlacing mode determined by the configuration module 11, and turns off deinterlacing corresponding to the determined deinterlacing mode. Before the deinterlacing logic outside the logic, the configuration module 11 also needs to configure related information of each register, so that the deinterlacing module 12 can De-interlacing the data to be processed by using the corresponding de-interlacing logic; the information about the respective registers to be configured by the configuration module 11 may specifically include:

所述配置模块11根据待处理图像数据的长和宽，在分辨率寄存器中对待处理图像数据的分辨率进行配置，以便去隔行模块12可以处理不同分辨率的图像数据；其中，实际应用时，一般场内去隔行逻辑和带有运动检测的四场去隔行逻辑要求待处理图像数据的分辨率为1920*1080；The configuration module 11 configures the resolution of the image data to be processed in the resolution register according to the length and width of the image data to be processed, so that the deinterlacing module 12 can process image data of different resolutions; The general field deinterlacing logic and the four-field deinterlacing logic with motion detection require the resolution of the image data to be processed to be 1920*1080;

当确定的去隔行模式为带有运动检测的四场去隔行模式时，所述配置模块11在阈值寄存器中配置第一阈值T1以及第二阈值T2；其中，在带有运动检测的四场去隔行模式下，所述第一阈值T1以及第二阈值T2用于判断像素是处于运动状态还是静止状态。When the determined deinterlacing mode is the four-field deinterlacing mode with motion detection, the configuration module 11 configures the first threshold T1 and the second threshold T2 in the threshold register; wherein, in the four fields with motion detection In the interlaced mode, the first threshold T1 and the second threshold T2 are used to determine whether the pixel is in a motion state or a stationary state.

当所述配置模块11将上述各寄存器配置完成后，所述配置模块11最后在使能(enable)寄存器中配置用于使能所述去隔行模块12的第一使能信号；具体地，当所述装置需要处理图像数据时，所述配置模块22将所述enable寄存器的第一使能信号配置为高电平，从而使能所述去隔行模块12，换句话说，启动所述去隔行模块12；当一帧图像数据处理完毕，且后续无图像数据需要处理时，所述配置模块22在所述enable寄存器中配置低电平，从而去使能所述去隔行模块12，换句话说，关闭所述去隔行模块12。After the configuration module 11 configures the above registers, the configuration module 11 finally configures a first enable signal for enabling the deinterlacing module 12 in an enable register; specifically, when When the device needs to process image data, the configuration module 22 configures the first enable signal of the enable register to a high level, thereby enabling the deinterlacing module 12, in other words, initiating the deinterlacing Module 12; when one frame of image data is processed and no subsequent image data needs to be processed, the configuration module 22 configures a low level in the enable register to disable the deinterlacing module 12, in other words The deinterlacing module 12 is turned off.

实际应用时，当一帧图像数据处理完毕后，且后续还有图像数据需要处理时，所述配置模块11还需要在中断寄存器中配置用于清除中断信号的第二使能信号，并重新对分辨率寄存器及阈值寄存器进行配置，以进行下一帧图像数据的处理；这里，当一帧图像处理完毕之后，所述装置会产生中断信号，因此需要将所述中断寄存器的第二使能信号配置为高电平，以清除中断信号，从而进行后续图像数据的处理。In practical application, when one frame of image data is processed, and then there is still image data to be processed, the configuration module 11 further needs to configure a second enable signal for clearing the interrupt signal in the interrupt register, and re-pair The resolution register and the threshold register are configured to perform processing of the next frame of image data; here, after one frame of image processing is completed, the device generates an interrupt signal, so the second enable signal of the interrupt register needs to be Configured high to clear the interrupt signal for subsequent image data processing.

如图2所示，所述装置还包括：顶层模块21、及同步模块22；其中，As shown in FIG. 2, the device further includes: a top layer module 21, and a synchronization module 22;

所述顶层模块21，配置为提供所述装置与外部连接的输入输出接口； The top layer module 21 is configured to provide an input and output interface of the device and an external connection;

所述同步模块22，配置为将所述配置模块11配置的各寄存器的参数同步至所述去隔行模块12。The synchronization module 22 is configured to synchronize parameters of the registers configured by the configuration module 11 to the deinterlacing module 12.

具体地，所述同步模块22将各寄存器的时钟通过握手信号同步为所述去隔行模块12的工作时钟。Specifically, the synchronization module 22 synchronizes the clocks of the respective registers to the operating clock of the deinterlacing module 12 by the handshake signal.

更具体地，当所述配置模块11对上述各寄存器配置完成后，所述同步模块22，将各寄存器的时钟同步请求发送至所述去隔行模块12，并将所述去隔行模块12的时钟同步请求响应发送至所述同步模块22，从而通过时钟同步请求及时钟同步请求响应将所述各寄存器中的配置时钟同步为所述去隔行模块12的工作时钟。More specifically, after the configuration module 11 completes the configuration of each of the above registers, the synchronization module 22 sends a clock synchronization request of each register to the deinterlacing module 12, and the clock of the deinterlacing module 12 A synchronization request response is sent to the synchronization module 22 to synchronize the configuration clocks in the respective registers to the operating clock of the deinterlacing module 12 by a clock synchronization request and a clock synchronization request response.

其中，在输入第一帧图像数据之前，各寄存器都处于有效状态，因此能对第一帧图像数据进行相应的处理；所述各寄存器包括：分辨率寄存器、去隔行寄存器、中断寄存器、以及enable寄存器；这里，当确定的去隔行模式为带有运动检测的四场去隔行模式时，所述各寄存器还包括：阈值寄存器。Wherein, before inputting the first frame image data, each register is in an active state, so that the first frame image data can be processed correspondingly; the registers include: a resolution register, a deinterlace register, an interrupt register, and enable Register; here, when the determined deinterlacing mode is a four-field deinterlacing mode with motion detection, the registers further include: a threshold register.

这里，在进行第一帧图像数据处理时，当enable寄存器的第二使能信号处于高电平状态时，通过所述顶层模块21接收第一帧待处理图像数据后，所述去隔行模块12根据预先配置的分辨率寄存器的分辨率确定第一帧图像数据的分辨率，根据不使能去隔行模式对应的去隔行逻辑对所述待处理图像数据进行去隔行处理，并关闭场内去隔行模式对应的去隔行逻辑及带有运动检测的四场去隔行模式对应的逻辑；或者，根据场内去隔行模式对应的去隔行逻辑对所述待处理图像数据进行去隔行处理，并关闭不使能去隔行模式对应的去隔行逻辑及带有运动检测的四场去隔行模式对应的去隔行逻辑；或者，根据带有运动检测的去隔行模式对应的去隔行逻辑对所述待处理图像数据进行去隔行处理，并关闭不使能去隔行模式对应的去隔行逻辑及场内去隔行模式对应的去隔行逻辑。 Here, when the first frame image data processing is performed, when the second enable signal of the enable register is in the high level state, after the first frame module 21 receives the first frame to be processed image data, the deinterlacing module 12 Determining the resolution of the image data of the first frame according to the resolution of the pre-configured resolution register, deinterlacing the image data to be processed according to the deinterlacing logic corresponding to the deinterlacing mode, and turning off the deinterlacing in the field The de-interlacing logic corresponding to the mode and the logic corresponding to the four-field deinterlacing mode with motion detection; or de-interlacing the image data to be processed according to de-interlacing logic corresponding to the de-interlacing mode in the field, and shutting down The deinterlacing logic corresponding to the interlaced mode corresponding to the interlaced mode and the deinterlacing logic corresponding to the four-field deinterlacing mode with motion detection; or the deinterlacing logic corresponding to the deinterlacing mode with motion detection Deinterlace processing, and turn off the deinterlacing logic corresponding to the interlaced mode and the deinterlacing logic corresponding to the deinterlacing mode in the field. Series.

其中，所述去隔行模块12在采用相应的去隔行逻辑对所述待处理图像数据进行去隔行处理时，还配置为采用ram复用的方式，对所述待处理图像数据进行去隔行处理。其中，所述ram包括：第一ram、第二ram、第三ram、第四ram；所述第一ram、第二ram、第三ram以及第四ram容量都为120*128；所述120代表ram的最大存储空间，所述128表示ram的位宽。The deinterlacing module 12 is configured to perform deinterlacing processing on the image data to be processed when the image data to be processed is deinterlaced by using the corresponding deinterlacing logic. The ram includes: a first ram, a second ram, a third ram, and a fourth ram; the first ram, the second ram, the third ram, and the fourth ram have a capacity of 120*128; Representing the maximum storage space of the ram, the 128 represents the bit width of the ram.

这里，所述采用ram复用的方式是指：在不使能去隔行模式下，所述第一ram、第二ram、第三ram及第四ram，配置为存储待处理数据，以便能将非同步输入的数据进行同步输出；在场内去隔行模式或带有运动检测的四场去隔行模式下，所述第一ram、第二ram、第三ram及第四ram，配置为存储待处理图像数据中的第N行图像数据及待处理图像数据中的第N-1行图像数据，以便能在场内去隔行模式对应的去隔行逻辑或带有运动检测的四场去隔行模式对应的去隔行逻辑下，对待处理图像数据进行相应的去隔行处理。Here, the method of using ram multiplexing means that, in the de-interlace mode, the first ram, the second ram, the third ram, and the fourth ram are configured to store data to be processed, so that The asynchronous input data is synchronously outputted; in the inter-deinterlace mode or the four-field deinterlacing mode with motion detection, the first ram, the second ram, the third ram, and the fourth ram are configured to be stored for processing The Nth line image data in the image data and the N-1th line image data in the image data to be processed so as to be deinterlaced logic corresponding to the deinterlacing mode in the field or the four-field deinterlacing mode with motion detection Under the interlaced logic, the image data to be processed is subjected to corresponding deinterlacing processing.

如图3所示，所述去隔行模块12包括：数据输入子模块121、读数据子模块122、以及去隔行逻辑子模块123；其中，As shown in FIG. 3, the deinterlacing module 12 includes: a data input submodule 121, a read data submodule 122, and a deinterlacing logic submodule 123;

所述数据输入子模块121，配置为将输入的待处理图像数据存储至所有去隔行逻辑共用的ram中；The data input sub-module 121 is configured to store the input image data to be processed into a ram shared by all deinterlacing logics;

所述读数据子模块122，配置为读取ram中的待处理图像数据；The read data sub-module 122 is configured to read image data to be processed in the ram;

所述去隔行逻辑子模块123，配置为根据确定的去隔行模式对读取的待处理图像数据进行去隔行处理。The deinterlacing logic sub-module 123 is configured to perform deinterlacing processing on the read image data to be processed according to the determined deinterlacing mode.

具体地，当所述配置模块11根据接收的去隔行模式指令，将所述去隔行模式寄存器的状态位指令配置为00，即确定待处理图像数据的去隔行模式为不使能去隔行模式时，则会自动关闭场内去隔行模式及带有运动检测的四场去隔行模式对应的去隔行逻辑；这里，当前输入的图像数据可以是隔行视频序列，也可以是逐行视频序列；该装置可以包括四个输入通道，当输入的图像数据是隔行视频序列时，数据输入子模块121将隔行视频序列中奇数场的图像数据输入通道1中，将偶数场的图像数据输入通道2中；当输入的图像数据是逐行视频序列时，所述数据输入子模块121将逐行视频序列中奇数场的图像数据输入通道1中，将偶数场的图像数据输入通道2中；其中，所述通道1的输入地址为addr_in_1，输出地址为addr_out_1；通道2的输入地址为addr_in_2，输出地址为addr_out_2；如图4所示，在初始条件下，所述addr_in_1、addr_in_2、addr_out_1以及addr_out_2均为0。Specifically, when the configuration module 11 configures the status bit instruction of the deinterlace mode register to 00 according to the received deinterlace mode instruction, that is, when the deinterlacing mode of the image data to be processed is determined to be de-interlaced mode is disabled. , the deinterlacing mode corresponding to the deinterlacing mode in the field and the four deinterlacing modes with motion detection are automatically turned off; here, the currently input image data may be an interlaced video sequence or a progressive video sequence; Can include four input channels, When the input image data is an interlaced video sequence, the data input sub-module 121 inputs the image data of the odd field in the interlaced video sequence into the channel 1, and inputs the image data of the even field into the channel 2; when the input image data is progressive In the video sequence, the data input sub-module 121 inputs the image data of the odd field in the progressive video sequence into the channel 1, and inputs the image data of the even field into the channel 2; wherein the input address of the channel 1 is addr_in_1, The output address is addr_out_1; the input address of channel 2 is addr_in_2, and the output address is addr_out_2; as shown in FIG. 4, under initial conditions, the addr_in_1, addr_in_2, addr_out_1, and addr_out_2 are all 0.

这里，所述输出子模块125可通过通道1及所述通道2将非同步输入的图像数据的Y分量同步输出至显示装置；将非同步输入的图像数据的UV分量同步输出显示装置；当所述图像数据的Y分量及UV分量同步输出至显示装置后，即可在显示装置中看到经不使能去隔行逻辑处理后的图像；其中，所述显示装置可以为手机、电脑等。Here, the output sub-module 125 can synchronously output the Y component of the asynchronously input image data to the display device through the channel 1 and the channel 2; synchronously output the UV component of the asynchronously input image data to the display device; After the Y component and the UV component of the image data are synchronously output to the display device, the image after the deinterlacing logic is not enabled can be seen in the display device; wherein the display device can be a mobile phone, a computer, or the like.

这里，以Y分量为例，如图5所示，当所述数据输入子模块121通过通道1输入一个单位的待处理图像数据后，将所述一个单位的待处理图像数据的Y分量存储到第一ram中，所述addr_in_1的地址就加1，输出addr_out_1不变，当所述数据输入子模块121没有向通道2中输入待处理图像数据时，所述addr_in_2的地址不变，所述addr_out_2也不变；其中，所述一个单位的图像数据包括十六个像素。Here, taking the Y component as an example, as shown in FIG. 5, when the data input sub-module 121 inputs one unit of image data to be processed through the channel 1, the Y component of the one-unit image data to be processed is stored to In the first ram, the address of the addr_in_1 is incremented by 1, and the output addr_out_1 is unchanged. When the data input sub-module 121 does not input the image data to be processed into the channel 2, the address of the addr_in_2 is unchanged, and the addr_out_2 Also unchanged; wherein the image data of the one unit includes sixteen pixels.

如图6所示，当所述数据输入子模块121通过通道1再输入一个单位的图像数据时，也将该图像数据的Y分量存储到第一ram中，所述addr_in_1的地址为2，输出addr_out_1不变；当所述数据输入子模块121向通道2中输入一个单位的图像数据时，将该图像数据的Y分量存储到第三ram中，所述addr_in_2的地址为1，所述addr_out_2也不变；可以看出，通道1的输入地址不等于通道1的输出地址，通道2的输入地址也不等于通道2的输出地址，即满足了(addr_in_1！＝addr_out_1)&&(addr_in_2！＝addr_out_2)，这时，如图7所示，当所述输出子模块125通过通道1及通道2同时输出一个Y分量的单位数据，所述addr_out_1和addr_out_2同时加1，这样，对非同步输入的图像数据完成了同步输出；其中，所述第一ram和第三ram的位宽及存储空间完全相同，当输入地址addr_in_1、addr_in_2达到ram的上限时，addr_in_1和addr_in_2重新返回到0。As shown in FIG. 6, when the data input sub-module 121 re-enters one unit of image data through the channel 1, the Y component of the image data is also stored in the first ram, and the address of the addr_in_1 is 2, and the output is Addr_out_1 is unchanged; when the data input sub-module 121 inputs one unit of image data into the channel 2, the Y component of the image data is stored in the third ram, the address of the addr_in_2 is 1, and the addr_out_2 is also It is unchanged; it can be seen that the input address of channel 1 is not equal to the output address of channel 1, and the input address of channel 2 is not equal to the channel 2 The output address satisfies (addr_in_1!=addr_out_1)&&(addr_in_2!=addr_out_2). At this time, as shown in FIG. 7, when the output sub-module 125 simultaneously outputs a unit data of a Y component through the channel 1 and the channel 2 The addr_out_1 and addr_out_2 are simultaneously incremented by 1, so that the synchronous output of the image data of the asynchronous input is completed; wherein the bit width and the storage space of the first ram and the third ram are identical, when the input addresses addr_in_1, addr_in_2 are input. When the upper limit of ram is reached, addr_in_1 and addr_in_2 return to 0 again.

这里，对非同步输入的UV分量进行同步输出的处理流程与Y分量的处理流程类似，区别是所述数据输入子模块121将输入通道1中的待处理图像数据的UV分量是存储在第二ram中，将输入通道2中待处理图像数据的UV分量存储在第四ram中。Here, the processing flow for synchronously outputting the UV component of the asynchronous input is similar to the processing flow of the Y component, with the difference that the data input sub-module 121 stores the UV component of the image data to be processed in the input channel 1 in the second. In the ram, the UV component of the image data to be processed in the input channel 2 is stored in the fourth ram.

当所述配置模块11根据接收的去隔行模式指令，将所述去隔行模式寄存器的状态位指令配置为01，即确定待处理图像数据的去隔行模式为场内去隔行模式时，则会自动关闭不使能去隔行模式及带有运动检测的四场去隔行模式对应的去隔行逻辑；这里，当前输入的图像数据为隔行视频序列，以视频图像数据中的Y分量y_1_in为例，所述数据输入子模块121，将待插值的t场中第N行图像数据的y_1_in输入通道1中；其中，所述N为大于或等于1的整数，当N等于1时，表示所述数据输入子模块121将待插值的t场中第1行图像数据的y_1_in输入通道1中。When the configuration module 11 configures the status bit instruction of the deinterlace mode register to be 01 according to the received deinterlacing mode instruction, that is, when the deinterlacing mode of the image data to be processed is determined to be an intra-interlace mode, the configuration module 11 automatically Turning off the deinterlacing logic corresponding to the deinterlacing mode and the four-field deinterlacing mode with motion detection; here, the currently input image data is an interlaced video sequence, taking the Y component y_1_in in the video image data as an example, The data input sub-module 121 inputs the y_1_in of the image data of the Nth row in the t field to be interpolated into the channel 1; wherein the N is an integer greater than or equal to 1, and when N is equal to 1, the data input is The module 121 inputs y_1_in of the image data of the first line in the t field to be interpolated into the channel 1.

这里，如图8所示，所述数据输入子模块121是将待插值的t场中第N行图像数据的y_1_in的两个像素为一组进行输入的，并暂存在第一准备寄存器datain_r0 81中，所述第一准备寄存器datain_r0 81对通道1中第一ram的y_1_in的像素进行拼接，直至将y_1_in拼接满十六个像素，并将拼接满十六个像素的数据datain传输至第二准备寄存器datain_r1 82中；当datain的位宽达到128位时，所述第一准备寄存器datain_r0 81将读ram信号read_out拉高，即read_out＝1，所述读数据子模块122按照两个像素为一组的格式读取第一ram中之前存储的第N-1行图像数据的Y分量的第一组datain，并将第N-1行图像数据的Y分量的第一组datain输出至第一输出寄存器data_out 83；其中，所述第N-1行图像数据的Y分量为第N行Y分量的上一行图像数据，所述第一ram的初始地址addr_ram为0；所述一组datain包括十六个像素。Here, as shown in FIG. 8, the data input sub-module 121 inputs two pixels of y_1_in of the N-th row image data in the t field to be interpolated, and temporarily stores the first preparation register datain_r0 81. The first preparation register datain_r0 81 splices the pixels of the first ram y_1_in in the channel 1 until the y_1_in is spliced to sixteen pixels, and the datain which is spliced to sixteen pixels is transmitted to the second preparation. The datain_r1 82 is in the register; when the bit width of the datain reaches 128 bits, the first preparation register datain_r0 81 pulls the read ram signal read_out high, that is, read_out=1, and the read data sub-module 122 is grouped by two pixels. The format reads the first group datain of the Y component of the N-1th line image data stored in the first ram, and outputs the first group datain of the Y component of the N-1th line image data to the first output register Data_out 83; wherein, the Y component of the N-1th row image data is the previous row of image data of the Nth row Y component, the initial address addr_ram of the first ram is 0; and the set of datain includes sixteen Pixel.

当所述读数据子模块122将第N-1行图像数据的Y分量的第一组datain输出至第一输出寄存器data_out 83后，所述第一准备寄存器datain_r0 81将read_out拉低，即read_out＝0；将写ram信号write_into拉高，即write_into＝1，所述第二准备存器datain_r1 82将第N行图像数据的y_1_in的第一组datain写入第一ram中，所述addr_ram自动加1；After the read data sub-module 122 outputs the first group datain of the Y component of the N-1th line image data to the first output register data_out 83, the first preparation register datain_r0 81 pulls the read_out low, that is, read_out= 0; the write ram signal write_into is pulled high, that is, write_into=1, the second preparation memory datain_r1 82 writes the first group datain of the y_1_in of the Nth line image data into the first ram, and the addr_ram is automatically added 1 ;

当所述第二准备寄存器datain_r182将第N行图像数据的y_1_in的第一组datain写入第一ram中后，所述数据输入子模块21，还配置为输入第N行图像数据的y_1_in的第二组datain；与输入第N行图像数据的y_1_in的第一组datain采用相同的方法，当所述第一准备寄存器datain_r0 81对第N行图像数据的y_1_in的第二组datain完成拼接后，将第N行图像数据的y_1_in的第二组datain传输至所述第二准备寄存器datain_r1 82，再将read_out拉高，所述读数据子模块122读取第N行图像数据的y_1_in的第一组datain，并将第一输出寄存器data_out 83中第N-1行图像数据的Y分量的第一组datain输出至第二输出寄存器data_out r 85；将所述第一ram中第N-1行图像数据的Y分量的第二组datain输出至第一输出寄存器data_out 83；将所述第N行图像数据的y_1_in的第一组datain输出至第一延迟寄存器datain_dly 84中；After the second preparation register datain_r182 writes the first group datain of the y_1_in of the Nth row image data into the first ram, the data input submodule 21 is further configured to input the y_1_in of the Nth row image data. Two sets of datain; in the same way as the first set of datain of y_1_in inputting the image data of the Nth row, when the first preparation register datain_r0 81 completes the splicing of the second set of datain of y_1_in of the image data of the Nth row, The second group of datain of the y_1_in of the Nth line image data is transferred to the second preparation register datain_r1 82, and the read_out is pulled high, and the read data sub-module 122 reads the first group of datain of the y_1_in of the image data of the Nth line. And outputting the first group datain of the Y component of the N-1th line image data in the first output register data_out 83 to the second output register data_out r 85; the image data of the N-1th line in the first ram The second group of datain of the Y component is output to the first output register data_out 83; the first group of datain of the y_1_in of the Nth row of image data is output to the first delay register datain_dly 84;

所述读数据子模块122将N行图像数据的y_1_in的第一组datain输出至第一延迟寄存器datain_dly 84后，所述第一准备寄存器datain_r0 81将read_out拉低；将write_into拉高，所述第二准备寄存器datain_r1 82将第N 行图像数据的y_1_in的第二组datain写入第一ram中，所述addr_ram自动加1；After the read data sub-module 122 outputs the first group datain of the y_1_in of the N rows of image data to the first delay register datain_dly 84, the first preparation register datain_r0 81 pulls the read_out low; pulls the write_into high, the first The second preparation register datain_r1 82 will be the Nth The second group of datain of y_1_in of the line image data is written into the first ram, and the addr_ram is automatically incremented by one;

当所述第二准备寄存器datain_r182将第N行图像数据的y_1_in的第二组datain写入第一ram中后，所述数据输入子模块121，还配置为输入第N行图像数据的y_1_in的第三组datain；与输入第N行图像数据的y_1_in的第一组、第二组datain采用相同的方法，当所述第一准备寄存器datain_r0 81对第N行图像数据的y_1_in的第三组datain完成拼接后，将第N行图像数据的y_1_in的第三组datain传输至所述第二准备寄存器datain_r1 82，再将read_out拉高，所述读数据子模块122读取第N行图像数据的y_1_in的第二组datain，将第一输出寄存器data_out 83中第N-1行图像数据的Y分量的第二组datain输出至第二输出寄存器data_out r 85；将所述第一ram中第N-1行图像数据的Y分量的第三组datain输出至第一输出寄存器data_out 83；将所述第N行图像数据的y_1_in的第二组datain输出至第一延迟寄存器datain_dly 84中；After the second preparation register datain_r182 writes the second group datain of the y_1_in of the Nth row of image data into the first ram, the data input submodule 121 is further configured to input the y_1_in of the image data of the Nth row. Three sets of datain; the same method as the first group and the second group of datain of y_1_in inputting the image data of the Nth row, when the first preparation register datain_r0 81 is completed for the third group of datain of y_1_in of the image data of the Nth row After splicing, the third group datain of the y_1_in of the image data of the Nth row is transferred to the second preparation register datain_r1 82, and the read_out is pulled high, and the read data sub-module 122 reads the y_1_in of the image data of the Nth row. a second group of datains, outputting a second group of datain of the Y component of the N-1th row of the first output register data_out 83 to the second output register data_out r 85; the N-1th row of the first ram a third group of datain of the Y component of the image data is output to the first output register data_out 83; a second group of datain of the y_1_in of the Nth row of image data is output to the first delay register datain_dly 84;

所述读数据子模块122将N行图像数据的y_1_in的第二组datain输出至第一延迟寄存器datain_dly 84后，所述第一准备寄存器datain_r0 81将read_out拉低；将write_into拉高，所述第二准备寄存器datain_r1 82将第N行图像数据的y_1_in的第三组datain写入第一ram中，所述addr_ram自动加1；其中，After the read data sub-module 122 outputs the second group datain of the y_1_in of the N rows of image data to the first delay register datain_dly 84, the first preparation register datain_r0 81 pulls the read_out low; pulls the write_into high, the first The second preparation register datain_r1 82 writes the third group datain of the y_1_in of the Nth line image data into the first ram, and the addr_ram is automatically incremented by one;

为了保证没有经过去隔行运算处理的第N行图像数据的Y分量可以与经去隔行处理后的第N行图像数据的Y分量能同步输出，所述每一组datain还需要经过第二延迟寄存器datain_dly0 86和第三延迟寄存器datain_dly1 87的延迟；所述第一延迟寄存器datain_dly 84、第二延迟寄存器datain_dly0 86及第三延迟寄存器datain_dly1 87的延迟时间可自行配置。In order to ensure that the Y component of the Nth line image data that has not undergone deinterlacing processing can be output synchronously with the Y component of the deinterlaced Nth line image data, each of the sets of datain also needs to pass through the second delay register. The delay of the datain_dly0 86 and the third delay register datain_dly1 87; the delay times of the first delay register datain_dly 84, the second delay register datain_dly0 86, and the third delay register datain_dly1 87 are self-configurable.

当所述读数据子模块122读取第一ram中第N-1行图像数据的Y分量的第三组datain后，所述去隔行逻辑子模块123对输出的第N-1行图像数据的Y分量的第一组datain和输入的第N行图像数据的Y分量的第一组datain进行场内去隔行逻辑运算处理；具体地，如图9所示，首先采用基于边缘的行平均插值法，在待插值点附近对t场中第N行图像数据的Y分量第一组datain的像素进行边缘检测，其次将所述边缘上的两个像素点求平均，将平均值作为插值结果对第N行图像数据的Y分量进行插值；这里，可以对i行j列的矩阵进行边缘检测以得出插值结果，第i行第j列的坐标为P(i，j)；比如，将参数β值取为1，即对3行3列的矩阵做边缘检测得出插值结果，如果t场中第N行的像素点需要进行插值，则可以将t-1场中第N行像素的色彩分量复制到待插值t场中的第N行相应的像素点中；比如，如果t场中的最后一行的像素点需要进行插值，则可以将t-1场中最后一行像素的色彩分量复制到待插值t场中的最后一行相应的像素点中；这里，可以采取同样的方法对各列的插值点进行插值。When the read data sub-module 122 reads the Y component of the image data of the N-1th line in the first ram After the third group of datains, the deinterlacing logic sub-module 123 performs the first group datain of the Y component of the output N-1th line image data and the first group datain of the Y component of the input Nth row image data. In-field deinterlacing logic operation; specifically, as shown in FIG. 9, first, the edge-based row average interpolation method is used, and the Y component of the Nth line image data in the t field is adjacent to the pixel to be interpolated. Edge detection is performed, secondly, two pixel points on the edge are averaged, and the average value is used as an interpolation result to interpolate the Y component of the image data of the Nth row; here, the edge detection of the matrix of the i row and the j column may be performed. The interpolation result is obtained, and the coordinates of the jth column of the i-th row are P(i, j); for example, the parameter β value is taken as 1, that is, the edge detection is performed on the matrix of the 3 rows and 3 columns to obtain the interpolation result, if the t field If the pixel of the Nth row needs to be interpolated, the color component of the Nth row of pixels in the t-1 field can be copied into the corresponding pixel of the Nth row in the t field to be interpolated; for example, if in the t field The pixel of the last line needs to be interpolated, then the last one in the t-1 field can be The pixel color components are copied to the corresponding pixel to be interpolated t field in the last row; here, the same method can be taken for each column interpolation points interpolated.

其中，与将上下两行像素简单地求平均的方法相比，本实施例提供的基于边缘的行平均插值法可以更加清晰地显示出图像的边缘；所述边缘为对角线方向上两个像素点绝对值的差为最小时，由这两个像素点连接成的线段；所述β为像素矩阵的大小。The edge-based line average interpolation method provided by the embodiment can display the edge of the image more clearly than the method of simply averaging the upper and lower rows of pixels; the edge is two in the diagonal direction. When the difference in the absolute value of the pixel is the smallest, the line segment is connected by the two pixel points; the β is the size of the pixel matrix.

当所述数据输入子模块121采用相同的方法输入第N行图像数据的y_1_in的第四组datain时，所述读数据子模块122采用上述处理方法对相应的数据进行读取、写入；所述去隔行逻辑子模块123采用上述去隔行方法对输出的第N-1行图像数据的Y分量的第二组datain和输入的第N行图像数据的Y分量的第二组datain进行场内去隔行逻辑运算处理，直到一帧图像数据处理完成；When the data input sub-module 121 inputs the fourth group datain of the y_1_in of the Nth row image data by the same method, the read data sub-module 122 reads and writes the corresponding data by using the above processing method; The deinterlacing logic sub-module 123 performs on-the-spot on the second group datain of the Y component of the output N-1th line image data and the second group datain of the Y component of the input Nth line image data by using the deinterlacing method described above. Interlaced logic operation until one frame of image data processing is completed;

这里，所述去隔行逻辑子模块123对图像数据进行去隔行逻辑运算处理后，还配置为对去隔行处理后的图像数据的像素进行组合；并输出组合后的去隔行图像数据。Here, the deinterlacing logic sub-module 123 performs deinterlacing logic operation processing on the image data, and is further configured to combine pixels of the deinterlaced image data; and output the combination After deinterlacing image data.

所述去隔行逻辑子模块123将去隔行后的第N-1行图像数据的Y分量的第一组datain和第N行图像数据的Y分量的第一组datain进行重组逻辑运算处理，直至处理完一帧图像数据；其中，所述去隔行后的第N-1行图像数据的Y分量的第一组datain与第N行图像数据的Y分量的第一组datain也是以两个像素为一组的格式进行输出的，所以需要去隔行逻辑子模块123对datain进行重组；The deinterlacing logic sub-module 123 performs recombination logic operation processing on the first group datain of the Y component of the N-1th line image data after deinterlacing and the first group datain of the Y component of the Nth row image data until processing Finishing one frame of image data; wherein, the first group of datain of the Y component of the N-1th line of image data after deinterlacing and the first group of datain of the Y component of the image data of the Nth row are also two pixels The format of the group is output, so it is necessary to de-interlace the logical sub-module 123 to reorganize the datain;

当所述去隔行逻辑子模块123对一组datain进行重组后，将没有经过去隔行运算处理的第N行图像数据的Y分量从通道2输出，将重组逻辑运算处理后的第N行图像数据的Y分量从通道1输出到暂存寄存器temp_data 88中，以使通过通道1输出的图像数据与通过通道2输出的图像数据可以进行同步输出，直至输出完一帧图像数据。After the deinterlacing logic sub-module 123 reorganizes a group of datains, the Y component of the image data of the Nth line that has not undergone the deinterlacing operation is output from the channel 2, and the image data of the Nth row after the rectification logic operation is processed. The Y component is output from the channel 1 to the temporary register temp_data 88 so that the image data output through the channel 1 and the image data output through the channel 2 can be output in synchronization until the image data of one frame is output.

这里，本实施例可以采取与第N行图像数据的Y分量同样的去隔行处理方法对第N行图像数据的UV分量进行去隔行处理；主要区别在于：第N-1行图像数据的UV分量是通过第二ram存储的。Here, in this embodiment, the deinterlacing processing method of the image data of the Nth line can be deinterlaced by the same deinterlacing processing method as the Y component of the image data of the Nth line; the main difference is: the UV component of the image data of the N-1th line. It is stored by the second ram.

这样，在场内去隔行模式下，随着图像数据的不断输入，不断地对第N行图像数据的Y分量、UV分量分别完成场内去隔行处理，即可得到最终的一帧图像数据。In this way, in the inter-deinterlace mode, as the image data is continuously input, the Y component and the UV component of the image data of the Nth line are successively subjected to intra-field deinterlacing processing, and the final image data of one frame can be obtained.

当所述配置模块11根据接收的去隔行模式指令，将所述去隔行模式寄存器的状态位指令配置为10，即确定待处理图像数据的去隔行模式为带有运动检测的四场去隔行模式时，则会自动关闭不使能去隔行模式及场内去隔行模式对应的去隔行逻辑；其中，在带有运动检测的四场去隔行模式下，运动自适应法是通过运动检测来判断像素是否运动，由于运动检测不能精确地检测出像素是否是运动的，所以，一般来说，检测结果分为三种情况：显著运动、静止以及不显著运动。当检测结果为显著运动时，所述去隔行逻辑子模块123则采用场内插值算法对图像数据进行去隔行处理；当检测结果为静止时，所述去隔行逻辑子模块123则采用场合并算法对图像数据进行去隔行处理；当检测结果为不显著运动时，所述去隔行逻辑子模块123则将显著运动和静止运动按照一定比例合并在一起对图像数据进行去隔行处理。When the configuration module 11 configures the status bit instruction of the deinterlacing mode register to 10 according to the received deinterlacing mode instruction, that is, determining the deinterlacing mode of the image data to be processed is a four-field deinterlacing mode with motion detection. At the same time, the deinterlacing logic corresponding to the interlaced mode and the interlaced mode in the field is automatically turned off; wherein, in the four-field deinterlacing mode with motion detection, the motion adaptive method determines the pixel by motion detection. Whether it is motion or not, since the motion detection cannot accurately detect whether the pixel is moving or not, in general, the detection result is divided into three cases: significant motion, static motion, and insignificant motion. Deinterlacing when the detection result is significant motion The logic sub-module 123 uses the intra-field interpolation algorithm to deinterlace the image data; when the detection result is static, the deinterlacing logic sub-module 123 uses the occasional algorithm to deinterlace the image data; when the detection result is When there is no significant motion, the deinterlacing logic sub-module 123 combines the significant motion and the stationary motion in a certain ratio to deinterlace the image data.

如图10所示，Delta_1的值是t场中待插值点上一行的三个像素点的色彩分量R、G、B、A与t-2场中对应的三个像素点的色彩分量各个差值的绝对值之和；Delta_2的值是t-1场中与t场中插值点所处的行所对应的行中三个像素点的色彩分量与t+1场中对应行中三个像素点的色彩分量各个差值的绝对值之和；Delta_3的值t场中待插值点上一行的三个像素点的色彩分量R、G、B、A与t-2场中对应的三个像素点的色彩分量的插值绝对值的和；其中，所述t场中待插值点为图10中纯黑色的点，所述Delta_1、Delta_2、Delta_3的和为Delta_sum的值；即：As shown in FIG. 10, the value of Delta_1 is the difference between the color components R, G, B, A of the three pixels of the row to be interpolated in the t field and the color components of the corresponding three pixels in the t-2 field. The sum of the absolute values of the values; the value of Delta_2 is the color component of the three pixels in the row corresponding to the row in which the interpolation point in the t field is in the t-1 field and the three pixels in the corresponding row in the t+1 field. The sum of the absolute values of the differences of the color components of the point; the value of the Delta_3 in the color field of the three pixels of the row to be interpolated in the field of the pixel, R, G, B, A and the corresponding three pixels in the t-2 field The sum of the absolute values of the interpolation of the color components of the point; wherein the point to be interpolated in the t field is a point of pure black in FIG. 10, and the sum of the Delta_1, Delta_2, and Delta_3 is a value of Delta_sum;

Delta_sum＝Delta_1+Delta_2+Delta_3；Delta_sum=Delta_1+Delta_2+Delta_3;

所述插值结果u可利用公式(1)得出：The interpolation result u can be obtained by using formula (1):

所述Delta_sum≥T2表示显著运动；所述Delta_sum≤T1表示静止；所述T1<Delta_sum<T2表示不显著运动；所述f(T1，T2)的值由公式(2)得出；The Delta_sum≥T2 represents a significant motion; the Delta_sum≤T1 represents a stationary; the T1<Delta_sum<T2 represents an insignificant motion; the value of the f(T1, T2) is derived from the formula (2);

其中，u为插值结果；X1为t-1场中对应像素点的值；X2为根据场内插值算法得到的插值结果；所述阈值寄存器中的第一阈值T1和第二阈值T2，可根据实际情况配置。Wherein u is an interpolation result; X1 is a value of a corresponding pixel point in the t-1 field; X2 is an interpolation result obtained according to an intra-field interpolation algorithm; and the first threshold T1 and the second threshold T2 in the threshold register are Actual configuration.

这里，当所述数据输入子模块121将t-2场中的待处理图像数据、t-1 场中的待处理图像数据、t场中的待处理图像数据及t+1场中的待处理图像数据分别通过通道1、3、2、4分别输入后，将t-2场中的第N行待处理图像数据的Y分量储存在第一ram中，将t-2场中的第N行待处理图像数据的UV分量储存在第二ram中，将t场中的第N行待处理图像数据的Y分量储存在第三ram中，将t场中的第N行待处理图像数据的UV分量储存在第四ram中，按照与上述场内去隔行模式下的数据处理方法将图像数据进行处理后；所述去隔行逻辑子模块123根据上述公式(1)(2)分别对t-2场及t场中的第N-1行图像数据的Y分量的第一组datain和t-2场及t场中的第N行图像数据的Y分量的第一组datain进行去隔行逻辑运算处理，直到一帧图像数据处理完成；这里，因为只需处理t-1场中的第N行待处理图像数据及t+1场中的第N行待处理图像数据，不需要处理t-1场中的第N-1行待处理图像数据及t+1场中的第N-1行待处理图像数据，所以不需要在ram中存储t-1场中的待处理图像数据及t+1场中的待处理图像数据；当t-1场中的待处理图像数据及t+1场中的待处理图像数据分别从通道3、4输入之后，直接按照上述公式(1)(2)对待处理图像的第N行待处理图像数据进行处理即可。Here, when the data input sub-module 121 takes the image data to be processed in the t-2 field, t-1 The image data to be processed in the field, the image data to be processed in the t field, and the image data to be processed in the t+1 field are respectively input through

channels

1, 3, 2, and 4, and the Nth in the t-2 field is respectively input. The Y component of the image data to be processed is stored in the first ram, and the UV component of the image data of the Nth row in the t-2 field is stored in the second ram, and the image of the Nth row in the t field is to be processed. The Y component of the data is stored in the third ram, and the UV component of the image data of the Nth row in the t field is stored in the fourth ram, and the image data is processed according to the data processing method in the above-described deinterlacing mode in the field. After processing, the deinterlacing logic sub-module 123 respectively pairs the first group of datain and t-2 of the Y component of the image data of the N-1th row in the t-2 field and the t field according to the above formula (1)(2). The first group of datain of the Y component of the image data of the Nth row in the field and the t field is subjected to deinterlacing logic operation until one frame of image data processing is completed; here, since only the Nth row in the t-1 field needs to be processed Processing the image data and the Nth line of the to-be-processed image data in the t+1 field, without processing the N-1th line of the to-be-processed image data in the t-1 field and t The N-1th line in the +1 field is to be processed image data, so it is not necessary to store the image data to be processed in the t-1 field and the image data to be processed in the t+1 field in the ram; when in the t-1 field After the image data to be processed and the image data to be processed in the t+1 field are respectively input from the channels 3 and 4, the image data of the Nth line to be processed of the image to be processed can be directly processed according to the above formula (1) (2). .

这里，所述去隔行逻辑子模块123对图像数据进行去隔行逻辑运算处理后，还配置为对去隔行处理后的图像数据的像素进行组合；并输出组合后的去隔行图像数据。Here, the deinterlacing logic sub-module 123 performs deinterlacing logic operation processing on the image data, and is further configured to combine the pixels of the deinterlaced image data; and output the combined deinterlaced image data.

具体地，所述去隔行逻辑子模块123将去隔行后的第N-1行图像数据的Y分量的第一组datain和第N行图像数据的Y分量的第一组datain进行重组逻辑运算处理，直至处理完一帧图像数据；其中，所述去隔行后的第N-1行图像数据的Y分量的第一组datain与第N行图像数据的Y分量的第一组datain也是以两个像素为一组的格式进行输出的，所以需要所述去隔行逻辑子模块123对datain进行重组。 Specifically, the deinterlacing logic sub-module 123 performs recombination logic operation on the first group datain of the Y component of the N-1th line image data after deinterlacing and the first group datain of the Y component of the Nth row image data. Until processing one frame of image data; wherein, the first group of datain of the Y component of the deinterlaced image data of the N-1th row and the first group of datain of the Y component of the image data of the Nth row are also two The pixels are output in a set of formats, so the deinterlacing logic sub-module 123 is required to reassemble the datain.

当去隔行逻辑子模块123对一组datain进行重组后，将重组逻辑运算处理后的第N行图像数据的Y分量从通道2输出，将重组逻辑运算处理后的第N行图像数据的Y分量从通道1输出到暂存寄存器temp_data 88中，以使从通道1输出的图像数据与从通道2输出的图像数据进行同步输出，直至输出完一帧图像数据。After the deinterlacing logic sub-module 123 reorganizes a group of datains, the Y component of the image data of the Nth row after the recombination logic operation is output from the channel 2, and the Y component of the image data of the Nth row after the recombination logic operation is processed. The channel 1 is outputted to the scratchpad register temp_data 88 so that the image data output from the channel 1 is output in synchronization with the image data output from the channel 2 until the image data of one frame is output.

实际应用时，所述顶层模块21、所述配置模块11、所述去隔行模块12、及所述同步模块22可由图像去隔行装置中的中央处理器(CPU，Central Processing Unit)、数字信号处理器(DSP，Digital Signal Processor)或可编程逻辑阵列(FPGA，Field－Programmable Gate Array)实现。In actual application, the top layer module 21, the configuration module 11, the deinterlacing module 12, and the synchronization module 22 may be processed by a central processing unit (CPU) in the image deinterlacing device. (DSP, Digital Signal Processor) or Programmable Array (FPGA) implementation.

本实施例提供的图像去隔行装置，内置有不使能去隔行逻辑、场内去隔行逻辑以及带有运动检测的四场去隔行逻辑三种逻辑，可方便用户根据不同的场景自行选择去隔行模式，使其适用于更多场景。The image deinterlacing device provided in this embodiment has three logics of de-interlacing logic, intra-field deinterlacing logic and four-field deinterlacing logic with motion detection, which can be conveniently selected by the user to deinterlace according to different scenes. The mode makes it suitable for more scenes.

该装置同时采用ram复用的方法，节省了ram空间。The device also adopts the ram multiplexing method, which saves ram space.

实施例二 Embodiment 2

相应于实施例一，本实施例还提供了一种图像去隔行方法；如图11所示，该方法包括以下步骤：Corresponding to the first embodiment, the embodiment further provides an image deinterlacing method; as shown in FIG. 11, the method includes the following steps:

步骤1100，根据接收的去隔行模式指令，确定待处理图像数据的去隔行模式；Step 1100: Determine a deinterlace mode of image data to be processed according to the received deinterlace mode instruction;

本步骤中，根据接收的去隔行模式指令，将去隔行寄存器进行相应去隔行模式的指示配置。In this step, according to the received deinterlace mode instruction, the deinterlace register is configured to perform the corresponding deinterlace mode indication configuration.

实际应用时，为了方便使用，可以在图像去隔行装置中内置三个去隔行逻辑，分别为：不使能去隔行逻辑、场内去隔行逻辑以及带有运动检测的四场去隔行逻辑；其中，不使能去隔行逻辑的功能是：将非同步输入的待处理图像数据进行同步输出；场内去隔行逻辑的功能是：分别对输入的待处理图像数据的Y分量及UV分量进行场内去隔行逻辑处理；带有运动检测的四场去隔行逻辑的功能是：分别对输入的待处理图像数据的Y分量及UV分量进行四场去隔行逻辑处理。In practical applications, for the convenience of use, three deinterlacing logics can be built in the image deinterlacing device, namely: deinterlacing logic, in-field deinterlacing logic, and four deinterlacing logic with motion detection; The function of not enabling the interlaced logic is: synchronously outputting the image data to be processed that is not synchronously input; the function of the deinterlacing logic in the field is: performing on-field respectively on the Y component and the UV component of the input image data to be processed. Deinterlacing logic; with motion The function of the detected four-field deinterlacing logic is to perform four-field deinterlacing logic processing on the Y component and the UV component of the input image data to be processed, respectively.

相应的，当接收的去隔行模式指令为不使能去隔行模式指示时，可以根据接收的去隔行模式指令，将所述去隔行模式寄存器的状态位指令配置为00，从而实现对所述去隔行寄存器的去隔行模式的指示配置，以便确定待处理图像数据的去隔行模式为不使能去隔行模式；当接收的去隔行模式指令为场内去隔行模式指示时，可以根据接收的去隔行模式指令，将所述去隔行模式寄存器的状态位指令配置为01，从而实现对所述去隔行寄存器的去隔行模式的指示配置，以便确定待处理图像数据的去隔行模式为场内去隔行模式；当接收的去隔行模式指令为带有运动检测的四场去隔行模式指示时，根据接收的去隔行模式指令，将所述去隔行模式寄存器的状态位指令配置为10，从而实现对所述去隔行寄存器的去隔行模式的指示配置，以便确定待处理图像数据的去隔行模式为四场去隔行模式；其中，所述去隔行模式寄存器还可以预留一个状态位指令11，以便后续扩展应用。Correspondingly, when the received deinterlace mode instruction is not enabling the deinterlacing mode indication, the status bit instruction of the deinterlacing mode register may be configured to 00 according to the received deinterlacing mode instruction, thereby implementing the An indication of the deinterlacing mode of the interlace register to determine that the deinterlacing mode of the image data to be processed is not deinterlacing mode; when the received deinterlacing mode instruction is an interlaced mode indication, the deinterlacing may be based on the received deinterlacing mode a mode instruction, configured to configure a status bit instruction of the deinterlace mode register to 01, thereby implementing an indication configuration of the deinterlace mode of the deinterlace register to determine a deinterlacing mode of the image data to be processed as an intra-interlace mode When the received deinterlace mode command is a four-field deinterlace mode indication with motion detection, the status bit instruction of the deinterlace mode register is configured to 10 according to the received deinterlace mode instruction, thereby implementing the De-interlace mode indication configuration of the interlace register to determine the deinterlacing mode of the image data to be processed Interlace mode is to four; wherein said deinterlacing mode register may be reserved for a status bit instruction 11, for subsequent expansion applications.

步骤1101，采用确定的去隔行模式对应的去隔行逻辑对所述待处理图像数据进行去隔行处理，并关闭除所述确定的去隔行模式对应的去隔行逻辑外的其它去隔行逻辑。Step 1101: Deinterlace the image data to be processed by de-interlacing logic corresponding to the determined deinterlacing mode, and turn off deinterlacing logic except the deinterlacing logic corresponding to the determined deinterlacing mode.

这里，所述采用确定的去隔行模式对的去隔行逻辑对所述待处理图像数据进行去隔行处理，并关闭除所述确定的去隔行模式对应的去隔行逻辑外的其它去隔行逻辑之前，还需要对各寄存器的相关信息进行配置，以便能采用相应的去隔行逻辑对所述待处理数据进行去隔行处理；其中，需要配置的各寄存器的相关信息，具体可以包括： Here, the deinterlacing logic using the determined deinterlacing mode pair deinterlaces the image data to be processed, and turns off other deinterlacing logics other than the deinterlacing logic corresponding to the determined deinterlacing mode. It is also required to configure related information of each register, so that the data to be processed can be deinterlaced by using corresponding deinterlacing logic; wherein the related information of each register to be configured may include:

根据待处理图像数据的长和宽在分辨率寄存器中，对待处理图像数据的分辨率式进行配置，以便可以处理不同分辨率的图像数据；其中，实际应用时，一般场内去隔行逻辑和带有运动检测的四场去隔行逻辑要求待处理图像数据的分辨率为1920*1080；According to the length and width of the image data to be processed, in the resolution register, the resolution of the image data to be processed is configured so that image data of different resolutions can be processed; wherein, in practical applications, the general deinterlacing logic and band in the field are generally applied. The four-field deinterlacing logic with motion detection requires the resolution of the image data to be processed to be 1920*1080;

当确定的去隔行模式为带有运动检测的四场去隔行模式时，还需要配置阈值寄存器的第一阈值T1及第二阈值T2；其中，在带有运动检测的四场去隔行模式下，所述第一阈值T1以及第二阈值T2用于判断像素是处于运动状态还是静止状态。When the determined deinterlacing mode is the four-field deinterlacing mode with motion detection, it is also necessary to configure the first threshold T1 and the second threshold T2 of the threshold register; wherein, in the four-field deinterlacing mode with motion detection, The first threshold T1 and the second threshold T2 are used to determine whether the pixel is in a moving state or a stationary state.

当所将上述各寄存器配置完成后，还需要最后在使能(enable)寄存器中配置用于使能的第一使能信号；具体地，当所述装置需要处理图像数据时，将所述enable寄存器的第一使能信号配置为高电平，从而使能图像去隔行装置的去隔行模块，换句话说，启动所述去隔行模块；当一帧图像数据处理完毕，且后续无图像数据需要处理时，在所述enable寄存器中配置低电平，从而去使能所述去隔行模块，换句话说，关闭所述去隔行模块。After the configuration of the above registers is completed, it is also necessary to finally configure a first enable signal for enabling in an enable register; specifically, when the device needs to process image data, the enable register is The first enable signal is configured to a high level, thereby enabling the deinterlacing module of the image deinterlacing device, in other words, starting the deinterlacing module; when one frame of image data is processed, and no subsequent image data needs to be processed When the low level is configured in the enable register, the deinterlacing module is disabled, in other words, the deinterlacing module is turned off.

实际应用时，当一帧图像数据处理完毕后，且后续还有图像数据需要处理时，还需要在中断寄存器中配置用于清除中断信号的第二使能信号，并重新对分辨率寄存器及阈值寄存器进行配置，以进行下一帧图像数据的处理；这里，当一帧图像处理完毕之后，所述装置会产生中断信号，因此需要将所述中断寄存器的第二使能信号配置为高电平，以清除中断信号，从而进行后续图像数据的处理。In practical application, when one frame of image data is processed, and subsequent image data needs to be processed, a second enable signal for clearing the interrupt signal needs to be configured in the interrupt register, and the resolution register and the threshold are re-set. The register is configured to perform processing of the next frame of image data; here, after one frame of image processing is completed, the device generates an interrupt signal, so the second enable signal of the interrupt register needs to be configured to a high level. To clear the interrupt signal for subsequent image data processing.

这里，是对分辨率寄存器、去隔行寄存器、阈值寄存器、中断寄存器配置完成之后才对enable寄存器进行配置；所述各寄存器包括：分辨率寄存器、去隔行寄存器、中断寄存器以及enable寄存器；其中，当确定的去隔行模式为带有运动检测的四场去隔行模式时，所述各寄存器还包括：阈值寄存器。 Here, the enable register is configured after the resolution register, the deinterlace register, the threshold register, and the interrupt register are configured; the registers include: a resolution register, a deinterlace register, an interrupt register, and an enable register; When the determined deinterlacing mode is a four-field deinterlacing mode with motion detection, each of the registers further includes: a threshold register.

当对上述各寄存器配置完成后，将配置的各寄存器的参数同步至图像去隔行装置的去隔行模块，以便所述去隔行模块能对所述待处理数据进行去隔行处理。After the configuration of each of the above registers is completed, the parameters of the configured registers are synchronized to the deinterlacing module of the image deinterlacing device, so that the deinterlacing module can deinterlace the data to be processed.

具体地，将各寄存器中的时钟通过握手信号同步为所述去隔行处理模块的工作时钟。Specifically, the clocks in the respective registers are synchronized by the handshake signal to the operating clock of the deinterlacing processing module.

更具体地，将各寄存器的时钟同步请求发送至所述去隔行模块，并接收所述去隔行模块的时钟同步请求响应，从而通过时钟同步请求及时钟同步请求响应将所述各寄存器中的配置时钟同步为所述去隔行模块的工作时钟。More specifically, a clock synchronization request of each register is sent to the deinterlacing module, and a clock synchronization request response of the deinterlacing module is received, thereby configuring the registers in the respective registers by a clock synchronization request and a clock synchronization request response. The clock synchronization is the operating clock of the deinterlacing module.

本步骤中，在进行第一帧图像数据处理时，当enable寄存器的第二使能信号处于高电平状态时，接收第一帧图像数据后，根据预先配置的分辨率寄存器的分辨率确定第一帧图像数据的分辨率，根据不使能去隔行模式对应的去隔行逻辑对所述待处理图像数据进行去隔行处理，并关闭场内去隔行模式对应的去隔行逻辑及带有运动检测的四场去隔行模式对应的逻辑；或者，根据场内去隔行模式对应的去隔行逻辑对所述待处理图像数据进行去隔行处理，并关闭不使能去隔行模式对应的去隔行逻辑及带有运动检测的四场去隔行模式对应的去隔行逻辑；或者，根据带有运动检测的去隔行模式对应的去隔行逻辑对所述待处理图像数据进行去隔行处理，并关闭不使能去隔行模式对应的去隔行逻辑及场内去隔行模式对应的去隔行逻辑。 In this step, when the first frame image data processing is performed, when the second enable signal of the enable register is in a high level state, after receiving the first frame image data, determining according to the resolution of the pre-configured resolution register The resolution of one frame of image data, deinterlacing the image data to be processed according to the deinterlacing logic corresponding to the deinterlacing mode, and turning off the deinterlacing logic corresponding to the deinterlacing mode in the field and the motion detection The logic corresponding to the four-field deinterlacing mode; or deinterlacing the image data to be processed according to the deinterlacing logic corresponding to the deinterlacing mode in the field, and turning off the deinterlacing logic corresponding to the deinterlacing mode The de-interlacing logic corresponding to the four-field deinterlacing mode of motion detection; or deinterlacing the image data to be processed according to the de-interlacing logic corresponding to the de-interlacing mode with motion detection, and turning off the de-interlacing mode Corresponding deinterlacing logic and deinterlacing logic corresponding to the deinterlacing mode in the field.

其中，在采用相应的去隔行逻辑对所述待处理图像数据进行去隔行处理时，还用于采用ram复用的方式，对所述待处理图像数据进行去隔行处理；其中，所述ram包括：第一ram、第二ram、第三ram、第四ram；所述第一ram、第二ram、第三ram以及第四ram容量都为120*128；所述120代表ram的最大存储空间，所述128表示ram的位宽。And the deinterlacing processing is performed on the to-be-processed image data by using a ram multiplexing method, where the ram includes The first ram, the second ram, the third ram, and the fourth ram; the first ram, the second ram, the third ram, and the fourth ram have a capacity of 120*128; the 120 represents a maximum storage space of the ram The 128 represents the bit width of the ram.

具体地，当根据接收的去隔行模式指令，将所述去隔行模式寄存器的状态位指令为00，确定待处理图像数据的去隔行模式为不使能去隔行模式时，则会自动关闭场内去隔行模式及带有运动检测的四场去隔行模式对应的去隔行逻辑；这里，当输入的图像数据是隔行视频序列时，将隔行视频序列中奇数场的图像数据输入通道1中，将偶数场的图像数据输入通道2中；Specifically, when the deinterlace mode of the to-be-interlaced mode data is set to 00 according to the received deinterlace mode instruction, and the deinterlacing mode of the image data to be processed is determined to be de-interlaced mode, the intra-field is automatically turned off. Deinterlace mode corresponding to deinterlace mode and four-field deinterlacing mode with motion detection; here, when the input image data is an interlaced video sequence, the image data of the odd field in the interlaced video sequence is input into channel 1, and the even number is Field image data is input to channel 2;

当输入的图像数据是逐行视频序列时，将逐行视频序列中奇数场的图像数据输入通道1中，将偶数场的图像数据输入通道2中；其中，所述通道1的输入地址为addr_in_1，输出地址为addr_out_1；通道2的输入地址为addr_in_2，输出地址为addr_out_2；如图4所示，在初始条件下，所述addr_in_1、addr_in_2、addr_out_1以及addr_out_2均为0。When the input image data is a progressive video sequence, the image data of the odd field in the progressive video sequence is input into the channel 1, and the image data of the even field is input into the channel 2; wherein the input address of the channel 1 is addr_in_1 The output address is addr_out_1; the input address of channel 2 is addr_in_2, and the output address is addr_out_2; as shown in FIG. 4, under the initial condition, the addr_in_1, addr_in_2, addr_out_1, and addr_out_2 are all 0.

可通过通道1及所述通道2将非同步输入的图像数据的Y分量同步输出至显示装置；将非同步输入的图像数据的UV分量同步输出至显示装置；其中，当所述图像数据的Y分量及UV分量同步输出至显示装置后，即可在显示装置中看到经不使能去隔行逻辑处理后的图像；所述显示装置可以为手机、电脑等。The Y component of the asynchronously input image data can be synchronously transmitted through channel 1 and the channel 2 Outputting to the display device; synchronously outputting the UV component of the asynchronously input image data to the display device; wherein, when the Y component and the UV component of the image data are synchronously output to the display device, the display device can be seen in the display device The image processed by the interlaced logic is not enabled; the display device may be a mobile phone, a computer, or the like.

这里，以Y分量为例，如图5所示，当通过通道1输入一个单位的待处理图像数据后，将所述一个单位的图像数据的Y分量存储到第一ram中，所述addr_in_1的地址就加1，输出addr_out_1不变，当没有向通道2输入图像数据时，所述addr_in_2的地址不变，所述addr_out_2也不变；其中，所述一个单位的图像数据包括十六个像素。Here, taking the Y component as an example, as shown in FIG. 5, after inputting one unit of image data to be processed through the channel 1, the Y component of the image data of the one unit is stored in the first ram, the addr_in_1 The address is incremented by 1, and the output addr_out_1 is unchanged. When no image data is input to the channel 2, the address of the addr_in_2 is unchanged, and the addr_out_2 is also unchanged; wherein the image data of the one unit includes sixteen pixels.

如图6所示，当通过通道1再输入一个单位的图像数据时，也将该图像数据的Y分量存储到第一ram中，所述addr_in_1的地址为2，输出addr_out_1不变；当通过通道2输入一个单位的图像数据时，将该图像数据的Y分量存储到第三ram中，所述addr_in_2的地址为1，所述addr_out_2也不变；可以看出，通道1的输入地址不等于通道1的输出地址，通道2的输入地址也不等于通道2的输出地址，即满足了(addr_in_1！＝addr_out_1)&&(addr_in_2！＝addr_out_2)，这时，如图7所示，通过通道1及通道2同时输出一个Y分量的单位数据，所述addr_out_1和addr_out_2同时加1，这样，对非同步输入的图像数据完成了同步输出；其中，所述第一ram和第三ram的位宽及存储空间完全相同，当输入地址addr_in_1、addr_in_2达到ram的上限时，addr_in_1和addr_in_2又重新返回到0。As shown in FIG. 6, when one unit of image data is input again through the channel 1, the Y component of the image data is also stored in the first ram, the address of the addr_in_1 is 2, and the output addr_out_1 is unchanged; 2 When inputting one unit of image data, the Y component of the image data is stored in the third ram, the address of the addr_in_2 is 1, and the addr_out_2 is also unchanged; it can be seen that the input address of the channel 1 is not equal to the channel. The output address of 1 and the input address of channel 2 are not equal to the output address of channel 2, that is, (addr_in_1!=addr_out_1)&&(addr_in_2!=addr_out_2) is satisfied. At this time, as shown in Fig. 7, through channel 1 and channel 2 simultaneously outputting unit data of a Y component, the addr_out_1 and addr_out_2 are simultaneously incremented by 1, so that the synchronous output is completed for the image data of the asynchronous input; wherein the bit width and the storage space of the first ram and the third ram are The same is true. When the input addresses addr_in_1 and addr_in_2 reach the upper limit of ram, addr_in_1 and addr_in_2 return to 0 again.

这里，对非同步输入的UV分量进行同步输出的处理流程与Y分量的处理流程类似，区别是将输入通道1中待处理图像数据的UV分量存储在第二ram中，将输入通道2中待处理图像数据的UV分量存储在第四ram中。Here, the processing flow for synchronously outputting the UV component of the asynchronous input is similar to the processing flow of the Y component. The difference is that the UV component of the image data to be processed in the input channel 1 is stored in the second ram, and the input channel 2 is to be treated. The UV component of the processed image data is stored in the fourth ram.

当根据接收的去隔行模式指令，将所述去隔行模式寄存器的状态位指令配置为01，即确定待处理图像数据的去隔行模式为场内去隔行模式时，则会自动关闭不使能去隔行模式及带有运动检测的四场去隔行模式对应的去隔行逻辑；这里，当前输入的图像数据为隔行视频序列，以视频图像数据中的Y分量y_1_in为例，将待插值的t场中第N行图像数据的y_1_in输入通道1中；其中，所述N为大于或等于1的整数，当N等于1时，表示将待插值的t场中第1行图像数据的y_1_in输入通道1中。When the deinterlace mode instruction is received according to the received deinterlacing mode instruction, the status bit of the deinterlaced mode register is Let the configuration be 01, that is, when the deinterlacing mode of the image data to be processed is determined to be in the inter-deinterlacing mode, the deinterlacing logic corresponding to the deinterlacing mode and the four-field deinterlacing mode with motion detection is automatically turned off; Here, the currently input image data is an interlaced video sequence, and the Y component y_1_in in the video image data is taken as an example, and y_1_in of the Nth row image data in the t field to be interpolated is input into the channel 1; wherein the N is greater than Or an integer equal to 1, when N is equal to 1, it indicates that y_1_in of the image data of the first row in the t field to be interpolated is input into channel 1.

这里，如图8所示，将待插值的t场中第N行图像数据的y_1_in的两个像素为一组的格式进行输入的，并暂存在第一准备寄存器datain_r0中，所述第一准备寄存器datain_r0对通道1内的y_1_in的像素进行拼接，直至将y_1_in拼接满十六个像素，并将拼接满十六个像素的数据datain传输至第二准备寄存器datain_r1中；当datain的位宽达到128位时，所述第一准备寄存器datain_r0将读ram信号read_out拉高，即read_out＝1，按照两个像素为一组的格式读取第一ram中之前存储的第N-1行图像数据的Y分量的第一组datain，并将第N-1行图像数据的Y分量的第一组datain输出至第一输出寄存器data_out；其中，所述第N-1行图像数据的Y分量为第N行Y分量的上一行图像数据，所述第一ram的初始地址addr_ram为0；所述一组datain包括十六个像素。Here, as shown in FIG. 8, the two pixels of the y_1_in of the image data of the Nth row in the t field to be interpolated are input, and temporarily stored in the first preparation register datain_r0, the first preparation The register datain_r0 splices the pixels of y_1_in in channel 1 until y_1_in is spliced to sixteen pixels, and data datain spliced to sixteen pixels is transferred to the second preparation register datain_r1; when the bit width of datain reaches 128 When the bit is set, the first preparation register datain_r0 pulls the read ram signal read_out high, that is, read_out=1, and reads the Y of the N-1th line image data stored in the first ram in a format in which two pixels are grouped. a first group of datain of the component, and outputting the first group of datain of the Y component of the N-1th line image data to the first output register data_out; wherein the Y component of the image data of the (N-1)th row is the Nth row The image of the previous line of the Y component, the initial address addr_ram of the first ram is 0; the set of datain includes sixteen pixels.

将第N-1行图像数据的Y分量的第一组datain输出至第一输出寄存器data_out后，所述第一准备寄存器datain_r0将read_out拉低，即read_out＝0；将写ram信号write_into拉高，即write_into＝1，所述第二准备寄存器datain_r1将第N行图像数据的y_1_in的第一组datain写入第一ram中，所述addr_ram自动加1；After outputting the first group datain of the Y component of the N-1th row image data to the first output register data_out, the first preparation register datain_r0 pulls read_out low, that is, read_out=0; and writes the write ram signal write_into high. That is, write_into=1, the second preparation register datain_r1 writes the first group datain of the y_1_in of the Nth line image data into the first ram, and the addr_ram is automatically incremented by one;

当所述第二准备寄存器datain_r1将第N行图像数据的y_1_in的第一组datain写入第一ram中后，还需要输入第N行图像数据的y_1_in的第二组datain；与输入第N行图像数据的y_1_in的第一组datain采用相同的方法，当所述第一准备寄存器datain_r0对第N行图像数据的y_1_in的第二组datain完成拼接后，将第N行图像数据的y_1_in的第二组datain传输至所述第二准备寄存器datain_r1，再将read_out拉高，读取第N行图像数据的y_1_in的第一组datain，并将第一输出寄存器data_out中第N-1行图像数据的Y分量的第一组datain输出至第二输出寄存器data_out r；将所述第一ram中第N-1行图像数据的Y分量的第二组datain输出至第一输出寄存器data_out；将所述第N行图像数据的y_1_in的第一组datain输出至第一延迟寄存器datain_dly中；After the second preparation register datain_r1 writes the first group datain of the y_1_in of the Nth row image data into the first ram, it is also necessary to input the second group datain of y_1_in of the Nth row image data; and input the Nth row The first method of datain y_1_in uses the same method. After the first preparation register datain_r0 completes splicing of the second group datain of y_1_in of the Nth row image data, the second group datain of y_1_in of the Nth row image data is transmitted to the second preparation register datain_r1, and then Read_out is pulled high, reads the first group of datain of y_1_in of the image data of the Nth row, and outputs the first group of datain of the Y component of the image data of the N-1th line in the first output register data_out to the second output register data_out r Outputting a second group of datains of the Y component of the N-1th row of the first ram to the first output register data_out; outputting the first group of datain of the y_1_in of the Nth row of image data to the first Delay register datain_dly;

将第N行图像数据的y_1_in的第一组datain输出至第一延迟寄存器datain_dly后，所述第一准备寄存器datain_r0将read_out拉低；将write_into拉高，所述第二准备寄存器datain_r1将第N行图像数据的y_1_in的第二组datain写入第一ram中，所述addr_ram自动加1；After outputting the first group datain of the y_1_in of the Nth row image data to the first delay register datain_dly, the first preparation register datain_r0 pulls the read_out low; the write_into is pulled high, and the second preparation register datain_r1 sets the Nth row The second group of datain of y_1_in of the image data is written into the first ram, and the addr_ram is automatically incremented by one;

将第N行图像数据的y_1_in的第二组datain写入第一ram中后，输入第N行图像数据的y_1_in的第三组datain；与输入第N行图像数据的y_1_in的第一组、第二组datain采用相同的方法，当所述第一准备寄存器datain_r0对第N行图像数据的y_1_in的第三组datain完成拼接后，将第N行图像数据的y_1_in的第三组datain传输至所述第二准备寄存器datain_r1，再将read_out拉高，读取第N行图像数据的y_1_in的第二组datain，将第N-1行图像数据的Y分量的第二组datain输出至第二输出寄存器data_out r；将所述第一ram中第N-1行图像数据的Y分量的第三组datain输出至第一输出寄存器data_out；将所述第N行图像数据的y_1_in的第二组datain输出至第一延迟寄存器datain_dly中；After writing the second group datain of y_1_in of the image data of the Nth row into the first ram, inputting the third group datain of y_1_in of the image data of the Nth row; and the first group of the y_1_in of the image data of the input Nth row, The two sets of datain adopt the same method, and after the first preparation register datain_r0 completes the splicing of the third group datain of y_1_in of the Nth line image data, the third group datain of the y_1_in of the Nth line image data is transmitted to the The second preparation register datain_r1, pulls the read_out high, reads the second group datain of the y_1_in of the Nth line image data, and outputs the second group datain of the Y component of the N-1th line image data to the second output register data_out r; outputting a third group datain of the Y component of the N-1th line image data in the first ram to the first output register data_out; outputting the second group datain of the y_1_in of the Nth row image data to the first a delay register datain_dly;

将第N行图像数据的y_1_in的第二组datain输出至第一延迟寄存器datain_dly后，所述第一准备寄存器datain_r0将read_out拉低；将write_into拉高，所述第二准备寄存器datain_r1将第N行图像数据的y_1_in的第三组 datain写入第一ram中，所述addr_ram自动加1；其中，After outputting the second group datain of the y_1_in of the Nth row image data to the first delay register datain_dly, the first preparation register datain_r0 pulls the read_out low; the write_into is pulled high, and the second preparation register datain_r1 takes the Nth row The third group of image data y_1_in Datain is written into the first ram, and the addr_ram is automatically incremented by one;

为了保证没有经过去隔行运算处理的第N行图像数据的Y分量可以与经去隔行处理后的第N行图像数据的Y分量能同步输出，所述每一组datain还需要经过第二延迟寄存器datain_dly0和第三延迟寄存器datain_dly1的延迟；所述第一延迟寄存器datain_dly、第二延迟寄存器datain_dly0及第三延迟寄存器datain_dly1的延迟时间可自行配置。In order to ensure that the Y component of the Nth line image data that has not undergone deinterlacing processing can be output synchronously with the Y component of the deinterlaced Nth line image data, each of the sets of datain also needs to pass through the second delay register. The delay of the datain_dly0 and the third delay register datain_dly1; the delay times of the first delay register datain_dly, the second delay register datain_dly0, and the third delay register datain_dly1 are self-configurable.

当读取第一ram中第N-1行图像数据的Y分量的第三组datain后，对输出的第N-1行图像数据的Y分量的第一组datain和输入的第N行图像数据的Y分量的第一组datain进行场内去隔行逻辑运算处理；具体地，如图9所示，首先采用基于边缘的行平均插值法，在待插值点附近对t场中第N行图像数据的Y分量第一组datain的像素进行边缘检测，其次将所述边缘上的两个像素点求平均，将平均值作为插值结果对第N行图像数据的Y分量进行插值；这里，可以对第i行j列的矩阵进行边缘检测以得出插值结果，第i行第j列的坐标为P(i，j)；比如，将参数β值取为1，即对3行3列的矩阵做边缘检测得出插值结果，如果t场中第N行的像素点需要进行插值，则可以将t-1场中第N行像素的色彩分量复制到待插值t场中的第N行相应的像素点中；比如，如果t场中的最后一行的像素点需要进行插值，则可以将t-1场中最后一行像素的色彩分量复制到待插值t场中的最后一行相应的像素点中；这里，可以采取同样的方法对各列的插值点进行插值。After reading the third group datain of the Y component of the N-1th line image data in the first ram, the first group datain of the Y component of the output N-1th line image data and the input Nth line image data The first group of datain of the Y component performs on-field deinterlacing logic operation; specifically, as shown in FIG. 9, the edge-based row average interpolation method is first used, and the image data of the Nth row in the t field is near the point to be interpolated. The Y component of the first group of datain pixels is edge-detected, and then the two pixel points on the edge are averaged, and the average value is used as an interpolation result to interpolate the Y component of the N-th row image data; here, the The matrix of i rows and j columns is edge-detected to obtain an interpolation result, and the coordinates of the i-th row and the j-th column are P(i, j); for example, the parameter β value is taken as 1, that is, the matrix of 3 rows and 3 columns is made. The edge detection results in an interpolation result. If the pixel of the Nth row in the t field needs to be interpolated, the color component of the Nth row of pixels in the t-1 field can be copied to the corresponding pixel of the Nth row in the t field to be interpolated. In the point; for example, if the pixel of the last row in the t field needs to be interpolated, Copy field t-1 color components to the last row of pixels of the corresponding pixel to be interpolated t field in the last row; here, the same method can be taken for each column interpolation points interpolated.

当采用相同的方法输入第N行图像数据的y_1_in的第四组datain时，采用上述处理方法对相应的数据进行读取、写入；并采用上述去隔行方法对输出的第N-1行图像数据的Y分量的第二组datain和输入的第N行图像数据的Y分量的第二组datain进行场内去隔行逻辑运算处理，直到一帧图像数据处理完成；When the fourth group of datain of y_1_in of the image data of the Nth row is input by the same method, the corresponding data is read and written by using the above processing method; and the above deinterlacing method is adopted. Performing an intra-field deinterlacing logic operation on the second group datain of the Y component of the output N-1th line image data and the second group datain of the Y component of the input Nth line image data until one frame of image data processing is completed ;

对图像数据进行去隔行逻辑运算处理后，还可以对去隔行处理后的图像数据的像素进行组合；并输出组合后的去隔行图像数据。After the deinterlacing logic operation processing is performed on the image data, the pixels of the deinterlaced image data may be combined; and the combined deinterlaced image data is output.

具体地，对去隔行后的第N-1行图像数据的Y分量的第一组datain和第N行图像数据的Y分量的第一组datain进行重组逻辑运算处理，直至处理完一帧图像数据；其中，所述去隔行后的第N-1行图像数据的Y分量的第一组datain与第N行图像数据的Y分量的第一组datain也是以两个像素为一组的格式进行输出的，所以需要对datain进行重组；Specifically, the first group datain of the Y component of the N-1th line image data after deinterlacing and the first group datain of the Y component of the Nth line image data are subjected to recombination logic operation processing until the image data of one frame is processed. Wherein the first group datain of the Y component of the N-1th line image data after the deinterlacing and the first group datain of the Y component of the Nth row image data are also outputted in a format of two pixels. , so you need to reorganize datain;

当完成一组datain的重组后，将没有经过去隔行运算处理的第N行图像数据的Y分量从通道2输出，将经过重组逻辑运算处理后的第N行图像数据的Y分量从通道1输出到暂存寄存器temp_data中，以使通过通道1输出的图像数据与通过通道2输出的图像数据可以进行同步输出，直至输出完一帧图像数据。When the reorganization of a set of datains is completed, the Y component of the image data of the Nth line that has not undergone the deinterlacing operation is output from the channel 2, and the Y component of the image data of the Nth line subjected to the recombination logic operation is output from the channel 1. The temporary register temp_data is input so that the image data output through the channel 1 and the image data output through the channel 2 can be synchronously output until the image data of one frame is output.

当根据接收的去隔行模式指令，将所述去隔行模式寄存器的状态位指令配置为10，即确定待处理图像数据的去隔行模式为带有运动检测的四场去隔行模式时，则会自动关闭不使能去隔行模式及场内去隔行模式对应的去隔行逻辑；其中，在带有运动检测的四场去隔行模式下，运动自适应法是通过运动检测来判断像素是否运动，由于运动检测不能精确地检测出像素是否是运动的，所以，一般来说，检测结果分为三种情况：显著运动、静止以及不显著运动。当检测结果为显著运动时，则采用场内插值算法对图像数据进行去隔行处理；当检测结果为静止时，则采用场合并算法对图像数据进行去隔行处理；当检测结果为不显著运动时，则将显著运动和静止运动按照一定比例合并在一起对图像数据进行去隔行处理。When the de-interlaced mode register status bit instruction is configured to 10 according to the received deinterlacing mode instruction, that is, when the deinterlacing mode of the image data to be processed is determined to be four-field deinterlacing mode with motion detection, Turn off deinterlacing logic that does not enable deinterlacing mode and inter-field deinterlacing mode; where, in four deinterlacing modes with motion detection, motion adaptive method It is determined by motion detection whether the pixel is moving. Since the motion detection cannot accurately detect whether the pixel is moving or not, in general, the detection result is divided into three cases: significant motion, static motion, and insignificant motion. When the detection result is significant motion, the image data is deinterlaced by the intra-field interpolation algorithm; when the detection result is static, the image data is deinterlaced by the occasional algorithm; when the detection result is not significant motion , the significant motion and the stationary motion are combined in a certain proportion to deinterlace the image data.

Delta_sum＝Delta_1+Delta_2+Delta_3；Delta_sum=Delta_1+Delta_2+Delta_3;

所述插值结果u可利用公式(1)得出；所述阈值寄存器中的第一阈值T1和第二阈值T2，可根据实际情况配置。The interpolation result u can be obtained by using the formula (1); the first threshold T1 and the second threshold T2 in the threshold register can be configured according to actual conditions.

这里，将t-2场中的待处理图像数据、t-1场中的待处理图像数据、t场中的待处理图像数据以及t+1场中的待处理图像数据分别通过通道1、3、2、4分别输入后，将t-2场中的第N行待处理图像数据的Y分量储存在第一ram中，将t-2场中的第N行待处理图像数据的UV分量储存在第二ram中，将t场中的第N行待处理图像数据的Y分量储存在第三ram中，将t场中的第N行待处理图像数据的UV分量储存在第四ram中，按照与上述场内去隔行模式下的数据处理方法将图像数据进行处理；根据上述公式(1)(2)分别对t-2场及t场中的第N-1行图像数据的Y分量的第一组datain和t-2及 t场中的第N行图像数据的Y分量的第一组datain进行去隔行逻辑运算处理，直到一帧图像数据处理完成；这里，因为只需处理t-1场中的第N行待处理图像数据及t+1场中的第N行待处理图像数据，不需要处理t-1场中的第N-1行待处理图像数据及t+1场中的第N-1行待处理图像数据，所以不需要在ram中存储t-1场中的待处理图像数据及t+1场中的待处理图像数据；当t-1场中的待处理图像数据及t+1场中的待处理图像数据分别从通道3、4输入之后，直接按照上述公式(1)(2)对待处理图像的第N行待处理图像数据进行处理即可。Here, the image data to be processed in the t-2 field, the image data to be processed in the t-1 field, the image data to be processed in the t field, and the image data to be processed in the t+1 field are respectively passed through the channels 1, 3 After inputting 2 and 4 respectively, the Y component of the image data of the Nth line in the t-2 field is stored in the first ram, and the UV component of the image data of the Nth line in the t-2 field is stored. In the second ram, the Y component of the image data of the Nth row in the t field is stored in the third ram, and the UV component of the image data of the Nth row in the t field is stored in the fourth ram. The image data is processed according to the data processing method in the above-described in-field deinterlacing mode; the Y component of the image data of the N-1th line in the t-2 field and the t field is respectively obtained according to the above formula (1)(2) The first set of datain and t-2 and The first group of datain of the Y component of the image data of the Nth row in the t field is subjected to deinterlacing logic operation until one frame of image data processing is completed; here, since only the Nth row of the to-be-processed image in the t-1 field is processed The data and the Nth row of the to-be-processed image data in the t+1 field do not need to process the N-1th row of the to-be-processed image data in the t-1 field and the N-1th row of the to-be-processed image data in the t+1 field. , so there is no need to store the image data to be processed in the t-1 field and the image data to be processed in the t+1 field in the ram; when the image data to be processed in the t-1 field and the to-be-processed in the t+1 field After the image data is input from the channels 3 and 4, respectively, the image data of the Nth line to be processed of the image to be processed is directly processed according to the above formula (1) (2).

具体地，将去隔行后的第N-1行图像数据的Y分量的第一组datain与第N行图像数据的Y分量的第一组datain也是以两个像素为一组的格式进行输出的，所以需要对datain进行重组。Specifically, the first group datain of the Y component of the N-1th line image data after deinterlacing and the first group datain of the Y component of the Nth line image data are also outputted in a format of two pixels. So you need to reorganize datain.

将没有经过去隔行运算处理的第N行图像数据的Y分量从通道2输出，将重组逻辑运算处理后的第N行图像数据的Y分量从通道1输出到暂存寄存器temp_data中，以使通过通道1输出的图像数据与通道2输出的图像数据可以进行同步输出，直至输出完一帧图像数据。The Y component of the image data of the Nth line that has not undergone the deinterlacing operation is output from the channel 2, and the Y component of the image data of the Nth line after the recombination logic operation is output from the channel 1 to the temporary register temp_data, so as to pass The image data output from channel 1 and the image data output from channel 2 can be output synchronously until one frame of image data is output.

本发明实施例提供的图像去隔行方法，可以内置有多种去隔行逻辑，因此，可方便用户根据不同的场景自行选择去隔行模式，使其适用于更多场景。The image deinterlacing method provided by the embodiment of the invention may have a plurality of deinterlacing logics built in. Therefore, the user may select the deinterlacing mode according to different scenarios to make it suitable for more scenes.

另外，在进行去隔行处理时，采用ram复用的方法，节省了ram空间。In addition, when deinterlacing is performed, the ram multiplexing method is used, which saves ram space.

本领域内的技术人员应明白，本发明的实施例可提供为方法、***、或计算机程序产品。因此，本发明可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。Those skilled in the art will appreciate that embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the present invention may employ computer-usable storage media (including but not limited to disks) in one or more of the computer-usable program code embodied therein. A form of computer program product embodied on a memory and optical storage, etc.).

本发明是参照根据本发明实施例的方法、设备(***)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (system), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device. Means for implementing the functions specified in one or more of the flow or in a block or blocks of the flow chart.

这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。The computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device. The apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.

这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. The instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。 The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in Within the scope of protection of the present invention.

Claims

一种图像去隔行装置，所述装置包括：配置模块及去隔行模块；其中，An image deinterlacing device, the device comprising: a configuration module and a deinterlacing module; wherein

所述配置模块，配置为根据接收的去隔行模式指令，确定待处理图像数据的去隔行模式；The configuration module is configured to determine a deinterlace mode of image data to be processed according to the received deinterlace mode instruction;

所述去隔行模块，配置为采用配置模块确定的去隔行模式对应的去隔行逻辑对所述待处理图像数据进行去隔行处理，并关闭除所述确定的去隔行模式对应的去隔行逻辑外的其它去隔行逻辑。The deinterlacing module is configured to deinterlace the image data to be processed by deinterlacing logic corresponding to the deinterlacing mode determined by the configuration module, and close the deinterlacing logic corresponding to the determined deinterlacing mode. Other deinterlacing logic.
根据权利要求1所述的装置，其中，所述配置模块，配置为：根据接收的去隔行模式指令，将去隔行寄存器进行相应去隔行模式的指示配置；The apparatus according to claim 1, wherein the configuration module is configured to: perform an indication configuration of the deinterlace mode in the deinterlace mode according to the received deinterlace mode instruction;

相应地，所述去隔行模块，配置为根据所述去隔行寄存器的指示配置，采用对应的去隔行逻辑对所述待处理图像数据进行去隔行处理，并关闭除所述确定的去隔行模式对应的去隔行逻辑外的其它去隔行逻辑。Correspondingly, the deinterlacing module is configured to deinterlace the image data to be processed by using corresponding deinterlacing logic according to the indication configuration of the deinterlace register, and close the deinterlacing mode corresponding to the determined deinterlacing mode. Deinterlacing logic other than deinterlacing logic.
根据权利要求1所述的装置，其中，所述配置模块，还配置为：The device of claim 1, wherein the configuration module is further configured to:

根据待处理图像数据的长和宽，在分辨率寄存器中对待处理图像数据的分辨率进行配置；并在使能寄存器中配置用于使能所述去隔行模块的第一使能信号。The resolution of the image data to be processed is configured in the resolution register according to the length and width of the image data to be processed; and the first enable signal for enabling the deinterlacing module is configured in the enable register.
根据权利要求3所述的装置，其中，所述配置模块，还配置为当确定的去隔行模式对应的去隔行逻辑为带有运动检测的四场去隔行逻辑时，在使能寄存器中配置用于使能所述去隔行模块的第一使能信号之前，在阈值寄存器中配置第一阈值以及第二阈值；所述第一阈值以及第二阈值用于判断像素是处于运动状态或静止状态。The apparatus according to claim 3, wherein said configuration module is further configured to configure in the enable register when the deinterlace logic corresponding to the determined deinterlace mode is four-field deinterlacing logic with motion detection Before the first enable signal of the deinterlacing module is enabled, the first threshold and the second threshold are configured in the threshold register; the first threshold and the second threshold are used to determine whether the pixel is in a motion state or a stationary state.
根据权利要求3或4所述的装置，其中，所述配置模块，还配置为当一帧图像数据处理完毕，且后续还有图像数据需要处理时，在中断寄存器中配置用于清除中断信号的第二使能信号，并重新对分辨率寄存器进行配置，或者重新对分辨率寄存器和阈值寄存器进行配置。The apparatus according to claim 3 or 4, wherein the configuration module is further configured to: when the image data of one frame is processed, and the image data needs to be processed subsequently, the interrupt register is configured to clear the interrupt signal. Second enable signal and re-send the resolution register Configure or reconfigure the resolution and threshold registers.
根据权利要求5所述的装置，其中，所述装置还包括：顶层模块、及同步模块；其中，The device according to claim 5, wherein the device further comprises: a top module, and a synchronization module; wherein

所述顶层模块，配置为提供所述装置与外部连接的输入输出接口；The top layer module is configured to provide an input and output interface of the device and an external connection;

所述同步模块，配置为将所述配置模块配置的各寄存器的参数同步至所述去隔行模块。The synchronization module is configured to synchronize parameters of respective registers configured by the configuration module to the deinterlacing module.
根据权利要求6所述的装置，其中，所述同步模块，配置为：将各寄存器的时钟通过握手信号同步为所述去隔行模块的工作时钟。The apparatus of claim 6, wherein the synchronization module is configured to synchronize the clock of each register to a working clock of the deinterlacing module by a handshake signal.
根据权利要求1所述的装置，其中，所述去隔行模块，还配置为采用ram复用的方式，对所述待处理图像数据进行去隔行处理。The apparatus according to claim 1, wherein the deinterlacing module is further configured to perform deinterlacing processing on the image data to be processed by means of ram multiplexing.
一种图像去隔行方法，所述方法包括：An image deinterlacing method, the method comprising:

根据接收的去隔行模式指令，确定待处理图像数据的去隔行模式；Deinterlacing the image data to be processed according to the received deinterlace mode command;

采用确定的去隔行模式对应的去隔行逻辑对所述待处理图像数据进行去隔行处理，并关闭除所述确定的去隔行模式对应的去隔行逻辑外的其它去隔行逻辑。Deinterlacing the image data to be processed by de-interlacing logic corresponding to the determined deinterlacing mode, and turning off deinterlacing logic other than the deinterlacing logic corresponding to the determined deinterlacing mode.
根据权利要求9所述的方法，其中，所述根据接收的去隔行模式指令，确定待处理图像数据的去隔行模式，包括：The method of claim 9, wherein the determining the deinterlacing mode of the image data to be processed according to the received deinterlacing mode instruction comprises:

根据接收的去隔行模式指令，将去隔行寄存器进行相应去隔行模式的指示配置，确定待处理图像数据的去隔行模式；De-interlacing the deinterlace mode according to the received de-interlace mode instruction, and determining the de-interlaced mode of the image data to be processed;

相应地，根据所述去隔行寄存器的指示配置，采用对应的去隔行逻辑对所述待处理图像数据进行去隔行处理，并关闭除所述确定的去隔行模式对应的去隔行逻辑外的其它去隔行逻辑。Correspondingly, according to the indication configuration of the deinterlace register, deinterlacing the image data to be processed by using corresponding deinterlacing logic, and turning off the deinterlacing logic corresponding to the determined deinterlacing mode Interlaced logic.
根据权利要求9所述的方法，其中，在所述确定的去隔行模式对应的去隔行逻辑对所述待处理图像数据进行去隔行处理，并关闭除所述确定的去隔行模式对应的去隔行逻辑外的其它去隔行逻辑之前，所述方法还包括：The method according to claim 9, wherein said de-interlacing logic corresponding to said determined deinterlacing mode deinterlaces said image data to be processed, and turns off deinterlacing corresponding to said determined deinterlacing mode Before the logic de-interlacing logic, the method is still include:

根据待处理图像数据的长和宽，在分辨率寄存器中对待处理图像数据的分辨率进行配置；并在使能寄存器中配置用于使能所述去隔行模块的第一使能信号。The resolution of the image data to be processed is configured in the resolution register according to the length and width of the image data to be processed; and the first enable signal for enabling the deinterlacing module is configured in the enable register.
根据权利要求11所述的方法，其中，当确定的去隔行模式对应的去隔行逻辑为带有运动检测的四场去隔行逻辑时，在使能寄存器中配置用于使能所述去隔行模块的第一使能信号之前，所述方法还包括：The method of claim 11 wherein when the deinterlacing logic corresponding to the determined deinterlacing mode is four field deinterlacing logic with motion detection, configuring the deinterlacing module in the enable register Before the first enable signal, the method further includes:

在阈值寄存器中配置第一阈值以及第二阈值；所述第一阈值以及第二阈值用于判断像素是处于运动状态或静止状态。A first threshold and a second threshold are configured in the threshold register; the first threshold and the second threshold are used to determine whether the pixel is in a motion state or a stationary state.
根据权利要求11或12所述的方法，其中，当一帧图像数据处理完毕，且后续还有图像数据需要处理时，所述方法还包括：The method according to claim 11 or 12, wherein when the processing of one frame of image data is completed, and the image data is subsequently processed, the method further comprises:

在中断寄存器中配置用于清除中断信号的第二使能信号，并重新对分辨率寄存器进行配置，或者重新对分辨率寄存器和阈值寄存器进行配置。A second enable signal for clearing the interrupt signal is configured in the interrupt register, and the resolution register is reconfigured or the resolution register and threshold register are reconfigured.
根据权利要求13所述的方法，其中，配置完各寄存器，且在所述确定的去隔行模式对应的去隔行逻辑对所述待处理图像数据进行去隔行处理，并关闭除所述确定的去隔行模式对应的去隔行逻辑外的其它去隔行逻辑之前，所述方法还包括：The method according to claim 13, wherein each register is configured, and the deinterlacing logic corresponding to the determined deinterlacing mode deinterlaces the image data to be processed, and turns off the determination Before the interlaced logic corresponding to the deinterlacing logic corresponding to the interlaced mode, the method further includes:

将配置的各寄存器的参数同步至图像去隔行装置的去隔行模块。Synchronize the parameters of the configured registers to the deinterlacing module of the image deinterlacer.
根据权利要求14所述的方法，其中，所述将配置的各寄存器的参数同步至去隔行处理的装置的去隔行模块，为：The method of claim 14, wherein said synchronizing the parameters of the configured registers to the deinterlacing module of the deinterlacing device is:

将各寄存器的时钟通过握手信号同步为所述去隔行模块的工作时钟。The clocks of the respective registers are synchronized by the handshake signal to the operating clock of the deinterlacing module.
根据权利要求9所述的方法，其中，在对所述待处理图像进行去隔行处理时，所述方法还包括：采用ram复用的方式，对所述待处理图像数据进行去隔行处理。The method according to claim 9, wherein when the image to be processed is deinterlaced, the method further comprises: deinterlacing the image data to be processed by using ram multiplexing.
根据权利要求16所述的方法，其中，所述采用ram复用的方式，对所述待处理图像数据进行去隔行处理，包括：The method according to claim 16, wherein said ram multiplexing is performed, Deinterlacing the image data to be processed, including:

在不使能去隔行模式下，ram配置为存储待处理数据，以使非同步输入的数据进行同步输出；In the de-interlace mode, the ram is configured to store the data to be processed, so that the asynchronous input data is synchronously output;

在场内去隔行模式或带有运动检测的四场去隔行模式下，所述ram，配置为存储待处理图像数据中的第N行图像数据及待处理图像数据中的第N-1行图像数据，以使在场内去隔行模式对应的去隔行逻辑或带有运动检测的四场去隔行模式对应的去隔行逻辑对所述待处理图像数据进行相应的去隔行处理。In the inter-bank deinterlacing mode or the four-field deinterlacing mode with motion detection, the ram is configured to store the Nth line image data in the image data to be processed and the N-1th line image data in the image data to be processed. The deinterlacing logic corresponding to the deinterlacing logic corresponding to the interlaced mode in the field or the deinterlacing logic corresponding to the four-field deinterlacing mode with motion detection performs corresponding deinterlacing processing on the image data to be processed.
一种计算机存储介质，所述计算机存储介质包括一组指令，当执行所述指令时，引起至少一个处理器执行如权利要求9至17任一项所述的图像去隔行方法。 A computer storage medium comprising a set of instructions that, when executed, cause at least one processor to perform the image deinterlacing method of any one of claims 9-17.