WO2015136603A1 - Power semiconductor module, and manufacturing and inspection method therefor - Google Patents

Power semiconductor module, and manufacturing and inspection method therefor Download PDF

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Publication number
WO2015136603A1
WO2015136603A1 PCT/JP2014/056207 JP2014056207W WO2015136603A1 WO 2015136603 A1 WO2015136603 A1 WO 2015136603A1 JP 2014056207 W JP2014056207 W JP 2014056207W WO 2015136603 A1 WO2015136603 A1 WO 2015136603A1
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terminal contact
contact portion
circuit pattern
sic
electrically connected
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PCT/JP2014/056207
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French (fr)
Japanese (ja)
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安井　感
善章 豊田
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株式会社日立製作所
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Priority to PCT/JP2014/056207 priority Critical patent/WO2015136603A1/en
Publication of WO2015136603A1 publication Critical patent/WO2015136603A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2637—Circuits therefor for testing other individual devices
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/45001—Core members of the connector
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    • H01L2224/45014—Ribbon connectors, e.g. rectangular cross-section
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    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to a power semiconductor module and a manufacturing inspection method thereof.
  • SiC silicon carbide
  • SiC has a wide energy band gap, a dielectric breakdown electric field strength that is an order of magnitude higher than that of silicon, and is suitable for high-voltage applications. Its thermal conductivity is three times that of silicon, and it does not lose its semiconductor properties even at high temperatures. In particular, it is resistant to temperature rise and can reduce the resistance of the element, so it is suitable as a power semiconductor material.
  • the development of a hybrid module in which the switching diode and the rectifying element of the power module constituting the inverter are replaced with silicon instead of the rectifying element (freewheeling diode) is leading.
  • the rectifying element has a simple structure and operation compared to the switching element, facilitates the development of the element, and clearly shows the merit of greatly reducing the switching loss.
  • a conventional power module uses a silicon IGBT (Insulated Gate Bipolar Transistor) as a switching element, and a silicon PN diode is used as a free-wheeling diode to be combined in antiparallel.
  • IGBT Insulated Gate Bipolar Transistor
  • SiC low-resistance SiC makes it possible to apply unipolar SBDs up to high breakdown voltage regions where conventional silicon SBDs such as breakdown voltages of 600 V to 3.3 kV could not be applied.
  • Patent Document 1 As a known example of a power semiconductor device having a power semiconductor element using Si as a base and a power semiconductor element using SiC as a base, there is a technique described in Patent Document 1.
  • SiC hybrid module Due to the excellent physical properties of SiC, SBD can be applied to the high breakdown voltage region, and a SiC hybrid module combined with high breakdown voltage silicon IGBT (Si-IGBT) can be realized. On the other hand, there is a problem peculiar to the SiC hybrid module that occurs because the characteristics of both are different.
  • Si-IGBT and SiC SBD are different, which causes a problem in the accuracy of defect detection.
  • Si-IGBT and SiC-SBD are combined in antiparallel with each other.
  • the leak current inspection since a high voltage is applied between the collector terminal and the emitter terminal, the same voltage is always applied between the collector and emitter of the Si-IGBT and the cathode and anode of the SiC-SBD, and the sum of the leak currents of both is detected.
  • the leakage current of the SiC-SBD having a Schottky barrier with a low barrier height is several orders of magnitude greater than the leakage current of the Si-IGBT.
  • FIG. 19 shows a typical leakage current profile in the case of both 3.3 kV breakdown voltage elements as an example.
  • the leakage current of SiC-SBD (broken line) is 1 to 2 orders of magnitude larger than the leakage current of Si-IGBT (solid line) in the range of 3.3 to 3.6 kV where the defect is determined.
  • the leakage current of the Si-IGBT increases to about 1000 times the room temperature, while the SiC-SBD increases only about several tens of times. Will increase.
  • the background leakage current level increases, and the difference from the leakage current caused by a defect due to a process defect becomes small and the S / N ratio is lowered.
  • Si-IGBT and SiC-SBD may be possible to detect defects independently by inspecting the leakage current of Si-IGBT and SiC-SBD in the chip state before assembling the device, but this is not sufficient.
  • the leakage defects of Si-IGBT there are defects due to the defects of the back surface structure peculiar to the IGBT, and these leakage defects become obvious only after soldering the back surface of the chip. A leak failure is not detected only by contacting the back surface of the chip. For this reason, leakage current is first inspected at the wafer or chip stage, but inspection is also required after the chip is mounted on an insulating substrate or the like.
  • a power semiconductor element using Si as a base and a power semiconductor element using a band gap semiconductor element such as SiC as a base are mounted on separate insulating substrates.
  • the positive and negative main terminals to which the power semiconductor element is connected are electrically separated from each other.
  • Patent Document 1 has the following problems.
  • An object of the present invention is to realize a power semiconductor module capable of ensuring element integration density, reducing inductance, and performing dynamic characteristic inspection without complicated operations, and a manufacturing inspection method thereof.
  • the present invention is configured as follows to achieve the above object.
  • the power semiconductor module of the present invention electrically connects a semiconductor element using silicon as a substrate.
  • the power semiconductor module of the present invention is formed in the first circuit pattern, and the first terminal contact portion connected to one end of the semiconductor element to which the first circuit pattern is electrically connected; A second terminal contact portion formed in a second circuit pattern, connected to one end of a semiconductor element to which the second circuit pattern is electrically connected, and formed adjacent to the first terminal contact portion. And the first circuit pattern is connected to the other end of the electrically connected semiconductor element, and the second circuit pattern is connected to the other end of the electrically connected semiconductor element, on the substrate.
  • a common main terminal contact portion to be formed and an electrode main terminal are provided, and the first terminal contact portion and the second terminal contact portion are electrically connected to each other by the electrode main terminal.
  • the manufacturing inspection method for the power semiconductor module according to the present invention includes a leakage of a semiconductor element to which the first circuit pattern is electrically connected by using the first terminal contact portion and the common main terminal contact portion.
  • a current inspection is performed, and a leakage current inspection of the semiconductor element to which the second circuit pattern is electrically connected is performed using the second terminal contact portion and the common main terminal contact portion.
  • the terminal contact portion and the second terminal contact portion are electrically connected, and the first terminal contact portion, the second terminal contact portion, and the common terminal contact portion are used to connect the first terminal contact portion and the second terminal contact portion.
  • a dynamic inspection is performed on the semiconductor element to which the first circuit pattern is electrically connected and the semiconductor element to which the second circuit pattern is electrically connected.
  • the first terminal contact portion and the second terminal contact portion are connected to each other by the electrode main terminal.
  • FIG. 1 is a diagram showing a first embodiment of the present invention, in which a Si-IGBT as a switching element group and a SiC-SBD as a diode element group of a 3.3 kV withstand voltage product are electrically separated.
  • a Si-IGBT as a switching element group
  • a SiC-SBD as a diode element group of a 3.3 kV withstand voltage product are electrically separated.
  • an insulating substrate with a separated circuit pattern on the emitter terminal side is shown.
  • FIG. 16 is an external view of a power module (which is also applied to the present invention), and FIG. 17 is a diagram showing a circuit configuration example of a general power module (G: gate, E: emitter, C: collector) ).
  • G gate, E: emitter, C: collector
  • FIG. 18 is an enlarged view of the insulating substrate 22.
  • each insulating substrate 22 a plurality of switching elements 23 (IGBT, MOS, etc.) and freewheeling diodes 24 are mounted in each insulating substrate 22.
  • IGBT IGBT
  • MOS metal-oxide-semiconductor
  • freewheeling diodes 24 are mounted in each insulating substrate 22.
  • Each insulating substrate 22 is in electrical contact with the outside through an electrode main terminal 21 shown in FIG.
  • FIG. 16 shows an example of a 1 in 1 configuration in which a single power module is combined with a set of IGBTs and diodes.
  • the emitter of the Si-IGBT and the anode of the SiC-SBD are electrically coupled by a common emitter circuit pattern 27 as shown in FIG. Through the common emitter main terminal contact 28 to the outside of the module.
  • FIG. 1 is a diagram showing an insulating substrate 60 in the first embodiment of the present invention.
  • the emitter circuit patterns are 29 on the Si-IGBT side and on the SiC-SBD side.
  • the main terminal contact part is also divided into 31 and 32 correspondingly.
  • the Si-IGBT side emitter main terminal contact 31 and the SiC-SBD side emitter main terminal contact 32 which are close to each other can be connected, and the dynamic characteristic inspection can be performed before the module assembly. Further, since the Si-IGBT side emitter main terminal contact 31 and the SiC-SBD side emitter main terminal contact 32 are formed close to each other, the closed loop formed by the current path can be reduced, and the parasitic inductance can be reduced. Can do.
  • FIG. 2 is a circuit diagram at the time of substrate sorting inspection in the first embodiment of the present invention.
  • the coupling between the emitter side of the Si-IGBT and the SiC-SBD anode side is separated.
  • the gate (G) and the emitter (E) are short-circuited, the E_SW terminal 31 is grounded, and the collector terminal (C) 43 (common main terminal contact portion) has a high voltage (up to 3.6 kV). Voltage) is applied.
  • the E_FWD terminal 32 is grounded and a similar high voltage is applied to the collector terminal 43.
  • the same kind of element group of Si-IGBT or SiC-SBD mounted is connected in parallel and inspected at the same time.
  • a normal leakage current profile is shown in FIG. 19.
  • the leakage current may increase rapidly from a certain voltage range.
  • FIG. 18 there is a problem that an abnormality cannot be detected behind the leakage current of SiC-SBDs connected in parallel, and a non-defective product is erroneously detected.
  • both can be measured independently, no defects are missed.
  • FIG. 3 is a flowchart of the substrate inspection according to the first embodiment of the present invention.
  • an open / short check is performed before application of a high voltage (step S1), and then a leakage current inspection for applying a high voltage is performed independently in the order of Si-IGBT and SiC-SBD (step S2). , S3).
  • an RBSOA (Reverse Bias Safe Operating Area) test and a recovery SOA test are performed as a dynamic characteristic inspection for each substrate (step S4).
  • RBSOA Reverse Bias Safe Operating Area
  • the E_SW terminal 31 and the E_FWD terminal 32 on the emitter side shown in the circuit diagram of FIG. Perform in a shorted state.
  • the E_SW terminal 31 and the E_FWD terminal 32 that are close to each other can be coupled at the time of measurement, there is an advantage that both a breakdown voltage test independent of each element group and a dynamic characteristic test combining both can be performed.
  • FIG. 4 shows a flowchart of substrate inspection in the example shown in FIG.
  • the withstand voltage test is performed independently for each element group, but in the example shown in FIG. 18, Si-IGBT and SiC-SBD are simultaneously used. It is executed (step S0).
  • step S0 it is possible to introduce an inspection method with a current track record with only one step increase. For this reason, the present invention has good compatibility with existing production lines and can follow established reliability test methods.
  • FIG. 5 is an enlarged view of a connection portion between the main terminal 21 and the insulating substrate 60 at this time.
  • the electrode main terminal 21 has a shape in which terminals branched toward the E_SW terminal 31 and the E_FWD terminal 32, which are contact portions, are coupled immediately above the substrate 60, thereby suppressing an increase in parasitic inductance to a minimum.
  • the cover 26 is installed in the case 25 and assembled as a semiconductor module.
  • the insulating substrate 60 is made of a material having high thermal conductivity such as aluminum nitride, silicon nitride, alumina, or the like, so that the heat generated by the elements on the insulating substrate 60 can be efficiently radiated. ing.
  • a plurality of Si-IGBTs 11 and a plurality of SiC-SBDs 12 are formed on one insulating substrate 60 and separated from each other in the central region of the substrate 60.
  • -IGBT side circuit pattern 29 and SiC-SBD side circuit pattern 30 are formed, and Si-IGBT side emitter main terminal contact 31 and SiC-SBD side emitter main terminal contact 32 are arranged close to each other.
  • the SiC-SBD 12 and the Si-IGBT 11 are separated from each other to perform a leakage current inspection, and the SiC-SBD 12 and the Si-IGBT 11 are connected by a connection pin or the like to perform a dynamic inspection.
  • the anode of the SiC-SBD 12 and the emitter of the Si-IGBT 11 separated from each other are connected by the electrode main terminal 21 when the power module is assembled, and the connection work between the anode of the SiC-SBD 12 and the emitter of the Si-IGBT 11 is complicated There is no action involved.
  • a power semiconductor module capable of ensuring element integration density, reducing inductance, and performing dynamic characteristic inspection without complicated operations, and a manufacturing inspection method thereof are realized. be able to.
  • the second embodiment of the present invention is an example in which the collector terminal of the Si-IGBT and the cathode terminal of the SiC-SBD are separated.
  • FIG. 6 shows an insulating substrate 60 in the second embodiment of the present invention.
  • FIG. 7 is a circuit diagram in the second embodiment of the present invention. In the first embodiment, the emitter and the anode are separated, whereas in the second embodiment, the collector and the cathode are separated.
  • the wire bonding length from the diode and the complexity of the wiring pattern are increased, but the collector side where high voltage is applied is separated from the normally grounded emitter side. There is an advantage that stress on non-measuring elements can be reduced.
  • each element on the insulating substrate 60 is as follows. There is a part similar to the first embodiment, but the collector side circuit pattern is separated into two, a circuit pattern 33 on the Si-IGBT side and a circuit pattern 34 on the SiC-SBD side. This is different from the first embodiment.
  • the second embodiment of the present invention can also obtain the same effect as the first embodiment.
  • FIG. 8 is a diagram showing a configuration of an insulating substrate having a structure in which sense terminals are separated when the present invention is not applied.
  • an emitter sense terminal extraction circuit pattern 37 and a gate terminal extraction circuit pattern 38 are provided on the opposite side of the main terminal. Further, there are a plurality of main terminal contact portions 39, which are arranged close to the main terminal contact portions 39 of adjacent substrates arranged opposite to each other, and are characterized in that the parasitic inductance of the main terminals can be reduced as much as possible. It has become.
  • SiC-SBD SiC-SBD, where ringing is likely to occur due to parasitic inductance during high-speed switching.
  • FIG. 9 is a diagram showing an insulating substrate 60 in the third embodiment of the present invention, which is an example of a configuration in which a circuit pattern on the emitter terminal side is separated.
  • the wire bonding 41 extending from the Si-IGBT 11 to the island circuit pattern 40 is not connected at the stage of substrate selection inspection.
  • the circuit is in the state shown in FIG. 2, and the leakage currents of Si-IGBT and SiC-SBD can be independently evaluated.
  • a jig that contacts the contact portion 43 of the collector terminal, the sense terminal circuit pattern 37 of the emitter, and the gate terminal circuit pattern 38 short-circuited with the emitter may be used.
  • an electrical connection may be made from the contact portion 43 of the collector terminal and the contact portion 28 of the emitter terminal.
  • FIG. 10 is a flowchart of substrate inspection in the third embodiment. Steps S1, S2, S3, and S4 are the same as the example shown in FIG. 3, but in the third embodiment, the Si-IGBT 11 and the relay island pattern 40 are between the steps S3 and S4. Are connected by wire bonding 41 (step S44).
  • the substrate inspection process sandwiches the wire bonding process S44 after the leakage current measurement, there is a disadvantage that the number of processes is increased by being divided into two.
  • the configuration of the interface portion between the contact portions 28 and 43 with the main terminal and the surroundings such as the sense terminal portions 37 and 38 is the same as the existing method, the measurement tool for the main terminal structure and the substrate selection inspection is used. There is a feature that there is no need to change the design of the system, the introduction cost can be suppressed, and the advantage that parts and processes can be shared is great.
  • FIG. 11 is a diagram showing a fourth embodiment of the present invention.
  • the collector terminal circuit pattern 33 on the Si-IGBT side and the circuit pattern 34 on the collector terminal (cathode side terminal) on the SiC-SBD side are separated, and main terminal contact portions 35 and 36 are provided.
  • the emitter terminal contact portion 28 is common, and the collector terminal contact portion side can be used separately for the Si-IGBT 35 and the SiC-SBD 36, whereby the leakage current inspection of both can be performed independently.
  • the substrate inspection flow is the flow shown in FIG. 3 as in the first embodiment.
  • FIG. 12 is an explanatory diagram of the substrate sorting inspection jig 61.
  • the substrate sorting inspection jig 61 includes a main terminal pin 51, a gate pin 52, a sense pin 53, a current detection terminal 55, and a cable 54 that connects the main terminal pin 51, the gate pin 52, and the sense pin 53 to the current detection terminal 55. It has.
  • the main terminal pin 51 is connected to the main terminal contact portions 35 and 36 and the emitter terminal contact portion 28 of the insulating substrate 60.
  • the sense pin 53 is connected to the sense terminal circuit pattern 37 on the insulating substrate 60, and the gate pin 52 is connected to the gate circuit pattern 38 on the insulating substrate 60.
  • FIG. 13 is a diagram showing the configuration of the insulating substrate 60 in the fifth embodiment of the present invention.
  • the emitter side connection is separated.
  • the wire 45 extending from the Si-IGBT 11 to the emitter terminal circuit pattern 27 is not connected at the stage of substrate selection inspection. At this time, the circuit is in the state shown in FIG.
  • the leakage current inspection of both the Si-IGBT and the SiC-SBD is independently performed in a state where the wire 45 that connects the Si-IGBT 11 and the emitter terminal circuit pattern 27 is not connected.
  • a dynamic characteristic inspection such as RBSOA is performed.
  • the substrate inspection flow is the same as that of the third embodiment, which is the flow shown in FIG.
  • the layout efficiency is improved by arranging the emitter terminal circuit pattern 27 near the center of the substrate and adjoining both the Si-IGBT 11 and the SiC-SBD 12.
  • the number of mounted chips of SiC-SBD 12 can be increased from 10 chips in the third embodiment to 12 chips in the fifth embodiment.
  • FIG. 14 is a diagram showing a sixth embodiment of the present invention, and shows an example of a configuration in which the pattern of the emitter terminal wiring portion is divided.
  • the leakage current inspection of the Si-IGBT 11 is performed by using the contact portion 31 and the collector terminal contact portion 35 of the emitter side circuit pattern 29, and the leakage current inspection of the SiC-SBD 12 is performed by the contact portion 32 and the collector of the other emitter side circuit pattern 30. This is performed using the terminal contact portion 35.
  • the final connection on the emitter side is performed by connecting the contact portions 31 and 32 with the main terminal 21 simultaneously with the attaching process of the main terminal 21.
  • FIG. 15 is a diagram showing a seventh embodiment of the present invention, which is an example of separating a circuit pattern on the collector side.
  • the configuration of the insulating substrate is such that the collector terminal circuit pattern 33 on the Si-IGBT 11 side and the circuit pattern 34 on the collector terminal (cathode side) on the SiC-SBD 12 side are separated, and each main terminal contact portion 35 and 36 are provided.
  • the emitter terminal contact portion 28 is common, and the collector terminal contact portion side can be separately used for the Si-IGBT 11 and the SiC-SBD 12, whereby the leakage current inspection of both can be performed independently.
  • the substrate inspection flow is the flow shown in FIG. 3 as in the first embodiment.
  • the seventh embodiment inherits the advantages of the fifth embodiment with good layout efficiency and the ability to mount 12 chips of SiC-SBD, and also has the advantages of the sixth embodiment in which there is no increase in the flow of substrate inspection. Further, since the collector side to which a high voltage is applied is separated, there is an advantage that stress on the non-measuring element can be reduced.
  • tool suitable for the formation pattern of the insulated substrate 60 is used also about another Example.
  • the essence of this invention is the circuit which will be in the state electrically isolated in the test
  • a wiring structure is provided.
  • it is not limited to the combination of Si-IGBT and SiC-SBD, but a wide band gap semiconductor such as SiC, GaN, and diamond, and a general band such as silicon, gallium arsenide, and germanium. It is also effective for combinations of semiconductors with band gaps, and improves the inspection accuracy in combinations of Schottky barrier diodes and PN diodes and switching elements such as MOS, JFET, and bipolar transistors as element groups with different leakage current characteristics. be able to.
  • examples of the switching element made of a wide band gap semiconductor include a GaN transistor (HEMT) and a transistor made of diamond.
  • HEMT GaN transistor
  • the structure in which the electrical circuit of the diode element and the switching element is not closed realizes the circuit configuration on the insulating substrate by a circuit pattern or a wiring pattern electrically separated by the diode element group and the switching element group. At the same time as the wire connection process after inspection, ribbon bonding, lead frame, etc., or the process of connecting the main terminals of the module, there is no increase in the process by connecting the unbonded parts, or with minimal addition An electrical circuit can be completed.
  • the pattern to be separated in advance is sufficient if it is at least one of the collector terminal (cathode side for the diode) and the emitter terminal (anode side for the diode) of the circuit in which the switching element and the diode element are combined in antiparallel. It is.
  • the power semiconductor module of the present invention realizes low loss and miniaturization as a hybrid module, and can realize high reliability because leakage defects can be detected and eliminated with high accuracy.
  • a leakage failure of Si-IGBT having a relatively low room temperature leakage current level is detected and eliminated with high accuracy.
  • leakage current defects due to Si-IGBT back surface defects are detected without fail, and the occurrence of defects during use such as increased leakage current due to deterioration over time and thermal runaway at the back surface defects can be prevented and higher withstand voltage reliability Can be realized.
  • the inspection is performed in a state where the pattern on the insulating substrate is separated, and the pattern is separated on the insulating substrate simultaneously with the subsequent wire bonding for terminal connection and the metal bonding process for main terminal bonding. Complete the electrical connection of the parts. For this reason, the number of process increases is zero or minimal.
  • the property measurement accuracy in the intermediate inspection process it becomes possible to detect process abnormalities early, elucidate the mechanism, and provide early feedback to the manufacturing process.

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Abstract

The present invention realizes a power semiconductor module that is capable of ensuring element integration density and reducing inductance, and which enables dynamic properties to be inspected without performing complicated work. A plurality of Si-IGBTs (11) and a plurality of SiC-SBDs (12) are formed on top of a single insulated substrate (60), and an Si-IGBT-side circuit pattern (29) and an SiC-SBD-side circuit pattern (30) are formed separated from each other in the center region of the substrate (60). An Si-IGBT-side emitter primary terminal contact (31) and an SiC-SBD-side emitter primary terminal contact (32) are arranged near each other. The SiC-SBDs (12) and the Si-IGBTs (11) are separated and a leak current inspection is performed respectively thereon, and the SiC-SBDs (12) and the Si-IGBTs (11) are connected with a connection pin or the like and a dynamic inspection is performed thereon. The anodes of the SiC-SBDs (12) and the emitters of the Si-IGBTs (11) are connected by an electrode primary terminal when the power module is assembled.

Description

パワー半導体モジュール及びその製造検査方法Power semiconductor module and manufacturing inspection method thereof
　本発明は、パワー半導体モジュールおよびその製造検査方法に関する。 The present invention relates to a power semiconductor module and a manufacturing inspection method thereof.
　インバータに代表される電力変換機器の中で、パワー半導体は整流機能やスイッチング機能をもつ主要な構成部品として使われている。パワー半導体の材料として現在はシリコンが主流であるが、物性に優れるシリコンカーバイド（ＳｉＣ）の採用に向けた開発が進んでいる。 In power conversion equipment represented by inverters, power semiconductors are used as main components with rectification and switching functions. Silicon is currently the mainstream material for power semiconductors, but development toward the adoption of silicon carbide (SiC), which has excellent physical properties, is in progress.
　ＳｉＣは、エネルギーバンドギャップが広く、シリコンに対して絶縁破壊電界強度が一桁高く高電圧用途に適すること、熱伝導率もシリコンの３倍で、かつ高温でも半導体の性質を失いにくいことから原理的に温度上昇にも強く、素子の抵抗を下げられるためパワー半導体の材料として適している。 The principle of SiC is that it has a wide energy band gap, a dielectric breakdown electric field strength that is an order of magnitude higher than that of silicon, and is suitable for high-voltage applications. Its thermal conductivity is three times that of silicon, and it does not lose its semiconductor properties even at high temperatures. In particular, it is resistant to temperature rise and can reduce the resistance of the element, so it is suitable as a power semiconductor material.
　特に、インバータを構成するパワーモジュールのスイッチング素子と整流素子の内、整流素子の還流ダイオード（フリーホイーリングダイオード）をシリコンからＳｉＣに置き換えたハイブリッドモジュールの開発が先行している。整流素子はスイッチング素子に比べて構造と動作が単純で素子開発を進めやすいこと、またスイッチング損失を大幅に低減できるメリットが明確なことが理由にある。 In particular, the development of a hybrid module in which the switching diode and the rectifying element of the power module constituting the inverter are replaced with silicon instead of the rectifying element (freewheeling diode) is leading. The reason is that the rectifying element has a simple structure and operation compared to the switching element, facilitates the development of the element, and clearly shows the merit of greatly reducing the switching loss.
　従来のパワーモジュールはスイッチング素子としてシリコンのＩＧＢＴ（Insulated Gate Bipolar Transistor）を用いており、これと逆並列に組み合わせる還流ダイオードにはシリコンのＰＮダイオードを用いていた。 A conventional power module uses a silicon IGBT (Insulated Gate Bipolar Transistor) as a switching element, and a silicon PN diode is used as a free-wheeling diode to be combined in antiparallel.
　ここで、シリコンのＰＮダイオードをＳｉＣのショットキーバリアダイオード（ＳＢＤ、　Schottky Barrier Diode）に置き換えると、リカバリ電流が無いためスイッチング損失が１／１０に減るとの報告がある。 Here, it is reported that if the silicon PN diode is replaced with a SiC Schottky barrier diode (SBD, Schottky Barrier Diode), the switching loss is reduced to 1/10 because there is no recovery current.
　これはバイポーラ素子のＰＮダイオードではスイッチング時に蓄積された少数キャリアが、リカバリ電流として流れるが、ユニポーラ素子のＳＢＤでは少数キャリアの蓄積が無いためである。なお、シリコンでもＳＢＤを製造することは可能だが、耐圧を高めるためにボディ層の厚みを増すと抵抗が高くなり実用的ではない。 This is because, in the PN diode of the bipolar element, minority carriers accumulated at the time of switching flow as a recovery current, but in the SBD of the unipolar element, there is no accumulation of minority carriers. It is possible to manufacture SBD with silicon, but if the thickness of the body layer is increased in order to increase the withstand voltage, the resistance increases and is not practical.
　低抵抗なＳｉＣを用いることで、耐圧６００Ｖ～３．３ｋＶといった従来シリコンのＳＢＤを適用できなかった高耐圧領域までユニポーラのＳＢＤを適用することが可能になる。 Using low-resistance SiC makes it possible to apply unipolar SBDs up to high breakdown voltage regions where conventional silicon SBDs such as breakdown voltages of 600 V to 3.3 kV could not be applied.
　Ｓｉを基体として用いる電力半導体素子と、ＳｉＣを基体として用いる電力半導体素子とを有するパワー半導体装置の公知例としては、特許文献１に記載された技術がある。 As a known example of a power semiconductor device having a power semiconductor element using Si as a base and a power semiconductor element using SiC as a base, there is a technique described in Patent Document 1.
特開２０１０－２３２５７６号公報JP 2010-232576 A
　ＳｉＣの優れた物性によってＳＢＤを高耐圧領域まで適用可能となり、高耐圧のシリコンＩＧＢＴ（Ｓｉ－ＩＧＢＴ）と組み合わせるＳｉＣハイブリッドモジュールが実現可能になった。一方で、両者の特性が異なるために生じるＳｉＣハイブリッドモジュール特有の課題がある。 Due to the excellent physical properties of SiC, SBD can be applied to the high breakdown voltage region, and a SiC hybrid module combined with high breakdown voltage silicon IGBT (Si-IGBT) can be realized. On the other hand, there is a problem peculiar to the SiC hybrid module that occurs because the characteristics of both are different.
　実装工程のリーク電流検査工程では、Ｓｉ－ＩＧＢＴとＳｉＣのＳＢＤ（ＳｉＣ－ＳＢＤ）のリーク電流特性が異なるために不良検出の精度に問題が生じる。一般的なパワーモジュールの回路構成において、Ｓｉ－ＩＧＢＴとＳｉＣ－ＳＢＤは互いに逆並列に組み合わせられる。リーク電流検査ではコレクタ端子とエミッタ端子間に高電圧をかけるため、Ｓｉ－ＩＧＢＴのコレクタ－エミッタ間とＳｉＣ－ＳＢＤのカソード－アノード間に常に同じ電圧が加わり、両者のリーク電流の和が検出される。 In the leakage current inspection process of the mounting process, the leakage current characteristics of Si-IGBT and SiC SBD (SiC-SBD) are different, which causes a problem in the accuracy of defect detection. In a general power module circuit configuration, Si-IGBT and SiC-SBD are combined in antiparallel with each other. In the leak current inspection, since a high voltage is applied between the collector terminal and the emitter terminal, the same voltage is always applied between the collector and emitter of the Si-IGBT and the cathode and anode of the SiC-SBD, and the sum of the leak currents of both is detected. The
　検査を行う室温では、バリアハイトの低いショットキー障壁を持つＳｉＣ－ＳＢＤのリーク電流はＳｉ－ＩＧＢＴのリーク電流より数桁も大きい。 At the room temperature where the inspection is performed, the leakage current of the SiC-SBD having a Schottky barrier with a low barrier height is several orders of magnitude greater than the leakage current of the Si-IGBT.
　図１９に、一例として、両者の、３．３ｋＶ耐圧素子の場合の典型的なリーク電流プロファイルを示す。図１９において、不良判定を行う３．３～３．６ｋＶの範囲ではＳｉＣ－ＳＢＤのリーク電流（破線）はＳｉ－ＩＧＢＴ（実線）のリーク電流より１～２桁大きい。 FIG. 19 shows a typical leakage current profile in the case of both 3.3 kV breakdown voltage elements as an example. In FIG. 19, the leakage current of SiC-SBD (broken line) is 1 to 2 orders of magnitude larger than the leakage current of Si-IGBT (solid line) in the range of 3.3 to 3.6 kV where the defect is determined.
　このため、実質的にＳｉＣ－ＳＢＤのリーク電流のみが観測され、仮にＳｉ－ＩＧＢＴに異常があっても検出されない可能性がある。 For this reason, substantially only the leakage current of SiC-SBD is observed, and even if there is an abnormality in the Si-IGBT, it may not be detected.
　高温で検査を行えば、Ｓｉ－ＩＧＢＴのリーク電流が室温の１０００倍程度に増加する一方、ＳｉＣ－ＳＢＤは数十倍程度の増加に留まるため、両者のリーク電流は同程度もしくはＳｉ－ＩＧＢＴの方が増加する。しかし、高温ではバックグラウンドのリーク電流レベルが増加して、プロセス欠陥等による不良起因のリーク電流との差が僅かになりＳＮ比が下がるため不良検査には適さない。 If the inspection is performed at a high temperature, the leakage current of the Si-IGBT increases to about 1000 times the room temperature, while the SiC-SBD increases only about several tens of times. Will increase. However, at a high temperature, the background leakage current level increases, and the difference from the leakage current caused by a defect due to a process defect becomes small and the S / N ratio is lowered.
　装置の組み立てを行う前にＳｉ－ＩＧＢＴとＳｉＣ－ＳＢＤをチップ状態でリーク電流を検査すれば両者独立に不良を検出できると思われるが、これも十分ではない。Ｓｉ－ＩＧＢＴのリーク不良の中には、ＩＧＢＴ特有の裏面構造の欠陥に起因した不良があり、これらはチップ裏面を半田付けした後に初めてリーク不良が顕在化し、チップ検査時の平坦な金属電極とチップ裏面が接触しただけではリーク不良が検出されない。このことから、まずウエハやチップの段階でリーク電流の検査が行われるが、絶縁基板等にチップを実装した後にも検査が必要となっている。 It may be possible to detect defects independently by inspecting the leakage current of Si-IGBT and SiC-SBD in the chip state before assembling the device, but this is not sufficient. Among the leakage defects of Si-IGBT, there are defects due to the defects of the back surface structure peculiar to the IGBT, and these leakage defects become obvious only after soldering the back surface of the chip. A leak failure is not detected only by contacting the back surface of the chip. For this reason, leakage current is first inspected at the wafer or chip stage, but inspection is also required after the chip is mounted on an insulating substrate or the like.
　そこで、特許文献１に記載された技術においては、Ｓｉを基体として用いる電力半導体素子と、ＳｉＣ等のバンドギャップ半導体素子を基体として用いる電力半導体素子とが、それぞれ別の絶縁基板に搭載され、両電力半導体素子が接続される正負極主端子は互いに電気的に分離されている。 Therefore, in the technique described in Patent Document 1, a power semiconductor element using Si as a base and a power semiconductor element using a band gap semiconductor element such as SiC as a base are mounted on separate insulating substrates. The positive and negative main terminals to which the power semiconductor element is connected are electrically separated from each other.
　これにより、両電力半導体素子のリーク電流が正確に検知できるように構成されている。 Thus, the leakage current of both power semiconductor elements can be accurately detected.
　しかしながら、特許文献１に記載の技術は以下のような問題点があった。 However, the technique described in Patent Document 1 has the following problems.
　１．素子集積度の低下
　特許文献１に記載の技術のような基板分離方式では、接続端子領域（主端子、センス端子）や基板外周絶縁部、幾何学的余剰領域が存在するため、素子集積度が低下してしまう。パワーモジュールは、年次と共に電力密度を向上してきており、さらなる電力密度（素子集積度にほぼ等しい）の向上が要求されているが、それに十分に応えることが困難である。 1. Decrease in device integration degree In the substrate separation method such as the technique described in Patent Document 1, since the connection terminal region (main terminal, sense terminal), the substrate outer peripheral insulating portion, and the geometric surplus region exist, the device integration degree is low. It will decline. The power module has been improved in power density with the years, and further improvement in power density (approximately equal to the degree of device integration) is required, but it is difficult to sufficiently respond to it.
　２．インダクタンス低減化の困難
　特許文献１に記載の技術のような基板分離方式では、主端子間を接近させることが困難であり、電流経路が作る閉ループを小さくすることができず、寄生インダクタンスを低減することが困難である。これにより、スイッチング時の電圧変動を低減することが困難である。 2. Difficulty in reducing inductance In the substrate separation system such as the technique described in Patent Document 1, it is difficult to bring the main terminals close to each other, the closed loop formed by the current path cannot be reduced, and the parasitic inductance is reduced. Is difficult. This makes it difficult to reduce voltage fluctuations during switching.
　３．動的特性検査の煩雑化
　特許文献１に記載の技術のような基板分離方式では、モジュールを組み立てる前に基板毎に特性検査を実施するが、スイッチング動作を行う動的特性検査には、ＳｉのＩＧＢＴとＳｉＣのダイオードとの双方の素子が互いに接続された状態で行う必要がある。特許文献１に記載の基板分離方式でも、モジュールを組み立てた後に動的特性検査を行うことは可能であるが、モジュールを組み立てる前に、動的特性の検査を実行し、その良否を判断することが必要である。特許文献１では、その点につき、考慮がなされておらず、モジュール組立前に動的検査を行う場合は、煩雑な作業を伴ってしまうと考えられる。 3. Complicated dynamic characteristic inspection In the substrate separation method such as the technique described in Patent Document 1, the characteristic inspection is performed for each substrate before assembling the module. It is necessary to perform the process in a state where both elements of the IGBT and the SiC diode are connected to each other. Even with the substrate separation method described in Patent Document 1, it is possible to perform a dynamic characteristic inspection after assembling the module. However, before assembling the module, a dynamic characteristic inspection is performed to determine whether the module is good or bad. is required. In Patent Document 1, this point is not taken into consideration, and it is considered that a complicated operation is involved when performing dynamic inspection before module assembly.
　本発明の目的は、素子集積密度の確保、インダクタンスの低減、煩雑な作業を伴うことのない動的特性検査が可能なパワー半導体モジュール及びその製造検査方法を実現することである。 An object of the present invention is to realize a power semiconductor module capable of ensuring element integration density, reducing inductance, and performing dynamic characteristic inspection without complicated operations, and a manufacturing inspection method thereof.
　本発明は、上記目的を達成するため、次のように構成される。 The present invention is configured as follows to achieve the above object.
　本発明のパワー半導体モジュールは、シリコンを基体として用いる半導体素子を電気的に

接続する第１の回路パターンと、シリコンよりエネルギーバンドギャップが広い半導体素子を基体として用いる半導体素子を電気的に接続する第２の回路パターンと、少なくとも上記第１の回路パターンと上記第２の回路パターンとが共に形成された基板とを備える。 The power semiconductor module of the present invention electrically connects a semiconductor element using silicon as a substrate.

A first circuit pattern to be connected; a second circuit pattern for electrically connecting a semiconductor element using a semiconductor element having a wider energy band gap than silicon as a base; and at least the first circuit pattern and the second circuit And a substrate on which a pattern is formed.
　さらに、本発明のパワー半導体モジュールは、上記第１の回路パターンに形成され、上記第１の回路パターンが電気的に接続する半導体素子の一方端に接続された第１の端子コンタクト部と、上記第２の回路パターンに形成され、上記第２の回路パターンが電気的に接続する半導体素子の一方端に接続され、上記第１の端子コンタクト部に隣接して形成された第２の端子コンタクト部と、上記第１の回路パターンが電気的に接続する半導体素子の他方端に接続されると共に、上記第２の回路パターンが電気的に接続する半導体素子の他方端に接続され、上記基板上に形成される共通主端子コンタクト部と、電極主端子とを備え、上記第１の端子コンタクト部と上記第２の端子コンタクト部とは電極主端子により互いに電気的に接続される。 Furthermore, the power semiconductor module of the present invention is formed in the first circuit pattern, and the first terminal contact portion connected to one end of the semiconductor element to which the first circuit pattern is electrically connected; A second terminal contact portion formed in a second circuit pattern, connected to one end of a semiconductor element to which the second circuit pattern is electrically connected, and formed adjacent to the first terminal contact portion. And the first circuit pattern is connected to the other end of the electrically connected semiconductor element, and the second circuit pattern is connected to the other end of the electrically connected semiconductor element, on the substrate. A common main terminal contact portion to be formed and an electrode main terminal are provided, and the first terminal contact portion and the second terminal contact portion are electrically connected to each other by the electrode main terminal.
　また、本発明のパワー半導体モジュールの製造検査方法は、上記第１の端子コンタクト部と、上記共通主端子コンタクト部とを用いて、上記第１の回路パターンが電気的に接続する半導体素子のリーク電流検査を行い、上記第２の端子コンタクト部と、上記共通主端子コンタクト部とを用いて、上記第２の回路パターンが電気的に接続する半導体素子のリーク電流検査を行い、上記第１の端子コンタクト部と上記第２の端子コンタクト部とを電気的に接続し、接続した上記第１の端子コンタクト部及び上記第２の端子コンタクト部と、上記共通端子コンタクト部とを用いて、上記第１の回路パターンが電気的に接続する半導体素子及び上記第２の回路パターンが電気的に接続する半導体素子の動的検査を行う。 Further, the manufacturing inspection method for the power semiconductor module according to the present invention includes a leakage of a semiconductor element to which the first circuit pattern is electrically connected by using the first terminal contact portion and the common main terminal contact portion. A current inspection is performed, and a leakage current inspection of the semiconductor element to which the second circuit pattern is electrically connected is performed using the second terminal contact portion and the common main terminal contact portion. The terminal contact portion and the second terminal contact portion are electrically connected, and the first terminal contact portion, the second terminal contact portion, and the common terminal contact portion are used to connect the first terminal contact portion and the second terminal contact portion. A dynamic inspection is performed on the semiconductor element to which the first circuit pattern is electrically connected and the semiconductor element to which the second circuit pattern is electrically connected.
　そして、上記動的検査が終了した後、上記第１の端子コンタクト部と上記第２の端子コンタクト部とを上記電極主端子により互いに接続する。 Then, after the dynamic inspection is completed, the first terminal contact portion and the second terminal contact portion are connected to each other by the electrode main terminal.
　素子集積密度の確保、インダクタンスの低減、煩雑な作業を伴うことのない動的特性検査が可能なパワー半導体モジュール及びその製造検査方法を実現することができる。 It is possible to realize a power semiconductor module capable of ensuring element integration density, reducing inductance, and performing dynamic characteristic inspection without complicated work, and a manufacturing inspection method thereof.
本発明の第１の実施例を示す図である。It is a figure which shows the 1st Example of this invention. 本発明の第１の実施例における基板選別検査時の回路図である。It is a circuit diagram at the time of the board | substrate selection test | inspection in the 1st Example of this invention. 本発明の第１の実施例による基板検査のフローチャートである。It is a flowchart of the board | substrate inspection by 1st Example of this invention. 図１８に示した例における基板検査のフローチャートである。It is a flowchart of the board | substrate test | inspection in the example shown in FIG. 電極主端子と絶縁基板との接続部の拡大図である。It is an enlarged view of the connection part of an electrode main terminal and an insulated substrate. 本発明の第２の実施例における絶縁基板を示す図である。It is a figure which shows the insulated substrate in the 2nd Example of this invention. 本発明の第２の実施例における回路図である。It is a circuit diagram in the 2nd example of the present invention. 本発明を適用しない場合におけるセンス端子を分離した構造の絶縁基板の構成を示す図である。It is a figure which shows the structure of the insulated substrate of the structure where the sense terminal was isolate | separated when not applying this invention. 本発明の第３の実施例における絶縁基板を示す図である。It is a figure which shows the insulated substrate in the 3rd Example of this invention. 第３の実施例における基板検査のフローチャートである。It is a flowchart of the board | substrate inspection in a 3rd Example. 本発明の第４の実施例を示す図である。It is a figure which shows the 4th Example of this invention. 基板選別検査治具の説明図である。It is explanatory drawing of a board | substrate selection inspection jig. 本発明の第５の実施例における絶縁基板の構成を示す図である。It is a figure which shows the structure of the insulated substrate in the 5th Example of this invention. 本発明の第６の実施例を示す図である。It is a figure which shows the 6th Example of this invention. 本発明の第７の実施例を示す図である。It is a figure which shows the 7th Example of this invention. パワーモジュールの外観図である。It is an external view of a power module. 一般的なパワーモジュールの回路構成例を示す図である。It is a figure which shows the circuit structural example of a general power module. 絶縁基板の拡大図である。It is an enlarged view of an insulating substrate. リーク電流プロファイルを示すグラフである。It is a graph which shows a leakage current profile.
　以下、本発明の実施形態について、添付図面を参照して説明する。 Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
　（第１の実施例）
　図１は、本発明の第１の実施例を示す図であり、耐圧３．３ｋＶ製品の、スイッチング素子群としてのＳｉ－ＩＧＢＴと、ダイオード素子群としてのＳｉＣ－ＳＢＤが電気的に分離された例の一つで、エミッタ端子側の回路パターンを分離した絶縁基板を示す。 (First embodiment)
FIG. 1 is a diagram showing a first embodiment of the present invention, in which a Si-IGBT as a switching element group and a SiC-SBD as a diode element group of a 3.3 kV withstand voltage product are electrically separated. In one example, an insulating substrate with a separated circuit pattern on the emitter terminal side is shown.
　ここで、まず、本発明が適用されていない例を本発明との比較例として説明する。 Here, first, an example to which the present invention is not applied will be described as a comparative example with the present invention.
　図１６は、パワーモジュールの外観図であり（本発明にも適用される）、図１７は一般的なパワーモジュールの回路構成例を示す図である（Ｇ：ゲート、Ｅ：エミッタ、Ｃ：コレクタ）。図１６において、ケース２５内には複数枚の絶縁基板２２が格納される。図１８は、絶縁基板２２の拡大図である。 FIG. 16 is an external view of a power module (which is also applied to the present invention), and FIG. 17 is a diagram showing a circuit configuration example of a general power module (G: gate, E: emitter, C: collector) ). In FIG. 16, a plurality of insulating substrates 22 are stored in the case 25. FIG. 18 is an enlarged view of the insulating substrate 22.
　図１８において、各絶縁基板２２内にスイッチング素子２３（ＩＧＢＴ、ＭＯＳ等）と、還流ダイオード２４とが複数チップ実装されている。チップ間をつなぐワイヤボンディング１３は簡単のため図の左半分のみ記載した（以降の絶縁基板図でも同様とする）。各絶縁基板２２は図１６に示す電極主端子２１により外部との電気的コンタクトをとる。なお、図１６は一つのパワーモジュールに一組のＩＧＢＴとダイオードを組み合わせた１ｉｎ１構成を例として示している。 In FIG. 18, a plurality of switching elements 23 (IGBT, MOS, etc.) and freewheeling diodes 24 are mounted in each insulating substrate 22. For the sake of simplicity, only the left half of the figure shows the wire bonding 13 that connects the chips (the same applies to the following insulating substrate drawings). Each insulating substrate 22 is in electrical contact with the outside through an electrode main terminal 21 shown in FIG. FIG. 16 shows an example of a 1 in 1 configuration in which a single power module is combined with a set of IGBTs and diodes.
　本発明が適用されていない絶縁基板２２は、図１８に示されるように、共通のエミッタ回路パターン２７によって、Ｓｉ－ＩＧＢＴのエミッタと、ＳｉＣ－ＳＢＤのアノードとが電気的に結合されおり、ここから共通のエミッタ主端子コンタクト部２８を経由してモジュールの外部へ電流が流れている。 In the insulating substrate 22 to which the present invention is not applied, the emitter of the Si-IGBT and the anode of the SiC-SBD are electrically coupled by a common emitter circuit pattern 27 as shown in FIG. Through the common emitter main terminal contact 28 to the outside of the module.
　図１は、本発明の第１の実施例における絶縁基板６０を示す図であり、本発明の第１の実施例においては、エミッタ回路パターンが、Ｓｉ－ＩＧＢＴ側の２９と、ＳｉＣ－ＳＢＤ側の３０とに分離されており、対応して主端子コンタクト部も３１と３２とに分割することを特徴としている。 FIG. 1 is a diagram showing an insulating substrate 60 in the first embodiment of the present invention. In the first embodiment of the present invention, the emitter circuit patterns are 29 on the Si-IGBT side and on the SiC-SBD side. The main terminal contact part is also divided into 31 and 32 correspondingly.
　つまり、図１の例においては、一つの絶縁基板６０の周囲領域に複数のＳｉ－ＩＧＢＴ１１が形成された第１の回路パターンと、複数のＳｉＣ－ＳＢＤ１２とが形成された第２の回路パターンと、基板６０の中央領域に互いに分離したＳｉ－ＩＧＢＴ側の２９とＳｉＣ－ＳＢＤ側の３０とが形成され、かつ、Ｓｉ－ＩＧＢＴ側エミッタ主端子コンタクト３１（第１の端子コンタクト部）と、ＳｉＣ－ＳＢＤ側エミッタ主端子コンタクト３２（第２の端子コンタクト部）とが接近して配置されている。これにより、素子集積密度を確保した上で、Ｓｉ－ＩＧＢＴとＳｉＣ－ＳＢＤとを互いに分離した状態で、リーク電流検査を行うことができる。また、互いに接近したＳｉ－ＩＧＢＴ側エミッタ主端子コンタクト３１とＳｉＣ－ＳＢＤ側エミッタ主端子コンタクト３２とを接続して、動的特性検査をモジュール組立前に実施することができる。また、Ｓｉ－ＩＧＢＴ側エミッタ主端子コンタクト３１とＳｉＣ－ＳＢＤ側エミッタ主端子コンタクト３２とが接近して形成されているので、電流経路が作る閉ループを小さくすることができ、寄生インダクタンスを低減することができる。 That is, in the example of FIG. 1, a first circuit pattern in which a plurality of Si-IGBTs 11 are formed in a peripheral region of one insulating substrate 60, and a second circuit pattern in which a plurality of SiC-SBDs 12 are formed In the central region of the substrate 60, the Si-IGBT side 29 and the SiC-SBD side 30 separated from each other are formed, and the Si-IGBT side emitter main terminal contact 31 (first terminal contact portion) and SiC The SBD-side emitter main terminal contact 32 (second terminal contact portion) is disposed close to it. Accordingly, the leakage current inspection can be performed in a state where the Si-IGBT and the SiC-SBD are separated from each other while securing the element integration density. Further, the Si-IGBT side emitter main terminal contact 31 and the SiC-SBD side emitter main terminal contact 32 which are close to each other can be connected, and the dynamic characteristic inspection can be performed before the module assembly. Further, since the Si-IGBT side emitter main terminal contact 31 and the SiC-SBD side emitter main terminal contact 32 are formed close to each other, the closed loop formed by the current path can be reduced, and the parasitic inductance can be reduced. Can do.
　次に、基板選抜検査について説明する。 Next, the board selection inspection will be described.
　図２は、本発明の第１の実施例における基板選別検査時の回路図である。図２において、Ｓｉ－ＩＧＢＴのエミッタ側と、ＳｉＣ－ＳＢＤアノード側との結合が分離されている。Ｓｉ－ＩＧＢＴの試験ではゲート（Ｇ）とエミッタ（Ｅ）間をショートしてＥ＿ＳＷ端子３１を接地し、コレクタ端子（Ｃ）４３（共通主端子コンタクト部）に高電圧（３．６ｋＶまでの高電圧）を印加することになる。 FIG. 2 is a circuit diagram at the time of substrate sorting inspection in the first embodiment of the present invention. In FIG. 2, the coupling between the emitter side of the Si-IGBT and the SiC-SBD anode side is separated. In the Si-IGBT test, the gate (G) and the emitter (E) are short-circuited, the E_SW terminal 31 is grounded, and the collector terminal (C) 43 (common main terminal contact portion) has a high voltage (up to 3.6 kV). Voltage) is applied.
　ＳｉＣ－ＳＢＤの試験では、Ｅ＿ＦＷＤ端子３２を接地してコレクタ端子４３に同様の高電圧を印加する。 In the SiC-SBD test, the E_FWD terminal 32 is grounded and a similar high voltage is applied to the collector terminal 43.
　何れの試験においても実装されたＳｉ－ＩＧＢＴないしはＳｉＣ－ＳＢＤの同一種類の素子群は並列に接続されており同時に検査される。正常なリーク電流プロファイルは、図１９に示したが、例えばＳｉ－ＩＧＢＴのリーク不良では、ある電圧範囲からリーク電流が急増する場合がある。図１８に示した例では、並列に接続されているＳｉＣ－ＳＢＤのリーク電流に隠れて異常を検出できず誤って良品判定される問題点があったが、本発明の第１の実施例では両者を独立に測定できるため不良を見逃さない。 In any test, the same kind of element group of Si-IGBT or SiC-SBD mounted is connected in parallel and inspected at the same time. A normal leakage current profile is shown in FIG. 19. For example, in the case of Si-IGBT leakage failure, the leakage current may increase rapidly from a certain voltage range. In the example shown in FIG. 18, there is a problem that an abnormality cannot be detected behind the leakage current of SiC-SBDs connected in parallel, and a non-defective product is erroneously detected. However, in the first embodiment of the present invention, Since both can be measured independently, no defects are missed.
　図３は、本発明の第１の実施例による基板検査のフローチャートである。図３において、まず、高電圧印加前にオープン・ショートチェックを行い（ステップＳ１）、続いてＳｉ－ＩＧＢＴ、ＳｉＣ－ＳＢＤの順で独立に、高電圧を印加するリーク電流検査を行う（ステップＳ２、Ｓ３）。次に、基板単位での動的な特性検査として、ＲＢＳＯＡ（Reverse Bias Safe Operating Area）試験とリカバリＳＯＡ試験を行う（ステップＳ４）。 FIG. 3 is a flowchart of the substrate inspection according to the first embodiment of the present invention. In FIG. 3, first, an open / short check is performed before application of a high voltage (step S1), and then a leakage current inspection for applying a high voltage is performed independently in the order of Si-IGBT and SiC-SBD (step S2). , S3). Next, an RBSOA (Reverse Bias Safe Operating Area) test and a recovery SOA test are performed as a dynamic characteristic inspection for each substrate (step S4).
　これらの試験はスイッチング素子群とダイオード素子群とが電気的に接続されている必要があるため、図２に示した回路図で示すエミッタ側のＥ＿ＳＷ端子の３１とＥ＿ＦＷＤ端子３２を測定冶具のピンでショートさせた状態で行う。本発明の方法では、測定時に近接したＥ＿ＳＷ端子３１とＥ＿ＦＷＤ端子３２とを結合できるため、各素子群独立の耐圧検査と、両者を組み合わせた動的特性検査の両方を実施できる長所がある。 In these tests, since the switching element group and the diode element group need to be electrically connected, the E_SW terminal 31 and the E_FWD terminal 32 on the emitter side shown in the circuit diagram of FIG. Perform in a shorted state. In the method of the present invention, since the E_SW terminal 31 and the E_FWD terminal 32 that are close to each other can be coupled at the time of measurement, there is an advantage that both a breakdown voltage test independent of each element group and a dynamic characteristic test combining both can be performed.
　比較のため、図１８に示した例における基板検査のフローチャートを図４に示す。本発明の第１の実施例との差異は、本発明においては、耐圧検査を素子群ごとに独立して行うが、図１８に示した例においては、Ｓｉ－ＩＧＢＴとＳｉＣ－ＳＢＤとが同時に実行される（ステップＳ０）。本発明においては、１ステップ増加するのみで、他は現在実績のある検査方法を導入することができる。このため、本発明は、現存の生産ラインへの親和性も良く、確立した信頼性試験方法を踏襲することができる。 For comparison, FIG. 4 shows a flowchart of substrate inspection in the example shown in FIG. The difference from the first embodiment of the present invention is that, in the present invention, the withstand voltage test is performed independently for each element group, but in the example shown in FIG. 18, Si-IGBT and SiC-SBD are simultaneously used. It is executed (step S0). In the present invention, it is possible to introduce an inspection method with a current track record with only one step increase. For this reason, the present invention has good compatibility with existing production lines and can follow established reliability test methods.
　基板検査後のモジュール組み立て工程では、絶縁基板６０をベースに接合した後、モジュールケース２５（図１６に示す）と、電極主端子２１および補助端子を組み付ける。この工程で、主端子２１によってＥ＿ＳＷ端子３１とＥ＿ＦＷＤ端子３２とが電気的に接続される。図５は、このときの主端子２１と絶縁基板６０との接続部の拡大図である。電極主端子２１は、コンタクト部であるＥ＿ＳＷ端子３１とＥ＿ＦＷＤ端子３２とに向かって枝分かれした端子が基板６０の直上で結合する形状となっており、寄生インダクタンス増加を最小限に抑制している。 In the module assembling step after the substrate inspection, after the insulating substrate 60 is joined to the base, the module case 25 (shown in FIG. 16), the electrode main terminal 21 and the auxiliary terminal are assembled. In this step, the E_SW terminal 31 and the E_FWD terminal 32 are electrically connected by the main terminal 21. FIG. 5 is an enlarged view of a connection portion between the main terminal 21 and the insulating substrate 60 at this time. The electrode main terminal 21 has a shape in which terminals branched toward the E_SW terminal 31 and the E_FWD terminal 32, which are contact portions, are coupled immediately above the substrate 60, thereby suppressing an increase in parasitic inductance to a minimum.
　そして、カバー２６がケース２５に設置され、半導体モジュールとして組み立てられる。 Then, the cover 26 is installed in the case 25 and assembled as a semiconductor module.
　なお、絶縁基板６０は、アルミナイトライド、シリコンナイトライド、アルミナ等のセラミックで熱伝導率が高い材質を使用し、絶縁基板６０上の素子が発する熱を効率よく放熱することができる構成となっている。 The insulating substrate 60 is made of a material having high thermal conductivity such as aluminum nitride, silicon nitride, alumina, or the like, so that the heat generated by the elements on the insulating substrate 60 can be efficiently radiated. ing.
　以上のように、本発明の第１実施例によれば、一つの絶縁基板６０上に複数のＳｉ－ＩＧＢＴ１１と、複数のＳｉＣ－ＳＢＤ１２とが形成され、基板６０の中央領域に互いに分離したＳｉ－ＩＧＢＴ側回路パターン２９とＳｉＣ－ＳＢＤ側回路パターン３０とが形成され、かつ、Ｓｉ－ＩＧＢＴ側エミッタ主端子コンタクト３１と、ＳｉＣ－ＳＢＤ側エミッタ主端子コンタクト３２とが接近して配置されている。ＳｉＣ－ＳＢＤ１２とＳｉ－ＩＧＢＴ１１とを分離して、それぞれのリーク電流検査を行い、接続ピン等でＳｉＣ－ＳＢＤ１２とＳｉ－ＩＧＢＴ１１とを接続して動的検査を行う。そして、互いに分離したＳｉＣ－ＳＢＤ１２のアノードとＳｉ－ＩＧＢＴ１１のエミッタとは、パワーモジュール組立時に、電極主端子２１により接続され、ＳｉＣ－ＳＢＤ１２のアノードとＳｉ－ＩＧＢＴ１１のエミッタとの接続作業は煩雑な動作を伴うことはない。 As described above, according to the first embodiment of the present invention, a plurality of Si-IGBTs 11 and a plurality of SiC-SBDs 12 are formed on one insulating substrate 60 and separated from each other in the central region of the substrate 60. -IGBT side circuit pattern 29 and SiC-SBD side circuit pattern 30 are formed, and Si-IGBT side emitter main terminal contact 31 and SiC-SBD side emitter main terminal contact 32 are arranged close to each other. . The SiC-SBD 12 and the Si-IGBT 11 are separated from each other to perform a leakage current inspection, and the SiC-SBD 12 and the Si-IGBT 11 are connected by a connection pin or the like to perform a dynamic inspection. The anode of the SiC-SBD 12 and the emitter of the Si-IGBT 11 separated from each other are connected by the electrode main terminal 21 when the power module is assembled, and the connection work between the anode of the SiC-SBD 12 and the emitter of the Si-IGBT 11 is complicated There is no action involved.
　よって、本発明の第１の実施例によれば、素子集積密度を確保、インダクタンスの低減、煩雑な作業を伴うことのない動的特性検査が可能なパワー半導体モジュール及びその製造検査方法を実現することができる。 Therefore, according to the first embodiment of the present invention, a power semiconductor module capable of ensuring element integration density, reducing inductance, and performing dynamic characteristic inspection without complicated operations, and a manufacturing inspection method thereof are realized. be able to.
　(第２の実施例)
　本発明の第２の実施例は、Ｓｉ－ＩＧＢＴのコレクタ端子とＳｉＣ－ＳＢＤのカソード端子とを分離した例である。図６は本発明の第２の実施例における絶縁基板６０を示す図である。図７は、本発明の第２の実施例における回路図である。第１の実施例ではエミッタとアノードとを分離したのに対して第２の実施例ではコレクタとカソードとを分離している。 (Second embodiment)
The second embodiment of the present invention is an example in which the collector terminal of the Si-IGBT and the cathode terminal of the SiC-SBD are separated. FIG. 6 shows an insulating substrate 60 in the second embodiment of the present invention. FIG. 7 is a circuit diagram in the second embodiment of the present invention. In the first embodiment, the emitter and the anode are separated, whereas in the second embodiment, the collector and the cathode are separated.
　本発明の第２の実施例の構成では、ダイオードからのワイヤボンディング長や配線パターンの複雑性が増すが、通常は接地されているエミッタ側ではなく、高電圧のかかるコレクタ側を分離することで非測定素子へのストレスを軽減できるメリットがある。 In the configuration of the second embodiment of the present invention, the wire bonding length from the diode and the complexity of the wiring pattern are increased, but the collector side where high voltage is applied is separated from the normally grounded emitter side. There is an advantage that stress on non-measuring elements can be reduced.
　図６に示すように、絶縁基板６０における各要素の配置は。第１の実施例と同様の部分があるが、コレクタ側の回路パターンを、Ｓｉ－ＩＧＢＴ側の回路パターン３３と、ＳｉＣ－ＳＢＤ側の回路パターン３４との２つに分離している点が第１の実施例と異なっている。 As shown in FIG. 6, the arrangement of each element on the insulating substrate 60 is as follows. There is a part similar to the first embodiment, but the collector side circuit pattern is separated into two, a circuit pattern 33 on the Si-IGBT side and a circuit pattern 34 on the SiC-SBD side. This is different from the first embodiment.
　コレクタ側の回路パターンが分断される領域が長いが、電流は各々のコレクタ端子（３５または３６）から素子裏面と表面を通ってワイヤボンディングを流れていき、その経路上は分断されないため影響は無視でき、インダクタンス分が増加することはない。 Although the area where the circuit pattern on the collector side is divided is long, the current flows through the wire bonding from each collector terminal (35 or 36) through the back surface and the surface of the element, and the influence is ignored because it is not divided on the path. Inductance is not increased.
　なお、基板検査のフローと主端子の構造は、第１の実施例と第２の実施例とは全く同じとなるため、詳細な説明は省略する。 Note that the substrate inspection flow and the main terminal structure are exactly the same as those in the first and second embodiments, and a detailed description thereof will be omitted.
　本発明の第２の実施例も、第１の実施例と同様な効果を得ることができる。 The second embodiment of the present invention can also obtain the same effect as the first embodiment.
　(第３の実施例)
　本発明の第３の実施例として、センス端子を分離した構造の絶縁基板を用いる例を説明する。 (Third embodiment)
As a third embodiment of the present invention, an example using an insulating substrate having a structure in which sense terminals are separated will be described.
　図８は、本発明を適用しない場合におけるセンス端子を分離した構造の絶縁基板の構成を示す図である。 FIG. 8 is a diagram showing a configuration of an insulating substrate having a structure in which sense terminals are separated when the present invention is not applied.
　図８において、エミッタセンス端子の取り出し用回路パターン３７とゲート端子の取り出し用回路パターン３８を主端子と反対側に設けている。また、主端子のコンタクト部３９は、複数存在し、互いに対向して並べられる隣接基板の主端子コンタクト部３９と接近して配置され、主端子の寄生インダクタンスを可能な限り低減できる構造が特徴となっている。 In FIG. 8, an emitter sense terminal extraction circuit pattern 37 and a gate terminal extraction circuit pattern 38 are provided on the opposite side of the main terminal. Further, there are a plurality of main terminal contact portions 39, which are arranged close to the main terminal contact portions 39 of adjacent substrates arranged opposite to each other, and are characterized in that the parasitic inductance of the main terminals can be reduced as much as possible. It has become.
　このため、高速スイッチング時の寄生インダクタンスでリンギングが発生しやすいＳｉＣ－ＳＢＤに適している。 For this reason, it is suitable for SiC-SBD, where ringing is likely to occur due to parasitic inductance during high-speed switching.
　このセンス端子を分離した構造の絶縁基板形状に対して本発明を適用した例が本発明の第３の実施例である。図９は、本発明の第３の実施例における絶縁基板６０を示す図であり、エミッタ端子側の回路パターンを分離した構成の例である。 An example in which the present invention is applied to an insulating substrate shape having a structure in which the sense terminals are separated is a third embodiment of the present invention. FIG. 9 is a diagram showing an insulating substrate 60 in the third embodiment of the present invention, which is an example of a configuration in which a circuit pattern on the emitter terminal side is separated.
　センス端子を分離した構造のタイプの絶縁基板は、Ｓｉ－ＩＧＢＴのエミッタ電極からのワイヤボンディングは全てＳｉＣ－ＳＢＤを経由して、スティッチとして結線していたため、本発明の第３の実施例では、Ｓｉ－ＩＧＢＴとＳｉＣ－ＳＢＤとの間のエミッタ側ワイヤ配線を分離して、中継用のアイランド回路パターン４０を設けた形としている。 In the insulating substrate of the type having a separated sense terminal, all wire bonding from the emitter electrode of the Si-IGBT is connected as a stitch via the SiC-SBD. Therefore, in the third embodiment of the present invention, The emitter-side wire wiring between the Si-IGBT and the SiC-SBD is separated and a relay island circuit pattern 40 is provided.
　Ｓｉ－ＩＧＢＴ１１からアイランド回路パターン４０へ伸びるワイヤボンディング４１は、基板選別検査の段階では結線しない。ワイヤボンディング４１で結線していない場合は、回路的には図２の状態となり、Ｓｉ－ＩＧＢＴとＳｉＣ－ＳＢＤのリーク電流を独立に評価できる。 The wire bonding 41 extending from the Si-IGBT 11 to the island circuit pattern 40 is not connected at the stage of substrate selection inspection. When the wire bonding 41 is not used, the circuit is in the state shown in FIG. 2, and the leakage currents of Si-IGBT and SiC-SBD can be independently evaluated.
　Ｓｉ－ＩＧＢＴのリーク電流評価には、コレクタ端子のコンタクト部４３と、エミッタのセンス端子回路パターン３７と、エミッタとショートするゲート端子回路パターン３８にコンタクトする冶具を用いれば良い。ＳｉＣ－ＳＢＤのリーク電流評価には、コレクタ端子のコンタクト部４３とエミッタ端子のコンタクト部２８から電気的接続を取れば良い。リーク電流検査の後に、中継用アイランド部４０へのワイヤボンディングを実施し、Ｓｉ－ＩＧＢＴとＳｉＣ－ＳＢＤとを接続して、ＲＢＳＯＡ（Reverse Bias Safe Operating Area）等の動的特性検査を行う。 For evaluating the leakage current of the Si-IGBT, a jig that contacts the contact portion 43 of the collector terminal, the sense terminal circuit pattern 37 of the emitter, and the gate terminal circuit pattern 38 short-circuited with the emitter may be used. In order to evaluate the leakage current of the SiC-SBD, an electrical connection may be made from the contact portion 43 of the collector terminal and the contact portion 28 of the emitter terminal. After the leakage current inspection, wire bonding to the relay island 40 is performed, the Si-IGBT and the SiC-SBD are connected, and dynamic characteristic inspection such as RBSOA (Reverse Bias Safe Operating Area) is performed.
　図１０は、第３の実施例における基板検査のフローチャートである。ステップＳ１、Ｓ２、Ｓ３、Ｓ４は、図３に示した例と同様であるが、第３の実施例においては、ステップＳ３とＳ４との間に、Ｓｉ－ＩＧＢＴ１１と中継用のアイランドパターン４０とをワイヤボンディング４１により結線する（ステップＳ４４）。 FIG. 10 is a flowchart of substrate inspection in the third embodiment. Steps S1, S2, S3, and S4 are the same as the example shown in FIG. 3, but in the third embodiment, the Si-IGBT 11 and the relay island pattern 40 are between the steps S3 and S4. Are connected by wire bonding 41 (step S44).
　本発明の第３の実施例では、基板検査の工程がリーク電流測定後のワイヤボンディング工程Ｓ４４を挟むため、二分割されて工程数が増加する短所がある。その反面、主端子とのコンタクト部２８や４３と、センス端子部の３７や３８など周囲とのインターフェースとなる部分の構成は、現存方式と同一のため、主端子構造や基板選別検査の測定冶具への設計変更が不要で、導入コストが抑制でき、部品や工程を共通化できるメリットが大きい特徴がある。 In the third embodiment of the present invention, since the substrate inspection process sandwiches the wire bonding process S44 after the leakage current measurement, there is a disadvantage that the number of processes is increased by being divided into two. On the other hand, since the configuration of the interface portion between the contact portions 28 and 43 with the main terminal and the surroundings such as the sense terminal portions 37 and 38 is the same as the existing method, the measurement tool for the main terminal structure and the substrate selection inspection is used. There is a feature that there is no need to change the design of the system, the introduction cost can be suppressed, and the advantage that parts and processes can be shared is great.
　その他は、本発明の第１の実施例と同様な効果を得ることができる。 Otherwise, the same effects as those of the first embodiment of the present invention can be obtained.
　(第４の実施例)
　本発明の第４の実施例として、第３の実施例と同じセンス端子を分離した構造の絶縁基板６０において、コレクタ端子側の回路パターンを分離した構成を説明する。 (Fourth embodiment)
As a fourth embodiment of the present invention, a configuration in which a circuit pattern on the collector terminal side is separated in an insulating substrate 60 having the same structure as that of the third embodiment in which the sense terminals are separated will be described.
　図１１は、本発明の第４の実施例を示す図である。図１１において、Ｓｉ－ＩＧＢＴ側のコレクタ端子回路パターン３３とＳｉＣ－ＳＢＤ側のコレクタ端子（カソード側端子）の回路パターン３４とを分離し、各々の主端子コンタクト部３５と３６を設けている。 FIG. 11 is a diagram showing a fourth embodiment of the present invention. In FIG. 11, the collector terminal circuit pattern 33 on the Si-IGBT side and the circuit pattern 34 on the collector terminal (cathode side terminal) on the SiC-SBD side are separated, and main terminal contact portions 35 and 36 are provided.
　基板選別検査工程では、エミッタ端子コンタクト部２８は共通で、コレクタ端子コンタクト部側をＳｉ－ＩＧＢＴ３５とＳｉＣ－ＳＢＤ３６とで使い分けることで両者のリーク電流検査を独立に行うことができる。基板検査のフローは第１の実施例と同様に、図３に示したフローとなる。 In the substrate screening inspection process, the emitter terminal contact portion 28 is common, and the collector terminal contact portion side can be used separately for the Si-IGBT 35 and the SiC-SBD 36, whereby the leakage current inspection of both can be performed independently. The substrate inspection flow is the flow shown in FIG. 3 as in the first embodiment.
　ここで、第４の実施例における基板選別検査治具について説明する。図１２は、基板選別検査治具６１の説明図である。基板選別検査治具６１は、主端子ピン５１と、ゲートピン５２と、センスピン５３と、電流検出端子５５と、主端子ピン５１、ゲートピン５２、及びセンスピン５３を電流検出端子５５に接続するケーブル５４とを備えている。 Here, the substrate sorting inspection jig in the fourth embodiment will be described. FIG. 12 is an explanatory diagram of the substrate sorting inspection jig 61. The substrate sorting inspection jig 61 includes a main terminal pin 51, a gate pin 52, a sense pin 53, a current detection terminal 55, and a cable 54 that connects the main terminal pin 51, the gate pin 52, and the sense pin 53 to the current detection terminal 55. It has.
　そして、主端子ピン５１は、絶縁基板６０の主端子コンタクト部３５、３６及びエミッタ端子コンタクト部２８に接続される。また、センスピン５３は絶縁基板６０のセンス端子回路パターン３７に接続され、ゲートピン５２は、絶縁基板６０のゲート回路パターン３８に接続される。 The main terminal pin 51 is connected to the main terminal contact portions 35 and 36 and the emitter terminal contact portion 28 of the insulating substrate 60. The sense pin 53 is connected to the sense terminal circuit pattern 37 on the insulating substrate 60, and the gate pin 52 is connected to the gate circuit pattern 38 on the insulating substrate 60.
　本発明の第３の実施例では、高電圧の印加されるコレクタ側を分離しているために、非測定素子へのストレスが低減できる長所がある。 In the third embodiment of the present invention, since the collector side to which a high voltage is applied is separated, there is an advantage that stress on the non-measuring element can be reduced.
　その他は、本発明の第１の実施例と同様な効果を得ることができる。 Otherwise, the same effects as those of the first embodiment of the present invention can be obtained.
　（第５の実施例）
　本発明の第５の実施例は、第３の実施例の変形例である。図１３は、本発明の第５の実施例における絶縁基板６０の構成を示す図である。第５の実施例では、エミッタ側の接続を分離した構造をとる。Ｓｉ－ＩＧＢＴ１１からエミッタ端子回路パターン２７へ伸びるワイヤ４５は、基板選別検査の段階では結線しない。このとき、回路的には図２に示した状態となる。 (Fifth embodiment)
The fifth embodiment of the present invention is a modification of the third embodiment. FIG. 13 is a diagram showing the configuration of the insulating substrate 60 in the fifth embodiment of the present invention. In the fifth embodiment, the emitter side connection is separated. The wire 45 extending from the Si-IGBT 11 to the emitter terminal circuit pattern 27 is not connected at the stage of substrate selection inspection. At this time, the circuit is in the state shown in FIG.
　第３の実施例と同様に、Ｓｉ－ＩＧＢＴ１１とエミッタ端子回路パターン２７とを接続するワイヤ４５が接続されていない状態で、Ｓｉ－ＩＧＢＴとＳｉＣ－ＳＢＤ双方のリーク電流検査を独立に行って、ワイヤ４５をワイヤボンディング工程で結線した後にＲＢＳＯＡ等の動特性検査を行う。 As in the third embodiment, the leakage current inspection of both the Si-IGBT and the SiC-SBD is independently performed in a state where the wire 45 that connects the Si-IGBT 11 and the emitter terminal circuit pattern 27 is not connected. After the wire 45 is connected in the wire bonding process, a dynamic characteristic inspection such as RBSOA is performed.
　基板検査のフローも第３の実施例と同様であり、図１０に示したフローとなる。第５の実施例の構成では、エミッタ端子回路パターン２７を基板中央付近に配置して、Ｓｉ－ＩＧＢＴ１１とＳｉＣ－ＳＢＤ１２の双方に隣接させることでレイアウト効率が向上する。その効果として、ＳｉＣ－ＳＢＤ１２の搭載チップ数を第３の実施例の１０チップから、第５の実施例では１２チップに増加させることができる。 The substrate inspection flow is the same as that of the third embodiment, which is the flow shown in FIG. In the configuration of the fifth embodiment, the layout efficiency is improved by arranging the emitter terminal circuit pattern 27 near the center of the substrate and adjoining both the Si-IGBT 11 and the SiC-SBD 12. As an effect, the number of mounted chips of SiC-SBD 12 can be increased from 10 chips in the third embodiment to 12 chips in the fifth embodiment.
　その他は、本発明の第１の実施例と同様な効果を得ることができる。 Otherwise, the same effects as those of the first embodiment of the present invention can be obtained.
　（第６の実施例）
　本発明の第６の実施例は、第５の実施例の変形例である。図１４は、本発明の第６の実施形態を示す図であり、エミッタ端子配線部のパターンを分割した構成の例を示す。 (Sixth embodiment)
The sixth embodiment of the present invention is a modification of the fifth embodiment. FIG. 14 is a diagram showing a sixth embodiment of the present invention, and shows an example of a configuration in which the pattern of the emitter terminal wiring portion is divided.
　第５の実施例と異なり、全てのワイヤボンディングは予め結線して基板選別検査工程に進む。このため、基板選別検査工程のフロー増加が無いことが長所となる。Ｓｉ－ＩＧＢＴ１１のリーク電流検査はエミッタ側回路パターン２９のコンタクト部３１とコレクタ端子コンタクト部３５を用いて行い、ＳｉＣ－ＳＢＤ１２のリーク電流検査はもう一つのエミッタ側回路パターン３０のコンタクト部３２とコレクタ端子コンタクト部３５を用いて行う。最終的なエミッタ側の結線は、主端子２１の取り付け工程と同時にコンタクト部の３１と３２が主端子２１で接続されることで行われる。 Unlike the fifth embodiment, all wire bondings are connected in advance and proceed to the substrate sorting inspection process. For this reason, it is an advantage that there is no increase in the flow of the substrate sorting inspection process. The leakage current inspection of the Si-IGBT 11 is performed by using the contact portion 31 and the collector terminal contact portion 35 of the emitter side circuit pattern 29, and the leakage current inspection of the SiC-SBD 12 is performed by the contact portion 32 and the collector of the other emitter side circuit pattern 30. This is performed using the terminal contact portion 35. The final connection on the emitter side is performed by connecting the contact portions 31 and 32 with the main terminal 21 simultaneously with the attaching process of the main terminal 21.
　(第７の実施例)
　本発明の第７の実施例は、第５の実施例のさらなる変形例である。図１５は、本発明の第７の実施形態を示す図であり、コレクタ側の回路パターンを分離する例である。絶縁基板の構成は、図１５に示すように、Ｓｉ－ＩＧＢＴ１１側のコレクタ端子回路パターン３３とＳｉＣ－ＳＢＤ１２側のコレクタ端子（カソード側端子）の回路パターン３４を分離し、各々の主端子コンタクト部３５と３６を設けている。 (Seventh embodiment)
The seventh embodiment of the present invention is a further modification of the fifth embodiment. FIG. 15 is a diagram showing a seventh embodiment of the present invention, which is an example of separating a circuit pattern on the collector side. As shown in FIG. 15, the configuration of the insulating substrate is such that the collector terminal circuit pattern 33 on the Si-IGBT 11 side and the circuit pattern 34 on the collector terminal (cathode side) on the SiC-SBD 12 side are separated, and each main terminal contact portion 35 and 36 are provided.
　基板選別検査工程では、エミッタ端子コンタクト部２８は共通で、コレクタ端子コンタクト部側をＳｉ－ＩＧＢＴ１１とＳｉＣ－ＳＢＤ１２で使い分けることで両者のリーク電流検査を独立に行うことができる。 In the substrate screening inspection process, the emitter terminal contact portion 28 is common, and the collector terminal contact portion side can be separately used for the Si-IGBT 11 and the SiC-SBD 12, whereby the leakage current inspection of both can be performed independently.
　基板検査のフローは第１の実施例と同様に図３に示したフローなる。第７の本実施例は、レイアウト効率が良くＳｉＣ－ＳＢＤを１２チップ搭載できる第５の実施例の長所を引き継ぎ、また基板検査のフロー増加が無い第６の実施例の長所も併せ持っている。さらに、高電圧の印加されるコレクタ側を分離しているために、非測定素子へのストレスが低減できる長所がある。 The substrate inspection flow is the flow shown in FIG. 3 as in the first embodiment. The seventh embodiment inherits the advantages of the fifth embodiment with good layout efficiency and the ability to mount 12 chips of SiC-SBD, and also has the advantages of the sixth embodiment in which there is no increase in the flow of substrate inspection. Further, since the collector side to which a high voltage is applied is separated, there is an advantage that stress on the non-measuring element can be reduced.
　なお、基板選別検査治具については、第４の実施例についてのみ説明したが、他の実施例についても、絶縁基板６０の形成パターンに適合した適切な基板選別検査治具が用いられる。 In addition, although only the 4th Example was demonstrated about the board | substrate selection inspection jig | tool, the board | substrate selection inspection jig | tool suitable for the formation pattern of the insulated substrate 60 is used also about another Example.
　以上、本発明の代表的な実施例を記載したが、本発明の本質は特性の異なる２種以上の素子群について、これらを実装した後の検査段階では電気的に分離された状態となる回路または配線の構造を設けることにある。その意味では上記Ｓｉ－ＩＧＢＴとＳｉＣ－ＳＢＤの組み合わせのみに限定されず、エネルギーバンドギャップが広い、ＳｉＣやＧａＮ、ダイヤモンド等のワイドバンドギャップ半導体と、シリコンや、ガリウムヒ素、ゲルマニウム等の一般的なバンドギャップを持つ半導体の組み合わせにも有効であり、リーク電流特性の異なる素子群として、ショットキーバリアダイオードやＰＮダイオードと、ＭＯＳやＪＦＥＴ、バイポーラトランジスタなどのスイッチング素子との組み合わせにおいて検査精度を向上することができる。 As mentioned above, although the typical Example of this invention was described, the essence of this invention is the circuit which will be in the state electrically isolated in the test | inspection stage after mounting these about 2 or more types of element groups from which a characteristic differs Alternatively, a wiring structure is provided. In that sense, it is not limited to the combination of Si-IGBT and SiC-SBD, but a wide band gap semiconductor such as SiC, GaN, and diamond, and a general band such as silicon, gallium arsenide, and germanium. It is also effective for combinations of semiconductors with band gaps, and improves the inspection accuracy in combinations of Schottky barrier diodes and PN diodes and switching elements such as MOS, JFET, and bipolar transistors as element groups with different leakage current characteristics. be able to.
　また、ワイドバンドギャップ半導体から成るスイッチング素子としては、ＧａＮのトランジスタ（ＨＥＭＴ）やダイヤモンドから成るトランジスタが挙げられる。 Also, examples of the switching element made of a wide band gap semiconductor include a GaN transistor (HEMT) and a transistor made of diamond.
　ダイオード素子とスイッチング素子の電気的回路が閉じられていない構造は、絶縁基板上の回路構成を、ダイオード素子群とスイッチング素子群でそれぞれ電気的に分離された回路パターンもしくは配線パターンで実現する。検査後のワイヤボンディングやリボンボンディング、リードフレーム等の配線接続工程か、モジュールの主端子を接続する工程と同時に、未結合部の電気的接続を取ることで工程増加が無い、もしくは最少の追加で電気的回路を完成できる。 The structure in which the electrical circuit of the diode element and the switching element is not closed realizes the circuit configuration on the insulating substrate by a circuit pattern or a wiring pattern electrically separated by the diode element group and the switching element group. At the same time as the wire connection process after inspection, ribbon bonding, lead frame, etc., or the process of connecting the main terminals of the module, there is no increase in the process by connecting the unbonded parts, or with minimal addition An electrical circuit can be completed.
　予め分離しておくパターンは、スイッチング素子とダイオード素子を逆並列に組み合わせた回路のコレクタ端子（ダイオードにとってはカソード側）か、エミッタ端子（ダイオードにとってはアノード側）の少なくともいずれか一方であれば十分である。 The pattern to be separated in advance is sufficient if it is at least one of the collector terminal (cathode side for the diode) and the emitter terminal (anode side for the diode) of the circuit in which the switching element and the diode element are combined in antiparallel. It is.
　本発明のパワー半導体モジュールは、ハイブリッドモジュールとして低損失、小型化を実現すると共に、リーク不良を高精度に検出し除外できるため高信頼性を実現できる。典型的には、Ｓｉ－ＩＧＢＴとＳｉＣ－ＳＢＤを組み合わせたＳｉＣハイブリッドモジュールにおいて、相対的に室温リーク電流レベルの低いＳｉ－ＩＧＢＴのリーク不良を高精度に検出し排除する。特にＳｉ－ＩＧＢＴの裏面欠陥起因のリーク電流不良を逃さず検出し、裏面欠陥部でリーク電流が経時劣化により増加して熱暴走するような使用中の不良発生を未然に防ぎ、より高い耐圧信頼性を実現できる。 The power semiconductor module of the present invention realizes low loss and miniaturization as a hybrid module, and can realize high reliability because leakage defects can be detected and eliminated with high accuracy. Typically, in a SiC hybrid module combining Si-IGBT and SiC-SBD, a leakage failure of Si-IGBT having a relatively low room temperature leakage current level is detected and eliminated with high accuracy. In particular, leakage current defects due to Si-IGBT back surface defects are detected without fail, and the occurrence of defects during use such as increased leakage current due to deterioration over time and thermal runaway at the back surface defects can be prevented and higher withstand voltage reliability Can be realized.
　リーク不良チップが実装された絶縁基板を予め排除することで、チップ実装済み絶縁基板を複数マウントした後のモジュール完成段階で不良となる割合を低減し、スクラップコストを抑制する効果も得られる。 By eliminating the insulating substrate on which the defective chip is mounted in advance, it is possible to reduce the rate of failure at the completion of the module after mounting a plurality of chip-mounted insulating substrates, and to reduce the scrap cost.
　本発明の製造検査方法では、絶縁基板上のパターンが分離された状態で検査を行い、後続の端子結線用ワイヤボンディングや主端子接合用のメタルボンディング工程と同時に、絶縁基板上で分離されていた部分の電気的な接続を完成させる。このため、工程の増加数がゼロ、または最小限度で済む。また、中間検査工程での特性測定精度を向上することで、プロセス異常の早期発見とメカニズム解明、製造プロセスへの早期フィードバックが可能になる。 In the manufacturing inspection method of the present invention, the inspection is performed in a state where the pattern on the insulating substrate is separated, and the pattern is separated on the insulating substrate simultaneously with the subsequent wire bonding for terminal connection and the metal bonding process for main terminal bonding. Complete the electrical connection of the parts. For this reason, the number of process increases is zero or minimal. In addition, by improving the property measurement accuracy in the intermediate inspection process, it becomes possible to detect process abnormalities early, elucidate the mechanism, and provide early feedback to the manufacturing process.
　１１・・・Ｓｉ－ＩＧＢＴ、　１２・・・ＳｉＣ－ＳＢＤ、　１３・・・ワイヤボンディング、２１・・・電極主端子、　２５・・・ケース、　２６・・・カバー、　２７・・・共通エミッタ回路パターン、　２８・・・共通エミッタ主端子コンタクト、　２９・・・Ｓｉ－ＩＧＢＴ側エミッタ回路パターン、　３０・・・ＳｉＣ－ＳＢＤ側エミッタ回路パターン、　３１・・・Ｓｉ－ＩＧＢＴ側エミッタ主端子コンタクト、　３２・・・ＳｉＣ－ＳＢＤ側エミッタ主端子コンタクト、　３３・・・Ｓｉ－ＩＧＢＴ側コレクタ回路パターン、　３４・・・ＳｉＣ－ＳＢＤ側コレクタ（カソード）回路パターン、　３５・・・Ｓｉ－ＩＧＢＴ側コレクタ主端子コンタクト、　３６・・・ＳｉＣ－ＳＢＤ側コレクタ（カソード）主端子コンタクト、３７・・・エミッタセンス端子の回路パターン、３８・・・ゲート端子の回路パターン、３９・・・主端子コンタクト、４０・・・中継用のアイランド回路パターン、４１・・・Ｓｉ－ＩＧＢＴからアイランド回路パターンへのワイヤ、　４２・・・共通コレクタ回路パターン、　４３・・・通コレクタ主端子コンタクト、４５・・・Ｓｉ－ＩＧＢＴからエミッタ回路パターンへのワイヤ、　６０・・・絶縁基板、　６１・・・基板選別検査治具 11 ... Si-IGBT, 12 ... SiC-SBD, 13 ... wire bonding, 21 ... electrode main terminal, 25 ... case, 26 ... cover, 27 ... common emitter circuit Pattern: 28 ... Common emitter main terminal contact, 29 ... Si-IGBT side emitter circuit pattern, 30 ... SiC-SBD side emitter circuit pattern, 31 ... Si-IGBT side emitter main terminal contact, 32 ... SiC-SBD side emitter main terminal contact, 33 ... Si-IGBT side collector circuit pattern, 34 ... SiC-SBD side collector (cathode) circuit pattern, 35 ... Si-IGBT side collector main terminal Contact, 36 ... SiC-SBD side collector (cathode) main terminal contact 37 ... emitter sense terminal circuit pattern, 38 ... gate terminal circuit pattern, 39 ... main terminal contact, 40 ... relay island circuit pattern, 41 ... Si-IGBT to island Wire to circuit pattern, 42 ... Common collector circuit pattern, 43 ... Collector main terminal contact, 45 ... Wire from Si-IGBT to emitter circuit pattern, 60 ... Insulating substrate, 61 ...・ Substrate sorting inspection jig

Claims (11)

  1. 　シリコンを基体として用いる半導体素子に電気的に接続する第１の回路パターンと、
    　シリコンよりエネルギーバンドギャップが広い半導体素子を基体として用いる半導体素子に電気的に接続する第２の回路パターンと、
    　少なくとも上記第１の回路パターンと上記第２の回路パターンとが共に形成された基板と、
    　上記第１の回路パターンに形成され、上記第１の回路パターンが電気的に接続する半導体素子の一方端に接続された第１の端子コンタクト部と、
    　上記第２の回路パターンに形成され、上記第２の回路パターンが電気的に接続する半導体素子の一方端に接続され、上記第１の端子コンタクト部に隣接して形成された第２の端子コンタクト部と、
    　上記第１の回路パターンが電気的に接続する半導体素子の他方端に接続されると共に、上記第２の回路パターンが電気的に接続する半導体素子の他方端に接続され、上記基板上に形成される共通主端子コンタクト部と、
    　上記第１の端子コンタクト部と上記第２の端子コンタクト部とを互いに電気的に接続する電極主端子と、
    　を備えることを特徴とするパワー半導体モジュール。     A first circuit pattern electrically connected to a semiconductor element using silicon as a substrate;
    A second circuit pattern electrically connected to a semiconductor element using a semiconductor element having a wider energy band gap than silicon as a substrate;
    A substrate on which at least the first circuit pattern and the second circuit pattern are formed;
    A first terminal contact portion formed in the first circuit pattern and connected to one end of a semiconductor element to which the first circuit pattern is electrically connected;
    A second terminal contact formed on the second circuit pattern, connected to one end of a semiconductor element to which the second circuit pattern is electrically connected, and formed adjacent to the first terminal contact portion. And
    The first circuit pattern is connected to the other end of the electrically connected semiconductor element, and the second circuit pattern is connected to the other end of the electrically connected semiconductor element and formed on the substrate. Common main terminal contact
    An electrode main terminal for electrically connecting the first terminal contact portion and the second terminal contact portion to each other;
    A power semiconductor module comprising:
  2. 　請求項１に記載のパワー半導体モジュールにおいて、
    　上記第１の回路が電気的に接続する半導体素子はトランジスタであり、上記第２の回路が電気的に接続する半導体素子はダイオードであり、上記第１の端子コンタクト部は上記トランジスタのエミッタに接続され、上記第２の端子コンタクト部は上記ダイオードのアノードに接続されていることを特徴とするパワー半導体モジュール。     The power semiconductor module according to claim 1,
    The semiconductor element to which the first circuit is electrically connected is a transistor, the semiconductor element to which the second circuit is electrically connected is a diode, and the first terminal contact portion is connected to the emitter of the transistor. And the second terminal contact portion is connected to the anode of the diode.
  3. 　請求項１に記載のパワー半導体モジュールにおいて、
    　上記第１の回路が電気的に接続する半導体素子はトランジスタであり、上記第２の回路が電気的に接続する半導体素子はダイオードであり、上記第１の端子コンタクト部は上記トランジスタのコレクタに接続され、上記第２の端子コンタクト部は上記ダイオードのカソードに接続されていることを特徴とするパワー半導体モジュール。     The power semiconductor module according to claim 1,
    The semiconductor element to which the first circuit is electrically connected is a transistor, the semiconductor element to which the second circuit is electrically connected is a diode, and the first terminal contact portion is connected to the collector of the transistor. And the second terminal contact portion is connected to the cathode of the diode.
  4. 　請求項２に記載のパワー半導体モジュールにおいて、
    　上記ダイオードはシリコンカーバイドを基体として用いたダイオードであることを特徴とするパワー半導体モジュール。     The power semiconductor module according to claim 2,
    The power semiconductor module, wherein the diode is a diode using silicon carbide as a base.
  5. 　請求項３に記載のパワー半導体モジュールにおいて、
    　上記ダイオードはシリコンカーバイドを基体として用いたダイオードであることを特徴とするパワー半導体モジュール。     In the power semiconductor module according to claim 3,
    The power semiconductor module, wherein the diode is a diode using silicon carbide as a base.
  6. 　請求項２に記載のパワー半導体モジュールにおいて、
    　上記トランジスタのエミッタセンス端子の取り出し回路パターンと、上記トランジスタのゲート端子の取り出し回路パターンとが上記基板に形成されていることを特徴とするパワー半導体モジュール。     The power semiconductor module according to claim 2,
    A power semiconductor module, wherein an extraction circuit pattern of an emitter sense terminal of the transistor and an extraction circuit pattern of a gate terminal of the transistor are formed on the substrate.
  7. 　請求項１に記載のパワー半導体モジュールの製造検査方法において、
    　上記第１の端子コンタクト部と、上記共通主端子コンタクト部とを用いて、上記第１の回路パターンが電気的に接続する半導体素子のリーク電流検査を行い、
    　上記第２の端子コンタクト部と、上記共通主端子コンタクト部とを用いて、上記第２の回路パターンが電気的に接続する半導体素子のリーク電流検査を行い、
    　上記第１の端子コンタクト部と上記第２の端子コンタクト部とを電気的に接続し、接続した上記第１の端子コンタクト部及び上記第２の端子コンタクト部と、上記共通端子コンタクト部とを用いて、上記第１の回路パターンが電気的に接続する半導体素子及び上記第２の回路パターンが電気的に接続する半導体素子の動的検査を行い、
    　上記動的検査が終了した後、上記第１の端子コンタクト部と上記第２の端子コンタクト部とを上記電極主端子により互いに接続することを特徴とするパワー半導体モジュールの製造検査方法。     In the manufacturing inspection method of the power semiconductor module according to claim 1,
    Using the first terminal contact portion and the common main terminal contact portion, a leakage current inspection of a semiconductor element to which the first circuit pattern is electrically connected is performed,
    Using the second terminal contact portion and the common main terminal contact portion, a leakage current inspection of a semiconductor element to which the second circuit pattern is electrically connected is performed,
    The first terminal contact portion and the second terminal contact portion are electrically connected, and the connected first terminal contact portion and second terminal contact portion are used together with the common terminal contact portion. A dynamic inspection of the semiconductor element to which the first circuit pattern is electrically connected and the semiconductor element to which the second circuit pattern is electrically connected;
    A method of manufacturing and inspecting a power semiconductor module, comprising: connecting the first terminal contact portion and the second terminal contact portion to each other by the electrode main terminal after the dynamic inspection is completed.
  8. 　請求項７に記載のパワー半導体モジュールの製造検査方法において、
    　上記第１の回路が電気的に接続する半導体素子はトランジスタであり、上記第２の回路が電気的に接続する半導体素子はダイオードであり、上記第１の端子コンタクト部は上記トランジスタのエミッタに接続され、上記第２の端子コンタクト部は上記ダイオードのアノードに接続されていることを特徴とするパワー半導体モジュール。     In the manufacturing inspection method of the power semiconductor module according to claim 7,
    The semiconductor element to which the first circuit is electrically connected is a transistor, the semiconductor element to which the second circuit is electrically connected is a diode, and the first terminal contact portion is connected to the emitter of the transistor. And the second terminal contact portion is connected to the anode of the diode.
  9. 　請求項７に記載のパワー半導体モジュールの製造検査方法において、
    　上記第１の回路が電気的に接続する半導体素子はトランジスタであり、上記第２の回路が電気的に接続する半導体素子はダイオードであり、上記第１の端子コンタクト部は上記トランジスタのコレクタに接続され、上記第２の端子コンタクト部は上記ダイオードのカソードに接続されていることを特徴とするパワー半導体モジュール。     In the manufacturing inspection method of the power semiconductor module according to claim 7,
    The semiconductor element to which the first circuit is electrically connected is a transistor, the semiconductor element to which the second circuit is electrically connected is a diode, and the first terminal contact portion is connected to the collector of the transistor. And the second terminal contact portion is connected to the cathode of the diode.
  10. 　請求項８に記載のパワー半導体モジュールの製造検査方法において、
    　上記ダイオードはシリコンカーバイドを基体として用いたダイオードであることを特徴とするパワー半導体モジュールの製造検査方法。     In the manufacturing inspection method of the power semiconductor module according to claim 8,
    A method for manufacturing and inspecting a power semiconductor module, wherein the diode is a diode using silicon carbide as a substrate.
  11. 　請求項９に記載のパワー半導体モジュールの製造検査方法において、
    　上記ダイオードはシリコンカーバイドを基体として用いたダイオードであることを特徴とするパワー半導体モジュールの製造検査方法。     In the manufacturing inspection method of the power semiconductor module according to claim 9,
    A method for manufacturing and inspecting a power semiconductor module, wherein the diode is a diode using silicon carbide as a substrate.
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JP7466483B2 (en) 2021-03-17 2024-04-12 三菱電機株式会社 Semiconductor Device
DE112022001872T5 (en) 2021-12-27 2024-01-18 Fuji Electric Co., Ltd. SEMICONDUCTOR MODULE
WO2024018810A1 (en) * 2022-07-21 2024-01-25 ローム株式会社 Semiconductor device

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