WO2015131775A1 - 一种2-1t1r rram存储单元和存储阵列 - Google Patents

一种2-1t1r rram存储单元和存储阵列 Download PDF

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WO2015131775A1
WO2015131775A1 PCT/CN2015/073334 CN2015073334W WO2015131775A1 WO 2015131775 A1 WO2015131775 A1 WO 2015131775A1 CN 2015073334 W CN2015073334 W CN 2015073334W WO 2015131775 A1 WO2015131775 A1 WO 2015131775A1
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memory cell
rram
read
current
cell
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PCT/CN2015/073334
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English (en)
French (fr)
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任奇伟
潘立阳
韩小炜
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山东华芯半导体有限公司
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0042—Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/82—Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials

Definitions

  • the present invention relates to the field of emerging non-volatile random access memory design, and in particular to a 2-1T1R RRAM memory cell and a memory array.
  • the resistance of the reference unit itself has a consistency problem, which is positively distributed, and the read margin cannot be guaranteed for the high resistance unit or the low resistance unit.
  • I L –I H always (I L is the current when the resistive unit is in the low-impedance state, and I H is the current when the resistive unit is in the high-impedance state), so it not only reduces the reading speed, but also Greatly reduce the reading success rate.
  • the invention provides a resistive random access memory (RRAM) memory cell with a read self-referencing function, a 2-1T1R (2-1 Transistor 1 Resistor) memory cell and a memory array, and a reference memory cell in an opposite state generates a reference for the main memory cell.
  • the current, read readout is always I L –I H , which greatly improves the read speed and success rate.
  • a 2-1T1R RRAM memory cell with read self-referencing function including two 1T1R RRAM memory cells 1T1R1 and 1T1R2.
  • 1T1R is a conventional RRAM memory cell structure, R is a resistive change cell, and has high resistance and low resistance. State, T is the select transistor. When R is low impedance, 1T1R is stored as '1'. When R is high impedance, 1T1R is stored as '0'.
  • Both 1T1R1 and 1T1R2 can be used as the primary storage unit or the reference storage unit. If 1T1R1 is used as the primary storage unit, 1T1R2 is used as the reference storage unit; if 1T1R2 is used as the primary storage unit, 1T1R1 is used as the reference storage unit.
  • the main memory cell writes '1' (the R of the main memory cell is low-impedance), the reference memory cell writes '0' (refer to the R of the memory cell is high-impedance), and the 2-1T1R memory cell writes The input value is '1'; the main storage unit writes '0', the reference memory location writes '1', and the 2-1T1R memory location writes the value to '0'.
  • the reference memory cell During the read operation, the reference memory cell generates a reference current for the main memory cell, and the read circuit compares the read current generated by the main memory cell with a reference current generated by the reference memory cell, and determines the read value according to the comparison result. Preferably, if the read current is greater than the reference current, the read value is '1', and conversely, the read value is '0'.
  • the current sense and the reference current are compared using a current mode based sense amplifier.
  • the present invention also provides a memory array including a main memory array, a row decoder, a column selection, and an execution circuit based on the 2-1T1R RRAM memory cell, the main memory array including N of the 2-1T1R RRAM memories Unit (N primary storage units and N corresponding reference storage units), N is an integer greater than one.
  • writing to the storage array is: selecting, by the row decoder and the column selection, a 2-1T1R RRAM storage unit that performs reading according to an input address, and the 2-1T1R RRAM storage unit
  • the resistive change unit R in the main memory cell and the resistive change cell R in the reference memory cell of the 2-1T1R RRAM memory cell are set to opposite resistance states, the memory value of the memory array and the main memory cell
  • the stored values are the same.
  • Reading to the storage array selecting, by the row decoder and the column selection, a 2-1T1R RRAM storage unit that performs reading, and storing, by the execution circuit, the 2-1T1R RRAM
  • the read current generated by the main memory cell in the cell is compared with a reference current generated by the reference memory cell, and the stored value of the memory array is read according to the result of the comparison.
  • the read current is greater than the reference current
  • the read value of the memory array is '1'
  • the read current is less than the reference current
  • the read value of the memory array is ' 0'.
  • the current mode based sense amplifier in the execution circuit compares the read current generated by the main memory cell with the reference current generated by the reference memory cell.
  • the 2-1T1R RRAM memory cell and the select transistor T in the memory array are MOS transistors.
  • the present invention has the following advantages:
  • Each 2-1T1R RRAM memory cell in the memory array is mainly composed of two conventional 1T1R memory cells, one is a main memory cell and the other is a reference memory cell, and the reference memory cell in the opposite state generates a reference current for the main memory cell. Not only can the resistance deviation caused by the area and temperature be tracked, but also the reference current is increased from (I L –I H )/2 to I L relative to the reference current generated by the fixed reference current and the shared reference unit. –I H , and can always be I L –I H , which greatly improves the reading speed and success rate; suitable for high-speed embedded applications.
  • Figure 1 is a block diagram of a conventional 1T1R RRAM memory cell.
  • Figure 2 is a block diagram of a 2-1T1R RRAM memory cell of the present invention.
  • 3 is a memory array embodiment based on an exemplary conventional 1T1R RRAM memory cell.
  • FIG. 4 is a memory array embodiment of an exemplary 2-1T1R RRAM memory cell based on the present invention.
  • Figure 5 is a schematic diagram of the reading of a sense amplifier based on current mode.
  • Table 1 shows exemplary conventional 1T1R RRAM memory cell read and write operating conditions.
  • Table 2 shows exemplary read and write operating conditions for an exemplary 2-1T1R RRAM memory cell of the present invention.
  • the conventional 1T1R RRAM memory cell includes a resistive change unit 15 and a selection transistor 16 .
  • One end of the resistive change unit 15 is connected to the bit line BL (Bit Line) 11 , and the other end of the resistive change unit and the drain of the select transistor 16 .
  • the terminal 13 is connected, the source terminal of the selection transistor 16 is connected to the source line SL (Source Line) 12, and the gate terminal is connected to the word line WL (Word Line) 14.
  • the storage value of the 1T1R RRAM memory cell is '1'; when the resistive change cell 15 is set to the high resistance state, the storage value of the 1T1R RRAM memory cell is '0'.
  • Table 1 shows the read and write operation conditions with respect to the 1T1R RRAM memory cell of FIG.
  • "write '1'” is a process of writing '1' to the 1T1R RRAM memory cell, ie, setting the resistive change unit 15 to a low-impedance state
  • "writing '0'” is for the 1T1R RRAM memory cell.
  • Writing '0' that is, the process of setting the resistive switching unit 15 to a high impedance state
  • “reading” is a process of reading the 1T1R RRAM memory cell.
  • the 1T1R RRAM memory cell is read, that is, the word line WL 14 is connected to the power supply VDD, the bit line BL 11 is connected to the voltage Vread, the source line SL 12 is connected to the ground GND, and then passed through a current mode based sense amplifier.
  • the read current on the bit line BL 11 is compared with the reference current (the fixed reference current or the reference current generated by the shared reference cell). If the read current on the bit line BL 11 is greater than the reference current, the reading of the 1T1R RRAM memory cell is performed. The value is '1'. If the current on the bit line BL 11 is less than the reference current, the reading of the 1T1R RRAM memory cell The value is '0'.
  • 1T1R1 and 1T1R2 have the 1T1R structure shown in FIG.
  • 1T1R1 comprising a resistive element 24 and the selection transistor 25
  • resistive element 24 is the anode and the bit line BL1 21 connected to the cathode terminal of a drain of the selection transistor 25 of resistive element 24 is connected to a source terminal of the source select transistor 25
  • the line SL1 22 is connected, the gate terminal is connected to the word line WL1 23;
  • the 1T1R2 includes the resistive change unit 29 and the selection transistor 30 , and the anode of the resistive change unit 29 is connected to the bit line BL2 26, and the cathode of the resistive change unit 29 and the drain of the selection transistor 30
  • the source terminal of the selection transistor 30 is connected to the source line SL2 27, and the gate terminal is connected to the word line WL2 28.
  • One of 1T1R1 and 1T1R2 is used as the main storage unit, and the other is used as the reference storage unit.
  • the read and write operation conditions of each of 1T1R1 and 1T1R2 are as shown in Table 1.
  • the resistive switching unit 24 is set to the low resistance state
  • the storage value of the 1T1R1 RRAM memory cell is '1'
  • the resistive switching cell 24 is set to the high impedance state
  • the storage value of the 1T1R1 memory cell is '0'.
  • the storage value of the 1T1R2 RRAM memory cell is '1'; when the resistive change cell 29 is set to the high resistance state, the storage value of the 1T1R2 memory cell is '0'.
  • Table 2 shows the read and write operation conditions of the 2-1T1R RRAM memory cell of FIG. 2.
  • 1T1R1 is used as the primary storage unit
  • 1T1R2 is used as the reference storage unit (it is emphasized that 1T1R2 may be the main The storage unit, 1T1R1 as a reference storage unit).
  • 1T1R1 may be the main The storage unit, 1T1R1 as a reference storage unit).
  • Reading 2-1T1R that is, connecting word line WL1 23 and word line WL2 28 to power supply VDD, connecting bit lines BL1 21 and BL2 26 to voltage Vread, and source lines SL1 22 and SL2 27 are both The ground GND is connected, and then the read current on the bit line BL1 21 of the main memory cell 1T1R1 is compared with the reference current on the bit line BL2 26 of the reference memory cell 1T1R2 by the current mode based sense amplifier, if the bit line BL1 21 The read current is greater than the reference current on bit line BL2 26, and the read value of the 2-1T1R RRAM memory cell is '1'. If the read current on bit line BL1 21 is less than the reference current on bit line BL2 26, then The read value of the 2-1T1R RRAM memory cell is '0'.
  • FIG. 3 illustrates one memory array embodiment based on an exemplary conventional 1T1R RRAM memory cell.
  • the memory array embodiment includes a main memory array 314 consisting of N (N is an integer greater than 1) conventional 1T1R memory cells 311 , a reference array 315 , a row decoder 313 , a column selection 316 , a current buffer 317, and an execution circuit 318 .
  • N is an integer greater than 1
  • the different memory cells have the same reference memory cells, and the bit and source lines connected to the respective memory cells are connected to column selects 316 (e.g., bit line 322 and source line 323), and reference storage.
  • the word line connected to the cell is the same as the word line connected to the memory cell, and the bit line 324 and the source line 325 connected to the reference memory cell are connected to the current buffer 317 .
  • Column select 316 and current buffer 317 are both connected to execution circuit 318 .
  • Execution circuit 318 connects data line 326.
  • the bit lines according to the input address selection unit 311 is connected with the 1T1R memory 322, source line 323 and word line 321, and the bit line 322 connected to the Vset voltage, the source line 323 and the ground GND is connected to the word line 321 connected to a voltage Vset_wl, and open the 1T1R memory cell selection transistor 311, thereby achieving the 1T1R resistive memory cell unit 311 is set to a low resistance state, The process of writing '1' to the 1T1R unit 311 is completed, thus completing the process of writing '1' to the storage array.
  • the bit line 322, the source line 323, and the word line 321 connected to the 1T1R memory cell 311 are selected according to the input address, and the bit line 322 is connected to the ground GND, and the source line 323 is connected to the voltage.
  • Vreset the word line 321 is connected to the voltage Vreset_wl, and the selection transistor of the 1T1R memory cell 311 is turned on, thereby realizing the process of setting the resistive cell of the 1T1R memory cell 311 to a high resistance state, and completing the writing of '0' to the 1T1R cell 311 . Therefore, the process of writing '0' to the storage array is completed.
  • the bit line 322, the source line 323, and the word line 321 connected to the 1T1R memory cell 311 are first selected according to the input address, and the bit line 322 is used.
  • the source line bit line connected to the voltage Vread, the source line 323 and the ground GND is connected to 321 is connected to the power supply VDD word line, while connected to the reference memory cell 312 to 324 connected to voltage Vread, to be connected to the reference memory cell 312 325
  • the ground GND is connected, the word line connected to the reference memory cell 312 is connected to the power supply VDD, and the selection transistors of the memory cell 311 and the reference memory cell 312 are turned on, and then the current mode-based sense amplifier pair memory cell 311 in the execution circuit 318 is executed.
  • the read current on the bit line 322 is compared with the reference current on the bit line 324 of the reference memory cell 312. If the read current is greater than the reference current, the read value of the memory array is '1' if the current is read. Below the reference current, the read value of the memory array is '0'.
  • the storage unit 311 in FIG. 3 in the above-mentioned read and write process is only one schematic storage unit in the main storage array 314 , and the actual working position may be any storage unit in the main storage array 314 .
  • the row decoder 313 and the column selection 316 determine which location of the memory cell is selected.
  • the reference storage unit 312 in FIG. 3 in the above reading process is only one schematic reference storage unit in the reference array 315 , and the actual working position may be any reference storage unit in the reference array 315 , specifically by the row decoder 313. Determine which location of the reference storage unit is selected.
  • FIG. 4 shows a memory array embodiment of a 2-1T1R RRAM memory cell in accordance with the present invention.
  • the memory array includes a main memory array 415 consisting of N (N is an integer greater than 1) of the 2-1T1R RRAM memory cells 411 of the present invention, a row decoder 414 , a column select 416, and an execution circuit 417 .
  • the memory array includes N 1T1R main memory cells 412 and N corresponding reference memory cells 413 , and bit lines and source lines connected to each 2-1T1R memory cell 411 are connected to column selection 416.
  • the read current generated by the main memory cell flows through line 424 to execution circuit 417
  • the reference current generated by the reference memory cell flows through line 425 to execution circuit 417 .
  • Execution circuit 417 includes a write driver and a sense amplifier.
  • a write operation is performed on the memory array, that is, when a '1' is written to the memory array, the bit line 420, the source line 421 and the word line 418 connected to the main memory unit 412 , and the reference memory unit are selected according to the input address. 413 connected bit line 422, source line 423 and word line 419, then connect bit line 420 to voltage Vset, connect source line 421 to ground GND, connect word line 418 to voltage Vset_wl, and connect bit line 422 to ground GND.
  • the source line 423 is connected to the voltage Vreset, the word line 419 is connected to the voltage Vreset_wl, and the selection transistors of the main memory unit 412 and the reference memory unit 413 are turned on, thereby implementing the resistance change unit of the main memory unit 412 to a low resistance state and will be referred to
  • the resistive unit of the memory cell 413 is set to a high-impedance state, completing the process of writing '1' to the main memory cell 412 and simultaneously writing '0' to the reference memory cell 413 , thus completing writing '1' to the memory array.
  • the bit line 420, the source line 421 and the word line 418 connected to the main memory unit 412 , and the bit line 422, the source line 423, and the word connected to the reference memory unit 413 are selected according to the input address.
  • a read operation is performed on the memory array, that is, a read operation is performed on the 2-1T1R RRAM memory cell 411 , and the bit line 420, the source line 421, and the word line 418 connected to the main memory unit 412 are first selected according to the input address, and Referring to the bit line 422, the source line 423, and the word line 419 connected to the memory cell 413 , the bit lines 420 and 422 are then connected to the voltage Vread, the source lines 421 and 423 are connected to the ground GND, and the word lines 418 and 419 are connected to the power supply VDD.
  • the read current on the bit line 420 of the main memory cell 412 and the bit of the reference memory cell 413 The reference current on line 422 is compared. If the read current is greater than the reference current, the read value of the memory array is '1'. If the read current is less than the reference current, the read value of the memory array is '0'. .
  • the storage unit 411 in FIG. 4 in the above-mentioned reading and writing process is only one schematic storage unit in the main storage array 415 , and the actual working position may be any storage unit in the main storage array 415 , specifically
  • the row decoder 414 and column selection 416 determine which location of the memory cell is selected.
  • Figure 5 shows the read schematic of a sense amplifier based on current mode.
  • the two input terminals of the sense amplifier are connected to the two paths 511 and 512 through lines 530 and 531, respectively, and the voltages at the connection points are Vin and Vref, respectively.
  • the main memory cell 513 and the reference memory cell 514 of the 2-1T1R RRAM memory cell 515 are selected by the column select signal Ysel 528 at the gate terminal of the select transistor Nsel. And clamping the voltages of the bit lines 523 and 524 connected to the memory cells 513 and 514 to the voltage Vread by the clamp voltage Vclamp provided at the gate terminal of the clamp transistor Nclp, respectively, and connecting them to the memory cells 513 and 514, respectively.
  • the source lines 525 and 526 are connected to the ground GND, the word line 529 is connected to the power supply VDD, and the selection transistors of the memory cells 513 and 514 are turned on, at which time the current flowing through the memory cells 513 and 514 is read by the main memory cell, respectively.

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Abstract

本发明提供一种2-1T1R RRAM存储单元和存储阵列。该存储单元由两个1T1R RRAM存储单元组成，其中一个为主存储单元，另外一个为参考存储单元。对2-1T1R RRAM存储单元进行写操作时，将两个1T1R存储单元的阻变单元设置为相反的状态，2-1T1R存储单元的存储值与主存储单元的存储值相同；对2-1T1R RRAM存储单元进行读操作时，通过基于电流的灵敏放大器对所述主存储单元产生的读取电流和所述参考存储单元产生的参考电流作比较，根据比较的结果读取2-1T1R RRAM存储单元的值。该存储阵列包括由N（N为大于1的整数）个该2-1T1R RRAM存储单元组成的主存储阵列、行译码器、列选择以及执行电路。

Description

一种2-1T1R RRAM存储单元和存储阵列 技术领域
本发明涉及新兴的非挥发随机存储器设计领域，具体涉及一种2-1T1R RRAM存储单元和存储阵列。
背景技术
近几年在智能手机、智能电视和平板电脑等消费类市场牵引下，flash存储器得到迅速发展。但是，由于复杂的掩模图形及昂贵的制造成本，越来越大的字线漏电和单元之间的串扰，以及浮栅中电子数目越来越少等原因，其尺寸缩小能力受到了很大限制。因此，新兴的非挥发存储器CBRAM、MRAM、PRAM、RRAM等越来越受到重视，其中RRAM凭借高速度、大容量、低功耗、低成本和高可靠性被认为是flash最有力的候选者。
但是，由于工艺、电压以及温度(PVT)的影响，RRAM阻变单元电阻大小存在严重的一致性问题，晶圆和晶圆之间，芯片与芯片之间，同一芯片上不同区域都存在着电阻大小的偏差。无论是高阻态还是低阻态，电阻大小都是有一定范围的正态分布。因此，对于基于电流模式的读取电路来说，就很难提供一个比较理想的参考电流。首先采用固定参考电流是不可能，因为它无法跟踪阻变单元高阻态和低阻态由于区域和温度带来的偏差。对于共享的参考单元来说，虽然能够跟踪电阻随着区域和温度的变化，但参考单元本身电阻大小也存在一致性问题，呈正太分布，对于高阻单元或者低阻单元不能保证读取裕度始终为(IL–IH)/2(IL为阻变单元处于低阻态时的电流，IH为阻变单元处于高阻态时的电流)，所以不仅会降低读取速度，还大大减小读取成功率。
发明内容
本发明提出一种具有读取自参考功能的阻变随机存储器(RRAM)存储单元，2-1T1R(2-1Transistor 1Resistor)存储单元和存储阵列，处于相反状态的参考存储单元为主存储单元产生参考电流，读取裕读始终为IL–IH， 大大提高了读取速度和成功率。
为了实现上述目的，本发明采用如下技术方案：
一种具有读取自参考功能的2-1T1R RRAM存储单元，包括两个1T1R RRAM存储单元1T1R1和1T1R2。1T1R为传统的RRAM存储单元结构，R为阻变单元，具有高阻和低阻两个状态，T为选择晶体管，当R为低阻态时，1T1R存储值为‘1’，当R为高阻态时，1T1R存储值为‘0’。
1T1R1和1T1R2均可以作为主存储单元或参考存储单元，若1T1R1作为主存储单元，则1T1R2作为参考存储单元；若1T1R2作为主存储单元，则1T1R1作为参考存储单元。
写操作时，主存储单元写入‘1’(主存储单元的R为低阻态)，参考存储单元写入‘0’(参考存储单元的R为高阻态)，2-1T1R存储单元写入值为‘1’；主存储单元写入‘0’，参考存储单元写入‘1’，2-1T1R存储单元写入值为‘0’。
读操作时，参考存储单元为主存储单元产生参考电流，读取电路对主存储单元产生的读取电流和参考存储单元产生参考电流进行比较，根据所述比较结果确定读取值。优选地，若读取电流大于参考电流，读取值为‘1’，反之，读取值为‘0’。在本发明的一个实施方案中，使用基于电流模式的灵敏放大器对该读取电流和该参考电流进行比较。
本发明还提出一种存储阵列，包括基于所述2-1T1R RRAM存储单元的主存储阵列、行译码器、列选择以及执行电路，所述主存储阵列包括N个所述2-1T1R RRAM存储单元(N个主存储单元和N个相应的参考存储单元)，N为大于1的整数。
优选地，对所述存储阵列写入为：通过所述行译码器和所述列选择根据输入的地址选择出执行读取的2-1T1R RRAM存储单元，将所述2-1T1R RRAM存储单元的主存储单元中的阻变单元R和所述2-1T1R RRAM存储单元的参考存储单元中的阻变单元R设置为相反的阻态，所述存储阵列的存储值与所述主存储单元的存储值相同。
对所述存储阵列读取为：通过所述行译码器和所述列选择选择出执行读取的2-1T1R RRAM存储单元，由执行电路对所述2-1T1R RRAM存储 单元中主存储单元产生的读取电流和参考存储单元产生的参考电流作比较，根据所述比较的结果读取所述存储阵列的存储值。优选地，若所述读取电流大于所述参考电流，所述存储阵列的读取值为‘1’；若所述读取电流小于所述参考电流，所述存储阵列的读取值为‘0’。
优选地，使用所述执行电路中的基于电流模式的灵敏放大器对主存储单元产生的读取电流和参考存储单元产生的参考电流作比较。优选地，所述2-1T1R RRAM存储单元和存储阵列中的选择晶体管T是MOS晶体管。
相对于现有技术，本发明具有以下优点：
存储阵列中的每个2-1T1R RRAM存储单元主要由两个传统的1T1R存储单元组成，一个为主存储单元，另一个为参考存储单元，处于相反状态的参考存储单元为主存储单元产生参考电流，不仅可以跟踪区域和温度带来的电阻偏差，而且相对于采用固定参考电流和共享参考单元产生参考电流，还将读取裕度从(IL–IH)/2提高一倍至IL–IH，且可以始终保持为IL–IH，大大提高了读取速度和成功率；适合高速嵌入式应用。
附图说明
为便于阅读附图，各附图中的标号分为带有下划线和不带下划线两种，其中带有下划线的标号指代电子元器件或功能单元，不带下划线的标号指代线路。
图1为一个传统的1T1R RRAM存储单元的结构图。
图2为一个本发明的2-1T1R RRAM存储单元的结构图。
图3为基于示例性传统1T1R RRAM存储单元的一个存储阵列实施例。
图4为基于本发明示例性2-1T1R RRAM存储单元的一个存储阵列实施例。
图5为基于电流模式的灵敏放大器的读取原理图。
附表说明
表1为示例性传统的1T1R RRAM存储单元读写操作条件。
表2为本发明示例性2-1T1R RRAM存储单元读写操作条件。
具体实施方式
下面结合附图和附表对本发明的实施方式做进一步描述。
图1为示例性传统的1T1R RRAM存储单元的结构图。如图1所示，传统的1T1R RRAM存储单元包括阻变单元15和选择晶体管16，阻变单元15的一端与位线BL(Bit Line)11连接，阻变单元另一端与选择晶体管16的漏极端13连接，选择晶体管16的源极端与源线SL(Source Line)12连接，栅极端与字线WL(Word Line)14连接。当将阻变单元15设置为低阻态时，1T1R RRAM存储单元的存储值为‘1’；当将阻变单元15设置为高阻态时，1T1R RRAM存储单元的存储值为‘0’。
表1为相对于图1的1T1R RRAM存储单元的读写操作条件。在表1中，“写入‘1’”是对1T1R RRAM存储单元写入‘1’，即将阻变单元15设置为低阻态的过程；“写入‘0’”是对1T1R RRAM存储单元写入‘0’，即将阻变单元15设置为高阻态的过程；“读取”是对1T1R RRAM存储单元进行读取的过程。
如表1所示：
对1T1R RRAM存储单元写入‘1’，也就是，将字线WL 14连接电压Vset_wl，将位线BL 11连接电压Vset，将源线SL 12与地GND连接，从而实现将阻变单元15设置为低阻态；
对1T1R RRAM存储单元写入‘0’，也就是，将字线WL 14连接电压Vreset_wl，将位线BL 11与地GND连接，将源线SL 12连接电压Vreset，从而实现将阻变单元15设置为高阻态；
对1T1R RRAM存储单元进行读取，也就是，将字线WL 14与电源VDD连接，将位线BL 11连接电压Vread，将源线SL 12与地GND连接，之后通过基于电流模式的灵敏放大器将位线BL 11上的读取电流和参考电流(固定参考电流或共享参考单元产生的参考电流)作对比，如果位线BL 11上的读取电流大于参考电流，则1T1R RRAM存储单元的读取值为‘1’，如果位线BL 11上的电流小于参考电流，则1T1R RRAM存储单元的读取 值为‘0’。
表1
1T1R 写入‘1’ 写入‘0’ 读取
WL Vset_wl Vreset_wl VDD
BL Vset 0 Vread
SL 0 Vreset 0
状态 LRS(1) HRS(0) 1/0
图2为本发明的具有读取自参考功能的示例性2-1T1R RRAM存储单元，包括两个传统的1T1R RRAM存储单元1T1R1和1T1R2。1T1R1和1T1R2具有图1所示的1T1R结构，如图2所示，1T1R1包括阻变单元24和选择晶体管25，阻变单元24的阳极与位线BL1 21连接，阻变单元24的阴极与选择晶体管25的漏极端连接，选择晶体管25的源极端与源线SL1 22连接，栅极端与字线WL1 23连接；1T1R2包括阻变单元29和选择晶体管30，阻变单元29的阳极与位线BL2 26连接，阻变单元29的阴极与选择晶体管30的漏极端连接，选择晶体管30的源极端与源线SL2 27连接，栅极端与字线WL2 28连接。
1T1R1和1T1R2中一个作为主存储单元，另一个作为参考存储单元，1T1R1和1T1R2每个的读写操作条件如表1所示。当将阻变单元24设置为低阻态时，1T1R1 RRAM存储单元的存储值为‘1’；当将阻变单元24设置为高阻态时，1T1R1存储单元的存储值为‘0’。当将阻变单元29设置为低阻态时，1T1R2 RRAM存储单元的存储值为‘1’；当将阻变单元29设置为高阻态时，1T1R2存储单元的存储值为‘0’。
表2为图2的2-1T1R RRAM存储单元的读写操作条件，在此实施方案中，将1T1R1作为主存储单元，1T1R2作为参考存储单元(需要强调的是，也可以是，将1T1R2作为主存储单元，1T1R1作为参考存储单元)。如表2所示：
对2-1T1R RRAM写入‘1’，也就是，对主存储单元1T1R1存储单元写入‘1’，同时对参考存储单元1T1R2存储单元写入‘0’，即将字线WL1 23连接电压Vset_wl，将位线BL1 21连接电压Vset，将源线SL1 22与地GND 连接，将字线WL2 28连接电压Vreset_wl，将位线BL2 26与地GND连接，将源线SL2 27连接电压Vreset，从而实现将阻变单元24设置为低阻态且同时实现将阻变单元29设置为高阻态；
对2-1T1R RRAM写入‘0’，也就是，对主存储单元1T1R1存储单元写入‘0’，同时对参考存储单元1T1R2存储单元写入‘1’，即将字线WL1 23连接电压Vreset_wl，将位线BL1 21与地GND连接，将源线SL1 22连接电压Vreset，将字线WL2 28连接电压Vset_wl，将位线BL2 26连接电压Vset，将源线SL2 27与地GND连接，从而实现将阻变单元24设置为高阻态且同时实现将阻变单元29设置为低阻态；
对2-1T1R进行读取，也就是，将字线WL1 23和字线WL2 28均与电源VDD连接，将位线BL1 21和BL2 26均连接电压Vread，将源线SL1 22和SL2 27均与地GND连接，之后通过基于电流模式的灵敏放大器对主存储单元1T1R1的位线BL1 21上的读取电流和参考存储单元1T1R2的位线BL2 26上的参考电流作比较，如果位线BL1 21上的读取电流大于位线BL2 26上的参考电流，2-1T1R RRAM存储单元的读取值为‘1’，如果位线BL1 21上的读取电流小于位线BL2 26上的参考电流，则2-1T1R RRAM存储单元的读取值为‘0’。
表2
Figure PCTCN2015073334-appb-000001
图3示出了基于示例性传统1T1R RRAM存储单元的一个存储阵列实施例。该存储阵列实施例包括由N(N为大于1的整数)个传统1T1R存储单元311组成的主存储阵列314、参考阵列315、行译码器313、列选择316、电流缓冲区317以及执行电路318。从图3中可以看到，不同的存储单元具有相同的参考存储单元，与各个存储单元连接的位线和源线连接到列选择316(例如：位线322和源线323)，与参考存储单元连接的字线和与存储单元连接的字线相同，与参考存储单元连接的位线324和源线325连接到电流缓冲区317。列选择316和电流缓冲区317均连接到执行电路318。执行电路318连接数据线326。
对该存储阵列进行写入操作，也就是，对1T1R存储单元311写入‘1’时，根据输入地址选择与1T1R存储单元311连接的位线322、源线323和字线321，且将位线322连接电压Vset，将源线323与地GND连接，将字线321连接电压Vset_wl，并打开1T1R存储单元311的选择晶体管，从而实现将1T1R存储单元311的阻变单元设置为低阻态，完成对1T1R单元311写入‘1’的过程，因此完成对存储阵列写入‘1’的过程。
对1T1R单元311写入‘0’时，根据输入地址选择与1T1R存储单元311连接的位线322、源线323和字线321，且将位线322与地GND连接，将源线323连接电压Vreset，将字线321连接电压Vreset_wl，并打开1T1R存储单元311的选择晶体管，从而实现将1T1R存储单元311的阻变单元设置为高阻态，完成对1T1R单元311写入‘0’的过程，因此完成对存储阵列写入‘0’的过程。
对该存储阵列进行读取操作，也就是对存储单元311进行读取操作时，首先根据输入地址选择与1T1R存储单元311连接的位线322、源线323和字线321，且将位线322连接电压Vread，将源线323与地GND连接，将字线321与电源VDD连接，同时将与参考存储单元312连接的位线324连接电压Vread，将与参考存储单元312连接的源线325与地GND连接，将与参考存储单元312连接的字线与电源VDD连接，并打开存储单元311和参考存储单元312的选择晶体管，然后通过执行电路318中的基于电流模式的灵敏放大器对存储单元311的位线322上的读取电流和参考存储单 元312的位线324上的参考电流作对比，如果读取电流大于参考电流，则该存储阵列的读取值为‘1’，如果读取电流小于参考电流，则该存储阵列的读取值为‘0’。
需要强调的是：为了便于说明，上述读写过程中图3中的存储单元311只是主存储阵列314中的一个示意存储单元，实际工作时位置可以为主存储阵列314中任一存储单元，具体由行译码器313和列选择316确定选中哪个位置的存储单元。同样的，上述读过程中图3中的参考存储单元312只是参考阵列315中的一个示意参考存储单元，实际工作时位置可以为参考阵列315中任一参考存储单元，具体由行译码器313确定选中哪个位置的参考存储单元。
图4给出了基于本发明的2-1T1R RRAM存储单元的一个存储阵列实施例。该存储阵列包括由N(N为大于1的整数)个本发明的2-1T1R RRAM存储单元411组成的主存储阵列415，行译码器414，列选择416以及执行电路417。在图4的实施例中，该存储阵列包括N个1T1R主存储单元412和N个相应的参考存储单元413，与每个2-1T1R存储单元411连接的位线和源线连接到列选择416，主存储单元产生的读取电流流经线424至执行电路417，参考存储单元产生的参考电流流经线425至执行电路417。执行电路417包括写驱动器和灵敏放大器。
对该存储阵列进行写入操作，也就是，对该存储阵列写入‘1’时，根据输入地址选择与主存储单元412连接的位线420、源线421和字线418以及与参考存储单元413连接的位线422、源线423和字线419，然后将位线420连接电压Vset，将源线421与地GND连接，将字线418连接电压Vset_wl，将位线422与地GND连接，将源线423连接电压Vreset，将字线419连接电压Vreset_wl，并打开主存储单元412和参考存储单元413的选择晶体管，从而实现将主存储单元412的阻变单元设置为低阻态且将参考存储单元413的阻变单元设置为高阻态，完成对主存储单元412写入‘1’且同时对参考存储单元413写入‘0’的过程，因此完成对存储阵列写入‘1’。
对该存储阵列写入‘0’时，根据输入地址选择与主存储单元412连接的 位线420、源线421和字线418以及与参考存储单元413连接的位线422、源线423和字线419，然后将位线420与地GND连接，将源线421连接电压Vreset，将字线418连接电压Vreset_wl，将位线422连接电压Vset，将源线423与地GND连接，将字线419连接电压Vset_wl，并打开主存储单元412和参考存储单元413的选择晶体管，从而实现将主存储单元412的阻变单元设置为高阻态且同时将参考存储单元413的阻变单元设置为低阻态，完成对主存储单元412写入‘0’且对参考存储单元413写入‘1’的过程，因此完成对存储阵列写入‘0’。
对该存储阵列进行读取操作，也就是，对2-1T1R RRAM存储单元411进行读取操作，首先根据输入地址选择与主存储单元412连接的位线420、源线421和字线418以及与参考存储单元413连接的位线422、源线423和字线419，然后将位线420和422连接电压Vread，将源线421和423与地GND连接，将字线418和419与电源VDD连接，并打开主存储单元412和参考存储单元413的选择晶体管，然后通过执行电路417中的基于电流模式的灵敏放大器对主存储单元412的位线420上的读取电流和参考存储单元413的位线422上的参考电流作比较，如果读取电流大于参考电流，则该存储阵列的读取值为‘1’，如果读取电流小于参考电流，则该存储阵列的读取值为‘0’。
需要强调的是：为了便于说明，上述读写过程中图4中的存储单元411只是主存储阵列415中的一个示意存储单元，实际工作时位置可以为主存储阵列415中任一存储单元，具体由行译码器414和列选择416确定选中哪个位置的存储单元。
图5给出了基于电流模式的灵敏放大器的读取原理图。其中灵敏放大器的两个输入端分别通过线530和531与两个通路511和512连接，连接点的电压分别为Vin和Vref。
如图5所示，对2-1T1R存储单元515进行读取时，通过选择晶体管Nsel的栅极端处的列选择信号Ysel 528选择2-1T1R RRAM存储单元515的主存储单元513和参考存储单元514，且通过将箝位晶体管Nclp的栅极端设置的钳位电压Vclamp分别将与存储单元513和514连接的位线523 和524的电压钳位至电压Vread，并将分别与存储单元513和514连接的源线525和526连接至地GND，将字线529连接至电源VDD，同时打开存储单元513和514的选择晶体管，此时流经存储单元513和514的电流分别为主存储单元产生的读取电流Icell和参考存储单元产生的参考电流Iref，因为Icell和Iref的大小不同，所以在Pm晶体管521和522分别与灵敏放大器516的连接点530和531处的电压Vin和Vref不相同，当Vin<Vref(即Icell>Iref)时，2-1T1R RRAM存储单元515的读取值为‘1’，当Vin>Vref(即Icell<Iref)时，2-1T1R RRAM存储单元515的读取值为‘0’。

Claims (10)

  1. 一种2-1T1R RRAM存储单元，其特征在于：包括两个1T1R RRAM存储单元，分别记为1T1R1和1T1R2，其中一个作为主存储单元，另一个作为参考存储单元；
    所述1T1R RRAM存储单元包括一个阻变单元R和一个选择晶体管T，阻变单元R具有高阻态和低阻态两个状态，以实现‘0’和‘1’的写入；
    写入时，主存储单元的阻变单元R与参考存储单元的阻变单元R保持相反的阻态，2-1T1R RRAM存储单元的值等于主存储单元的值；读取时，参考存储单元为主存储单元产生参考电流。
  2. 根据权利要求1所述的2-1T1R RRAM存储单元，其中
    对所述2-1T1R RRAM存储单元写入‘1’为：将所述主存储单元中的阻变单元R设置为低阻态，将所述参考存储单元中的阻变单元R设置为高阻态；
    对所述2-1T1R RRAM存储单元写入‘0’为：将所述主存储单元中的阻变单元R设置为高阻态，将所述参考存储单元中的阻变单元R设置为低阻态。
  3. 根据权利要求1或2所述的2-1T1R RRAM存储单元，其中对所述2-1T1R RRAM存储单元读取为：对所述主存储单元产生的读取电流和所述参考存储单元产生的参考电流作比较，根据所述比较的结果读取所述存储阵列的存储值。
  4. 根据权利要求3所述的2-1T1R RRAM存储单元，若所述读取电流大于所述参考电流，所述2-1T1R RRAM存储单元的读取值为‘1’，若所述读取电流小于所述参考电流，所述2-1T1R RRAM存储单元的读取值为‘0’。
  5. 根据权利要求3所述的2-1T1R RRAM存储单元，其中使用基于电流模式的灵敏放大器对所述主存储单元产生的读取电流和所述参考存储单元产生的参考电流作比较。
  6. 一种存储阵列，其特征在于，包括基于权利要求1所述的2-1T1R RRAM存储单元的主存储阵列、行译码器、列选择以及执行电路，其中所述主存储阵列包括N个所述2-1T1R RRAM存储单元，N为大于1的整数。
  7. 根据权利要求6所述的存储阵列，其中对所述存储阵列写入为：通过所述行译码器和所述列选择根据输入的地址选择出执行读取的2-1T1R RRAM存储单元，将所述2-1T1R RRAM存储单元的主存储单元中的阻变单元R和所述2-1T1R RRAM存储单元的参考存储单元中的阻变单元R设置为相反的阻态，所述存储阵列的存储值与所述主存储单元的存储值相同。
  8. 根据权利要求6或7所述的存储阵列，其中对所述存储阵列读取为：通过所述行译码器和所述列选择选择出执行读取的2-1T1R RRAM存储单元，由执行电路对所述2-1T1R RRAM存储单元中主存储单元产生的读取电流和参考存储单元产生的参考电流作比较，根据所述比较的结果读取所述存储阵列的存储值。
  9. 根据权利要求8所述的存储阵列，其中所述读取电流大于所述参考电流，所述存储阵列的读取值为‘1’；所述读取电流小于所述参考电流，所述存储阵列的读取值为‘0’。
  10. 根据权利要求8所述的存储阵列，其中使用所述执行电路中的基于电流模式的灵敏放大器对所述读取电流和所述参考电流作比较。
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