WO2015115739A1 - Three dimensional flash memory using electrode layers and/or interlayer insulation layers having different properties, and preparation method therefor - Google Patents

Three dimensional flash memory using electrode layers and/or interlayer insulation layers having different properties, and preparation method therefor Download PDF

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Publication number
WO2015115739A1
WO2015115739A1 PCT/KR2014/013095 KR2014013095W WO2015115739A1 WO 2015115739 A1 WO2015115739 A1 WO 2015115739A1 KR 2014013095 W KR2014013095 W KR 2014013095W WO 2015115739 A1 WO2015115739 A1 WO 2015115739A1
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Prior art keywords
interlayer insulating
layer
electrode layers
layers
electrode
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PCT/KR2014/013095
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French (fr)
Korean (ko)
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송윤흡
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한양대학교 산학협력단
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Priority claimed from KR1020140122650A external-priority patent/KR101622036B1/en
Application filed by 한양대학교 산학협력단 filed Critical 한양대학교 산학협력단
Priority to CN201480074446.7A priority Critical patent/CN105940492B/en
Priority to US15/115,232 priority patent/US9922990B2/en
Priority to CN201811575987.4A priority patent/CN110085597B/en
Publication of WO2015115739A1 publication Critical patent/WO2015115739A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to a three-dimensional flash memory using an electrode layer and / or an interlayer insulating layer having different characteristics, and to a method of manufacturing the same.
  • each of the plurality of electrode layers has different characteristics or a plurality of interlayer insulating layers.
  • a three-dimensional flash memory and a method of manufacturing the same which improve the threshold voltage distribution of a plurality of electrode layers and make the stress level applied to each of the plurality of interlayer insulating layers by having each of them have different characteristics.
  • Flash memory devices are electrically erasable programmable read only memory (EEPROM), which may be, for example, a computer, a digital camera, an MP3 player, a game system, a memory stick. ) May be commonly used.
  • EEPROM electrically erasable programmable read only memory
  • the flash memory device electrically controls input and output of data by F-N tunneling or hot electron injection.
  • N cell transistors are connected in series to form a unit string, and the unit strings are connected in parallel between a bit line and a ground line.
  • NAND-type flash memory device having a structure in which the cell transistors are connected in parallel between the bit line and the ground line.
  • the flash memory device should be designed to store high capacity data. Therefore, a plurality of cell transistors must be formed in the unit chip. However, it is not easy to highly integrate cell transistors within a limited horizontal area.
  • the three-dimensional memory structure improves the limitation of two-dimensional scaling of NAND flash memory.
  • the structure of the three-dimensional NAND flash memory includes, for example, a BICS (Built-In Current Sensor) structure and a pipe type (BiP Type) Bit Cost Scalable (BIC) NAND flash memory structure having an improved BICS structure.
  • Embodiments of the present invention provide a three-dimensional flash memory and a method of manufacturing the same by improving the threshold voltage distribution of the plurality of electrode layers by different physical structures or materials of the plurality of electrode layers.
  • embodiments of the present invention by making the physical structure or material of the interlayer insulating layers, as well as the plurality of electrode layers different from each other, the three-dimensional flash memory and its fabrication to uniform the stress level applied to each of the interlayer insulating layers Provide a method.
  • 3D flash memory is a channel layer; A plurality of electrode layers connected to the channel layer and stacked vertically; And a plurality of interlayer insulating layers connected to the channel layer, alternately disposed with the plurality of electrode layers, and stacked vertically, wherein each of the plurality of electrode layers has a different physical structure or is different from each other. It is formed of a substance.
  • the thickness of the first electrode layer among the plurality of electrode layers may be thicker than the thickness of the second electrode layer existing on the upper layer of the first electrode layer.
  • the length of each of the plurality of electrode layers or the pattern formed on the surface of each of the plurality of electrode layers may be different.
  • the material forming the first electrode layer among the plurality of electrode layers may have better electrical transfer characteristics than the material of the second electrode layer existing on the upper layer of the first electrode layer.
  • Each of the at least two electrode layers of the plurality of electrode layers may be formed of different materials.
  • An interlayer oxide film, the silicon nitride film, and a tunnel oxide film may be disposed between each of the plurality of electrode layers and the channel layer.
  • 3D flash memory is a channel layer; A plurality of electrode layers connected to the channel layer and stacked vertically; And a plurality of interlayer insulating layers connected to the channel layer, alternately disposed with the plurality of electrode layers, and stacked vertically, wherein each of the plurality of interlayer insulating layers is formed of a different material or is different from each other. It has a physical structure.
  • the material forming the first interlayer insulating layer among the plurality of interlayer insulating layers may have a property that is stronger in stress than the material of the second interlayer insulating layer existing on the first interlayer insulating layer.
  • At least two interlayer insulating layers of the plurality of interlayer insulating layers may be formed of different materials.
  • the thickness of the first interlayer insulating layer of the plurality of interlayer insulating layers may be thicker than the thickness of the second interlayer insulating layer on the upper layer of the first interlayer insulating layer.
  • a length of each of the plurality of interlayer insulating layers or a pattern formed on a surface of each of the plurality of interlayer insulating layers may be different.
  • An interlayer oxide film, the silicon nitride film, and a tunnel oxide film may be disposed between each of the plurality of electrode layers and the channel layer.
  • 3D flash memory is a channel layer; A plurality of electrode layers connected to the channel layer and stacked vertically; And a plurality of interlayer insulating layers connected to the channel layer, alternately disposed with the plurality of electrode layers, and stacked vertically, wherein each of the plurality of interlayer insulating layers is formed of a different material or is different from each other. It has a physical structure, and each of the plurality of electrode layers is formed of different materials or have different physical structures.
  • Embodiments of the present invention can provide a three-dimensional flash memory and a method of manufacturing the same by improving the threshold voltage distribution of the plurality of electrode layers by different physical structures or materials of the plurality of electrode layers. Therefore, the reliability of the data stored in the three-dimensional flash memory can be improved.
  • embodiments of the present invention by making the physical structure or material of the interlayer insulating layers, as well as the plurality of electrode layers different from each other, the three-dimensional flash memory and its fabrication to uniform the stress level applied to each of the interlayer insulating layers It may provide a method.
  • FIG. 1 shows a general cross-sectional view of a three-dimensional flash memory.
  • FIG. 2 is a cross-sectional view of a three-dimensional flash memory formed of the same material and including a plurality of interlayer insulating layers having a uniform physical structure.
  • FIG. 3 is a cross-sectional view of a three-dimensional flash memory formed of different materials and including a plurality of interlayer insulating layers having a uniform physical structure in accordance with an embodiment of the present invention.
  • FIG. 4 illustrates a cross-sectional view of a three-dimensional flash memory formed of different materials and including a plurality of interlayer insulating layers having different physical structures in accordance with an embodiment of the present invention.
  • FIG. 5 is a cross-sectional view of a three-dimensional flash memory having a uniform physical structure and including a plurality of electrode layers formed of the same material.
  • FIG. 6 is a cross-sectional view of a 3D flash memory having a plurality of electrode layers having different physical structures and formed of the same material according to an embodiment of the present invention.
  • FIG. 7 is a cross-sectional view of a three-dimensional flash memory having a plurality of electrode layers having different physical structures and formed of different materials according to an embodiment of the present invention.
  • FIG. 8 illustrates a storage device including a 3D flash memory according to an embodiment of the present invention.
  • FIG. 9 illustrates a structure of a 3D flash memory having a uniform physical structure and including a plurality of electrode layers formed of the same material.
  • FIG. 10 is a graph illustrating a threshold voltage distribution in the three-dimensional flash memory shown in FIG. 9.
  • FIG. 11 is a graph illustrating threshold voltage distribution in a three-dimensional flash memory according to thicknesses of the plurality of electrode layers.
  • FIG. 1 shows a general cross-sectional view of a three-dimensional flash memory.
  • a 3D flash memory includes a channel layer 110 as a vertical structure. That is, the channel layer 110 is formed perpendicular to the substrate (not shown).
  • the channel layer may be formed of monocrystalline silicon, and for example, may be formed through a selective epitaxial growth process or a phase change epitaxial process using a substrate as a seed.
  • the tunnel oxide layer 120, the silicon nitride layer 130, and the interlayer oxide layer 140 may be formed around the channel layer 110, and the plurality of electrode layers 150 may be vertically stacked. Although not shown in FIG. 1, a plurality of interlayer insulating layers are alternately disposed between the plurality of electrode layers 150.
  • the tunnel oxide film 120, the silicon nitride film 130, and the interlayer oxide film 140 formed around the channel layer 110 may store data by trapping charges.
  • external stress or internal stress occurring in the process of trapping charge or spread of charges over time can cause data disturbance.
  • the external stress or the internal stress generated in the process of trapping the charge acts differently on each of the plurality of interlayer insulating layers. For example, a low level of stress may be applied to the interlayer insulating layer present in the upper layer, and a high level of stress may be applied to the interlayer insulating layer present in the lower layer.
  • the threshold voltage of each of the plurality of electrode layers 150 may be different because current densities flowing through the plurality of electrode layers 150 are different.
  • the electrode layer present in the upper layer may have a high current density
  • the electrode layer present in the lower layer may have a relatively low current density.
  • FIG. 2 is a cross-sectional view of a three-dimensional flash memory formed of the same material and including a plurality of interlayer insulating layers having a uniform physical structure.
  • a low level of stress is applied to an interlayer insulating layer of an upper layer among the plurality of interlayer insulating layers 220 arranged alternately with the plurality of electrode layers 210.
  • a high level of stress is applied to the interlayer insulating layer of the lower layer.
  • embodiments of the present invention propose a material or physical structure of the plurality of interlayer insulating layers 220 to apply a substantially uniform level of stress to each of the plurality of interlayer insulating layers 220.
  • FIG. 3 is a cross-sectional view of a three-dimensional flash memory formed of different materials and including a plurality of interlayer insulating layers having a uniform physical structure in accordance with an embodiment of the present invention.
  • an embodiment of the present invention forms a plurality of interlayer insulating layers 320 disposed between the plurality of electrode layers 310 using different materials.
  • the plurality of interlayer insulating layers 320 may include an interlayer insulating layer 330 of material 1, an interlayer insulating layer 331 of material 2, an interlayer insulating layer 332 of material 3, and an interlayer insulating layer of material 4. 333 may be included.
  • the plurality of interlayer insulating layers 320 are used for the purpose of planarization or insulation, and include a gas material formed by CVD such as SiO 2, DSG (SiOF), TFOS, BPSG, and SOG (Spin-on-Glass / Shirokisan-based) It may include a coating material (SOD) represented by. These various materials may have various material properties in terms of mechanical strength, dielectric constant, dielectric loss, chemical stability, thermal stability, conductivity, and the like, and these characteristics determine durability against internal stress or external stress.
  • an embodiment of the present invention may use a relatively stress-sensitive material for the interlayer insulating layers present in the upper layer of the plurality of interlayer insulating layers 320 and relatively for the interlayer insulating layers present in the lower layer. Stress-resistant materials can be used. Therefore, the level of stress applied to each of the plurality of interlayer insulating layers 320 may be uniform.
  • FIG. 4 illustrates a cross-sectional view of a three-dimensional flash memory formed of different materials and including a plurality of interlayer insulating layers having different physical structures in accordance with an embodiment of the present invention.
  • an embodiment of the present invention uses different materials for each of the plurality of interlayer insulating layers as shown in FIG. 3, while designing different physical structures of each of the plurality of interlayer insulating layers. can do.
  • the physical structure may be determined by the thickness, length, etc. of each of the plurality of interlayer insulating layers.
  • the plurality of interlayer insulating layers include a top interlayer insulating layer, a bottom interlayer insulating layer, and a middle interlayer insulating layer. Therefore, hereinafter, the physical structure of each of the plurality of interlayer insulating layers may be differently designed may mean that the physical structure of each of the plurality of interlayer insulating layers is differently designed.
  • the plurality of interlayer insulating layers 420 respectively present between the plurality of electrode layers 410 may include the interlayer insulating layer 430 of material 1 and the interlayer insulation of material 2.
  • the thicknesses of the interlayer insulating layer 430 of the material 1, the interlayer insulating layer 431 of the material 2, the interlayer insulating layer 432 of the material 3, and the interlayer insulating layer 433 of the material 4 may be different from each other. have.
  • the thickness of the interlayer insulating layer 430 of the material 1 is formed to be thicker than the thickness of the interlayer insulating layer 431 of the material 2, the interlayer insulating layer 432 of the material 3, and the interlayer insulating layer 433 of the material 4. This may make the level of stress applied to each of the plurality of interlayer insulating layers 420 uniform.
  • the physical structure is changed by changing the thickness of each of the plurality of interlayer insulating layers 420, but embodiments of the present invention are formed on the surfaces of each of the plurality of interlayer insulating layers 420 of various lengths. It includes a change in the pattern or the like.
  • the embodiment of the present invention proposes a plurality of interlayer insulating layers 420 having different physical structures as well as being formed of different materials, but is not limited thereto and is formed of the same material.
  • a plurality of interlayer insulating layers 420 having only different physical structures may also be proposed.
  • FIG. 5 is a cross-sectional view of a three-dimensional flash memory having a uniform physical structure and including a plurality of electrode layers formed of the same material.
  • an electrode layer of an upper layer of the plurality of electrode layers 510 may be formed. Since the current density flowing in the electrode layer is different from the current density flowing in the electrode layer of the lower layer, a difference between threshold voltages of each of the plurality of electrode layers 510 may occur.
  • embodiments of the present invention propose a material or physical structure of the plurality of electrode layers 510 to have a substantially uniform threshold voltage for each of the plurality of electrode layers 510.
  • the plurality of interlayer insulating layers 520 alternately arranged with the plurality of electrode layers 510 may have a material or a physical structure to which a substantially uniform level of stress is applied to each of the above-described ones. .
  • FIG. 6 is a cross-sectional view of a 3D flash memory having a plurality of electrode layers having different physical structures and formed of the same material according to an embodiment of the present invention.
  • an embodiment of the present invention may design different physical structures of each of the plurality of electrode layers 610.
  • the physical structure may be determined by the thickness, length, etc. of each of the plurality of electrode layers 610.
  • the plurality of electrode layers 610 may include a top electrode layer, a bottom electrode layer, and a middle electrode layer. Therefore, hereinafter, the physical structure of each of the plurality of electrode layers 610 is differently designed may mean that the physical structure of each of the plurality of intermediate electrode layers is designed differently.
  • the plurality of electrode layers 610 may include an electrode layer 1 620, an electrode layer 2 621, an electrode layer 3 622, and an electrode layer 4 623 having different thicknesses.
  • the thickness of the electrode layer 1 620 may be formed to be thicker than the thickness of the electrode layer 2 621, the electrode layer 3 622, and the electrode layer 4 623, and this may increase the threshold voltage of each of the plurality of electrode layers 610. It can be made uniform.
  • the physical structure is changed by changing the thickness of each of the plurality of electrode layers 610, but embodiments of the present invention vary the length, the pattern formed on the surface of each of the plurality of electrode layers 610, and the like. It includes.
  • the plurality of interlayer insulating layers 630 alternately arranged with the plurality of electrode layers 610 may have a material or a physical structure to which a substantially uniform level of stress is applied, as described above. .
  • FIG. 7 is a cross-sectional view of a three-dimensional flash memory having a plurality of electrode layers having different physical structures and formed of different materials according to an embodiment of the present invention.
  • each of the plurality of electrode layers may be differently designed, but different materials may be used for each of the plurality of electrode layers.
  • the plurality of electrode layers 710 may include an electrode layer 720 of material 1, an electrode layer 721 of material 2, an electrode layer 722 of material 3, and an electrode layer of material 4 ( 723).
  • a material having a relatively low electrical transmission property may be used for an electrode layer existing in an upper layer among the plurality of electrode layers 710, and a relatively electrical transmission property for an electrode layer existing in a lower layer.
  • This excellent material can be used.
  • the electrical transfer properties of the electrode layer 720 of material 1 may be superior to the electrical transfer properties of the electrode layer 723 of material 4. Therefore, the threshold voltage of each of the plurality of electrode layers 710 may be uniform.
  • the plurality of interlayer insulating layers 730 disposed alternately with the plurality of electrode layers 710 may have a material or a physical structure to which a substantially uniform level of stress is applied to each of the above-described ones. .
  • the embodiment of the present invention proposes a plurality of electrode layers 710 having different physical structures and formed of different materials, the present invention is not limited thereto and is not limited thereto. A plurality of electrode layers 710 formed only as well may also be proposed.
  • FIG. 8 illustrates a storage device including a 3D flash memory according to an embodiment of the present invention.
  • the memory 810 refers to the above-described three-dimensional flash memory.
  • the memory 810 may be not only a NAND flash memory but also a Arthur flash memory to which the spirit of the present invention is applied.
  • the memory controller 820 provides an input signal to control the operation of the memory 810.
  • the system 500 controls input / output data by transmitting a command of a host when the memory controller used in the memory card is related to the memory, or controls various data in the memory based on an authorized control signal.
  • This structure is applied not only to simple memory cards but also to many digital devices that use memory, and applies to all digital devices that need memory such as portable digital cameras and mobile phones.
  • FIG. 9 illustrates a structure of a 3D flash memory having a uniform physical structure and including a plurality of electrode layers formed of the same material.
  • a 3D flash memory is a NAND flash memory having a structure in which cell transistors are connected in series to form a unit string, and the unit strings are connected in parallel between a bit line and a ground line.
  • the current density becomes weaker as the lower portion of the string decreases.
  • FIG. 10 as shown in FIG. 9B, the number of stacks of cells included in the string is changed to 10, 30, and 50 stages, respectively, and the program bias of 10V is applied to the upper and lower cells, respectively.
  • FIG. 10 is a graph illustrating a threshold voltage distribution in the three-dimensional flash memory shown in FIG. 9.
  • the top and bottom drain currents 1030 and 1040 when the number of stacked cells is 30 stages are reduced than the top and bottom drain currents 1010 and 1020 when the number of cells stacked is 10 stages.
  • the drain currents 1050 and 1060 of the top and bottom when the number of stacked cells is 50 stages are lower than the drain currents 1030 and 1040 of the top and the bottom when the number of stacked cells is 30 stages.
  • Table 1 10-speed cell 30-speed cell 50-speed cell top bottom top bottom top bottom Saturation Drain Current [A] 3.69E-05 3.69E-05 3.69E-05 3.69E-05 3.69E-05 3.69E-05 3.69E-05 Vt [V] 0.7247 0.6549 0.6530 0.5080 0.4715 0.2633 ⁇ Vt [V] 0.0698 0.1450 0.2082
  • FIG. 11 is a graph illustrating threshold voltage distribution in a three-dimensional flash memory according to thicknesses of the plurality of electrode layers.
  • the threshold voltage distributions according to the changed thicknesses are compared.
  • each of the plurality of electrode layers is fixed to 40 nm as shown in (a), it can be seen that the difference between the threshold voltages 1110 and 1120 between the upper electrode layer and the lower electrode layer among the plurality of electrode layers is 0.2082.
  • the thickness of each of the plurality of electrode layers is increased as the thickness of the upper electrode layer increases. It can be seen that the difference between the threshold voltages 1130 and 1140 between the electrode layer and the lower electrode layer is 0.3918.
  • the thickness of each of the plurality of electrode layers decreases as the upper portion is increased, the upper electrode layer among the plurality of electrode layers. It can be seen that the difference between the threshold voltages 1150 and 1160 between the electrode layer and the lower electrode layer is -0.2198.
  • the thickness of each of the plurality of electrode layers decreases as the upper portion is increased, the upper electrode layer among the plurality of electrode layers. It can be seen that the difference between the threshold voltages 1170 and 1180 between the electrode layer and the lower electrode layer is 0.0039.
  • the threshold voltage distribution can be improved by forming the thickness of each of the plurality of electrode layers as the thickness becomes lower. Therefore, the physical structure of each of the plurality of electrode layers is differently designed such that the thickness of the first electrode layer among the plurality of electrode layers is thicker than the thickness of the second electrode layer existing on the upper layer of the first electrode layer. Can improve their threshold voltage distribution.

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Abstract

Embodiments of the present invention enable threshold voltage distribution of a plurality of electrode layers to be improved by configuring each of the plurality of electrode layers to have different physical structures or materials, etc., thereby enhancing credibility during a process of maintaining stored data and a reading process.

Description

서로 다른 특성을 갖는 전극층 및/또는 층간 절연층을 이용하는 3차원 플래시 메모리 및 그 제작 방법3D flash memory using an electrode layer and / or an interlayer insulating layer having different characteristics and a manufacturing method thereof
본 발명은 서로 다른 특성을 갖는 전극층 및/또는 층간 절연층을 이용하는 3차원 플래시 메모리 및 그 제작 방법에 관한 것으로서, 구체적으로, 복수의 전극층들 각각을 서로 다른 특성을 갖도록 하거나, 복수의 층간 절연층들 각각을 서로 다른 특성을 갖도록 함으로써, 복수의 전극층들의 문턱 전압 산포를 개선하고, 복수의 층간 절연층들 각각에 가해지는 스트레스 레벨을 균일하게 하는 3차원 플래시 메모리 및 그 제작 방법에 관한 기술이다.The present invention relates to a three-dimensional flash memory using an electrode layer and / or an interlayer insulating layer having different characteristics, and to a method of manufacturing the same. Specifically, each of the plurality of electrode layers has different characteristics or a plurality of interlayer insulating layers. A three-dimensional flash memory and a method of manufacturing the same which improve the threshold voltage distribution of a plurality of electrode layers and make the stress level applied to each of the plurality of interlayer insulating layers by having each of them have different characteristics.
플래시 메모리 소자는 전기적으로 소거가능하며 프로그램가능한 판독 전용 메모리(Electrically Erasable Programmable Read Only Memory :EEPROM)로서, 그 메모리는, 예를 들어, 컴퓨터, 디지털 카메라, MP3 플레이어, 게임 시스템, 메모리 스틱(memory stick) 등에 공통적으로 이용될 수 있다. 상기 플래시 메모리 소자는 F-N 터널링(Fowler-Nordheimtunneling) 또는 열전자 주입(hot electron injection)에 의해 전기적으로 데이터의 입?출력을 제어한다.Flash memory devices are electrically erasable programmable read only memory (EEPROM), which may be, for example, a computer, a digital camera, an MP3 player, a game system, a memory stick. ) May be commonly used. The flash memory device electrically controls input and output of data by F-N tunneling or hot electron injection.
상기 플래시 메모리 소자를 회로적 관점에서 살펴보면, N개의 셀 트랜지스터들이 직렬로 연결되어 단위 스트링(string)을 이루고 이러한 단위 스트링들이 비트 라인(bit line)과 접지 라인(ground line) 사이에 병렬로 연결되어 있는 구조를 갖는 NAND형 플래시 메모리 소자와, 각각의 셀 트랜지스터들이 비트 라인과 접지 라인 사이에 병렬로 연결되어 있는 구조를 갖는 NOR형 플래시 메모리 소자가 존재한다.Looking at the flash memory device from a circuit point of view, N cell transistors are connected in series to form a unit string, and the unit strings are connected in parallel between a bit line and a ground line. There is a NAND-type flash memory device having a structure in which the cell transistors are connected in parallel between the bit line and the ground line.
상기 플래시 메모리 소자는 고용량의 데이터를 저장할 수 있도록 설계되어야 한다. 그러므로, 단위 칩 내에는 다수의 셀 트랜지스터가 형성되어야 한다. 그러나, 한정된 수평 면적 내에 셀 트랜지스터들을 고도로 집적시키는 것이 용이하지 않다.The flash memory device should be designed to store high capacity data. Therefore, a plurality of cell transistors must be formed in the unit chip. However, it is not easy to highly integrate cell transistors within a limited horizontal area.
3차원 메모리 구조는 낸드 플래시 메모리(NAND Flash Memory)의 2차원상 스케일링(Scaling)의 한계를 개선한다. 3차원 낸드 플래시 메모리의 구조는 예를 들어, BICS(Built-In Current Sensor) 구조 및 BICS 구조를 개선한 파이프 형식(Piped Type)의 BiCS(Bit Cost Scalable) 낸드 플래시 메모리 구조를 포함한다.The three-dimensional memory structure improves the limitation of two-dimensional scaling of NAND flash memory. The structure of the three-dimensional NAND flash memory includes, for example, a BICS (Built-In Current Sensor) structure and a pipe type (BiP Type) Bit Cost Scalable (BIC) NAND flash memory structure having an improved BICS structure.
본 발명의 실시예들은 복수의 전극층들의 물리적 구조 혹은 재료 등을 서로 다르게 함으로써, 복수의 전극층들의 문턱 전압 산포를 개선한 3차원 플래시 메모리 및 그 제작 방법을 제공한다.Embodiments of the present invention provide a three-dimensional flash memory and a method of manufacturing the same by improving the threshold voltage distribution of the plurality of electrode layers by different physical structures or materials of the plurality of electrode layers.
또한, 본 발명의 실시예들은 복수의 전극층들 뿐만 아니라, 층간 절연층들의 물리적 구조 혹은 재료 등을 서로 다르게 함으로써, 층간 절연층들 각각에 가해지는 스트레스 레벨을 균일하게 한 3차원 플래시 메모리 및 그 제작 방법을 제공한다.In addition, embodiments of the present invention, by making the physical structure or material of the interlayer insulating layers, as well as the plurality of electrode layers different from each other, the three-dimensional flash memory and its fabrication to uniform the stress level applied to each of the interlayer insulating layers Provide a method.
본 발명의 일실시예에 따른 3차원 플래시 메모리는 채널층; 상기 채널층과 연결되고, 수직적으로 적층되는 복수의 전극층들; 및 상기 채널층과 연결되고, 상기 복수의 전극층들과 교대로 배치되며, 수직적으로 적층되는 복수의 층간 절연층들을 포함하고, 상기 복수의 전극층들 각각은 서로 다른 물리적인 구조를 갖거나, 서로 다른 물질로 형성된다.3D flash memory according to an embodiment of the present invention is a channel layer; A plurality of electrode layers connected to the channel layer and stacked vertically; And a plurality of interlayer insulating layers connected to the channel layer, alternately disposed with the plurality of electrode layers, and stacked vertically, wherein each of the plurality of electrode layers has a different physical structure or is different from each other. It is formed of a substance.
상기 복수의 전극층들 중 제1 전극층의 두께는 상기 제1 전극층의 상층에 존재하는 제2 전극층의 두께보다 두껍게 형성될 수 있다.The thickness of the first electrode layer among the plurality of electrode layers may be thicker than the thickness of the second electrode layer existing on the upper layer of the first electrode layer.
상기 복수의 전극층들 각각의 길이 또는 상기 복수의 전극층들 각각의 표면에 형성되는 패턴은 서로 다를 수 있다.The length of each of the plurality of electrode layers or the pattern formed on the surface of each of the plurality of electrode layers may be different.
상기 복수의 전극층들 중 제1 전극층을 형성하는 재료는 상기 제1 전극층의 상층에 존재하는 제2 전극층의 재료보다 우수한 전기적인 전달 특성을 가질 수 있다.The material forming the first electrode layer among the plurality of electrode layers may have better electrical transfer characteristics than the material of the second electrode layer existing on the upper layer of the first electrode layer.
상기 복수의 전극층들 중 적어도 두 개의 전극층들 각각은 서로 다른 물질로 형성될 수 있다.Each of the at least two electrode layers of the plurality of electrode layers may be formed of different materials.
상기 복수의 전극층들 각각과 상기 채널층 사이에는 인터레이어 산화막, 상기 실리콘 질화막 및 터널 산화막이 배치될 수 있다.An interlayer oxide film, the silicon nitride film, and a tunnel oxide film may be disposed between each of the plurality of electrode layers and the channel layer.
본 발명의 다른 일실시예에 따른 3차원 플래시 메모리는 채널층; 상기 채널층과 연결되고, 수직적으로 적층되는 복수의 전극층들; 및 상기 채널층과 연결되고, 상기 복수의 전극층들과 교대로 배치되며, 수직적으로 적층되는 복수의 층간 절연층들을 포함하고, 상기 복수의 층간 절연층들 각각은 서로 다른 물질로 형성되거나, 서로 다른 물리적인 구조를 갖는다.3D flash memory according to another embodiment of the present invention is a channel layer; A plurality of electrode layers connected to the channel layer and stacked vertically; And a plurality of interlayer insulating layers connected to the channel layer, alternately disposed with the plurality of electrode layers, and stacked vertically, wherein each of the plurality of interlayer insulating layers is formed of a different material or is different from each other. It has a physical structure.
상기 복수의 층간 절연층들 중 제1 층간 절연층을 형성하는 재료는 상기 제1 층간 절연층의 상층에 존재하는 제2 층간 절연층의 재료보다 스트레스에 강한 특성을 가질 수 있다.The material forming the first interlayer insulating layer among the plurality of interlayer insulating layers may have a property that is stronger in stress than the material of the second interlayer insulating layer existing on the first interlayer insulating layer.
상기 복수의 층간 절연층들 중 적어도 두 개의 층간 절연층들은 서로 다른 물질로 형성될 수 있다.At least two interlayer insulating layers of the plurality of interlayer insulating layers may be formed of different materials.
상기 복수의 층간 절연층들 중 제1 층간 절연층의 두께는 상기 제1 층간 절연층의 상층에 존재하는 제2 층간 절연층의 두께보다 두껍게 형성될 수 있다.The thickness of the first interlayer insulating layer of the plurality of interlayer insulating layers may be thicker than the thickness of the second interlayer insulating layer on the upper layer of the first interlayer insulating layer.
상기 복수의 층간 절연층들 각각의 길이 또는 상기 복수의 층간 절연층들 각각의 표면에 형성되는 패턴은 서로 다를 수 있다.A length of each of the plurality of interlayer insulating layers or a pattern formed on a surface of each of the plurality of interlayer insulating layers may be different.
상기 복수의 전극층들 각각과 상기 채널층 사이에는 인터레이어 산화막, 상기 실리콘 질화막 및 터널 산화막이 배치될 수 있다.An interlayer oxide film, the silicon nitride film, and a tunnel oxide film may be disposed between each of the plurality of electrode layers and the channel layer.
본 발명의 또 다른 일실시예에 따른 3차원 플래시 메모리는 채널층; 상기 채널층과 연결되고, 수직적으로 적층되는 복수의 전극층들; 및 상기 채널층과 연결되고, 상기 복수의 전극층들과 교대로 배치되며, 수직적으로 적층되는 복수의 층간 절연층들을 포함하고, 상기 복수의 층간 절연층들 각각은 서로 다른 물질로 형성되거나, 서로 다른 물리적인 구조를 가지며, 상기 복수의 전극층들 각각은 서로 다른 물질로 형성되거나, 서로 다른 물리적인 구조를 갖는다.3D flash memory according to another embodiment of the present invention is a channel layer; A plurality of electrode layers connected to the channel layer and stacked vertically; And a plurality of interlayer insulating layers connected to the channel layer, alternately disposed with the plurality of electrode layers, and stacked vertically, wherein each of the plurality of interlayer insulating layers is formed of a different material or is different from each other. It has a physical structure, and each of the plurality of electrode layers is formed of different materials or have different physical structures.
본 발명의 실시예들은 복수의 전극층들의 물리적 구조 혹은 재료 등을 서로 다르게 함으로써, 복수의 전극층들의 문턱 전압 산포를 개선한 3차원 플래시 메모리 및 그 제작 방법을 제공할 수 있다. 따라서, 3차원 플래시 메모리에 저장된 데이터의 신뢰도를 향상시킬 수 있다.Embodiments of the present invention can provide a three-dimensional flash memory and a method of manufacturing the same by improving the threshold voltage distribution of the plurality of electrode layers by different physical structures or materials of the plurality of electrode layers. Therefore, the reliability of the data stored in the three-dimensional flash memory can be improved.
또한, 본 발명의 실시예들은 복수의 전극층들 뿐만 아니라, 층간 절연층들의 물리적 구조 혹은 재료 등을 서로 다르게 함으로써, 층간 절연층들 각각에 가해지는 스트레스 레벨을 균일하게 한 3차원 플래시 메모리 및 그 제작 방법을 제공할 수 있다.In addition, embodiments of the present invention, by making the physical structure or material of the interlayer insulating layers, as well as the plurality of electrode layers different from each other, the three-dimensional flash memory and its fabrication to uniform the stress level applied to each of the interlayer insulating layers It may provide a method.
도 1은 3차원 플래시 메모리의 일반적인 단면도를 나타낸다.1 shows a general cross-sectional view of a three-dimensional flash memory.
도 2는 동일한 물질로 형성되고, 균일한 물리적 구조를 갖는 복수의 층간 절연층들을 포함하는 3차원 플래시 메모리의 단면도를 나타낸다.2 is a cross-sectional view of a three-dimensional flash memory formed of the same material and including a plurality of interlayer insulating layers having a uniform physical structure.
도 3은 본 발명의 실시예에 따라 서로 다른 물질로 형성되고, 균일한 물리적 구조를 갖는 복수의 층간 절연층들을 포함하는 3차원 플래시 메모리의 단면도를 나타낸다.3 is a cross-sectional view of a three-dimensional flash memory formed of different materials and including a plurality of interlayer insulating layers having a uniform physical structure in accordance with an embodiment of the present invention.
도 4는 본 발명의 실시예에 따라 서로 다른 물질로 형성되고, 서로 다른 물리적 구조를 갖는 복수의 층간 절연층들을 포함하는 3차원 플래시 메모리의 단면도를 나타낸다.4 illustrates a cross-sectional view of a three-dimensional flash memory formed of different materials and including a plurality of interlayer insulating layers having different physical structures in accordance with an embodiment of the present invention.
도 5는 균일한 물리적 구조를 갖고, 동일한 물질로 형성되는 복수의 전극층들을 포함하는 3차원 플래시 메모리의 단면도를 나타낸다.5 is a cross-sectional view of a three-dimensional flash memory having a uniform physical structure and including a plurality of electrode layers formed of the same material.
도 6은 본 발명의 실시예에 따라 서로 다른 물리적 구조를 갖고, 동일한 물질로 형성되는 복수의 전극층들을 포함하는 3차원 플래시 메모리의 단면도를 나타낸다.6 is a cross-sectional view of a 3D flash memory having a plurality of electrode layers having different physical structures and formed of the same material according to an embodiment of the present invention.
도 7은 본 발명의 실시예에 따라 서로 다른 물리적 구조를 갖고, 서로 다른 물질로 형성되는 복수의 전극층들을 포함하는 3차원 플래시 메모리의 단면도를 나타낸다.7 is a cross-sectional view of a three-dimensional flash memory having a plurality of electrode layers having different physical structures and formed of different materials according to an embodiment of the present invention.
도 8은 본 발명의 일실시예에 따른 3차원 플래시 메모리를 포함하는 저장 장치를 나타낸 도면이다.8 illustrates a storage device including a 3D flash memory according to an embodiment of the present invention.
도 9는 균일한 물리적 구조를 갖고, 동일한 물질로 형성되는 복수의 전극층들을 포함하는 3차원 플래시 메모리의 구조를 나타낸 도면이다.FIG. 9 illustrates a structure of a 3D flash memory having a uniform physical structure and including a plurality of electrode layers formed of the same material.
도 10은 도 9에 도시된 3차원 플래시 메모리에서 문턱 전압 산포를 나타낸 그래프이다.FIG. 10 is a graph illustrating a threshold voltage distribution in the three-dimensional flash memory shown in FIG. 9.
도 11은 복수의 전극층들 각각의 두께에 따른 3차원 플래시 메모리에서 문턱 전압 산포를 나타낸 그래프들이다.FIG. 11 is a graph illustrating threshold voltage distribution in a three-dimensional flash memory according to thicknesses of the plurality of electrode layers.
이하, 본 발명에 따른 실시예들을 첨부된 도면을 참조하여 상세하게 설명한다. 그러나 본 발명이 실시예들에 의해 제한되거나 한정되는 것은 아니다. 또한, 각 도면에 제시된 동일한 참조 부호는 동일한 부재를 나타낸다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or limited by the embodiments. Also, like reference numerals in the drawings denote like elements.
도 1은 3차원 플래시 메모리의 일반적인 단면도를 나타낸다.1 shows a general cross-sectional view of a three-dimensional flash memory.
도 1을 참조하면, 3차원 플래시 메모리는 수직 구조물로서 채널층(110)을 포함한다. 즉, 채널층(110)은 기판(미도시)에 대하여 수직적으로 형성된다. 여기서, 채널층은 단결정질의 실리콘으로 형성될 수 있으며, 예를 들어 기판을 시드로 이용하는 선택적 에피택셜 성장 공정 또는 상전이 에피택셜 공정 등을 통하여 형성될 수 있다.Referring to FIG. 1, a 3D flash memory includes a channel layer 110 as a vertical structure. That is, the channel layer 110 is formed perpendicular to the substrate (not shown). Here, the channel layer may be formed of monocrystalline silicon, and for example, may be formed through a selective epitaxial growth process or a phase change epitaxial process using a substrate as a seed.
채널층(110) 주변에는 터널 산화막(120), 실리콘 질화막(130), 인터레이어 산화막(140)이 형성될 수 있으며, 복수의 전극층들(150)은 수직적으로 적층된다. 그리고, 도 1에 도시되지 아니하였지만, 복수의 전극층들(150) 사이에는 복수의 층간 절연층들이 교대로 배치된다.The tunnel oxide layer 120, the silicon nitride layer 130, and the interlayer oxide layer 140 may be formed around the channel layer 110, and the plurality of electrode layers 150 may be vertically stacked. Although not shown in FIG. 1, a plurality of interlayer insulating layers are alternately disposed between the plurality of electrode layers 150.
아래에서 상세히 설명하겠지만, 채널층(110) 주변에 형성된 터널 산화막(120), 실리콘 질화막(130), 인터레이어 산화막(140)은 전하를 트래핑함으로써 데이터를 저장할 수 있다. 그러나, 전하를 트래핑하는 과정에서 발생하는 외적인 스트레스 혹은 내적인 스트레스 또는 시간의 경과에 따른 전하들의 확산은 데이터 교란을 발생시킬 수 있다. 이 때, 전하를 트래핑하는 과정에서 발생하는 외적인 스트레스 혹은 내적인 스트레스는 복수의 층간 절연층들 각각에 다르게 작용한다. 예를 들어, 상층부에 존재하는 층간 절연층에는 낮은 레벨의 스트레스가 가해질 수 있고, 하층부에 존재하는 층간 절연층에는 높은 레벨의 스트레스가 가해질 수 있다.As will be described in detail below, the tunnel oxide film 120, the silicon nitride film 130, and the interlayer oxide film 140 formed around the channel layer 110 may store data by trapping charges. However, external stress or internal stress occurring in the process of trapping charge or spread of charges over time can cause data disturbance. At this time, the external stress or the internal stress generated in the process of trapping the charge acts differently on each of the plurality of interlayer insulating layers. For example, a low level of stress may be applied to the interlayer insulating layer present in the upper layer, and a high level of stress may be applied to the interlayer insulating layer present in the lower layer.
또한, 3차원 플래시 메모리의 채널층(110)의 저항률은 위치에 따라 다르기 때문에 복수의 전극층들(150) 각각의 문턱 전압의 차이가 발생되어 문턱 전압 산포가 확산될 수 있다. 이와 같은, 문턱 전압 산포의 확산은 저장된 데이터를 유지하는 과정 및 판독 과정에서의 신뢰도를 하락시킬 수 있다. 이 때, 복수의 전극층들(150) 각각의 문턱 전압은 복수의 전극층들(150) 각각에 흐르는 전류밀도가 다르기 때문에, 차이가 발생될 수 있다. 예를 들어, 상층부에 존재하는 전극층은 높은 전류밀도를 가질 수 있고, 하층부에 존재하는 전극층은 상대적으로 낮은 전류밀도를 가질 수 있다.In addition, since the resistivity of the channel layer 110 of the 3D flash memory varies depending on the position, a difference in threshold voltages of the plurality of electrode layers 150 may occur, thereby spreading the threshold voltage distribution. Such spreading of the threshold voltage distribution can degrade the reliability in the process of holding and reading the stored data. At this time, the threshold voltage of each of the plurality of electrode layers 150 may be different because current densities flowing through the plurality of electrode layers 150 are different. For example, the electrode layer present in the upper layer may have a high current density, and the electrode layer present in the lower layer may have a relatively low current density.
도 2는 동일한 물질로 형성되고, 균일한 물리적 구조를 갖는 복수의 층간 절연층들을 포함하는 3차원 플래시 메모리의 단면도를 나타낸다.2 is a cross-sectional view of a three-dimensional flash memory formed of the same material and including a plurality of interlayer insulating layers having a uniform physical structure.
도 2를 참조하면, 3차원 플래시 메모리의 구조적인 문제로 인하여, 복수의 전극층들(210)과 교대로 배치되는 복수의 층간 절연층들(220) 중 상층부의 층간 절연층에는 낮은 레벨의 스트레스가 작용하는 반면에, 하층부의 층간 절연층에는 높은 레벨의 스트레스가 작용한다.Referring to FIG. 2, due to a structural problem of a 3D flash memory, a low level of stress is applied to an interlayer insulating layer of an upper layer among the plurality of interlayer insulating layers 220 arranged alternately with the plurality of electrode layers 210. On the other hand, a high level of stress is applied to the interlayer insulating layer of the lower layer.
이와 같이, 복수의 층간 절연층들(220) 각각마다 서로 다른 레벨의 스트레스가 작용하는 것은 저장된 데이터의 신뢰성을 낮추는 원인이 될 수 있다. 따라서, 본 발명의 실시예들은 복수의 층간 절연층들(220) 각각마다 실질적으로 균일한 레벨의 스트레스가 적용할 수 있도록 복수의 층간 절연층들(220)의 재료 또는 물리적인 구조를 제안한다.As such, a different level of stress acting on each of the plurality of interlayer insulating layers 220 may cause a lower reliability of stored data. Accordingly, embodiments of the present invention propose a material or physical structure of the plurality of interlayer insulating layers 220 to apply a substantially uniform level of stress to each of the plurality of interlayer insulating layers 220.
도 3은 본 발명의 실시예에 따라 서로 다른 물질로 형성되고, 균일한 물리적 구조를 갖는 복수의 층간 절연층들을 포함하는 3차원 플래시 메모리의 단면도를 나타낸다.3 is a cross-sectional view of a three-dimensional flash memory formed of different materials and including a plurality of interlayer insulating layers having a uniform physical structure in accordance with an embodiment of the present invention.
도 3을 참조하면, 본 발명의 실시예는 복수의 전극층들(310) 사이에 각각 배치되는 복수의 층간 절연층들(320)을 서로 다른 물질을 이용하여 형성한다. 예를 들어, 복수의 층간 절연층들(320)은 물질 1의 층간 절연층(330), 물질 2의 층간 절연층(331), 물질 3의 층간 절연층(332) 및 물질 4의 층간 절연층(333)을 포함할 수 있다.Referring to FIG. 3, an embodiment of the present invention forms a plurality of interlayer insulating layers 320 disposed between the plurality of electrode layers 310 using different materials. For example, the plurality of interlayer insulating layers 320 may include an interlayer insulating layer 330 of material 1, an interlayer insulating layer 331 of material 2, an interlayer insulating layer 332 of material 3, and an interlayer insulating layer of material 4. 333 may be included.
복수의 층간 절연층들(320)은 평탄화 혹은 절연을 목적으로 사용되며, SiO2, DSG(SiOF), TFOS, BPSG 등의 CVD로 성막되는 가스재료와, SOG(스핀온글라 스/시로키산계)로 대표되는 도포재료(SOD) 등을 포함할 수 있다. 이러한 다양한 재료들은 기계적 강도, 유전상수, 유전 손실, 화학적 안정도, 열적 안정성, 도전율 등에서 다양한 재료적인 특성을 가질 수 있으며, 이러한 특성은 내적인 스트레스 혹은 외부의 스트레스에 대한 내구도를 결정한다.The plurality of interlayer insulating layers 320 are used for the purpose of planarization or insulation, and include a gas material formed by CVD such as SiO 2, DSG (SiOF), TFOS, BPSG, and SOG (Spin-on-Glass / Shirokisan-based) It may include a coating material (SOD) represented by. These various materials may have various material properties in terms of mechanical strength, dielectric constant, dielectric loss, chemical stability, thermal stability, conductivity, and the like, and these characteristics determine durability against internal stress or external stress.
이 때, 본 발명의 실시예는 복수의 층간 절연층들(320) 중 상층부에 존재하는 층간 절연층들을 위해서는 상대적으로 스트레스에 약한 재료를 사용할 수 있고, 하층부에 존재하는 층간 절연층들을 위해서는 상대적으로 스트레스에 강인한 재료를 사용할 수 있다. 따라서, 복수의 층간 절연층들(320) 각각에 가해지는 스트레스의 레벨이 균일하게 될 수 있다.In this case, an embodiment of the present invention may use a relatively stress-sensitive material for the interlayer insulating layers present in the upper layer of the plurality of interlayer insulating layers 320 and relatively for the interlayer insulating layers present in the lower layer. Stress-resistant materials can be used. Therefore, the level of stress applied to each of the plurality of interlayer insulating layers 320 may be uniform.
도 4는 본 발명의 실시예에 따라 서로 다른 물질로 형성되고, 서로 다른 물리적 구조를 갖는 복수의 층간 절연층들을 포함하는 3차원 플래시 메모리의 단면도를 나타낸다.4 illustrates a cross-sectional view of a three-dimensional flash memory formed of different materials and including a plurality of interlayer insulating layers having different physical structures in accordance with an embodiment of the present invention.
도 4를 참조하면, 본 발명의 실시예는 도 3에 도시된 바와 같이 복수의 층간 절연층들 각각을 위하여 서로 다른 물질을 사용하면서도, 복수의 층간 절연층들 각각의 물리적인 구조를 서로 다르게 설계할 수 있다. 여기서, 물리적인 구조는 복수의 층간 절연층들 각각의 두께, 길이 등에 의하여 결정될 수 있다. 이 때, 복수의 층간 절연층들은 최상위 층간 절연층, 최하위 층간 절연층 및 중간 층간 절연층들을 포함한다. 따라서, 이하, 복수의 층간 절연층들 각각의 물리적인 구조가 서로 다르게 설계된다는 것은 복수의 중간 층간 절연층들 각각의 물리적인 구조가 서로 다르게 설계되는 것을 의미할 수 있다.Referring to FIG. 4, an embodiment of the present invention uses different materials for each of the plurality of interlayer insulating layers as shown in FIG. 3, while designing different physical structures of each of the plurality of interlayer insulating layers. can do. Here, the physical structure may be determined by the thickness, length, etc. of each of the plurality of interlayer insulating layers. In this case, the plurality of interlayer insulating layers include a top interlayer insulating layer, a bottom interlayer insulating layer, and a middle interlayer insulating layer. Therefore, hereinafter, the physical structure of each of the plurality of interlayer insulating layers may be differently designed may mean that the physical structure of each of the plurality of interlayer insulating layers is differently designed.
다시 도 4를 참조하면, 본 발명의 실시예는 복수의 전극층들(410) 사이에 각각 존재하는 복수의 층간 절연층들(420)은 물질 1의 층간 절연층(430), 물질 2의 층간 절연층(431), 물질 3의 층간 절연층(432) 및 물질 4의 층간 절연층(433)을 포함할 수 있다. 이 때, 물질 1의 층간 절연층(430), 물질 2의 층간 절연층(431), 물질 3의 층간 절연층(432) 및 물질 4의 층간 절연층(433) 각각의 두께는 서로 다르게 결정될 수 있다. 예를 들어, 물질 1의 층간 절연층(430)의 두께는 물질 2의 층간 절연층(431), 물질 3의 층간 절연층(432) 및 물질 4의 층간 절연층(433)의 두께보다 두껍게 형성될 수 있으며, 이것은 복수의 층간 절연층들(420) 각각에 가해지는 스트레스의 레벨을 균일하게 할 수 있다.Referring back to FIG. 4, according to an embodiment of the present invention, the plurality of interlayer insulating layers 420 respectively present between the plurality of electrode layers 410 may include the interlayer insulating layer 430 of material 1 and the interlayer insulation of material 2. Layer 431, interlayer dielectric layer 432 of material 3, and interlayer dielectric layer 433 of material 4. In this case, the thicknesses of the interlayer insulating layer 430 of the material 1, the interlayer insulating layer 431 of the material 2, the interlayer insulating layer 432 of the material 3, and the interlayer insulating layer 433 of the material 4 may be different from each other. have. For example, the thickness of the interlayer insulating layer 430 of the material 1 is formed to be thicker than the thickness of the interlayer insulating layer 431 of the material 2, the interlayer insulating layer 432 of the material 3, and the interlayer insulating layer 433 of the material 4. This may make the level of stress applied to each of the plurality of interlayer insulating layers 420 uniform.
도 4에서 복수의 층간 절연층들(420) 각각의 두께의 변화를 통하여 물리적 구조의 변경을 설명하였지만, 본 발명의 실시예들은 다양한 길이, 복수의 층간 절연층들(420) 각각의 표면에 형성되는 패턴 등의 변화를 포함한다.In FIG. 4, the physical structure is changed by changing the thickness of each of the plurality of interlayer insulating layers 420, but embodiments of the present invention are formed on the surfaces of each of the plurality of interlayer insulating layers 420 of various lengths. It includes a change in the pattern or the like.
이와 같이, 본 발명의 실시예는 서로 다른 물질로 형성될 뿐만 아니라, 서로 다른 물리적 구조를 갖는 복수의 층간 절연층들(420)을 제안하고 있으나, 이에 제한되거나 한정되지 않고, 동일한 물질로 형성되면서 서로 다른 물리적 구조만을 갖는 복수의 층간 절연층들(420) 역시 제안할 수 있다.As described above, the embodiment of the present invention proposes a plurality of interlayer insulating layers 420 having different physical structures as well as being formed of different materials, but is not limited thereto and is formed of the same material. A plurality of interlayer insulating layers 420 having only different physical structures may also be proposed.
도 5는 균일한 물리적 구조를 갖고, 동일한 물질로 형성되는 복수의 전극층들을 포함하는 3차원 플래시 메모리의 단면도를 나타낸다.5 is a cross-sectional view of a three-dimensional flash memory having a uniform physical structure and including a plurality of electrode layers formed of the same material.
도 5를 참조하면, 3차원 플래시 메모리의 구조적인 문제(예컨대, 3차원 플래시 메모리에 포함되는 채널층의 저항률이 위치에 따라 변화되는 문제)로 인하여, 복수의 전극층들(510) 중 상층부의 전극층에 흐르는 전류밀도가 하층부의 전극층에 흐르는 전류밀도와 다르기 때문에, 복수의 전극층들(510) 각각의 문턱 전압 사이의 차이가 발생될 수 있다.Referring to FIG. 5, due to a structural problem of the 3D flash memory (for example, a problem in that the resistivity of the channel layer included in the 3D flash memory varies depending on a location), an electrode layer of an upper layer of the plurality of electrode layers 510 may be formed. Since the current density flowing in the electrode layer is different from the current density flowing in the electrode layer of the lower layer, a difference between threshold voltages of each of the plurality of electrode layers 510 may occur.
이와 같이, 복수의 전극층들(510) 각각의 문턱 전압의 차이는 문턱 전압 산포의 확산을 가져오고, 문턱 전압의 확산은 저장된 데이터를 유지하는 과정 및 판독 과정에서의 신뢰성을 낮추는 원인이 될 수 있다. 따라서, 본 발명의 실시예들은 복수의 전극층들(510) 각각마다 실질적으로 균일한 문턱 전압을 갖도록 복수의 전극층들(510)의 재료 또는 물리적인 구조를 제안한다. 이 때, 복수의 전극층들(510)과 교대로 배치되는 복수의 층간 절연층들(520)은 위에서 상술한, 각각마다 실질적으로 균일한 레벨의 스트레스가 적용되는 재료 또는 물리적인 구조를 가질 수도 있다.As such, the difference in the threshold voltages of the plurality of electrode layers 510 may lead to the spread of the threshold voltage distribution, and the spread of the threshold voltage may cause the reliability of the stored data and the reading process to be lowered. . Accordingly, embodiments of the present invention propose a material or physical structure of the plurality of electrode layers 510 to have a substantially uniform threshold voltage for each of the plurality of electrode layers 510. In this case, the plurality of interlayer insulating layers 520 alternately arranged with the plurality of electrode layers 510 may have a material or a physical structure to which a substantially uniform level of stress is applied to each of the above-described ones. .
도 6은 본 발명의 실시예에 따라 서로 다른 물리적 구조를 갖고, 동일한 물질로 형성되는 복수의 전극층들을 포함하는 3차원 플래시 메모리의 단면도를 나타낸다.6 is a cross-sectional view of a 3D flash memory having a plurality of electrode layers having different physical structures and formed of the same material according to an embodiment of the present invention.
도 6을 참조하면, 본 발명의 실시예는 복수의 전극층들(610) 각각의 물리적인 구조를 서로 다르게 설계할 수 있다. 여기서, 물리적인 구조는 복수의 전극층들(610) 각각의 두께, 길이 등에 의하여 결정될 수 있다. 이 때, 복수의 전극층들(610)은 최상위 전극층, 최하위 전극층 및 중간 전극층들을 포함한다. 따라서, 이하, 복수의 전극층들(610) 각각의 물리적인 구조가 서로 다르게 설계된다는 것은 복수의 중간 전극층들 각각의 물리적인 구조가 서로 다르게 설계되는 것을 의미할 수 있다.Referring to FIG. 6, an embodiment of the present invention may design different physical structures of each of the plurality of electrode layers 610. Here, the physical structure may be determined by the thickness, length, etc. of each of the plurality of electrode layers 610. In this case, the plurality of electrode layers 610 may include a top electrode layer, a bottom electrode layer, and a middle electrode layer. Therefore, hereinafter, the physical structure of each of the plurality of electrode layers 610 is differently designed may mean that the physical structure of each of the plurality of intermediate electrode layers is designed differently.
예를 들어, 복수의 전극층들(610)은 서로 다른 두께를 갖는 전극층 1(620), 전극층 2(621), 전극층 3(622) 및 전극층 4(623)를 포함할 수 있다. 이 때, 전극층 1(620)의 두께는 전극층 2(621), 전극층 3(622) 및 전극층 4(623)의 두께보다 두껍게 형성될 수 있으며, 이것은 복수의 전극층들(610) 각각의 문턱 전압을 균일하게 할 수 있다.For example, the plurality of electrode layers 610 may include an electrode layer 1 620, an electrode layer 2 621, an electrode layer 3 622, and an electrode layer 4 623 having different thicknesses. In this case, the thickness of the electrode layer 1 620 may be formed to be thicker than the thickness of the electrode layer 2 621, the electrode layer 3 622, and the electrode layer 4 623, and this may increase the threshold voltage of each of the plurality of electrode layers 610. It can be made uniform.
도 6에서 복수의 전극층들(610) 각각의 두께 변화를 통하여 물리적 구조의 변경을 설명하였지만, 본 발명의 실시예들은 다양한 길이, 복수의 전극층들(610) 각각의 표면에 형성되는 패턴 등의 변화를 포함한다.In FIG. 6, the physical structure is changed by changing the thickness of each of the plurality of electrode layers 610, but embodiments of the present invention vary the length, the pattern formed on the surface of each of the plurality of electrode layers 610, and the like. It includes.
이 때, 복수의 전극층들(610)과 교대로 배치되는 복수의 층간 절연층들(630)은 위에서 상술한, 각각마다 실질적으로 균일한 레벨의 스트레스가 적용되는 재료 또는 물리적인 구조를 가질 수도 있다.In this case, the plurality of interlayer insulating layers 630 alternately arranged with the plurality of electrode layers 610 may have a material or a physical structure to which a substantially uniform level of stress is applied, as described above. .
도 7은 본 발명의 실시예에 따라 서로 다른 물리적 구조를 갖고, 서로 다른 물질로 형성되는 복수의 전극층들을 포함하는 3차원 플래시 메모리의 단면도를 나타낸다.7 is a cross-sectional view of a three-dimensional flash memory having a plurality of electrode layers having different physical structures and formed of different materials according to an embodiment of the present invention.
도 7을 참조하면, 본 발명의 실시예는 도 6에 도시된 바와 같이, 복수의 전극층들 각각의 물리적인 구조를 서로 다르게 설계하면서도, 복수의 전극층들 각각을 위하여 서로 다른 물질을 사용할 수 있다.Referring to FIG. 7, as shown in FIG. 6, the physical structure of each of the plurality of electrode layers may be differently designed, but different materials may be used for each of the plurality of electrode layers.
다시 도 7을 참조하면, 본 발명의 실시예는 복수의 전극층들(710)은 물질 1의 전극층(720), 물질 2의 전극층(721), 물질 3의 전극층(722) 및 물질 4의 전극층(723)을 포함할 수 있다.Referring back to FIG. 7, in the embodiment of the present invention, the plurality of electrode layers 710 may include an electrode layer 720 of material 1, an electrode layer 721 of material 2, an electrode layer 722 of material 3, and an electrode layer of material 4 ( 723).
여기서, 본 발명의 실시예는 복수의 전극층들(710) 중 상층부에 존재하는 전극층을 위해서는 상대적으로 전기적인 전달 특성이 약한 재료를 사용할 수 있고, 하층부에 존재하는 전극층을 위해서는 상대적으로 전기적인 전달 특성이 우수한 재료를 사용할 수 있다. 예를 들어, 물질 1의 전극층(720)의 전기적인 전달 특성은 물질 4의 전극층(723)의 전기적인 전달 특성보다 우수할 수 있다. 따라서, 복수의 전극층들(710) 각각의 문턱 전압은 균일하게 될 수 있다.Here, in the embodiment of the present invention, a material having a relatively low electrical transmission property may be used for an electrode layer existing in an upper layer among the plurality of electrode layers 710, and a relatively electrical transmission property for an electrode layer existing in a lower layer. This excellent material can be used. For example, the electrical transfer properties of the electrode layer 720 of material 1 may be superior to the electrical transfer properties of the electrode layer 723 of material 4. Therefore, the threshold voltage of each of the plurality of electrode layers 710 may be uniform.
이 때, 복수의 전극층들(710)과 교대로 배치되는 복수의 층간 절연층들(730)은 위에서 상술한, 각각마다 실질적으로 균일한 레벨의 스트레스가 적용되는 재료 또는 물리적인 구조를 가질 수도 있다.In this case, the plurality of interlayer insulating layers 730 disposed alternately with the plurality of electrode layers 710 may have a material or a physical structure to which a substantially uniform level of stress is applied to each of the above-described ones. .
또한, 본 발명의 실시예는 서로 다른 물리적 구조를 가지면서 서로 다른 물질로 형성되는 복수의 전극층들(710)을 제안하고 있으나, 이에 제한되거나 한정되지 않고, 균일한 물리적 구조를 가지면서 서로 다른 물질로만 형성되는 복수의 전극층들(710) 역시 제안할 수 있다.In addition, although the embodiment of the present invention proposes a plurality of electrode layers 710 having different physical structures and formed of different materials, the present invention is not limited thereto and is not limited thereto. A plurality of electrode layers 710 formed only as well may also be proposed.
도 8은 본 발명의 일실시예에 따른 3차원 플래시 메모리를 포함하는 저장 장치를 나타낸 도면이다.8 illustrates a storage device including a 3D flash memory according to an embodiment of the present invention.
도 8을 참조하면, 시스템(800)은 메모리(810)와 메모리 컨트롤러(820)가 연결되어 있다. 이 때, 메모리(810)는 위에서 상술한 3차원 플래시 메모리를 의미한다. 메모리(810)는 낸드 플래시 메모리뿐만 아니라, 본 발명의 사상을 응용한 노아 플래시 메모리도 될 수 있다.Referring to FIG. 8, in the system 800, a memory 810 and a memory controller 820 are connected. In this case, the memory 810 refers to the above-described three-dimensional flash memory. The memory 810 may be not only a NAND flash memory but also a Noah flash memory to which the spirit of the present invention is applied.
메모리 컨트롤러(820)는 메모리(810)의 동작을 컨트롤하기 위해서 입력신호를 제공한다.The memory controller 820 provides an input signal to control the operation of the memory 810.
시스템(500)은 예를 들어 메모리 카드에 쓰이는 메모리 컨트롤러와 메모리와의 관계라면 호스트의 명령을 전달하여 입출력 데이터를 컨트롤하거나, 인가받은 컨트롤 신호를 기초로 메모리의 다양한 데이터를 컨트롤 한다.For example, the system 500 controls input / output data by transmitting a command of a host when the memory controller used in the memory card is related to the memory, or controls various data in the memory based on an authorized control signal.
이러한 구조는 간단한 메모리카드뿐 아니라 메모리가 쓰이는 많은 디지털기기에 응용되어 휴대용 디지털 카메라, 휴대폰 등 메모리가 필요한 모든 디지털 기기에 적용 된다.This structure is applied not only to simple memory cards but also to many digital devices that use memory, and applies to all digital devices that need memory such as portable digital cameras and mobile phones.
도 9는 균일한 물리적 구조를 갖고, 동일한 물질로 형성되는 복수의 전극층들을 포함하는 3차원 플래시 메모리의 구조를 나타낸 도면이다.FIG. 9 illustrates a structure of a 3D flash memory having a uniform physical structure and including a plurality of electrode layers formed of the same material.
도 9를 참조하면, 3차원 플래시 메모리가 셀 트랜지스터들이 직렬로 연결되어 단위 스트링을 이루고, 이러한 단위 스트링들이 비트 라인과 접지 라인 사이에 병렬로 연결되어 있는 구조를 갖는 낸드 플래시 메모리인 경우를 설명한다. 이 때, 도 9의 (a)를 살펴보면, 스트링의 길이가 길어질수록 채널층의 저항이 증가되어 비트 라인에 가해진 판독 전류가 채널층을 따라 흐르면서 전류밀도가 스트링의 하층부로 내려갈수록 취약해짐을 알 수 있다. 이하, 도 10에서는 도 9의 (b)와 같이, 스트링에 포함되는 셀의 적층수를 10단, 30단 및 50단으로 다르게 하면서, 상부에 있는 셀과 하부에 있는 셀에 각각 10V의 프로그램 바이어스를 인가하여, 저장된 데이터의 판독 동작을 수행할 때 게이트 전압에 따른 드레인 전류를 확인하는 실험을 기재한다.Referring to FIG. 9, a case in which a 3D flash memory is a NAND flash memory having a structure in which cell transistors are connected in series to form a unit string, and the unit strings are connected in parallel between a bit line and a ground line. . In this case, as shown in FIG. 9A, as the length of the string increases, the resistance of the channel layer increases, and as the read current applied to the bit line flows along the channel layer, the current density becomes weaker as the lower portion of the string decreases. Can be. In FIG. 10, as shown in FIG. 9B, the number of stacks of cells included in the string is changed to 10, 30, and 50 stages, respectively, and the program bias of 10V is applied to the upper and lower cells, respectively. The experiment to check the drain current according to the gate voltage when performing the read operation of the stored data by applying a.
도 10은 도 9에 도시된 3차원 플래시 메모리에서 문턱 전압 산포를 나타낸 그래프이다.FIG. 10 is a graph illustrating a threshold voltage distribution in the three-dimensional flash memory shown in FIG. 9.
도 10을 참조하면, 셀의 적층수가 30단인 경우의 top과 bottom의 드레인 전류(1030, 1040)가 셀의 적층수가 10단인 경우의 top과 bottom의 드레인 전류(1010, 1020)보다 감소했음을 알 수 있고, 셀의 적층수가 50단인 경우의 top과 bottom의 드레인 전류(1050, 1060)가 셀의 적층수가 30단인 경우의 top과 bottom의 드레인 전류(1030, 1040)보다 감소했음을 알 수 있다.Referring to FIG. 10, it can be seen that the top and bottom drain currents 1030 and 1040 when the number of stacked cells is 30 stages are reduced than the top and bottom drain currents 1010 and 1020 when the number of cells stacked is 10 stages. In addition, it can be seen that the drain currents 1050 and 1060 of the top and bottom when the number of stacked cells is 50 stages are lower than the drain currents 1030 and 1040 of the top and the bottom when the number of stacked cells is 30 stages.
또한, 셀의 적층수에 따른 게이트 전압 차이는 아래의 표 1과 같이 나타났다.In addition, the gate voltage difference according to the number of stacked cells is shown in Table 1 below.
표 1
10단 셀 30단 셀 50단 셀
top bottom top bottom top bottom
Saturation Drain Current[A] 3.69E-05 3.69E-05 3.69E-05 3.69E-05 3.69E-05 3.69E-05
Vt [V] 0.7247 0.6549 0.6530 0.5080 0.4715 0.2633
△Vt [V] 0.0698 0.1450 0.2082
Table 1
10-speed cell 30-speed cell 50-speed cell
top bottom top bottom top bottom
Saturation Drain Current [A] 3.69E-05 3.69E-05 3.69E-05 3.69E-05 3.69E-05 3.69E-05
Vt [V] 0.7247 0.6549 0.6530 0.5080 0.4715 0.2633
ΔVt [V] 0.0698 0.1450 0.2082
표 1을 살펴보면, 3차원 낸드 플래시 메모리의 적층수가 증가할수록 상부에 위치한 셀과 하부에 위치한 셀 사이의 문턱 전압의 차이가 커지는 경향을 알 수 있다. 다시 말해, 셀의 단수가 적을 때에는 셀의 위치에 따른 문턱 전압의 차이가 미미하지만, 셀의 단수가 커지게 되면, 문턱 전압의 산포가 확산될 수 있다. 이러한 결과는 특히, 셀 당 2비트 이사의 정보를 저장하는 MLC(Multi Level Cell)에서 저장된 데이터의 판독 과정에서의 신뢰성을 저하시키게 된다.Referring to Table 1, it can be seen that as the number of stacked 3D NAND flash memories increases, the difference in the threshold voltage between the upper cell and the lower cell increases. In other words, when the number of cells is small, the difference in the threshold voltage according to the position of the cell is insignificant. However, when the number of cells becomes large, the distribution of the threshold voltages may spread. This result is particularly deteriorated in the reading process of data stored in a MLC (Multi Level Cell) that stores two bits of information per cell.
도 11은 복수의 전극층들 각각의 두께에 따른 3차원 플래시 메모리에서 문턱 전압 산포를 나타낸 그래프들이다.FIG. 11 is a graph illustrating threshold voltage distribution in a three-dimensional flash memory according to thicknesses of the plurality of electrode layers.
도 11을 참조하면, 3차원 플래시 메모리의 게이트층인 복수의 전극층들 각각의 두께를 조절함으로써, 변화되는 두께에 따른 문턱 전압 산포를 비교한다.Referring to FIG. 11, by adjusting the thicknesses of the plurality of electrode layers, which are the gate layers of the 3D flash memory, the threshold voltage distributions according to the changed thicknesses are compared.
(a)와 같이 복수의 전극층들 각각의 두께를 40nm으로 일정하게 한 경우, 복수의 전극층들 중 상부의 전극층과 하부의 전극층 사이의 문턱 전압(1110, 1120)의 차이는 0.2082임을 알 수 있다.When the thickness of each of the plurality of electrode layers is fixed to 40 nm as shown in (a), it can be seen that the difference between the threshold voltages 1110 and 1120 between the upper electrode layer and the lower electrode layer among the plurality of electrode layers is 0.2082.
또한, (b)와 같이 복수의 전극층들 각각의 두께를 상부의 전극층을 70nm으로 설정하고 하부의 전극층을 40nm으로 설정하여, 상부로 올라갈수록 두께를 증가시킨 경우, 복수의 전극층들 중 상부의 전극층과 하부의 전극층 사이의 문턱 전압(1130, 1140)의 차이는 0.3918임을 알 수 있다.In addition, as shown in (b), when the upper electrode layer is set to 70 nm and the lower electrode layer is set to 40 nm, the thickness of each of the plurality of electrode layers is increased as the thickness of the upper electrode layer increases. It can be seen that the difference between the threshold voltages 1130 and 1140 between the electrode layer and the lower electrode layer is 0.3918.
또한, (c)와 같이 복수의 전극층들 각각의 두께를 상부의 전극층을 10nm으로 설정하고 하부의 전극층을 40nm으로 설정하여, 상부로 올라갈수록 두께를 감소시킨 경우, 복수의 전극층들 중 상부의 전극층과 하부의 전극층 사이의 문턱 전압(1150, 1160)의 차이는 -0.2198임을 알 수 있다.In addition, as shown in (c), when the upper electrode layer is set to 10 nm and the lower electrode layer is set to 40 nm, the thickness of each of the plurality of electrode layers decreases as the upper portion is increased, the upper electrode layer among the plurality of electrode layers. It can be seen that the difference between the threshold voltages 1150 and 1160 between the electrode layer and the lower electrode layer is -0.2198.
또한, (d)와 같이 복수의 전극층들 각각의 두께를 상부의 전극층을 20nm으로 설정하고 하부의 전극층을 40nm으로 설정하여, 상부로 올라갈수록 두께를 감소시킨 경우, 복수의 전극층들 중 상부의 전극층과 하부의 전극층 사이의 문턱 전압(1170, 1180)의 차이는 0.0039임을 알 수 있다.In addition, as shown in (d), when the upper electrode layer is set to 20 nm and the lower electrode layer is set to 40 nm, the thickness of each of the plurality of electrode layers decreases as the upper portion is increased, the upper electrode layer among the plurality of electrode layers. It can be seen that the difference between the threshold voltages 1170 and 1180 between the electrode layer and the lower electrode layer is 0.0039.
즉, 복수의 전극층들 각각의 두께를 하부에 내려갈수록 두껍게 형성함으로써, 문턱 전압 산포를 개선할 수 있음을 알 수 있다. 따라서, 복수의 전극층들 중 제1 전극층의 두께를 제1 전극층의 상층에 존재하는 제2 전극층의 두께보다 두껍게 형성하는 것 같이 복수의 전극층들 각각의 물리적인 구조를 서로 다르게 설계함으로써, 복수의 전극층들의 문턱 전압 산포를 개선할 수 있다.That is, it can be seen that the threshold voltage distribution can be improved by forming the thickness of each of the plurality of electrode layers as the thickness becomes lower. Therefore, the physical structure of each of the plurality of electrode layers is differently designed such that the thickness of the first electrode layer among the plurality of electrode layers is thicker than the thickness of the second electrode layer existing on the upper layer of the first electrode layer. Can improve their threshold voltage distribution.
이상과 같이 실시예들이 비록 한정된 실시예와 도면에 의해 설명되었으나, 해당 기술분야에서 통상의 지식을 가진 자라면 상기의 기재로부터 다양한 수정 및 변형이 가능하다. 예를 들어, 설명된 기술들이 설명된 방법과 다른 순서로 수행되거나, 및/또는 설명된 시스템, 구조, 장치, 회로 등의 구성요소들이 설명된 방법과 다른 형태로 결합 또는 조합되거나, 다른 구성요소 또는 균등물에 의하여 대치되거나 치환되더라도 적절한 결과가 달성될 수 있다.Although the embodiments have been described by the limited embodiments and the drawings as described above, various modifications and variations are possible to those skilled in the art from the above description. For example, the described techniques may be performed in a different order than the described method, and / or components of the described systems, structures, devices, circuits, etc. may be combined or combined in a different form than the described method, or other components. Or even if replaced or substituted by equivalents, an appropriate result can be achieved.
그러므로, 다른 구현들, 다른 실시예들 및 특허청구범위와 균등한 것들도 후술하는 특허청구범위의 범위에 속한다.Therefore, other implementations, other embodiments, and equivalents to the claims are within the scope of the claims that follow.

Claims (13)

  1. 3차원 플래시 메모리에 있어서,In three-dimensional flash memory,
    채널층;Channel layer;
    상기 채널층과 연결되고, 수직적으로 적층되는 복수의 전극층들; 및A plurality of electrode layers connected to the channel layer and stacked vertically; And
    상기 채널층과 연결되고, 상기 복수의 전극층들과 교대로 배치되며, 수직적으로 적층되는 복수의 층간 절연층들A plurality of interlayer insulating layers connected to the channel layer, alternately disposed with the plurality of electrode layers, and stacked vertically;
    을 포함하고,Including,
    상기 복수의 전극층들 각각은 서로 다른 물리적인 구조를 갖거나, 서로 다른 물질로 형성되는 3차원 플래시 메모리.Each of the plurality of electrode layers has a different physical structure or is formed of different materials.
  2. 제1항에 있어서,The method of claim 1,
    상기 복수의 전극층들 중 제1 전극층의 두께는 상기 제1 전극층의 상층에 존재하는 제2 전극층의 두께보다 두껍게 형성되는 3차원 플래시 메모리.The thickness of the first electrode layer of the plurality of electrode layers is formed thicker than the thickness of the second electrode layer existing on the upper layer of the first electrode layer.
  3. 제1항에 있어서,The method of claim 1,
    상기 복수의 전극층들 각각의 길이 또는 상기 복수의 전극층들 각각의 표면에 형성되는 패턴은 서로 다른 3차원 플래시 메모리.The length of each of the plurality of electrode layers or the pattern formed on the surface of each of the plurality of electrode layers are different from each other three-dimensional flash memory.
  4. 제1항에 있어서,The method of claim 1,
    상기 복수의 전극층들 중 제1 전극층을 형성하는 재료는 상기 제1 전극층의 상층에 존재하는 제2 전극층의 재료보다 우수한 전기적인 전달 특성을 갖는 3차원 플래시 메모리.The material forming the first electrode layer of the plurality of electrode layers has a better electrical transfer characteristics than the material of the second electrode layer existing on the upper layer of the first electrode layer.
  5. 제1항에 있어서,The method of claim 1,
    상기 복수의 전극층들 중 적어도 두 개의 전극층들 각각은 서로 다른 물질로 형성되는 3차원 플래시 메모리.Each of the at least two electrode layers of the plurality of electrode layers is formed of a different material.
  6. 제1항에 있어서,The method of claim 1,
    상기 복수의 전극층들 각각과 상기 채널층 사이에는 인터레이어 산화막, 상기 실리콘 질화막 및 터널 산화막이 배치되는 3차원 플래시 메모리.And an interlayer oxide film, the silicon nitride film, and a tunnel oxide film between each of the plurality of electrode layers and the channel layer.
  7. 3차원 플래시 메모리에 있어서,In three-dimensional flash memory,
    채널층;Channel layer;
    상기 채널층과 연결되고, 수직적으로 적층되는 복수의 전극층들; 및A plurality of electrode layers connected to the channel layer and stacked vertically; And
    상기 채널층과 연결되고, 상기 복수의 전극층들과 교대로 배치되며, 수직적으로 적층되는 복수의 층간 절연층들A plurality of interlayer insulating layers connected to the channel layer, alternately disposed with the plurality of electrode layers, and stacked vertically;
    을 포함하고,Including,
    상기 복수의 층간 절연층들 각각은 서로 다른 물질로 형성되거나, 서로 다른 물리적인 구조를 갖는 3차원 플래시 메모리.Each of the plurality of interlayer insulating layers may be formed of different materials or have different physical structures.
  8. 제7항에 있어서,The method of claim 7, wherein
    상기 복수의 층간 절연층들 중 제1 층간 절연층을 형성하는 재료는 상기 제1 층간 절연층의 상층에 존재하는 제2 층간 절연층의 재료보다 스트레스에 강한 특성을 갖는 3차원 플래시 메모리.The material forming the first interlayer insulating layer of the plurality of interlayer insulating layers has a stress-resistant property than the material of the second interlayer insulating layer present on the first interlayer insulating layer.
  9. 제7항에 있어서,The method of claim 7, wherein
    상기 복수의 층간 절연층들 중 적어도 두 개의 층간 절연층들은 서로 다른 물질로 형성되는 3차원 플래시 메모리.At least two interlayer insulating layers of the plurality of interlayer insulating layers are formed of different materials.
  10. 제7항에 있어서,The method of claim 7, wherein
    상기 복수의 층간 절연층들 중 제1 층간 절연층의 두께는 상기 제1 층간 절연층의 상층에 존재하는 제2 층간 절연층의 두께보다 두껍게 형성되는 3차원 플래시 메모리.The thickness of the first interlayer insulating layer of the plurality of interlayer insulating layers is formed thicker than the thickness of the second interlayer insulating layer existing on the upper layer of the first interlayer insulating layer.
  11. 제7항에 있어서,The method of claim 7, wherein
    상기 복수의 층간 절연층들 각각의 길이 또는 상기 복수의 층간 절연층들 각각의 표면에 형성되는 패턴은 서로 다른 3차원 플래시 메모리.The length of each of the plurality of interlayer insulating layers or a pattern formed on a surface of each of the plurality of interlayer insulating layers are different from each other.
  12. 제7항에 있어서,The method of claim 7, wherein
    상기 복수의 전극층들 각각과 상기 채널층 사이에는 인터레이어 산화막, 상기 실리콘 질화막 및 터널 산화막이 배치되는 3차원 플래시 메모리.And an interlayer oxide film, the silicon nitride film, and a tunnel oxide film between each of the plurality of electrode layers and the channel layer.
  13. 3차원 플래시 메모리에 있어서,In three-dimensional flash memory,
    채널층;Channel layer;
    상기 채널층과 연결되고, 수직적으로 적층되는 복수의 전극층들; 및A plurality of electrode layers connected to the channel layer and stacked vertically; And
    상기 채널층과 연결되고, 상기 복수의 전극층들과 교대로 배치되며, 수직적으로 적층되는 복수의 층간 절연층들A plurality of interlayer insulating layers connected to the channel layer, alternately disposed with the plurality of electrode layers, and stacked vertically;
    을 포함하고,Including,
    상기 복수의 층간 절연층들 각각은 서로 다른 물질로 형성되거나, 서로 다른 물리적인 구조를 가지며, Each of the plurality of interlayer insulating layers may be formed of different materials or have different physical structures.
    상기 복수의 전극층들 각각은 서로 다른 물질로 형성되거나, 서로 다른 물리적인 구조를 갖는 3차원 플래시 메모리.Each of the plurality of electrode layers may be formed of different materials or have different physical structures.
PCT/KR2014/013095 2014-01-28 2014-12-31 Three dimensional flash memory using electrode layers and/or interlayer insulation layers having different properties, and preparation method therefor WO2015115739A1 (en)

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