WO2015109968A1 - 晶圆级半导体器件及其制备方法 - Google Patents
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- WO2015109968A1 WO2015109968A1 PCT/CN2015/070836 CN2015070836W WO2015109968A1 WO 2015109968 A1 WO2015109968 A1 WO 2015109968A1 CN 2015070836 W CN2015070836 W CN 2015070836W WO 2015109968 A1 WO2015109968 A1 WO 2015109968A1
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
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- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/16—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
- H01L33/18—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous within the light emitting region
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- H01—ELECTRIC ELEMENTS
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- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
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Definitions
- the present invention relates to a semiconductor device and a process for fabricating the same, and more particularly to a high power, large area wafer level semiconductor device and a method for fabricating the same, the wafer level semiconductor device being a plurality of unit cells formed on a wafer Devices connected in series and parallel can be used without cutting separation.
- P 1 and P 2 are the yields of the LED chips with the area of A 1 and A 2 respectively. Assuming that the yield of the LED chip with an area of 1 mm 2 is 99%, then we can calculate the good device with the increase of the chip area. The rate has dropped dramatically. As shown in Figure 1, when the chip area is increased to 500mm 2 , the yield has dropped to ⁇ 1%, and if the chip area is increased to 1000mm 2 , the yield is only 0.34%, which cannot be used to produce large area and large. Power LED device products.
- one of the objects of the present invention is to provide a wafer level semiconductor device which has the advantages of simple and convenient process, low cost, and high yield.
- Another object of the present invention is to provide a process for preparing the aforementioned wafer level semiconductor device.
- a wafer level semiconductor device comprising:
- Wafer level substrate Wafer level substrate
- each unit cell is directly grown
- An independent functional unit formed by processing a semiconductor layer on the surface of the substrate;
- a method of fabricating a wafer level semiconductor device comprising:
- each series group comprises a plurality of parallel groups arranged in series, each parallel group comprising a plurality of unit cells arranged in parallel, and each unit cell is An independent functional unit formed by processing a semiconductor layer directly grown on the surface of the substrate;
- the preparation method may include the following steps:
- any of the first parallel groups includes a plurality of normal unit cells arranged in parallel
- any second parallel group It includes a plurality of redundant unit cells arranged in parallel
- M is a positive integer
- N is 0 or a positive integer
- the foregoing unit cell refers to a device unit having an independent and complete function, and the conductive semiconductor layers of any two unit cells are isolated to make any unit cell electrically independent; and the plurality of unit cells are electrically connected through the metal interconnection. , to form larger devices, to achieve higher device performance, such as: power increase.
- the aforementioned wafer level substrate has a diameter of 2 inches or more.
- the unit cell may be an electronic component such as a semiconductor laser, a light-emitting element such as an LED, or a diode.
- the two selected parallel groups are non-adjacent.
- all of the unit cells formed on the surface of the substrate include a plurality of normal unit cells and a plurality of redundant unit cells, and the plurality of normal unit cells are arranged in a plurality of multi-level unit groups arranged in parallel.
- Any multi-level cell group includes a plurality of first parallel groups arranged in series, and the selected M first parallel groups of any one of the multi-level cell groups are further connected in series with the N second parallel groups to form a series group.
- any of the first parallel groups includes a plurality of normal cells arranged in parallel
- any of the second parallel groups includes a plurality of redundant cells arranged in parallel
- M is a positive integer
- N is 0 or a positive integer
- At least one matching resistor is further provided in at least one series group.
- the selected two or more first parallel groups of the at least one multi-level cell group are directly connected in series with the at least one second parallel group to form a series group.
- the series connection has a turn-on voltage of 110V ⁇ 20V, 220V ⁇ 40V or 380V ⁇ 70V.
- the wafer level semiconductor device may further include a cooling structure sealingly connected to the substrate, and the selected area of the second surface of the substrate is exposed to the cooling medium circulation cavity in the cooling structure, the selected area At least corresponding to a region of the first surface of the substrate on which the plurality of unit cells are distributed.
- the wafer level semiconductor device may further include a cooling structure sealingly connected to the substrate, and the plurality of unit cells are exposed to the cooling medium circulation cavity in the cooling structure.
- At least a portion of the surface of the wafer level semiconductor device exposed to the cavity is distributed with a heat dissipation mechanism.
- the heat dissipating mechanism may include a plurality of sheet-like and/or columnar heat dissipating members connected to at least one side of the wafer level semiconductor device.
- the heat dissipating structure may also include a plurality of fin fins or arrays arranged on one side of the wafer level semiconductor device and a plurality of heat dissipating columns distributed on one side of the wafer level semiconductor device.
- a surface of the wafer-level semiconductor device exposed to the cavity is further connected with a reflective layer, and the functional unit cell is distributed on the other surface of the wafer-level semiconductor device.
- a reflective layer may be disposed between the heat dissipation mechanism and one side of the wafer level semiconductor device.
- the heat dissipating housing may also be distributed with a heat transfer medium inlet and an outlet communicating with the cavity.
- the heat dissipation housing has a closed inner cavity, and the heat dissipation housing further has a plurality of heat dissipation fins.
- the heat dissipation housing can be soldered and fixed to the wafer level semiconductor device.
- a plug-in electrical connection structure including an insulating substrate and an elastic conductive mechanism may be employed in the wafer level semiconductor device, and the elastic conductive mechanism and An insulating base is fixedly connected, wherein a resilient clamping structure for holding and fixing the wafer level semiconductor device is formed between a selected portion between one end or both ends of the elastic conductive mechanism and the insulating substrate
- a selected portion between one or both ends of the elastic conductive mechanism is also in electrical contact with the cathode or anode of the wafer level semiconductor device.
- the elastic conductive mechanism may be a metal reed, and one end of the metal reed is fixedly connected to the insulating base, and the other end is a movable end.
- the other end of the metal reed has at least one arc structure, and when the wafer level semiconductor device is inserted into the elastic clamping structure, the top end portion of at least one of the arc structures and the crystal The cathode or anode of the circular semiconductor device is in electrical contact.
- the elastic conductive mechanism is fixedly connected to one end of the insulating base body, and the other end portion has a protruding portion, and the protruding portion and a selected portion between one end or both ends of the elastic conductive mechanism The elastic clamping structure is formed therebetween.
- the elastic conductive mechanism is electrically connected to the power source via a wire distributed on the insulating substrate.
- the insulating substrate is in contact with the other surface of the substrate.
- the present invention has at least the following advantages: the wafer level semiconductor device structure Simple, simple and convenient process, low cost, high yield, suitable for large-scale manufacturing and application.
- Figure 1 is a graph showing the relationship between LED chip yield and chip area
- FIG. 3 is a schematic structural view of a conventional integrated high power LED device
- FIGS. 4a-4b are top and cross-sectional views, respectively, of a wafer level LED device in accordance with a preferred embodiment of the present invention.
- 5a is a working circuit diagram of a wafer level LED device in accordance with a preferred embodiment of the present invention.
- 5b is a circuit diagram showing the operation of another wafer level LED device in accordance with a preferred embodiment of the present invention.
- FIG. 6 is a circuit diagram showing the operation of a wafer level LED device in another preferred embodiment of the present invention.
- FIGS. 7a-7b are schematic diagrams and partial enlarged views of a heat dissipation structure of a wafer level semiconductor device according to an embodiment of the present invention.
- FIGS. 8a-8b are schematic diagrams showing a heat dissipation structure of a wafer level semiconductor device and a cross-sectional view taken along line A-A in an exemplary embodiment of the present invention
- FIGS. 9a-9b are schematic structural views of a heat dissipation mechanism of a wafer level semiconductor device in several exemplary embodiments of the present invention.
- FIG. 10 is a schematic diagram of a heat dissipation structure of a wafer level semiconductor device in another exemplary embodiment of the present invention.
- FIG. 11 is a schematic diagram of a heat dissipation structure of a wafer level semiconductor device in still another exemplary embodiment of the present invention.
- 12a-12c are schematic views of an anti-reflection anti-reflection structure in several exemplary embodiments of the present invention.
- FIG. 13 is a schematic diagram of a heat dissipation and electrical connection structure of a wafer level semiconductor device according to an exemplary embodiment of the present invention.
- FIG. 14 is a flow chart of a process for preparing a wafer level LED according to an exemplary embodiment of the present invention.
- 15 is a second flow chart of a process for preparing a wafer level LED according to an exemplary embodiment of the present invention.
- transfer substrate 10 transfer substrate 10, wafer level substrate 11, functional unit cell 12, n-type semiconductor 121, p-type semiconductor 122, luminescent quantum well 123, insulating medium 124, interconnect metal 13, cathode 14, anode 15 , reflective layer 16, fin fin 171, heat sink 172, LED chip 20, substrate 201, epitaxial layer 202, working electrode 203, cavity 21, heat sink 22, phase change heat sink 23, heat sink fin 24.
- the LED device As an example, from the principle analysis, there are two main failure modes in the LED device, namely: short circuit failure and open circuit failure.
- short circuit failure In order to obtain a large-area, high-power LED chip, a multi-stage series method or a plurality of parallel methods may be employed.
- the probability of a short-circuit in one stage is P s
- the probability P sk of the k-level short-circuit can be expressed as follows:
- the probability analysis method can also be used to analyze the yield of multiple parallel LEDs. Taking 24 single-cell parallel LEDs as an example, if the short-circuit failure probability (P s ) and the open-circuit failure probability (P o ) of the unit cell are both 2%, it can be analyzed: 1) only when 0 cells are short-circuited LED can work normally, its yield is 13.5%; 2) When k cells are disconnected, LED can still work normally. When k is less than or equal to 5, the total yield is over 98%. Therefore, the parallel mode has the ability to resist open circuit failure.
- the short-circuit failure and open-circuit failure mentioned above are the main failure modes in LEDs. Therefore, when designing large-area LED chips, especially wafer-level LED chips, it must be able to resist both failures at the same time.
- the LED is a current-type semiconductor device, and the current is an exponential relationship of voltage, which can be expressed as:
- I s is the reverse saturation current and n ideal is the ideal factor for the device.
- n ideal is the ideal factor for the device.
- the voltage of each stage is close to the n-level average of the total voltage.
- the methods used include:
- the redundancy level in the series group is different from the parallel level in the series group
- the reason is that the redundant level electrode is large, and it can be electrically contacted by the probe, and after the chip is completed, the series test and its redundancy level are electrically tested, and then according to the principle that the turn-on voltage is consistent
- the redundancy stage is connected to the output electrode by a jumper.
- the connection resistance is used to further match according to the set operating current.
- a "jumper” as used herein shall be understood to mean a conductor for electrically connecting a circuit, in particular a particular two demand points in a series circuit, and having more than one space between the two demand points.
- the functional elements constituting the series circuit are, for example, one or more of the aforementioned parallel groups.
- the wafer level semiconductor device provided by the present invention is directly formed by processing a wafer level substrate having a semiconductor material layer (which may also be an "epitaxial layer"), and the main structure thereof.
- a wafer level substrate is included, and a plurality of unit cells having a set function formed by processing a semiconductor layer directly grown on the first surface of the substrate.
- the present invention provides a process for preparing the aforementioned wafer level semiconductor device, which mainly comprises the following processes: after forming an epitaxial layer on a wafer level substrate, processing is performed on the substrate. A plurality of unit cells arranged in an array are formed.
- the wafer level semiconductor device process of the present invention does not need to include at least thinning, cutting and splitting of the substrate, and does not need to be one-to-one compared to the packaging process of the conventional semiconductor chip or the integrated semiconductor device.
- the small-sized semiconductor chip is packaged, and the small-sized semiconductor chip is not required to be bonded to the transfer substrate one by one to perform subsequent operations, and only one package can construct the main structure of the high-power semiconductor device, and the operation is simple. The cost is low, and many operations that may cause damage to the epitaxial wafer or unit cell are avoided, and environmental pollution is not caused.
- the selected substrate is a transparent wafer such as a sapphire wafer
- the wafer-level semiconductor device of the present invention when used as a flip-chip device, the unthinned substrate can also be used as a light-emitting device.
- the window further enhances the luminous efficiency of the device.
- a part of the unit cell formed on the substrate is defined as a normal unit cell, and the rest is defined as a redundant unit cell, wherein the normal unit cell line serves as an effective working unit of the wafer level semiconductor device during operation, and the redundant unit cell A considerable part of it is used as a spare unit of work, so the number of normal unit cells should be as much as possible and far greater than the redundant unit cells;
- the plurality of normal cells are divided into two or more multi-level cell groups arranged in parallel, and any multi-level cell group includes two or more first parallel groups arranged in series.
- the selected M first parallel groups of any multi-level cell group are further connected in series with the N second parallel groups to form a series group, and finally the turn-on voltages of the respective series groups are substantially the same (generally, at ⁇ Within 10%).
- any of the first parallel groups includes two or more normal unit cells arranged in parallel
- any of the second parallel groups includes two or more redundant unit cells arranged in parallel
- M is a positive integer
- N is 0 or a positive integer
- the M first parallel groups may be selected from any of the multi-level cell groups to form a series group directly through the wires and the N second parallel groups, and the remaining one or more abnormal first parallel groups Isolating from the working circuit, so that the turn-on voltage of each series group is basically the same, which ensures the working stability of the device and improves its working efficiency.
- the second parallel group may not be included in a certain series group, and a part of the first parallel group is selected to be electrically connected to the working electrode of the semiconductor device through a wire.
- At least one matching resistor may be further disposed in each of the foregoing series groups, and the matching resistor may be a resistor having a fixed resistance, and the resistance may be according to each series group and the remaining series group. It is determined by the difference in the on-voltage, and of course, an adjustable resistor can also be preferably used.
- One of the effective heat dissipation methods is to directly contact one surface of the wafer level device with a liquid or gaseous cooling medium to avoid heat sink resistance, soldering thermal resistance and heat sink thermal resistance, and to obtain a minimum heat dissipation path for optimum heat dissipation performance.
- an active cooling structure sealingly coupled to the substrate may be employed, and selected regions of the second surface of the substrate are exposed to the cooling medium flow chamber in the cooling structure, and The selected area corresponds to at least the area of the first surface of the substrate on which the plurality of unit cells are distributed, and the speed at which the cooling medium circulates can be adjusted according to actual conditions, so that the heat generated by each unit cell during operation can be quickly and timely transferred. Without a large accumulation, the device is destroyed.
- the cooling structure may also be sealed on the substrate, and the plurality of unit cells are exposed to the cooling medium circulation cavity in the cooling structure.
- wafer level means that the diameter of the substrate is 2 inches or more.
- the wafer level semiconductor device of the present invention includes a semiconductor light emitting device such as an LED or the like, and is not limited thereto.
- the method for fabricating the wafer level semiconductor device may further include:
- Unit cell (1) directly processing the semiconductor material layer to form a plurality of unit cells 2 having a set function, and setting a portion of all unit cells 2 of the normal region as a normal unit cell, and the rest is set to be redundant.
- the second parallel group comprises two or more redundant unit cells arranged in parallel, M is a positive integer, and N is 0 or a positive integer.
- the wafer level semiconductor device of the present invention has a simple structure, a simple and convenient process, low cost, and high yield, and is suitable for large-scale manufacturing and application.
- the present embodiment relates to a wafer level LED device including a wafer level substrate 11 and a plurality of unit cells 12 fixed to the top end surface ("first surface") of the substrate 1.
- the plurality of unit cells are formed by dividing a semiconductor layer directly grown on the first surface of the substrate.
- the substrate may be a sapphire wafer, a SiC wafer, an Si wafer or the like, and is not limited thereto.
- the semiconductor layer may also be named as an epitaxial layer, which may include a PN heterojunction, an active layer, and the like, which are well known in the art to form a constituent unit of a light-emitting semiconductor device, and thus the structure thereof will not be described herein. .
- the LED unit cell is a functional unit that can normally emit light under a certain working voltage, and, as mentioned above, each LED unit cell should be electrically isolated from each other.
- the foregoing unit cell includes a plurality of normal unit cells and a plurality of redundant unit cells
- the plurality of normal unit cells are divided into a plurality of multi-level cell groups arranged in parallel, and any multi-level cell group comprises a plurality of first parallel groups a arranged in series, and the selected M in any multi-level cell group
- the first parallel groups are also directly connected in series with the N second parallel groups via wires to form a series b, and the conduction voltages of all series groups are substantially the same.
- substantially consistent means that the variation of the on-voltage of each series group is within ⁇ 10%.
- any of the foregoing first parallel groups includes two or more normal unit cells arranged in parallel, and any second parallel group includes two or more redundant unit cells arranged in parallel, M is a positive integer, and N is 0 or a positive integer.
- a specific site is selected to be electrically connected to a working electrode of the device via a wire, that is, at each multi-level.
- Some or all of the first parallel groups in the cell group are connected in series to form a series group, and finally the turn-on voltages of all the series groups are substantially uniform.
- At least one matching resistor is connected to each series group, and the matching resistor can be implemented according to the foregoing implementation.
- the difference in the turn-on voltage of each series group is specifically adjusted, and finally the difference in the turn-on voltage of each series group is eliminated, so that the obtained wafer-level LED device has the best working stability and luminous efficiency.
- the preparation work may include:
- the tuple includes two or more first parallel groups arranged in series, and any of the first parallel groups includes two or more normal unit cells arranged in parallel;
- the second parallel group comprises two or more redundant unit cells arranged in parallel, M is a positive integer, and N is 0 or a positive integer.
- At least one matching resistor may be disposed in each series group.
- the electrical connection between the working electrode and the unit cell can be processed on each unit cell by various metal evaporation, deposition and micro-nano processing processes well known in the art. line.
- an emission light wavelength conversion structure in order to enable the obtained wafer-level LED device to have better light-emitting efficiency, etc., an emission light wavelength conversion structure, a reflective layer, an anti-reflection structure, an optical lens, or the like may be introduced into the device for packaging, in the present invention.
- the wafer-level LED device can be regarded as a large LED chip in fact, it is not necessary to separately package each unit cell, and only one package of the whole device is required, which greatly simplifies the packaging process. It also saves packaging materials.
- the cooling structure can be supplemented in the wafer-level LED devices obtained in the foregoing embodiments, such as the currently used heat sink, microfluidic cooling structure and the like.
- two cooling structures as described below may be employed, including:
- the cooling structure can be sealingly coupled to the substrate and the selected area of the second surface of the substrate is integrally exposed to the cooling medium flow chamber of the cooling structure, the selected region being at least A region of the first surface of the substrate on which the plurality of unit cells are distributed corresponds.
- the cooling structure can also be sealed to the substrate, but at least all of the unit cells distributed in the working circuit are exposed to the cooling medium flow chamber in the cooling structure.
- the wafer level LED chip includes a wafer-level substrate 11 and a plurality of functional unit cells 12 directly formed by an epitaxial layer grown on one side of the substrate, wherein the heat-dissipating housing is provided with a cavity 21 for storing a heat-conducting medium, and the crystal A partial region of one side of the circular semiconductor device corresponding to the functional unit cell is exposed within the cavity.
- Each of the foregoing functional unit cells may include a structural layer such as an n-type semiconductor 121, a p-type semiconductor 122, a light-emitting quantum well 123, and an insulating medium 124.
- an interconnect metal 13 or the like is disposed between the functional cells, and is electrically connected to the cathode 14, the anode 15, and the like.
- a reflective layer 16 may be connected to one side of the wafer-level LED chip exposed to the cavity, so that the functional unit cell is distributed on the other surface of the wafer-level LED chip.
- At least a heat dissipation mechanism may be distributed over a partial area of the wafer-level semiconductor device exposed to one side of the cavity.
- the heat dissipation mechanism may include a plurality of fin fins 171 connected to one side of the wafer level semiconductor device, and the other surface of the wafer level semiconductor device is distributed Functional unit cell.
- the heat dissipation mechanism may include a plurality of heat dissipation columns 172 connected to one side of the wafer level semiconductor device, and a function sheet is distributed on the other surface of the wafer level semiconductor device. Cell.
- a pressing block 51 may be further disposed in the heat dissipation structure, wherein a peripheral portion of the wafer level semiconductor device is fastened and clamped to the pressing block and the heat dissipation housing.
- a sealing member such as an O-ring 53 , is further disposed between the peripheral portion of the wafer-level semiconductor device and the pressing block and the heat dissipation housing.
- the clamp can also be fastened to the heat dissipation housing by fasteners such as bolts 52.
- the heat dissipation housing may be soldered to the wafer level semiconductor device.
- a solder layer 34 may be formed between the substrate and the heat dissipation housing by using solder to seal the substrate to the heat dissipation housing, thereby making the structure of the device simpler and more compact.
- the aforementioned heat transfer medium may be a material in a fluid form such as water, heat transfer oil or the like.
- a heat transfer medium inlet connected to the cavity may be disposed on the heat dissipation housing And the outlet so that the heat transfer medium can circulate quickly.
- the aforementioned heat conductive medium may also adopt other types of phase change materials such as water, acetone, alcohol, and the like.
- the heat dissipation housing can adopt a closed design.
- the phase change heat sink housing 23 may be distributed with a plurality of hollow heat dissipating fins 24, which are filled between the heat dissipating posts 172 on the back side of the wafer level semiconductor device during operation.
- the phase change heat dissipating liquid 61 is heated to form phase change steam 62, and enters the heat dissipating fin to exchange heat with the outside, and then recondenses into a phase change heat dissipating liquid to realize heat conduction.
- an anti-reflection mechanism may be disposed on the light-emitting surface of the device, which may be a photonic crystal structure, a large lens, a lenslet group, or the like.
- a back surface light-emitting structure design may be adopted, and a photonic crystal structure 421, a large lens 422, a small lens group 423, and the like may be disposed on the light-emitting surface, thereby improving light emission on the one hand.
- Efficiency on the other hand, can also expose the active area to the heat transfer medium, thereby further shortening the heat conduction path and improving heat dissipation efficiency.
- the LED device should use a transparent substrate such as sapphire.
- the heat conductive medium is preferably an insulating heat conductive medium such as heat transfer oil or the like.
- the wafer level semiconductor device can have the shortest heat dissipation path and the maximum heat dissipation performance, thereby improving the working stability of the device and prolonging its service life.
- the wafer level semiconductor device may further comprise a plug-in electrical connection structure, which may include an insulating substrate and an elastic conductive mechanism, wherein the elastic conductive mechanism is fixedly connected to the insulating substrate, wherein Forming a resilient clamping structure between the selected portion between the one end or both ends of the elastic conductive mechanism and the insulating substrate for holding and fixing the wafer level semiconductor device, when the wafer level semiconductor device is to be When the elastic clamping structure is inserted, a selected portion between one or both ends of the elastic conductive mechanism is further in electrical contact with a cathode or an anode of the wafer level semiconductor device.
- a plug-in electrical connection structure which may include an insulating substrate and an elastic conductive mechanism, wherein the elastic conductive mechanism is fixedly connected to the insulating substrate, wherein Forming a resilient clamping structure between the selected portion between the one end or both ends of the elastic conductive mechanism and the insulating substrate for holding and fixing the wafer level semiconductor device, when the wafer level semiconductor device is to be When the
- the elastic conductive mechanism includes a metal reed 33 , and one end of the metal reed is fixedly connected to the insulating base 31 , The other end is the active end.
- the other end of the metal reed has at least one arcuate structure, and when the wafer level LED device is inserted into the elastic clamping structure, at least one of the top ends of the arc structure Electrically contacting the cathode or anode of the wafer level LED device.
- the elastic conductive mechanism is fixedly connected to one end portion of the insulating base body, and the other end portion has a protruding portion, and the elastic portion forms the elasticity between the selected portion between one end and both ends of the elastic conductive mechanism. Clamping structure.
- the insulating substrate is in contact with the other surface of the substrate.
- the resilient conductive mechanism can be electrically connected to a power source via a wire (metal lead 32) distributed over the insulating substrate.
- the elastic clamping structure formed by the base can be simple and convenient to operate, does not damage the wafer-level semiconductor device, and the operator can insert and remove through the insulating substrate, thereby ensuring the personal safety of the operator, on the other hand, It avoids problems such as damage to wafer-level semiconductor devices due to factors such as static electricity from the human body.
- the method for fabricating a wafer level light emitting diode may include the following steps:
- Step 1 depositing a transparent conductive electrode ITO (indium tin oxide) on the LED epitaxial wafer;
- Step 2 The first time lithographic etching of the transparent conductive electrode ITO ensures that the uncovered photoresist region is corroded clean.
- Step 3 A thick silicon dioxide mask, a lithographically etched silicon dioxide mask sidewall exhibits a relatively sloped slope.
- Step 4 Etching the gallium nitride epitaxial layer with ICP (Inductively Coupled Plasma) and etching it to the insulating substrate.
- ICP Inductively Coupled Plasma
- Step 5 N mesa lithography, and then etch the gallium nitride epitaxial layer to the N-type heavily doped region by ICP.
- Step 6 Completely remove the mask by wet method.
- Step 7 Annealing.
- Step 8 Deposit an insulating dielectric layer.
- Step 9 Photolithography is performed for the fourth time and the insulating dielectric layer of the uncovered region of the photoresist is etched away, and the cleaning is ensured.
- Step 10 The last lithography, and deposition of metal and then stripping.
- the manufacturing method can effectively improve the yield of the wafer-level LED while improving the electrical and reliability performance of the device.
- the process is easy to control and fully compatible with existing processes.
- Step 3 step 4, and step 5 are performed sequentially, or may be performed in the order of step 5, step 3, and step 4.
- the step 5 etching the silicon dioxide mask is performed by first dry etching and then wet etching.
- step 7 is performed after steps 1-6.
- step 7 (annealing) can also be performed after step 2, and other steps are postponed.
- the insulating dielectric layer may be a sandwich structure of silicon dioxide/silicon nitride/silicon dioxide.
- the present invention can significantly reduce short circuit and leakage between LED single packages.
- the dry-wet etching etches a thick silicon dioxide mask, causing a large slope on the sidewall of the silicon dioxide, which is transferred to the gallium nitride layer by ICP etching, thereby reducing the disconnection of the interconnect metal at the climbing.
- a method of fabricating a wafer level light emitting diode can include:
- Step S1 The cleaned LED epitaxial wafer is immersed in aqua regia to remove the natural oxide layer and metal particles on the surface, then ultrasonically cleaned with deionized water, and finally blown dry with high pressure nitrogen gas. Then, ITO deposition was performed using an optical coater (see Fig. 15, a).
- Step S2 Photolithography and etching of the ITO (see FIG. 15, b), confirming that the ITO not covering the photoresist region is etched clean, removing the photoresist and cleaning.
- Step S3 PECVD ((Plasma Enhanced Chemical Vapor Deposition)) is used to deposit a certain thickness, for example, silicon dioxide having a thickness of about 2.5 to 3.5 ⁇ m, and performing isolation lithography and etching silicon dioxide.
- the silicon oxide is firstly etched and then wet etched to cause a 30 to 60 degree slope of the silicon dioxide and to remove the photoresist (see Figure 15, c).
- Step S4 Selecting appropriate ICP etching conditions, etching and etching GaN, so that the slope of the silicon dioxide can be transferred to the gallium nitride epitaxial layer (see FIG. 15, d). And to ensure that the isolation region GaN is completely etched clean.
- Step S5 N photolithography and etching.
- RIE reactive Ion Etching
- etching removes the silicon dioxide at the clean window, removes the photoresist, and etches about GaN by ICP (see FIG. 15, e).
- Step S6 The remaining silica is etched clean with BOE (Buffer Oxide Etcher).
- Step S7 Annealing in compressed air at 450 to 650 ° C (see Fig. 15, f).
- Step S8 Silica/silicon nitride/silicon dioxide was deposited as an insulating layer by PECVD (see Fig. 15, g).
- Step S9 The medium is photolithographically etched and the insulating dielectric layer of the uncovered region of the photoresist is etched away, and the cleaning is ensured. The photoresist is then removed (see Figure 15, h).
- Step S10 interconnect metal lithography, using electron beam evaporation to deposit Ti/Al/Ni/Al/Ni/Au as the interconnect metal. Finally, the non-interconnected metal is stripped off by ultrasonic (see Figure 15, i).
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Abstract
Description
Claims (39)
- 一种晶圆级半导体器件,其特征在于包括:晶圆级基片;形成于所述基片表面且并联设置的多个串联组,每一串联组包括串联设置的多个并联组,每一并联组包括并联设置的多个单胞,其中每一单胞均是由直接生长于所述基片表面的半导体层加工形成的独立功能单元;以及,导线,其至少电性连接于每一串联组中的一个选定并联组与所述半导体器件的一个电极之间和/或两个选定并联组之间,用以使所有串联组的导通电压基本一致。
- 根据权利要求1所述的晶圆级半导体器件,其特征在于,形成于所述基片表面的所有单胞包括多个正常单胞和多个冗余单胞,该多个正常单胞被排布为并联设置的多个多级单元组,任一多级单元组包括串联设置的多个第一并联组,并且任一多级单元组中选定的M个第一并联组还与N个第二并联组串联形成一串联组,其中,任一第一并联组包括并联设置的多个正常单胞,任一第二并联组包括并联设置的多个冗余单胞,M为正整数,N为0或正整数。
- 根据权利要求1所述的晶圆级半导体器件,其特征在于,至少一串联组中还设有至少一匹配电阻。
- 根据权利要求2所述的晶圆级半导体器件,其特征在于,至少一多级单元组中选定的两个以上第一并联组直接经过导线与至少一第二并联组串联形成串联组。
- 根据权利要求1所述的晶圆级半导体器件,其特征在于它还包含散热结构,所述散热结构包括与所述晶圆级半导体器件连接的至少一散热壳体,所述散热壳体内设有可储纳导热介质的空腔,且至少所述晶圆级半导体器件一面的至少与所述功能单胞相应的局部区域暴露于所述空腔内。
- 根据权利要求5所述的晶圆级半导体器件,其特征在于至少所述晶圆级半导体器件的暴露于所述空腔内的一面的至少局部区域上分布有散热机构。
- 根据权利要求6所述的晶圆级半导体器件,其特征在于所述散热机构包括至少连接于所述晶圆级半导体器件的一面上的复数片状和/或柱状散热部件。
- 根据权利要求5-7中任一项所述的晶圆级半导体器件,其特征在于所述散热结构包括并行排布在所述晶圆级半导体器件一面上的复数鳍状散热片或阵列分布在所述晶圆级半导体器件一面上的复数散热柱。
- 根据权利要求5-7中任一项所述的晶圆级半导体器件,其特征在于所述晶圆级半导体器件的暴露于所述空腔内的一面上还连接有反射层,所述功能单胞分布在所述晶圆级半导体器件的另一面上。
- 根据权利要求5-7中任一项所述的晶圆级半导体器件,其特征在于所述散热机构与所述晶圆级半导体器件的一面之间还设有反射层。
- 根据权利要求5-7中任一项所述的晶圆级半导体器件,其特征在于所述散热壳体上还分布有与所述空腔连通的导热介质入口和出口。
- 根据权利要求5-7中任一项所述的晶圆级半导体器件,其特征在于所述散热壳体具有封闭内腔,且所述散热壳体还具有复数散热翅片。
- 根据权利要求5-7中任一项所述的晶圆级半导体器件,其特征在于所述散热机构还包括压块,其中至少所述晶圆级半导体器件的周缘部被紧固夹持于所述压块与散热壳体之间,且至少所述晶圆级半导体器件的周缘部与所述压块与散热壳体之间还分别设有密封件。
- 根据权利要求13所述的晶圆级半导体器件,其特征在于所述散热机构还包括用以将所述压块与散热壳体紧固连接的紧固件。
- 根据权利要求5-7中任一项所述的晶圆级半导体器件,其特征在于所述散热壳体与所述晶圆级半导体器件焊接固定。
- 根据权利要求1-7、14中任一项所述的晶圆级半导体器件,其特征在于它还包含插拔式电连接结构,所述插拔式电连接结构包括绝缘基体以及弹性导电机构,所述弹性导电机构与绝缘基体固定连接,其中所述弹性导电机构一端部或两端之间的选定部位与绝缘基体之间形成有可供夹持固定所述晶圆级半导体器件的弹性夹持结构,当将所述晶圆级半导体器件***所述弹性夹持结构时,所述弹性导电机构一端或两端之间的选定部位还与所述晶圆级半导体器件的阴极或阳极电性接触。
- 根据权利要求16所述的晶圆级半导体器件,其特征在于所述弹性导电机构包括金属簧片,所述金属簧片一端部与绝缘基体固定连接,另一端部为活动端。
- 根据权利要求17所述的晶圆级半导体器件,其特征在于所述金属簧片另一端部具有至少一弧形结构,当将所述晶圆级半导体器件***所述弹性夹持结构时,其中至少一弧形结构的顶端部与所述晶圆级半导体器件的阴极或阳极电性接触。
- 根据权利要求16所述的晶圆级半导体器件,其特征在于所述弹性导电机构与所述绝缘基体的一端部固定连接,另一端部具有一凸出部,所述凸出部 与所述弹性导电机构一端或两端之间的选定部位之间形成所述弹性夹持结构。
- 根据权利要求16所述的晶圆级半导体器件,其特征在于所述弹性导电机构经分布在所述绝缘基体上的导线与电源电连接。
- 根据权利要求16所述的晶圆级半导体器件,其特征在于,当将所述晶圆级半导体器件***所述弹性夹持结构时,所述绝缘基体与所述基片另一面接触。
- 根据权利要求1-7、14、17-21中任一项所述的晶圆级半导体器件,其特征在于,所述晶圆级基片的直径在2英寸以上。
- 根据权利要求1所述的晶圆级半导体器件,其特征在于,所述串联组的导通电压为110V±20V、220V±40V或380V±70V。
- 根据权利要求1-7、14、17-21中任一项所述的晶圆级半导体器件,其特征在于,所述晶圆级半导体器件包括半导体激光器、LED或二极管。
- 根据权利要求24所述的晶圆级半导体器件,其特征在于所述晶圆级半导体器件为半导体发光器件,且所述半导体发光器件的出光面上还分布有减反增透机构,所述减反增透机构包括光子晶体结构或一个以上透镜机构。
- 权利要求1-25中任一项所述晶圆级半导体器件的制备方法,其特征在于包括:在晶圆级基片表面形成并联设置的多个串联组,其中每一串联组包括串联设置的多个并联组,每一并联组包括并联设置的多个单胞,而每一单胞均是由直接生长于所述基片表面的半导体层加工形成的独立功能单元;以及,至少以导线将每一串联组中的一个选定并联组与所述半导体器件的一个电极电连接和/或将每一串联组中的两个选定并联组电连接,从而使所有串联组的导通电压基本一致。
- 根据权利要求26所述晶圆级半导体器件的制备方法,其特征在于包括如下步骤:(1)提供第一表面生长有半导体层的晶圆级基片,即晶圆级LED外延片;(2)将所述半导体层加工形成多个单胞;(3)选取该多个单胞中的部分作为正常单胞,其余作为冗余单胞,并且将所有正常单胞分为两个以上多级单元组并联设置,任一多级单元组包括串联设置的两个以上第一并联组,以及,将任一多级单元组中选定M个第一并联组与N个第二并联组串联形成一串联组,使该两个以上串联组的导通电压基本一致,其中,任一第一并联组包括多个并联设置的正常单胞,任一第二并联组 包括并联设置的多个冗余单胞,M为正整数,N为0或正整数。
- 根据权利要求27所述晶圆级半导体器件的制备方法,其特征在于该方法包括:将任一多级单元组中选定的两个以上第一并联组直接经过导线与至少一第二并联组串联形成一串联组;或者,在至少一串联组中设置至少一匹配电阻。
- 根据权利要求27所述晶圆级半导体器件的制备方法,其特征在于该方法还包括:将所述基片与散热结构和/或插拔式电连接结构连接。
- 根据权利要求26-29中任一项所述晶圆级半导体器件的制备方法,其特征在于该方法还包括:(1)提供外延片,所述外延片包括所述基片和生长于所述基片上的半导体材料层;(2)在所述半导体材料层上形成透明导电层;(3)对透明导电层进行刻蚀,形成透明电极图形;(4)Ⅰ、在所述外延片上形成掩膜层,并对掩膜层的选定区域进行刻蚀,直至露出所述半导体材料层,并使被刻蚀区域的掩膜层侧壁形成30°-60°的斜坡,对从掩膜层中暴露出的半导体材料层局部进行刻蚀,直至露出所述基片,从而在半导体材料层中形成彼此隔离的功能单胞基体,对从掩膜层中暴露出的半导体材料层局部继续进行刻蚀,从而在各功能单胞基体内形成台面结构;或者,Ⅱ、对从掩膜层中暴露出的半导体材料层局部继续进行刻蚀,从而在各功能单胞基体内形成台面结构,在所述外延片上形成掩膜层,并对掩膜层的选定区域进行刻蚀,直至露出所述半导体材料层,并使被刻蚀区域的掩膜层侧壁形成30°-60°的斜坡,对从掩膜层中暴露出的半导体材料层局部进行刻蚀,直至露出所述基片,从而在半导体材料层中形成彼此隔离的功能单胞基体;(5)将所述掩膜层完全去除,再于所述外延层上形成绝缘介质层;(6)对所述绝缘介质层的选定区域进行刻蚀,从而各功能单胞基体上用以沉积互联金属的互联金属区露出;(7)在所述外延片上沉积互联金属,再剥离未沉积在互联金属区的互联金属,从而将相配合的功能单胞电连接。
- 根据权利要求30所述的晶圆级半导体发光器件的制造方法,其特征在于:步骤(3)还包括:在形成透明电极图形后,对所形成的器件进行退火;或者,步骤(5)还包括:将所述掩膜层完全去除后,退火,再于所述外延层上形成绝缘介质层。
- 根据权利要求30所述的晶圆级半导体发光器件的制造方法,其特征在于步骤(3)包括:采用光刻工艺刻蚀所述透明导电层而形成透明导电图形。
- 根据权利要求30所述的晶圆级半导体发光器件的制造方法,其特征在于步骤(4)包括:采用光刻工艺刻蚀所述掩膜层直至露出所述半导体材料层。
- 根据权利要求30所述的晶圆级半导体发光器件的制造方法,其特征在于步骤(4)中所述掩膜层采用二氧化硅掩膜层。
- 根据权利要求30所述的晶圆级半导体发光器件的制造方法,其特征在于步骤(4)包括:采用干法工艺对从掩膜层中暴露出的半导体材料层局部进行刻蚀,直至露出所述基片。
- 根据权利要求30所述的晶圆级半导体发光器件的制造方法,其特征在于步骤(4)包括:将窗口处的掩膜层采用干法刻蚀和/或湿法刻蚀工艺除净,之后利用干法刻蚀工艺对从掩膜层中暴露出的半导体材料层局部继续进行刻蚀,从而在各功能单胞基体内形成台面结构。
- 根据权利要求30所述的晶圆级半导体发光器件的制造方法,其特征在于所述透明导电层的材质选自ITO、石墨烯或碳纳米管膜。
- 根据权利要求30所述的晶圆级半导体发光器件的制造方法,其特征在于所述基片选用绝缘晶圆,所述绝缘晶圆包括蓝宝石晶圆。
- 根据权利要求30所述的晶圆级半导体发光器件的制造方法,其特征在于所述绝缘介质层包含由二氧化硅层/氮化硅层/二氧化硅层形成的三明治结构。
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