WO2015087450A1 - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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Publication number
WO2015087450A1
WO2015087450A1 PCT/JP2013/083503 JP2013083503W WO2015087450A1 WO 2015087450 A1 WO2015087450 A1 WO 2015087450A1 JP 2013083503 W JP2013083503 W JP 2013083503W WO 2015087450 A1 WO2015087450 A1 WO 2015087450A1
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Prior art keywords
electrode
pad electrode
chip
semiconductor device
semiconductor
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PCT/JP2013/083503
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French (fr)
Japanese (ja)
Inventor
白田　理一郎
大場　隆之
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株式会社Ｗｏｗリサーチセンター
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Priority to CN201380081522.2A priority Critical patent/CN105900233A/en
Priority to PCT/JP2013/083503 priority patent/WO2015087450A1/en
Publication of WO2015087450A1 publication Critical patent/WO2015087450A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof.
  • MCP Multi-Chip-Package
  • eMMC embedded Multi-Media Card
  • FIG. 1 is a schematic view illustrating a conventional semiconductor device.
  • a semiconductor device 100X is an MCP package in which a plurality of NAND flash memory chips 101 and a NAND controller chip 102 are connected.
  • the NAND flash memory chips 101 are stacked at different positions to expose the bonding connection terminals (pad electrodes) of the chips in each layer, and the terminals of each chip are connected to the lowermost package substrate 109 (lead frame or FBGA). Bonding wires 110 are used for bonding to terminals of substrates such as Fine pitch Ball Grid Array).
  • the terminals of the NAND controller chip 102 are also bonded to the package substrate 109 with bonding wires 110.
  • the stacked NAND flash memory chip 101 is electrically connected to the NAND controller chip 102, and the operation is managed by the NAND controller chip 102.
  • the NAND controller chip 102 has input / output terminals for connection to devices outside the package in addition to the connection terminals to the NAND flash memory chip 101, and these input / output terminals are connected to the package substrate 109 by bonding wires 110. Bonded and further connected to the pins 103 of the semiconductor device 100X through the package substrate 109.
  • Solid State Drive Solid State Drive
  • each chip must be connected from the pad electrode to the terminal of the package substrate 109 by the bonding wire 110.
  • the bonding wire 110 In order to form 110, a certain amount of margin in the height direction, a margin for shifting the chip in the lateral direction, and a margin for bonding the package substrate 109 are required.
  • the number of chips that can be stacked is limited due to wire bonding restrictions, and it is difficult to realize a semiconductor device (for example, a large-capacity nonvolatile memory) in which a large number of semiconductor chips (for example, NAND flash memory chips) are stored in a small package.
  • a semiconductor device for example, a large-capacity nonvolatile memory
  • semiconductor chips for example, NAND flash memory chips
  • the present invention has been made in view of the above points, and an object of the present invention is to provide a small-sized and large-capacity semiconductor device and the like.
  • the semiconductor device includes a stacked body in which a plurality of semiconductor chips are stacked, and each of the semiconductor chips stacked on the lowermost semiconductor chip of the stacked body in the thickness direction so as to pass through the lowermost semiconductor chip.
  • a through electrode connected to the pad electrode, and at least one of the power line and the signal line of the multilayer body is commonly connected to the semiconductor chip constituting the multilayer body via the through electrode. Is a requirement.
  • a small and large-capacity semiconductor device or the like can be provided.
  • FIG. 1 is a perspective view illustrating the concept of a semiconductor device according to a first embodiment.
  • FIG. 3 is a plan view illustrating an example in which no bump electrode is used in the semiconductor device of FIG. 2. It is sectional drawing which follows the AA line of FIG. 3A.
  • FIG. 3 is a plan view showing an example when bump electrodes are used in the semiconductor device of FIG. 2.
  • FIG. 4B is a sectional view taken along line AA in FIG. 4A.
  • FIG. 9 is a cross-sectional view illustrating the case where TSVs of pad electrodes of stacked memory chips are connected to terminals of a package (part 1); FIG.
  • FIG. 14 is a cross-sectional view (part 2) illustrating the case where the TSVs of the pad electrodes of the stacked memory chips are connected to the terminals of the package.
  • FIG. 4 is a plan view showing an example when a controller chip is added to the semiconductor device of FIG. 3. It is sectional drawing which follows the BB line of FIG. 6A. It is a schematic diagram which shows a mode that the memory chip and the controller chip were mutually connected.
  • FIG. 4 is a cross-sectional view showing another example when a controller chip is added to the semiconductor device of FIG. 3. It is a figure explaining selection of a memory chip by an address signal. It is FIG. (1) explaining the method to set a chip address. It is FIG. (2) explaining the method to set a chip address.
  • FIG. (1) explaining the cutting
  • FIG. (2) explaining the cutting
  • FIG. 6 is a diagram (part 1) illustrating a chip address setting method;
  • FIG. 3 is a second diagram illustrating a chip address setting method; It is sectional drawing corresponding to FIG. 15A.
  • FIG. 15B is a plan view corresponding to FIG. 15B.
  • FIG. 11 is a diagram (part 1) illustrating an example of a process of creating two or more TSV regions in one pad.
  • FIG. 11 is a diagram (part 2) illustrating an example of a process of creating two or more TSV regions in one pad.
  • FIG. 10 is a diagram (No. 3) illustrating an example of a process of creating two or more TSV regions in one pad.
  • FIG. 14 is a diagram (No.
  • TSV through silicon vias
  • a new chip selection method was devised to operate the desired chip at that time. Since exactly the same NAND flash memory chips are stacked, a unique chip address must be assigned to each chip so that one NAND flash memory chip to be operated by the NAND controller can be selected. A chip address signal is output from the NAND controller, and only the NAND flash memory chip that matches the chip address signal enters the operation mode, and the other chips enter the non-selection / pause mode.
  • FIG. 2 is a perspective view illustrating the concept of the semiconductor device according to the first embodiment.
  • the semiconductor device 100A according to the first embodiment in a stacked body in which a plurality of NAND flash memory chips 101 (hereinafter simply referred to as memory chips 101) are stacked,
  • the pad electrodes located at substantially overlapping positions in plan view are electrically connected by a common TSV 201 (through electrode).
  • the power supply lines Vcc and Vss and the input / output signal lines necessary for operating each memory chip 101 are commonly connected to all the memory chips 101 stacked through the corresponding TSV 201.
  • FIGS. 3A and 3B are diagrams showing an example in which no bump electrode is used (bump-less) in the semiconductor device 100A of FIG. 2, FIG. 3A is a plan view, and FIG. 3B is a line AA in FIG. 3A. It is sectional drawing which follows.
  • a plurality of memory chips 101a are stacked on the lowermost memory chip 101b, and a stacked body is configured by the memory chips 101a and 101b.
  • the semiconductor device shown in FIGS. 3A and 3B includes a TSV 201 (through electrode) that penetrates each memory chip 101a stacked on the memory chip 101b in the thickness direction and is connected to the pad electrode 204 of the lowermost memory chip 101b. have.
  • the TSV 201 of each memory chip 101a is formed on the pad electrode 204 of each memory chip 101a.
  • the metal layer 202 is embedded in the center of the hole penetrating each memory chip 101a, and the insulating film 203 covers the outside of the metal layer 202.
  • the insulating film 203 insulates the hole penetrating the memory chip 101a from the metal layer 202 embedded in the hole.
  • the memory chips 101a are simply referred to as the memory chips 101 when it is not necessary to distinguish between the memory chips 101a or the memory chips 101a and 101b.
  • An adhesive layer 205 (insulating layer) is formed between the stacked memory chips 101.
  • Each TSV 201 penetrates from the stacked uppermost memory chip 101a to the second memory chip 101a one layer above the memory chip 101b, including each adhesive layer 205.
  • the pad electrodes 204 of each memory chip 101a and memory chip 101b are connected to the metal layer 202 in the TSV 201.
  • the TSVs 201 of the memory chips 101a that are vertically adjacent to each other are directly connected to each other.
  • each TSV 201 has a structure in which a metal layer 202 is embedded in the center of a hole penetrating the stacked memory chip 101a, and an insulating film 203 covers the outside of the metal layer 202.
  • the insulating film 203 insulates the metal layer 202 from the hole penetrating the memory chip 101a.
  • An adhesive layer 212 (insulating layer) is formed between the stacked memory chips 101.
  • Micro-bumps 213 (bump electrodes) are formed between the TSVs 201 of the stacked memory chips 101a and between the TSV 201 of the second-layer memory chip 101a and the pad electrodes 204 of the memory chip 101b. Yes.
  • Each TSV 201 penetrates from the uppermost stacked memory chip 101a to the second-layer memory chip 101a one layer above the memory chip 101b.
  • the pad electrode 204 of each memory chip 101 a and memory chip 101 b is connected to the metal layer 202 in the TSV 201.
  • the TSVs 201 of the memory chips 101a adjacent in the vertical direction are connected to each other via the bump electrodes.
  • the pad electrode 204 and the metal layer 202 are electrically connected, there may be a planar positional shift as shown in FIG. 4A.
  • the memory chip 101a to be stacked is made by thinly cutting a semiconductor substrate such as a silicon substrate so that many chips can be stacked.
  • the memory chip 101b in the lowermost layer may be made thick to be used as a substitute for a package structural material.
  • the thickness of the memory chip 101a to be stacked can be, for example, about 2 ⁇ m to 100 ⁇ m, but is preferably about 3 ⁇ m to 10 ⁇ m. This is because when the substrate volume is reduced, the TSV processing time is significantly shortened, and the aspect ratio is relaxed by thinning, and the embedding property and coverage are improved.
  • the memory chip 101b may be thicker than the memory chip 101a.
  • the power supply lines (VCC, VSS) and the input / output signal lines necessary for operating the memory chip 101 are commonly connected to all the memory chips 101 constituting the stacked body via the corresponding TSV 201. Yes. Then, the power supply line and the input / output signal line are taken out from the uppermost memory chip 101a to the external connection terminal (pin) of the package.
  • any desired memory chip in the stacked memory chips can be selected and operated by applying a desired potential to the power supply line and supplying a necessary signal to the signal line.
  • the power supply line and the input / output signal line are commonly connected to all the memory chips 101 constituting the stacked body via the TSV 201, but only one of the power supply line and the signal line is connected. It is also possible to adopt a configuration in which all memory chips 101 constituting the stacked body are commonly connected via the TSV201.
  • 5A and 5B are cross-sectional views illustrating the case where the TSV of the pad electrode of the stacked memory chip is connected to the terminal of the package.
  • 5A and 5B correspond to the case of bumpless, but the same applies to the case of using bumps.
  • the memory chip 101 has power supply (Vcc, Vss) pins, I / O pins, and input / output signal pins (CE, WE, WP, R / B, etc.) related to various operation modes.
  • TSVs 201 are provided at the pad electrodes 204 to connect the memory chips 101 in common, and are connected to the external connection terminals 302 of the package.
  • the TSV 201 of the pad electrode 204 of the uppermost memory chip 101 may be connected to the external connection terminal 302 of the package, or the lowermost memory chip 101 may be connected to the package as shown in FIG. 5B. It may be connected to the external connection terminal 302. 5A and 5B, the connection wiring 303 in the package substrate 301 for connecting the metal material of the TSV 201 of the pad electrode 204 of the memory chip 101 and the external connection terminal 302 of the package is drawn so as to extend upward or downward as it is.
  • the wiring board 301 may have a wiring portion running sideways.
  • FIGS. 6A and 6B are diagrams illustrating an example where a NAND controller chip (a semiconductor chip of a different type from the memory chip) is added to the semiconductor device of FIG. 3, and FIG. 6A is a plan view of the plane P of FIG. 6B. 6B is a cross-sectional view taken along line BB in FIG. 6A.
  • FIG. 7 is a schematic diagram showing a state in which the memory chip 101 and the NAND controller chip 102 in FIGS. 6A and 6B are connected to each other.
  • a NAND controller chip 102 (hereinafter simply referred to as a controller chip 102) that controls the memory chip 101 is also enclosed in the same package. preferable.
  • the pad electrode 204 of the uppermost memory chip 101 a and the pad electrode 204 c of the controller chip 102 can be electrically connected to be output as the external connection terminal 302 of the controller chip 102 via the connection wiring 303.
  • the controller chip 102 may be the lowermost layer, but since the controller chip 102 is usually smaller than the memory chip 101, the uppermost layer is preferred.
  • the insulating layer 309 can be formed on the periphery of the controller chip 102.
  • the external connection terminal 302 of the package is output from the controller chip 102, and the terminal connected to the memory chip 101 of the controller chip 102 is connected to the pad electrode 204 of the memory chip 101 by the TSV 201.
  • FIG. 6A shows the upper surface of the controller chip 102 (surface P in which the circuit is formed in FIG. 6B), and the BB line is applied to both the pad electrode 204c connected to the memory chip 101 and the pad electrode 204c connected to the terminal of the package. It depends. 6A and 6B, for the sake of simplicity, the arrangement of the pad electrodes connected to the memory chip 101 is the same as the pad electrodes of the memory chip 101. If they are different, an interface chip is inserted between them. do it.
  • the controller chip 102 is stacked on the uppermost memory chip 101 via the adhesive layer 205.
  • the signal terminal 305 to be connected to the memory chip 101 of the controller chip 102 is connected to the pad electrode 304 of the uppermost memory chip 101 via the bonding wire 110.
  • the signal terminal 306 to be connected to the external connection terminal of the controller chip 102 is connected to the bonding pad electrode 307 of the package substrate 301 via the bonding wire 110.
  • the pad electrode 307 is connected to the pin 103 of the semiconductor device 100B through the connection wiring 303.
  • the memory chips are connected to each other through the TSV, and the conventional technique of wire bonding is not used.
  • a large-capacity semiconductor memory device can be realized with a much thinner and smaller package.
  • each memory chip stacked on the lowermost memory chip of the stacked body in which a plurality of memory chips are stacked has a TSV penetrating in the thickness direction and connected to the pad electrode of the lowermost memory chip.
  • at least one of the power supply line and the signal line of the stacked body is commonly connected to all the memory chips constituting the stacked body through the TSV. Therefore, the TSV process is simplified, and a low cost and high yield TSV connection can be realized.
  • a controller chip which is a semiconductor chip of a different type from the memory chips constituting the stacked body, can be incorporated in the same package as the stacked body.
  • the incorporation of the controller chip is not limited to the TSV technology, and may be performed by a wire bonding method.
  • the memory address inside the chip is inputted from the I / O terminal, but normally addresses corresponding to the number of memory cells inside the memory chip are inputted.
  • a chip address for selecting a higher-order memory chip is not used. Even one memory chip can be selected.
  • this upper address setting needs to be set in advance by a wafer test (WT) (internal fuse memory writing or the like), which makes management difficult, and causes a problem of a power source large current peak at power-on, which will be described later.
  • WT wafer test
  • a chip address indicating how many layers of each memory chip are stacked is set in each memory chip 101. Note that an address is set for each memory chip 101 before the memory chips 101 are stacked. A specific method is described below.
  • the memory chip 101 has a chip address pin AINj (j represents an integer such as 0, 1, 2, etc., and has more than the number necessary for the chip address. For example, if there are 8 chips, at least 0, 1, 2)
  • a plurality of predetermined potential comparison circuits 333 are arranged in the memory chip. Each potential comparison circuit 333 is connected to one chip selection circuit 334.
  • the potential comparison circuit 333 is a circuit that determines whether or not the chip address matches the signal input via the TSV, and has two input terminals. One input terminal of the potential comparison circuit 333 is connected to the chip address pin AINj, and the other input terminal of the potential comparison circuit 333 has two wirings (a wiring VH having a high level potential and a low level potential). Wiring VL). Note that CAj represents the potential of the other input terminal of the potential comparison circuit 333.
  • each wiring may be provided with a fuse element and cut as necessary.
  • the potential comparison circuit 333 illustrated in FIG. 10B (b) is an Ex-OR (Exclusive OR) circuit.
  • a chip address of a predetermined memory chip 101 is set depending on which one of the high level (VH, for example, Vcc) or low level (VL, for example, Vss) potential lines is cut. For example, if three sets of this mechanism are prepared, a combination of 3 bits can be made and a total of 8 chips can be selected. This combination of cutting differs between the stacked memory chips, so that there is no same thing.
  • the chip address AINj is connected to the address signal 331 in FIG.
  • the chip address signal AINn (n also represents an integer similar to j above) output from the controller chip 102 and the high-level or low-level wiring (VH and VL) is compared, and if both are high or low, a low level signal (low) is output from the output terminal MAn. If the two levels are different, a high level signal (high) is output from the output terminal MAn.
  • the output line MAm (m also represents an integer similar to j and n) from each potential comparison circuit 333 is an input to the chip selection circuit 334.
  • the chip selection circuit 334 may output a low level potential signal (low) from the output terminal AMatch when all the input lines become high level, and recognize that the present memory chip 101 is selected. .
  • the high-level / low-level potential line cutting combination CAj is input to the delay circuit of the power-on reset circuit, so that the power-on start timing of each memory chip can be shifted little by little.
  • the peak of the power supply current at the time of ON can be lowered. This is very important in integrating a large number of semiconductor memory chips, and it is possible to reduce the possibility of noise caused by a large current and malfunction due to a power supply voltage drop and a ground voltage rise.
  • FIG. 11A is a block diagram illustrating a part of the internal circuit of the memory chip.
  • a power-on detection circuit 342 that detects the voltage of the power supply Vcc and an initial setting operation circuit 344 that performs an initial setting operation of the memory chip 101 in response to the detection signal are usually provided in the memory chip 101.
  • a delay circuit 343 controlled by a chip address signal CAj formed in the chip described in FIG. 10A or the like is inserted in the meantime by the number of CAj (or only a few higher ranks).
  • FIG. 11B is a block diagram illustrating a delay circuit built in the memory chip.
  • the delay element 353 is switched by a switch circuit 352 made of a MOS transistor controlled by a signal of CAj between the case where the delay element 353 is short-circuited between IN and OUT, and the case where the delay works without being short-circuited. Can do.
  • An inverter 351 inverts the voltage level of the signal CAj, and 352 forms a switch circuit in which P-channel and N-channel MOS transistors are connected in parallel.
  • Reference numeral 354 denotes a buffer circuit.
  • FIG. 12 is a diagram for explaining the effect when a delay circuit is mounted, and an example in which eight layers of memory chips 101 are stacked is explained.
  • the top diagram shows the rise (power-on) of the power supply Vcc
  • the second diagram shows the power supply current Icc of the first-layer memory chip 101
  • 3 The second diagram shows the power supply current Icc of the second-layer memory chip 101
  • the fourth diagram shows the power-supply current Icc of the eighth-layer memory chip 101
  • the fifth (bottom) diagram shows the total (eight memory chips).
  • 101) is a power supply current Icc.
  • the power supply current Icc of the memory chips 101 in the third to seventh layers is not shown.
  • FIG. 12 (a) shows an example in which a conventional delay circuit is not installed. All memory chips 101 start operating from the time when the power supply Vcc exceeds the power-on detection voltage, and the power supply current Icc has one peak. This is almost 8 times that of the memory chip.
  • FIG. 12B shows a case in which the delay circuit shown in FIGS. 11A and 11B is mounted.
  • Each memory chip has the first one, one no delay from the time when the power supply Vcc exceeds the power-on detection voltage.
  • Three memory chips with delays (not shown in FIG. 12), three memory chips with two delays (Delay-2 in FIG. 12), and one memory chip with three delays (Delay-2 in FIG. 12) Since the initial setting operation is sequentially started with Delay-8) in FIG. 12, the peak of the power supply current Icc is almost half that of the conventional one.
  • which layer of memory chip is accessed can be set at the time of stacking, so that troublesome management after the wafer test (WT) can be avoided.
  • a plurality of delay circuits are provided between the power-on detection circuit for the power supply voltage and the initial setting operation circuit, and the chip address controls the delay circuit to have a delay corresponding to the chip address. Since a predetermined delay time can be set before the setting operation, the problem of a large power supply current peak at power-on can also be avoided. Furthermore, since the memory chips other than the memory chip to be accessed can be set in the standby mode, the overall power consumption can be reduced.
  • each memory chip is stacked in units of wafers, TSVs are formed and connected in units of wafers, and then separated (separated) and packaged.
  • Laminated in wafer units TSVs are formed and connected at once in a laminated wafer state, and then separated (separated) and packaged, or laminated in wafer units and TSVs in wafer units. are preferably formed and connected, separated after being packaged in wafer units (separated).
  • defective chips are included in the stacked memory chips.
  • the leakage current between pins is large, the operation of other memory chips is also affected, and in the worst case, the operation is not performed.
  • the DC leakage current of each memory chip on the wafer is monitored. If a current exceeding a specified value flows, as shown in FIGS. 13A and 13B, in order to inactivate the defective chip, the wiring 401 related to the current or the wiring to be connected to all the TSVs is cut. .
  • This embodiment shows a method of cutting a wiring as a fuse. Thereafter, wafers of memory chips including defective chips are stacked.
  • FIG. 13A is a plan view
  • FIG. 13B is a cross-sectional view taken along the line CC of FIG. 13A
  • FIG. 13B (a) shows the state before cutting the wiring 401
  • FIG. 13B (b) shows the wiring 401. After cutting is schematically shown by a broken line.
  • Reference numeral 402 denotes an insulating film.
  • a memory chip having a large leak current is selected from the stacked memory chips and electrically Since it can be eliminated, it is possible to prevent malfunction due to leakage current and increase in current consumption.
  • a memory chip (defective chip) determined to be defective needs to be electrically insulated from a common TSV.
  • a selected pad electrode pad electrode of the defective chip
  • a TSV penetrating the selected pad electrode pad electrode of the defective chip
  • FIG. 14A (a) a plurality of wafers 500 having memory chips to be stacked by wafer-on-wafer technology are prepared.
  • an electrical test wafer test
  • FIG. 14A (a) good / bad determination is made on a memory chip basis (OK is a non-defective chip, NG indicates a defective chip).
  • NG defective chips
  • positional information within the wafer is stored in addition to the defect information.
  • FIG. 14A (b) based on the position information of the defective chip (NG), over all the pad electrode openings 204W of the defective chip (NG) to which the TSV is to be formed and connected.
  • An insulating film 502 is selectively formed.
  • the insulating film 502 is not formed on the pad electrode opening 204W of the non-defective chip (OK).
  • SOG spin-on-glass SOG
  • the insulating layers 503 and 504 are formed on the lowermost wafer in which insulating layers 503 and 504 (passivation film) such as polyimide covering the pad electrode 204P are formed on the silicon substrate 505. A plurality of through holes (openings) that expose the surface of the pad electrode 204P are formed. Then, for the defective chip (NG) shown in FIG. 14B (a), SOG which is an insulating material to be the insulating film 502 is applied to a predetermined region including the inside of the opening.
  • NG defective chip
  • the metal layer 506 is selectively formed on the pad electrode 204P where the TSV is formed on the wafer to be used as the lowermost layer among the wafers to be laminated.
  • a barrier metal such as Ti / TiN is generated by sputtering or the like, and the metal layer 506 made of Cu or the like is sufficiently embedded in the barrier metal by an electroless plating method or the like. Form to the extent.
  • CMP Chemical Mechanical Polishing
  • the pad electrode 204P of the defective chip (NG) shown in FIG. 14C (a) has an insulating film 502 formed by inkjet printing or the like. Therefore, in the defective chip (NG), the metal layer 506 is formed over the pad electrode 204P with the insulating film 502 interposed therebetween. That is, in the defective chip (NG), the pad electrode 204P and the metal layer 506 are not electrically connected. On the other hand, in the non-defective chip (OK) shown in FIG. 14C (b), since the insulating film 502 does not exist, the pad electrode 204P and the metal layer 506 are in contact with each other and become conductive.
  • FIG. 14D the process proceeds to the wafer stacking process.
  • a second wafer reinforced with glass or the like and cut into a predetermined thickness is laminated on the lowermost wafer via an adhesive layer 205.
  • a plurality of through holes (first through holes) that penetrate the insulating layers 503 and 504 and expose the surface of the pad electrode 204P are formed.
  • FIG. 14D (a) shows a case where a non-defective chip (OK) is stacked on the first-layer defective chip (NG), and
  • FIG. 14D (b) shows a defect on the first-layer defective chip (OK).
  • a case where chips (NG) are stacked is shown.
  • the insulating film 502 is formed on the pad electrode 204P exposed in the through hole (first through hole).
  • a photoresist 510 is applied on the entire surface, and the resist in a region where a TSV is to be formed is removed by a normal photolithography technique using a mask.
  • the insulating film 502, the pad electrode 204P, the insulating layer 504, the silicon substrate 505, and the adhesive layer 205 between the wafers are etched by plasma using the photoresist 510 as a mask, and the first layer wafer
  • a TSV hole (second through hole) is formed. That is, in the second layer wafer, the second layer wafer is penetrated in the thickness direction in each through hole (first through hole), and the surface of the metal layer 506 formed on the lowermost wafer is exposed.
  • a through hole (second through hole) is formed.
  • an insulating film 203 such as an oxide film for electrically insulating the side walls and the like of the TSV holes (first through hole and second through hole), for example, It is formed by low temperature plasma CVD.
  • the insulating film 203 is etched by etching the insulating film 203, and the insulating film 203 remains on the side wall.
  • the insulating film 203 in the portion connected to the TSV is etched to expose the surface of the pad electrode 204P.
  • the surface of the pad electrode 204P is covered with the insulating film 502 and is not exposed to the outside.
  • the insulating film 203 (second insulating film) is formed only on the side wall of the TSV hole (the side wall of the first through hole and the side wall of the second through hole).
  • a barrier metal such as Ti / TiN is formed to complete the TSV, and the TSV is embedded with a metal layer 202 such as Cu by electroless plating or the like. Further, the metal layer 202 other than the portion connected to the TSV and the pad electrode 204P of the chip is removed by using a normal CMP technique. Accordingly, in the second layer wafer, the TSV hole (in the first through hole and the second through hole) is electrically connected to the metal layer 506 formed in the lowermost wafer, and one TSV A metal layer 202 (second metal layer) forming a part is formed, and the lamination of the second wafer is completed.
  • the pad electrode 204P of the chip and the metal layer 202 of the TSV are electrically connected, but in the defective chip (NG), the pad electrode 204P is covered with the insulating film 502. Therefore, it is electrically insulated from the TSV metal layer 202.
  • a semiconductor memory device in which a plurality of wafers in which defective chips (NG) are selectively insulated from TSVs are stacked by sequentially stacking the same processes for the third and subsequent wafers. Device) is formed.
  • chips (defective chips) determined to be defective in the stacked memory chips can be selectively electrically excluded. Further, the step of cutting the fuse as in the third embodiment is not necessary, and since the ink jet printing technique is used to selectively form the insulating film, the manufacturing cost can be greatly reduced.
  • the fourth embodiment can be applied to the chip address designation method for selecting which memory chip to select and the writing of the signature indicating the number of layers shown in the second embodiment.
  • the memory selected in consideration of the coincidence of the chip address held in the stacked chip and the address output from the controller chip A method of determining a chip is used, which is similar to a method having an address pin such as DRAM or SRAM.
  • a NAND flash memory does not have an address pin, and the address of a memory cell in the chip is input as input data from an input / output pin. Therefore, a system in which the chip address is extended and assigned to the upper bits of the input data is used. It is preferable to take.
  • a method for setting the chip address of the NAND flash memory it is possible to use a method in which the power supply voltage Vcc or the ground voltage Vss is set by connecting several input pads prepared therefor through wire bonding. Note that the address input AINn in FIG. 10B (b) can be given from the input data through a chip internal circuit.
  • FIG. 15A and 15B show chip address setting methods using typical bonding options.
  • a pull-up circuit 423 is attached to the input circuit, and only the pad electrode 204P to be connected to the pad 411 (ground voltage Vss) is connected by a bonding wire.
  • Reference numeral 421 denotes a pull-up transistor, and 422 denotes a buffer circuit.
  • each pad electrode 204P is connected to either the high level or the low level by a bonding wire.
  • a chip selection CE divided into two signal chip select 1 (CE1) and chip select 2 (CE2) for bonding option.
  • the pad electrode to be connected to a predetermined voltage ground voltage Vss or power supply voltage Vcc
  • Vss ground voltage
  • Vcc power supply voltage
  • one TSV may be prepared for each pad electrode, and the “connecting and insulating to TSV” method of the fourth embodiment may be applied.
  • a cross-sectional view of this embodiment is shown in FIG. Since FIG. 15A is a pull-up circuit, TSV in FIG. 16 becomes the ground voltage Vss.
  • each memory chip has a pad electrode for setting a chip address, a pull-up circuit or pull-down circuit for an input unit, and a pad electrode for setting a chip address, and a predetermined voltage (ground voltage Vss or A TSV connected to the power supply voltage Vcc) is provided.
  • a predetermined voltage ground voltage Vss or A TSV connected to the power supply voltage Vcc
  • An arbitrary chip address can be set by selectively applying the structure of electrically insulating the pad electrode and TSV of the fourth embodiment to the pad electrode for setting the chip address. it can.
  • the pad 411 at the power supply voltage Vcc level or the ground voltage Vss level is provided on the chip address setting input pad 204P in the memory chip 101, respectively.
  • the pad 411 at the power supply voltage Vcc level or the ground voltage Vss level is provided on the chip address setting input pad 204P in the memory chip 101, respectively.
  • the pad 411 and the pad electrode shown in FIG. Connection can be abolished.
  • a specific method is shown below.
  • FIG. 17A is a diagram schematically showing a state in which two pad electrodes 204P having a normal size are arranged adjacent to each other and connected to a common wiring.
  • a TSV 201a penetrating one of two adjacent pad electrodes 204P and a TSV 201b penetrating the other are formed for an input of 1 bit of a chip address.
  • Bit-0 (CA0), Bit-1 (CA1), and Bit-2 (CA2) in FIG. 17A are connected to the input CAj of the potential comparison circuit 333 (see FIGS. 10A and 10B).
  • FIG. 17B which is a cross-sectional view taken along the line DD in FIG. 17A
  • TSV 201a connected to power supply voltage Vcc on adjacent pad electrode 204P is formed for each wafer and each chip.
  • An insulating film 502 is formed by selectively applying SOG to the opening or the opening where the TSV 201b connected to the ground voltage Vss is formed by using inkjet printing.
  • the potential of each bit signal CAj can be selected.
  • Bit-0 (CA0), Bit-1 (CA1), and Bit-2 (CA2) selectively connected to the TSV 201a or 201b are connected to the input CAj of the potential comparison circuit 333 (see FIGS. 10A and 10B). Is done.
  • the chip address CA0 of bit 0 is “0” for the first layer, “0” for the second layer, and “1” for the third layer.
  • the insulating film 502 is formed in the opening where the TSV 201a connected to the power supply voltage Vcc is formed.
  • the insulating film 502 may be formed in the opening where the TSV 201b connected to the ground voltage Vss is formed.
  • the TSVs 201a and 201b connected to the pad electrode 204P can be connected to the external connection terminal 302 via the connection wirings 303a and 303b in the package substrate 301.
  • the insulating films 203 and 502 shown in FIG. 17B and the like are not shown.
  • this process is equivalent to the process for the defective chip of the fourth embodiment, when applying SOG to the pad electrode connected to the TSV of the defective chip in the fourth embodiment, this chip address or signature is simultaneously applied. This is realized only by applying SOG to a necessary portion of the pad electrode of the bit. As a result, it is possible to recognize which layer of the chip should correspond to which address in the entire memory area.
  • each memory chip has a first pad electrode through which TSV 201a connected to the first voltage (power supply voltage Vcc) passes and a TSV 201b connected to the second voltage (ground voltage Vss) through which the first pad electrode penetrates.
  • a structure in which two pad electrodes are provided and connected to a common wiring, and the pad electrode and the TSV of the fourth embodiment are electrically insulated is selectively applied to the first pad electrode or the second pad electrode.
  • the first pad electrode and the second pad electrode may be connected to different external signal lines.
  • the first pad electrode and the second pad electrode are chip selection signal input pads
  • the external signal lines are two chip selection signal lines (chip select 1 and chip select 2).
  • chip select 1 and chip select 2 two chip selection signal lines
  • FIGS. 17A and 17B In the method according to FIGS. 17A and 17B described above, an area equal to or more than two normal pad electrodes is required for one bit, which is not preferable because the current memory chip needs to be corrected. Since the pad electrode 204P can be 80 to 100 ⁇ m and the hole of the TSV 201 can be 10 ⁇ m or less, two or more TSV regions can be formed in one normal pad electrode as shown in FIG. The function is the same as in FIGS. 17A and 17B.
  • 18A is a plan view of a pad electrode for 3 bits
  • FIG. 18B is an enlarged view of one pad electrode
  • FIG. 18C is a cross section taken along line EE in FIG. 18B.
  • FIG. 18B shows a case where the pad opening is divided into four parts, it may be divided into two.
  • the two unused areas are displayed so that the pad electrode 204P can be seen from above, it is preferable to perform a treatment of filling with a metal layer or an insulating layer.
  • a TSV penetrating each region of the pad electrode can be provided by separating the pad electrode into a plurality of regions by an insulating layer formed on a normal pad electrode.
  • the insulating layer formed on the pad electrode is formed before the second wafer is stacked in the case of the first wafer, and is formed immediately after the wafer is stacked in the second and subsequent wafers. .
  • FIG. 19A to 19D show an example of the manufacturing process.
  • a pad electrode penetrating through the insulating layer 504 is formed on the lowermost wafer in which an insulating layer 504 (passivation film) such as polyimide covering the pad electrode 204P is formed on the silicon substrate 505.
  • a plurality of pad electrode openings 204W (through holes) that expose the surface of 204P are formed.
  • the insulating layer 503 is not necessary in this embodiment mode, but this is not a problem in the process.
  • the electrical test WT can be performed without any problem.
  • an SOG film or a polyimide film is applied and flattened to form an insulating layer 523.
  • FIG. 19B (a) a part of the insulating layer 523 in the pad electrode opening 204W is removed using a photoresist and a mask, and a TSV is formed in the center of the pad electrode opening 204W. A partition wall of the metal layer 202 is formed.
  • FIGS. 19B (b) to 19D (c) the process is the same as the steps shown in FIGS. 14B (a) to 14I (b) of the fourth embodiment.
  • the TSV 201b connected to the TSV 201b and the TSV 201b penetrating the first region, or the second region through which the pad electrode and the TSV of the fourth embodiment are electrically insulated are provided.
  • ⁇ Fifth Embodiment-4> In the fifth embodiment-2 and the fifth embodiment-3, an example is shown in which one of two TSVs is connected to one input circuit. However, the number of TSVs is not limited to two. It is obvious. In particular, in the fifth embodiment-3, it can be seen from FIG. 18B that at least four TSVs are possible. Then, if four chip selection signals (for example, CE0, CE1, CE2, CE3) are output from the controller chip, these correspond to the four TSVs, respectively, and are applied to the chip selection signal pads of the memory chip. Many chips can be stacked.
  • the chip selection signal is not limited to the NAND flash memory, but is selected by the memory chip called chip select (CS) or chip enable (CE), which is possessed by any memory device. Points to the input signal.
  • CS chip select
  • CE chip enable
  • the chip address or signature indicating which layer the stacked memory chip is in can be shared with the process for the defective chip of the fourth embodiment. This leads to reduced manufacturing costs.
  • ⁇ Sixth embodiment> In the case of stacking in a wafer state on a wafer-on-wafer as described above, the chip stacked on the wafer and finally stacked must be diced (separated) and shipped as a product memory chip. Conventionally, a package is encapsulated by dicing every chip, but in this embodiment, a plurality of memory chip stacks are formed by dicing in groups of 2 chips or groups of 4 chips. To package. As a result, it is possible to achieve higher density than the conventional one-chip package mounting.
  • FIG. 20A shows a state in which the same signal line is connected in the package substrate 301 to realize a state equivalent to a double stacked chip in order to package two stacked chips as a unit.
  • 20A (a) is a plan view
  • FIG. 20A (b) is a cross-sectional view.
  • Only the chip selection signal CE can be made independent as CE1 and CE2, or the data input / output terminal I / O can be made independent and used as a double data width. Note that wiring of a printed circuit board may be used instead of connection within the package substrate 301.
  • FIG. 20B shows a state in which the same signal line is connected in the package substrate 301 in order to package two stacked chips as a unit, and a state equivalent to a double stacked chip is realized (FIG. 20A Another example).
  • 20B (a) is a plan view
  • FIG. 20B (b) is a cross-sectional view.
  • Only the chip selection signal CE can be made independent as CE1 and CE2, or the data input / output terminal I / O can be made independent and used as a double data width.
  • wiring of a printed circuit board may be used instead of connection within the package substrate 301.
  • the difference from FIG. 20A is that the wiring in the package substrate 301 is a single layer. As can be seen from the plan view shown in FIG. 20B (a), the wiring routing is different from FIG. 20A.
  • FIGS. 5A, 5B, 6A, and 6B it is preferable to further mount (stack) the package substrate 301 after stacking the wafers, and then dicing the stacked chip into product chips as individual pieces. Obviously, the lowest cost and preferred. However, of course, after stacking on the wafer, it is of course possible to first dice into a stack as shown in FIGS. 5A and 5B, 6A and 6B, and then enclose the package as shown in FIG. According to the sixth embodiment, it is possible to easily mount at higher density.
  • one or more memory chips are further stacked, so that Even if a defective chip is included in the memory, a desired storage capacity can be obtained.
  • FIGS. 22A (a) and 22A (b) are process flow diagrams for explaining a method according to the eighth embodiment.
  • a pad electrode 204P 1 Al pad or the like
  • the insulating layer 5042 and the pad electrode 204P 2 on the silicon substrate 505 2 having a device (Al pads) is thinned is formed 2 prepare layers th wafer, through the adhesive layer 205 1 is stacked on the first layer of the wafer.
  • the pad electrode 204P 2, openings 204W 2 penetrating the pad electrode 204P 2 are formed.
  • 22A (c) is a cross-sectional view
  • FIG. 22A (d) is a plan view.
  • a pad electrode 204P 3 Al pad or the like having an insulating layer 504 3 and an opening 204W 3 is formed on a silicon substrate 505 3 having a device and thinned 3.
  • a pad electrode 204P 3 Al pad or the like
  • the opening diameter of the opening 204W 3 is larger than the opening diameter of the opening 204W 2.
  • a thinned fourth layer wafer is prepared in which an insulating layer 504 4 and a pad electrode 204P 4 (such as an Al pad) having an opening 204W 4 are formed on a silicon substrate 505 4 having a device, and an adhesive layer is prepared. 205 3 via, laminated onto third layer of the wafer.
  • the opening diameter of the opening 204W 4 is larger than the opening diameter of the opening 204W 3.
  • a photoresist 520 that is patterned.
  • the photoresist 520 is exposed inside the insulating layer 504 fourth opening 204W 4, patterned so as to cover the outer insulating layer 504 4 of the pad electrode 204P 4. That is, the sidewall of the opening of the photoresist 520 is positioned on the pad electrode 204P 4.
  • each wafer is etched until the surface of the pad electrode 204P1 of the first wafer is exposed, and then the photoresist 520 is removed. Wash further. During the etching, the pad electrode of each wafer also functions as a mask, so that a step-like hole 240 as shown in FIG. 22C (a) is formed.
  • an insulating film 203 is formed on the sidewall of the hole 240, on the fourth layer wafer, and on each wafer exposed in the hole 240.
  • the thickness of the insulating film 203 on the side wall of the hole 240 can be, for example, about 50 to 100 nm.
  • the insulating film 203 formed on the side wall of the hole 240 is removed by, for example, RIE (Reactive Ion Etching).
  • RIE Reactive Ion Etching
  • the sidewall of the hole 240 of the second layer of the wafer is covered with an insulating film 203 2
  • the side walls of the hole 240 of the third layer of the wafer is covered with an insulating film 203 3
  • the holes 240 of the fourth layer of the wafer sidewalls are covered with an insulating film 203 4.
  • 22D (a) is a cross-sectional view
  • FIG. 22D (b) is a plan view.
  • the insulating film 203 2 , the insulating film 203 3 , and the insulating film 203 4 are arranged in a concentric ring shape, separated by each insulating film, and pad electrode 204P from the inside. 1 , a pad electrode 204P 2 , a pad electrode 204P 3 , and a pad electrode 204P 4 are arranged.
  • a metal such as Ti / TiN, Ta, etc. is about 50 to 100 nm on the side wall of the hole 240, the fourth layer wafer, and each wafer exposed in the hole 240.
  • a metal layer 601 to be a barrier layer is formed by sputtering or the like.
  • a metal such as Cu is formed on the metal layer 601 by a sputtering method or the like with a thickness of about 500 nm to form a metal layer 602 to be a seed layer.
  • each metal layer protruding from the surface of the insulating film 503 is filled with a metal such as Cu in the hole 240 by electrolytic plating using the metal layer 602 as a seed layer. Is removed by CMP or the like, and a metal layer 603 is formed in the hole 240.
  • a TSV having an integrally formed metal layer 603 penetrating each stacked semiconductor chip in the thickness direction is formed.
  • the thickness of the portion that penetrates each layer of the metal layer 603 is formed thicker as the upper layer. Note that the upper surface of the insulating film 503 and the upper surface of the metal layer 603 are flat surfaces.
  • TSVs metal layers 603
  • the number of wafers to be stacked may be further increased. Thereby, the manufacturing process can be simplified, and the cost of the manufactured semiconductor device can be reduced.
  • the opening diameter of the upper layer pad electrode larger than the opening diameter of the lower layer pad electrode, the area of the contact area between the pad electrode and the TSV metal layer can be reduced. Since it can be increased, reliable contact can be achieved and the resistance value of the contact portion can be reduced.
  • 23A to 23D are process flow diagrams for explaining a method according to the first modification of the eighth embodiment.
  • the steps shown in FIGS. 22A to 22E may be similar to the steps shown in FIGS. 23A to 23D.
  • 23A to 23D are different from FIGS. 22A to 22E in that the insulating layers 504 2 to 504 4 are replaced with the insulating layers 704 2 to 704 4 .
  • the insulating layers 704 2 to 704 4 have a portion penetrating the silicon substrate below the pad electrode of each wafer.
  • the portions of the insulating layers 704 2 to 704 4 that pass through the silicon substrate are made larger than the diameter of the largest opening among the openings formed in the pad electrode of each wafer.
  • the portion of the insulating layers 704 2 to 704 4 that penetrates the silicon substrate may be larger than the pad electrode of each wafer.
  • the hole 240 is formed in the step shown in FIG. 23C (a), the insulating layers 704 2 to 704 4 are exposed on the side walls of the hole 240, so that FIG. 22C (b), FIG. 22D (a), and FIG. The process of 22D (b) can be omitted.
  • the manufacturing process can be further simplified, and the cost of the manufactured semiconductor device can be further reduced.
  • FIG. 24 is a process flow diagram for explaining a method according to the second modification of the eighth embodiment.
  • the diameter of the opening portion formed in the pad electrode of each wafer as shown in FIG. May be the same.
  • the wall surface (side wall) of the opening of the pad electrode of each wafer is electrically connected to the metal layers 601, 602, and 603.
  • the pad electrode 204P 3 and TSV metal layer 603
  • the signal line can be wired to any laminated wafer.
  • the same signal can be supplied to the fourth layer wafer and the second layer wafer through the third layer wafer, or an independent wiring can be supplied to each layer wafer.
  • the NAND flash memory has been described.
  • the present invention is not limited to this, and the present invention can be widely applied to, for example, a NOR type flash memory and a semiconductor memory such as a DRAM.
  • the present invention can be applied to a three-dimensional device, a CMOS image sensor, a power transistor, a high frequency device, and the like in which logic circuit devices that perform parallel operations are stacked.
  • materials such as silicon substrate, SOG and Cu were mentioned in the process description and the like, and the structure of the TSV was explained, it is obvious that details of actual materials and structures are not limited to this.
  • an SOI substrate Silicon-on-insulator
  • 100A, 100B Semiconductor device 101, 101a, 101b NAND flash memory chip (memory chip) 102 NAND controller chip (controller chip) 110 Bonding wire 201 TSV 202, 506, 601, 602, 603 Metal layer 203, 203 2 to 203 4 , 502 Insulating film 204, 204c, 204P, 204P 1 to 204P 4 Pad electrode 204W Pad electrode opening 204W 2 to 204W 4 Opening 205, 205 1 to 205 3 , 212 Adhesive layer 240 hole 301 Package substrate 302 External connection terminals 303, 303 a, 303 b Connection wiring 331 Chip address signal 333 Potential comparison circuit 334 Chip selection circuit 342 Power-on detection circuit 343 Delay circuit 344 Initial setting operation circuit 351 Inverter 352 Switch circuit 353 Delay element 354, 422 Buffer circuit 401 Wiring 411 Pad 421 Pull-up transistor 424 Input circuit 500 Wafer 503, 504, 504 1 to 504 4 , 523, 704

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Abstract

　This semiconductor device has a laminate obtained by laminating a plurality of semiconductor chips, and a through-electrode which penetrates, in the thickness direction, each of the semiconductor chips laminated on the semiconductor chip at the lowermost layer of the laminate, the through-electrode being connected to a pad electrode of the semiconductor chip at the lowermost layer. A power supply line and/or the signal line of the laminate is connected in common, via the through-electrode, to the semiconductor chips constituting the laminate.

Description

半導体装置及びその製造方法Semiconductor device and manufacturing method thereof
　本発明は、半導体装置及びその製造方法に関する。 The present invention relates to a semiconductor device and a manufacturing method thereof.
　従来ＭＣＰ（Ｍｕｌｔｉ－Ｃｈｉｐ－Ｐａｃｋａｇｅ）、またはｅＭＭＣ（ｅｍｂｅｄｄｅｄ　Ｍｕｌｔｉ－Ｍｅｄｉａ　Ｃａｒｄ）と呼ばれるＤＲＡＭやＮＡＮＤフラッシュメモリ等の半導体チップを１個のパッケージの中に複数積層した製品があるが、積層数に制限があった。 Conventionally, there are products in which multiple semiconductor chips such as DRAM and NAND flash memory called MCP (Multi-Chip-Package) or eMMC (embedded Multi-Media Card) are stacked in one package, but the number of stacks is limited. was there.
　図１は、従来の半導体装置を例示する模式図である。図１を参照するに、半導体装置１００Ｘは、複数のＮＡＮＤフラッシュメモリチップ１０１と、ＮＡＮＤコントローラチップ１０２とを接続したＭＣＰパッケージである。 FIG. 1 is a schematic view illustrating a conventional semiconductor device. Referring to FIG. 1, a semiconductor device 100X is an MCP package in which a plurality of NAND flash memory chips 101 and a NAND controller chip 102 are connected.
　各ＮＡＮＤフラッシュメモリチップ１０１は、位置をずらして積層され、各層のチップのボンディング接続用端子（パッド電極）を露出し、各チップの該端子を最下部にあるパッケージ基板１０９（リードフレームやＦＢＧＡ（Fine pitch Ball Grid Array）等の基板）の端子にボンディングワイヤ１１０でボンディングされている。 The NAND flash memory chips 101 are stacked at different positions to expose the bonding connection terminals (pad electrodes) of the chips in each layer, and the terminals of each chip are connected to the lowermost package substrate 109 (lead frame or FBGA). Bonding wires 110 are used for bonding to terminals of substrates such as Fine pitch Ball Grid Array).
　更に、ＮＡＮＤコントローラチップ１０２の端子もボンディングワイヤ１１０でパッケージ基板１０９にボンディングされている。積層されたＮＡＮＤフラッシュメモリチップ１０１はＮＡＮＤコントローラチップ１０２に電気的に繋がり、ＮＡＮＤコントローラチップ１０２によって動作が管理されている。又、ＮＡＮＤコントローラチップ１０２は、ＮＡＮＤフラッシュメモリチップ１０１との接続端子以外に、該パッケージ外部の装置との接続のための入出力端子を持ち、この入出力端子はボンディングワイヤ１１０によってパッケージ基板１０９にボンディングされ、更にパッケージ基板１０９を介して半導体装置１００Ｘのピン１０３に繋がっている。 Furthermore, the terminals of the NAND controller chip 102 are also bonded to the package substrate 109 with bonding wires 110. The stacked NAND flash memory chip 101 is electrically connected to the NAND controller chip 102, and the operation is managed by the NAND controller chip 102. The NAND controller chip 102 has input / output terminals for connection to devices outside the package in addition to the connection terminals to the NAND flash memory chip 101, and these input / output terminals are connected to the package substrate 109 by bonding wires 110. Bonded and further connected to the pins 103 of the semiconductor device 100X through the package substrate 109.
特開２０１０－２７８２７９号公報JP 2010-278279 A
　ところで、最近、スマートフォン等のモバイル機器の発達により、大容量且つ薄膜化された半導体メモリのモバイル機器への搭載が重要になっている。更に、ハードディスクドライブＨＤＤに代わるフラッシュメモリを用いたソリッドステートドライブＳＳＤ（Ｓｏｌｉｄ　Ｓｔａｔｅ　Ｄｒｉｖｅ）の用途が広がっているが、やはりフォームファクターの小さいソリッドステートドライブＳＳＤの要求が強い。 Recently, with the development of mobile devices such as smartphones, it has become important to mount large-capacity and thin semiconductor memories on mobile devices. Furthermore, the use of a solid state drive SSD (Solid State Drive) using a flash memory in place of the hard disk drive HDD is expanding, but there is a strong demand for a solid state drive SSD with a small form factor.
　しかし、図１に示した従来技術のようにＮＡＮＤフラッシュメモリチップ１０１をワイヤボンディングで繋ぐ手法では、各チップはパッド電極からボンディングワイヤ１１０でパッケージ基板１０９の端子に接続しなければならず、ボンディングワイヤ１１０を形成するために、ある程度の高さ方向の余裕と、横方向にチップをずらす余裕、及びパッケージ基板１０９のボンディング場所の余裕が必要である。 However, in the technique of connecting the NAND flash memory chips 101 by wire bonding as in the prior art shown in FIG. 1, each chip must be connected from the pad electrode to the terminal of the package substrate 109 by the bonding wire 110. In order to form 110, a certain amount of margin in the height direction, a margin for shifting the chip in the lateral direction, and a margin for bonding the package substrate 109 are required.
　ところが、ワイヤボンディングの制約から積層できるチップ数には制約があり、小さいパッケージに多数の半導体チップ（例えば、ＮＡＮＤフラッシュメモリチップ）を格納した半導体装置（例えば、大容量不揮発性メモリ）の実現は困難であった。 However, the number of chips that can be stacked is limited due to wire bonding restrictions, and it is difficult to realize a semiconductor device (for example, a large-capacity nonvolatile memory) in which a large number of semiconductor chips (for example, NAND flash memory chips) are stored in a small package. Met.
　本発明は上記の点に鑑みてなされたもので、小型で大容量の半導体装置等を提供することを課題とする。 The present invention has been made in view of the above points, and an object of the present invention is to provide a small-sized and large-capacity semiconductor device and the like.
　本半導体装置は、複数の半導体チップが積層された積層体と、前記積層体の最下層の半導体チップ上に積層された各々の半導体チップを厚さ方向に貫通して前記最下層の半導体チップのパッド電極と接続された貫通電極と、を有し、前記積層体の電源線及び信号線の少なくとも一方は、前記貫通電極を介して、前記積層体を構成する半導体チップに共通に接続されていることを要件とする。 The semiconductor device includes a stacked body in which a plurality of semiconductor chips are stacked, and each of the semiconductor chips stacked on the lowermost semiconductor chip of the stacked body in the thickness direction so as to pass through the lowermost semiconductor chip. A through electrode connected to the pad electrode, and at least one of the power line and the signal line of the multilayer body is commonly connected to the semiconductor chip constituting the multilayer body via the through electrode. Is a requirement.
　本発明によれば、小型で大容量の半導体装置等を提供できる。 According to the present invention, a small and large-capacity semiconductor device or the like can be provided.
従来の半導体装置を例示する模式図である。It is a schematic diagram which illustrates the conventional semiconductor device. 第１の実施の形態に係る半導体装置の概念を例示する斜視図である。1 is a perspective view illustrating the concept of a semiconductor device according to a first embodiment. 図２の半導体装置においてバンプ電極を使用しない場合の例を示す平面図である。FIG. 3 is a plan view illustrating an example in which no bump electrode is used in the semiconductor device of FIG. 2. 図３ＡのＡ－Ａ線に沿う断面図である。It is sectional drawing which follows the AA line of FIG. 3A. 図２の半導体装置においてバンプ電極を使用した場合の例を示す平面図である。FIG. 3 is a plan view showing an example when bump electrodes are used in the semiconductor device of FIG. 2. 図４ＡのＡ－Ａ線に沿う断面図である。FIG. 4B is a sectional view taken along line AA in FIG. 4A. 積層したメモリチップのパッド電極のＴＳＶをパッケージの端子に接続した場合を例示する断面図（その１）である。FIG. 9 is a cross-sectional view illustrating the case where TSVs of pad electrodes of stacked memory chips are connected to terminals of a package (part 1); 積層したメモリチップのパッド電極のＴＳＶをパッケージの端子に接続した場合を例示する断面図（その２）である。FIG. 14 is a cross-sectional view (part 2) illustrating the case where the TSVs of the pad electrodes of the stacked memory chips are connected to the terminals of the package. 図３の半導体装置にコントローラチップを追加した場合の例を示す平面図である。FIG. 4 is a plan view showing an example when a controller chip is added to the semiconductor device of FIG. 3. 図６ＡのＢ－Ｂ線に沿う断面図である。It is sectional drawing which follows the BB line of FIG. 6A. メモリチップとコントローラチップが相互に接続された様子を示す模式図である。It is a schematic diagram which shows a mode that the memory chip and the controller chip were mutually connected. 図３の半導体装置にコントローラチップを追加した場合の他の例を示す断面図である。FIG. 4 is a cross-sectional view showing another example when a controller chip is added to the semiconductor device of FIG. 3. アドレス信号によるメモリチップの選択について説明する図である。It is a figure explaining selection of a memory chip by an address signal. チップアドレスを設定する方法を説明する図（その１）である。It is FIG. (1) explaining the method to set a chip address. チップアドレスを設定する方法を説明する図（その２）である。It is FIG. (2) explaining the method to set a chip address. メモリチップの内部回路の一部を例示するブロック図である。It is a block diagram which illustrates a part of internal circuit of a memory chip. メモリチップに内蔵されるディレイ回路を例示するブロック図である。It is a block diagram which illustrates the delay circuit built in a memory chip. ディレイ回路を搭載した場合の効果を説明する図である。It is a figure explaining the effect at the time of carrying a delay circuit. 不良チップを不活性にするための配線の切断について説明する図（その１）である。It is FIG. (1) explaining the cutting | disconnection of the wiring for inactivating a defective chip. 不良チップを不活性にするための配線の切断について説明する図（その２）である。It is FIG. (2) explaining the cutting | disconnection of the wiring for inactivating a defective chip. 第４の実施の形態に係る方法を説明するプロセスフロー図（その１）である。It is a process flow figure (the 1) explaining the method concerning a 4th embodiment. 第４の実施の形態に係る方法を説明するプロセスフロー図（その２）である。It is a process flow figure (the 2) explaining the method concerning a 4th embodiment. 第４の実施の形態に係る方法を説明するプロセスフロー図（その３）である。It is a process flow figure (the 3) explaining the method which concerns on 4th Embodiment. 第４の実施の形態に係る方法を説明するプロセスフロー図（その４）である。It is a process flow figure (the 4) explaining the method concerning a 4th embodiment. 第４の実施の形態に係る方法を説明するプロセスフロー図（その５）である。It is a process flow figure (the 5) explaining the method which concerns on 4th Embodiment. 第４の実施の形態に係る方法を説明するプロセスフロー図（その６）である。It is a process flow figure (the 6) explaining the method which concerns on 4th Embodiment. 第４の実施の形態に係る方法を説明するプロセスフロー図（その７）である。It is a process flow figure explaining the method which concerns on 4th Embodiment (the 7). 第４の実施の形態に係る方法を説明するプロセスフロー図（その８）である。It is a process flow figure (the 8) explaining the method which concerns on 4th Embodiment. 第４の実施の形態に係る方法を説明するプロセスフロー図（その９）である。It is a process flow figure (the 9) explaining the method which concerns on 4th Embodiment. チップアドレスの設定方法を例示する図（その１）である。FIG. 6 is a diagram (part 1) illustrating a chip address setting method; チップアドレスの設定方法を例示する図（その２）である。FIG. 3 is a second diagram illustrating a chip address setting method; 図１５Ａに対応する断面図である。It is sectional drawing corresponding to FIG. 15A. 図１５Ｂに対応する平面図である。FIG. 15B is a plan view corresponding to FIG. 15B. 図１５Ｂに対応する断面図である。It is sectional drawing corresponding to FIG. 15B. 電源電圧に接続されるＴＳＶ及び接地電圧Ｖｓｓに接続されるＴＳＶをパッケージの端子に接続した場合を例示する断面図である。It is sectional drawing which illustrates the case where TSV connected to the power supply voltage and TSV connected to the ground voltage Vss are connected to the terminal of a package. １つのパッド内に２つ以上のＴＳＶ領域を作製する例を示す図であるIt is a figure which shows the example which produces two or more TSV area | regions in one pad. １つのパッド内に２つ以上のＴＳＶ領域を作製する工程の例を示す図（その１）である。FIG. 11 is a diagram (part 1) illustrating an example of a process of creating two or more TSV regions in one pad. １つのパッド内に２つ以上のＴＳＶ領域を作製する工程の例を示す図（その２）である。FIG. 11 is a diagram (part 2) illustrating an example of a process of creating two or more TSV regions in one pad. １つのパッド内に２つ以上のＴＳＶ領域を作製する工程の例を示す図（その３）である。FIG. 10 is a diagram (No. 3) illustrating an example of a process of creating two or more TSV regions in one pad. １つのパッド内に２つ以上のＴＳＶ領域を作製する工程の例を示す図（その４）である。FIG. 14 is a diagram (No. 4) illustrating an example of a process of creating two or more TSV regions in one pad. ２個の積層チップを一単位としてパッケージングする例を示す図である。It is a figure which shows the example which packages two laminated chips as a unit. ２個の積層チップを一単位としてパッケージングする別の例を示す図である。It is a figure which shows another example which packages two laminated chips as a unit. 規定のメモリ容量に達するウェハに加えて余分のウェハを積層する例を示す図である。It is a figure which shows the example which laminates | stacks an extra wafer in addition to the wafer which reaches a regular memory capacity. 第８の実施の形態に係る方法を説明するプロセスフロー図（その１）である。It is a process flow figure explaining the method which concerns on 8th Embodiment (the 1). 第８の実施の形態に係る方法を説明するプロセスフロー図（その２）である。It is a process flow figure (the 2) explaining the method which concerns on 8th Embodiment. 第８の実施の形態に係る方法を説明するプロセスフロー図（その３）である。It is a process flow figure (the 3) explaining the method which concerns on 8th Embodiment. 第８の実施の形態に係る方法を説明するプロセスフロー図（その４）である。It is a process flow figure (the 4) explaining the method which concerns on 8th Embodiment. 第８の実施の形態に係る方法を説明するプロセスフロー図（その５）である。It is a process flow figure (the 5) explaining the method which concerns on 8th Embodiment. 第８の実施の形態の変形例１に係る方法を説明するプロセスフロー図（その１）である。It is a process flow figure explaining the method which concerns on the modification 1 of 8th Embodiment (the 1). 第８の実施の形態の変形例１に係る方法を説明するプロセスフロー図（その２）である。It is a process flow figure explaining the method which concerns on the modification 1 of 8th Embodiment (the 2). 第８の実施の形態の変形例１に係る方法を説明するプロセスフロー図（その３）である。It is a process flow figure explaining the method which concerns on the modification 1 of 8th Embodiment (the 3). 第８の実施の形態の変形例１に係る方法を説明するプロセスフロー図（その４）である。It is a process flow figure explaining the method which concerns on the modification 1 of 8th Embodiment (the 4). 第８の実施の形態の変形例２に係る方法を説明するプロセスフロー図である。It is a process flow figure explaining a method concerning modification 2 of an 8th embodiment. 任意のパッド電極とＴＳＶとを電気的に分離する方法を説明する図である。It is a figure explaining the method of electrically isolate | separating arbitrary pad electrodes and TSV.
　以下、図面を参照して発明を実施するための形態について説明する。以下の各実施の形態ではＮＡＮＤフラッシュメモリを例として説明するが、本発明はそれに限定するものでない。なお、各図面において、同一構成部分には同一符号を付し、重複した説明を省略する場合がある。 Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. In the following embodiments, a NAND flash memory will be described as an example, but the present invention is not limited thereto. In addition, in each drawing, the same code | symbol is attached | subjected to the same component and the overlapping description may be abbreviate | omitted.
　ＮＡＮＤフラッシュメモリチップを多数積層しスルーシリコン・ビア（以下、ＴＳＶという）でチップ間を電気的に繋ぐ。その際各チップの各端子（パッド電極）は上部チップから下部チップまで各々共通したＴＳＶにて接続する。共通ＴＳＶとすることでＴＳＶプロセスが簡易となり、低コスト且つ高歩留まりのＴＳＶ接続が実現できる。 A large number of NAND flash memory chips are stacked and the chips are electrically connected by through silicon vias (hereinafter referred to as TSV). At that time, each terminal (pad electrode) of each chip is connected by a common TSV from the upper chip to the lower chip. By using a common TSV, the TSV process can be simplified, and a low-cost and high-yield TSV connection can be realized.
　又、その際所望のチップを動作させるための、新たなチップ選択法を考案した。全く同じＮＡＮＤフラッシュメモリチップを積層するので、各チップに固有のチップアドレスを割り付けて、ＮＡＮＤコントローラにより動作させる１個のＮＡＮＤフラッシュメモリチップを選択できるようにしなければならない。ＮＡＮＤコントローラよりチップアドレス信号を出し、それに合致したＮＡＮＤフラッシュメモリチップのみが動作モードになり、他のチップは非選択・休止モードになる。 In addition, a new chip selection method was devised to operate the desired chip at that time. Since exactly the same NAND flash memory chips are stacked, a unique chip address must be assigned to each chip so that one NAND flash memory chip to be operated by the NAND controller can be selected. A chip address signal is output from the NAND controller, and only the NAND flash memory chip that matches the chip address signal enters the operation mode, and the other chips enter the non-selection / pause mode.
　又、ＮＡＮＤフラッシュメモリのウェハとウェハを積層し、各チップの端子間（パッド電極間）をＴＳＶで繋ぎ、その後ダイシングして切りだす方法があるが、その場合積層チップ内に不良チップが含まれるおそれがある。その際、不良チップが他のチップの動作中に不具合とならないようにするための手法も考案した。まず、ウェハを積層する前にウェハ内の不良チップの有無を検査し、そして不良チップに対しては後のＴＳＶ接続で電気的に繋がらないようにする。具体的には、１つには、ＴＳＶと繋がるべき不良チップ内の配線の切断、もう１つはＴＳＶ工程で不良チップのパッド電極とＴＳＶの間に絶縁膜を形成しておくという、２つの方法を提案する。 In addition, there is a method in which the wafers of the NAND flash memory are laminated, the terminals (between pad electrodes) of each chip are connected by TSV, and then diced and cut out. In this case, defective chips are included in the laminated chip. There is a fear. At that time, a technique was also devised to prevent the defective chip from malfunctioning during the operation of other chips. First, before the wafers are stacked, the presence or absence of defective chips in the wafer is inspected, and the defective chips are not electrically connected by subsequent TSV connection. Specifically, one is cutting the wiring in the defective chip to be connected to the TSV, and the other is forming an insulating film between the pad electrode of the defective chip and the TSV in the TSV process. Suggest a method.
　〈第１の実施の形態〉
　図２は、第１の実施の形態に係る半導体装置の概念を例示する斜視図である。図２を参照するに、第１の実施の形態に係る半導体装置１００Ａでは、ＮＡＮＤフラッシュメモリチップ１０１（以降、単にメモリチップ１０１とする）を複数個積層した積層体において、それぞれのメモリチップ１０１の平面視において略重複する位置にあるパッド電極間を各々共通のＴＳＶ２０１（貫通電極）で電気的接続している。各メモリチップ１０１を動作させるために必要な電源線Ｖｃｃ、Ｖｓｓ及び入出力信号線は、それぞれに対応するＴＳＶ２０１を通して積層された全てのメモリチップ１０１に共通に繋がっている。 <First Embodiment>
FIG. 2 is a perspective view illustrating the concept of the semiconductor device according to the first embodiment. Referring to FIG. 2, in the semiconductor device 100A according to the first embodiment, in a stacked body in which a plurality of NAND flash memory chips 101 (hereinafter simply referred to as memory chips 101) are stacked, The pad electrodes located at substantially overlapping positions in plan view are electrically connected by a common TSV 201 (through electrode). The power supply lines Vcc and Vss and the input / output signal lines necessary for operating each memory chip 101 are commonly connected to all the memory chips 101 stacked through the corresponding TSV 201.
　図３Ａ及び図３Ｂは、図２の半導体装置１００Ａにおいてバンプ電極を使用しない（ｂｕｍｐ－ｌｅｓｓ）場合の例を示す図であり、図３Ａは平面図、図３Ｂは図３ＡのＡ－Ａ線に沿う断面図である。図３Ａ及び図３Ｂに示す半導体装置では、最下層のメモリチップ１０１ｂ上に、複数のメモリチップ１０１ａが積層されて、メモリチップ１０１ａ及び１０１ｂにより積層体を構成している。図３Ａ及び図３Ｂに示す半導体装置は、メモリチップ１０１ｂ上に積層された各メモリチップ１０１ａを厚さ方向に貫通して最下層のメモリチップ１０１ｂのパッド電極２０４と接続されたＴＳＶ２０１（貫通電極）を有している。 3A and 3B are diagrams showing an example in which no bump electrode is used (bump-less) in the semiconductor device 100A of FIG. 2, FIG. 3A is a plan view, and FIG. 3B is a line AA in FIG. 3A. It is sectional drawing which follows. In the semiconductor device shown in FIGS. 3A and 3B, a plurality of memory chips 101a are stacked on the lowermost memory chip 101b, and a stacked body is configured by the memory chips 101a and 101b. The semiconductor device shown in FIGS. 3A and 3B includes a TSV 201 (through electrode) that penetrates each memory chip 101a stacked on the memory chip 101b in the thickness direction and is connected to the pad electrode 204 of the lowermost memory chip 101b. have.
　各メモリチップ１０１ａのＴＳＶ２０１は、各メモリチップ１０１ａのパッド電極２０４に形成されている。具体的には、各メモリチップ１０１ａに形成されたＴＳＶ２０１の構造は、各メモリチップ１０１ａを貫通する穴の中央部に金属層２０２が埋め込まれており、金属層２０２の外側を絶縁膜２０３が覆い、絶縁膜２０３はメモリチップ１０１ａを貫通する穴と穴に埋め込まれた金属層２０２とを絶縁している。なお、各メモリチップ１０１ａ同士や、メモリチップ１０１ａとメモリチップ１０１ｂとを特に区別する必要がない場合には、単にメモリチップ１０１と称するものとする。 The TSV 201 of each memory chip 101a is formed on the pad electrode 204 of each memory chip 101a. Specifically, in the structure of the TSV 201 formed in each memory chip 101a, the metal layer 202 is embedded in the center of the hole penetrating each memory chip 101a, and the insulating film 203 covers the outside of the metal layer 202. The insulating film 203 insulates the hole penetrating the memory chip 101a from the metal layer 202 embedded in the hole. Note that the memory chips 101a are simply referred to as the memory chips 101 when it is not necessary to distinguish between the memory chips 101a or the memory chips 101a and 101b.
　積層された各メモリチップ１０１間には接着層２０５（絶縁層）が形成されている。各ＴＳＶ２０１は、各接着層２０５を含めて、積層された最上層のメモリチップ１０１ａからメモリチップ１０１ｂの１つ上部の２層目のメモリチップ１０１ａまで貫通している。そして、各メモリチップ１０１ａ及びメモリチップ１０１ｂのパッド電極２０４はＴＳＶ２０１内にある金属層２０２と接続されている。このように、図３Ａ及び図３Ｂに示す半導体装置では、上下に隣接するメモリチップ１０１ａのＴＳＶ２０１同士が直接接続されている。なお、パッド電極２０４と金属層２０２とは電気的に接続されていれば、図３Ａに示すように平面的な位置ずれがあってもよい。 An adhesive layer 205 (insulating layer) is formed between the stacked memory chips 101. Each TSV 201 penetrates from the stacked uppermost memory chip 101a to the second memory chip 101a one layer above the memory chip 101b, including each adhesive layer 205. The pad electrodes 204 of each memory chip 101a and memory chip 101b are connected to the metal layer 202 in the TSV 201. As described above, in the semiconductor device shown in FIGS. 3A and 3B, the TSVs 201 of the memory chips 101a that are vertically adjacent to each other are directly connected to each other. In addition, as long as the pad electrode 204 and the metal layer 202 are electrically connected, there may be a planar positional shift as shown in FIG. 3A.
　図４Ａ及び図４Ｂは、図２の半導体装置１００Ａにおいてバンプ電極を使用した場合の例を示す図であり、図４Ａは平面図、図４Ｂは図４ＡのＡ－Ａ線に沿う断面図である。図４Ａ及び図４Ｂに示す半導体装置では、各ＴＳＶ２０１の構造は、積層したメモリチップ１０１ａを貫通する穴の中央部に金属層２０２が埋め込まれており、金属層２０２の外側を絶縁膜２０３が覆い、絶縁膜２０３はメモリチップ１０１ａを貫通する穴と金属層２０２とを絶縁している。 4A and 4B are diagrams showing an example in which a bump electrode is used in the semiconductor device 100A of FIG. 2, FIG. 4A is a plan view, and FIG. 4B is a cross-sectional view taken along the line AA of FIG. 4A. . In the semiconductor device shown in FIGS. 4A and 4B, each TSV 201 has a structure in which a metal layer 202 is embedded in the center of a hole penetrating the stacked memory chip 101a, and an insulating film 203 covers the outside of the metal layer 202. The insulating film 203 insulates the metal layer 202 from the hole penetrating the memory chip 101a.
　積層された各メモリチップ１０１間には接着層２１２（絶縁層）が形成されている。又、積層されたメモリチップ１０１ａの各ＴＳＶ２０１間、及び２層目のメモリチップ１０１ａのＴＳＶ２０１とメモリチップ１０１ｂのパッド電極２０４間にはマイクロバンプ（ｍｉｃｒｏ－ｂｕｍｐ）２１３（バンプ電極）が形成されている。各ＴＳＶ２０１は、積層された最上層のメモリチップ１０１ａからメモリチップ１０１ｂの１つ上部の２層目のメモリチップ１０１ａまで貫通している。各メモリチップ１０１ａ及びメモリチップ１０１ｂのパッド電極２０４はＴＳＶ２０１内にある金属層２０２と接続されている。このように、図４Ａ及び図４Ｂに示す半導体装置では、上下に隣接するメモリチップ１０１ａのＴＳＶ２０１同士がバンプ電極を介して接続されている。なお、パッド電極２０４と金属層２０２とは電気的に接続されていれば、図４Ａに示すように平面的な位置ずれがあってもよい。 An adhesive layer 212 (insulating layer) is formed between the stacked memory chips 101. Micro-bumps 213 (bump electrodes) are formed between the TSVs 201 of the stacked memory chips 101a and between the TSV 201 of the second-layer memory chip 101a and the pad electrodes 204 of the memory chip 101b. Yes. Each TSV 201 penetrates from the uppermost stacked memory chip 101a to the second-layer memory chip 101a one layer above the memory chip 101b. The pad electrode 204 of each memory chip 101 a and memory chip 101 b is connected to the metal layer 202 in the TSV 201. As described above, in the semiconductor device shown in FIGS. 4A and 4B, the TSVs 201 of the memory chips 101a adjacent in the vertical direction are connected to each other via the bump electrodes. In addition, as long as the pad electrode 204 and the metal layer 202 are electrically connected, there may be a planar positional shift as shown in FIG. 4A.
　なお、積層するメモリチップ１０１ａはシリコン基板等の半導体基板を薄く削り、多くのチップを積層できるようにするが、最下層のメモリチップ１０１ｂは厚くしてパッケージの構造材代りとしてもよい。積層するメモリチップ１０１ａの厚さは、例えば、２μｍ～１００μｍ程度とすることができるが、３μｍ～１０μｍ程度とすることが好ましい。基板体積を小さくするとＴＳＶ加工時間が大幅に短縮され、薄化でアスペクト比が緩和され埋め込み性やカバレッジが改善されるからである。メモリチップ１０１ｂはメモリチップ１０１ａよりも厚くして構わない。 Note that the memory chip 101a to be stacked is made by thinly cutting a semiconductor substrate such as a silicon substrate so that many chips can be stacked. However, the memory chip 101b in the lowermost layer may be made thick to be used as a substitute for a package structural material. The thickness of the memory chip 101a to be stacked can be, for example, about 2 μm to 100 μm, but is preferably about 3 μm to 10 μm. This is because when the substrate volume is reduced, the TSV processing time is significantly shortened, and the aspect ratio is relaxed by thinning, and the embedding property and coverage are improved. The memory chip 101b may be thicker than the memory chip 101a.
　メモリチップ１０１を動作させるために必要な、電源線（ＶＣＣ、ＶＳＳ）及び入出力信号線は、それぞれに対応するＴＳＶ２０１を介して、積層体を構成する全てのメモリチップ１０１に共通に接続されている。そして、最上層のメモリチップ１０１ａから電源線と入出力信号線をパッケージの外部接続端子（ピン）に取り出す。それにより、電源線には所望の電位を与え、信号線には必要な信号を与えることで、積層されたメモリチップ内の任意の１つのメモリチップを選択し動作させることできる。 The power supply lines (VCC, VSS) and the input / output signal lines necessary for operating the memory chip 101 are commonly connected to all the memory chips 101 constituting the stacked body via the corresponding TSV 201. Yes. Then, the power supply line and the input / output signal line are taken out from the uppermost memory chip 101a to the external connection terminal (pin) of the package. Thus, any desired memory chip in the stacked memory chips can be selected and operated by applying a desired potential to the power supply line and supplying a necessary signal to the signal line.
　なお、本実施の形態では、電源線及び入出力信号線をＴＳＶ２０１を介して積層体を構成する全てのメモリチップ１０１に共通に接続しているが、電源線及び信号線の何れか一方のみをＴＳＶ２０１を介して積層体を構成する全てのメモリチップ１０１に共通に接続する構成にすることも可能である。 In this embodiment, the power supply line and the input / output signal line are commonly connected to all the memory chips 101 constituting the stacked body via the TSV 201, but only one of the power supply line and the signal line is connected. It is also possible to adopt a configuration in which all memory chips 101 constituting the stacked body are commonly connected via the TSV201.
　図５Ａ及び図５Ｂは、積層したメモリチップのパッド電極のＴＳＶをパッケージの端子に接続した場合を例示する断面図である。図５Ａ及び図５Ｂはバンプレスの場合に相当するが、バンプ使用の場合も同様である。メモリチップ１０１は、電源（Ｖｃｃ、Ｖｓｓ）ピンとＩ／Ｏピン、各種動作モードに関係した入出力信号ピン（ＣＥ，ＷＥ，ＷＰ，Ｒ／Ｂ等）を有する。それらのパッド電極２０４の部分にＴＳＶ２０１を設けてメモリチップ１０１同士を共通に繋げ、それをパッケージの外部接続端子３０２に出したものである。 5A and 5B are cross-sectional views illustrating the case where the TSV of the pad electrode of the stacked memory chip is connected to the terminal of the package. 5A and 5B correspond to the case of bumpless, but the same applies to the case of using bumps. The memory chip 101 has power supply (Vcc, Vss) pins, I / O pins, and input / output signal pins (CE, WE, WP, R / B, etc.) related to various operation modes. TSVs 201 are provided at the pad electrodes 204 to connect the memory chips 101 in common, and are connected to the external connection terminals 302 of the package.
　図５Ａに示すように、最上層のメモリチップ１０１のパッド電極２０４のＴＳＶ２０１をパッケージの外部接続端子３０２に接続してもよいし、図５Ｂに示すように、最下層のメモリチップ１０１からパッケージの外部接続端子３０２に接続してもよい。なお、図５Ａ及び図５Ｂでは、メモリチップ１０１のパッド電極２０４のＴＳＶ２０１の金属材とパッケージの外部接続端子３０２を接続するパッケージ基板３０１内の接続配線３０３をそのまま上又は下に延ばすように描いているが、パッケージ基板３０１内を横に走る配線部を有してもよい。 5A, the TSV 201 of the pad electrode 204 of the uppermost memory chip 101 may be connected to the external connection terminal 302 of the package, or the lowermost memory chip 101 may be connected to the package as shown in FIG. 5B. It may be connected to the external connection terminal 302. 5A and 5B, the connection wiring 303 in the package substrate 301 for connecting the metal material of the TSV 201 of the pad electrode 204 of the memory chip 101 and the external connection terminal 302 of the package is drawn so as to extend upward or downward as it is. However, the wiring board 301 may have a wiring portion running sideways.
　積層体を構成するメモリチップとは種類の異なる半導体チップが、積層体と同一のパッケージに封入され、積層体を構成するメモリチップの少なくとも一部の信号線が、種類の異なる半導体チップの信号線に接続されてもよい。図６Ａ及び図６Ｂは、図３の半導体装置にＮＡＮＤコントローラチップ（メモリチップとは種類の異なる半導体チップ）を追加した場合の例を示す図であり、図６Ａは図６Ｂの面Ｐの平面図、図６Ｂは図６ＡのＢ－Ｂ線に沿う断面図である。図７は、図６Ａ及び図６Ｂのメモリチップ１０１とＮＡＮＤコントローラチップ１０２が相互に接続された様子を示す模式図である。 A semiconductor chip of a different type from the memory chip constituting the stacked body is enclosed in the same package as the stacked body, and at least a part of the signal lines of the memory chip constituting the stacked body is a signal line of a semiconductor chip of a different type. May be connected. 6A and 6B are diagrams illustrating an example where a NAND controller chip (a semiconductor chip of a different type from the memory chip) is added to the semiconductor device of FIG. 3, and FIG. 6A is a plan view of the plane P of FIG. 6B. 6B is a cross-sectional view taken along line BB in FIG. 6A. FIG. 7 is a schematic diagram showing a state in which the memory chip 101 and the NAND controller chip 102 in FIGS. 6A and 6B are connected to each other.
　図６Ａ及び図６Ｂに示すように、メモリチップ１０１を積層してパッケージに封止する際、メモリチップ１０１を制御するＮＡＮＤコントローラチップ１０２（以降、単にコントローラチップ１０２とする）も同一パッケージに封入すると好ましい。 As shown in FIGS. 6A and 6B, when the memory chips 101 are stacked and sealed in a package, a NAND controller chip 102 (hereinafter simply referred to as a controller chip 102) that controls the memory chip 101 is also enclosed in the same package. preferable.
　その場合は、最上層のメモリチップ１０１ａのパッド電極２０４とコントローラチップ１０２のパッド電極２０４ｃとを電気接続させて、接続配線３０３を介して、コントローラチップ１０２の外部接続端子３０２として出すことができる。もちろん、コントローラチップ１０２が最下層でもよいが、通常はコントローラチップ１０２はメモリチップ１０１よりも小さいので最上層とする方が好適である。コントローラチップ１０２がメモリチップ１０１よりも小さい場合には、コントローラチップ１０２の周辺部に絶縁層３０９を形成することができる。 In this case, the pad electrode 204 of the uppermost memory chip 101 a and the pad electrode 204 c of the controller chip 102 can be electrically connected to be output as the external connection terminal 302 of the controller chip 102 via the connection wiring 303. Of course, the controller chip 102 may be the lowermost layer, but since the controller chip 102 is usually smaller than the memory chip 101, the uppermost layer is preferred. In the case where the controller chip 102 is smaller than the memory chip 101, the insulating layer 309 can be formed on the periphery of the controller chip 102.
　パッケージの外部接続端子３０２はコントローラチップ１０２から出され、コントローラチップ１０２のメモリチップ１０１へ接続される端子はＴＳＶ２０１でメモリチップ１０１のパッド電極２０４に繋がる。図６Ａはコントローラチップ１０２の上面（図６Ｂにおいて回路形成されている面Ｐ）を示しており、Ｂ－Ｂ線はメモリチップ１０１に繋がるパッド電極２０４ｃとパッケージの端子に繋がるパッド電極２０４ｃの双方にかかっている。図６Ａ及び図６Ｂのコントローラチップ１０２は簡単のために、メモリチップ１０１に繋がるパッド電極の配置はメモリチップ１０１のパッド電極と同じにしたが、異なっている場合には、間にインターフェイスチップを挿入すればよい。 The external connection terminal 302 of the package is output from the controller chip 102, and the terminal connected to the memory chip 101 of the controller chip 102 is connected to the pad electrode 204 of the memory chip 101 by the TSV 201. FIG. 6A shows the upper surface of the controller chip 102 (surface P in which the circuit is formed in FIG. 6B), and the BB line is applied to both the pad electrode 204c connected to the memory chip 101 and the pad electrode 204c connected to the terminal of the package. It depends. 6A and 6B, for the sake of simplicity, the arrangement of the pad electrodes connected to the memory chip 101 is the same as the pad electrodes of the memory chip 101. If they are different, an interface chip is inserted between them. do it.
　又、図８のような構造にしてもよい。図８に示す半導体装置１００Ｂでは、最上層のメモリチップ１０１上に接着層２０５を介してコントローラチップ１０２を積層している。そして、コントローラチップ１０２のメモリチップ１０１へ接続すべき信号端子３０５を、ボンディングワイヤ１１０を介して、最上層のメモリチップ１０１のパッド電極３０４に接続している。 Alternatively, a structure as shown in FIG. In the semiconductor device 100 </ b> B shown in FIG. 8, the controller chip 102 is stacked on the uppermost memory chip 101 via the adhesive layer 205. The signal terminal 305 to be connected to the memory chip 101 of the controller chip 102 is connected to the pad electrode 304 of the uppermost memory chip 101 via the bonding wire 110.
　又、コントローラチップ１０２の外部接続端子へ接続すべき信号端子３０６を、ボンディングワイヤ１１０を介して、パッケージ基板３０１のボンディング用のパッド電極３０７に接続している。パッド電極３０７は、接続配線３０３を介して、半導体装置１００Ｂのピン１０３に繋がっている。 The signal terminal 306 to be connected to the external connection terminal of the controller chip 102 is connected to the bonding pad electrode 307 of the package substrate 301 via the bonding wire 110. The pad electrode 307 is connected to the pin 103 of the semiconductor device 100B through the connection wiring 303.
　このように、本実施の形態によれば、複数のメモリチップが積層された積層体において、メモリチップ同士はＴＳＶを介して接続されており、従来技術であるワイヤボンディングを用いていないため、従来に比べ、大幅に薄くかつ小さなパッケージで大容量の半導体記憶装置を実現できる。 As described above, according to the present embodiment, in a stacked body in which a plurality of memory chips are stacked, the memory chips are connected to each other through the TSV, and the conventional technique of wire bonding is not used. Compared to the above, a large-capacity semiconductor memory device can be realized with a much thinner and smaller package.
　又、複数のメモリチップが積層された積層体の最下層のメモリチップ上に積層された各々のメモリチップを厚さ方向に貫通して最下層のメモリチップのパッド電極と接続されたＴＳＶを有し、積層体の電源線及び信号線の少なくとも一方がＴＳＶを介して、積層体を構成する全てのメモリチップに共通に接続されている。そのため、ＴＳＶプロセスが簡易となり、低コスト且つ高歩留まりのＴＳＶ接続が実現できる。 In addition, each memory chip stacked on the lowermost memory chip of the stacked body in which a plurality of memory chips are stacked has a TSV penetrating in the thickness direction and connected to the pad electrode of the lowermost memory chip. In addition, at least one of the power supply line and the signal line of the stacked body is commonly connected to all the memory chips constituting the stacked body through the TSV. Therefore, the TSV process is simplified, and a low cost and high yield TSV connection can be realized.
　更に、積層体を構成するメモリチップとは種類の異なる半導体チップであるコントローラチップも積層体と同一パッケージに組み込むことが可能となる。但し、コントローラチップの組み込みはＴＳＶ技術に限らず、ワイヤボンディング法で行ってもよい。 Furthermore, a controller chip, which is a semiconductor chip of a different type from the memory chips constituting the stacked body, can be incorporated in the same package as the stacked body. However, the incorporation of the controller chip is not limited to the TSV technology, and may be performed by a wire bonding method.
　〈第２の実施の形態〉
　第２の実施の形態では、複数のメモリチップが積層され各メモリチップが共通ＴＳＶで接続された半導体記憶装置において、１つのメモリチップを選択して書き込み・消去・読み出しを行う方法を述べる。 <Second Embodiment>
In the second embodiment, a method of performing writing / erasing / reading by selecting one memory chip in a semiconductor memory device in which a plurality of memory chips are stacked and each memory chip is connected by a common TSV will be described.
　一つのメモリチップを選択するためには、各メモリチップ夫々に異なったアドレスを設定しなければならない。図９に示す様に、コントローラチップ１０２より選択すべきメモリチップ１０１のアドレス信号３３１を与えると、同一アドレスを持つメモリチップ１０１（図９中Ｓで表示）が動作状態になり、アドレスの異なる他のメモリチップ１０１は休止或いはアイドル状態となる。 In order to select one memory chip, a different address must be set for each memory chip. As shown in FIG. 9, when the address signal 331 of the memory chip 101 to be selected is given from the controller chip 102, the memory chip 101 having the same address (indicated by “S” in FIG. 9) enters the operating state, The memory chip 101 is in a paused or idle state.
　ＮＡＮＤフラッシュメモリの場合は、チップ内部のメモリアドレスはＩ／Ｏ端子より入力されるが、通常はメモリチップ内部のメモリセルの数だけのアドレスを入力するようになっている。しかし、多数のメモリチップを使用する前提で、上位となるメモリチップを選択するチップアドレスも同じくＩ／Ｏ端子への入力で設定できる設計も可能で、その場合はここで述べる例は使用しなくても１個のメモリチップを選択できる。しかしながら、この上位アドレス設定は予めウェハテスト（ＷＴ）にて設定（内部ヒューズメモリ書込み等）する必要があり、管理が大変となり、又、後述するパワーオン時の電源大電流ピークの問題がある。 In the case of a NAND flash memory, the memory address inside the chip is inputted from the I / O terminal, but normally addresses corresponding to the number of memory cells inside the memory chip are inputted. However, on the premise that a large number of memory chips are used, it is possible to design a chip address for selecting a higher-order memory chip by inputting to the I / O terminal. In that case, the example described here is not used. Even one memory chip can be selected. However, this upper address setting needs to be set in advance by a wafer test (WT) (internal fuse memory writing or the like), which makes management difficult, and causes a problem of a power source large current peak at power-on, which will be described later.
　そこで、本実施の形態では、各メモリチップ１０１に、各メモリチップが積層体の何層目に積層されているかを示すチップアドレスを設定する。なお、メモリチップ１０１を積層する前に、各メモリチップ１０１にアドレスを設定する。具体的な方法を以下に記す。 Therefore, in this embodiment, a chip address indicating how many layers of each memory chip are stacked is set in each memory chip 101. Note that an address is set for each memory chip 101 before the memory chips 101 are stacked. A specific method is described below.
　図１０Ａに示す様に、メモリチップ１０１はチップアドレスピンＡＩＮｊ（ｊは０、１、２等の整数を表し、チップアドレスに必要な数以上を持つ。例えば８チップなら少なくとも０、１、２）を持ち、又、同メモリチップ内には所定の複数の電位比較回路３３３が配置されている。各電位比較回路３３３は、１つのチップ選択回路３３４に接続されている。 As shown in FIG. 10A, the memory chip 101 has a chip address pin AINj (j represents an integer such as 0, 1, 2, etc., and has more than the number necessary for the chip address. For example, if there are 8 chips, at least 0, 1, 2) In addition, a plurality of predetermined potential comparison circuits 333 are arranged in the memory chip. Each potential comparison circuit 333 is connected to one chip selection circuit 334.
　電位比較回路３３３は、チップアドレスと、ＴＳＶを介して入力される信号とが一致するか否かを判別する回路であり、２つの入力端子を有する。電位比較回路３３３の一方の入力端子はチップアドレスピンＡＩＮｊと接続されており、電位比較回路３３３の他方の入力端子は２つの配線（高レベルの電位を持つ配線ＶＨと、低レベルの電位を持つ配線ＶＬ）と接続されている。なお、ＣＡｊは、電位比較回路３３３の他方の入力端子の電位を示している。 The potential comparison circuit 333 is a circuit that determines whether or not the chip address matches the signal input via the TSV, and has two input terminals. One input terminal of the potential comparison circuit 333 is connected to the chip address pin AINj, and the other input terminal of the potential comparison circuit 333 has two wirings (a wiring VH having a high level potential and a low level potential). Wiring VL). Note that CAj represents the potential of the other input terminal of the potential comparison circuit 333.
　そして、図１０Ｂ（ａ）に示す様に、その２つの配線ＶＨ、ＶＬの片方を切断し、高レベル或いは低レベルの配線（ＶＨ及びＶＬ）のどちらかの電位ＣＡｊを有する１つの配線のみが電位比較回路３３３の他方の入力端子に接続されるようにする。各配線には、例えば、ヒューズ素子を設けておき、必要に応じて切断すれば良い。なお、図１０Ｂ（ｂ）に示す電位比較回路３３３はＥｘ－ＯＲ（排他的論理和：Exclusive OR）回路である。 Then, as shown in FIG. 10B (a), one of the two wirings VH and VL is cut, and only one wiring having the potential CAj of either the high level or low level wiring (VH and VL) is obtained. The potential comparison circuit 333 is connected to the other input terminal. For example, each wiring may be provided with a fuse element and cut as necessary. Note that the potential comparison circuit 333 illustrated in FIG. 10B (b) is an Ex-OR (Exclusive OR) circuit.
　高レベル（ＶＨ、例えばＶｃｃ）或いは低レベル（ＶＬ、例えばＶｓｓ）の電位線のどちらを切断するかで、所定のメモリチップ１０１のチップアドレスを設定する。この仕組みを例えば３組用意すれば、３ビットの組み合わせができ、計８チップを選択できる。この切断の組み合わせは積層されるメモリチップ間でそれぞれ異なっており、同じものは無いようにする。なお、チップアドレスＡＩＮｊは図９のアドレス信号３３１に接続されるものである。 A chip address of a predetermined memory chip 101 is set depending on which one of the high level (VH, for example, Vcc) or low level (VL, for example, Vss) potential lines is cut. For example, if three sets of this mechanism are prepared, a combination of 3 bits can be made and a total of 8 chips can be selected. This combination of cutting differs between the stacked memory chips, so that there is no same thing. The chip address AINj is connected to the address signal 331 in FIG.
　図１０Ｂ（ｂ）に示すように、電位比較回路３３３では、コントローラチップ１０２から出されるチップアドレス信号ＡＩＮｎ（ｎも上記ｊと同様の整数を表す）と上記高レベル或いは低レベルの配線（ＶＨ及びＶＬ）のどちらかの電位ＣＡｎを比較し、両者がともに高レベル或いはともに低レベルであれば出力端子ＭＡｎから低レベルの信号（ｌｏｗ）を出す。又、両者が異なるレベルであれば出力端子ＭＡｎから高レベル電位の信号（ｈｉｇｈ）を出す。 As shown in FIG. 10B (b), in the potential comparison circuit 333, the chip address signal AINn (n also represents an integer similar to j above) output from the controller chip 102 and the high-level or low-level wiring (VH and VL) is compared, and if both are high or low, a low level signal (low) is output from the output terminal MAn. If the two levels are different, a high level signal (high) is output from the output terminal MAn.
　図１０Ｂ（ｃ）に示すように、各電位比較回路３３３からの出力線ＭＡｍ（ｍもｊ、ｎ同様の整数を表す）はチップ選択回路３３４への入力となっていて、チップ選択回路３３４においては全入力線ＭＡｍの電位が低レベルならば出力端子ＡＭａｔｃｈから高レベル電位の信号（ｈｉｇｈ）を出力し、本メモリチップ１０１が選択されたものと認識する。すなわち、コントローラチップ１０２からのチップアドレス信号ＡＩＮとそのメモリチップ１０１の高レベル／低レベル電位配線の切断の組み合わせＣＡが一致したとき、該当するメモリチップ１０１が選択される。 As shown in FIG. 10B (c), the output line MAm (m also represents an integer similar to j and n) from each potential comparison circuit 333 is an input to the chip selection circuit 334. Outputs a high level potential signal (high) from the output terminal AMatch if the potentials of all the input lines MAm are at a low level, and recognizes that the present memory chip 101 is selected. That is, when the chip address signal AIN from the controller chip 102 matches the combination CA of cutting the high-level / low-level potential wiring of the memory chip 101, the corresponding memory chip 101 is selected.
　なお、電位比較回路３３３の出力信号の高レベル／低レベルは逆でも良い。それに伴いチップ選択回路３３４では全入力線が高レベルになった時に出力端子ＡＭａｔｃｈから低レベル電位の信号（ｌｏｗ）を出力し、本メモリチップ１０１が選択されたものと認識するようにすれば良い。 Note that the high level / low level of the output signal of the potential comparison circuit 333 may be reversed. Accordingly, the chip selection circuit 334 may output a low level potential signal (low) from the output terminal AMatch when all the input lines become high level, and recognize that the present memory chip 101 is selected. .
　又、この高レベル／低レベル電位配線の切断の組み合わせＣＡｊをパワーオン・リセット回路のディレイ回路に入力するようにして、各メモリチップのパワーオンの開始タイミングを少しずつシフトすることができ、パワーオン時の電源電流のピークを下げることができる。これは多数の半導体メモリチップを集積する上では非常に重要なことで、大電流によるノイズや電源電圧降下と接地電圧上昇による誤動作が生じるおそれを低減できる。 In addition, the high-level / low-level potential line cutting combination CAj is input to the delay circuit of the power-on reset circuit, so that the power-on start timing of each memory chip can be shifted little by little. The peak of the power supply current at the time of ON can be lowered. This is very important in integrating a large number of semiconductor memory chips, and it is possible to reduce the possibility of noise caused by a large current and malfunction due to a power supply voltage drop and a ground voltage rise.
　以下に具体例を示す。図１１Ａは、メモリチップの内部回路の一部を例示するブロック図である。まず、図１１Ａに示すように、メモリチップ１０１内には電源Ｖｃｃの電圧を検知するパワーオン検知回路３４２とその検知信号を受けてメモリチップ１０１の初期設定動作を行う初期設定動作回路３４４が通常設けられているが、その間に、図１０Ａ等にて説明したチップ内部に形成されたチップアドレス信号ＣＡｊにより制御されるディレイ回路３４３をＣＡｊの数だけ（或いは上位の何個かのみ）挿入する。 Specific examples are shown below. FIG. 11A is a block diagram illustrating a part of the internal circuit of the memory chip. First, as shown in FIG. 11A, a power-on detection circuit 342 that detects the voltage of the power supply Vcc and an initial setting operation circuit 344 that performs an initial setting operation of the memory chip 101 in response to the detection signal are usually provided in the memory chip 101. In the meantime, a delay circuit 343 controlled by a chip address signal CAj formed in the chip described in FIG. 10A or the like is inserted in the meantime by the number of CAj (or only a few higher ranks).
　図１１Ｂは、メモリチップに内蔵されるディレイ回路を例示するブロック図である。ディレイ素子３５３は、ＣＡｊの信号により制御されるＭＯＳトランジスタよりなるスイッチ回路３５２により、ディレイ素子３５３のＩＮとＯＵＴが短絡されディレイが働かない場合と、短絡されずにディレイが働く場合とを切り替えることができる。 FIG. 11B is a block diagram illustrating a delay circuit built in the memory chip. The delay element 353 is switched by a switch circuit 352 made of a MOS transistor controlled by a signal of CAj between the case where the delay element 353 is short-circuited between IN and OUT, and the case where the delay works without being short-circuited. Can do.
　すなわち、ＣＡ０～２が例えば［０Ｖ，０Ｖ，０Ｖ］ならばディレイはなし、［Ｖｃｃ，Ｖｃｃ，Ｖｃｃ］ならば３個のディレイが働く。［０Ｖ，Ｖｃｃ，０Ｖ］や［０Ｖ，０Ｖ，Ｖｃｃ］は１個のディレイが働き、［Ｖｃｃ，Ｖｃｃ，０Ｖ］や［０Ｖ，Ｖｃｃ，Ｖｃｃ］は２個のディレイが働く。なお、３５１はインバータで、信号ＣＡｊの電圧レベルを反転させ、３５２はＰチャンネル及びＮチャンネルのＭＯＳトランジスタを並列接続したスイッチ回路を形成するものである。３５４はバッファ回路である。 That is, if CA0 to 2 is [0V, 0V, 0V], for example, there is no delay, and if [Vcc, Vcc, Vcc], three delays work. [0V, Vcc, 0V] and [0V, 0V, Vcc] work one delay, and [Vcc, Vcc, 0V] and [0V, Vcc, Vcc] work two delays. An inverter 351 inverts the voltage level of the signal CAj, and 352 forms a switch circuit in which P-channel and N-channel MOS transistors are connected in parallel. Reference numeral 354 denotes a buffer circuit.
　図１２は、ディレイ回路を搭載した場合の効果を説明する図であり、８層のメモリチップ１０１を積層した例で説明している。図１２（ａ）及び図１２（ｂ）において、１番上の図は電源Ｖｃｃの立上がり（パワーオン）を示しており、２番目の図は１層目のメモリチップ１０１の電源電流Ｉｃｃ、３番目の図は２層目のメモリチップ１０１の電源電流Ｉｃｃ、４番目の図は８層目のメモリチップ１０１の電源電流Ｉｃｃ、５番目（一番下）の図はトータル（８個のメモリチップ１０１）の電源電流Ｉｃｃを示している。なお、３層目～７層目のメモリチップ１０１の電源電流Ｉｃｃは図示を省略している。 FIG. 12 is a diagram for explaining the effect when a delay circuit is mounted, and an example in which eight layers of memory chips 101 are stacked is explained. 12A and 12B, the top diagram shows the rise (power-on) of the power supply Vcc, and the second diagram shows the power supply current Icc of the first- layer memory chip 101, 3 The second diagram shows the power supply current Icc of the second-layer memory chip 101, the fourth diagram shows the power-supply current Icc of the eighth-layer memory chip 101, and the fifth (bottom) diagram shows the total (eight memory chips). 101) is a power supply current Icc. The power supply current Icc of the memory chips 101 in the third to seventh layers is not shown.
　図１２（ａ）は従来のディレイ回路を搭載しない場合の例で、パワーオンの検知電圧を電源Ｖｃｃが越えた時点から全てのメモリチップ１０１の動作が開始され、電源電流Ｉｃｃのピークは１個のメモリチップの場合のほぼ８倍となる。 FIG. 12 (a) shows an example in which a conventional delay circuit is not installed. All memory chips 101 start operating from the time when the power supply Vcc exceeds the power-on detection voltage, and the power supply current Icc has one peak. This is almost 8 times that of the memory chip.
　図１２（ｂ）は図１１Ａ及び図１１Ｂに示すディレイ回路を搭載した場合で、各メモリチップはパワーオンの検知電圧を電源Ｖｃｃが越えた時点からディレイが働かない最初の１個、１個のディレイ（図１２では図示せず）が働く３個のメモリチップ、２個のディレイ（図１２のDelay-2）が働く３個のメモリチップ、そして３個のディレイが働く１個のメモリチップ（図１２のDelay-8）と順次初期設定動作を開始していくので、電源電流Ｉｃｃのピークは従来のほぼ半分となる。 FIG. 12B shows a case in which the delay circuit shown in FIGS. 11A and 11B is mounted. Each memory chip has the first one, one no delay from the time when the power supply Vcc exceeds the power-on detection voltage. Three memory chips with delays (not shown in FIG. 12), three memory chips with two delays (Delay-2 in FIG. 12), and one memory chip with three delays (Delay-2 in FIG. 12) Since the initial setting operation is sequentially started with Delay-8) in FIG. 12, the peak of the power supply current Icc is almost half that of the conventional one.
　図１１Ａ及び図１１Ｂの回路では一度に３個のチップが動作を開始したが、信号ＣＡｊをデコードし、ディレイ回路を８個用意して１個１個制御すれば、８段階のディレイで全てのメモリチップを異なるタイミングで動作させ、同時に動作するメモリチップをなくすことができる。その結果、電源電流Ｉｃｃのピークを従来のほぼ１／８にできる。 In the circuits of FIGS. 11A and 11B, three chips start operating at once. However, if the signal CAj is decoded and eight delay circuits are prepared and controlled one by one, all of the chips are controlled with eight stages of delay. The memory chips can be operated at different timings, and the memory chips operating at the same time can be eliminated. As a result, the peak of the power supply current Icc can be reduced to about 1/8 of the conventional one.
　以上のように、第２の実施の形態によれば、どの階層のメモリチップをアクセスするかを積層時に設定できるため、ウェハテスト（ＷＴ）以降の面倒な管理を回避できる。又、電源電圧のパワーオン検知回路と初期設定動作回路の間に複数のディレイ回路を設け、チップアドレスがディレイ回路を制御して、チップアドレスに対応したディレイを持つことにより、パワーオン検知から初期設定動作までに所定の遅延時間を設定できるため、パワーオン時の大電源電流ピークの問題も回避できる。更に、アクセスするメモリチップ以外はスタンバイモードにできるため、全体の消費電力も低減できる。 As described above, according to the second embodiment, which layer of memory chip is accessed can be set at the time of stacking, so that troublesome management after the wafer test (WT) can be avoided. A plurality of delay circuits are provided between the power-on detection circuit for the power supply voltage and the initial setting operation circuit, and the chip address controls the delay circuit to have a delay corresponding to the chip address. Since a predetermined delay time can be set before the setting operation, the problem of a large power supply current peak at power-on can also be avoided. Furthermore, since the memory chips other than the memory chip to be accessed can be set in the standby mode, the overall power consumption can be reduced.
　〈第３の実施の形態〉
　以上のようにメモリチップを積層する場合、各メモリチップはウェハ単位で積層され、ウェハ単位でＴＳＶが形成及び接続された後に切り離され（個片化され）、パッケージ封入されたものであるか、ウェハ単位で積層され、積層されたウェハ状態で一気にＴＳＶが形成及び接続された後に切り離され（個片化され）パッケージ封入されたものであるか、又は、ウェハ単位で積層され、ウェハ単位でＴＳＶが形成及び接続され、ウェハ単位でパッケージ封入された後に切り離され（個片化され）たものであることが好ましい。 <Third Embodiment>
When stacking memory chips as described above, each memory chip is stacked in units of wafers, TSVs are formed and connected in units of wafers, and then separated (separated) and packaged. Laminated in wafer units, TSVs are formed and connected at once in a laminated wafer state, and then separated (separated) and packaged, or laminated in wafer units and TSVs in wafer units. Are preferably formed and connected, separated after being packaged in wafer units (separated).
　しかし、各メモリチップをウェハ単位で積層し、後にダイシングする（チップ単位に切り離す）場合は、積層したメモリチップの中に不良品（以降、不良チップという）が含まれているおそれがある。例えば、ピン間のリーク電流が多い場合には、他のメモリチップの動作にも影響を与え、最悪の場合は動作しない。 However, when each memory chip is stacked in units of wafers and then diced (separated in units of chips), there is a possibility that defective products (hereinafter referred to as defective chips) are included in the stacked memory chips. For example, when the leakage current between pins is large, the operation of other memory chips is also affected, and in the worst case, the operation is not performed.
　そこで、ウェハを積層する前に、ウェハ内の各メモリチップについて良品・不良品の電気的測定及び判定を行い、不良品と判定されたメモリチップのパッド電極とそのパッド電極に繋がる内部配線とを電気的に絶縁する絶縁構造を有することが好ましい。 Therefore, before stacking the wafer, electrical measurement and determination of non-defective / defective products are performed for each memory chip in the wafer, and the pad electrode of the memory chip determined to be defective and the internal wiring connected to the pad electrode are determined. It is preferable to have an electrically insulating structure.
　具体的には、メモリチップのウェハを積層する前に該ウェハ上の各メモリチップのＤＣ的なリーク電流をモニタする。そして、規定値以上の電流が流れていれば、図１３Ａ及び図１３Ｂに示すように、不良チップを不活性にするために、電流に関与した配線４０１ないし全てのＴＳＶと繋がるべき配線を切断する。本実施の形態は、配線をヒューズとして切る方法を示す。その後不良チップを含めて、メモリチップのウェハを積層する。 Specifically, before stacking the memory chip wafers, the DC leakage current of each memory chip on the wafer is monitored. If a current exceeding a specified value flows, as shown in FIGS. 13A and 13B, in order to inactivate the defective chip, the wiring 401 related to the current or the wiring to be connected to all the TSVs is cut. . This embodiment shows a method of cutting a wiring as a fuse. Thereafter, wafers of memory chips including defective chips are stacked.
　なお、図１３Ａは平面図、図１３Ｂは図１３ＡのＣ－Ｃ線に沿う断面図であり、図１３Ｂ（ａ）は配線４０１を切断する前を示しており、図１３Ｂ（ｂ）は配線４０１を切断した後を破線で模式的に示している。又、４０２は絶縁膜である。 13A is a plan view, FIG. 13B is a cross-sectional view taken along the line CC of FIG. 13A, FIG. 13B (a) shows the state before cutting the wiring 401, and FIG. 13B (b) shows the wiring 401. After cutting is schematically shown by a broken line. Reference numeral 402 denotes an insulating film.
　第３の実施の形態によれば、各メモリチップのパッド電極と内部配線との間に切断可能なヒューズを設けることにより、積層したメモリチップからリーク電流の多いメモリチップを選択して電気的に排除できるため、リーク電流による誤動作や消費電流の増加を防止できる。 According to the third embodiment, by providing a severable fuse between the pad electrode and the internal wiring of each memory chip, a memory chip having a large leak current is selected from the stacked memory chips and electrically Since it can be eliminated, it is possible to prevent malfunction due to leakage current and increase in current consumption.
　〈第４の実施の形態〉
　第３の実施の形態で述べたように、不良と判断されるメモリチップ（不良チップ）は共通となるＴＳＶから電気的に絶縁する必要がある。本実施の形態は、不良チップをＴＳＶから電気的に絶縁させるために、選択されたパッド電極（不良チップのパッド電極）と、選択されたパッド電極（不良チップのパッド電極）を貫通するＴＳＶとの間に絶縁構造を設ける例を示す。図１４Ａ～図１４Ｉは第４の実施の形態に係る方法を説明するプロセスフロー図である。 <Fourth embodiment>
As described in the third embodiment, a memory chip (defective chip) determined to be defective needs to be electrically insulated from a common TSV. In this embodiment, in order to electrically insulate a defective chip from the TSV, a selected pad electrode (pad electrode of the defective chip) and a TSV penetrating the selected pad electrode (pad electrode of the defective chip) An example in which an insulating structure is provided between the two will be described. 14A to 14I are process flow diagrams for explaining a method according to the fourth embodiment.
　まず、図１４Ａ（ａ）に示すように、ウェハ・オン・ウェハ技術により積層されるべきメモリチップを有する複数のウェハ５００が準備される。次に、各ウェハ５００に対し、最初に電気的テスト（ウェハテスト）が行われ、図１４Ａ（ａ）に示すように、メモリチップ単位で良不良の判定がなされる（ＯＫは良品チップを、ＮＧは不良チップを示している）。不良チップ（ＮＧ）に対しては、不良情報に加え、ウェハ内での位置情報も記憶される。なお、本プロセスはウェハ単位で行われるが、説明の都合上、以降の図では１つの良品のメモリチップと１つの不良品のメモリチップ（不良チップ）についてのみ示す。 First, as shown in FIG. 14A (a), a plurality of wafers 500 having memory chips to be stacked by wafer-on-wafer technology are prepared. Next, an electrical test (wafer test) is first performed on each wafer 500, and as shown in FIG. 14A (a), good / bad determination is made on a memory chip basis (OK is a non-defective chip, NG indicates a defective chip). For defective chips (NG), positional information within the wafer is stored in addition to the defect information. Although this process is performed in units of wafers, for convenience of explanation, the following drawings show only one good memory chip and one defective memory chip (defective chip).
　次に、図１４Ａ（ｂ）に示したように、不良チップ（ＮＧ）の位置情報をもとに、ＴＳＶが形成・接続されるべき不良チップ（ＮＧ）の全てのパッド電極開口部２０４Ｗ上に絶縁膜５０２を選択的に形成する。なお、図１４Ａ（ｃ）に示したように、良品チップ（ＯＫ）のパッド電極開口部２０４Ｗ上には絶縁膜５０２を形成しない。選択的に絶縁膜５０２を形成する方法の一例として、スピン・オン・ガラスＳＯＧ（以下、ＳＯＧという。）をインクジェット印刷により不良チップ（ＮＧ）のＴＳＶが接続されるパッド電極上に塗布する方法を挙げることができる。 Next, as shown in FIG. 14A (b), based on the position information of the defective chip (NG), over all the pad electrode openings 204W of the defective chip (NG) to which the TSV is to be formed and connected. An insulating film 502 is selectively formed. As shown in FIG. 14A (c), the insulating film 502 is not formed on the pad electrode opening 204W of the non-defective chip (OK). As an example of a method of selectively forming the insulating film 502, a method of applying spin-on-glass SOG (hereinafter referred to as SOG) onto a pad electrode to which a defective chip (NG) TSV is connected by ink jet printing. Can be mentioned.
　具体的には、図１４Ｂに示すように、シリコン基板５０５上にパッド電極２０４Ｐを被覆するポリイミド等の絶縁層５０３及び５０４（パッシベーション膜）が形成された最下層のウェハに、絶縁層５０３及び５０４を貫通してパッド電極２０４Ｐの表面を露出する複数の貫通穴（開口部）を形成する。そして、図１４Ｂ（ａ）に示す不良チップ（ＮＧ）については、開口部内を含む所定の領域に絶縁膜５０２となる絶縁物質であるＳＯＧを塗布する。 Specifically, as shown in FIG. 14B, the insulating layers 503 and 504 are formed on the lowermost wafer in which insulating layers 503 and 504 (passivation film) such as polyimide covering the pad electrode 204P are formed on the silicon substrate 505. A plurality of through holes (openings) that expose the surface of the pad electrode 204P are formed. Then, for the defective chip (NG) shown in FIG. 14B (a), SOG which is an insulating material to be the insulating film 502 is applied to a predetermined region including the inside of the opening.
　インクジェット印刷を用いることで、絶縁のために塗布すべきところ以外にはＳＯＧは塗布されない。そのため、ＳＯＧパターンを形成するためのマスクが不要となり、通常、パターンを形成するのに必要なマスクの作製やフォトリソ・エッチングという工程が不要となり、製造コストの削減が可能となる。ＳＯＧ塗布の後、所定の温度でキュアを行う事で、十分絶縁性が確保された絶縁膜５０２を不良チップのＴＳＶが接続されるパッド電極２０４Ｐ上に形成することが可能である。なお、図１４Ｂ（ｂ）に示す良品チップ（ＯＫ）については、絶縁膜５０２を形成しない。 By using inkjet printing, SOG is not applied except where it should be applied for insulation. For this reason, a mask for forming the SOG pattern is not required, and a process of manufacturing a mask and photolithography / etching, which are usually necessary for forming the pattern, is not required, and the manufacturing cost can be reduced. By performing curing at a predetermined temperature after SOG application, it is possible to form the insulating film 502 with sufficient insulation on the pad electrode 204P to which the defective chip TSV is connected. Note that the insulating film 502 is not formed for the non-defective chip (OK) shown in FIG. 14B (b).
　次に、図１４Ｃに示すように、積層すべきウェハのうち、最下層に使用されるウェハに対してＴＳＶが形成されるパッド電極２０４Ｐ上へ金属層５０６の選択的な形成を行う。具体的には、例えばＴｉ／ＴｉＮ等のバリアメタル（図示せず）をスパッタ等で生成し、バリアメタル上に無電解めっき法等によりＣｕ等からなる金属層５０６を上記開口部が十分埋め込まれる程度に形成する。その後ＣＭＰ（Chemical Mechanical Polishing）等により金属層５０６のウェハ表面からの突出部分をウェハ表面から削り込むことで図１４Ｃの構造が完成する。 Next, as shown in FIG. 14C, the metal layer 506 is selectively formed on the pad electrode 204P where the TSV is formed on the wafer to be used as the lowermost layer among the wafers to be laminated. Specifically, for example, a barrier metal (not shown) such as Ti / TiN is generated by sputtering or the like, and the metal layer 506 made of Cu or the like is sufficiently embedded in the barrier metal by an electroless plating method or the like. Form to the extent. Thereafter, the projecting portion of the metal layer 506 from the wafer surface is etched from the wafer surface by CMP (Chemical Mechanical Polishing) or the like, thereby completing the structure of FIG. 14C.
　但し、図１４Ｃ（ａ）に示す不良チップ（ＮＧ）のパッド電極２０４Ｐではインクジェット印刷等により形成された絶縁膜５０２が存在している。そのため、不良チップ（ＮＧ）では、パッド電極２０４Ｐ上に絶縁膜５０２を介して金属層５０６が形成される。すなわち、不良チップ（ＮＧ）では、パッド電極２０４Ｐと金属層５０６とは導通しない。一方、図１４Ｃ（ｂ）に示す良品チップ（ＯＫ）では、絶縁膜５０２が存在しないため、パッド電極２０４Ｐと金属層５０６とは接触し導通する。 However, the pad electrode 204P of the defective chip (NG) shown in FIG. 14C (a) has an insulating film 502 formed by inkjet printing or the like. Therefore, in the defective chip (NG), the metal layer 506 is formed over the pad electrode 204P with the insulating film 502 interposed therebetween. That is, in the defective chip (NG), the pad electrode 204P and the metal layer 506 are not electrically connected. On the other hand, in the non-defective chip (OK) shown in FIG. 14C (b), since the insulating film 502 does not exist, the pad electrode 204P and the metal layer 506 are in contact with each other and become conductive.
　次に、図１４Ｄに示すように、ウェハの積層工程へと進む。ガラス等で補強されかつ所定の厚さに削り込まれた２層目のウェハを最下層のウェハに接着層２０５を介して積層する。そして、２層目のウェハにおいて、絶縁層５０３及び５０４を貫通してパッド電極２０４Ｐの表面を露出する複数の貫通穴（第１貫通穴）を形成する。図１４Ｄ（ａ）は、１層目の不良チップ（ＮＧ）上に良品チップ（ＯＫ）が積層された場合を示し、図１４Ｄ（ｂ）は、１層目の良品チップ（ＯＫ）上に不良チップ（ＮＧ）が積層された場合を示している。１層目と同様に、不良チップ（ＮＧ）については、貫通穴（第１貫通穴）内に露出するパッド電極２０４Ｐ上に絶縁膜５０２を形成する。 Next, as shown in FIG. 14D, the process proceeds to the wafer stacking process. A second wafer reinforced with glass or the like and cut into a predetermined thickness is laminated on the lowermost wafer via an adhesive layer 205. In the second wafer, a plurality of through holes (first through holes) that penetrate the insulating layers 503 and 504 and expose the surface of the pad electrode 204P are formed. FIG. 14D (a) shows a case where a non-defective chip (OK) is stacked on the first-layer defective chip (NG), and FIG. 14D (b) shows a defect on the first-layer defective chip (OK). A case where chips (NG) are stacked is shown. As with the first layer, for the defective chip (NG), the insulating film 502 is formed on the pad electrode 204P exposed in the through hole (first through hole).
　次に、図１４Ｅに示すように、全面にフォトレジスト５１０を塗布し、マスクを用いて通常のフォトリソグラフィー技術により、ＴＳＶを形成すべき領域のレジストを取り除く。その後、図１４Ｆに示すように、フォトレジスト５１０をマスクにして、絶縁膜５０２、パッド電極２０４Ｐ、絶縁層５０４、シリコン基板５０５、ウェハ間の接着層２０５をプラズマでエッチングし、１層目のウェハの金属層５０６でエッチングを止めることで、ＴＳＶの穴（第２貫通穴）が形成される。すなわち、２層目のウェハにおいて、各貫通穴（第１貫通穴）内に、２層目のウェハを厚さ方向に貫通し、最下層のウェハに形成された金属層５０６の表面を露出する貫通穴（第２貫通穴）が形成される。 Next, as shown in FIG. 14E, a photoresist 510 is applied on the entire surface, and the resist in a region where a TSV is to be formed is removed by a normal photolithography technique using a mask. Thereafter, as shown in FIG. 14F, the insulating film 502, the pad electrode 204P, the insulating layer 504, the silicon substrate 505, and the adhesive layer 205 between the wafers are etched by plasma using the photoresist 510 as a mask, and the first layer wafer By stopping etching at the metal layer 506, a TSV hole (second through hole) is formed. That is, in the second layer wafer, the second layer wafer is penetrated in the thickness direction in each through hole (first through hole), and the surface of the metal layer 506 formed on the lowermost wafer is exposed. A through hole (second through hole) is formed.
　この時、良品チップ（ＯＫ）では最初の絶縁膜５０２のエッチングステップで過剰のエッチングとなるが（絶縁膜５０２存在しないため）、絶縁膜５０２のエッチングにおいてはパッド電極２０４Ｐとのエッチングの選択比を十分とれる。そのため、パッド電極２０４Ｐはほとんどエッチングされないので、良品チップ（ＯＫ）でも問題なくＴＳＶのホールを形成できる。 At this time, in the non-defective chip (OK), excessive etching is performed in the first insulating film 502 etching step (because the insulating film 502 does not exist), but the etching selectivity with respect to the pad electrode 204P is set in the etching of the insulating film 502. Enough. Therefore, since the pad electrode 204P is hardly etched, TSV holes can be formed without any problem even with a non-defective chip (OK).
　その後、図１４Ｇに示すように、ＴＳＶのホール（第１貫通穴及び第２貫通穴）の側壁等を電気的に絶縁するための酸化膜等の絶縁膜２０３（第２絶縁膜）を、例えば低温のプラズマＣＶＤにより形成する。 After that, as shown in FIG. 14G, an insulating film 203 (second insulating film) such as an oxide film for electrically insulating the side walls and the like of the TSV holes (first through hole and second through hole), for example, It is formed by low temperature plasma CVD.
　更に、図１４Ｈに示すように、例えば異方性の強いＲＩＥを用い、絶縁膜２０３をエッチングすることでＴＳＶのホール底部の絶縁膜２０３がエッチングされ、側壁に絶縁膜２０３が残る。この時、図１４Ｈ（ａ）に示すように、２層目のウェハで良品チップ（ＯＫ）ではＴＳＶと接続される部分の絶縁膜２０３がエッチングされてパッド電極２０４Ｐの表面が露出している。一方、図１４Ｈ（ｂ）に示すように、不良チップ（ＮＧ）ではパッド電極２０４Ｐの表面は絶縁膜５０２で被覆されており、外部には露出していない。このようにして、２層目のウェハにおいて、ＴＳＶのホールの側壁（第１貫通孔の側壁及び第２貫通孔の側壁）のみに絶縁膜２０３（第２絶縁膜）が形成される。 Further, as shown in FIG. 14H, for example, by using RIE having strong anisotropy, the insulating film 203 is etched by etching the insulating film 203, and the insulating film 203 remains on the side wall. At this time, as shown in FIG. 14H (a), in the non-defective chip (OK) in the second layer wafer, the insulating film 203 in the portion connected to the TSV is etched to expose the surface of the pad electrode 204P. On the other hand, as shown in FIG. 14H (b), in the defective chip (NG), the surface of the pad electrode 204P is covered with the insulating film 502 and is not exposed to the outside. In this manner, in the second layer wafer, the insulating film 203 (second insulating film) is formed only on the side wall of the TSV hole (the side wall of the first through hole and the side wall of the second through hole).
　次に、図１４Ｉに示すように、ＴＳＶを完成するためにＴｉ／ＴｉＮ等のバリアメタル（図示せず）を形成し、無電解めっき等によりＴＳＶをＣｕ等の金属層２０２で埋め込む。更に、通常のＣＭＰ技術を用いて、ＴＳＶとチップのパッド電極２０４Ｐと接続されている部分以外の金属層２０２を除去する。これにより、２層目のウェハにおいて、ＴＳＶのホール内（第１貫通孔内及び第２貫通孔内）に、最下層のウェハに形成された金属層５０６と電気的に接続され、ＴＳＶの一部をなす金属層２０２（第２金属層）が形成され、２層目のウェハの積層が完成する。 Next, as shown in FIG. 14I, a barrier metal (not shown) such as Ti / TiN is formed to complete the TSV, and the TSV is embedded with a metal layer 202 such as Cu by electroless plating or the like. Further, the metal layer 202 other than the portion connected to the TSV and the pad electrode 204P of the chip is removed by using a normal CMP technique. Accordingly, in the second layer wafer, the TSV hole (in the first through hole and the second through hole) is electrically connected to the metal layer 506 formed in the lowermost wafer, and one TSV A metal layer 202 (second metal layer) forming a part is formed, and the lamination of the second wafer is completed.
　この時、良品チップ（ＯＫ）においては、チップのパッド電極２０４ＰとＴＳＶの金属層２０２は電気的に接続されているが、不良チップ（ＮＧ）はパッド電極２０４Ｐが絶縁膜５０２で覆われているため、ＴＳＶの金属層２０２とは電気的に絶縁されている。 At this time, in the non-defective chip (OK), the pad electrode 204P of the chip and the metal layer 202 of the TSV are electrically connected, but in the defective chip (NG), the pad electrode 204P is covered with the insulating film 502. Therefore, it is electrically insulated from the TSV metal layer 202.
　３層目以降のウェハ積層に対しても同様な工程を繰り返して順次積層することで、ＴＳＶから不良チップ（ＮＧ）が選択的に絶縁された複数のウェハを積層した半導体記憶装置（ＮＡＮＤフラッシュメモリデバイス）が形成される。 A semiconductor memory device (NAND flash memory) in which a plurality of wafers in which defective chips (NG) are selectively insulated from TSVs are stacked by sequentially stacking the same processes for the third and subsequent wafers. Device) is formed.
　第４の実施の形態によれば、積層されたメモリチップ中の不良と判定されるチップ（不良チップ）を選択的に電気的に排除できる。更に、第３の実施の形態のようにヒューズの切断という工程が必要でなく、選択的に絶縁膜を形成するのにインクジェット印刷技術を用いているため、製造コストの大きな低減が可能である。 According to the fourth embodiment, chips (defective chips) determined to be defective in the stacked memory chips can be selectively electrically excluded. Further, the step of cutting the fuse as in the third embodiment is not necessary, and since the ink jet printing technique is used to selectively form the insulating film, the manufacturing cost can be greatly reduced.
　〈第５の実施の形態〉
　第４の実施の形態は、第２の実施の形態に示された、どの階層のメモリチップを選択するかのチップアドレスの指定方法や何層目かを示すシグネチャーの書込みにも応用できる。第２の実施の形態では、図９、図１０Ａ、及び図１０Ｂで示したように、積層したチップの内部に保持したチップアドレスとコントローラチップから出力されるアドレスとの一致をみて選択されたメモリチップを判定する方式をとり、これはＤＲＡＭやＳＲＡＭ等のアドレスピンを持つものに類似の方法である。 <Fifth embodiment>
The fourth embodiment can be applied to the chip address designation method for selecting which memory chip to select and the writing of the signature indicating the number of layers shown in the second embodiment. In the second embodiment, as shown in FIG. 9, FIG. 10A, and FIG. 10B, the memory selected in consideration of the coincidence of the chip address held in the stacked chip and the address output from the controller chip A method of determining a chip is used, which is similar to a method having an address pin such as DRAM or SRAM.
　しかしながら、一般にＮＡＮＤフラッシュメモリはアドレスピンを持たずに該チップ内のメモリセルのアドレスは入出力ピンから入力データとして入力されるので、該入力データの上位ビットにチップアドレスを拡張して割り付ける方式をとる方が好ましい。この場合、ＮＡＮＤフラッシュメモリのチップアドレスの設定方法として、そのために用意したいくつかの入力パッドにワイヤボンディングを通じて電源電圧Ｖｃｃ或いは接地電圧Ｖｓｓを接続して設定する方法を用いることができる。なお、図１０Ｂ（ｂ）におけるアドレス入力ＡＩＮｎは該入力データからチップ内部回路を通じて与えることができる。 However, in general, a NAND flash memory does not have an address pin, and the address of a memory cell in the chip is input as input data from an input / output pin. Therefore, a system in which the chip address is extended and assigned to the upper bits of the input data is used. It is preferable to take. In this case, as a method for setting the chip address of the NAND flash memory, it is possible to use a method in which the power supply voltage Vcc or the ground voltage Vss is set by connecting several input pads prepared therefor through wire bonding. Note that the address input AINn in FIG. 10B (b) can be given from the input data through a chip internal circuit.
　図１５Ａ及び図１５Ｂに代表的なボンディング・オプションによるチップアドレスの設定方法を示す。図１５Ａは入力回路にプルアップ回路４２３が付いているもので、パッド４１１（接地電圧Ｖｓｓ）に接続したいパッド電極２０４Ｐのみとボンディングワイヤにより接続する。なお、４２１はプルアップ用トランジスタ、４２２はバッファ回路である。 15A and 15B show chip address setting methods using typical bonding options. In FIG. 15A, a pull-up circuit 423 is attached to the input circuit, and only the pad electrode 204P to be connected to the pad 411 (ground voltage Vss) is connected by a bonding wire. Reference numeral 421 denotes a pull-up transistor, and 422 denotes a buffer circuit.
　これに対して、図１５Ｂに示すようにプルアップ回路（或いはプルダウン回路）がない入力回路４２４の場合は、ハイレベル或いはローレベルの２種類のパッド４１１が必要となる。各パッド電極２０４Ｐをハイレベル或いはローレベルの何れか一方とボンディングワイヤにより接続する。図１５Ｂの類似の例として、チップセレクトＣＥを２つの信号チップセレクト１（ＣＥ１）とチップセレクト２（ＣＥ２）に分けてボンディング・オプションするものがある。 On the other hand, in the case of the input circuit 424 having no pull-up circuit (or pull-down circuit) as shown in FIG. 15B, two kinds of pads 411 of high level or low level are required. Each pad electrode 204P is connected to either the high level or the low level by a bonding wire. As a similar example of FIG. 15B, there is a chip selection CE divided into two signal chip select 1 (CE1) and chip select 2 (CE2) for bonding option.
　〈第５の実施の形態－１〉
　一般的に、積層すべきメモリチップ数がＮの場合、Ｎ＝２ＸとなるＸビットのチップアドレス（或いはシグネチャー）回路が準備される。図１５Ａに示すようにメモリチップ内のチップアドレス設定用入力パッド２０４Ｐにプルアップ回路（或いはプルダウン回路）４２３がある場合は、所定の電圧（接地電圧Ｖｓｓ或いは電源電圧Ｖｃｃ）に接続したいパッド電極にのみＴＳＶを接続し、そうでないパッド電極に対してはＴＳＶから絶縁することで、図１５Ａに示すパッド４１１とパッド電極とのボンディングでの接続を廃止できる。 <Fifth Embodiment-1>
Generally, the memory chip number to be stacked if the N, N = 2 X become X-bit chip address (or signature) circuit is prepared. As shown in FIG. 15A, when the chip address setting input pad 204P in the memory chip has a pull-up circuit (or pull-down circuit) 423, the pad electrode to be connected to a predetermined voltage (ground voltage Vss or power supply voltage Vcc) is used. By connecting only the TSV and insulating the other pad electrodes from the TSV, the connection by bonding between the pad 411 and the pad electrode shown in FIG. 15A can be eliminated.
　具体的には、各パッド電極に対して１本のＴＳＶを用意して、第４の実施の形態の「ＴＳＶに接続する、絶縁する」方法を適用すれば良い。この実施の形態の断面図を図１６に示す。図１５Ａはプルアップの回路なので図１６のＴＳＶは接地電圧Ｖｓｓとなる。 Specifically, one TSV may be prepared for each pad electrode, and the “connecting and insulating to TSV” method of the fourth embodiment may be applied. A cross-sectional view of this embodiment is shown in FIG. Since FIG. 15A is a pull-up circuit, TSV in FIG. 16 becomes the ground voltage Vss.
　図１６では、１層目のメモリチップ（１）では、Ｂｉｔ－０に対応するパッド電極２０４Ｐは絶縁膜５０２で被覆されているためＢｉｔ－０＝‘１’となり、Ｂｉｔ－１及びＢｉｔ－２に対応するパッド電極２０４Ｐは絶縁膜で被覆されていないため接地電圧ＶｓｓのＴＳＶと接続されＢｉｔ－１＝Ｂｉｔ－２＝‘０’となる。同様に、２層目のメモリチップ（２）では、Ｂｉｔ－０＝‘１’、Ｂｉｔ－１＝‘０’、Ｂｉｔ－２＝‘１’となる。又、３層目のメモリチップ（３）では、Ｂｉｔ－０＝‘０’、Ｂｉｔ－１＝‘１’、Ｂｉｔ－２＝‘０’となる。 In FIG. 16, in the first-layer memory chip (1), since the pad electrode 204P corresponding to Bit-0 is covered with the insulating film 502, Bit-0 = '1', and Bit-1 and Bit-2 Since the pad electrode 204P corresponding to is not covered with an insulating film, it is connected to the TSV of the ground voltage Vss, and Bit-1 = Bit-2 = '0'. Similarly, in the second-layer memory chip (2), Bit-0 = '1', Bit-1 = '0', and Bit-2 = '1'. In the third-layer memory chip (3), Bit-0 = '0', Bit-1 = '1', Bit-2 = '0'.
　このように、各メモリチップに、チップアドレスを設定するためのパッド電極、入力部のプルアップ回路又はプルダウン回路、及びチップアドレスを設定するためのパッド電極を貫通し所定の電圧（接地電圧Ｖｓｓ或いは電源電圧Ｖｃｃ）に接続されるＴＳＶを設ける。そして、第４の実施の形態のパッド電極とＴＳＶとを電気的に絶縁する構造を、チップアドレスを設定するためのパッド電極に選択的に適用することにより、任意のチップアドレスを設定することができる。 As described above, each memory chip has a pad electrode for setting a chip address, a pull-up circuit or pull-down circuit for an input unit, and a pad electrode for setting a chip address, and a predetermined voltage (ground voltage Vss or A TSV connected to the power supply voltage Vcc) is provided. An arbitrary chip address can be set by selectively applying the structure of electrically insulating the pad electrode and TSV of the fourth embodiment to the pad electrode for setting the chip address. it can.
　〈第５の実施の形態－２〉
　図１５Ｂに示すようにプルアップ回路（或いはプルダウン回路）がない入力回路４２４の場合は、メモリチップ１０１内のチップアドレス設定用入力パッド２０４Ｐにはそれぞれ電源電圧Ｖｃｃ或いは接地電圧Ｖｓｓレベルのパッド４１１を接続しなければならない。そのためには各パッドに対して２本のＴＳＶ、電源電圧Ｖｃｃと接地電圧Ｖｓｓが必要となる。所定の電圧（接地電圧Ｖｓｓ或いは電源電圧Ｖｃｃ）に接続したいパッド電極に何れか一方のＴＳＶを接続し、他方のＴＳＶから絶縁することで、図１５Ｂに示すパッド４１１とパッド電極とのボンディングでの接続を廃止できる。具体的な方法を以下に示す。 <Fifth embodiment-2>
In the case of the input circuit 424 having no pull-up circuit (or pull-down circuit) as shown in FIG. 15B, the pad 411 at the power supply voltage Vcc level or the ground voltage Vss level is provided on the chip address setting input pad 204P in the memory chip 101, respectively. Must be connected. For this purpose, two TSVs, a power supply voltage Vcc and a ground voltage Vss are required for each pad. By connecting any one TSV to a pad electrode to be connected to a predetermined voltage (ground voltage Vss or power supply voltage Vcc) and insulating it from the other TSV, the pad 411 and the pad electrode shown in FIG. Connection can be abolished. A specific method is shown below.
　図１７Ａは、通常の大きさの２つのパッド電極２０４Ｐが隣接して配置され、共通の配線に接続された様子を模式的に示した図である。図１７Ａに示すように、チップアドレス１ビットの入力に対して、隣接して配置された２つのパッド電極２０４Ｐの一方を貫通するＴＳＶ２０１ａと他方を貫通するＴＳＶ２０１ｂを形成する。なお、図１７ＡのＢｉｔ－０（ＣＡ０）、Ｂｉｔ－１（ＣＡ１）、及びＢｉｔ－２（ＣＡ２）は、電位比較回路３３３（図１０Ａ及び図１０Ｂ参照）の入力ＣＡｊに接続される。 FIG. 17A is a diagram schematically showing a state in which two pad electrodes 204P having a normal size are arranged adjacent to each other and connected to a common wiring. As shown in FIG. 17A, a TSV 201a penetrating one of two adjacent pad electrodes 204P and a TSV 201b penetrating the other are formed for an input of 1 bit of a chip address. Note that Bit-0 (CA0), Bit-1 (CA1), and Bit-2 (CA2) in FIG. 17A are connected to the input CAj of the potential comparison circuit 333 (see FIGS. 10A and 10B).
　図１７ＡのＤ－Ｄ線に沿う断面図である図１７Ｂに示すように、それぞれのウェハ、それぞれのチップに対して、隣接するパッド電極２０４Ｐ上の電源電圧Ｖｃｃに接続されるＴＳＶ２０１ａが形成される開口部か、接地電圧Ｖｓｓに接続されるＴＳＶ２０１ｂが形成される開口部かの何れかに、インクジェット印刷を用いて選択的にＳＯＧを塗布して絶縁膜５０２を形成し、絶縁構造とすることで、各ビット信号ＣＡｊの電位を選択できる。ＴＳＶ２０１ａ又は２０１ｂと選択的に接続されたＢｉｔ－０（ＣＡ０）、Ｂｉｔ－１（ＣＡ１）、及びＢｉｔ－２（ＣＡ２）は、電位比較回路３３３（図１０Ａ及び図１０Ｂ参照）の入力ＣＡｊに接続される。 As shown in FIG. 17B, which is a cross-sectional view taken along the line DD in FIG. 17A, TSV 201a connected to power supply voltage Vcc on adjacent pad electrode 204P is formed for each wafer and each chip. An insulating film 502 is formed by selectively applying SOG to the opening or the opening where the TSV 201b connected to the ground voltage Vss is formed by using inkjet printing. The potential of each bit signal CAj can be selected. Bit-0 (CA0), Bit-1 (CA1), and Bit-2 (CA2) selectively connected to the TSV 201a or 201b are connected to the input CAj of the potential comparison circuit 333 (see FIGS. 10A and 10B). Is done.
　例えば、ビット０のチップアドレスＣＡ０が１層目は“０”、２層目は“０”、３層目は“１”となる場合を考える。この場合、図１７Ｂに示したように１層目のメモリチップ（１）及び２層目のメモリチップ（２）では、電源電圧Ｖｃｃに接続されるＴＳＶ２０１ａが形成される開口部に絶縁膜５０２を形成し、３層目のメモリチップ（３）では、接地電圧Ｖｓｓに接続されるＴＳＶ２０１ｂが形成される開口部に絶縁膜５０２を形成すればよい。 For example, consider the case where the chip address CA0 of bit 0 is “0” for the first layer, “0” for the second layer, and “1” for the third layer. In this case, as shown in FIG. 17B, in the first-layer memory chip (1) and the second-layer memory chip (2), the insulating film 502 is formed in the opening where the TSV 201a connected to the power supply voltage Vcc is formed. In the third-layer memory chip (3), the insulating film 502 may be formed in the opening where the TSV 201b connected to the ground voltage Vss is formed.
　又、図１７Ｃに示すように、パッド電極２０４Ｐに接続されるＴＳＶ２０１ａ及び２０１ｂは、パッケージ基板３０１内の接続配線３０３ａ及び３０３ｂを介して、外部接続端子３０２に接続することができる。なお、図１７Ｃでは、図１７Ｂ等に示す絶縁膜２０３、５０２の図示は省略されている。 Further, as shown in FIG. 17C, the TSVs 201a and 201b connected to the pad electrode 204P can be connected to the external connection terminal 302 via the connection wirings 303a and 303b in the package substrate 301. In FIG. 17C, the insulating films 203 and 502 shown in FIG. 17B and the like are not shown.
　この工程は第４の実施の形態の不良チップに対する工程と同等であることから、第４の実施の形態で不良チップのＴＳＶに接続するパッド電極にＳＯＧを塗布する際、同時にこのチップアドレス或いはシグネチャービットのパッド電極にも必要な部分にＳＯＧを塗布することだけで実現される。これにより、何層目のチップが全体のメモリ領域のどのアドレスに対応すべきかを認識することができる。 Since this process is equivalent to the process for the defective chip of the fourth embodiment, when applying SOG to the pad electrode connected to the TSV of the defective chip in the fourth embodiment, this chip address or signature is simultaneously applied. This is realized only by applying SOG to a necessary portion of the pad electrode of the bit. As a result, it is possible to recognize which layer of the chip should correspond to which address in the entire memory area.
　このように、各メモリチップに、第１の電圧（電源電圧Ｖｃｃ）に接続されたＴＳＶ２０１ａが貫通する第１パッド電極と、第２の電圧（接地電圧Ｖｓｓ）に接続されたＴＳＶ２０１ｂが貫通する第２パッド電極とを設けて共通の配線に接続し、第４の実施の形態のパッド電極とＴＳＶとを電気的に絶縁する構造を、第１パッド電極又は第２パッド電極に選択的に適用することにより、任意のチップアドレスを設定することができる。 In this manner, each memory chip has a first pad electrode through which TSV 201a connected to the first voltage (power supply voltage Vcc) passes and a TSV 201b connected to the second voltage (ground voltage Vss) through which the first pad electrode penetrates. A structure in which two pad electrodes are provided and connected to a common wiring, and the pad electrode and the TSV of the fourth embodiment are electrically insulated is selectively applied to the first pad electrode or the second pad electrode. Thus, an arbitrary chip address can be set.
　類似の例として、第１パッド電極及び第２パッド電極を各々別の外部信号線に接続してもよい。例えば、第１パッド電極及び第２パッド電極がチップ選択信号の入力パッドであり、外部信号線が２つのチップ選択信号線（チップセレクト１、チップセレクト２）である場合を挙げることができる。もちろん、３つ以上のパッド電極を設ければ、３つ以上のチップ選択信号線（チップセレクト１、チップセレクト２、・・・）に対応可能である。 As a similar example, the first pad electrode and the second pad electrode may be connected to different external signal lines. For example, the first pad electrode and the second pad electrode are chip selection signal input pads, and the external signal lines are two chip selection signal lines (chip select 1 and chip select 2). Of course, if three or more pad electrodes are provided, three or more chip selection signal lines (chip select 1, chip select 2,...) Can be handled.
　〈第５の実施の形態－３〉
　上記の図１７Ａ及び図１７Ｂによる方法では、１つのＢｉｔに対して通常のパッド電極２個分以上の領域が必要であるため、現在のメモリチップの修正が必要になり好ましくない。パッド電極２０４Ｐは８０～１００μｍ、ＴＳＶ２０１の穴は１０μｍ以下とできるので、図１８に示すように通常の１個分のパッド電極内に２つ以上のＴＳＶ領域を作製することができる。機能は図１７Ａ及び図１７Ｂと同じである。図１８（ａ）は３ビット分のパッド電極の平面図、図１８（ｂ）は１個のパッド電極の拡大図、図１８（ｃ）は図１８（ｂ）のＥ－Ｅ線に沿う断面図である。 <Fifth Embodiment-3>
In the method according to FIGS. 17A and 17B described above, an area equal to or more than two normal pad electrodes is required for one bit, which is not preferable because the current memory chip needs to be corrected. Since the pad electrode 204P can be 80 to 100 μm and the hole of the TSV 201 can be 10 μm or less, two or more TSV regions can be formed in one normal pad electrode as shown in FIG. The function is the same as in FIGS. 17A and 17B. 18A is a plan view of a pad electrode for 3 bits, FIG. 18B is an enlarged view of one pad electrode, and FIG. 18C is a cross section taken along line EE in FIG. 18B. FIG.
　なお、図１８（ｂ）では、パッド開口部を４つに分けた場合を示したが当然２つに分けただけでも良い。又、使用しない２つの領域はパッド電極２０４Ｐが上から見えるように表示したが、金属層又は絶縁層で埋める処置を行うことが好ましい。 Although FIG. 18B shows a case where the pad opening is divided into four parts, it may be divided into two. In addition, although the two unused areas are displayed so that the pad electrode 204P can be seen from above, it is preferable to perform a treatment of filling with a metal layer or an insulating layer.
　このように、通常の１個分のパッド電極上に形成された絶縁層でパッド電極を複数の領域に分離し、パッド電極の各領域を貫通するＴＳＶを設けることができる。なお、パッド電極上に形成する絶縁層は、１層目のウェハの場合は２層目のウェハの積層前に形成され、２層目以降のウェハの場合はそのウェハの積層直後に形成される。 Thus, a TSV penetrating each region of the pad electrode can be provided by separating the pad electrode into a plurality of regions by an insulating layer formed on a normal pad electrode. The insulating layer formed on the pad electrode is formed before the second wafer is stacked in the case of the first wafer, and is formed immediately after the wafer is stacked in the second and subsequent wafers. .
　図１９Ａ～図１９Ｄにその作製工程の例を示す。図１９Ａ（ａ）に示すように、シリコン基板５０５上にパッド電極２０４Ｐを被覆するポリイミド等の絶縁層５０４（パッシベーション膜）が形成された最下層のウェハに、絶縁層５０４を貫通してパッド電極２０４Ｐの表面を露出する複数のパッド電極開口部２０４Ｗ（貫通穴）を形成する。なお、本実施の形態の場合は絶縁層５０３は不要であるが、これは特にプロセス上の問題とはならない。又、絶縁層５０３がなくても絶縁層５０４があるので電気的試験ＷＴは問題なくできる。この状態で、図１９Ａ（ｂ）に示すようにＳＯＧ膜やポリイミド膜を塗布コーティング及び平坦化し、絶縁層５２３を形成する。 19A to 19D show an example of the manufacturing process. As shown in FIG. 19A (a), a pad electrode penetrating through the insulating layer 504 is formed on the lowermost wafer in which an insulating layer 504 (passivation film) such as polyimide covering the pad electrode 204P is formed on the silicon substrate 505. A plurality of pad electrode openings 204W (through holes) that expose the surface of 204P are formed. Note that the insulating layer 503 is not necessary in this embodiment mode, but this is not a problem in the process. In addition, since there is the insulating layer 504 without the insulating layer 503, the electrical test WT can be performed without any problem. In this state, as shown in FIG. 19A (b), an SOG film or a polyimide film is applied and flattened to form an insulating layer 523.
　次に、図１９Ｂ（ａ）に示すように、フォトレジストとマスクを使用して、パッド電極開口部２０４Ｗ内の絶縁層５２３の一部を除去し、パッド電極開口部２０４Ｗの中央部にＴＳＶの金属層２０２の隔壁を形成する。この後は、図１９Ｂ（ｂ）～図１９Ｄ（ｃ）に示すように、第４の実施の形態の図１４Ｂ（ａ）～図１４Ｉ（ｂ）に示す工程と同様である。 Next, as shown in FIG. 19B (a), a part of the insulating layer 523 in the pad electrode opening 204W is removed using a photoresist and a mask, and a TSV is formed in the center of the pad electrode opening 204W. A partition wall of the metal layer 202 is formed. Thereafter, as shown in FIGS. 19B (b) to 19D (c), the process is the same as the steps shown in FIGS. 14B (a) to 14I (b) of the fourth embodiment.
　このように、各メモリチップの１つのパッド電極（通常の大きさ）に、第１の電圧（電源電圧Ｖｃｃ）に接続されたＴＳＶ２０１ａが貫通する第１領域と、第２の電圧（接地電圧Ｖｓｓ）に接続されたＴＳＶ２０１ｂが貫通する第２領域とを設け、第４の実施の形態のパッド電極とＴＳＶとを電気的に絶縁する構造を、第１領域を貫通するＴＳＶ２０１ａ又は第２領域を貫通するＴＳＶ２０１ｂに選択的に適用することにより、任意のチップアドレスを設定することができる。 As described above, the first region through which the TSV 201a connected to the first voltage (power supply voltage Vcc) passes through one pad electrode (normal size) of each memory chip, and the second voltage (ground voltage Vss). The TSV 201b connected to the TSV 201b and the TSV 201b penetrating the first region, or the second region through which the pad electrode and the TSV of the fourth embodiment are electrically insulated are provided. By selectively applying to the TSV 201b to be performed, an arbitrary chip address can be set.
　〈第５の実施の形態－４〉
　第５の実施の形態－２及び第５の実施の形態－３では、１つの入力回路に２本のＴＳＶの一方を接続する例を示したが、ＴＳＶ本数は２本に限られないことは明白である。特に第５の実施の形態－３では、図１８（ｂ）から少なくとも４本のＴＳＶが可能であることがわかる。そして、コントローラチップからチップ選択信号を４本（例えばＣＥ０，ＣＥ１，ＣＥ２，ＣＥ３）出すようにし、これらをそれぞれ上記４本のＴＳＶに対応させ、メモリチップのチップ選択信号パッドに適用すれば、更に多くのチップを積層できる。ここで、チップ選択信号というのは、ＮＡＮＤフラッシュメモリに限らずメモリデバイスなら持っている、チップ・セレクト（ＣＳ）或いはチップ・イネーブル（ＣＥ）と言われる、そのメモリチップを選択して動作を行うための入力信号を指している。 <Fifth Embodiment-4>
In the fifth embodiment-2 and the fifth embodiment-3, an example is shown in which one of two TSVs is connected to one input circuit. However, the number of TSVs is not limited to two. It is obvious. In particular, in the fifth embodiment-3, it can be seen from FIG. 18B that at least four TSVs are possible. Then, if four chip selection signals (for example, CE0, CE1, CE2, CE3) are output from the controller chip, these correspond to the four TSVs, respectively, and are applied to the chip selection signal pads of the memory chip. Many chips can be stacked. Here, the chip selection signal is not limited to the NAND flash memory, but is selected by the memory chip called chip select (CS) or chip enable (CE), which is possessed by any memory device. Points to the input signal.
　このように、第５の実施の形態によれば、積層されたメモリチップがどの層にあるかを示すチップアドレス或いはシグネチャーを、第４の実施の形態の不良チップに対する工程と共有化できるため、製造コスト低減につながる。 Thus, according to the fifth embodiment, the chip address or signature indicating which layer the stacked memory chip is in can be shared with the process for the defective chip of the fourth embodiment. This leads to reduced manufacturing costs.
　〈第６の実施の形態〉
　上記のようにウェハ・オン・ウェハでウェハ状態で積層する場合は、ウェハで積層して最後に積層したチップをダイシング（切り離す）して製品メモリチップとして出荷しなければならない。従来では１チップ毎にダイシングしてパッケージ封入していたが、本実施の形態では、積層した単位での２チップや４チップのグループ単位でダイシングして、メモリチップの積層体を複数個有するようにパッケージングする。これにより、従来の１チップ単位のパッケージでの実装よりも高密度化が可能となる。 <Sixth embodiment>
In the case of stacking in a wafer state on a wafer-on-wafer as described above, the chip stacked on the wafer and finally stacked must be diced (separated) and shipped as a product memory chip. Conventionally, a package is encapsulated by dicing every chip, but in this embodiment, a plurality of memory chip stacks are formed by dicing in groups of 2 chips or groups of 4 chips. To package. As a result, it is possible to achieve higher density than the conventional one-chip package mounting.
　図２０Ａに２個の積層チップを一単位としてパッケージングするため、同一信号線をパッケージ基板３０１内で結線して２倍の積層化チップと同等の状態を実現した様子を示す。図２０Ａ（ａ）は平面図、図２０Ａ（ｂ）は断面図である。チップ選択信号ＣＥのみをＣＥ１、ＣＥ２のように独立させるか、データ入出力端子Ｉ／Ｏを独立させ２倍のデータ幅として使用することができる。なお、パッケージ基板３０１内での結線に代えて、プリント基板の配線を用いてもよい。 FIG. 20A shows a state in which the same signal line is connected in the package substrate 301 to realize a state equivalent to a double stacked chip in order to package two stacked chips as a unit. 20A (a) is a plan view, and FIG. 20A (b) is a cross-sectional view. Only the chip selection signal CE can be made independent as CE1 and CE2, or the data input / output terminal I / O can be made independent and used as a double data width. Note that wiring of a printed circuit board may be used instead of connection within the package substrate 301.
　図２０Ｂに２個の積層チップを一単位としてパッケージングするため、同一信号線をパッケージ基板３０１内で結線して２倍の積層化チップと同等の状態を実現した様子を示す（図２０Ａとは別の例）。図２０Ｂ（ａ）は平面図、図２０Ｂ（ｂ）は断面図である。チップ選択信号ＣＥのみをＣＥ１、ＣＥ２のように独立させるか、データ入出力端子Ｉ／Ｏを独立させ２倍のデータ幅として使用することができる。なお、パッケージ基板３０１内での結線に代えて、プリント基板の配線を用いてもよい。図２０Ａとの差は、パッケージ基板３０１内の配線が単層になっていることで、図２０Ｂ（ａ）に示す平面図で分かるように、図２０Ａとは配線の引き回しが異なっている。 FIG. 20B shows a state in which the same signal line is connected in the package substrate 301 in order to package two stacked chips as a unit, and a state equivalent to a double stacked chip is realized (FIG. 20A Another example). 20B (a) is a plan view and FIG. 20B (b) is a cross-sectional view. Only the chip selection signal CE can be made independent as CE1 and CE2, or the data input / output terminal I / O can be made independent and used as a double data width. Note that wiring of a printed circuit board may be used instead of connection within the package substrate 301. The difference from FIG. 20A is that the wiring in the package substrate 301 is a single layer. As can be seen from the plan view shown in FIG. 20B (a), the wiring routing is different from FIG. 20A.
　ここで、上記のようにウェハで積層した場合のパッケージ封入について説明する。図５Ａ及び図５Ｂ、図６Ａ及び図６Ｂに示すように、ウェハ積層後にパッケージ基板３０１を更に実装（積層）する方が好ましく、その後、積層チップをダイシングして個片として製品チップとするのが最も低コストであり、好ましいのは明白である。しかしながら、当然、ウェハで積層後に、図５Ａ及び図５Ｂ、図６Ａ及び図６Ｂに示すような積層体にまずダイシングしてから、図８に示すようにパッケージ封入することも、もちろん可能である。第６の実施の形態によれば、簡単に、より高密度での実装が可能になる。 Here, the package encapsulation when the wafers are stacked as described above will be described. As shown in FIGS. 5A, 5B, 6A, and 6B, it is preferable to further mount (stack) the package substrate 301 after stacking the wafers, and then dicing the stacked chip into product chips as individual pieces. Obviously, the lowest cost and preferred. However, of course, after stacking on the wafer, it is of course possible to first dice into a stack as shown in FIGS. 5A and 5B, 6A and 6B, and then enclose the package as shown in FIG. According to the sixth embodiment, it is possible to easily mount at higher density.
　〈第７の実施の形態〉
　第３及び第６の実施の形態で述べたように、ウェハとウェハを積層し、後にダイシングする場合は、積層されたメモリチップの中には不良チップが含まれているおそれがある。すると所望のメモリ容量より結果的に少なくなってしまう可能性がある。そこで、図２１に示すように、規定のメモリ容量に達するＷａ枚のウェハに加えて、Ｗｂ枚の少量の余分のウェハを積層する。そうすれば不良チップが存在しても、全メモリ容量が規定値より下回ることを回避できる。 <Seventh embodiment>
As described in the third and sixth embodiments, when wafers are stacked and then diced later, defective chips may be included in the stacked memory chips. As a result, there is a possibility that it will eventually become less than the desired memory capacity. Therefore, as shown in FIG. 21, in addition to the Wa wafers reaching the prescribed memory capacity, a small amount of Wb extra wafers are stacked. Then, even if there is a defective chip, it is possible to avoid that the total memory capacity falls below the specified value.
　第７の実施の形態によれば、積層が必要とされる最低限のメモリチップの数に加え、１層以上のメモリチップを更に積層することで、積層されたメモリチップに対して、その中に不良チップが含まれたとしても、所望の記憶容量を得ることができる。 According to the seventh embodiment, in addition to the minimum number of memory chips that are required to be stacked, one or more memory chips are further stacked, so that Even if a defective chip is included in the memory, a desired storage capacity can be obtained.
　〈第８の実施の形態〉
　前述の実施の形態では、所定のウェハにＴＳＶを形成した後、次のウェハを積層してＴＳＶを形成及び接続し、更に次のウェハを積層してＴＳＶを形成及び接続する工程を繰り返す例を示した。第８の実施の形態では、複数のウェハを積層後、積層されたウェハ状態で一気にＴＳＶを形成及び接続する例を示す。 <Eighth embodiment>
In the above-described embodiment, an example in which a TSV is formed on a predetermined wafer, a next wafer is stacked to form and connect a TSV, and a next wafer is further stacked to form and connect a TSV is repeated. Indicated. In the eighth embodiment, an example is shown in which TSVs are formed and connected all at once in a stacked wafer state after a plurality of wafers are stacked.
　図２２Ａ～図２２Ｅは、第８の実施の形態に係る方法を説明するプロセスフロー図である。まず、図２２Ａ（ａ）及び図２２Ａ（ｂ）に示すように、デバイスを有するシリコン基板５０５１上に絶縁層５０４１及びパッド電極２０４Ｐ１（Ａｌパッド等）が形成された１層目のウェハを準備する。なお、図２２Ａ（ａ）は断面図、図２２Ａ（ｂ）は平面図である。 22A to 22E are process flow diagrams for explaining a method according to the eighth embodiment. First, as shown in FIGS. 22A (a) and 22A (b), a first layer wafer in which an insulating layer 504 1 and a pad electrode 204P 1 (Al pad or the like) are formed on a silicon substrate 505 1 having a device. Prepare. 22A (a) is a cross-sectional view, and FIG. 22A (b) is a plan view.
　次に、図２２Ａ（ｃ）及び図２２Ａ（ｄ）に示すように、デバイスを有するシリコン基板５０５２上に絶縁層５０４２及びパッド電極２０４Ｐ２（Ａｌパッド等）が形成され薄化された２層目のウェハを準備し、接着層２０５１を介して、１層目のウェハ上に積層する。パッド電極２０４Ｐ２には、パッド電極２０４Ｐ２を貫通する開口部２０４Ｗ２が形成されている。なお、図２２Ａ（ｃ）は断面図、図２２Ａ（ｄ）は平面図である。 Next, as shown in FIG. 22A (c) and FIG. 22A (d), the insulating layer 5042 and the pad electrode 204P 2 on the silicon substrate 505 2 having a device (Al pads) is thinned is formed 2 prepare layers th wafer, through the adhesive layer 205 1 is stacked on the first layer of the wafer. The pad electrode 204P 2, openings 204W 2 penetrating the pad electrode 204P 2 are formed. 22A (c) is a cross-sectional view, and FIG. 22A (d) is a plan view.
　次に、図２２Ｂ（ａ）に示すように、デバイスを有するシリコン基板５０５３上に絶縁層５０４３及び開口部２０４Ｗ３を有するパッド電極２０４Ｐ３（Ａｌパッド等）が形成され薄化された３層目のウェハを準備し、接着層２０５２を介して、２層目のウェハ上に積層する。なお、開口部２０４Ｗ３の開口径は、開口部２０４Ｗ２の開口径よりも大きく形成されている。 Next, as shown in FIG. 22B (a), a pad electrode 204P 3 (Al pad or the like) having an insulating layer 504 3 and an opening 204W 3 is formed on a silicon substrate 505 3 having a device and thinned 3. prepare layers th wafer, through the adhesive layer 205 2 is stacked on the second layer of the wafer. Incidentally, the opening diameter of the opening 204W 3 is larger than the opening diameter of the opening 204W 2.
　同様に、デバイスを有するシリコン基板５０５４上に絶縁層５０４４及び開口部２０４Ｗ４を有するパッド電極２０４Ｐ４（Ａｌパッド等）が形成され薄化された４層目のウェハを準備し、接着層２０５３を介して、３層目のウェハ上に積層する。なお、開口部２０４Ｗ４の開口径は、開口部２０４Ｗ３の開口径よりも大きく形成されている。 Similarly, a thinned fourth layer wafer is prepared in which an insulating layer 504 4 and a pad electrode 204P 4 (such as an Al pad) having an opening 204W 4 are formed on a silicon substrate 505 4 having a device, and an adhesive layer is prepared. 205 3 via, laminated onto third layer of the wafer. Incidentally, the opening diameter of the opening 204W 4 is larger than the opening diameter of the opening 204W 3.
　次に、図２２Ｂ（ｂ）に示すように、絶縁層５０４４上に、パターニングされたフォトレジスト５２０を形成する。フォトレジスト５２０は、開口部２０４Ｗ４の内側の絶縁層５０４４を露出し、パッド電極２０４Ｐ４の外側の絶縁層５０４４を被覆するようにパターニングする。つまり、フォトレジスト５２０の開口部の側壁は、パッド電極２０４Ｐ４上に位置している。 Next, as shown in FIG. 22B (b), on the insulating layer 504 4, a photoresist 520 that is patterned. The photoresist 520 is exposed inside the insulating layer 504 fourth opening 204W 4, patterned so as to cover the outer insulating layer 504 4 of the pad electrode 204P 4. That is, the sidewall of the opening of the photoresist 520 is positioned on the pad electrode 204P 4.
　次に、図２２Ｃ（ａ）に示すように、フォトレジスト５２０をマスクとして、１層目のウェハのパッド電極２０４Ｐ１の表面が露出するまで各ウェハをエッチングし、その後フォトレジスト５２０を除去し、更に洗浄する。エッチングの際、各ウェハのパッド電極もマスクとして機能するため、図２２Ｃ（ａ）のような断面形状が階段状の穴２４０が形成される。 Next, as shown in FIG. 22C (a), using the photoresist 520 as a mask, each wafer is etched until the surface of the pad electrode 204P1 of the first wafer is exposed, and then the photoresist 520 is removed. Wash further. During the etching, the pad electrode of each wafer also functions as a mask, so that a step-like hole 240 as shown in FIG. 22C (a) is formed.
　次に、図２２Ｃ（ｂ）に示すように、穴２４０の側壁、４層目のウェハ上、及び穴２４０内に露出する各ウェハ上に絶縁膜２０３を成膜する。穴２４０の側壁における絶縁膜２０３の厚さは、例えば、５０～１００ｎｍ程度とすることができる。 Next, as shown in FIG. 22C (b), an insulating film 203 is formed on the sidewall of the hole 240, on the fourth layer wafer, and on each wafer exposed in the hole 240. The thickness of the insulating film 203 on the side wall of the hole 240 can be, for example, about 50 to 100 nm.
　次に、図２２Ｄ（ａ）及び図２２Ｄ（ｂ）に示すように、穴２４０の側壁以外に成膜された絶縁膜２０３を、例えばＲＩＥ（反応性イオンエッチング
；Reactive Ion Etching）により除去する。これにより、２層目のウェハの穴２４０の側壁は絶縁膜２０３２で被覆され、３層目のウェハの穴２４０の側壁は絶縁膜２０３３で被覆され、４層目のウェハの穴２４０の側壁は絶縁膜２０３４で被覆される。なお、図２２Ｄ（ａ）は断面図、図２２Ｄ（ｂ）は平面図である。 Next, as shown in FIGS. 22D (a) and 22D (b), the insulating film 203 formed on the side wall of the hole 240 is removed by, for example, RIE (Reactive Ion Etching). Thus, the sidewall of the hole 240 of the second layer of the wafer is covered with an insulating film 203 2, the side walls of the hole 240 of the third layer of the wafer is covered with an insulating film 203 3, the holes 240 of the fourth layer of the wafer sidewalls are covered with an insulating film 203 4. 22D (a) is a cross-sectional view, and FIG. 22D (b) is a plan view.
　図２２Ｄ（ｂ）に示すように、平面視では、絶縁膜２０３２、絶縁膜２０３３、及び絶縁膜２０３４が同心の円環状に配され、各絶縁膜で分離されて内側からパッド電極２０４Ｐ１、パッド電極２０４Ｐ２、パッド電極２０４Ｐ３、及びパッド電極２０４Ｐ４が配される。 As shown in FIG. 22D (b), in a plan view, the insulating film 203 2 , the insulating film 203 3 , and the insulating film 203 4 are arranged in a concentric ring shape, separated by each insulating film, and pad electrode 204P from the inside. 1 , a pad electrode 204P 2 , a pad electrode 204P 3 , and a pad electrode 204P 4 are arranged.
　図２２Ｄ（ｂ）で平面視できる部分のパッド電極２０４Ｐ１、パッド電極２０４Ｐ２、及びパッド電極２０４Ｐ３は、最終的に金属層６０１、６０２、及び６０３と接触して導通する部分となる（図２２Ｅ（ｂ）参照）。従って、導通する部分の抵抗値を均一にするために、図２２Ｄ（ｂ）で平面視できる部分のパッド電極２０４Ｐ１、パッド電極２０４Ｐ２、及びパッド電極２０４Ｐ３は、略等面積としておくことが好ましい。後述の図２２Ｅ（ｂ）において絶縁膜５０３から露出する部分のパッド電極２０４Ｐ４の面積についても同様である。 The portion of the pad electrode 204P 1 , the pad electrode 204P 2 , and the pad electrode 204P 3 that can be viewed in plan in FIG. 22D (b) finally comes into contact with the metal layers 601, 602, and 603 to become conductive (FIG. 22E (b)). Therefore, in order to make the resistance values of the conductive portions uniform, the portions of the pad electrode 204P 1 , pad electrode 204P 2 , and pad electrode 204P 3 that can be seen in a plan view in FIG. preferable. The same applies to the area of the pad electrode 204P 4 of the portion exposed from the insulating film 503 in later-described FIG. 22E (b).
　次に、図２２Ｅ（ａ）に示すように、穴２４０の側壁、４層目のウェハ上、及び穴２４０内に露出する各ウェハ上に、Ｔｉ／ＴｉＮ、Ｔａ等の金属を５０～１００ｎｍ程度スパッタ法等により成膜し、バリア層となる金属層６０１を形成する。更に、金属層６０１上に、Ｃｕ等の金属を５００ｎｍ程度スパッタ法等により成膜し、シード層となる金属層６０２を形成する。 Next, as shown in FIG. 22E (a), a metal such as Ti / TiN, Ta, etc. is about 50 to 100 nm on the side wall of the hole 240, the fourth layer wafer, and each wafer exposed in the hole 240. A metal layer 601 to be a barrier layer is formed by sputtering or the like. Further, a metal such as Cu is formed on the metal layer 601 by a sputtering method or the like with a thickness of about 500 nm to form a metal layer 602 to be a seed layer.
　次に、図２２Ｅ（ｂ）に示すように、金属層６０２をシード層とする電解めっき法等により穴２４０内にＣｕ等の金属を充填し、更に絶縁膜５０３の表面より突出する各金属層をＣＭＰ等により除去して、穴２４０内に金属層６０３を形成する。これにより、積層された各々の半導体チップを厚さ方向に貫通する、一体に形成された金属層６０３を有するＴＳＶが形成される。金属層６０３の各層を貫通する部分の太さは、上層ほど太く形成される。なお、絶縁膜５０３の上面と、金属層６０３の上面とは、平坦な面となる。 Next, as shown in FIG. 22E (b), each metal layer protruding from the surface of the insulating film 503 is filled with a metal such as Cu in the hole 240 by electrolytic plating using the metal layer 602 as a seed layer. Is removed by CMP or the like, and a metal layer 603 is formed in the hole 240. Thus, a TSV having an integrally formed metal layer 603 penetrating each stacked semiconductor chip in the thickness direction is formed. The thickness of the portion that penetrates each layer of the metal layer 603 is formed thicker as the upper layer. Note that the upper surface of the insulating film 503 and the upper surface of the metal layer 603 are flat surfaces.
　このようにして、複数のウェハを積層後、積層されたウェハ状態で一気にＴＳＶ（金属層６０３）を形成し、各ウェハのパッド電極に接続することができる。積層するウェハを更に増やしてもよい。これにより、製造工程の簡略化が可能となり、製造される半導体装置の低コスト化を実現できる。 In this way, after a plurality of wafers are laminated, TSVs (metal layers 603) can be formed at once in the laminated wafer state and connected to the pad electrodes of each wafer. The number of wafers to be stacked may be further increased. Thereby, the manufacturing process can be simplified, and the cost of the manufactured semiconductor device can be reduced.
　又、図２２Ｄ（ｂ）に示したように、上層のパッド電極の開口径を下層のパッド電極の開口径よりも大きくすることで、パッド電極とＴＳＶの金属層とが接触する部分の面積を大きくできるため、確実な接触を可能にすると共に、接触部分の抵抗値を低減できる。 Further, as shown in FIG. 22D (b), by making the opening diameter of the upper layer pad electrode larger than the opening diameter of the lower layer pad electrode, the area of the contact area between the pad electrode and the TSV metal layer can be reduced. Since it can be increased, reliable contact can be achieved and the resistance value of the contact portion can be reduced.
　図２３Ａ～図２３Ｄは、第８の実施の形態の変形例１に係る方法を説明するプロセスフロー図である。図２２Ａ～図２２Ｅに示す工程は、図２３Ａ～図２３Ｄに示す工程のようにしてもよい。図２３Ａ～図２３Ｄにおいて、図２２Ａ～図２２Ｅと異なるのは、絶縁層５０４２～５０４４が絶縁層７０４２～７０４４に置換された点である。絶縁層７０４２～７０４４は、各ウェハのパッド電極の下部のシリコン基板を貫通する部分を有している。絶縁層７０４２～７０４４のシリコン基板を貫通する部分は、各ウェハのパッド電極に形成された開口部のうち最大の開口部の径よりも大きくされている。絶縁層７０４２～７０４４のシリコン基板を貫通する部分を、各ウェハのパッド電極より大きくしてもよい。 23A to 23D are process flow diagrams for explaining a method according to the first modification of the eighth embodiment. The steps shown in FIGS. 22A to 22E may be similar to the steps shown in FIGS. 23A to 23D. 23A to 23D are different from FIGS. 22A to 22E in that the insulating layers 504 2 to 504 4 are replaced with the insulating layers 704 2 to 704 4 . The insulating layers 704 2 to 704 4 have a portion penetrating the silicon substrate below the pad electrode of each wafer. The portions of the insulating layers 704 2 to 704 4 that pass through the silicon substrate are made larger than the diameter of the largest opening among the openings formed in the pad electrode of each wafer. The portion of the insulating layers 704 2 to 704 4 that penetrates the silicon substrate may be larger than the pad electrode of each wafer.
　これにより、図２３Ｃ（ａ）に示す工程で穴２４０を形成すると、穴２４０の側壁には絶縁層７０４２～７０４４が露出するため、図２２Ｃ（ｂ）、図２２Ｄ（ａ）、及び図２２Ｄ（ｂ）の工程を省略できる。その結果、製造工程の一層の簡略化が可能となり、製造される半導体装置の一層の低コスト化を実現できる。 Accordingly, when the hole 240 is formed in the step shown in FIG. 23C (a), the insulating layers 704 2 to 704 4 are exposed on the side walls of the hole 240, so that FIG. 22C (b), FIG. 22D (a), and FIG. The process of 22D (b) can be omitted. As a result, the manufacturing process can be further simplified, and the cost of the manufactured semiconductor device can be further reduced.
　図２４は、第８の実施の形態の変形例２に係る方法を説明するプロセスフロー図である。図２３Ａ～図２３Ｄに示す工程では、各ウェハのパッド電極の開口部の壁面（側壁）は絶縁層に被覆されないため、図２４に示すように、各ウェハのパッド電極に形成する開口部の径を同一にしてもよい。図２４の場合には、各ウェハのパッド電極の開口部の壁面（側壁）と金属層６０１、６０２、及び６０３とが導通する。 FIG. 24 is a process flow diagram for explaining a method according to the second modification of the eighth embodiment. In the steps shown in FIGS. 23A to 23D, since the wall surface (side wall) of the opening portion of the pad electrode of each wafer is not covered with the insulating layer, the diameter of the opening portion formed in the pad electrode of each wafer as shown in FIG. May be the same. In the case of FIG. 24, the wall surface (side wall) of the opening of the pad electrode of each wafer is electrically connected to the metal layers 601, 602, and 603.
　又、図２５に示すように、パッド電極２０４Ｐ３に、パッド電極２０４Ｐ３を貫通し、平面視でパッド電極２０４Ｐ３を囲むように絶縁層８０４を設けてもよい。これにより、ＴＳＶを形成する工程を変えることなく、パッド電極２０４Ｐ３とＴＳＶ（金属層６０３）とを電気的に分離できる。 Further, as shown in FIG. 25, the pad electrode 204P 3, through the pad electrode 204P 3, it may be an insulating layer 804 so as to surround the pad electrode 204P 3 provided in a plan view. Thus, without changing the process for forming a TSV, it can electrically isolate the pad electrode 204P 3 and TSV (metal layer 603).
　図２５では、一例としてパッド電極２０４Ｐ３に絶縁層８０４を設ける例を示したが、任意のパッド電極に、任意のパッド電極を貫通し、平面視で任意のパッド電極を囲むように絶縁層を設けることができる。 In Figure 25, the example of providing the insulating layer 804 on the pad electrode 204P 3 as an example, to any of the pad electrode, through any of the pad electrode, an insulating layer so as to surround any of the pad electrode in plan view Can be provided.
　この手法を用いると、信号線を、積層した任意のウェハに配線することができる。例えば、同じ信号を、３層目のウェハを素通りして４層目のウェハや２層目のウェハに供給したり、独立配線を各層のウェハに供給したりできる。 When this method is used, the signal line can be wired to any laminated wafer. For example, the same signal can be supplied to the fourth layer wafer and the second layer wafer through the third layer wafer, or an independent wiring can be supplied to each layer wafer.
　以上、好ましい実施の形態について詳説したが、本発明は、上述した実施の形態に制限されることはなく、本発明の範囲を逸脱することなく、上述した実施の形態に種々の変形及び置換を加えることができる。 Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the present invention. Can be added.
　例えば、各実施の形態においては、ＮＡＮＤフラッシュメモリについて説明しているが、本発明はこれに限らず、例えば、ＮＯＲ型フラッシュメモリやＤＲＡＭ等の半導体メモリについても広く適用できる。又、半導体メモリ以外では、並列動作をさせる論理回路デバイスを積層した３次元デバイス、ＣＭＯＳイメージセンサ、パワートランジスタ、高周波デバイス等に適用できる。又、工程説明等でシリコン基板、ＳＯＧやＣｕ等の材料を挙げたり、ＴＳＶの構造について説明したりしたが、実際の材料や構造の詳細についてはこれに限られるものでないことは明白である。例えば、シリコン基板に代えて、ＳＯＩ基板（Silicon on Insulator）等を用いてもよい。 For example, in each embodiment, the NAND flash memory has been described. However, the present invention is not limited to this, and the present invention can be widely applied to, for example, a NOR type flash memory and a semiconductor memory such as a DRAM. In addition to semiconductor memories, the present invention can be applied to a three-dimensional device, a CMOS image sensor, a power transistor, a high frequency device, and the like in which logic circuit devices that perform parallel operations are stacked. In addition, although materials such as silicon substrate, SOG and Cu were mentioned in the process description and the like, and the structure of the TSV was explained, it is obvious that details of actual materials and structures are not limited to this. For example, instead of a silicon substrate, an SOI substrate (Silicon-on-insulator) or the like may be used.
　１００Ａ、１００Ｂ　半導体装置
　１０１、１０１ａ、１０１ｂ　ＮＡＮＤフラッシュメモリチップ（メモリチップ）
　１０２　ＮＡＮＤコントローラチップ（コントローラチップ）
　１１０　ボンディングワイヤ
　２０１　ＴＳＶ
　２０２、５０６、６０１、６０２、６０３　金属層
　２０３、２０３２～２０３４、５０２　絶縁膜
　２０４、２０４ｃ、２０４Ｐ、２０４Ｐ１～２０４Ｐ４　パッド電極
　２０４Ｗ　パッド電極開口部
　２０４Ｗ２～２０４Ｗ４　開口部
　２０５、２０５１～２０５３、２１２　接着層
　２４０　穴
　３０１　パッケージ基板
　３０２　外部接続端子
　３０３、３０３ａ、３０３ｂ　接続配線
　３３１　チップアドレス信号
　３３３　電位比較回路
　３３４　チップ選択回路
　３４２　パワーオン検知回路
　３４３　ディレイ回路
　３４４　初期設定動作回路
　３５１　インバータ
　３５２　スイッチ回路
　３５３　ディレイ素子
　３５４、４２２　バッファ回路
　４０１　配線
　４１１　パッド
　４２１　プルアップ用トランジスタ
　４２４　入力回路
　５００　ウェハ
　５０３、５０４、５０４１～５０４４、５２３、７０４２～７０４４、８０４　絶縁層
　５０５、５０５１～５０５４　シリコン基板
　５１０、５２０　フォトレジスト 100A, 100B Semiconductor device 101, 101a, 101b NAND flash memory chip (memory chip)
102 NAND controller chip (controller chip)
110 Bonding wire 201 TSV
202, 506, 601, 602, 603 Metal layer 203, 203 2 to 203 4 , 502 Insulating film 204, 204c, 204P, 204P 1 to 204P 4 Pad electrode 204W Pad electrode opening 204W 2 to 204W 4 Opening 205, 205 1 to 205 3 , 212 Adhesive layer 240 hole 301 Package substrate 302 External connection terminals 303, 303 a, 303 b Connection wiring 331 Chip address signal 333 Potential comparison circuit 334 Chip selection circuit 342 Power-on detection circuit 343 Delay circuit 344 Initial setting operation circuit 351 Inverter 352 Switch circuit 353 Delay element 354, 422 Buffer circuit 401 Wiring 411 Pad 421 Pull-up transistor 424 Input circuit 500 Wafer 503, 504, 504 1 to 504 4 , 523, 704 2 to 704 4 , 804 Insulating layer 505, 505 1 to 505 4 Silicon substrate 510, 520 Photoresist

Claims (30)

  1. 　複数の半導体チップが積層された積層体と、
    　前記積層体の最下層の半導体チップ上に積層された各々の半導体チップを厚さ方向に貫通して前記最下層の半導体チップのパッド電極と接続された貫通電極と、を有し、
    　前記積層体の電源線及び信号線の少なくとも一方は、前記貫通電極を介して、前記積層体を構成する半導体チップに共通に接続されている半導体装置。     A laminate in which a plurality of semiconductor chips are laminated;
    A through electrode connected to the pad electrode of the lowermost semiconductor chip through each semiconductor chip stacked on the lowermost semiconductor chip of the stacked body in the thickness direction;
    A semiconductor device in which at least one of a power supply line and a signal line of the multilayer body is commonly connected to a semiconductor chip constituting the multilayer body via the through electrode.
  2. 　前記貫通電極は、各々の前記半導体チップのパッド電極の部分に形成されている請求項１記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the through electrode is formed in a pad electrode portion of each semiconductor chip.
  3. 　上下に隣接する前記半導体チップの貫通電極同士が直接接続されている請求項１記載の半導体装置。 The semiconductor device according to claim 1, wherein the through electrodes of the semiconductor chips adjacent in the vertical direction are directly connected to each other.
  4. 　前記貫通電極は、積層された各々の半導体チップを厚さ方向に貫通する、一体に形成された金属層を有する請求項１記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the through electrode has an integrally formed metal layer that penetrates each stacked semiconductor chip in the thickness direction.
  5. 　前記貫通電極の各層を貫通する部分の太さは、上層ほど太く形成されている請求項４記載の半導体装置。 5. The semiconductor device according to claim 4, wherein a thickness of a portion that penetrates each layer of the through electrode is formed thicker as an upper layer.
  6. 　上下に隣接する前記半導体チップの貫通電極同士がバンプ電極を介して接続されている請求項１記載の半導体装置。 The semiconductor device according to claim 1, wherein through electrodes of the semiconductor chips adjacent in the vertical direction are connected to each other through a bump electrode.
  7. 　各々の前記半導体チップは、
    　各々の前記半導体チップが前記積層体の何層目に積層されているかを示すチップアドレスと、
    　前記チップアドレスと前記貫通電極を介して入力される信号とが一致するか否かを判別する電位比較回路と、を備えている請求項１記載の半導体装置。     Each of the semiconductor chips is
    A chip address indicating which layer of each of the semiconductor chips is stacked; and
    The semiconductor device according to claim 1, further comprising: a potential comparison circuit that determines whether or not the chip address and a signal input through the through electrode match.
  8. 　各々の前記半導体チップは、電源電圧のパワーオン検知回路と初期設定動作回路の間に複数のディレイ回路を有し、
    　前記チップアドレスは、前記ディレイ回路を制御して、前記チップアドレスに対応したディレイを持つことにより、パワーオン検知から初期設定動作までに所定の遅延時間を設定する請求項７記載の半導体装置。     Each of the semiconductor chips has a plurality of delay circuits between a power-on detection circuit for a power supply voltage and an initial setting operation circuit,
    8. The semiconductor device according to claim 7, wherein the chip address has a delay corresponding to the chip address by controlling the delay circuit to set a predetermined delay time from power-on detection to an initial setting operation.
  9. 　各々の前記半導体チップは、前記チップアドレスを設定するためのヒューズ素子を有する請求項７記載の半導体装置。 8. The semiconductor device according to claim 7, wherein each of the semiconductor chips has a fuse element for setting the chip address.
  10. 　前記積層体を構成する半導体チップとは種類の異なる半導体チップが、前記積層体と同一のパッケージに封入され、
    　前記積層体を構成する半導体チップの少なくとも一部の信号線が、前記種類の異なる半導体チップの信号線に接続されている請求項１記載の半導体装置。     A semiconductor chip of a type different from the semiconductor chip constituting the laminate is enclosed in the same package as the laminate,
    The semiconductor device according to claim 1, wherein at least a part of signal lines of the semiconductor chips constituting the stacked body are connected to signal lines of the different types of semiconductor chips.
  11. 　各々の前記半導体チップはウェハ単位で積層され、
    　前記貫通電極は、ウェハ単位で形成及び接続されている請求項１記載の半導体装置。     Each of the semiconductor chips is stacked on a wafer basis,
    The semiconductor device according to claim 1, wherein the through electrode is formed and connected in units of wafers.
  12. 　前記積層体は、ウェハ単位で積層され、ウェハ単位で前記貫通電極が形成及び接続された後に個片化され、個片化後にパッケージ封入されたものである請求項１１記載の半導体装置。 12. The semiconductor device according to claim 11, wherein the stacked body is stacked in units of wafers, separated into individual pieces after the through electrodes are formed and connected in units of wafers, and packaged after being separated into individual pieces.
  13. 　前記積層体は、ウェハ単位で積層され、ウェハ単位で前記貫通電極が形成及び接続され、ウェハ単位でパッケージ封入された後に個片化されたものである請求項１１記載の半導体装置。 The semiconductor device according to claim 11, wherein the stacked body is stacked in units of wafers, the through electrodes are formed and connected in units of wafers, and packaged in units of wafers and then separated into individual pieces.
  14. 　前記貫通電極は、各々の前記半導体チップの前記パッド電極を貫通して形成され、各々の前記半導体チップの前記パッド電極と内部配線との間には切断可能なヒューズが設けられている請求項１１記載の半導体装置。 12. The through electrode is formed so as to penetrate the pad electrode of each of the semiconductor chips, and a severable fuse is provided between the pad electrode of each of the semiconductor chips and an internal wiring. The semiconductor device described.
  15. 　前記貫通電極は、各々の前記半導体チップの前記パッド電極を貫通して形成され、選択されたパッド電極と前記選択されたパッド電極を貫通する貫通電極との間には絶縁構造が設けられている請求項１１記載の半導体装置。 The through electrode is formed through the pad electrode of each of the semiconductor chips, and an insulating structure is provided between the selected pad electrode and the through electrode that passes through the selected pad electrode. The semiconductor device according to claim 11.
  16. 　前記絶縁構造は、前記選択されたパッド電極にインクジェット印刷により塗布された絶縁物質からなる請求項１５記載の半導体装置。 The semiconductor device according to claim 15, wherein the insulating structure is made of an insulating material applied to the selected pad electrode by ink jet printing.
  17. 　ウェハを積層する前に、前記ウェハ内の各々の前記半導体チップについて良品・不良品の電気的測定及び判定を行い、
    　不良品と判定された半導体チップのパッド電極と前記不良品と判定された半導体チップのパッド電極を貫通する貫通電極、又は、不良品と判定された半導体チップのパッド電極と前記不良品と判定された半導体チップのパッド電極に繋がる内部配線を電気的に絶縁する絶縁構造を有する請求項１１記載の半導体装置。     Before laminating wafers, perform electrical measurement and determination of non-defective / defective products for each of the semiconductor chips in the wafer,
    The pad electrode of the semiconductor chip determined to be defective and the through electrode that penetrates the pad electrode of the semiconductor chip determined to be defective or the pad electrode of the semiconductor chip determined to be defective and the defective 12. The semiconductor device according to claim 11, wherein the semiconductor device has an insulating structure that electrically insulates internal wiring connected to the pad electrode of the semiconductor chip.
  18. 　各々の前記半導体チップは、各々の前記半導体チップが前記積層体の何層目に積層されているかを示すチップアドレスを備え、
    　各々の前記半導体チップは、第１の電圧に接続された貫通電極が貫通する第１パッド電極と、第２の電圧に接続された貫通電極が貫通する第２パッド電極と、を有し、
    　パッド電極と貫通電極とを電気的に絶縁する構造を、前記第１パッド電極又は前記第２パッド電極に選択的に適用することにより前記チップアドレスを構成する請求項１１記載の半導体装置。     Each of the semiconductor chips includes a chip address indicating which layer of the stacked body each semiconductor chip is stacked,
    Each of the semiconductor chips has a first pad electrode through which the through electrode connected to the first voltage passes, and a second pad electrode through which the through electrode connected to the second voltage passes,
    The semiconductor device according to claim 11, wherein the chip address is configured by selectively applying a structure for electrically insulating a pad electrode and a through electrode to the first pad electrode or the second pad electrode.
  19. 　各々の前記半導体チップは、各々の前記半導体チップが前記積層体の何層目に積層されているかを示すチップアドレスを備え、
    　各々の前記半導体チップは、第１の電圧に接続された貫通電極が貫通する第１領域と、第２の電圧に接続された貫通電極が貫通する第２領域と、を備えたパッド電極を有し、
    　パッド電極と貫通電極とを電気的に絶縁する構造を、前記第１領域を貫通する貫通電極又は前記第２領域を貫通する貫通電極に選択的に適用することにより前記チップアドレスを構成する請求項１１記載の半導体装置。     Each of the semiconductor chips includes a chip address indicating which layer of the stacked body each semiconductor chip is stacked,
    Each of the semiconductor chips has a pad electrode including a first region through which the through electrode connected to the first voltage passes and a second region through which the through electrode connected to the second voltage passes. And
    The chip address is configured by selectively applying a structure that electrically insulates a pad electrode and a through electrode to a through electrode that penetrates the first region or a through electrode that penetrates the second region. 11. The semiconductor device according to 11.
  20. 　各々の前記半導体チップは、各々の前記半導体チップが前記積層体の何層目に積層されているかを示すチップアドレスを備え、
    　各々の前記半導体チップは、前記チップアドレスを設定するためのパッド電極、入力部のプルアップ回路又はプルダウン回路、及び前記チップアドレスを設定するためのパッド電極を貫通し所定の電圧に接続される貫通電極を有し、
    　パッド電極と貫通電極とを電気的に絶縁する構造を、前記チップアドレスを設定するためのパッド電極に選択的に適用することにより前記チップアドレスを構成する請求項１１記載の半導体装置。     Each of the semiconductor chips includes a chip address indicating which layer of the stacked body each semiconductor chip is stacked,
    Each of the semiconductor chips penetrates through a pad electrode for setting the chip address, a pull-up circuit or a pull-down circuit of an input unit, and a pad electrode for setting the chip address and connected to a predetermined voltage. Having electrodes,
    12. The semiconductor device according to claim 11, wherein the chip address is configured by selectively applying a structure for electrically insulating the pad electrode and the through electrode to the pad electrode for setting the chip address.
  21. 　各々の前記半導体チップは、少なくとも２つの領域に分けられたパッド電極を有し、前記領域は各々絶縁された貫通電極を有し、
    　そのうちの１個の貫通電極のみが選択的に前記少なくとも２つの領域に分けられたパッド電極に接続され、
    　各々絶縁された貫通電極は各々別の外部信号線に接続された請求項１１記載の半導体装置。     Each of the semiconductor chips has a pad electrode divided into at least two regions, and each of the regions has an insulated through electrode,
    Only one of the through electrodes is selectively connected to the pad electrode divided into the at least two regions,
    12. The semiconductor device according to claim 11, wherein each insulated through electrode is connected to a different external signal line.
  22. 　前記少なくとも２つの領域に分けられたパッド電極はチップ選択信号の入力パッドであり、前記外部信号線は少なくとも２つのチップ選択信号線である請求項２１記載の半導体装置。 The semiconductor device according to claim 21, wherein the pad electrode divided into the at least two regions is an input pad for a chip selection signal, and the external signal line is at least two chip selection signal lines.
  23. 　前記積層体を複数個有する請求項１記載の半導体装置。 The semiconductor device according to claim 1, comprising a plurality of the stacked bodies.
  24. 　積層が必要とされる最低限の半導体チップの数に加え、１層以上の半導体チップを更に積層する請求項１記載の半導体装置。 The semiconductor device according to claim 1, wherein one or more semiconductor chips are further stacked in addition to the minimum number of semiconductor chips required to be stacked.
  25. 　複数の半導体チップが積層された積層体と、前記積層体の最下層の半導体チップ上に積層された各々の半導体チップを厚さ方向に貫通して前記最下層の半導体チップのパッド電極と接続された貫通電極と、を有し、前記積層体の電源線及び信号線の少なくとも一方は、前記貫通電極を介して、前記積層体を構成する半導体チップに共通に接続されている半導体装置の製造方法であって、
    　半導体基板上に複数のパッド電極及び複数の前記パッド電極を被覆する絶縁層が形成された最下層のウェハに、前記絶縁層を貫通して各々の前記パッド電極の表面を露出する貫通穴を形成する工程と、
    　前記最下層のウェハにおいて、前記貫通穴内に金属層を形成する工程と、
    　前記最下層のウェハの複数の前記パッド電極に対応する位置に、複数のパッド電極が形成された半導体基板上に、複数の前記パッド電極を被覆する絶縁層が形成された２層目のウェハを、前記最下層のウェハ上に積層する工程と、
    　前記２層目のウェハにおいて、前記絶縁層を貫通して各々の前記パッド電極の表面を露出する第１貫通穴を形成する工程と、
    　前記２層目のウェハにおいて、各々の前記第１貫通穴内に、前記２層目のウェハを厚さ方向に貫通し、前記最下層のウェハに形成された前記金属層の表面を露出する第２貫通穴を形成する工程と、
    　前記２層目のウェハにおいて、前記第１貫通穴の側壁及び前記第２貫通穴の側壁に第２絶縁膜を形成する工程と、
    　前記２層目のウェハにおいて、前記第１貫通穴内及び前記第２貫通穴内に、前記最下層のウェハに形成された前記金属層と電気的に接続され、前記貫通電極の一部をなす第２金属層を形成する工程と、を有し、
    　更に、前記最下層のウェハにおいて、選択された貫通穴の側壁及び前記選択された貫通穴内に露出する前記パッド電極の表面に絶縁膜を形成する工程と、
    　前記２層目のウェハにおいて、選択された第１貫通穴の側壁及び前記選択された第１貫通穴内に露出する前記パッド電極の表面に絶縁膜を形成する工程と、を備え、
    　前記貫通電極は、前記選択された貫通穴内のパッド電極及び前記選択された第１貫通穴内のパッド電極とは電気的に接続されず、選択されていない貫通穴内のパッド電極及び前記選択されていない第１貫通穴内のパッド電極とは電気的に接続され、
    　３層目以降のウェハを前記２層目のウェハと同等の工程で順次積層することを特徴とする半導体装置の製造方法。     A stacked body in which a plurality of semiconductor chips are stacked, and each semiconductor chip stacked on the lowermost semiconductor chip of the stacked body is connected to the pad electrode of the lowermost semiconductor chip through the thickness direction. A method of manufacturing a semiconductor device, wherein at least one of a power supply line and a signal line of the multilayer body is commonly connected to a semiconductor chip constituting the multilayer body via the through electrode. Because
    A through-hole that penetrates the insulating layer and exposes the surface of each pad electrode is formed in a lowermost wafer in which a plurality of pad electrodes and an insulating layer covering the plurality of pad electrodes are formed on a semiconductor substrate. And a process of
    Forming a metal layer in the through hole in the lowermost wafer;
    A second wafer in which an insulating layer that covers the plurality of pad electrodes is formed on a semiconductor substrate on which the plurality of pad electrodes are formed at positions corresponding to the plurality of pad electrodes of the lowermost wafer. Laminating on the lowermost wafer;
    Forming a first through hole in the second wafer to expose the surface of each pad electrode through the insulating layer;
    In the second layer wafer, a second layer that penetrates the second layer wafer in the thickness direction in each of the first through holes and exposes the surface of the metal layer formed on the lowermost wafer. Forming a through hole;
    Forming a second insulating film on the side wall of the first through hole and the side wall of the second through hole in the second layer wafer;
    In the second-layer wafer, a second electrode that is electrically connected to the metal layer formed on the lowermost wafer in the first through hole and the second through hole and forms a part of the through electrode. Forming a metal layer, and
    A step of forming an insulating film on a side wall of the selected through hole and a surface of the pad electrode exposed in the selected through hole in the lowermost wafer;
    Forming an insulating film on a side wall of the selected first through hole and a surface of the pad electrode exposed in the selected first through hole in the second-layer wafer; and
    The through electrode is not electrically connected to the pad electrode in the selected through hole and the pad electrode in the selected first through hole, and the pad electrode in the unselected through hole and the unselected The pad electrode in the first through hole is electrically connected,
    3. A method of manufacturing a semiconductor device, comprising sequentially stacking third and subsequent wafers in a process equivalent to that of the second wafer.
  26. 　前記最下層のウェハにおいて絶縁膜を形成する工程は、前記２層目のウェハを前記最下層のウェハ上に積層する工程の前に行い、
    　前記２層目のウェハにおいて絶縁膜を形成する工程は、前記第２貫通穴を形成する工程の前に行う請求項２５記載の半導体装置の製造方法。     The step of forming an insulating film in the lowermost wafer is performed before the step of laminating the second wafer on the lowermost wafer,
    26. The method of manufacturing a semiconductor device according to claim 25, wherein the step of forming an insulating film in the second layer wafer is performed before the step of forming the second through hole.
  27. 　前記選択された貫通穴の側壁及び前記選択された貫通穴内に露出する前記パッド電極の表面に形成する絶縁膜、並びに、前記選択された第１貫通穴の側壁及び前記選択された第１貫通穴内に露出する前記パッド電極の表面に形成する絶縁膜は、インクジェット印刷によって形成する請求項２５記載の半導体装置の製造方法。 The insulating film formed on the side wall of the selected through hole and the surface of the pad electrode exposed in the selected through hole, and the side wall of the selected first through hole and the inside of the selected first through hole 26. The method of manufacturing a semiconductor device according to claim 25, wherein the insulating film formed on the surface of the pad electrode exposed to is formed by ink jet printing.
  28. 　前記貫通電極と電気的に接続されない前記選択された貫通穴内のパッド電極、及び、前記貫通電極と電気的に接続されない前記選択された第１貫通穴内のパッド電極は、電気的測定で不良品と判定された半導体チップのパッド電極である請求項２５記載の半導体装置の製造方法。 The pad electrode in the selected through hole that is not electrically connected to the through electrode, and the pad electrode in the selected first through hole that is not electrically connected to the through electrode are defective in electrical measurement. 26. The method of manufacturing a semiconductor device according to claim 25, wherein the pad electrode of the determined semiconductor chip is used.
  29. 　前記貫通電極と電気的に接続されない前記選択された貫通穴内のパッド電極、及び、前記貫通電極と電気的に接続されない前記選択された第１貫通穴内のパッド電極は、各々の半導体チップが前記積層体の何層目に積層されているかを示すチップアドレスを構成するために、第１の電圧に接続される貫通電極が貫通する第１パッド電極と、第２の電圧に接続された貫通電極が貫通する第２パッド電極のうち、選択された何れか一方である請求項２５記載の半導体装置の製造方法。 The pad electrode in the selected through hole that is not electrically connected to the through electrode and the pad electrode in the selected first through hole that is not electrically connected to the through electrode are each stacked in the semiconductor chip. A first pad electrode through which a through electrode connected to a first voltage passes and a through electrode connected to a second voltage are provided to form a chip address indicating what layer of the body is stacked. 26. The method of manufacturing a semiconductor device according to claim 25, wherein one of the penetrating second pad electrodes is selected.
  30. 　複数の貫通電極が１つのパッド電極に貫通して設けられており、
    　前記１つのパッド電極に設けられた各々の貫通電極は、前記１つのパッド電極上に形成された絶縁層で分離されており、
    　各々の貫通電極を分離する前記絶縁層は、ウェハの積層前又は積層直後に形成する請求項２５記載の半導体装置の製造方法。     A plurality of through electrodes are provided so as to penetrate through one pad electrode,
    Each through electrode provided in the one pad electrode is separated by an insulating layer formed on the one pad electrode,
    26. The method of manufacturing a semiconductor device according to claim 25, wherein the insulating layer for separating each through electrode is formed before or just after the wafers are stacked.
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