WO2015078657A1 - Reverse-conducting power semiconductor device - Google Patents

Reverse-conducting power semiconductor device Download PDF

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Publication number
WO2015078657A1
WO2015078657A1 PCT/EP2014/073367 EP2014073367W WO2015078657A1 WO 2015078657 A1 WO2015078657 A1 WO 2015078657A1 EP 2014073367 W EP2014073367 W EP 2014073367W WO 2015078657 A1 WO2015078657 A1 WO 2015078657A1
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WO
WIPO (PCT)
Prior art keywords
layer
cathode
main side
gate
diode
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PCT/EP2014/073367
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French (fr)
Inventor
Martin Arnold
Umamaheswara Vemulapati
Munaf Rahimo
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Abb Technology Ag
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Publication of WO2015078657A1 publication Critical patent/WO2015078657A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/744—Gate-turn-off devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/7404—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device
    • H01L29/7412—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device the device being a diode
    • H01L29/7416—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device the device being a diode the device being an antiparallel diode, e.g. RCT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41716—Cathode or anode electrodes for thyristors

Definitions

  • the invention relates to the field of power electronics.
  • it relates to a semiconductor device according to the preamble of claim 1.
  • a bi-mode gate commutated thyristor combines one or more gate commutated thyristors (GCTs) and one or more diodes within a single power semiconductor device.
  • the BGCT is built around a semiconductor slab, in particular a semiconductor wafer, which comprises a plurality of gate commutated thyristor (GCT) regions electrically connected in parallel to one another, and a plurality of diode regions, also electrically connected in parallel to one another and to the gate turn-off thyristor regions, albeit with opposing forward direction.
  • GCT gate commutated thyristor
  • the BGCT is a major building block for BGCT modules, in which a capability of operating the BGCT in an integrated gate commutated thyristor (IGCT) mode is obtained by integrating the semiconductor slab with a gate circuit on a printed circuit board.
  • IGCT integrated gate commutated thyristor
  • the diode regions provided in the semiconductor slab allow for operating the BGCT in a diode mode; thus providing for reverse conductivity of the BGCT, which is required for a plurality of applications in power electronics.
  • FIG 1 shows in a sectional view of the prior art BGCT from WO 2012/041958 A2.
  • the prior art BGCT 1 ' comprises a semiconductor slab having a first main side 1 1 and a second main side 15, said second main side 15 being arranged parallel to the first main side 1 1 ; and an (n-)- doped bulk layer 3 located between - and extending in a di- rection parallel to - the first main side 1 1 and the second main side 15.
  • the BGCT 1 ' further comprises a plurality of gate commutated thyristor cells 91 , each gate commu- tated thyristor cell 91 comprising a GCT region in the semiconductor slab, said GCT region comprising layers in the following order between the first main side 1 1 and the second main side 15: an n-doped first cathode layer 4, a p-doped base layer 6, a thy- ristor drift layer 3' formed by the bulk layer 3, an n-doped buffer layer 8, a first (p+)- doped anode layer 5.
  • the gate commutated thyristor cell 91 further comprises a cathode electrode 2 arranged on the first main side on each first cathode layer 4, a first main electrode 25 arranged on the second main side on each first anode layer 5, a plurality of gate electrodes 7 arranged on each base layer 6 lateral to the first cathode layer 4 and separated from it by the base layer 6.
  • the BGCT 1 ' further comprises a plurality of diode cells 96, each diode cell comprising a diode region in the semiconductor slab, said diode region comprising layers in the following order in the semiconductor slab between the first and second main side: a p-doped second anode layer, a diode drift layer 3" formed by the bulk layer 3, and an n-doped second cathode layer 45, which is arranged alternating to the first anode layer 5 adjacent to the second main side 15.
  • BGCT V comprises a second anode electrode 28 arranged on the each first main side on the second anode layer 55.
  • the diode regions are separated from the GCT regions by uniform separation regions 350, which are formed by parts of the bulk layer 3 located between the diode regions and GCT regions and where the bulk layer 3 extends to the first main side 1 1.
  • WO 2012/041958 A2 suggests to at least par- tially utilize the same semiconductor volume in both GCT and diode modes.
  • the basic concept is based on enabling the GCT mode operation to utilize the diode regions during conduction due to the charge spreading, i.e. spreading of an electron-hole plasma which forms in the semiconductor slab when conduction occurs, into those regions.
  • the diode mode operation is also able to utilize the GCT regions. Tilted arrows in Fig.
  • GCT cells 96 and GCT cells 91 indicate an expected plasma spread in GCT mode of operation, which will be inverted for the diode mode.
  • a ratio of GCT cells to diode cells will determine the effective area utilized in both modes of operation.
  • Dimensioning of GCT cells and of the uniform separation regions 350 between the diode cells 96 and GCT cells 91 is also an important factor for area utilization.
  • the uniform separation regions 350 must be designed suffi- ciently broad to provide a sufficient blocking capability for a gate voltage required to drive the GCT, i.e. a gate to cathode blocking capability of -20 to -30 V must be ensured during GCT turn-off and blocking.
  • uniform separation region dimensions should be kept to a minimum for maximum total area utilization, as well as for maximum plasma spreading from the GCT regions to the diode regions in GCT mode of operation and vice versa.
  • Fig. 2 shows a top view of the prior art device shown in Fig. 1.
  • the device comprises at least one mixed part 99 in which diode cells 96 alternate with one or more GCT cells 91.
  • the bulk layer 3 is usually very low (n-)-doped, i.e. a net density of donors ⁇ /net in the bulk layer is in a range between
  • Fig. 3 illustrates simulation results of gate-cathode blocking characteristics for different widths of the uniform separation region. Leakage current for a single GCT-diode pair is plotted as a function of gate voltage. While only weak significant parasitic pnp-transistor behavior may be observed for a width of 75 ⁇ , an over-exponential increase in leakage current occurs between 0 and -25V for a width of 30 ⁇ .
  • the leakage current is unaccepta- bly high, given that a total leakage current for the BGCT corresponds to the current shown in Fig. 3 multiplied with the number of GCT-diode pairs in the device, which can amount from several hundred to several thousand; and that the gate voltage generally needs to be applied not only during turn-off, but also while the GCTs are in blocking mode to ensure a stable operation of the BGCT.
  • the gate circuit has to be properly designed to withstand such currents.
  • Electronic components, in particular MOSFETs, constituting the gate circuit thus have to meet demanding specifications, leading to an inacceptable increase in price and dimensions of BGCT modules produced from BGCTs with such high leakage currents.
  • a semiconductor device comprising a semiconductor slab, in particular a semiconductor wafer or semiconductor die, the semiconductor slab having a first main side and a second main side, said second main side being parallel to the first main side; and a bulk layer of a first conductivity type located between the first main side and the second main side, the semiconductor device comprising a gate com- mutated thyristor cell, said gate commutated thyristor cell comprising layers in the following order in the semiconductor slab between the first and second main side: a first cathode layer of the first conductivity type, a base layer of a second conductivity type different from the first conductivity type, the bulk layer, a buffer layer of the first conductivity type, a first anode layer of the second conductivity type; the gate commutated thy- ristor cell further comprising: a GCT cathode electrode arranged on the first main side on the first cathode layer, a gate electrode arranged on the base layer; the semiconductor device further comprising
  • a gate-cathode blocking region of the first conductivity type is arranged between second anode layer and base layer and adjacent to the first main side, the gate-cathode blocking region having a higher net doping concentration than the bulk layer.
  • the second anode layer and the base layer are separated from each other by the bulk layer and the gate-cathode blocking region, which is embedded in the drift layer.
  • the gate-cathode blocking region is not connected to any layer of the second conductivity type. This ensures a reliable blocking at low leakage currents.
  • it is easier to manufacture an n barrier in a lowly doped drift layer than in a highly p doped layer and the width and doping concentration of the separation region can be adjusted and optimized independently from each other.
  • the bulk layer preferably extends in a direction at least essentially parallel to the first main side and the second main side; the gate electrode is preferably arranged lateral to the first cathode layer at a distance from the latter and separated from the first cathode layer by the base layer; and/or the second cathode layer is ar- ranged alternating to the first anode layer.
  • the bulk layer constitutes a thyristor drift layer in a GCT region of the semiconductor slab comprised by the GCT cell; and a diode drift layer in a diode region of the semiconductor slab comprised by the diode cell.
  • the first main electrode arranged on the second main side is preferably arranged adjacent to, in particular contiguous to, both the first anode layer and the second cathode layer.
  • the device comprises at least one mixed part, in which diode cells (i.e. the second anode layers of the diode cells) alternate with one or more GCT cells (i.e. the first cathode layers (and gate electrode 7 and base layer 6) of the GCT cells).
  • diode cells i.e. the second anode layers of the diode cells
  • GCT cells i.e. the first cathode layers (and gate electrode 7 and base layer 6) of the GCT cells.
  • FIG. 1 shows a sectional view of a BGCT according to the prior art
  • FIG. 2 shows a top view of the prior art BGCT shown in Fig 1 ;
  • FIG. 3 shows simulation results for gate-cathode blocking characteristics of prior art BGCTs for different widths of the uniform separation region
  • FIG. 4 shows a sectional view of a semiconductor device in accordance with the present invention
  • FIG. 5 shows a comparison of gate-cathode blocking characteristics obtained by means of numeric simulation
  • FIG. 6 shows a sectional view of a preferred embodiment of a semiconductor device in accordance with the present invention.
  • FIG. 6 shows a sectional view of another preferred embodiment of a semiconductor device in accordance with the present invention.
  • FIG. 8 shows a top view of yet another preferred embodiment of a semiconductor device in accordance with the present invention
  • FIG. 4 shows a sectional view of bi-mode gate commutated thyristor (BGCT) representing a semiconductor device in accordance with the present invention.
  • BGCT 1 comprises a semiconductor slab in form of a silicon wafer 10, the semiconductor slab having a first main side 1 1 and a second main side 15, said second main side 15 being arranged parallel to the first main side 1 1 ; and a bulk layer 3 located between - and ex- tending in a direction at least essentially parallel to - the first main side 1 1 and the second main side 15.
  • the bulk layer exemplarily has a constant low doping concentration
  • the buffer layer 8 has a higher doping concentration than the bulk layer
  • the buffer layer has a doping concentration decreasing from a maximum doping concentration at or close to the interface the anode layer 3 to a lower doping concentration at the interface to the bulk layer 3.
  • the buffer layer could also have a constant high doping concentration.
  • Each diode cell 96 further comprises a diode anode electrode 28 arranged on the first main side on the second anode layer 55.
  • Cathode electrode 2 and anode electrode 28 are shorted by means of an electrically conductive connection not shown in Fig. 4.
  • each individual GCT cell 91 is preferably arranged lateral to the first cathode layer 4 and separated from it by the base layer 6 of said individual GCT cell 91 .
  • the buffer layer 8 has a net doping concentration of at most 10 16 cm -3 .
  • the first main sided layers of each individual GCT cell i.e. first cathode layer 4, base layer 6 together with gate electrode 7) may be aligned to the second main sided layers of said individual GCT cell (i.e. first anode layer 5).
  • first anode layer 5 which is arranged closest to the first main sided layers shall be regarded as belonging to the same GCT cell 91 . Therefore, in case of non-alignment the device may be designed in such a way that more than one second sided layer may be allocated to a cell or in which one second sided layer is allocated to two cells.
  • the (n+)-doped second cathode layer 45 of the diode cells are arranged alternating to the first anode layer 5 adjacent to the second main side 15.
  • the second anode layer 55 is contacted by the second anode electrode 28.
  • the first main sided layers of each individual diode cell i.e. second anode layer 55
  • second cathode layer 45 which is arranged closest to the first main sided layers shall belong to the same individual diode cell 96. Therefore, in case of non-alignment the device may be designed in such a way that more than one second sided layer may be allocated to an individual cell or in which one second sided layer is allocated to two individual cells.
  • the first anode layers 5 of the GCT cells 91 and second cathode layers 45 of the diode cells 96 are shorted by first main electrode 25. Due to these shorts, the BGCT shows a soft performance, i.e. a snappy reverse recovery behavior is alleviated.
  • an n-doped gate-cathode blocking region 351 is arranged between second anode layers 55 and base layers 6 of neighboring GCT cells 91 and diode cells 96 and adjacent to the first main side 1 1 , wherein the gate-cathode blocking region 351 has a higher net doping concentration than the bulk layer 3.
  • the gate-cathode blocking region 351 has a net doping concentration of /V ne t > 1.0- 10 13 cnr 3 and, most preferably /V ne t > 1 .0- 10 14 cnr 3 .
  • the gate-cathode blocking region 351 has a net doping concentration of /V ne t ⁇ 5.0-10 16 cnr 3 .
  • the second anode layer 55 of a diode cell 96 and the base layer 6 from a gate commutated thyristor cell 91 are separated from each other by the bulk layer 3 (i.e. such part of the bulk layer 3 lying between the second anode layer 55 and the base layer 6) and the gate-cathode blocking region 351 .
  • the gate-cathode blocking region 351 is embedded in the bulk layer 3, which shall mean that the gate-cathode blocking region 351 is separated from any p doped layer by the bulk layer 3.
  • the bulk layer 3 surrounds the gate-cathode blocking region 351 at the lateral sides and the bottom of the gate-cathode blocking region 351. Lateral is meant in a direction perpendicular to the first main side 1 1 , whereas the bottom shall be that side of the gate-cathode blocking region 351 , which is arranged opposite to the first main side 1 1.
  • the gate-cathode blocking region 351 is formed by an n-type doping process step, in particular implant and drive-in of phosphorus, arsenic, or some other V group elements suitable for n-type doping of silicon; or by phosphorus deposition mechanisms like exposition to POC and subsequent drive-in.
  • the gate-cathode blocking region 351 together with that parts of the bulk layer 3 which are located between the diode and GCT region represents the separation region 35 of a BGCT in accordance with the invention.
  • the gate-cathode blocking region 351 reduces gate-cathode leakage current while maintaining the gate-cathode blocking capability for the gate drive, thus allowing reduc- ing a minimum separation distance.
  • Fig. 5 shows a comparison of gate-cathode blocking characteristics obtained by means of numeric simulation.
  • the solid line represents gate-to-cathode leakage current for the prior art device as shown in Fig. 1 for a width of the uniform separation region 350 of 30 ⁇ .
  • the dashed line represents gate-to-cathode leakage current for the BGCT according to the invention as shown in Fig. 4 for widths of gate-cathode blocking region 351 and separation region 35 of 30 ⁇ .
  • the gate-to-cathode leakage current is significantly reduced for the BGCT with gate-cathode blocking region 351 in accordance with the invention, in particular for gate voltages between -20V and -30V.
  • the n-type doping process step for forming the gate-cathode blocking regions 351 may be spatially restricted to such areas located between diode cells and GCT cells by ap-litiste masks. Preferably, it may also be or can also be done at the total cathode side of the device without any additional mask.
  • FIG. 6 shows a sectional view of a preferred embodiment of a semiconductor device in accordance with the present invention.
  • the gate-cathode blocking region 351 is covered with oxide 352, i.e. S1O2.
  • the oxide is covered by a metallization 353.
  • an electrically conductive connection is provided between the metallization 353 and the cathode electrode 2 and/or the second anode electrode 28, so that the metallization 353 is always at a cathode potential of the GCT (i.e., the diode anode potential).
  • the minimum separation distance, and thus a width of the separation regions may be kept at a minimum. This allows a better utilization of semiconductor, i.e. silicon, volume, due to plasma spread from GCT regions to dedicated diode regions in GCT mode and vice versa
  • Gate-cathode leakage current may be reduced while maintaining the required blocking capability for the gate drive (the required gate-cathode blocking capability i.e., about -20 to -30 V)
  • ⁇ PNP (p-base, n-base, p-diode) punch through effect may be avoided, which is particularly important in situations where the minimum separation distance is reduced due to process variations, i.e. lateral diffusion of the p-profiles, in particular base layer 6 and second anode layer 55.
  • the device comprises at least one mixed part 99, in which diode cells 96 al- ternate with GCT cells 91.
  • the diode cells 96 are arranged such that one diode cell is arranged as to neighbor two GCT cells 91. That means that each diode cell 96 is arranged such that one second anode layer 55 is arranged to neighbor two GCT cells 91 , i.e. between the first cathode layers 4 belonging to these GCT cells 91 and/or their gate electrodes 7.
  • a bipolar junction transistor (BJT) is formed between the second anode layer 55 of diode cells 96 and the first anode layer 5 of neighboring GCT cells 91.
  • BJT bipolar junction transistor
  • SOA safe operating area
  • a gate power is reduced due to the BJT during turn-off, which will carry a certain amount of turn-off current through the cathode terminal of the BJT, i.e. the diode anode electrode 28.
  • the number of diode cells is defined as the number of second anode layers and for the GCT cells as the number of first cathode layers.
  • the diode cell shall be understood as the arrangement of the second anode layers and the GCT cells as the arrangement of first cathode layers.
  • a location of a diode cell 96 it shall be understood as a location of the second anode layer 55 of said diode cell, i.e. the location of the first main sided layers of said diode cell.
  • a location of an GCT cell it shall be understood as a location of the first cathode layer 4 (and gate electrode 7 and base layer 6), i.e. the location of the first main sided layers of the GCT cell.
  • the ratio of GCT cells 91 to diode cells 96 is at least 3:1 in order to achieve a good BGCT performance in GCT mode. Even with such a ratio, there are still enough diode cells 96 to ensure good performance in diode mode.
  • the structures on the first main side are aligned to the structures of the second main side. That means that in a diode cell the second anode layer is ar- ranged in projection/opposite to the second cathode layer. In the GCT cells the first cathode layer and the gate electrode are arranged in orthogonal projection /opposite to the first anode layer.
  • the diode cells 96 may have such a small size that during operation of the device in the GCT mode the plasma is formable in the diode cell 96.
  • This effect may be achieved by at least one of or all of the diode cells 96 have a maximum lateral extension in a plane parallel to the first main side 1 1 of 50 up to 500 ⁇ .
  • at least one of or all of the GCT cells 91 may have a maximum lateral extension between 50 ⁇ and 500 ⁇ .
  • at least one or all of the GCT and the diode cells have a maximum lateral between 50 ⁇ and 500 ⁇ .
  • first anode layer 5 and second cathode layer 45 may be aligned to the layers on the first main side such that for a diode cell 96 the second cathode layer 45 is arranged in orthogonal projection /opposite to the second anode layer 55.
  • first cathode layer and the gate electrode 7 are arranged in orthogonal projection to/opposite to the first anode layer 5.
  • the second cathode layers 45 are arranged in orthogonal projection to a second anode layer 55 in an area, which is limited at most by an orthogonal projection area of the first cathode layer 4 of the directly adjacent GCT cells.
  • the first cathode layer 4 comprises one first half part, which is arranged closer to a second cathode layer 45 than a second half part.
  • the area, in which the second cathode layer 45 is arranged may be further limited by the diode cell area and the orthogo- nal projection area of the first half part of the first cathode layers 4 of the directly adjacent GCT cells 91. That means that the second cathode layers 45 are arranged in orthogonal projection to a second anode layer 55 an area, which is limited at most by an orthogonal projection area of that half part of the first cathode layer 4 of the directly adjacent GCT cells 91 , which is arranged towards said second cathode layer 45.
  • a net doping concentration and depth of base layer 6 and the second anode layer 55 can be chosen to be identical or independently from each other.
  • the net doping concentration and/or the depth of the second anode layer 55 can be chosen to be lower than of the base layer 6. In that case, there is less injection efficiency in the second anode layer 55 and therefore, less lifetime control is needed than in a device with a deeper second anode layer 55.
  • the depth of the cathode blocking region 351 is lower than a depth of the base layer 6; and preferably also lower than a depth of the second anode layer 55; between which the cathode blocking region 351 is located.
  • the depth of the second anode layer 55 and the base layer 6 typically range between 2 ⁇ and 250 ⁇ , preferably between 10 ⁇ and 150 ⁇ ; the depth of the cathode blocking region 351 preferably ranges between 2 ⁇ and 30 ⁇ , preferably between 5 ⁇ and 15 ⁇ .
  • depth shall indicate the maximum distance to which a layer extends from that main side adjacent to which said layer is arranged, i.e. for the p-base layer 6 it is the maximum distance from the first main side 1 1 and in orthogonal projection to the first main side 1 1 .
  • the first main side 1 1 shall be arranged in that plane on which the GCT cathode electrodes 2 and/or the diode anode electrodes 28 project from the wafer 10.
  • the total area of the second cathode layers 45 in a plane parallel to the first main side 1 1 can exemplarily be chosen to be 10 to 30 % of the total wafer area.
  • the second cathode layer 45 effectively assumes the additional function of a buffer layer.
  • the second cathode layer 45 is more weakly n-doped as compared to embodiments in which a buffer layer 8 is present, i.e. with preferably with a net doping concentration as specified above for the buffer layer 8.
  • a modified second cathode layer 45' may be provided adjacent, preferably contiguous, to the second main side instead of the second cathode layer 45 as described above.
  • Modified second cathode layer 45' is formed of n-, preferably (n+)-doped distributed cathode regions 451 alternating with p-, preferably (p+)- doped anode shorted regions 51.
  • the modified second cathode layer 45' does not have to be aligned with the structure of the device on the first main side 1 1 , i.e.
  • the modified second cathode layer 45' does not have to be located underneath the second anode layer 55 in an orthogonal projection in a vertical direction.
  • the first anode layers 5 does not have to be located underneath the cathode layer 4 in an orthogonal projection in vertical direction.
  • the modified second cathode layer 45' may be located partially or completely underneath the cathode layer 4 of one or more GCT cells in an orthogonal projection in vertical direction.
  • the diode cells 96 i.e. second anode layers 55
  • the diode cells 96 may be distributed uniformly over the wafer area in the mixed part 99.
  • pilot GCT part 9 on the wafer 10, which only consists of GCT cells 91 (exemplarily six or more, exemplarily at least 10), which are arranged directly adjacent to each other, and not having a diode cell in the pilot GCT part 9.
  • a pilot GCT part 9 consists on the first main side 1 1 of first cathode layers 4 and gate electrodes 7 (together with the common, continuous base layer 6), which are arranged directly adjacent to each other, without having a second anode layer 55 in between.
  • Such a pilot GCT part can be a single GCT part 9 or there may be a plurality, i.e. two or more such GCT parts arranged in the device.
  • the total area of the GCT pilot parts 9 can be 10 to 50 % of the total wafer area. With such a pilot GCT part 9 the turn-on performance of the device can be improved.
  • Fig. 8 shows a top view of yet another preferred embodiment of a semiconductor device in accordance with the present invention, in which the silicon wafer 10 has a shape of a circle and the first cathode layers 4 and the second anode layers 55 are arranged as stripes radially to a center of the circle.
  • the diode cells 96 may be arranged in a regular manner around the center of the circle as shown in FIG. 8.
  • a gate contact 75 which is connected electrically conductive to the gate electrodes 7, is provided in a central area of the silicon wafer 10.
  • the gate contact may advantageously also be provided on a peripheral area of the silicon wafer, or between the stripes as which the first cathode layers 4 and the second anode layers 55 are arranged as described above; and may in particular have annular shape.
  • a lifetime killing layer is arranged at least in the diode cells 96. This may be achieved by limiting the lifetime killing layer to the diode cells 96 by using a mask during creation or by applying a laterally limited ion beam onto the diode cells 96.
  • the lifetime killing layer may be formed as a continuous layer over the whole area of the wafer in one plane, the plane being arranged parallel to the main sides. Independently of whether the lifetime killing layer is limited to the diode cells or made as a continuous layer, the device is exemplarily irradiated with protons or Helium ions for the creation of the lifetime killing layer, followed by an anneal step.
  • the conductivity types are interchanged, i.e. all layers and regions of the first conductivity type are (p-), p or (p+) type, respectively and all layers and regions of the second conductivity type are (n-), n, or (n+) type.
  • N ne i NA - ND for regions or layers in which a total density of donors ND is smaller than a total density of acceptors NA,
  • a net doping concentration /V ne t(n+) of an (n+)-doped region or layer is larger than a net doping concentration /V ne t(n) of an (n)-doped region or layer, which in turn is larger is larger than a net doping concentration /V ne t(n-) of an (n-)-doped region or layer.
  • a net doping concentration /V ne t(p+) of an (p+)-doped region or layer is larger than a net doping concentration /V ne t(p) of an (p)-doped region or layer, which in turn is larger is larger than a net doping concentration /V ne t(p-) of an (p-)-doped region or layer.
  • a net doping concentration of a region or layer is referred to, this is preferably to be understood as - possibly local - maximum net doping concentration within said region or layer.
  • a local net doping concentration decays in one or more spatial directions from an area with maximum net doping concentration.
  • the bulk layer 3 is a layer of una- mended net doping concentration by the dopant diffusion process step, i.e. having the net doping concentration as achieved preferably by epitaxial growth of the bulk layer 3.
  • the bulk layer 3 has a constantly low net doping concentration /V ne t(n-).
  • the substantially constant net doping concentration of the bulk layer 3 means that the net doping concentration is substantially homogeneous throughout the bulk layer 3, however without excluding that fluctuations in the net doping concentration within the bulk layer 3 being in the order of a factor of one to five may possibly be present due to e.g. fluctuations in the epitaxial growth process.
  • the final bulk layer thickness and net doping concentration is chosen due to the application needs.
  • a thickness of buffer layer 8 is usually between 15 ⁇ and 75 ⁇ , preferably between 20 ⁇ and 55 ⁇ .
  • a thickness of second cathode layer 45 is preferably between 2 ⁇ and 30 ⁇ , preferably 10 ⁇ and 25 ⁇ .
  • a thickness of bulk layer 3 depends on a voltage class of the semiconductor device and is preferably between 350 ⁇ and 440 ⁇ for a 3.3kV device, and preferably between 480 ⁇ and 570 ⁇ for a 4.5kV device.
  • the term lateral refers to a direction parallel to the first main side 1 1 .
  • lateral extension, dimension, distance etc. refers to an extension, dimension, distance, etc. in a direction or plane parallel to the first main side 1 1 .
  • the vertical refers to a direction perpendicular to the first main side 1 1.
  • vertical extension, dimension, distance etc. refers to an extension, dimension, distance, etc. in a direction perpendicular to the first main side 1 1 .

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  • Thyristors (AREA)

Abstract

A semiconductor device (1) comprises a semiconductor slab having a first main side (11) and a second main side (15), said second main side (15) being arranged parallel to the first main side (11); and a bulk layer (3) of a first conductivity type located between the first main side (11) and the second main side (15); the gate commutated thyristor cell (91) comprising layers in the following order in the semi-conductor slab between the first and second main side (11, 15): a first cathode layer (4) of the first conductivity type,a base layer (6) of a second conductivity type different from the first conductivity type,the bulk layer (3),a buffer layer (8) of the first conductivity type,a first anode layer (5) of the second conductivity type, the gate commutated thyristor cell (91) further comprising a GCT cathode electrode (2) arranged on the first main side on the first cathode layer,a first main electrode (25) arranged on the second main side on the first anode layer (5),a gate electrode (7) arranged on -preferably lateral to the first cathode layer (4) and separated from it by -the base layer (6);a diode cell (96), the diode cell comprising layers in the following order in the semiconductor slab between the first and second main side (11, 15):a second anode layer (55) of the second conductivity type,the bulk layer (3), and a second cathode layer (45) of the first conductivity type adjacent to the second main side (15); and a diode anode electrode (28) arranged on the first main side on the second anode layer (55). Agate-cathode blocking region (351) of the first conductivity type is arranged between second anode layer (55) and base layer (6) and adjacent to the first main side (11),the gate-cathode blocking region (351) having a higher net doping concentration than the bulk layer (3).

Description

Reverse-Conducting Power Semiconductor Device
Description Field of invention
The invention relates to the field of power electronics. In particular, it relates to a semiconductor device according to the preamble of claim 1.
Background of the invention
A bi-mode gate commutated thyristor (BGCT) combines one or more gate commutated thyristors (GCTs) and one or more diodes within a single power semiconductor device. The BGCT is built around a semiconductor slab, in particular a semiconductor wafer, which comprises a plurality of gate commutated thyristor (GCT) regions electrically connected in parallel to one another, and a plurality of diode regions, also electrically connected in parallel to one another and to the gate turn-off thyristor regions, albeit with opposing forward direction. The BGCT is a major building block for BGCT modules, in which a capability of operating the BGCT in an integrated gate commutated thyristor (IGCT) mode is obtained by integrating the semiconductor slab with a gate circuit on a printed circuit board. This allows for providing low inductance electrically conductive connections between gate circuit and actual gates of the gate commutated thy- ristor regions, which electrically conductive connections are capable of withstanding significantly higher currents than e.g. wires traditionally used to connect conventional, non-integrated gate circuits and gate turn-off transistors. IGCTs are explained in detail in Wikipedia article
http://en.wikipedia.org/w/index.php?title=lntegrated gate-commutated thyristor&oldid=560633166 which is hereby included by reference in its entirety. The diode regions provided in the semiconductor slab allow for operating the BGCT in a diode mode; thus providing for reverse conductivity of the BGCT, which is required for a plurality of applications in power electronics.
A prior art BGCT, also referred to as reverse-conducting I GCT (RC-IGCT) is described in WO 2012/041958 A2, which is hereby included by reference in its entirety. FIG 1 shows in a sectional view of the prior art BGCT from WO 2012/041958 A2.
The prior art BGCT 1 ' comprises a semiconductor slab having a first main side 1 1 and a second main side 15, said second main side 15 being arranged parallel to the first main side 1 1 ; and an (n-)- doped bulk layer 3 located between - and extending in a di- rection parallel to - the first main side 1 1 and the second main side 15. The BGCT 1 ' further comprises a plurality of gate commutated thyristor cells 91 , each gate commu- tated thyristor cell 91 comprising a GCT region in the semiconductor slab, said GCT region comprising layers in the following order between the first main side 1 1 and the second main side 15: an n-doped first cathode layer 4, a p-doped base layer 6, a thy- ristor drift layer 3' formed by the bulk layer 3, an n-doped buffer layer 8, a first (p+)- doped anode layer 5. The gate commutated thyristor cell 91 further comprises a cathode electrode 2 arranged on the first main side on each first cathode layer 4, a first main electrode 25 arranged on the second main side on each first anode layer 5, a plurality of gate electrodes 7 arranged on each base layer 6 lateral to the first cathode layer 4 and separated from it by the base layer 6. The BGCT 1 ' further comprises a plurality of diode cells 96, each diode cell comprising a diode region in the semiconductor slab, said diode region comprising layers in the following order in the semiconductor slab between the first and second main side: a p-doped second anode layer, a diode drift layer 3" formed by the bulk layer 3, and an n-doped second cathode layer 45, which is arranged alternating to the first anode layer 5 adjacent to the second main side 15. Finally, BGCT V comprises a second anode electrode 28 arranged on the each first main side on the second anode layer 55.
The diode regions are separated from the GCT regions by uniform separation regions 350, which are formed by parts of the bulk layer 3 located between the diode regions and GCT regions and where the bulk layer 3 extends to the first main side 1 1.
To alleviate problems with overheating that were observed in earlier versions of reverse conducting ICGT devices, in which a lateral distance between GCT and diode regions was sufficiently large so that no mutual influence occurred when the devices were operated in the respective modes, WO 2012/041958 A2 suggests to at least par- tially utilize the same semiconductor volume in both GCT and diode modes. The basic concept is based on enabling the GCT mode operation to utilize the diode regions during conduction due to the charge spreading, i.e. spreading of an electron-hole plasma which forms in the semiconductor slab when conduction occurs, into those regions. The diode mode operation is also able to utilize the GCT regions. Tilted arrows in Fig. 1 indicate an expected plasma spread in GCT mode of operation, which will be inverted for the diode mode. A ratio of GCT cells to diode cells will determine the effective area utilized in both modes of operation. Dimensioning of GCT cells and of the uniform separation regions 350 between the diode cells 96 and GCT cells 91 is also an important factor for area utilization. The uniform separation regions 350 must be designed suffi- ciently broad to provide a sufficient blocking capability for a gate voltage required to drive the GCT, i.e. a gate to cathode blocking capability of -20 to -30 V must be ensured during GCT turn-off and blocking. On the other hand, uniform separation region dimensions should be kept to a minimum for maximum total area utilization, as well as for maximum plasma spreading from the GCT regions to the diode regions in GCT mode of operation and vice versa.
Fig. 2 shows a top view of the prior art device shown in Fig. 1. As may be seen, the device comprises at least one mixed part 99 in which diode cells 96 alternate with one or more GCT cells 91.
Given that BGCTs are generally designed and intended for use in medium to high volt- age applications, the bulk layer 3 is usually very low (n-)-doped, i.e. a net density of donors Λ/net in the bulk layer is in a range between
/Vnet(n-) = 5.0- 1011cnr3 and /Vnet(n-) = 1.0- 1014cnr3. Therefore, if the uniform separation region dimensions, in particular a minimum separation distance between a diode region and an adjacent GCT region, are reduced, there is a possibility that a punch through ef- feet will occur so that the separation region cannot block the gate voltage required for turn-off or during blocking. Even if the minimum separation distance is sufficient to block required gate voltage (during turn-off and blocking), there will be a substantial gate-to-cathode leakage current due to a parasitic PNP transistor being formed by base layer 6, uniform separation region 350, and second anode layer 55. Due to the low doping of the bulk layer 3, which constitutes the uniform separation region and thus acts as n-base for the parasitic transistor, an unacceptably large transistor gain may result in connection with a small effective width of the transistor n-base. Fig. 3 illustrates simulation results of gate-cathode blocking characteristics for different widths of the uniform separation region. Leakage current for a single GCT-diode pair is plotted as a function of gate voltage. While only weak significant parasitic pnp-transistor behavior may be observed for a width of 75μηι, an over-exponential increase in leakage current occurs between 0 and -25V for a width of 30μηι. For a width of 20μηι, it was actually not possible to maintain a gate voltage of more than -10V due to the strong parasitic transistor effect. However, even at a width of 30μηι, the leakage current is unaccepta- bly high, given that a total leakage current for the BGCT corresponds to the current shown in Fig. 3 multiplied with the number of GCT-diode pairs in the device, which can amount from several hundred to several thousand; and that the gate voltage generally needs to be applied not only during turn-off, but also while the GCTs are in blocking mode to ensure a stable operation of the BGCT. As the total leakage current will flow through the gate circuit, the gate circuit has to be properly designed to withstand such currents. Electronic components, in particular MOSFETs, constituting the gate circuit thus have to meet demanding specifications, leading to an inacceptable increase in price and dimensions of BGCT modules produced from BGCTs with such high leakage currents.
Description of the invention
It is an object of the invention to provide a reverse conducting power semiconductor device with improved performance of the device in view of thermal and electrical properties and reduced size.
This object is achieved by a semiconductor device comprising a semiconductor slab, in particular a semiconductor wafer or semiconductor die, the semiconductor slab having a first main side and a second main side, said second main side being parallel to the first main side; and a bulk layer of a first conductivity type located between the first main side and the second main side, the semiconductor device comprising a gate com- mutated thyristor cell, said gate commutated thyristor cell comprising layers in the following order in the semiconductor slab between the first and second main side: a first cathode layer of the first conductivity type, a base layer of a second conductivity type different from the first conductivity type, the bulk layer, a buffer layer of the first conductivity type, a first anode layer of the second conductivity type; the gate commutated thy- ristor cell further comprising: a GCT cathode electrode arranged on the first main side on the first cathode layer, a gate electrode arranged on the base layer; the semiconductor device further comprising a diode cell, said diode cell comprising layers in the following order in the semiconductor slab between the first and second main side: a second anode layer of the second conductivity type, the bulk layer, a buffer layer having a higher doping concentration than the bulk layer, and a second cathode layer of the first conductivity type adjacent to the second main side; the diode cell further comprising a diode anode electrode arranged on the first main side on the second anode layer; the semiconductor device further comprising a first main electrode arranged on the second main side. A gate-cathode blocking region of the first conductivity type is arranged between second anode layer and base layer and adjacent to the first main side, the gate-cathode blocking region having a higher net doping concentration than the bulk layer. The second anode layer and the base layer are separated from each other by the bulk layer and the gate-cathode blocking region, which is embedded in the drift layer. Thus, the gate-cathode blocking region is not connected to any layer of the second conductivity type. This ensures a reliable blocking at low leakage currents. Furthermore, it is easier to manufacture an n barrier in a lowly doped drift layer than in a highly p doped layer and the width and doping concentration of the separation region can be adjusted and optimized independently from each other.
More specifically, the bulk layer preferably extends in a direction at least essentially parallel to the first main side and the second main side; the gate electrode is preferably arranged lateral to the first cathode layer at a distance from the latter and separated from the first cathode layer by the base layer; and/or the second cathode layer is ar- ranged alternating to the first anode layer. Also, preferably, the bulk layer constitutes a thyristor drift layer in a GCT region of the semiconductor slab comprised by the GCT cell; and a diode drift layer in a diode region of the semiconductor slab comprised by the diode cell. Further, the first main electrode arranged on the second main side is preferably arranged adjacent to, in particular contiguous to, both the first anode layer and the second cathode layer.
Preferably, the device comprises at least one mixed part, in which diode cells (i.e. the second anode layers of the diode cells) alternate with one or more GCT cells (i.e. the first cathode layers (and gate electrode 7 and base layer 6) of the GCT cells).
Further advantages according to the present invention will be apparent from the de- pendent claims.
Brief description of the drawings
The subject matter of the invention will be explained in more detail in the following text with reference to the attached drawings, in which: FIG. 1 shows a sectional view of a BGCT according to the prior art;
FIG. 2 shows a top view of the prior art BGCT shown in Fig 1 ;
FIG. 3 shows simulation results for gate-cathode blocking characteristics of prior art BGCTs for different widths of the uniform separation region;
FIG. 4 shows a sectional view of a semiconductor device in accordance with the present invention;
FIG. 5 shows a comparison of gate-cathode blocking characteristics obtained by means of numeric simulation;
FIG. 6 shows a sectional view of a preferred embodiment of a semiconductor device in accordance with the present invention;
FIG. 6 shows a sectional view of another preferred embodiment of a semiconductor device in accordance with the present invention;
FIG. 8 shows a top view of yet another preferred embodiment of a semiconductor device in accordance with the present invention
The reference symbols used in the figures and their meaning are summarized in the list of reference symbols. Generally, alike or alike-functioning parts are given the same reference symbols. The described embodiments are meant as examples and shall not confine the invention.
Detailed description of preferred embodiments
FIG. 4 shows a sectional view of bi-mode gate commutated thyristor (BGCT) representing a semiconductor device in accordance with the present invention. BGCT 1 comprises a semiconductor slab in form of a silicon wafer 10, the semiconductor slab having a first main side 1 1 and a second main side 15, said second main side 15 being arranged parallel to the first main side 1 1 ; and a bulk layer 3 located between - and ex- tending in a direction at least essentially parallel to - the first main side 1 1 and the second main side 15. The bulk layer 3 is (n-)-doped, representing a first conductivity type, preferably having a net doping concentration between /Vnet = 5.0- 1011cnr3 and /Vnet = 5.0- 1013cnr3, preferably less than 1.0- 1013cnr3. BGCT 1 further comprises a plurality of gate commutated thyristor cells 91 , each gate commutated thyristor cell 91 comprising layers in the following order in the semiconductor slab between the first and second main side: a first (n+)-doped cathode layer 4, a p-doped - representing a second conductivity type - base layer 6; the bulk layer 3, constituting a thyristor drift layer 3'; an n- doped buffer layer 8, which has a higher (net) doping concentration than the bulk layer 3, preferably having a net doping concentration between /Vnet = 1 .0- 1016cnr3 and /Vnet = 2.O 1016cnr3; a (p+)-doped first anode layer 5, preferably having a net doping concentration between /Vnet = 1 .0- 1017cnr3 and /Vnet = 1 .0- 1018cnr3, most preferably between Λ/net = 3.0- 1017cnr3 and /Vnet = 5.0- 1017cnr3; each gate commutated thyristor cell 91 further comprising a GCT cathode electrode 2 arranged on the first main side on the first cathode layer 4 preferably having a net doping concentration between /Vnet =
1.O 1018cnr3 and /Vnet = 1.0- 1021cnr3; a first main electrode 25 arranged on the second main side on the first anode layer 5; and a gate electrode 7 arranged on the base layer 6, preferably having a net doping concentration between /Vnet = 1 .0- 1016cnr3 and /Vnet = 1.O 1019cnr3. The bulk layer exemplarily has a constant low doping concentration, whereas the buffer layer 8 has a higher doping concentration than the bulk layer, exemplarily the buffer layer has a doping concentration decreasing from a maximum doping concentration at or close to the interface the anode layer 3 to a lower doping concentration at the interface to the bulk layer 3. The buffer layer could also have a constant high doping concentration.
BGCT 1 further comprises a plurality of diode cells 96, each diode cell 96 comprising layers in the following order in the semiconductor slab between the first main side 1 1 and the second main side 15; a p-doped - or alternatively (p+)-doped - second anode layer 55, preferably having a net doping concentration between /Vnet = 1.0- 1016cnr3 and Λ/net = 1.0- 1019cnr3; the bulk layer 3, constituting a diode drift layer 3", the buffer layer 8, and a, preferably (n+)-doped, second cathode layer 45 preferably having a net doping concentration between /Vnet = 1.0- 1018cnr3 and /Vnet = 1.0- 1019cnr3, which is arranged alternating to the first anode layer 5 adjacent to the second main side 15. Each diode cell 96 further comprises a diode anode electrode 28 arranged on the first main side on the second anode layer 55. The first main electrode 25, which extends contiguous to and along the second cathode layer 45 on the second main side 15, acts as diode cathode electrode. Cathode electrode 2 and anode electrode 28 are shorted by means of an electrically conductive connection not shown in Fig. 4.
The gate electrode 7 of each individual GCT cell 91 is preferably arranged lateral to the first cathode layer 4 and separated from it by the base layer 6 of said individual GCT cell 91 . In an exemplary embodiment the buffer layer 8 has a net doping concentration of at most 1016 cm-3. The first main sided layers of each individual GCT cell (i.e. first cathode layer 4, base layer 6 together with gate electrode 7) may be aligned to the second main sided layers of said individual GCT cell (i.e. first anode layer 5). In case of non-alignment that first anode layer 5, which is arranged closest to the first main sided layers shall be regarded as belonging to the same GCT cell 91 . Therefore, in case of non-alignment the device may be designed in such a way that more than one second sided layer may be allocated to a cell or in which one second sided layer is allocated to two cells.
The (n+)-doped second cathode layer 45 of the diode cells are arranged alternating to the first anode layer 5 adjacent to the second main side 15. The second anode layer 55 is contacted by the second anode electrode 28. The first main sided layers of each individual diode cell (i.e. second anode layer 55) may be aligned to the second main sided layers of said individual diode cell (i.e. second cathode layer 45). In case of non-alignment that second cathode layer 45, which is arranged closest to the first main sided layers shall belong to the same individual diode cell 96. Therefore, in case of non-alignment the device may be designed in such a way that more than one second sided layer may be allocated to an individual cell or in which one second sided layer is allocated to two individual cells.
The first anode layers 5 of the GCT cells 91 and second cathode layers 45 of the diode cells 96 are shorted by first main electrode 25. Due to these shorts, the BGCT shows a soft performance, i.e. a snappy reverse recovery behavior is alleviated.
According to the invention, an n-doped gate-cathode blocking region 351 is arranged between second anode layers 55 and base layers 6 of neighboring GCT cells 91 and diode cells 96 and adjacent to the first main side 1 1 , wherein the gate-cathode blocking region 351 has a higher net doping concentration than the bulk layer 3. Exemplarily the gate-cathode blocking region 351 has a net doping concentration of /Vnet > 1.0- 1013cnr3 and, most preferably /Vnet > 1 .0- 1014cnr3. Exemplarily the gate-cathode blocking region 351 has a net doping concentration of /Vnet < 5.0-1016cnr3. The second anode layer 55 of a diode cell 96 and the base layer 6 from a gate commutated thyristor cell 91 are separated from each other by the bulk layer 3 (i.e. such part of the bulk layer 3 lying between the second anode layer 55 and the base layer 6) and the gate-cathode blocking region 351 .The gate-cathode blocking region 351 is embedded in the bulk layer 3, which shall mean that the gate-cathode blocking region 351 is separated from any p doped layer by the bulk layer 3. Thus, the bulk layer 3 surrounds the gate-cathode blocking region 351 at the lateral sides and the bottom of the gate-cathode blocking region 351. Lateral is meant in a direction perpendicular to the first main side 1 1 , whereas the bottom shall be that side of the gate-cathode blocking region 351 , which is arranged opposite to the first main side 1 1. The gate-cathode blocking region 351 is formed by an n-type doping process step, in particular implant and drive-in of phosphorus, arsenic, or some other V group elements suitable for n-type doping of silicon; or by phosphorus deposition mechanisms like exposition to POC and subsequent drive-in.
The gate-cathode blocking region 351 together with that parts of the bulk layer 3 which are located between the diode and GCT region represents the separation region 35 of a BGCT in accordance with the invention.
The gate-cathode blocking region 351 reduces gate-cathode leakage current while maintaining the gate-cathode blocking capability for the gate drive, thus allowing reduc- ing a minimum separation distance. Fig. 5 shows a comparison of gate-cathode blocking characteristics obtained by means of numeric simulation. The solid line represents gate-to-cathode leakage current for the prior art device as shown in Fig. 1 for a width of the uniform separation region 350 of 30μηι. The dashed line represents gate-to-cathode leakage current for the BGCT according to the invention as shown in Fig. 4 for widths of gate-cathode blocking region 351 and separation region 35 of 30μηι. As can easily be discerned, the gate-to-cathode leakage current is significantly reduced for the BGCT with gate-cathode blocking region 351 in accordance with the invention, in particular for gate voltages between -20V and -30V.
Surprisingly, no negative influence on a main blocking capability of BGCT 1 could be observed, i.e. a maximum voltage that may be applied between cathode electrode 2, which is shorted to second anode electrode 28, and first main electrode 25 without the occurrence of a breakdown.
The n-type doping process step for forming the gate-cathode blocking regions 351 may be spatially restricted to such areas located between diode cells and GCT cells by ap- propriate masks. Preferably, it may also be or can also be done at the total cathode side of the device without any additional mask.
FIG. 6 shows a sectional view of a preferred embodiment of a semiconductor device in accordance with the present invention. The gate-cathode blocking region 351 is covered with oxide 352, i.e. S1O2. Preferably, the oxide is covered by a metallization 353. Preferably, an electrically conductive connection is provided between the metallization 353 and the cathode electrode 2 and/or the second anode electrode 28, so that the metallization 353 is always at a cathode potential of the GCT (i.e., the diode anode potential). The advantages of providing n-doped gate-cathode blocking regions 351 arranged between neighboring GCT and diode cells may be summarized as follows:
• The minimum separation distance, and thus a width of the separation regions may be kept at a minimum. This allows a better utilization of semiconductor, i.e. silicon, volume, due to plasma spread from GCT regions to dedicated diode regions in GCT mode and vice versa
• Gate-cathode leakage current may be reduced while maintaining the required blocking capability for the gate drive (the required gate-cathode blocking capability i.e., about -20 to -30 V)
· PNP (p-base, n-base, p-diode) punch through effect may be avoided, which is particularly important in situations where the minimum separation distance is reduced due to process variations, i.e. lateral diffusion of the p-profiles, in particular base layer 6 and second anode layer 55.
Preferably, the device comprises at least one mixed part 99, in which diode cells 96 al- ternate with GCT cells 91. In an exemplary embodiment, the diode cells 96 are arranged such that one diode cell is arranged as to neighbor two GCT cells 91. That means that each diode cell 96 is arranged such that one second anode layer 55 is arranged to neighbor two GCT cells 91 , i.e. between the first cathode layers 4 belonging to these GCT cells 91 and/or their gate electrodes 7.
Due to the alternating arrangement of GCT cells 91 and diode cells 96, a bipolar junction transistor (BJT) is formed between the second anode layer 55 of diode cells 96 and the first anode layer 5 of neighboring GCT cells 91. In GCT turn-off mode, a safe operating area (SOA) performance is improved due to this integrated BJT. Besides, a gate power is reduced due to the BJT during turn-off, which will carry a certain amount of turn-off current through the cathode terminal of the BJT, i.e. the diode anode electrode 28.
Due to the distributed arrangement of diode and GCT cells, heat produced during operation is distributed over a greater area, resulting in improved thermal resistance. In case of the device working in GCT mode exemplarily, due to the distributed cells, the heat can easily spread also into the diode cells and therefore, the temperature within the device is reduced as compared to devices in which a single diode is concentrated to one continuous area so that the heat spreads much less efficient into the diode area. Also the current handling capability is improved due to the at least part or full integration of the diode and GCT structures for allowing enhanced, ideally full, utilization of a cross section of the silicon wafer 10 in GCT mode and sufficient utilization of the cross section in the diode mode of operation. The above effect is reached due to the close proximity of the GCT and diode cells, i.e. the alternating arrangement of GCT and diode cells, which would allow the charge plasma during conduction for the GCTs to spread laterally into or through the adjacent diode cells.
In another exemplary embodiment there may be a plurality of GCT cells arranged directly neighboring each other such that the ratio of diode cells 96 to GCT cells 91 var- ies between 1 :1 and 1 :5. The number of diode cells is defined as the number of second anode layers and for the GCT cells as the number of first cathode layers. Also for the mixed part the diode cell shall be understood as the arrangement of the second anode layers and the GCT cells as the arrangement of first cathode layers.
Within the context of the present patent application a location of a diode cell 96 it shall be understood as a location of the second anode layer 55 of said diode cell, i.e. the location of the first main sided layers of said diode cell. A location of an GCT cell it shall be understood as a location of the first cathode layer 4 (and gate electrode 7 and base layer 6), i.e. the location of the first main sided layers of the GCT cell.
In this embodiment, there are at least as many GCT cells 91 as there are diode cells 96. Preferably, the ratio of GCT cells 91 to diode cells 96 is at least 3:1 in order to achieve a good BGCT performance in GCT mode. Even with such a ratio, there are still enough diode cells 96 to ensure good performance in diode mode. In another exemplary embodiment, the structures on the first main side are aligned to the structures of the second main side. That means that in a diode cell the second anode layer is ar- ranged in projection/opposite to the second cathode layer. In the GCT cells the first cathode layer and the gate electrode are arranged in orthogonal projection /opposite to the first anode layer.
The diode cells 96 may have such a small size that during operation of the device in the GCT mode the plasma is formable in the diode cell 96. This effect may be achieved by at least one of or all of the diode cells 96 have a maximum lateral extension in a plane parallel to the first main side 1 1 of 50 up to 500 μηη. In order to achieve the effect also at least one of or all of the GCT cells 91 may have a maximum lateral extension between 50 μηη and 500 μηη. In another exemplary embodiment, at least one or all of the GCT and the diode cells have a maximum lateral between 50 μηη and 500 μηη. In one preferred embodiment, the layers on the second main side 15, i.e. first anode layer 5 and second cathode layer 45 may be aligned to the layers on the first main side such that for a diode cell 96 the second cathode layer 45 is arranged in orthogonal projection /opposite to the second anode layer 55. For a GCT cell 91 the first cathode layer and the gate electrode 7 are arranged in orthogonal projection to/opposite to the first anode layer 5. Alternatively, there is no alignment between the first main sided layers and the second main sided layers.
In another exemplary embodiment the second cathode layers 45 are arranged in orthogonal projection to a second anode layer 55 in an area, which is limited at most by an orthogonal projection area of the first cathode layer 4 of the directly adjacent GCT cells.
The first cathode layer 4 comprises one first half part, which is arranged closer to a second cathode layer 45 than a second half part. The area, in which the second cathode layer 45 is arranged, may be further limited by the diode cell area and the orthogo- nal projection area of the first half part of the first cathode layers 4 of the directly adjacent GCT cells 91. That means that the second cathode layers 45 are arranged in orthogonal projection to a second anode layer 55 an area, which is limited at most by an orthogonal projection area of that half part of the first cathode layer 4 of the directly adjacent GCT cells 91 , which is arranged towards said second cathode layer 45.
A net doping concentration and depth of base layer 6 and the second anode layer 55 can be chosen to be identical or independently from each other. For example, the net doping concentration and/or the depth of the second anode layer 55 can be chosen to be lower than of the base layer 6. In that case, there is less injection efficiency in the second anode layer 55 and therefore, less lifetime control is needed than in a device with a deeper second anode layer 55. Preferably, the depth of the cathode blocking region 351 is lower than a depth of the base layer 6; and preferably also lower than a depth of the second anode layer 55; between which the cathode blocking region 351 is located. Notwithstanding, while the depth of the second anode layer 55 and the base layer 6 typically range between 2μηι and 250μηι, preferably between 10μηι and 150μηι; the depth of the cathode blocking region 351 preferably ranges between 2μηι and 30μηι, preferably between 5μηι and 15μηι.
In the context of the present invention, "depth" shall indicate the maximum distance to which a layer extends from that main side adjacent to which said layer is arranged, i.e. for the p-base layer 6 it is the maximum distance from the first main side 1 1 and in orthogonal projection to the first main side 1 1 . Preferably, the first main side 1 1 shall be arranged in that plane on which the GCT cathode electrodes 2 and/or the diode anode electrodes 28 project from the wafer 10.
The total area of the second cathode layers 45 in a plane parallel to the first main side 1 1 can exemplarily be chosen to be 10 to 30 % of the total wafer area.
In a preferred embodiment in accordance with the present invention no buffer layer 8 is provided, so that the second cathode layer 45 effectively assumes the additional function of a buffer layer. Preferably, the second cathode layer 45 is more weakly n-doped as compared to embodiments in which a buffer layer 8 is present, i.e. with preferably with a net doping concentration as specified above for the buffer layer 8.
In a preferred embodiment of a semiconductor device in accordance with the present invention as shown in Fig. 7, a modified second cathode layer 45' may be provided adjacent, preferably contiguous, to the second main side instead of the second cathode layer 45 as described above. Modified second cathode layer 45' is formed of n-, preferably (n+)-doped distributed cathode regions 451 alternating with p-, preferably (p+)- doped anode shorted regions 51. The modified second cathode layer 45' does not have to be aligned with the structure of the device on the first main side 1 1 , i.e. the modified second cathode layer 45' does not have to be located underneath the second anode layer 55 in an orthogonal projection in a vertical direction. Likewise, the first anode layers 5 does not have to be located underneath the cathode layer 4 in an orthogonal projection in vertical direction. In particular, the modified second cathode layer 45' may be located partially or completely underneath the cathode layer 4 of one or more GCT cells in an orthogonal projection in vertical direction.
To allow for fast switching between GCT to diode mode the diode cells 96 (i.e. second anode layers 55) may be distributed uniformly over the wafer area in the mixed part 99.
It may also be advantageous to have a pilot GCT part 9 on the wafer 10, which only consists of GCT cells 91 (exemplarily six or more, exemplarily at least 10), which are arranged directly adjacent to each other, and not having a diode cell in the pilot GCT part 9. Such a pilot GCT part 9 consists on the first main side 1 1 of first cathode layers 4 and gate electrodes 7 (together with the common, continuous base layer 6), which are arranged directly adjacent to each other, without having a second anode layer 55 in between. Such a pilot GCT part can be a single GCT part 9 or there may be a plurality, i.e. two or more such GCT parts arranged in the device. The total area of the GCT pilot parts 9 can be 10 to 50 % of the total wafer area. With such a pilot GCT part 9 the turn-on performance of the device can be improved.
Fig. 8 shows a top view of yet another preferred embodiment of a semiconductor device in accordance with the present invention, in which the silicon wafer 10 has a shape of a circle and the first cathode layers 4 and the second anode layers 55 are arranged as stripes radially to a center of the circle. The diode cells 96 may be arranged in a regular manner around the center of the circle as shown in FIG. 8. In another alternative, there are pilot GCT parts 9, arranged in segments of the circle alternating with segments, in which GCT cells 91 alternate with diode cells 96, thus forming an area 99 mixed with GCT cells 91 with diode cells 96. That means that a plurality of first cathode layers 4, base layer 6 and gate electrodes 7 are arranged directly adjacent to each other without having a second anode layer 4 in between.
In the embodiment as shown in Fig. 8, a gate contact 75, which is connected electrically conductive to the gate electrodes 7, is provided in a central area of the silicon wafer 10. Alternatively, the gate contact may advantageously also be provided on a peripheral area of the silicon wafer, or between the stripes as which the first cathode layers 4 and the second anode layers 55 are arranged as described above; and may in particular have annular shape.
In another preferred embodiment, a lifetime killing layer is arranged at least in the diode cells 96. This may be achieved by limiting the lifetime killing layer to the diode cells 96 by using a mask during creation or by applying a laterally limited ion beam onto the diode cells 96. In another exemplary embodiment, the lifetime killing layer may be formed as a continuous layer over the whole area of the wafer in one plane, the plane being arranged parallel to the main sides. Independently of whether the lifetime killing layer is limited to the diode cells or made as a continuous layer, the device is exemplarily irradiated with protons or Helium ions for the creation of the lifetime killing layer, followed by an anneal step.
In yet another preferred embodiment, the conductivity types are interchanged, i.e. all layers and regions of the first conductivity type are (p-), p or (p+) type, respectively and all layers and regions of the second conductivity type are (n-), n, or (n+) type.
Preferably, in all embodiments as described above, suffixes "-" and "+" after doping type indicators p, n are used to express relative net doping concentrations /Vnet, where Λ/net = Λ/D - NA for regions or layers in which a total density of donors No is larger than a total density of acceptors NA, i.e. ND > NA, and Nnei = NA - ND for regions or layers in which a total density of donors ND is smaller than a total density of acceptors NA, In particular, a net doping concentration /Vnet(n+) of an (n+)-doped region or layer is larger than a net doping concentration /Vnet(n) of an (n)-doped region or layer, which in turn is larger is larger than a net doping concentration /Vnet(n-) of an (n-)-doped region or layer. Likewise, a net doping concentration /Vnet(p+) of an (p+)-doped region or layer is larger than a net doping concentration /Vnet(p) of an (p)-doped region or layer, which in turn is larger is larger than a net doping concentration /Vnet(p-) of an (p-)-doped region or layer. Preferably, Nnet(n+)≥ /Vnet(p), Nnet(n)≥ /Vnet(p-), Nnet(p+)≥ /Vnet(n) and/or Nnet(p)≥ /Vnet(n-); most preferably, /Vnet(n+) > /Vnet(p), /Vnet(n) > /Vnet(p-), /Vnet(p+) > /Vnet(n) and/or /Vnet(p) > /Vnet(n-) also hold.
Preferably, in all embodiments as described above, where a net doping concentration of a region or layer is referred to, this is preferably to be understood as - possibly local - maximum net doping concentration within said region or layer. In particular for doped regions or layers which were formed including a dopant diffusion process step, a local net doping concentration decays in one or more spatial directions from an area with maximum net doping concentration.
Preferably, in all embodiments as described above, the bulk layer 3 is a layer of una- mended net doping concentration by the dopant diffusion process step, i.e. having the net doping concentration as achieved preferably by epitaxial growth of the bulk layer 3. Exemplarily, the bulk layer 3 has a constantly low net doping concentration /Vnet(n-). Therein, the substantially constant net doping concentration of the bulk layer 3 means that the net doping concentration is substantially homogeneous throughout the bulk layer 3, however without excluding that fluctuations in the net doping concentration within the bulk layer 3 being in the order of a factor of one to five may possibly be present due to e.g. fluctuations in the epitaxial growth process. The final bulk layer thickness and net doping concentration is chosen due to the application needs.
In all embodiments as described above, a thickness of buffer layer 8 is usually between 15μηι and 75μηι, preferably between 20μηι and 55μηι. A thickness of second cathode layer 45 is preferably between 2μηι and 30μηι, preferably 10μηι and 25μηι. A thickness of bulk layer 3 depends on a voltage class of the semiconductor device and is preferably between 350μηι and 440μηι for a 3.3kV device, and preferably between 480μηι and 570μηι for a 4.5kV device In all embodiments as described above, the term lateral refers to a direction parallel to the first main side 1 1 . In particular, lateral extension, dimension, distance etc. refers to an extension, dimension, distance, etc. in a direction or plane parallel to the first main side 1 1 . Likewise, the vertical refers to a direction perpendicular to the first main side 1 1. In particular, vertical extension, dimension, distance etc. refers to an extension, dimension, distance, etc. in a direction perpendicular to the first main side 1 1 .
It should be noted that the term "comprising" does not exclude other features, in particular elements or steps, and that the indefinite article "a" or "an" does not exclude the plural. Also elements described in association with different embodiments may be com- bined. It should also be noted that reference signs in the claims shall not be construed as limiting the scope of the claims.
These examples shall not limit the scope of the invention. The above mentioned designs and arrangements are just examples for any kinds of possible designs and arrangements for the base layer(s) and well (zones).
It will be appreciated by those skilled in the art that the present invention can be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The presently disclosed embodiments are therefore considered in all respects to be illustrative and not restricted. The scope of the invention is indicated by the appended claims rather than the foregoing description and all changes that come within the meaning and range and equivalence thereof are intended to be embraced therein.
List of Reference Numerals used in Figures r Prior art BGCT
1 Semiconductor device
10 Wafer
1 1 First main side
15 Second main side
2 Cathode electrode
25 First anode electrode
28 Second anode electrode
3 Bulk layer
3' Thyristor drift layer
3" Diode drift layer
35 Separation region
350 Homogenous separation region
351 Gate-cathode blocking region
352 Oxide
353 Metallization
4 First cathode layer
41 half part
45 Second cathode layer
451 Distributed cathode region
5 First anode layer
51 Anode short region
55 Second anode layer
6 Base layer
7 Gate electrode
75 Gate contact
8 Buffer layer
9 pilot IGCT part
91 GCT cell
96 diode cell
99 mixed IGCT / diode part

Claims

C L A I M S 1 ) A semiconductor device (1 ) comprising a semiconductor slab, in particular a semiconductor wafer (10) or semiconductor die, the semiconductor slab a) having a first main side (1 1 ) and a second main side (15), said second main side (15) being parallel to the first main side (1 1 ); and a bulk layer (3) of a first conductivity type located between the first main side (1 1 ) and the second main side (15), b) the semiconductor device further comprising i) a gate commutated thyristor cell (91 ), the gate commutated thyristor cell (91 ) comprising layers in the following order in the semiconductor slab between the first and second main side (1 1 , 15):
(1 ) a first cathode layer (4) of the first conductivity type,
(2) a base layer (6) of a second conductivity type different from the first con ductivity type,
(3) the bulk layer (3),
(4) a buffer layer (8) of the first conductivity type having a higher doping concentration than the bulk layer (3),
(5) a first anode layer (5) of the second conductivity type,
ii) the gate commutated thyristor cell (91 ) further comprising
(1 ) a GCT cathode electrode (2) arranged on the first main side on the first cathode layer (4),
(2) a gate electrode (7) arranged on - preferably lateral to the first cathode layer (4) and separated from it by - the base layer (6);
iii) a diode cell (96), the diode cell comprising layers in the following order in the semiconductor slab between the first and second main side (1 1 , 15)
(1 ) a second anode layer (55) of the second conductivity type,
(2) the bulk layer (3), and
(3) a second cathode layer (45) of the first conductivity type adjacent to the second main side (15);
(4) a diode anode electrode (28) arranged on the first main side on the second anode layer (55);
iv) a first main electrode (25) arranged on the second main side;
characterized in that C) a gate-cathode blocking region (351 ) of the first conductivity type is arranged between second anode layer (55) and base layer (6) and adjacent to the first main side (1 1 ), wherein the gate-cathode blocking region (351 ) is embedded in the bulk layer (3),
d) the gate-cathode blocking region (351 ) has a higher net doping concentration than the bulk layer (3),
e) the second anode layer (55) and base layer (6) are separated from each other by the bulk layer (3) and the gate-cathode blocking region (351 ). 2) The semiconductor device (1 ) according to claim 1 , wherein the gate-cathode
blocking region (351 ) is covered by an oxide layer (352) formed on the first main side (1 1 ).
3) The semiconductor device (1 ) according to claim 2, wherein a metallization (353) is formed on the oxide layer (352), said metallization being conductively connected the GCT cathode electrode (2).
4) The semiconductor device (1 ) according to one of the previous claims, wherein a depth of the cathode blocking region (351 ) is lower than a depth of the base layer (6); and preferably lower than a depth of the second anode layer (55).
5) The semiconductor device (1 ) according to one of the previous claims, wherein the semiconductor device comprises a plurality of gate commutated thyristor cells (91 ), a plurality of diode cells (96), and a plurality of gate-cathode blocking regions (351 ) formed between pairs of gate commutated thyristor cells (91 ) and neighboring diode cells (96).
6) The semiconductor device (1 ) according to the previous claims, wherein each gate- cathode blocking region (351 ) has a net doping concentration which is 5 to 1000 times higher than the net doping concentration of the bulk layer (3), preferably 20 to
50 times higher.
7) The semiconductor device (1 ) according to one of the previous claims, wherein each gate-cathode blocking region (351 ) has a net doping concentration greater than 1.0- 1013cnr3, preferably greater than 1.0- 1014cnr3, and smaller than
5.0- 1016cm-3.
8) The semiconductor device (1 ) according to one of the previous claims, wherein the device comprises at least one mixed part (99), in which diode cells (96) alternate with one or more gate commutated thyristor cells (91 ).
9) The semiconductor device according to one of the previous claims, wherein the device comprises at least one mixed part (99), in which the second anode layers (55) of the diode cells (96) alternate with the first cathode layers (4) of the gate commutated thyristor cells (91 ).
10) The semiconductor device (1 ) according to one of the previous claims, wherein the cathode electrode (2) and the second anode electrode (28) are constituted by a second main electrode which is provided on the first main side (1 1 ) of the semiconductor slab.
1 1 ) A reverse conducting power semiconductor module, comprising
a) a printed circuit board,
b) a semiconductor device according to one of the preceding claims arranged on said printed circuit board,
c) a gate circuit provided on said printed circuit board, said gate circuit connected by an electrically conductive connection to cathode electrodes (2) and gate electrodes (7) of each GCT cell (91 ), and configured to apply a turn-off voltage to the GCT cells (91 ) in response to an external control signal.
12) The module according to claim 1 1 , characterized in that the module is a reverse conducting integrated gate circuit thyristor (RC-IGCT) module.
PCT/EP2014/073367 2013-11-29 2014-10-30 Reverse-conducting power semiconductor device WO2015078657A1 (en)

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EP13195087.5 2013-11-29
EP13195087 2013-11-29

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CN106876452A (en) * 2017-03-07 2017-06-20 株洲中车时代电气股份有限公司 A kind of integrated gate commutated thyristor
CN111834451A (en) * 2019-04-23 2020-10-27 株洲中车时代半导体有限公司 Reverse-resistance type gate pole commutation thyristor and manufacturing method thereof
CN113809166A (en) * 2021-08-10 2021-12-17 西安理工大学 Having n+Zone-adjusting dual-mode GCT and preparation method thereof

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US6441407B1 (en) * 1998-01-09 2002-08-27 Asea Brown Boveri Ag Gate controlled thyristor driven with low-inductance
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US4791470A (en) * 1984-06-12 1988-12-13 Kabushiki Kaisha Toshiba Reverse conducting gate turn-off thyristor device
EP0643424A1 (en) * 1993-09-14 1995-03-15 Kabushiki Kaisha Toshiba Reverse conducting gate turn off thyristor
US6441407B1 (en) * 1998-01-09 2002-08-27 Asea Brown Boveri Ag Gate controlled thyristor driven with low-inductance
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106876452A (en) * 2017-03-07 2017-06-20 株洲中车时代电气股份有限公司 A kind of integrated gate commutated thyristor
CN111834451A (en) * 2019-04-23 2020-10-27 株洲中车时代半导体有限公司 Reverse-resistance type gate pole commutation thyristor and manufacturing method thereof
CN111834451B (en) * 2019-04-23 2023-04-07 株洲中车时代半导体有限公司 Reverse-resistance type gate pole commutation thyristor and manufacturing method thereof
CN113809166A (en) * 2021-08-10 2021-12-17 西安理工大学 Having n+Zone-adjusting dual-mode GCT and preparation method thereof
CN113809166B (en) * 2021-08-10 2024-05-14 西安理工大学 Having n+Dual mode GCT of adjustment region and preparation method thereof

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