WO2015064231A1 - 半導体モジュール - Google Patents

半導体モジュール Download PDF

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Publication number
WO2015064231A1
WO2015064231A1 PCT/JP2014/074484 JP2014074484W WO2015064231A1 WO 2015064231 A1 WO2015064231 A1 WO 2015064231A1 JP 2014074484 W JP2014074484 W JP 2014074484W WO 2015064231 A1 WO2015064231 A1 WO 2015064231A1
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Prior art keywords
metal foil
solder
semiconductor element
pin
semiconductor module
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PCT/JP2014/074484
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English (en)
French (fr)
Inventor
教文 山田
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富士電機株式会社
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Publication date
Application filed by 富士電機株式会社 filed Critical 富士電機株式会社
Priority to DE112014001491.5T priority Critical patent/DE112014001491T5/de
Priority to JP2015544858A priority patent/JP6149938B2/ja
Priority to CN201480020473.6A priority patent/CN105103286B/zh
Publication of WO2015064231A1 publication Critical patent/WO2015064231A1/ja
Priority to US14/878,596 priority patent/US9299637B2/en

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    • H—ELECTRICITY
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    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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    • H01L2224/29111—Tin [Sn] as principal constituent
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
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Definitions

  • the present invention relates to a semiconductor module that can improve cooling capacity in a semiconductor module using pin bonding.
  • Patent Documents 1 and 2 are known as documents disclosing semiconductor modules using pin bonding.
  • FIG. 1 of Patent Document 1 discloses a structure in which an implant pin pierced on a printed board and a semiconductor element are electrically joined.
  • Patent Document 2 discloses that a semiconductor element and a plurality of post electrodes are joined by solder.
  • Patent Documents 1 and 2 are documents that disclose a semiconductor module having a pin junction structure, which has been conceived as a measure for suppressing a peeling phenomenon between a wire frame and an electrode due to long-term use. However, since the cooling is performed from only one side of the semiconductor element, the cooling capacity is low, and it is difficult to fully exhibit the capacity of the semiconductor element.
  • an object of the present invention is to provide a semiconductor module capable of improving the cooling capacity in a semiconductor module using pin bonding.
  • the inventors have found that in a semiconductor module using pin bonding, the cooling capacity of the semiconductor module can be improved by optimizing the thickness of the solder for bonding the pin and the semiconductor element, and the present invention has been achieved.
  • a semiconductor module of the present invention includes a semiconductor element, pins electrically and thermally connected to one surface of the semiconductor element, an insulating substrate for pin wiring, and an insulating substrate for pin wiring.
  • Pin wiring board solder that joins the pin and the semiconductor element, a ceramic insulating substrate, a third metal foil disposed on the upper surface of the ceramic insulating substrate, and a fourth metal disposed on the lower surface of the ceramic insulating substrate
  • a semiconductor module comprising a DCB substrate having a foil, the third metal foil being bonded to the lower surface of the semiconductor element, and a first cooler thermally connected to the fourth metal foil.
  • H / T which is a ratio of the height H of the solder and the distance T from the semiconductor element to the first metal foil of the insulating substrate for pin wiring, is 0.2 or more; 7 or less.
  • the solder linear expansion coefficient is preferably less than 22.0 ppm / K.
  • the solder is preferably SnSb solder.
  • the SnSb solder preferably contains 13% by mass of Sb as a main component.
  • solder can be used as the solder.
  • the heat generated in the semiconductor element is transferred to both the pin wiring board that is pin-bonded to the surface of the semiconductor element by soldering and the ceramic insulating substrate that is solder-bonded to the back surface of the semiconductor element.
  • the ratio (H / T) between the solder height H and the distance T from the semiconductor element to the first metal foil is 0.2 or more and 0.7 or less. The effect can alleviate the transient phenomenon of heat transfer and suppress the temperature rise on the surface of the semiconductor element.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor module 100 according to the present invention.
  • the semiconductor module 100 includes a semiconductor element 1, a DCB substrate 2, a ceramic insulating substrate 2a, a third metal foil 2b, a fourth metal foil 2c, a solder 3a, a solder 3b, a solder 3c, a pin 4, a pin wiring substrate 5, and a pin wiring.
  • Insulating substrate 5a, first metal foil (circuit layer) 5b, second metal foil 5c, first cooler 6, first refrigerant passage 6a, fin 6b, external terminal 7a, external terminal 7b, and sealing resin 8 are provided.
  • the semiconductor element 1 is not particularly limited, but, for example, an IGBT (Insulated Gate Bipolar Transistor), a power MOSFET (Metal Oxide Semiconductor Field Transistor Transistor), or an FWD (Free Wheeling1) element, which may be one of the two semiconductor elements.
  • IGBT Insulated Gate Bipolar Transistor
  • MOSFET Metal Oxide Semiconductor Field Transistor Transistor
  • FWD Free Wheeling1
  • RB-IGBT Reverse Blocking-Insulated Gate Bipolar Transistor
  • RC-IGBT Reverse Conducting-Insulated Gate Bipolar Transistor
  • the pin wiring substrate 5 includes a pin wiring insulating substrate 5a, a first metal foil (circuit layer) 5b, and a second metal foil 5c, and is arranged so that the first metal foil (circuit layer) 5b faces the semiconductor element 1.
  • the pin wiring insulating substrate 5a is not particularly limited, but a material having a low dielectric constant and high thermal conductivity is preferable.
  • a polyimide resin or a glass epoxy resin can be used.
  • the pin wiring board 5 is not necessarily a printed board, and may be a copper thin plate, for example.
  • the first metal foil (circuit layer) 5b and the second metal foil 5c are not particularly limited, but are preferably made of a material having low electrical resistance and high thermal conductivity. For example, copper can be used.
  • the pin 4 is not particularly limited, but is preferably a metal with low electrical resistance and high thermal conductivity, specifically copper.
  • One end of the pin 4 is soldered to the upper surface of the semiconductor element 1 by the solder 3c, and the other end penetrates the pin wiring board 5 and is joined to the first metal foil (circuit layer) 5b and the second metal foil 5c. .
  • the pin 4 can be firmly fixed to the semiconductor element 1 and the pin wiring substrate 5, and the heat generated in the semiconductor element 1 can be transferred to the second metal foil 5 c via the pin 4.
  • the cooling efficiency of the module 100 can be increased.
  • the first cooler 6 is hollow inside and includes a plurality of fins 6b. A space between the fins 6b is a refrigerant passage 6a.
  • the refrigerant is not particularly limited.
  • a liquid refrigerant such as an ethylene glycol aqueous solution or water can be used, a gas refrigerant such as air can be used, or the refrigerant can be evaporated by a cooler such as Freon.
  • a phase-changeable refrigerant that cools the cooler with heat of vaporization can also be used.
  • the DCB substrate 2 includes a ceramic insulating substrate 2a, a third metal foil 2b, and a fourth metal foil 2c.
  • the third metal foil 2b is disposed on the upper surface of the ceramic insulating substrate 2a, and the fourth metal is disposed on the lower surface of the ceramic insulating substrate 2a.
  • a foil 2c is arranged.
  • the third metal foil 2 b of the DCB substrate 2 is bonded to the lower surface of the semiconductor element 1.
  • DCB is an abbreviation for Direct Copper Bonding, and a metal foil such as copper is directly bonded to a ceramic insulating substrate. Since the ceramic insulating substrate 2a is insulative, the third metal foil 2b and the fourth metal foil 2c are electrically insulated.
  • the material of the ceramic insulating substrate 2a is not particularly limited, but is preferably a material having high thermal conductivity. For example, Si 3 N 4 , AlN, or Al 2 O 3 can be used.
  • the solder 3a is electrically and thermally connected by connecting the lower surface of the semiconductor element 1 and the third metal foil 2b.
  • the solder 3 b connects the fourth metal foil 2 c of the DCB substrate 2 and the outer wall of the first cooler 6, and transfers heat transferred from the semiconductor element 1 to the DCB substrate 2 to the first cooler 6. .
  • External terminals 7a and 7b are terminals for conducting between the semiconductor element 1 and the outside, and the main power is conducted.
  • the external terminals 7a and 7b are electrically connected to the third metal foil 2b of the DCB substrate 2 by solder and are led out from the upper surface.
  • the semiconductor module 100 includes a control terminal (not shown).
  • the control terminal is a terminal for controlling the semiconductor element 1, and the semiconductor element 1 is controlled from the outside.
  • the sealing resin 8 is illustrated in a bonding surface between the first cooler 6 of the semiconductor module 100 and the fourth metal foil 2c of the first cooler 6, and a region led out of the external terminals 7a and 7b. It is sealed with a sealing resin except for a region led to the outside of the control terminals that are not.
  • the sealing resin 8 is not particularly limited as long as it has a predetermined insulating performance and good moldability. For example, an epoxy resin is preferably used.
  • the semiconductor module shown in FIG. 1 has only one semiconductor element, but may have a structure including a plurality of pairs of semiconductor elements 1 and pins 4.
  • the rated output that can be processed by the semiconductor module can be increased.
  • the types of the plurality of semiconductor elements 1 may be changed to different types of semiconductor elements. For example, an IGBT and FWD may be connected in parallel.
  • the pin 4 is soldered to the upper surface of the semiconductor element 1 by solder 3c.
  • a gap is provided between the surface of the solder 3 c and the first metal foil (circuit layer) 5 b of the pin wiring substrate 5.
  • the height of the solder is H
  • the distance from the semiconductor element to the first metal foil of the insulating substrate for pin wiring is T.
  • the solder may go up around the pin.
  • the solder height H is the height from the interface between the semiconductor element and the solder to the lowermost surface of the upper surface of the solder.
  • the solder height H is the height from the interface between the semiconductor element and the solder to the lowermost surface of the upper surface of the solder between the pins.
  • the ratio H / T between the height H of the solder and the distance T from the semiconductor element to the first metal foil of the insulating substrate for pin wiring is 0.2 or more, 0 .7 or less is preferable. If H / T is less than 0.2, the heat storage effect of the solder in the transient heat state is not sufficient, and the semiconductor element maximum temperature Tj exceeds the safe temperature range. If it is higher than 0.7, the stress applied to the semiconductor element becomes too large, and some of them break in high temperature operation tests and thermal cycle tests.
  • H / T which is a ratio between the solder height H and the distance T from the semiconductor element to the first metal foil of the insulating substrate for pin wiring, is 0.2 or more, Since it is in the range of 0.7 or less, the semiconductor element maximum temperature Tj in the transient heat state can be reduced by the heat storage effect of the solder, and the stress to the semiconductor element can be reduced.
  • the H / T is more preferably in the range of 0.26 or more and 0.53 or less. According to such a configuration, the cooling capacity of the semiconductor module can be further improved, the stress applied to the semiconductor element can be reduced, and the life of the semiconductor module can be improved.
  • the solder has a linear expansion coefficient of less than 22.0 ppm / K. Furthermore, it is more preferable that the linear expansion coefficient of the solder is 21.2 ppm / K or less.
  • the linear expansion coefficient of the solder is 22.0 ppm / K or more, when the semiconductor element generates heat, thermal stress is generated due to the difference in linear expansion coefficient between the pin and the solder, and the thermal stress is easily applied to the semiconductor element.
  • the linear expansion coefficient of the solder can be brought close to the linear expansion coefficient of the pin, and the thermal stress applied to the semiconductor element can be reduced.
  • the material of the pin is not particularly limited as long as it has a high thermal conductivity and is closer to the linear expansion coefficient of the solder, but it is desirable to use copper having a high thermal conductivity.
  • SnSb solder or SnAg solder can be preferably used as the solder.
  • the main component of SnSb solder is desirably Sn13Sb. Since Sn13Sb solder has a linear expansion coefficient of 21.2 ppm / K or less, it can reduce the thermal stress applied to the semiconductor element.
  • FIG. 2 shows the relationship between the solder height H and the semiconductor element maximum temperature Tj. It can be seen that the higher the solder height H, the lower the semiconductor element maximum temperature Tj during the operation of the semiconductor element 1.
  • FIG. 3 is a graph showing the relationship between the solder height and the reduction rate of the semiconductor element maximum temperature Tj obtained by conversion from FIG. It can be seen that increasing the solder height H has a temperature reduction effect of a little over 9%.
  • FIG. 4 is a diagram showing the relationship between the solder height H and the stress applied to the semiconductor element 1. It can be seen that when the solder height H is increased, the chip stress increases and exceeds 240 MPa.
  • FIG. 5 is a diagram showing the relationship between the solder height ratio H / T and the reduction rate of the semiconductor element maximum temperature Tj
  • FIG. 6 shows the solder height ratio H / T and the reduction rate of the stress applied to the semiconductor element 1. It is a figure which shows a relationship.
  • the solder height ratio H / T is 0.2 or more
  • the semiconductor element maximum temperature Tj can be reduced by 2% or more
  • the safe temperature range can be expanded by 4 ° C.
  • the solder height ratio H / T is 0.7 or less, the stress can be reduced by 6% or more, and the failure rate is improved in the high temperature operation test.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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Abstract

　ピン接合を利用した半導体モジュールの冷却能力を向上させる。　半導体素子１に接続されたピン４と、上下面に第２金属箔５ｃ、第１金属箔５ｂを備えており、かつ第１金属箔５ｂと第２金属箔５ｃとピン４とが電気的に接合しているピン配線基板５と、ピン４と半導体素子１を接合したハンダ３ｃと、上下面に第３金属箔２ｂ、第４金属箔２ｃを備えており、第３金属箔２ｂが半導体素子１の下面に接合されているＤＣＢ基板２と、第４金属箔２ｃに接続された第１冷却器６とを備えた半導体モジュールであって、ハンダの高さＨと、半導体素子１から第１金属箔５ｂまでの間の距離Ｔとの比であるＨ／Ｔが０．２以上、０．７以下の範囲内である。

Description

半導体モジュール
　本発明は、ピン接合を利用した半導体モジュールにおいて、冷却能力を向上できる半導体モジュールに関する。
　ピン接合を利用した半導体モジュールを開示した文献として、次の特許文献１、２の半導体モジュールが知られている。
　特許文献１の図１には、プリント基板に突き刺されたインプラントピンと半導体素子とを電気的に接合した構造が開示されている。
　特許文献２の図７、８、１１には、半導体素子と複数のポスト電極がハンダで接合されていることが開示されている。
ＷＯ２０１１/０８３７３７号公報 特開２００９－６４８５２号公報
　特許文献１や２は、長期間の使用によりワイヤーフレームと電極との間の剥離現象を抑制する対策として考え出されたピン接合構造の半導体モジュールを開示する文献であるが、該半導体モジュールの構造は、冷却を半導体素子の片面のみから行う構造のため冷却能力が低く、半導体素子の能力を十分に発揮させることが難しいという問題点があった。
　上記の課題を解決するべく、本発明は、ピン接合を利用した半導体モジュールにおいて、冷却能力を向上できる半導体モジュールを提供することを目的とする。
　発明者は、ピン接合を利用した半導体モジュールにおいて、ピンと半導体素子を接合するハンダの厚さを最適化することで、半導体モジュールの冷却能力が向上できることを見出し、本発明に至った。
　上記課題を解決するため、本発明の半導体モジュールは、半導体素子と、前記半導体素子の一方の面に電気的および熱的に接続されたピンと、ピン配線用絶縁基板、前記ピン配線用絶縁基板の下面に配置した第１金属箔、および前記ピン配線用絶縁基板の上面に配置した第２金属箔を備えており、かつ前記第１金属箔と前記第２金属箔と前記ピンとが電気的に接合しているピン配線基板と、前記ピンと前記半導体素子を接合したハンダと、セラミック絶縁基板、前記セラミック絶縁基板の上面に配置した第３金属箔、および前記セラミック絶縁基板の下面に配置した第４金属箔を備えており、前記第３金属箔が前記半導体素子の下面に接合されているＤＣＢ基板と、前記第４金属箔に熱的に接続された第１冷却器とを備えた半導体モジュールであって、前記ハンダの高さＨと、前記半導体素子から前記ピン配線用絶縁基板の前記第１金属箔までの間の距離Ｔとの比であるＨ／Ｔが０．２以上、０．７以下であることを特徴とする。
　本発明の半導体モジュールにおいて、ハンダの線膨張係数は２２．０ｐｐｍ／Ｋ未満であることが好ましい。
　本発明の半導体モジュールにおいて、前記ハンダはＳｎＳｂ系ハンダであることが好ましい。
　本発明の半導体モジュールにおいて、前記ＳｎＳｂ系ハンダは、主成分としてＳｂを１３質量％含有することが好ましい。
　また、本発明の半導体モジュールにおいて、前記ハンダとしてＳｎＡｇ系ハンダを用いることができる。
　本発明によれば、半導体素子で発生する熱を、半導体素子表面にハンダ付けによってピン接合したピン配線基板、及び半導体素子裏面にハンダ接合したセラミック絶縁基板の両方に伝熱することによって、冷却能力を高めることができる。また、前記ピン接合において、ハンダ高さＨと半導体素子から第１金属箔までの間の距離Ｔとの比（Ｈ／Ｔ）を０．２以上０．７以下としたことにより、ハンダの蓄熱効果によって伝熱の過渡現象を緩和し、半導体素子表面の温度上昇を抑制できる。
本発明の一実施形態に係る半導体モジュールの断面模式図である。 ハンダ高さと半導体素子最高温度Ｔｊの関係を示す図である。 ハンダ高さと半導体素子最高温度Ｔｊの低減率の関係を示す図である。 ハンダ高さと半導体素子にかかる応力の関係を示す図である。 ハンダ高さ比と半導体素子最高温度Ｔｊの低減率の関係を示す図である。 ハンダ高さ比と半導体素子にかかる応力の低減率の関係を示す図である。
　以下、図面を参照しながら本発明に係る半導体モジュールの実施形態を説明する。同一の構成要素については、同一の符号を付け、重複する説明は省略する。なお、本発明は、下記の実施形態に限定されるものではなく、その要旨を変更しない範囲内で適宜変形して実施することができるものである。
　まず、半導体モジュールの構造について説明する。
　図１には本発明による半導体モジュール１００の断面模式図が示されている。半導体モジュール１００は、半導体素子１、ＤＣＢ基板２、セラミック絶縁基板２ａ、第３金属箔２ｂ、第４金属箔２ｃ、ハンダ３ａ、ハンダ３ｂ、ハンダ３ｃ、ピン４、ピン配線基板５、ピン配線用絶縁基板５ａ、第１ 金属箔(回路層)５ｂ、第２金属箔５ｃ、第１冷却器６、第１冷媒通路６ａ、フィン６ｂ、外部端子７ａ、外部端子７ｂ、封止樹脂８を備える。
　半導体素子１は、特に限定されないが、例えば、ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）やパワーＭＯＳＦＥＴ（Ｍｅｔａｌ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）やＦＷＤ（Ｆｒｅｅ　Ｗｈｅｅｌｉｎｇ　Ｄｉｏｄｅ）であってもよく、これらを１つの半導体素子の中で縦方向に形成されたＲＢ－ＩＧＢＴ（Ｒｅｖｅｒｓｅ　Ｂｌｏｃｋｉｎｇ－Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）やＲＣ－ＩＧＢＴ（Ｒｅｖｅｒｓｅ　Ｃｏｎｄｕｃｔｉｎｇ－Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）であってもよい。
　ピン配線基板５は、ピン配線用絶縁基板５ａ、第１金属箔（回路層）５ｂ、第２金属箔５ｃからなり、第１金属箔（回路層）５ｂが半導体素子１に対向するように配置されている。ピン配線用絶縁基板５ａは、特に限定されないが、誘電率が低く、熱伝導率の高い材料が好ましく、例えばポリイミド樹脂やガラスエポキシ樹脂を使用することができる。なお、ピン配線用基板５は必ずしもプリント基板である必要はなく、例えば銅の薄板であっても良い。第１金属箔（回路層）５ｂと第２金属箔５ｃは、特に限定されないが、電気抵抗が低く、熱伝導率の高い材料が好ましく、例えば銅を使用することができる。
　ピン４は、特に限定されないが、電気抵抗が低く熱伝導率が高い金属、具体的には銅が好ましい。ピン４の一端はハンダ３ｃによって半導体素子１の上面にハンダ接合され、他端はピン配線基板５を貫通して、第１金属箔(回路層)５ｂ及び第２金属箔５ｃに接合されている。上記構造によれば、ピン４を半導体素子１及びピン配線基板５に強固に固定でき、半導体素子１で発生する熱はピン４を介して第２金属箔５ｃに熱を伝えることができ、半導体モジュール１００の冷却効率を高めることができる。また、ピン４は、１つの半導体素子１に対して複数のピンを配置することが好ましい。こうすることによって、電気抵抗を減らすと共に、熱伝導性能を向上できる。
　第１冷却器６は、内部が空洞であり、複数のフィン６ｂを備えている。フィン６ｂの間が冷媒通路６ａになっている。冷媒としては、特に限定されないが、例えば、エチレングリコール水溶液や水などの液体冷媒を用いることもできるし、空気のような気体冷媒を用いることもできるし、フロンのように冷却器で蒸発して気化熱で冷却器を冷やす相変化可能な冷媒を用いることもできる。
　ＤＣＢ基板２は、セラミック絶縁基板２ａと第３金属箔２ｂと第４金属箔２ｃからなり、セラミック絶縁基板２ａの上面に第３金属箔２ｂが配置され、セラミック絶縁基板２ａの下面に第４金属箔２ｃが配置されている。ＤＣＢ基板２の第３金属箔２ｂは、半導体素子１の下面に接合されている。ＤＣＢとは、Ｄｉｒｅｃｔ　Ｃｏｐｐｅｒ　Ｂｏｎｄｉｎｇの略であり、セラミック絶縁基板に銅などの金属箔が直接接合されている。セラミック絶縁基板２ａが絶縁性のため、第３金属箔２ｂと第４金属箔２ｃとは電気的に絶縁されている。なお、セラミック絶縁基板２ａの材質は、特に限定されないが、熱伝導率の高い材料であることが好ましく、例えばＳｉ３Ｎ４、ＡｌＮ、Ａｌ２Ｏ３を用いることができる。
　ハンダ３ａは、半導体素子１の下面と第３金属箔２ｂを接続して電気的および熱的に接続している。ハンダ３ｂは、ＤＣＢ基板２の第４金属箔２ｃと第１冷却器６の外壁とを接続しており、半導体素子１からＤＣＢ基板２に伝わった熱を第１冷却器６に伝熱している。
　外部端子７ａ、７ｂは、半導体素子１と外部との間を導通させる端子であり、主電力が導通される。外部端子７ａ、７ｂは、ＤＣＢ基板２の第３金属箔２ｂにハンダで電気的に接続され、上面から外部に導出されている。半導体モジュール１００は、図示していない制御端子を備えている。制御端子は、半導体素子１を制御するための端子であり、外部から半導体素子１が制御される。
　封止樹脂８は、半導体モジュール１００の第１冷却器６、及び第１冷却器６の第４金属箔２ｃとの接合面と、外部端子７ａ，７ｂの外部に導出される領域と、図示していない制御端子の外部に導出される領域とを除いて封止樹脂で封止されている。封止樹脂８は、所定の絶縁性能があり、成形性がよいものであれば特に限定されないが、例えば、エポキシ樹脂などが好適に用いられる。
　図１に示した半導体モジュールは半導体素子を１個しか持たないが、半導体素子１、ピン４の組を複数備えている構造にしてもよい。半導体素子１を複数並列接続で並べることで半導体モジュールの処理できる定格出力を増加できる。また、複数の半導体素子１の種類をそれぞれ異なる種類の半導体素子に変えてもよい。例えば、ＩＧＢＴとＦＷＤを並列接続にする構造としてもよい。
　次に、半導体素子１とピン４との接合部の詳細、及びその作用効果について説明する。
　ピン４は、半導体素子１の上面にハンダ３ｃによってハンダ接合されている。ハンダ３ｃの表面と、ピン配線基板５の第１金属箔（回路層）５ｂとの間には、間隙が設けられている。
　ここでハンダの高さをＨとし、半導体素子からピン配線用絶縁基板の前記第１金属箔までの間の距離をＴとする。ピンとハンダとの界面の端の部分は、ハンダがピンの周囲に上がる場合がある。前記ハンダの高さＨとは、前記半導体素子とハンダとの界面から前記ハンダの上面の最下面までの高さのことである。前記ピンが複数存在するときには、前記ハンダの高さＨとは、前記半導体素子とハンダとの界面からピンとピンの間のハンダの上面の最下面までの高さのことである。
　本願の半導体モジュールにおいて、前記ハンダの高さＨと、前記半導体素子から前記ピン配線用絶縁基板の前記第１金属箔までの間の距離Ｔとの比Ｈ／Ｔは、０．２以上、０．７以下であることが好ましい。Ｈ／Ｔが０．２未満だと過渡熱状態における前記ハンダの蓄熱効果が十分でなく、半導体素子最高温度Ｔｊが安全温度範囲を超えてしまう。０．７より高いと半導体素子へかかる応力が大きくなり過ぎ、高温動作試験や熱サイクル試験で破壊するものがあらわれる。
　このような構成によれば、ハンダの高さＨと、前記半導体素子から前記ピン配線用絶縁基板の前記第１金属箔までの距離Ｔとの比であるＨ／Ｔが、０．２以上、０．７以下の範囲内であるため、前記ハンダの蓄熱効果で過渡熱状態での半導体素子最高温度Ｔｊを低減することができ、かつ、半導体素子への応力を低減できる。
　また、上記の半導体モジュールにおいて、前記Ｈ／Ｔが０．２６以上、０．５３以下の範囲内であることがより望ましい。このような構成によれば、半導体モジュールの冷却能力をより向上でき、半導体素子にかかる応力も低減でき、半導体モジュールの寿命を向上できる。
　また、上記の半導体モジュールにおいて、前記ハンダの線膨張係数が２２．０ｐｐｍ／Ｋ未満であることが望ましい。さらに、前記ハンダの線膨張係数が２１．２ｐｐｍ／Ｋ以下であることがより望ましい。ハンダの線膨張係数が２２．０ｐｐｍ／Ｋ以上の場合、半導体素子が発熱した際に、ピンとハンダとの線膨張係数の違いによって熱応力が発生し、半導体素子に熱応力が加わり易くなる。
　このような構成によれば、ハンダの線膨張係数をピンの線膨張係数に近づけることができ、半導体素子にかかる熱応力を低減できる。ピンの材質は、熱伝導率が高くハンダの線膨張係数により近い金属であれば特に限定されないが、熱伝導率の高い銅を用いることが望ましい。前記ハンダは、具体的にはＳｎＳｂ系ハンダやＳｎＡｇ系ハンダを好適に用いることができる。ＳｎＳｂ系ハンダは、主成分がＳｎ１３Ｓｂであることが望ましい。Ｓｎ１３Ｓｂハンダは、線膨張係数が２１．２ｐｐｍ／Ｋ以下であるので半導体素子にかかる熱応力を低減できる。
　本発明の作用効果は、熱シミュレーションおよび熱応力シミュレーションによって検証することができる。以下、図１に示される半導体モジュールのシミュレーション結果について説明する。
　図２に、ハンダ高さＨと半導体素子最高温度Ｔｊの関係を示す。ハンダ高さＨが高いほど半導体素子１の動作時の半導体素子最高温度Ｔｊを低減できることがわかる。
　図３は、図２から換算して得られる、ハンダ高さと半導体素子最高温度Ｔｊの低減率の関係を示す図である。ハンダ高さＨを増やすことで最大９％強の温度低減効果があることがわかる。
　図４は、ハンダ高さＨと半導体素子１にかかる応力の関係を示す図である。ハンダ高さＨを高くするとチップ応力が増加し、２４０ＭＰａを超えることがわかる。
　図５は、ハンダ高さ比Ｈ／Ｔと半導体素子最高温度Ｔｊの低減率の関係を示す図であり、図６は、ハンダ高さ比Ｈ／Ｔと半導体素子１にかかる応力の低減率の関係を示す図である。ハンダ高さ比Ｈ／Ｔが０．２以上では、半導体素子最高温度Ｔｊを２％以上低減することができ、安全温度範囲を４℃拡大することができる。また、ハンダ高さ比Ｈ／Ｔが０．７以下では、応力を６％以上低減することができ、高温動作試験で故障率が改善される。
　以上のように、本発明の実施例によれば、ピン接合を利用した半導体モジュールにおいて、冷却能力を向上できる半導体モジュールを提供できる。
１ 半導体素子
２ ＤＣＢ基板
２ａ セラミック絶縁基板
２ｂ 第３金属箔
２ｃ 第４金属箔
３ａ，３ｂ，３ｃ ハンダ
４ ピン
５ ピン配線基板
５ａ ピン配線用絶縁基板
５ｂ 第１金属箔(回路層)
５ｃ 第２金属箔
６ 第１冷却器
６ａ 第１冷媒通路
６ｂ フィン
７ａ，７ｂ 外部端子
８ 封止樹脂
１００ 半導体モジュール

Claims (5)

  1. 　半導体素子と、
    　前記半導体素子の一方の面に電気的および熱的に接続されたピンと、
    　ピン配線用絶縁基板、前記ピン配線用絶縁基板の下面に配置した第１金属箔、および前記ピン配線用絶縁基板の上面に配置した第２金属箔を備えており、かつ前記第１金属箔と前記第２金属箔と前記ピンとが電気的に接合しているピン配線基板と、
    　前記ピンと前記半導体素子を接合したハンダと、
    　セラミック絶縁基板、前記セラミック絶縁基板の上面に配置した第３金属箔、および前記セラミック絶縁基板の下面に配置した第４金属箔を備えており、前記第３金属箔が前記半導体素子の下面に接合されているＤＣＢ基板と、
    　前記第４金属箔に熱的に接続された第１冷却器と、
    を備えた半導体モジュールであって、
    　前記ハンダの高さＨと、前記半導体素子から前記ピン配線用絶縁基板の前記第１金属箔までの間の距離Ｔとの比であるＨ／Ｔが０．２以上、０．７以下の範囲内であることを特徴とする半導体モジュール。
  2. 　前記ハンダの線膨張係数が２２．０ｐｐｍ／Ｋ未満である請求項１に記載の半導体モジュール。
  3. 　前記ハンダは、ＳｎＳｂ系ハンダである請求項１又は２に記載の半導体モジュール。
  4. 　前記ＳｎＳｂ系ハンダは、主成分としてＳｂを１３質量％含有する請求項３に記載の半導体モジュール。
  5. 　前記ハンダは、ＳｎＡｇ系ハンダである請求項１又は２に記載の半導体モジュール。
PCT/JP2014/074484 2013-10-30 2014-09-17 半導体モジュール WO2015064231A1 (ja)

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DE102016218207A1 (de) * 2016-09-22 2018-03-22 Robert Bosch Gmbh Elektronische Baugruppe, insbesondere eine elektronische Leistungsbaugruppe für Hybridfahrzeuge oder Elektrofahrzeuge
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