WO2015058435A1 - 阵列基板及3d显示设备 - Google Patents

阵列基板及3d显示设备 Download PDF

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Publication number
WO2015058435A1
WO2015058435A1 PCT/CN2013/087351 CN2013087351W WO2015058435A1 WO 2015058435 A1 WO2015058435 A1 WO 2015058435A1 CN 2013087351 W CN2013087351 W CN 2013087351W WO 2015058435 A1 WO2015058435 A1 WO 2015058435A1
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WIPO (PCT)
Prior art keywords
thin film
film transistor
pixel electrode
scan
line
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PCT/CN2013/087351
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English (en)
French (fr)
Inventor
陈政鸿
姜佳丽
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深圳市华星光电技术有限公司
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Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to KR1020167005021A priority Critical patent/KR20160036601A/ko
Priority to GB1604516.3A priority patent/GB2534064A/en
Priority to EA201690506A priority patent/EA031144B1/ru
Priority to JP2016519735A priority patent/JP6340072B2/ja
Priority to US14/234,426 priority patent/US20150109272A1/en
Publication of WO2015058435A1 publication Critical patent/WO2015058435A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/001—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background
    • G09G3/003—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background to produce spatial visual effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2014—Display of intermediate tones by modulation of the duration of a single pulse during which the logic level remains constant

Definitions

  • the present invention relates to the field of 3D display technologies, and in particular, to an array substrate and a 3D display device.
  • a common technique used by 3D Shutter Glass is to insert a backlit scan mode for black screens (Black) Insertion, BLU Blinking Mode), when the black screen is inserted, it is usually controlled by the TCON (Timing Controller) or SD (Converter) of the 3D display, which is realized by inserting a black screen when the left and right eye signals are switched, for example, After the end of the right eye frame, a black frame is inserted, and then the left eye frame is scanned.
  • TCON Transmission Controller
  • SD Converter
  • the present invention provides an array substrate and a 3D display device to solve the 3D display technology in which the black screen is inserted into the backlight scanning mode in the prior art, and only a gray scale image can be displayed, resulting in poor image quality in high brightness display. problem.
  • the present invention constructs an array substrate comprising a data line extending in a column direction and a common electrode line and a scan line extending in a row direction, the data line and the scan line being vertically interlaced, arranged in a matrix, and formed a plurality of pixel units including a pixel electrode, a first thin film transistor, and a second thin film transistor;
  • the scan line includes a first scan line connected to the pixel electrode through the first thin film transistor, and a second scan line connected through the second thin film transistor Pixel electrode
  • the first scan line is configured to transmit a first scan signal to turn on the first thin film transistor
  • the data line is configured to supply a pixel electrode voltage to the pixel electrode through the thin film transistor after the first thin film transistor is turned on, and charge the pixel electrode;
  • the second scan line is configured to transmit a second scan signal after the data line charges the pixel electrode to open the second thin film transistor
  • the common electrode line is configured to provide a common voltage to the pixel electrode through the second thin film transistor after the second thin film transistor is turned on to pull the pixel electrode voltage to the common voltage;
  • the duration of the second scan signal of the second scan line is a predetermined time to pull the voltage of the pixel electrode to a different level.
  • the embodiment of the present invention further constructs a 3D display device, including an array substrate, the array substrate includes a data line extending in a column direction and a common electrode line and a scan line extending in a row direction, The data line and the scan line are vertically interlaced, arranged in a matrix, and form a plurality of pixel units, wherein the pixel unit includes a pixel electrode, a first thin film transistor and a second thin film transistor;
  • the scan line includes a first scan line connected to the pixel electrode through the first thin film transistor, and a second scan line connected through the second thin film transistor Pixel electrode
  • the first scan line is configured to transmit a first scan signal to turn on the first thin film transistor
  • the data line is configured to supply a pixel electrode voltage to the pixel electrode through the thin film transistor after the first thin film transistor is turned on, and charge the pixel electrode;
  • the second scan line is configured to transmit a second scan signal after the data line charges the pixel electrode to open the second thin film transistor
  • the common electrode line is configured to provide a common voltage to the pixel electrode through the second thin film transistor after the second thin film transistor is turned on to pull the pixel electrode voltage to the common voltage;
  • the duration of the second scan signal of the second scan line is a predetermined time to pull the voltage of the pixel electrode to a different level.
  • the pixel electrode is charged, and then the corresponding thin film transistor is turned on by the second scan line to start the pixel.
  • the electrode applies a common voltage to achieve the effect of inserting a gray scale picture
  • the embodiment of the present invention controls the duration of the second scan signal of the second scan line, and pulls the voltage of the pixel electrode to different levels to achieve different gray scale brightness.
  • FIG. 1 is a schematic view showing the effect of a preferred embodiment of an array substrate in the present invention
  • 2A is a driving waveform diagram of the first scan line and the second scan line in one embodiment of the present invention
  • 2B is a driving waveform diagram of the first scan line and the second scan line according to another embodiment of the present invention.
  • 2C is a schematic diagram of a time corresponding to inserting a grayscale picture
  • 3A-3C are schematic diagrams showing the effects of an embodiment of the present invention.
  • FIG. 1 is a schematic view showing the effect of a preferred embodiment of the array substrate of the present invention.
  • the array substrate includes data lines 11 extending in the column direction A, and further includes a common electrode line 12, a first scan line 13, and a second scan line 14 extending in the row direction B.
  • the data line 11 and the first scan line 13 and the second scan line 14 are vertically interlaced with each other, arranged in a matrix, and a plurality of pixel units 20 are formed.
  • FIG. 1 only shows one of the pixels. The structure of more pixel units is similar to that of Figure 1, and will not be repeated here.
  • the pixel unit 20 includes a first thin film transistor 21 , a second thin film transistor 22 , a liquid crystal capacitor CLC and a storage capacitor CST , and of course, a pixel electrode 23 , the pixel electrode shown in FIG. 1 . 23 is only an effect diagram. In a specific implementation, the pixel electrode 23 is a layer structure parallel to the array substrate.
  • the first scan line 13 is connected to the pixel electrode 23 through the first thin film transistor 21, and the second scan line 14 is connected to the pixel electrode 23 through the second thin film transistor 22.
  • the first thin film transistor 21 includes a first gate G1, a first source S1, and a first drain D1.
  • the first gate G1 of the first thin film transistor 21 is electrically connected.
  • the first scan line 131, the first source S1 of the first thin film transistor 21 is electrically connected to the data line 11, and the first drain D1 of the first thin film transistor 21 is electrically connected to the pixel electrode 23.
  • the second thin film transistor 22 includes a second gate G2, a second source S2, and a second drain D2, and the second gate G2 of the second thin film transistor 22 is electrically connected to the first a second scan line 14, the second source S2 of the second thin film transistor 22 is electrically connected to the common electrode line 12, and the second drain D2 of the second thin film transistor 22 is electrically connected to the pixel electrode twenty three.
  • the first scan line 13 is configured to transmit a first scan signal to turn on the first gate G1 of the first thin film transistor 21, wherein the first scan signal is, for example, from a gate.
  • the driver chip (not shown).
  • the data line 11 supplies a pixel voltage to the pixel electrode 23 through the first thin film transistor 21, and charges the pixel electrode 23 to display a corresponding left-eye pixel or right-eye pixel.
  • the pixel electrode 23 is in a state of charge retention, at which time the second scan line 14 transmits a second scan signal to turn on the second gate G2 of the second thin film transistor 22, and the common electrode
  • the line 12 then supplies a common voltage to the pixel electrode 23 through the second thin film transistor 22 to pull the voltage of the pixel electrode 23 to the common voltage.
  • the duration of the second scan line 14 is a predetermined time to pull the voltage of the pixel electrode 23 to a different level, thereby implementing gray scale picture insertion of different brightness.
  • FIG. 2A is a driving waveform diagram of the first scan line 13 and the second scan line 14 in one embodiment of the present invention
  • FIG. 2B is a diagram of another embodiment of the present invention.
  • Driving waveform diagrams of the first scan line 13 and the second scan line 14, and FIG. 2C is a timing diagram corresponding to the insertion of the gray scale screen.
  • the first scan line 13 transmits a first scan signal to open the first gate G1 of the first thin film transistor 21, and the data line 11 supplies a voltage to the pixel electrode 23 through the opened first thin film transistor 21.
  • the pixel electrode 23 is charged to turn on the corresponding left eye pixel (Left) or right eye pixel (Right).
  • the pixel electrode 23 After the end of charging, that is, after the corresponding left eye pixel (Left) or right eye pixel (Right) is turned on, the pixel electrode 23 is in a power retention state, and at this time, the second scan line 14 transmits a second scan signal to open the location.
  • the second gate G2 of the second thin film transistor 22, the common electrode line 12 supplies a common voltage to the pixel electrode 23 through the second thin film transistor 22 that has been opened to pull the voltage of the pixel electrode 23 to the common Voltage, the effect of inserting a grayscale picture (Black).
  • the first scan signal has a first scan period T1
  • the second scan signal has a second scan period T2.
  • the second scan signal continues for a predetermined time t1, the range of the predetermined time t1 being between 0 and T2.
  • the second scan signal continues during the second scan period T2.
  • a predetermined time t2 the predetermined time t2 ranges between 0 and T2, obviously, t2> T1.
  • the common voltage input by the common electrode line 12 can pull the voltage of the pixel electrode 23 to different levels with the change of the predetermined time t1, t2, ..., thereby achieving different brightness. The insertion of the grayscale picture.
  • the embodiment of the present invention adjusts the brightness of the inserted picture by controlling the duration of the second scanning signal (predetermined time).
  • the principle of the invention adjusting the brightness of the inserted picture by controlling the duration of the second scanning signal Gate2 is:
  • the first scan line 13 transmits a first scan signal to open the first gate G1 of the first thin film transistor 21, and the data line 11 supplies a voltage to the pixel electrode 23 through the opened first thin film transistor 21.
  • the pixel electrode 23 is charged, and at the end of charging, the pixel electrode 23 is in a state of charge retention, at this time, on both sides of the second thin film transistor 22, the pixel electrode voltage of the pixel electrode 23 and the common electrode
  • the embodiment of the present invention can adjust the grayscale brightness of the inserted picture by controlling the length of time when the second gate G2 of the second thin film transistor 22 is turned on, that is, by controlling the duration of the second scan signal (predetermined The difference in time) pulls the voltage (Vpixel) of the pixel electrode 23 to a different level to achieve insertion of a picture of different gray level brightness, not just a black picture.
  • the second scan period T2 of the second scan signal and the second scan period T1 of the second scan line are preferably equal, and the second scan line 14 is preferably at (T1) of the first scan signal.
  • the second scan signal is transmitted at time /2, and it is of course also possible to transmit the second scan signal at other times, which are all within the protection scope of the present invention.
  • FIG. 3A-3C are schematic diagrams of effects according to an embodiment of the present invention, wherein L1 is a pixel electrode voltage when a black screen is simply inserted, and L2 is a predetermined time for controlling the second scan signal in the embodiment of the present invention.
  • t horizontal axis
  • the voltage Vpixel of the pixel electrode 23 is apparent.
  • the voltage Vpixel (vertical axis) of the pixel electrode 23 exhibits different values, that is, gray scales showing different brightnesses.
  • the embodiment of the present invention further provides a 3D display device, which includes the array substrate provided by the embodiment of the present invention. Since the array substrate has been described in detail above, it will not be described herein.
  • the pixel electrode is charged by setting the first scan line and the second scan line, and then the corresponding thin film transistor is turned on by the second scan line to start the pixel.
  • the electrode applies a common voltage to achieve the effect of inserting a gray scale picture
  • the embodiment of the present invention controls the duration of the second scan signal of the second scan line, and pulls the voltage of the pixel electrode to different levels to achieve different gray scale brightness. The insertion of the picture, not just the insertion of a black picture.

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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
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Abstract

一种阵列基板及3D显示设备。阵列基板包括第一薄膜晶体管（21）、第二薄膜晶体管（22）、第一扫描线（13）和第二扫描线（14）。首先通过第一扫描线（13）打开第一薄膜晶体管（21）对像素电极（23）进行充电，之后通过第二扫描线（14）打开第二薄膜晶体管（22）开始对像素电极（23）施加公共电压，以实现***灰阶画面的效果。该3D显示设备控制第二扫描线（14）的第二扫描信号的持续时间，将像素电极（23）的电压拉至不同准位，以实现不同灰阶亮度的画面的***，而并非只是***黑画面。

Description

阵列基板及3D显示设备 技术领域
本发明涉及3D显示技术领域，特别是涉及一种阵列基板及3D显示设备。
 背景技术
随着3D应用的不断普及推广，对3D技术的要求越来越高。
3D的快门（Shutter Glass）常用的一种技术为黑画面***背光扫描模式（Black Insertion，BLU Blinking Mode），此种3D技术在***黑画面时，通常由3D显示器的TCON（时序控制器）或SD（转换器）进行控制，其是通过在左右眼信号切换时***黑画面来实现，例如在右眼帧结束之后，***一帧黑画面，然后进行左眼帧的扫描。
但是由于该技术只能***黑画面，即只能显示一种亮度的灰阶画面（纯黑），不能根据3D（3D Mode）模式的不同而显示不同亮度的画面，限制了3D显示技术的发展，譬如在需要高亮度的灰阶画面时，此时若仍只是***黑画面，则将导致整个3D显示画质不佳，譬如亮度偏低。
因此，需解决现有技术存在的上述技术问题。
 技术问题
本发明提供一种阵列基板及3D显示设备，以解决现有技术中黑画面***背光扫描模式的3D显示技术，只能显示一种灰阶画面，导致在高亮度显示时画质不佳的技术问题。
 技术解决方案
本发明构造了一种阵列基板，包括沿列方向延伸的数据线以及沿行方向延伸的公共电极线和扫描线，所述数据线和所述扫描线相互垂直交错，呈矩阵式排列，并形成多个像素单元，所述像素单元内包括有像素电极、第一薄膜晶体管和第二薄膜晶体管；
所述扫描线包括第一扫描线和第二扫描线，所述第一扫描线通过所述第一薄膜晶体管连接所述像素电极，所述第二扫描线通过所述第二薄膜晶体管连接所述像素电极；
其中所述第一扫描线，用于传输第一扫描信号，以打开所述第一薄膜晶体管；
所述数据线，用于在所述第一薄膜晶体管打开后，通过所述薄膜晶体管提供像素电极电压至所述像素电极，对所述像素电极充电；
所述第二扫描线，用于在所述数据线对所述像素电极充电后，传输第二扫描信号，以打开所述第二薄膜晶体管；
所述公共电极线，用于在所述第二薄膜晶体管打开后，通过所述第二薄膜晶体管提供公共电压至所述像素电极，以将所述像素电极电压拉至所述公共电压；
其中所述第二扫描线的第二扫描信号的持续时间为一预定时间，以将所述像素电极的电压拉至不同的准位。
为解决上述技术问题，本发明实施例还构造了一种3D显示设备，包括阵列基板，所述阵列基板包括沿列方向延伸的数据线以及沿行方向延伸的公共电极线和扫描线，所述数据线和所述扫描线相互垂直交错，呈矩阵式排列，并形成多个像素单元，所述像素单元内包括有像素电极、第一薄膜晶体管和第二薄膜晶体管；
所述扫描线包括第一扫描线和第二扫描线，所述第一扫描线通过所述第一薄膜晶体管连接所述像素电极，所述第二扫描线通过所述第二薄膜晶体管连接所述像素电极；
其中所述第一扫描线，用于传输第一扫描信号，以打开所述第一薄膜晶体管；
所述数据线，用于在所述第一薄膜晶体管打开后，通过所述薄膜晶体管提供像素电极电压至所述像素电极，对所述像素电极充电；
所述第二扫描线，用于在所述数据线对所述像素电极充电后，传输第二扫描信号，以打开所述第二薄膜晶体管；
所述公共电极线，用于在所述第二薄膜晶体管打开后，通过所述第二薄膜晶体管提供公共电压至所述像素电极，以将所述像素电极电压拉至所述公共电压；
其中所述第二扫描线的第二扫描信号的持续时间为一预定时间，以将所述像素电极的电压拉至不同的准位。
 有益效果
本发明实施例通过设置第一扫描线和第二扫描线，首先通过第一扫描线打开相应的薄膜晶体管后，对像素电极进行充电，之后通过第二扫描线打开相应的薄膜晶体管，开始对像素电极施加公共电压，以实现***灰阶画面的效果，而且本发明实施例控制第二扫描线的第二扫描信号的持续时间，将像素电极的电压拉至不同准位，以实现不同灰阶亮度的画面的***，而并非只是***黑画面，解决了现有技术中只能显示一种灰阶画面，导致在高亮度显示时画质不佳的技术问题。
 附图说明
图1为本发明中阵列基板的较佳实施例效果示意图；
图2A为本发明其中一实施例中所述第一扫描线和所述第二扫描线的驱动波形图；
图2B为本发明另一实施例中所述第一扫描线和所述第二扫描线的驱动波形图；
图2C为对应***灰阶画面的时刻示意图；
图3A-3C为本发明实施例的效果示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
请参阅图1，图1为本发明中阵列基板的较佳实施例效果示意图。所述阵列基板包括沿列方向A延伸的数据线11，还包括有沿行方向B延伸的公共电极线12、第一扫描线13和第二扫描线14。其中所述数据线11与所述第一扫描线13、所述第二扫描线14均相互垂直交错，呈矩阵式排列，并形成多个像素单元20，当然，图1仅仅示出其中一像素单元，更多的像素单元的结构与图1类似，本文不再赘述。
请继续参阅图1，所述像素单元20包括有第一薄膜晶体管21、第二薄膜晶体管22，液晶电容CLC和存储电容CST，当然还包括有像素电极23，图1所示的所述像素电极23仅为一效果示意图，在具体实施中，所述像素电极23为平行于所述阵列基板的层结构。
其中所述第一扫描线13通过所述第一薄膜晶体管21连接所述像素电极23，所述第二扫描线14通过所述第二薄膜晶体管22连接所述像素电极23。
具体的，请参阅图1，所述第一薄膜晶体管21包括有第一栅极G1、第一源极S1以及第一漏极D1，所述第一薄膜晶体管21的第一栅极G1电连接所述第一扫描线131，所述第一薄膜晶体管21的第一源极S1电连接所述数据线11，所述第一薄膜晶体管21的第一漏极D1电连接所述像素电极23。
类似的，所述第二薄膜晶体管22包括有第二栅极G2、第二源极S2以及第二漏极D2，所述第二薄膜晶体管22的所述第二栅极G2电连接所述第二扫描线14，所述第二薄膜晶体管22的所述第二源极S2电连接所述公共电极线12，所述第二薄膜晶体管22的所述第二漏极D2电连接所述像素电极23。
在具体实施过程中，所述第一扫描线13用于传输第一扫描信号，以打开所述第一薄膜晶体管21的所述第一栅极G1，其中所述第一扫描信号譬如来自于栅驱动芯片（图未示出）。所述数据线11通过所述第一薄膜晶体管21提供像素电压至所述像素电极23，使所述像素电极23充电，以显示相应的左眼像素或者右眼像素。在充电结束，所述像素电极23处于电量保持状态，此时所述第二扫描线14传输第二扫描信号，以打开所述第二薄膜晶体管22的第二栅极G2，而所述公共电极线12则通过所述第二薄膜晶体管22提供公共电压至所述像素电极23，以将所述像素电极23的电压拉至所述公共电压。而且，在本发明实施例中，所述第二扫描线14的持续时间为一预定时间，以将所述像素电极23的电压拉至不同的准位，进而实现不同亮度的灰阶画面***。
譬如请参阅图2A-2C，图2A为本发明其中一实施例中所述第一扫描线13和所述第二扫描线14的驱动波形图，图2B为本发明另一实施例中所述第一扫描线13和所述第二扫描线14的驱动波形图，图2C为对应***灰阶画面的时刻示意图。
其中所述第一扫描线13传输第一扫描信号打开所述第一薄膜晶体管21的第一栅极G1，所述数据线11通过已打开的第一薄膜晶体管21给所述像素电极23提供电压，使所述像素电极23充电，以打开相应的左眼像素（Left）或者右眼像素（Right）。
在充电结束，即在打开相应的左眼像素（Left）或者右眼像素（Right）后，所述像素电极23处于电量保持状态，此时所述第二扫描线14传输第二扫描信号打开所述第二薄膜晶体管22的第二栅极G2，所述公共电极线12通过已打开的所述第二薄膜晶体管22给所述像素电极23提供公共电压，以将像素电极23的电压拉至公共电压，实现***灰阶画面（Black）的效果。
其中所述第一扫描信号具有一第一扫描周期T1，所述第二扫描信号具有第二扫描周期T2，在图2A所示的实施例中，在所述第二扫描周期T2内，所述第二扫描信号持续一预定时间t1，该预定时间t1的范围在0至T2之间，在图2B所示的实施例中，在所述第二扫描周期T2内，所述第二扫描信号持续一预定时间t2，该预定时间t2的范围在0至T2之间，明显的，t2> t1。在本发明实施例中，随着所述预定时间t1、t2…的变化，所述公共电极线12输入的公共电压可将所述像素电极23的电压拉至不同的准位，进而实现不同亮度的灰阶画面的***。
简言之，本发明实施例通过控制所述第二扫描信号的持续时间（预定时间）的长短来调整***画面的亮度。
其中，本发明通过控制所述第二扫描信号Gate2的持续时间的长短来调整***画面的亮度的原理为：
所述第一扫描线13传输第一扫描信号打开所述第一薄膜晶体管21的第一栅极G1，所述数据线11通过已打开的第一薄膜晶体管21给所述像素电极23提供电压，使所述像素电极23充电，在充电结束，所述像素电极23处于电量保持状态，此时在所述第二薄膜晶体管22的两侧，所述像素电极23的像素电极电压和所述公共电极线12的公共电极电压之间存在一电压差，在所述第二薄膜晶体管22的第二栅极G2打开时，上述电压差最大，此时***画面的亮度最亮，而随着所述第二薄膜晶体管22的第二栅极G2打开的时间越长，上述电压差逐渐减小，所述第二薄膜晶体管22两边的电荷重新分配，而***画面的亮度逐渐的变暗，直到上述电压差减小至零，此时所述第二薄膜晶体管22两边的电荷平衡，***画面的灰阶最暗。
显然，本发明实施例可通过控制所述第二薄膜晶体管22的第二栅极G2打开的时间的长短来调整***画面的灰阶亮度，即通过控制所述第二扫描信号的持续时间（预定时间）的不同，将所述像素电极23的电压（Vpixel）拉至不同准位，以实现不同灰阶亮度的画面的***，而并非只是黑画面。
其中所述第二扫描信号的第二扫描周期T2与所述第二扫描线的第二扫描周期T1优选为相等，且所述第二扫描线14优选在所述第一扫描信号的（T1）/2时刻开始传输所述第二扫描信号，当然也可在其它时刻传输所述第二扫描信号，均在本发明保护范围之内。
请参阅图3A-3C，图3A-3C为本发明实施例的效果示意图，其中L1为单纯***黑画面时的像素电极电压，L2为本发明实施例中控制所述第二扫描信号的预定时间t（横轴）在一定范围内变动时，所述像素电极23的电压Vpixel，显然，现对于现有技术，本发明实施例中，当所述第二扫描信号的预定时间t（横轴）在一定范围内变动时，所述像素电极23的电压Vpixel（纵轴）呈现不同数值，即显示不同亮度的灰阶。
本发明实施例还提供一种3D显示设备，所述3D显示设备包括本发明实施例提供的阵列基板，鉴于该阵列基板在上文已有详细的描述，此处不再赘述。
本发明实施例通过设置第一扫描线和第二扫描线，在通过第一扫描线打开相应的薄膜晶体管后，对像素电极进行充电，之后通过第二扫描线打开相应的薄膜晶体管，开始对像素电极施加公共电压，以实现***灰阶画面的效果，而且本发明实施例控制第二扫描线的第二扫描信号的持续时间，将像素电极的电压拉至不同准位，以实现不同灰阶亮度的画面的***，而并非只是***黑画面。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
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  1. 一种阵列基板，其中包括沿列方向延伸的数据线以及沿行方向延伸的公共电极线和扫描线，所述数据线和所述扫描线相互垂直交错，呈矩阵式排列，并形成多个像素单元，所述像素单元内包括有像素电极、第一薄膜晶体管和第二薄膜晶体管；
    所述扫描线包括第一扫描线和第二扫描线，所述第一扫描线通过所述第一薄膜晶体管连接所述像素电极，所述第二扫描线通过所述第二薄膜晶体管连接所述像素电极；
    所述第二薄膜晶体管包括有第二栅极、第二源极以及第二漏极，所述第二薄膜晶体管的所述栅极电连接所述第二扫描线，所述第二薄膜晶体管的所述源极电连接所述公共电极线，所述第二薄膜晶体管的所述第二漏极电连接所述像素电极；
    其中所述第一扫描线，用于传输第一扫描信号，以打开所述第一薄膜晶体管；
    所述数据线，用于在所述第一薄膜晶体管打开后，通过所述薄膜晶体管提供像素电极电压至所述像素电极，对所述像素电极充电；
    所述第二扫描线，用于在所述数据线对所述像素电极充电后，传输第二扫描信号，以打开所述第二薄膜晶体管；
    所述公共电极线，用于在所述第二薄膜晶体管打开后，通过所述第二薄膜晶体管提供公共电压至所述像素电极，以将所述像素电极电压拉至所述公共电压；
    其中所述第二扫描线的第二扫描信号的持续时间为一预定时间，以将所述像素电极的电压拉至不同的准位；所述第一扫描线具有第一扫描周期T1，所述预定时间的范围在0至T1之间。
  2. 根据权利要求1所述的阵列基板，其中所述第二扫描线具有第二扫描周期T2，所述第一扫描周期T1等于所述第二扫描周期T2。
  3. 根据权利要求2所述的阵列基板，其中所述第二扫描线是当所述第一扫描信号位于(T1) /2时开始传输所述第二扫描信号。
  4. 一种阵列基板，其中包括沿列方向延伸的数据线以及沿行方向延伸的公共电极线和扫描线，所述数据线和所述扫描线相互垂直交错，呈矩阵式排列，并形成多个像素单元，所述像素单元内包括有像素电极、第一薄膜晶体管和第二薄膜晶体管；
    所述扫描线包括第一扫描线和第二扫描线，所述第一扫描线通过所述第一薄膜晶体管连接所述像素电极，所述第二扫描线通过所述第二薄膜晶体管连接所述像素电极；
    其中所述第一扫描线，用于传输第一扫描信号，以打开所述第一薄膜晶体管；
    所述数据线，用于在所述第一薄膜晶体管打开后，通过所述薄膜晶体管提供像素电极电压至所述像素电极，对所述像素电极充电；
    所述第二扫描线，用于在所述数据线对所述像素电极充电后，传输第二扫描信号，以打开所述第二薄膜晶体管；
    所述公共电极线，用于在所述第二薄膜晶体管打开后，通过所述第二薄膜晶体管提供公共电压至所述像素电极，以将所述像素电极电压拉至所述公共电压；
    其中所述第二扫描线的第二扫描信号的持续时间为一预定时间，以将所述像素电极的电压拉至不同的准位。
  5. 根据权利要求4所述的阵列基板，其中所述第一扫描线具有第一扫描周期T1，所述预定时间的范围在0至T1之间。
  6. 根据权利要求5所述的阵列基板，其中所述第二扫描线具有第二扫描周期T2，所述第一扫描周期T1等于所述第二扫描周期T2。
  7. 根据权利要求6所述的阵列基板，其中所述第二扫描线是当所述第一扫描信号位于(T1) /2时开始传输所述第二扫描信号。
  8. 根据权利要求4所述的阵列基板，其中所述第二薄膜晶体管包括有第二栅极、第二源极以及第二漏极，所述第二薄膜晶体管的所述栅极电连接所述第二扫描线，所述第二薄膜晶体管的所述源极电连接所述公共电极线，所述第二薄膜晶体管的所述第二漏极电连接所述像素电极。
  9. 一种3D显示设备，其中包括阵列基板，所述阵列基板包括沿列方向延伸的数据线以及沿行方向延伸的公共电极线和扫描线，所述数据线和所述扫描线相互垂直交错，呈矩阵式排列，并形成多个像素单元，所述像素单元内包括有像素电极、第一薄膜晶体管和第二薄膜晶体管；
    所述扫描线包括第一扫描线和第二扫描线，所述第一扫描线通过所述第一薄膜晶体管连接所述像素电极，所述第二扫描线通过所述第二薄膜晶体管连接所述像素电极；
    其中所述第一扫描线，用于传输第一扫描信号，以打开所述第一薄膜晶体管；
    所述数据线，用于在所述第一薄膜晶体管打开后，通过所述薄膜晶体管提供像素电极电压至所述像素电极，对所述像素电极充电；
    所述第二扫描线，用于在所述数据线对所述像素电极充电后，传输第二扫描信号，以打开所述第二薄膜晶体管；
    所述公共电极线，用于在所述第二薄膜晶体管打开后，通过所述第二薄膜晶体管提供公共电压至所述像素电极，以将所述像素电极电压拉至所述公共电压；
    其中所述第二扫描线的第二扫描信号的持续时间为一预定时间，以将所述像素电极的电压拉至不同的准位。
  10. 根据权利要求9所述的3D显示设备，其中所述第一扫描线具有第一扫描周期T1，所述预定时间的范围在0至T1之间。
  11. 根据权利要求10所述的3D显示设备，其中所述第二扫描线具有第二扫描周期T2，所述第一扫描周期T1等于所述第二扫描周期T2。
  12. 根据权利要求11所述的3D显示设备，其中所述第二扫描线是当所述第一扫描信号位于(T1) /2时开始传输所述第二扫描信号。
  13. 根据权利要求9所述的3D显示设备，其中所述第二薄膜晶体管包括有第二栅极、第二源极以及第二漏极，所述第二薄膜晶体管的所述栅极电连接所述第二扫描线，所述第二薄膜晶体管的所述源极电连接所述公共电极线，所述第二薄膜晶体管的所述第二漏极电连接所述像素电极。
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