WO2015043386A1 - 场截止型绝缘栅双极型晶体管的制备方法 - Google Patents

场截止型绝缘栅双极型晶体管的制备方法 Download PDF

Info

Publication number
WO2015043386A1
WO2015043386A1 PCT/CN2014/086485 CN2014086485W WO2015043386A1 WO 2015043386 A1 WO2015043386 A1 WO 2015043386A1 CN 2014086485 W CN2014086485 W CN 2014086485W WO 2015043386 A1 WO2015043386 A1 WO 2015043386A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
substrate
bipolar transistor
insulated gate
gate bipolar
Prior art date
Application number
PCT/CN2014/086485
Other languages
English (en)
French (fr)
Inventor
王根毅
邓小社
钟圣荣
周东飞
Original Assignee
无锡华润上华半导体有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 无锡华润上华半导体有限公司 filed Critical 无锡华润上华半导体有限公司
Publication of WO2015043386A1 publication Critical patent/WO2015043386A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT

Definitions

  • the present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a field-off insulated gate bipolar transistor.
  • Insulated Gate Bipolar Transistor Insulated Gate Bipolar Transistor (Insulated Gate Bipolar Transistor) IGBT) has a lower on-resistance than DMOS. So far, IGBTs mainly have punch-through PT-IGBTs and non-punch-through NPT- Three structures of IGBT and field-stop FS-IGBT, the main difference between the three is different substrate PN junction structure and different drift region thickness. Compared with PT-IGBT and NPT-IGBT, the thickness of FS-IGBT is the thinnest, but the high cost of the thin-film equipment, the complicated process and the high fragmentation rate limit the performance of FS-IGBT (especially low-voltage IGBT). constantly improving.
  • the traditional FS-IGBT is usually after the FS layer is finished on the back side, and then the back side P+ layer is implanted according to the conventional IGBT front side process. This is easy to cause the front side of the wafer to be scratched, which is not conducive to the chip. The realization of normal functions.
  • a method of fabricating a field-cut insulated gate bipolar transistor comprising the steps of: providing a substrate, and growing a first oxide layer on a front side and a back side of the substrate; and injecting N-type ions inward from a back surface of the substrate Pushing the substrate to form a field stop layer in the region implanted with the N-type ions; removing the first oxide layer on the front side of the substrate; using the insulated gate bipolar transistor front side process in the substrate and the substrate Forming a front surface of the insulated gate bipolar transistor on the front surface; forming a front protective layer on the front surface structure; implanting P-type ions into the field stop layer to form a back P+ layer; removing the front protective layer, and The back P+ layer is pushed and formed; and a front metal layer is formed on one of the front surface structure and the back surface P+ layer, and a back metal layer is formed on the other side.
  • the method further includes removing the polysilicon layer and the back surface of the substrate.
  • the step of an oxide layer after the step of injecting N-type ions inwardly from the back side of the substrate, before the step of pushing the well, further comprising forming a polysilicon layer on the first oxide layer on the back surface of the substrate.
  • the step of removing the polysilicon layer is performed by a dry etching method.
  • the polysilicon layer in the step of forming a polysilicon layer on the first oxide layer on the back side of the substrate, has a thickness of 7000 angstroms.
  • phosphorus ions are implanted in the step of injecting N-type ions inward from the back surface of the substrate.
  • the step of forming a front protective layer on the front side structure comprises: forming a silicon nitride layer on the front side structure and forming a second oxide layer on the silicon nitride layer.
  • the step of removing the front protective layer employs a method of wet etching.
  • the step of pushing the well comprises annealing at a temperature above 500 degrees Celsius.
  • a method of wet etching is employed.
  • the thickness of the substrate is 400 ⁇ m.
  • the method for preparing the field-cut type insulated gate bipolar transistor can protect the front surface of the wafer by growing the front first oxide layer and forming a front protective layer after the front surface structure is formed, so that it is not protected during the manufacturing process. Easy to scratch.
  • FIG. 1 is a flow chart showing a method of fabricating a field-off insulated gate bipolar transistor in an embodiment
  • 2A-2G are partial cross-sectional views of a FS-IGBT prepared by a method for fabricating a field-cut insulated gate bipolar transistor in an embodiment.
  • FIG. 1 is a flow chart showing a method of fabricating a field-off insulated gate bipolar transistor in an embodiment, including the following steps:
  • a wafer material having a thickness of about 400 ⁇ m is used (Raw) Wafer) as the substrate 11, and the first oxide layer 12 is grown on the front and back sides of the substrate 11, see Fig. 2A.
  • Raw Raw
  • Wafer Wafer
  • an oxide layer is formed on both the front side and the back side, and the oxide layers on the front and back sides of the substrate 11 in the drawing are collectively referred to as the first oxide layer 12.
  • the wafer can be inverted and then implanted into the back side of the wafer by a front implanting machine.
  • the implanted N-type ions pass through the first oxide layer 12 on the back side into the substrate.
  • the implanted N-type ions are phosphorus ions, and in other embodiments, other types of N-type ions may be implanted.
  • the first oxide layer 12 on the back side can prevent the surface of the substrate 11 from being damaged during ion implantation in step S120.
  • the substrate is pushed to form a field in which the N-type ions are implanted to form a field stop layer.
  • the well is pushed with an annealing menu of more than 500 degrees Celsius to form a diffused N+ layer as the field stop (FS) layer 14.
  • FS field stop
  • a step of forming a polysilicon layer 13 on the first oxide layer 12 on the back surface of the substrate 11 may be further included between steps S120 and S130, see FIG. 2B.
  • a polysilicon layer is formed on both the front side and the back side, and the front and back polysilicon layers are collectively labeled as the polysilicon layer 13.
  • the thickness of the deposited polysilicon layer 13 is 7000 angstroms. In other embodiments, the thickness of the polysilicon layer 13 can also be adjusted according to specific conditions.
  • the polysilicon layer 13 on the back side can protect the N-type ions implanted in the step S120 to prevent contamination of the field stop layer 14 by subsequent operations.
  • the front polysilicon layer 13 is removed by dry etching, and the first oxide layer 12 is removed by wet etching.
  • the structure after the removal is completed is shown in Fig. 2C.
  • the front side structure of the IGBT can be prepared using a conventional IGBT front side process until the hole etching is completed, see FIG. 2D.
  • the front side structure on the substrate 11 includes a polysilicon gate 18, an interlayer dielectric (ILD) 19, and the like.
  • a front protective layer is grown on the interlayer dielectric 19.
  • the front protective layer includes a SiN layer 26 and a second oxide layer 25. It can be understood that, in the present embodiment, the SiN layer 26 and the second oxide layer 25 are simultaneously formed on the back surface due to process limitations. Therefore, it is necessary to remove the SiN layer 26 and the second oxide layer 25 on the back side.
  • the step S160 further includes the step of removing the SiN layer 26 and the second oxide layer 25 on the back surface. Specifically include:
  • a photoresist is coated on the front side of the wafer, and then the second oxide layer 25 on the back side of the wafer is removed with an etching solution.
  • the silicon nitride layer on the back side is removed by wet etching.
  • step S162 After the photoresist coated in step S162 is removed, the SiN layer 26 on the back side of the wafer is stripped off with a SiN total stripping solution.
  • the polysilicon layer 13 is also formed on the back side between the steps S120 and S130, so the polysilicon layer 13 is also removed before the step S170. Specifically, in the embodiment, the polysilicon layer 13 is removed by dry etching.
  • the first oxide layer on the back side of the substrate is removed.
  • the first oxide layer 12 on the back surface of the substrate 11 is removed by wet etching. It can be understood that the first oxide layer 12 on the back surface of the substrate 11 can be removed together in step S140.
  • the SiN layer 26, the second oxide layer 25, and the polysilicon layer 13 on the back side are all removed to obtain a structure as shown in FIG. 2E.
  • the field stop layer 14 can be implanted.
  • the implantation can be performed using a front implanting machine that implants boron ions to form a backside P+ layer 23 on the surface of the field stop layer 14, as shown in Figure 2F.
  • Other types of P-type ions can also be implanted in other embodiments.
  • the front protective layer protects the front side of the device during the implantation process.
  • the front protective layer is removed by wet etching. Specifically, a buffer oxide etchant (buffer oxide) The etch, BOE) solution etches away the front second oxide layer 25, and then removes the front SiN layer 26 using a SiN total stripping solution. The back P+ layer 23 is subjected to high temperature pushing.
  • a buffer oxide etchant buffer oxide
  • BOE buffer oxide
  • the etch, BOE solution etches away the front second oxide layer 25, and then removes the front SiN layer 26 using a SiN total stripping solution.
  • the back P+ layer 23 is subjected to high temperature pushing.
  • a front metal layer 27 and a back metal layer 28 are formed.
  • the formation of the metal layer can be carried out by a conventional process and will not be described herein.
  • the front side of the wafer can be protected by growing the front first oxide layer 12 in step S110 and forming a front protective layer in step S160 after the front surface structure is formed. It will not be easily scratched during the manufacturing process.
  • the implantation and pushing of the back P+ layer are performed before the metal layer is formed (step S190), and the high temperature pushing in step S180 can adopt an annealing menu of more than 1000 degrees Celsius, which is advantageous for improving the performance of the device.
  • the method of fabricating the above-described field-off insulated gate bipolar transistor is compatible with the existing metal-oxide-semiconductor (MOS) process, and can save cost.
  • MOS metal-oxide-semiconductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种场截止型绝缘栅双极型晶体管的制备方法，包括以下步骤：提供衬底（11），在衬底（11）正面和背面生长第一氧化层（12）；从衬底（11）的背面向内注入N型离子；对衬底（11）进行推阱，使注入了N型离子的区域形成场截止层（14）；去除衬底（11）正面的第一氧化层（12）；采用IGBT正面工艺在衬底（11）内和衬底（11）正面制备出IGBT的正面结构；在正面结构上形成正面保护层；对场截止层进行P型离子的注入，形成背面P+层（23）；去除正面保护层，并对背面P+层（23）进行推结；及于正面结构及背面P+层（23）其中之一上形成正面金属层（27），并于另一个上形成背面金属层（28）。通过生长正面的第一氧化层（12），并在正面结构形成后形成正面保护层，能够保护圆片的正面，令其在制造过程中不会被轻易划伤。

Description

场截止型绝缘栅双极型晶体管的制备方法
【技术领域】
本发明涉及一种半导体器件的制造方法，特别是涉及一种场截止型绝缘栅双极型晶体管的制备方法。
【背景技术】
由于电导调制效应，绝缘栅双极晶体管（Insulated Gate Bipolar Transistor， 简称 IGBT）具有比DMOS更低的导通电阻。迄今为止，IGBT主要有穿通型PT- IGBT、非穿通型NPT- IGBT和场截止型FS-IGBT三种结构，三者之间的主要差异是不同的衬底PN结结构和不同的漂移区厚度。相对PT-IGBT和NPT-IGBT来讲，FS-IGBT的厚度是最薄的，但薄片设备价格贵、工艺复杂以及很高的碎片率严重的限制了FS-IGBT（特别是低压IGBT）性能的不断提升。
另一方面，传统的FS-IGBT，通常是背面做完FS层以后，再按照常规的IGBT正面工艺流程最后进行背面P+层的注入，这样做很容易造成圆片的正面划伤，不利于芯片正常功能的实现。
【发明内容】
基于此，有必要提供一种制造过程中不易划伤的场截止型绝缘栅双极型晶体管的制备方法。
一种场截止型绝缘栅双极型晶体管的制备方法，包括以下步骤：提供衬底，并在衬底的正面和背面生长第一氧化层；从所述衬底的背面向内注入N型离子；对衬底进行推阱，使注入了N型离子的区域形成场截止层；去除衬底的正面的所述第一氧化层；采用绝缘栅双极型晶体管正面工艺在衬底内和衬底正面制备出绝缘栅双极型晶体管的正面结构；在所述正面结构上形成正面保护层；对所述场截止层进行P型离子的注入，形成背面P+层；去除正面保护层，并对所述背面P+层进行推结；及于所述正面结构及所述背面P+层其中之一上形成正面金属层，并于另一个上形成背面金属层。
在其中一个实施例中，所述从衬底的背面向内注入N型离子的步骤之后、所述推阱的步骤之前，还包括在衬底背面的所述第一氧化层上形成多晶硅层的步骤；所述在正面结构上形成正面保护层的步骤之后，所述对场截止层进行P型离子的注入、形成背面P+层的步骤之前，还包括去除所述多晶硅层及衬底背面的第一氧化层的步骤。
在其中一个实施例中，所述去除所述多晶硅层的步骤采用的是干法刻蚀的方法。
在其中一个实施例中，所述在衬底背面的所述第一氧化层上形成多晶硅层的步骤中，多晶硅层的厚度为7000埃。
在其中一个实施例中，所述从衬底的背面向内注入N型离子的步骤中，注入的是磷离子。
在其中一个实施例中，所述在正面结构上形成正面保护层的步骤包括：在所述正面结构上形成氮化硅层，并在所述氮化硅层上形成第二氧化层。
在其中一个实施例中，所述去除正面保护层的步骤采用的是湿法腐蚀的方法。
在其中一个实施例中，所述推阱的步骤包括使用500摄氏度以上的温度进行退火。
在其中一个实施例中，所述去除衬底正面的所述第一氧化层的步骤中，采用的是湿法腐蚀的方法。
在其中一个实施例中，所述提供衬底的步骤中，衬底的厚度为400微米。
上述场截止型绝缘栅双极型晶体管的制备方法，通过生长正面的第一氧化层，并在正面结构形成后形成正面保护层，能够保护圆片的正面，令其在制造过程中不会被轻易划伤。
【附图说明】
图1是一实施例中场截止型绝缘栅双极型晶体管的制备方法的流程图；
图2A~图2G是一实施例中采用场截止型绝缘栅双极型晶体管的制备方法制备的FS-IGBT在制备过程中的局部剖视图。
【具体实施方式】
为使本发明的目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。
图1是一实施例中场截止型绝缘栅双极型晶体管的制备方法的流程图，包括下列步骤：
S110，提供衬底，并在衬底的正面和背面生长氧化层。
在本实施例中，采用厚度为约400微米的晶圆原材料(Raw Wafer)作为衬底11，并在衬底11的正面和背面生长第一氧化层12，参照图2A。可以理解，在本实施例中，由于工艺的限制，会同时在正面和背面形成氧化层，附图中衬底11正面和背面的氧化层统一标号为第一氧化层12。
S120，从衬底的背面向内注入N型离子。
可以将圆片（wafer）翻转后用正面注入机台实现对圆片背面的注入，注入的N型离子穿过背面的第一氧化层12进入衬底。在本实施例中，注入的N型离子为磷离子，在其它实施例中注入的也可以是其它种类的N型离子。
背面的第一氧化层12可以防止步骤S120中的离子注入时导致衬底11表面损伤。
S130，对衬底进行推阱，使注入了N型离子的区域形成场截止层。
在本实施例中，是用超过500摄氏度的退火菜单进行推阱，形成扩散后的N+层作为场截止（FS）层14。
在本实施例中，于步骤S120和S130之间还可包括在衬底11背面的第一氧化层12上淀积形成多晶硅层13的步骤，参见图2B。可以理解，由于工艺的限制，在本实施例中，会同时在正面和背面形成多晶硅层，正面和背面的多晶硅层统一标号为多晶硅层13。在本实施例中，淀积的多晶硅层13的厚度为7000埃，在其它实施例中也可以根据具体情况调整多晶硅层13的厚度。
背面的多晶硅层13可以保护步骤S120中注入的N型离子，防止后续作业对场截止层14的污染。
S140，去除衬底正面的氧化层。
在本实施例中，不仅要去除衬底正面的第一氧化层12，而且要去除衬底正面的多晶硅层13。其中，正面的多晶硅层13采用干法刻蚀去除，第一氧化层12采用湿法腐蚀去除。去除完成后的结构如图2C所示。
S150，采用IGBT正面工艺在衬底内和衬底正面制备出IGBT的正面结构。
可以使用常规的IGBT正面工艺来制备IGBT的正面结构，直至孔刻蚀完成，参照图2D。衬底11上的正面结构包括多晶硅栅18、层间介质（ILD）19等。
S160，在IGBT的正面结构上形成正面保护层。
在层间介质19上生长正面保护层。在本实施例中，正面保护层包括SiN层26和第二氧化层25。可以理解，由于工艺的限制，在本实施例中，SiN层26和第二氧化层25同时会在背面形成。因此，需要将背面的SiN层26和第二氧化层25去除。
故，步骤S160后还包括去除背面的SiN层26和第二氧化层25步骤。具体包括：
S162，用湿法腐蚀去除背面的第二氧化层。
在圆片（wafer）正面涂覆光刻胶，然后用腐蚀液去除圆片背面的第二氧化层25。
S164，用湿法腐蚀去除背面的氮化硅层。
去除步骤S162中涂覆的光刻胶后，用SiN全剥药液，剥去圆片背面的SiN层26。
另外，正如前面所述，步骤S120和S130之间还会在背面形成多晶硅层13，因此同样要在步骤S170之前将该多晶硅层13去除。具体在本实施例中是采用干法刻蚀去除该多晶硅层13。
S165 去除衬底背面的第一氧化层。在本实施方式中，采用湿法腐蚀去除衬底11背面的第一氧化层12。可以理解，衬底11背面的第一氧化层12可以于步骤S140中一并除去。背面的SiN层26、第二氧化层25及多晶硅层13均去除后得到如图2E所示的结构。
S170，对场截止层进行P型离子的注入，形成背面P+层。
背面的SiN层26、第二氧化层25、多晶硅层13及第一氧化层12去除后，就可以对场截止层14进行注入了。注入可以使用正面注入机台进行，注入硼离子从而在场截止层14表面形成背面P+层23，如图2F所示。在其它实施例中也可以注入其它种类的P型离子。在注入过程中，正面保护层对器件正面形成保护。
S180，去除正面保护层，并对背面P+层进行推结。
采用湿法腐蚀的方式来去除正面保护层。具体是用缓冲氧化刻蚀剂(buffer oxide etch，BOE)溶液刻蚀掉正面的第二氧化层25，再使用SiN全剥药液去除正面的SiN层26。对背面P+层23进行高温推结。
S190，于正面结构及背面P+层其中之一上形成正面金属层，并于另一个上形成背面金属层。
如图2G所示，形成正面金属层27和背面金属层28。金属层的形成可以采用习知的工艺进行，此处不再赘述。
上述场截止型绝缘栅双极型晶体管的制备方法，通过在步骤S110中生长正面的第一氧化层12，并在正面结构形成后于步骤S160中形成正面保护层，能够保护圆片的正面，令其在制造过程中不会被轻易划伤。背面P+层的注入和推结在形成金属层（步骤S190）之前进行，步骤S180中的高温推结可以采用大于1000摄氏度的退火菜单，有利于提升器件的性能。
另外，上述场截止型绝缘栅双极型晶体管的制备方法与现有的金属-氧化物-半导体(metal–oxide–semiconductor，MOS)工艺兼容，能够节省成本。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种场截止型绝缘栅双极型晶体管的制备方法，包括以下步骤：
    提供衬底，并在衬底的正面和背面生长第一氧化层；
    从所述衬底的背面向内注入N型离子；
    对所述衬底进行推阱，使注入了N型离子的区域形成场截止层；
    去除所述衬底的正面的所述第一氧化层；
    采用绝缘栅双极型晶体管正面工艺在所述衬底内和所述衬底正面制备出绝缘栅双极型晶体管的正面结构；
    在所述正面结构上形成正面保护层；
    对所述场截止层进行P型离子的注入，形成背面P+层；
    去除所述正面保护层，并对所述背面P+层进行推结；及
    于所述正面结构及所述背面P+层其中之一上形成正面金属层，并于另一个上形成背面金属层。
  2. 根据权利要求1所述的场截止型绝缘栅双极型晶体管的制备方法，其特征在于，从所述衬底的背面向内注入N型离子的步骤之后、所述推阱的步骤之前，还包括在衬底背面的所述第一氧化层上形成多晶硅层的步骤；所述在正面结构上形成正面保护层的步骤之后，所述对场截止层进行P型离子的注入、形成背面P+层的步骤之前，还包括去除所述多晶硅层及所述衬底背面的第一氧化层的步骤。
  3. 根据权利要求2所述的场截止型绝缘栅双极型晶体管的制备方法，其特征在于，所述去除所述多晶硅层的步骤采用的是干法刻蚀的方法。
  4. 根据权利要求2所述的场截止型绝缘栅双极型晶体管的制备方法，其特征在于，在所述衬底背面的所述第一氧化层上形成多晶硅层的步骤中，所述多晶硅层的厚度为7000埃。
  5. 根据权利要求1所述的场截止型绝缘栅双极型晶体管的制备方法，其特征在于，所述从衬底的背面向内注入N型离子的步骤中，注入的是磷离子。
  6. 根据权利要求1所述的场截止型绝缘栅双极型晶体管的制备方法，其特征在于，在所述正面结构上形成正面保护层的步骤包括：在所述正面结构上形成氮化硅层，并在所述氮化硅层上形成第二氧化层。
  7. 根据权利要求6所述的场截止型绝缘栅双极型晶体管的制备方法，其特征在于，所述去除正面保护层的步骤采用的是湿法腐蚀的方法。
  8. 根据权利要求1所述的场截止型绝缘栅双极型晶体管的制备方法，其特征在于，所述推阱的步骤包括使用500摄氏度以上的温度进行退火。
  9. 根据权利要求1所述的场截止型绝缘栅双极型晶体管的制备方法，其特征在于，所述去除衬底正面的所述第一氧化层的步骤中，采用的是湿法腐蚀的方法。
  10. 根据权利要求1所述的场截止型绝缘栅双极型晶体管的制备方法，其特征在于，所述提供衬底的步骤中，所述衬底的厚度为400微米。
PCT/CN2014/086485 2013-09-26 2014-09-15 场截止型绝缘栅双极型晶体管的制备方法 WO2015043386A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310447027.0 2013-09-26
CN201310447027.0A CN104517836B (zh) 2013-09-26 2013-09-26 场截止型绝缘栅双极型晶体管的制备方法

Publications (1)

Publication Number Publication Date
WO2015043386A1 true WO2015043386A1 (zh) 2015-04-02

Family

ID=52742024

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/086485 WO2015043386A1 (zh) 2013-09-26 2014-09-15 场截止型绝缘栅双极型晶体管的制备方法

Country Status (2)

Country Link
CN (1) CN104517836B (zh)
WO (1) WO2015043386A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003059856A (ja) * 2001-08-09 2003-02-28 Fuji Electric Co Ltd 半導体装置の製造方法
US20100197127A1 (en) * 2009-02-04 2010-08-05 Fuji Electric Systems Co., Ltd. Method of manufacturing a semiconductor device
CN103050397A (zh) * 2011-10-13 2013-04-17 上海华虹Nec电子有限公司 Igbt器件背面外延场阻挡层的工艺实现方法
CN103199107A (zh) * 2012-01-06 2013-07-10 上海华虹Nec电子有限公司 半导体器件及制造方法
CN103578981A (zh) * 2012-07-19 2014-02-12 无锡华润上华半导体有限公司 场终止绝缘栅双极型晶体管的制备方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102693912B (zh) * 2011-03-24 2014-11-05 上海北车永电电子科技有限公司 制作igbt器件的方法及其装置
CN102184854B (zh) * 2011-04-14 2013-05-08 电子科技大学 一种功率器件背面热退火时对正面金属图形的保护方法
KR20120127055A (ko) * 2011-05-13 2012-11-21 삼성전자주식회사 절연 게이트 바이폴라 트랜지스터의 제조 방법
CN102420133B (zh) * 2011-09-30 2013-07-24 上海华虹Nec电子有限公司 Igbt器件的制造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003059856A (ja) * 2001-08-09 2003-02-28 Fuji Electric Co Ltd 半導体装置の製造方法
US20100197127A1 (en) * 2009-02-04 2010-08-05 Fuji Electric Systems Co., Ltd. Method of manufacturing a semiconductor device
CN103050397A (zh) * 2011-10-13 2013-04-17 上海华虹Nec电子有限公司 Igbt器件背面外延场阻挡层的工艺实现方法
CN103199107A (zh) * 2012-01-06 2013-07-10 上海华虹Nec电子有限公司 半导体器件及制造方法
CN103578981A (zh) * 2012-07-19 2014-02-12 无锡华润上华半导体有限公司 场终止绝缘栅双极型晶体管的制备方法

Also Published As

Publication number Publication date
CN104517836B (zh) 2018-01-23
CN104517836A (zh) 2015-04-15

Similar Documents

Publication Publication Date Title
WO2014114179A1 (zh) 分立式场氧结构的半导体器件的制造方法
TW201232760A (en) Semiconductor device and fabrication method thereof
TW200933818A (en) Semiconductor structure and method of manufacture
WO2014206193A1 (zh) 场截止型反向导通绝缘栅双极型晶体管及其制造方法
CN103715133A (zh) Mos晶体管及其形成方法
WO2016161842A1 (zh) 横向扩散金属氧化物半导体场效应管及其制造方法
WO2014206189A1 (zh) 场截止型反向导通绝缘栅双极型晶体管及其制造方法
WO2015027961A1 (zh) 反向导通绝缘栅双极型晶体管制造方法
WO2015103912A1 (zh) 对称隔离 ldmos 器件及其制造方法
CN108231767B (zh) 具有多个氮化层的装置结构
WO2014206300A1 (zh) 绝缘栅双极晶体管的制造方法
US8466500B2 (en) Semiconductor device and method for manufacturing the same
WO2015043386A1 (zh) 场截止型绝缘栅双极型晶体管的制备方法
JPH023964A (ja) 半導体装置においてポリシリコンゲートとポリシリコンエミッタとを同時に形成する方法
WO2015027850A1 (zh) 反向导通场截止型绝缘栅双极型晶体管的制造方法
WO2015043396A1 (zh) 场截止型绝缘栅双极型晶体管的背面工艺
WO2015014289A1 (zh) 绝缘栅双极型晶体管的制造方法
WO2017219755A1 (zh) 沟槽栅极结构及其制造方法
WO2015027878A1 (zh) 绝缘栅双极型晶体管及其制备方法
WO2012065514A1 (en) Ldmos device and method for fabricating the same
US6281093B1 (en) Method to reduce trench cone formation in the fabrication of shallow trench isolations
CN106571338B (zh) 半导体结构及其形成方法
WO2015027947A1 (zh) 绝缘栅双极型晶体管及其制备方法
WO2015010656A1 (zh) 非穿通型绝缘栅双极晶体管的制造方法
CN103730365B (zh) 晶体管的结构及其制作方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14847429

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14847429

Country of ref document: EP

Kind code of ref document: A1