WO2015037374A1 - Inductor and band elimination filter - Google Patents

Inductor and band elimination filter Download PDF

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Publication number
WO2015037374A1
WO2015037374A1 PCT/JP2014/071145 JP2014071145W WO2015037374A1 WO 2015037374 A1 WO2015037374 A1 WO 2015037374A1 JP 2014071145 W JP2014071145 W JP 2014071145W WO 2015037374 A1 WO2015037374 A1 WO 2015037374A1
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Prior art keywords
terminal electrode
coil conductor
conductor
lead pattern
coil
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PCT/JP2014/071145
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French (fr)
Japanese (ja)
Inventor
用水邦明
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株式会社村田製作所
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Priority to CN201490000926.4U priority Critical patent/CN205680518U/en
Publication of WO2015037374A1 publication Critical patent/WO2015037374A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/40—Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/0006—Printed inductances
    • H01F17/0013—Printed inductances with stacked layers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01—Frequency selective two-port networks
    • H03H7/0115—Frequency selective two-port networks comprising only inductors and capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/0006—Printed inductances
    • H01F17/0013—Printed inductances with stacked layers
    • H01F2017/0026—Multilayer LC-filter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
    • H03H2001/0021—Constructional details
    • H03H2001/0085—Multilayer, e.g. LTCC, HTCC, green sheets
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01—Frequency selective two-port networks
    • H03H2007/013—Notch or bandstop filters

Definitions

  • the present invention relates to a multilayer chip type inductor and a band elimination filter used in various electronic circuits.
  • a laminated chip type inductor has a structure in which an insulating base material on which a coil conductor pattern is formed is laminated, and both ends of the coil conductor pattern are connected to terminal electrodes.
  • Patent Document 1 discloses a multilayer chip inductor in which a coil conductor pattern is disposed closer to the center of a chip than two terminal electrode formation positions, and the coil conductor pattern and the terminal electrode do not overlap in plan view. It is shown.
  • the stray capacitance generated between the coil conductor pattern and the terminal electrode is small, and the self-resonant frequency of the inductor can be increased.
  • Patent Document 1 there is a problem that an inductance obtained per element size is reduced because a region where a coil conductor pattern is formed is limited. There is a similar problem with a filter including an inductor.
  • An object of the present invention is to provide an inductor and a band elimination filter that can suppress a decrease in inductance while suppressing stray capacitance.
  • the inductor of the present invention is Coil conductors, terminal electrodes, and connection conductors connecting the coil conductors and the terminal electrodes are formed in a laminate of a plurality of base material layers,
  • the terminal electrode includes a first terminal electrode and a second terminal electrode formed on a common mounting surface,
  • the coil conductor is formed across a plurality of the base material layers,
  • the formation region of the coil conductor has a portion that overlaps the first terminal electrode in a plan view, and does not overlap the second terminal electrode.
  • the path length from the first terminal electrode to the coil conductor is shorter than the path length from the second terminal electrode to the coil conductor.
  • the coil conductor is formed across the plurality of base material layers so as to extend in a direction away from the mounting surface on which the terminal electrodes are formed in the stacking direction of the plurality of base material layers. And A portion of the connection conductor that connects the second terminal electrode and the coil conductor connects a portion of the coil conductor that is farthest from the mounting surface in the stacking direction to the second terminal electrode.
  • a configuration is preferred. With the above configuration, the number of turns of the coil conductor can be easily increased.
  • an auxiliary conductor conducting to the first terminal electrode is provided between the coil conductor and the first terminal electrode.
  • a part of the coil conductor is formed on the same plane as the terminal electrode and between the first terminal electrode and the second terminal electrode.
  • the coil conductors formed on the plurality of base material layers have a pattern that goes around substantially the same path in a plan view.
  • the coil conductor formed on the base material layer away from the first terminal electrode among the coil conductors is blocked by the coil conductor formed on the base material layer close to the first terminal electrode. The stray capacitance generated between the electrode and the coil conductor pattern is suppressed.
  • the formation area of the coil conductor is substantially rectangular in plan view,
  • the first terminal electrode and the second terminal electrode are substantially rectangular;
  • the first side of the coil conductor formation region overlaps in the longitudinal direction of the first terminal electrode in plan view, It is preferable that the second side facing the first side of the coil conductor forming region is parallel to the longitudinal direction of the second terminal electrode.
  • the band elimination filter of the present invention includes the inductor and a capacitor connected in parallel to the inductor,
  • the capacitor is A first lead pattern drawn from the middle of the coil conductor of the inductor;
  • a second lead pattern that is drawn from a position closer to the second terminal electrode on the circuit than the first lead pattern, and is formed to overlap the first lead pattern in plan view;
  • a third lead pattern that is drawn from a position closer to the first terminal electrode on the circuit than the first lead pattern and is formed so as to overlap the first lead pattern in plan view;
  • the first lead pattern, the second lead pattern, and the third lead pattern are formed outside the formation region of the coil conductor in a plan view.
  • the capacitor can be formed in an empty space other than the formation region of the coil conductor, and the band elimination characteristic can be obtained without increasing the size.
  • the second lead pattern is preferably a connection conductor that connects the second terminal electrode and the coil conductor.
  • the third lead pattern does not overlap the second terminal electrode in plan view. With this configuration, unnecessary stray capacitance generated between the second terminal electrode and the third lead pattern is suppressed, and a capacitance component that is equivalently connected between the first terminal electrode and the second terminal electrode is small. It is easy to obtain good band elimination characteristics.
  • the present invention there is almost no stray capacitance between the first terminal electrode and the coil conductor, and the stray capacitance generated between the second terminal electrode and the coil conductor is reduced.
  • a small inductor is constructed. Since the formation area of the coil conductor is relatively large, a desired inductance can be obtained without increasing the overall size. In addition, a small band elimination filter can be obtained.
  • FIG. 1 is an exploded perspective view of an inductor 101 according to the first embodiment.
  • FIG. 2 is an exploded plan view of each base material layer of the inductor 101.
  • FIG. 3 is a cross-sectional view of inductor 101 at the position indicated by the alternate long and short dash line in FIG.
  • FIG. 4 is an exploded plan view of the inductor 102 according to the second embodiment.
  • FIG. 5 is an exploded plan view of the inductor 103 according to the third embodiment.
  • FIG. 6 is an exploded plan view of the band elimination filter 104 according to the fourth embodiment.
  • FIG. 7 is a circuit diagram of the band elimination filter 104 shown in FIG. 8A and 8B are diagrams showing the results of simulating the frequency characteristics of the insertion loss of the band elimination filter 104.
  • FIG. FIG. 9 is an exploded plan view of the band elimination filter 105 according to the fifth embodiment.
  • FIG. 10 is a circuit diagram of the band elimination filter 105.
  • FIG. 1 is an exploded perspective view of the inductor 101 according to the first embodiment
  • FIG. 2 is an exploded plan view of each base material layer of the inductor 101
  • 3 is a cross-sectional view of the inductor 101 at the position indicated by the alternate long and short dash line in FIG.
  • the inductor 101 includes a laminated body 10 in which insulating base material layers 11 to 15 are laminated and integrated.
  • the laminated body 10 is formed with a coil conductor, a terminal electrode, and a connection conductor that connects the coil conductor and the terminal electrode.
  • the insulating base layers 11 to 15 are, for example, LCP resin (liquid crystal polymer), and in-plane coil conductors 21, 22, 23, and 24 are formed on the lower surfaces of the base layers 11, 12, 13, and 14, respectively.
  • Interlayer coil conductors 62, 63, and 64 are formed on the base material layers 12, 13, and 14, respectively.
  • the interlayer coil conductor 62 connects one ends of the in-plane coil conductors 21 and 22,
  • the interlayer coil conductor 63 connects one ends of the in-plane coil conductors 22 and 23,
  • the interlayer coil conductor 64 connects the in-plane coil conductors 23 and 24. Connect one end of each other.
  • a broken-line circle represents a connection position with a lower interlayer coil conductor.
  • the coil conductor is constituted by the in-plane coil conductors 21, 22, 23, 24 and the interlayer coil conductors 62, 63, 64.
  • the first terminal electrode 31 and the second terminal electrode 32 are formed on the lower surface of the base material layer 15, respectively.
  • an interlayer connection conductor 41 is formed on the base material layer 15 to connect the end portion of the in-plane coil conductor 24 formed on the base material layer 14 and the first terminal electrode 31. That is, the portion of the connection conductor that connects the in-plane coil conductor and the first terminal electrode 31 is configured by the interlayer connection conductor 41.
  • An in-plane connection conductor 51 continuous from the in-plane coil conductor 21 is formed on the lower surface of the base material layer 11.
  • Interlayer connection conductors 45, 46, 47 and 48 are formed on the base material layers 12, 13, 14 and 15. These interlayer connection conductors 45 to 48 connect the end portion of the in-plane connection conductor 51 and the second terminal electrode 32. That is, of the connection conductors, the portions connecting the coil conductors (in-plane coil conductors 21, 22, 23, 24 and interlayer coil conductors 62, 63, 64) and the second terminal electrode 32 are the in-plane connection conductor 51 and It is composed of interlayer connection conductors 45-48.
  • the coil conductor extends in the stacking direction of the plurality of base material layers 11 to 15 while rotating around the direction away from the mounting surface on which the terminal electrodes are formed. 11 is formed. A portion of the connecting conductor that connects the second terminal electrode 32 and the coil conductor connects the portion of the coil conductor that is farthest from the mounting surface in the stacking direction to the second terminal electrode 32.
  • the formation regions of the coil conductors 21 to 24 and 62 to 64 in a plan view are rectangular.
  • the in-plane coil conductors 21 to 24 formed on the plurality of base material layers 11 to 14 circulate on the same rectangular path in plan view.
  • the first side of the coil conductor formation region overlaps the first terminal electrode 31.
  • the coil conductor formation region does not overlap the second terminal electrode 32, and the second side opposite to the first side of the coil conductor formation region is parallel to the longitudinal direction of the second terminal electrode 32. That is, in FIG. 2, the coil conductor formation region indicated by a two-dot chain line is closer to the first terminal electrode 31 than the second terminal electrode 32.
  • the path length from the first terminal electrode 31 to the in-plane coil conductor 24 (the length in the layer direction of the interlayer connection conductor 41) is the path length from the second terminal electrode 32 to the in-plane coil conductor 21 (interlayer connection conductor 45). (The length in the layer direction of .about.48 and the length of the in-plane connecting conductor 51).
  • the above configuration can be rephrased as follows.
  • the in-plane coil conductor 24 adjacent (immediately above) in the layer direction to the first terminal electrode 31 in which the formation regions of the coil conductors 21 to 24 and 62 to 64 overlap in plan view is interposed via the interlayer connection conductor 41. Connected in the shortest distance.
  • the uppermost in-plane coil conductor 21 among the in-plane coil conductors 21 to 24 formed on the plurality of base material layers is connected to the interlayer connection conductors 45 to 48 and the in-plane connection. It is connected via the conductor 51.
  • the interlayer connection conductors 45 to 48 are arranged on a straight line extending in the stacking direction. Therefore, the area where the “connecting portion” (the in-plane connection conductor 51 and the interlayer connection conductors 45 to 48) and the second terminal electrode 32 overlap in a plan view is small.
  • the second terminal electrode 32 and the formation region of the coil conductors 21 to 24 having a large potential difference are separated from each other. Therefore, the second terminal electrode 32 and the coil conductors (21 to 21) represented by the circuit symbol of the capacitor in FIG. 24, 62 to 64) are small in stray capacitance. Further, since the potential difference between the first terminal electrode 31 and the in-plane coil conductor 24 is small, the stray capacitance generated between them is also small. Although stray capacitance tends to occur between the first terminal electrode 31 and the in-plane coil conductors 23 to 21, the in-plane coil conductors 23 to 21 are stacked on the first terminal electrode 31.
  • the stray capacitance generated between the coil conductors 23 to 21 and the first terminal electrode 31 is also small.
  • the in-plane coil conductor 24 is interposed between the in-plane coil conductor 23 and the first terminal electrode 31, the stray capacitance generated between the in-plane coil conductor 23 and the first terminal electrode 31 is reduced. The same applies to the in-plane coil conductors 22 and 21.
  • the manufacturing method of the inductance 101 is as follows. (1) The LCP film laminated with Cu foil is patterned by photolithography. (2) A hole formed by laser processing is formed at the position where the interlayer connection conductors 41, 45 to 48, 62 to 64 are formed, and the hole is filled with a conductive paste containing Su, Cu, Ni, Ag soot and the like. (3) The base material layers are laminated and integrated by heating and pressing, and the interlayer connection conductor is solidified and electrically connected to the Cu foil. (4) Dividing into individual pieces to obtain individual chip type inductors.
  • FIG. 4 is an exploded plan view of the inductor 102 according to the second embodiment.
  • the formation position of the interlayer connection conductor 41 is different from that of the first embodiment.
  • An in-plane coil conductor 24 and an auxiliary conductor 71 are formed on the base material layer 14.
  • the interlayer connection conductor 41 is electrically connected to the connection portion between the in-plane coil conductor 24 and the auxiliary conductor 71. That is, the auxiliary conductor 71 is electrically connected to both the coil conductors (21 to 24, 62 to 64) and the first terminal electrode 31.
  • the auxiliary conductor 71 is disposed so as to overlap the first terminal electrode 31 in plan view.
  • the auxiliary conductor 71 is formed to extend in the longitudinal direction of the first terminal electrode 31.
  • the auxiliary conductor 71 is electrically connected to the in-plane coil conductor 24 at one end, but the other end is opened (having an open end) and thus does not act as a part of the coil conductor.
  • the configuration of the other parts is the same as that of the inductor 101 shown in the first embodiment.
  • the auxiliary conductor 71 since the auxiliary conductor 71 has the same potential as the first terminal electrode 31, the stray capacitance that is to be generated between the first terminal electrode 31 and a part of the in-plane coil conductor 23 is the auxiliary conductor. It is shielded by 71 and its stray capacitance is suppressed. Although stray capacitance is also generated between the auxiliary conductor 71 and the in-plane coil conductor 23, the auxiliary conductor 71 is entirely at the same potential as the first terminal electrode 31. Is smaller than the capacitance generated between the in-plane coil conductors 24 to 23 shown in FIG. 2 in the first embodiment.
  • the number of turns of the coil conductor is somewhat reduced, but the stray capacitance can be further suppressed.
  • FIG. 5 is an exploded plan view of the inductor 103 according to the third embodiment. Similar to the inductors shown in the first and second embodiments, the inductor 103 includes a laminated body in which insulating base layers 11 to 15 are laminated and integrated. A coil conductor, a terminal electrode, and a connection conductor that connects the coil conductor and the terminal electrode are formed on the laminate.
  • the in-plane coil conductors 21, 22, 23, 24, and 25 are formed on the lower surfaces of the base material layers 11, 12, 13, 14, and 15, respectively.
  • Interlayer coil conductors 62, 63, 64, and 65 are formed on the base material layers 12, 13, 14, and 15, respectively.
  • the interlayer coil conductor 62 connects one ends of the in-plane coil conductors 21 and 22,
  • the interlayer coil conductor 63 connects one ends of the in-plane coil conductors 22 and 23
  • the interlayer coil conductor 64 connects the in-plane coil conductors 23 and 24.
  • the inter-layer coil conductor 65 connects one ends of the in-plane coil conductors 24 and 25 to each other.
  • the coil conductor is constituted by the in-plane coil conductors 21, 22, 23, 24, 25 and the interlayer coil conductors 62, 63, 64, 65.
  • the first terminal electrode 31 and the second terminal electrode 32 are formed on the lower surface of the base material layer 15, respectively.
  • an in-plane connection conductor 55 that connects the first terminal electrode 31 and the end of the in-plane coil conductor 25 in the plane is formed on the base material layer 15. That is, a portion of the connection conductor that connects the coil conductor and the first terminal electrode 31 is configured by the in-plane connection conductor 55.
  • An in-plane connection conductor 51 continuous from the in-plane coil conductor 21 is formed on the lower surface of the base material layer 11.
  • Interlayer connection conductors 45, 46, 47 and 48 are formed on the base material layers 12, 13, 14 and 15. These interlayer connection conductors 45 to 48 connect the end portion of the in-plane connection conductor 51 and the second terminal electrode 32.
  • the portion of the connection conductor that connects the coil conductor and the second terminal electrode 32 is constituted by the in-plane connection conductor 51 and the interlayer connection conductors 45 to 48.
  • the path length from the first terminal electrode 31 to the in-plane coil conductor 25 (the length of the in-plane connection conductor 55) is the path length from the second terminal electrode 32 to the in-plane coil conductor 21 (interlayer connection conductors 45 to 45). 48 in the layer direction and the length of the in-plane connection conductor 51).
  • a small inductor having a predetermined inductance can be configured.
  • FIG. 6 is an exploded plan view of the band elimination filter 104 according to the fourth embodiment.
  • the band elimination filter 104 includes a laminated body in which insulating base material layers 11 to 15 are laminated and integrated. In this example, it is used in a high frequency region such as 700 MHz to 5 GHz. Since it is necessary to increase the self-resonance frequency of the coil in the high frequency region, a low dielectric constant material such as LCP is used for the base material layer.
  • LCP low dielectric constant material
  • the band elimination filter 104 of this embodiment includes the configuration of the inductor 101 shown in FIG. 2 in the first embodiment, and is formed by additionally forming an electrode and the like for forming a capacitor on the multilayer body.
  • the inductors are constituted by the coil conductors 21, 22, 23, 24 and the interlayer coil conductors 62, 63, 64, and the portions connecting the coil conductor and the second terminal electrode 32 are the in-plane connection conductor 51 and the interlayer connection conductor 45.
  • the configuration including ⁇ 48 is the same as the inductor 101 shown in FIG.
  • first lead patterns 28a and 28b drawn from the middle of the coil conductor 22 are formed.
  • An in-plane connection conductor 51 that is a second lead pattern is formed on the base material layer 11.
  • the in-plane connection conductor 51 overlaps the first lead pattern 28a in plan view. Therefore, the capacitor C2 is formed in the facing portion between the in-plane connection conductor 51 that is the second lead pattern and the first lead pattern 28a.
  • the second lead pattern 51 is drawn from a position closer to the second terminal electrode 32 on the circuit than the first lead patterns 28a and 28b.
  • the base layer 14 is formed with a third lead pattern 26 drawn from the middle of the coil conductor 24.
  • a third lead pattern 27 that is electrically connected to the third lead pattern 26 is formed on the base material layer 13.
  • the third lead patterns 26 and 27 overlap the first lead pattern 28a in plan view. Therefore, the capacitor C1 is formed in the portion where the third lead pattern 27 and the first lead pattern 28a face each other.
  • the third lead patterns 26 and 27 are drawn from a position closer to the first terminal electrode 31 on the circuit than the first lead pattern.
  • the base layer 13 is provided with a second lead pattern 29 that is connected (conducted) to the in-plane connection conductor 51 that is the second lead pattern. Further, the base layer 12 is formed with a first lead pattern 28b extending from the first lead pattern 28a. The first lead pattern 28b overlaps the second lead pattern 29 in plan view. Therefore, the capacitor C3 is formed in the portion where the first lead pattern 28b and the second lead pattern 29 are opposed to each other.
  • the coil conductor is formed in the coil conductor formation region Zt.
  • the first lead patterns 28a and 28b, the second lead patterns 51 and 29, and the third lead patterns 26 and 27 are formed outside the coil conductor formation region Zs in plan view.
  • FIG. 7 is a circuit diagram of the band elimination filter 104 shown in FIG.
  • the symbols [B1] [B2] [A1] [A2] [A3] [A4] [A5] [A6] indicate the correspondence between each part of the circuit and each part of the conductor pattern. Further, reference numerals of circuit elements are shown in FIG. 6 with parentheses. In this way, the inductors L1a, L1b, and L2 are formed by a continuous coil, and the first, second, and third lead patterns are drawn from the middle of the coil conductor, and the capacitors C1, C2, and C3 are formed by facing them. To do.
  • the third lead pattern 26 is drawn from the base material layer 14 which is the fourth layer, but in order to increase the capacity with the first lead pattern 28a, A third lead pattern 27 is formed at a position close to the first lead pattern 28 a, and the third lead patterns 26 and 27 are connected by the interlayer connection conductor 66.
  • a predetermined capacitance is obtained with a small facing area by forming the second lead pattern and the first lead pattern in a comb shape in the stacking direction.
  • the third lead patterns 26 and 27 do not overlap the second terminal electrode 32 in plan view. Therefore, the capacitor (floating capacitance) C4 generated between the second terminal electrode 32 and the third lead patterns 26 and 27 is suppressed, and is equivalently connected between the first terminal electrode 31 and the second terminal electrode 32. There are few capacitance components.
  • a first LC parallel resonant circuit is configured by the inductor L1b and the capacitor C1
  • a second LC parallel resonant circuit is configured by the inductor L2 and the capacitors C2 and C3.
  • the band elimination characteristic is obtained by the two LC parallel resonance circuits.
  • FIG. 8A and 8B are diagrams showing the results of simulating the frequency characteristics of the insertion loss of the band elimination filter 104.
  • FIG. FIG. 8A and FIG. 8B show a change in characteristics by adjusting the capacitance of the capacitor C1 and the combined capacitance of the capacitor (C2 + C3).
  • characteristic IL1 indicates a case where the value of capacitor C4 is small
  • characteristic IL2 indicates a case where the value of capacitor C4 is large.
  • a second stop band is generated with a center frequency.
  • the stop band whose insertion loss is a predetermined value or less is represented by hatching.
  • the first stop band is widened by reducing the value of the capacitor C4.
  • the first and second stop bands can be determined by adjusting the values of the capacitor C1 and the capacitor (C2 + C3).
  • FIG. 9 is an exploded plan view of the band elimination filter 105 according to the fifth embodiment.
  • This band elimination filter 105 is an example in which the first lead pattern 28b and the second lead pattern 29 shown in FIG. 6 in the fourth embodiment are omitted.
  • FIG. 10 is a circuit diagram of the band elimination filter 105. Since there is no first lead pattern 28b and second lead pattern 29, there is no capacitor C3 shown in FIG.
  • the second lead pattern may be simplified in this way.
  • the insulating base layer is not limited to resin such as LCP, but may be, for example, LTCC dielectric ceramics or magnetic ceramics.
  • the inductor can be configured on the ceramic multilayer substrate by integrally firing after the base material layers are laminated.

Abstract

Terminal electrodes (31, 32) are formed on a common base material layer (15), a coil conductor (21-24) is formed across a plurality of base material layers (11-14), and the formation region of the coil conductor in plan view has a portion overlapping with the first terminal electrode (31), and does not overlap with the second terminal electrode (32). A path length from the first terminal electrode (31) to the coil conductor (the length in the layer direction of an interlayer connection conductor (41)) is shorter than a path length from the second terminal electrode (32) to the coil conductor (the length in the layer direction of interlayer connection conductors (45-48) and the length of an in-plane connection conductor (51)).

Description

インダクタおよび帯域除去フィルタInductors and band rejection filters
　本発明は、各種電子回路に用いられる積層チップ型のインダクタおよび帯域除去フィルタに関するものである。 The present invention relates to a multilayer chip type inductor and a band elimination filter used in various electronic circuits.
　従来、積層チップ型のインダクタは、コイル導体パターンが形成された絶縁性基材が積層され、コイル導体パターンの両端が端子電極に接続された構造となっている。例えば特許文献１には、コイル導体パターンが、二つの端子電極形成位置よりもチップの中心側に配置されて、コイル導体パターンと端子電極とが平面視で重ならないように構成された積層チップインダクタが示されている。 Conventionally, a laminated chip type inductor has a structure in which an insulating base material on which a coil conductor pattern is formed is laminated, and both ends of the coil conductor pattern are connected to terminal electrodes. For example, Patent Document 1 discloses a multilayer chip inductor in which a coil conductor pattern is disposed closer to the center of a chip than two terminal electrode formation positions, and the coil conductor pattern and the terminal electrode do not overlap in plan view. It is shown.
特開２０００－１８２８３０号公報JP 2000-182830 A
　特許文献１に示されている積層チップインダクタにおいては、コイル導体パターンと端子電極との間に生じる浮遊容量が小さく、インダクタの自己共振周波数を高めることができる。 In the multilayer chip inductor disclosed in Patent Document 1, the stray capacitance generated between the coil conductor pattern and the terminal electrode is small, and the self-resonant frequency of the inductor can be increased.
　しかし、特許文献１に示されている構造によれば、コイル導体パターンを形成する領域が限られるので、素子のサイズ当たりに得られるインダクタンスが小さくなる、という課題がある。また、インダクタを含むフィルタについても同様の課題がある。 However, according to the structure shown in Patent Document 1, there is a problem that an inductance obtained per element size is reduced because a region where a coil conductor pattern is formed is limited. There is a similar problem with a filter including an inductor.
　本発明の目的は、浮遊容量を抑制しながら、インダクタンスが小さくなるのを抑制することのできるインダクタおよび帯域除去フィルタを提供することにある。 An object of the present invention is to provide an inductor and a band elimination filter that can suppress a decrease in inductance while suppressing stray capacitance.
　本発明のインダクタは、
　コイル導体、端子電極、および前記コイル導体と前記端子電極とを接続する接続導体が、複数の基材層の積層体に形成され、
　前記端子電極は共通の実装面に形成された第１端子電極および第２端子電極を含み、
　前記コイル導体は複数の前記基材層に亘って形成され、
　前記コイル導体の形成領域は、平面視で前記第１端子電極と重なる部分を有し、且つ前記第２端子電極とは重ならず、
　前記第１端子電極から前記コイル導体までの経路長は前記第２端子電極から前記コイル導体までの経路長よりも短いことを特徴とする。 The inductor of the present invention is
Coil conductors, terminal electrodes, and connection conductors connecting the coil conductors and the terminal electrodes are formed in a laminate of a plurality of base material layers,
The terminal electrode includes a first terminal electrode and a second terminal electrode formed on a common mounting surface,
The coil conductor is formed across a plurality of the base material layers,
The formation region of the coil conductor has a portion that overlaps the first terminal electrode in a plan view, and does not overlap the second terminal electrode.
The path length from the first terminal electrode to the coil conductor is shorter than the path length from the second terminal electrode to the coil conductor.
　上記構成により、第１端子電極とコイル導体との間には浮遊容量が殆ど生じることがなく、第２端子電極とコイル導体との間に生じる浮遊容量は低減されるので、浮遊容量の小さなインダクタが構成される。また、平面視でコイル導体と第１端子電極とが重なる分、コイル導体の形成領域が比較的大きいので、インダクタンスが小さくなるのを抑制できる。 With the above configuration, almost no stray capacitance is generated between the first terminal electrode and the coil conductor, and stray capacitance generated between the second terminal electrode and the coil conductor is reduced. Is configured. In addition, since the coil conductor is formed in a relatively large area as the coil conductor and the first terminal electrode overlap in a plan view, it is possible to suppress the inductance from being reduced.
　前記コイル導体は、前記複数の基材層の積層方向において前記端子電極が形成された実装面から離れる方向に向かって周回しながら延伸するように、前記複数の基材層に亘って形成されており、
　前記接続導体のうち、前記第２端子電極と前記コイル導体とを接続する部分は、前記コイル導体のうち、前記積層方向において前記実装面から最も離れた部分と前記第２端子電極とを接続する構成であることが好ましい。上記構成により、コイル導体の巻回数を容易に増やすことができる。 The coil conductor is formed across the plurality of base material layers so as to extend in a direction away from the mounting surface on which the terminal electrodes are formed in the stacking direction of the plurality of base material layers. And
A portion of the connection conductor that connects the second terminal electrode and the coil conductor connects a portion of the coil conductor that is farthest from the mounting surface in the stacking direction to the second terminal electrode. A configuration is preferred. With the above configuration, the number of turns of the coil conductor can be easily increased.
　前記コイル導体と前記第１端子電極との間には、第１端子電極に導通する補助導体を備えることが好ましい。この構成により、第１端子電極とコイル導体の一部との間に生じようとする浮遊容量は補助導体で遮蔽されるので、浮遊容量が抑制される。 It is preferable that an auxiliary conductor conducting to the first terminal electrode is provided between the coil conductor and the first terminal electrode. With this configuration, stray capacitance that is to be generated between the first terminal electrode and a part of the coil conductor is shielded by the auxiliary conductor, and thus stray capacitance is suppressed.
　前記コイル導体の一部は、端子電極と同一面で、且つ、第１端子電極および第２端子電極の間に形成されることが好ましい。この構成により、少ない基材層の層数でコイル導体の巻回数を増やすことができる。 It is preferable that a part of the coil conductor is formed on the same plane as the terminal electrode and between the first terminal electrode and the second terminal electrode. With this configuration, the number of turns of the coil conductor can be increased with a small number of base material layers.
　前記複数の基材層に形成されたコイル導体は、平面視で実質的に同一経路を周回するパターンであることが好ましい。この構成により、コイル導体のうち、第１端子電極から離れた基材層に形成されるコイル導体は、第１端子電極に近い基材層に形成されるコイル導体で遮られるので、第１端子電極とコイル導体パターンとの間に生じる浮遊容量が抑制される。 It is preferable that the coil conductors formed on the plurality of base material layers have a pattern that goes around substantially the same path in a plan view. With this configuration, the coil conductor formed on the base material layer away from the first terminal electrode among the coil conductors is blocked by the coil conductor formed on the base material layer close to the first terminal electrode. The stray capacitance generated between the electrode and the coil conductor pattern is suppressed.
　前記コイル導体の形成領域は平面視で実質的に矩形状であり、
　前記第１端子電極および前記第２端子電極は実質的に矩形状であり、
　前記コイル導体の形成領域の第１辺は、平面視で前記第１端子電極の長手方向に重なり、
　前記コイル導体の形成領域の第１辺に対向する第２辺は前記第２端子電極の長手方向と平行であることが好ましい。この構成により、コイル導体と第２端子電極との距離を確保しつつ、平面視で第２端子電極と重ならない領域の実質的に全体を周回する（すなわちコイル導体形成領域の面積が大きい）コイル導体が形成される。そのため、浮遊容量を抑制しつつ、インダクタンスが小さくなるのを抑制できる。 The formation area of the coil conductor is substantially rectangular in plan view,
The first terminal electrode and the second terminal electrode are substantially rectangular;
The first side of the coil conductor formation region overlaps in the longitudinal direction of the first terminal electrode in plan view,
It is preferable that the second side facing the first side of the coil conductor forming region is parallel to the longitudinal direction of the second terminal electrode. With this configuration, a coil that circulates substantially the entire area that does not overlap the second terminal electrode in plan view (that is, the area of the coil conductor forming area is large) while ensuring the distance between the coil conductor and the second terminal electrode. A conductor is formed. Therefore, it is possible to suppress a decrease in inductance while suppressing stray capacitance.
　本発明の帯域除去フィルタは、上記インダクタと、このインダクタに対して並列接続されたキャパシタとを備え、
　前記キャパシタは、
　前記インダクタのコイル導体の途中から引き出された第１引き出しパターンと、
　第１引き出しパターンよりも回路上第２端子電極寄りの位置から引き出され、平面視で第１引き出しパターンに重なるように形成された第２引き出しパターンと、
　第１引き出しパターンよりも回路上第１端子電極寄りの位置から引き出され、平面視で第１引き出しパターンに重なるように形成された第３引き出しパターンとで構成され、
　第１引き出しパターン、第２引き出しパターンおよび第３引き出しパターンは、平面視でコイル導体の形成領域外に形成されることを特徴とする。 The band elimination filter of the present invention includes the inductor and a capacitor connected in parallel to the inductor,
The capacitor is
A first lead pattern drawn from the middle of the coil conductor of the inductor;
A second lead pattern that is drawn from a position closer to the second terminal electrode on the circuit than the first lead pattern, and is formed to overlap the first lead pattern in plan view;
A third lead pattern that is drawn from a position closer to the first terminal electrode on the circuit than the first lead pattern and is formed so as to overlap the first lead pattern in plan view;
The first lead pattern, the second lead pattern, and the third lead pattern are formed outside the formation region of the coil conductor in a plan view.
　上記構成により、コイル導体の形成領域以外の空いたスペースにキャパシタを形成することができ、サイズを大きくすることなく、帯域除去特性を得ることができる。 With the above configuration, the capacitor can be formed in an empty space other than the formation region of the coil conductor, and the band elimination characteristic can be obtained without increasing the size.
　前記第２引き出しパターンは前記第２端子電極と前記コイル導体とを接続する接続導体であることが好ましい。この構成により、簡素な導体パターンでコイル部とキャパシタ部を構成でき、空間利用率が高まる。 The second lead pattern is preferably a connection conductor that connects the second terminal electrode and the coil conductor. With this configuration, the coil portion and the capacitor portion can be configured with a simple conductor pattern, and the space utilization rate is increased.
　前記第３引き出しパターンは前記第２端子電極に平面視で重なっていないことが好ましい。この構成により、第２端子電極と第３引き出しパターンとの間に生じる不要な浮遊容量が抑制され、第１端子電極と第２端子電極との間に等価的に接続されるキャパシタンス成分が少なく、良好な帯域除去特性が得やすい。 It is preferable that the third lead pattern does not overlap the second terminal electrode in plan view. With this configuration, unnecessary stray capacitance generated between the second terminal electrode and the third lead pattern is suppressed, and a capacitance component that is equivalently connected between the first terminal electrode and the second terminal electrode is small. It is easy to obtain good band elimination characteristics.
　本発明によれば、第１端子電極とコイル導体との間には浮遊容量が殆ど生じることがなく、第２端子電極とコイル導体との間に生じる浮遊容量は低減されるので、浮遊容量の小さなインダクタが構成される。コイル導体の形成領域は比較的大きいので、全体に大型化することなく所望のインダクタンスが得られる。また、小型の帯域除去フィルタが得られる。 According to the present invention, there is almost no stray capacitance between the first terminal electrode and the coil conductor, and the stray capacitance generated between the second terminal electrode and the coil conductor is reduced. A small inductor is constructed. Since the formation area of the coil conductor is relatively large, a desired inductance can be obtained without increasing the overall size. In addition, a small band elimination filter can be obtained.
図１は第１の実施形態に係るインダクタ１０１の分解斜視図である。FIG. 1 is an exploded perspective view of an inductor 101 according to the first embodiment. 図２はインダクタ１０１の各基材層の分解平面図である。FIG. 2 is an exploded plan view of each base material layer of the inductor 101. 図３は、図２中において一点鎖線で示す位置でのインダクタ１０１の断面図である。FIG. 3 is a cross-sectional view of inductor 101 at the position indicated by the alternate long and short dash line in FIG. 図４は第２の実施形態に係るインダクタ１０２の分解平面図である。FIG. 4 is an exploded plan view of the inductor 102 according to the second embodiment. 図５は第３の実施形態に係るインダクタ１０３の分解平面図である。FIG. 5 is an exploded plan view of the inductor 103 according to the third embodiment. 図６は第４の実施形態に係る帯域除去フィルタ１０４の分解平面図である。FIG. 6 is an exploded plan view of the band elimination filter 104 according to the fourth embodiment. 図７は図６に示した帯域除去フィルタ１０４の回路図である。FIG. 7 is a circuit diagram of the band elimination filter 104 shown in FIG. 図８（Ａ）（Ｂ）は帯域除去フィルタ１０４の挿入損失の周波数特性をシミュレーションした結果を示す図である。8A and 8B are diagrams showing the results of simulating the frequency characteristics of the insertion loss of the band elimination filter 104. FIG. 図９は第５の実施形態に係る帯域除去フィルタ１０５の分解平面図である。FIG. 9 is an exploded plan view of the band elimination filter 105 according to the fifth embodiment. 図１０は帯域除去フィルタ１０５の回路図である。FIG. 10 is a circuit diagram of the band elimination filter 105.
　以降、図を参照して幾つかの具体的な例を挙げて、本発明を実施するための複数の形態を示す。各図中には同一箇所に同一符号を付す。各実施形態は例示であり、異なる実施形態で示した構成の部分的な置換または組み合わせが可能であることは言うまでもない。 Hereinafter, several specific examples will be given with reference to the drawings to show a plurality of modes for carrying out the present invention. In the drawings, the same reference numerals are given to the same portions. Each embodiment is an exemplification, and needless to say, partial replacement or combination of configurations shown in different embodiments is possible.
《第１の実施形態》
　図１は第１の実施形態に係るインダクタ１０１の分解斜視図、図２はインダクタ１０１の各基材層の分解平面図である。また、図３は、図２中において一点鎖線で示す位置でのインダクタ１０１の断面図である。 << First Embodiment >>
FIG. 1 is an exploded perspective view of the inductor 101 according to the first embodiment, and FIG. 2 is an exploded plan view of each base material layer of the inductor 101. 3 is a cross-sectional view of the inductor 101 at the position indicated by the alternate long and short dash line in FIG.
　インダクタ１０１は、絶縁性の基材層１１～１５が積層一体化された積層体１０を備える。この積層体１０に、コイル導体、端子電極、および、コイル導体と端子電極とを接続する接続導体が形成される。 The inductor 101 includes a laminated body 10 in which insulating base material layers 11 to 15 are laminated and integrated. The laminated body 10 is formed with a coil conductor, a terminal electrode, and a connection conductor that connects the coil conductor and the terminal electrode.
　絶縁性の基材層１１～１５は例えばＬＣＰ樹脂（液晶ポリマー）であり、基材層１１，１２，１３，１４の下面に面内コイル導体２１，２２，２３，２４がそれぞれ形成される。基材層１２，１３，１４には層間コイル導体６２，６３，６４がそれぞれ形成される。層間コイル導体６２は面内コイル導体２１，２２の一端同士を接続し、層間コイル導体６３は面内コイル導体２２，２３の一端同士を接続し、層間コイル導体６４は面内コイル導体２３，２４の一端同士を接続する。図２において、破線の円は下層の層間コイル導体との接続位置を表す。このように、コイル導体は、面内コイル導体２１，２２，２３，２４および層間コイル導体６２，６３，６４により構成される。 The insulating base layers 11 to 15 are, for example, LCP resin (liquid crystal polymer), and in- plane coil conductors 21, 22, 23, and 24 are formed on the lower surfaces of the base layers 11, 12, 13, and 14, respectively. Interlayer coil conductors 62, 63, and 64 are formed on the base material layers 12, 13, and 14, respectively. The interlayer coil conductor 62 connects one ends of the in- plane coil conductors 21 and 22, the interlayer coil conductor 63 connects one ends of the in- plane coil conductors 22 and 23, and the interlayer coil conductor 64 connects the in- plane coil conductors 23 and 24. Connect one end of each other. In FIG. 2, a broken-line circle represents a connection position with a lower interlayer coil conductor. Thus, the coil conductor is constituted by the in- plane coil conductors 21, 22, 23, 24 and the interlayer coil conductors 62, 63, 64.
　基材層１５の下面には第１端子電極３１、第２端子電極３２がそれぞれ形成される。また、この基材層１５には、基材層１４に形成される面内コイル導体２４の端部と第１端子電極３１とを層間接続する層間接続導体４１が形成される。すなわち、接続導体のうち、面内コイル導体と第１端子電極３１とを接続する部分は、層間接続導体４１により構成される。 The first terminal electrode 31 and the second terminal electrode 32 are formed on the lower surface of the base material layer 15, respectively. In addition, an interlayer connection conductor 41 is formed on the base material layer 15 to connect the end portion of the in-plane coil conductor 24 formed on the base material layer 14 and the first terminal electrode 31. That is, the portion of the connection conductor that connects the in-plane coil conductor and the first terminal electrode 31 is configured by the interlayer connection conductor 41.
　基材層１１の下面には面内コイル導体２１から連続する面内接続導体５１が形成される。基材層１２，１３，１４，１５には、層間接続導体４５，４６，４７，４８が形成される。これら層間接続導体４５～４８は面内接続導体５１の端部と第２端子電極３２とを接続する。すなわち、接続導体のうち、コイル導体（面内コイル導体２１，２２，２３，２４および層間コイル導体６２，６３，６４）と第２端子電極３２とを接続する部分は、面内接続導体５１および層間接続導体４５～４８により構成される。 An in-plane connection conductor 51 continuous from the in-plane coil conductor 21 is formed on the lower surface of the base material layer 11. Interlayer connection conductors 45, 46, 47 and 48 are formed on the base material layers 12, 13, 14 and 15. These interlayer connection conductors 45 to 48 connect the end portion of the in-plane connection conductor 51 and the second terminal electrode 32. That is, of the connection conductors, the portions connecting the coil conductors (in- plane coil conductors 21, 22, 23, 24 and interlayer coil conductors 62, 63, 64) and the second terminal electrode 32 are the in-plane connection conductor 51 and It is composed of interlayer connection conductors 45-48.
　このように、コイル導体は、複数の基材層１１～１５の積層方向において、端子電極が形成された実装面から離れる方向に向かって周回しながら延伸するように、複数の基材層１４～１１に亘って形成される。そして、接続導体のうち、第２端子電極３２とコイル導体とを接続する部分は、コイル導体のうち、積層方向において実装面から最も離れた部分と第２端子電極３２とを接続する。 In this way, the coil conductor extends in the stacking direction of the plurality of base material layers 11 to 15 while rotating around the direction away from the mounting surface on which the terminal electrodes are formed. 11 is formed. A portion of the connecting conductor that connects the second terminal electrode 32 and the coil conductor connects the portion of the coil conductor that is farthest from the mounting surface in the stacking direction to the second terminal electrode 32.
　図２に二点鎖線の囲みで示すように、平面視での（基材層１１～１５の積層方向に視て）、コイル導体２１～２４，６２～６４の形成領域は矩形状である。また、複数の基材層１１～１４に形成された面内コイル導体２１～２４は、平面視で矩形の同一経路を周回する。このコイル導体の形成領域の第１辺は第１端子電極３１と重なる。コイル導体の形成領域は第２端子電極３２とは重ならず、コイル導体の形成領域の第１辺に対向する第２辺は第２端子電極３２の長手方向と平行である。すなわち、図２において二点鎖線の囲みで示すコイル導体の形成領域は第２端子電極３２より第１端子電極３１の方へ寄る。そして、第１端子電極３１から面内コイル導体２４までの経路長（層間接続導体４１の層方向長さ）は、第２端子電極３２から面内コイル導体２１までの経路長（層間接続導体４５～４８の層方向長さおよび面内接続導体５１の長さ）よりも短い。 As shown by the two-dot chain line in FIG. 2, the formation regions of the coil conductors 21 to 24 and 62 to 64 in a plan view (viewed in the stacking direction of the base material layers 11 to 15) are rectangular. The in-plane coil conductors 21 to 24 formed on the plurality of base material layers 11 to 14 circulate on the same rectangular path in plan view. The first side of the coil conductor formation region overlaps the first terminal electrode 31. The coil conductor formation region does not overlap the second terminal electrode 32, and the second side opposite to the first side of the coil conductor formation region is parallel to the longitudinal direction of the second terminal electrode 32. That is, in FIG. 2, the coil conductor formation region indicated by a two-dot chain line is closer to the first terminal electrode 31 than the second terminal electrode 32. The path length from the first terminal electrode 31 to the in-plane coil conductor 24 (the length in the layer direction of the interlayer connection conductor 41) is the path length from the second terminal electrode 32 to the in-plane coil conductor 21 (interlayer connection conductor 45). (The length in the layer direction of .about.48 and the length of the in-plane connecting conductor 51).
　上記構成は次のように換言できる。コイル導体２１～２４，６２～６４の形成領域が平面視で重なる第１端子電極３１に対して、これに層方向に隣接する（直上の）面内コイル導体２４が層間接続導体４１を介して最短距離で接続される。一方、第２端子電極３２に対しては、複数の基材層に形成される面内コイル導体２１～２４のうち、最も上層の面内コイル導体２１が層間接続導体４５～４８および面内接続導体５１を介して接続される。 The above configuration can be rephrased as follows. The in-plane coil conductor 24 adjacent (immediately above) in the layer direction to the first terminal electrode 31 in which the formation regions of the coil conductors 21 to 24 and 62 to 64 overlap in plan view is interposed via the interlayer connection conductor 41. Connected in the shortest distance. On the other hand, for the second terminal electrode 32, the uppermost in-plane coil conductor 21 among the in-plane coil conductors 21 to 24 formed on the plurality of base material layers is connected to the interlayer connection conductors 45 to 48 and the in-plane connection. It is connected via the conductor 51.
　層間接続導体４５～４８は、積層方向に延びる直線上に配置される。そのため、上記「接続する部分」（面内接続導体５１および層間接続導体４５～４８）と第２端子電極３２とが平面視で重なる面積は小さい。 The interlayer connection conductors 45 to 48 are arranged on a straight line extending in the stacking direction. Therefore, the area where the “connecting portion” (the in-plane connection conductor 51 and the interlayer connection conductors 45 to 48) and the second terminal electrode 32 overlap in a plan view is small.
　このように、電位差が大きな、第２端子電極３２とコイル導体２１～２４の形成領域とが互いに離れるので、図２中にキャパシタの回路記号で表す、第２端子電極３２とコイル導体（２１～２４，６２～６４）との間に生じる浮遊容量は小さい。また、第１端子電極３１と面内コイル導体２４とは電位差が小さいので、その間に生じる浮遊容量も小さい。なお、第１端子電極３１と面内コイル導体２３～２１との間に浮遊容量が生じようとするが、これら面内コイル導体２３～２１は第１端子電極３１の上に積み重なるので、面内コイル導体２３～２１と第１端子電極３１との間に生じる浮遊容量も小さい。例えば、面内コイル導体２３と第１端子電極３１との間には面内コイル導体２４が介在するので、面内コイル導体２３と第１端子電極３１との間に生じる浮遊容量は小さくなる。面内コイル導体２２，２１についても同様である。 In this way, the second terminal electrode 32 and the formation region of the coil conductors 21 to 24 having a large potential difference are separated from each other. Therefore, the second terminal electrode 32 and the coil conductors (21 to 21) represented by the circuit symbol of the capacitor in FIG. 24, 62 to 64) are small in stray capacitance. Further, since the potential difference between the first terminal electrode 31 and the in-plane coil conductor 24 is small, the stray capacitance generated between them is also small. Although stray capacitance tends to occur between the first terminal electrode 31 and the in-plane coil conductors 23 to 21, the in-plane coil conductors 23 to 21 are stacked on the first terminal electrode 31. The stray capacitance generated between the coil conductors 23 to 21 and the first terminal electrode 31 is also small. For example, since the in-plane coil conductor 24 is interposed between the in-plane coil conductor 23 and the first terminal electrode 31, the stray capacitance generated between the in-plane coil conductor 23 and the first terminal electrode 31 is reduced. The same applies to the in- plane coil conductors 22 and 21.
　上記インダクタンス１０１の製造方法は次のとおりである。（１）Cu箔がラミネートされたLCPフィルムをフォトリソグラフィによりパターンニングする。（２）層間接続導体４１，４５～４８，６２～６４の形成位置にレーザー加工による孔を形成し、その孔にSu,Cu,Ni,Ag 等を含む導電性ペーストを充填する。（３）各基材層を積層し、加熱プレスすることで一体化するとともに、層間接続導体の固化およびCu箔との電気的導通を図る。（４）個片に分割して、個々のチップ型インダクタを得る。 The manufacturing method of the inductance 101 is as follows. (1) The LCP film laminated with Cu foil is patterned by photolithography. (2) A hole formed by laser processing is formed at the position where the interlayer connection conductors 41, 45 to 48, 62 to 64 are formed, and the hole is filled with a conductive paste containing Su, Cu, Ni, Ag soot and the like. (3) The base material layers are laminated and integrated by heating and pressing, and the interlayer connection conductor is solidified and electrically connected to the Cu foil. (4) Dividing into individual pieces to obtain individual chip type inductors.
《第２の実施形態》
　図４は第２の実施形態に係るインダクタ１０２の分解平面図である。第１の実施形態とは、層間接続導体４１の形成位置が異なる。基材層１４には面内コイル導体２４および補助導体７１が形成される。この面内コイル導体２４と補助導体７１との接続部に層間接続導体４１が導通する。すなわち、補助導体７１は、コイル導体（２１～２４，６２～６４）および第１端子電極３１の両方に導通する。補助導体７１は、平面視で第１端子電極３１に重なるように配置される。また、補助導体７１は、第１端子電極３１の長手方向に延びるように形成される。なお、補助導体７１は面内コイル導体２４と一方端部で導通するが、他方端部が開放される（開放端を有する）ため、コイル導体の一部としては作用しない。他の部分の構成は、第１の実施形態で示したインダクタ１０１と同じである。 << Second Embodiment >>
FIG. 4 is an exploded plan view of the inductor 102 according to the second embodiment. The formation position of the interlayer connection conductor 41 is different from that of the first embodiment. An in-plane coil conductor 24 and an auxiliary conductor 71 are formed on the base material layer 14. The interlayer connection conductor 41 is electrically connected to the connection portion between the in-plane coil conductor 24 and the auxiliary conductor 71. That is, the auxiliary conductor 71 is electrically connected to both the coil conductors (21 to 24, 62 to 64) and the first terminal electrode 31. The auxiliary conductor 71 is disposed so as to overlap the first terminal electrode 31 in plan view. The auxiliary conductor 71 is formed to extend in the longitudinal direction of the first terminal electrode 31. The auxiliary conductor 71 is electrically connected to the in-plane coil conductor 24 at one end, but the other end is opened (having an open end) and thus does not act as a part of the coil conductor. The configuration of the other parts is the same as that of the inductor 101 shown in the first embodiment.
　本実施形態によれば、補助導体７１は第１端子電極３１と同電位であるので、第１端子電極３１と面内コイル導体２３の一部との間に生じようとする浮遊容量は補助導体７１で遮蔽され、その浮遊容量は抑制される。なお、補助導体７１と面内コイル導体２３との間にも浮遊容量は生じるが、補助導体７１はその全体が第１端子電極３１と同電位であるので、補助導体７１と面内コイル導体２３との間に生じる容量は、第１の実施形態で図２に示した面内コイル導体２４－２３間に生じる容量より小さい。 According to this embodiment, since the auxiliary conductor 71 has the same potential as the first terminal electrode 31, the stray capacitance that is to be generated between the first terminal electrode 31 and a part of the in-plane coil conductor 23 is the auxiliary conductor. It is shielded by 71 and its stray capacitance is suppressed. Although stray capacitance is also generated between the auxiliary conductor 71 and the in-plane coil conductor 23, the auxiliary conductor 71 is entirely at the same potential as the first terminal electrode 31. Is smaller than the capacitance generated between the in-plane coil conductors 24 to 23 shown in FIG. 2 in the first embodiment.
　本実施形態によれば、コイル導体の巻回数が多少少なくなるが、浮遊容量をさらに抑制できる。 According to the present embodiment, the number of turns of the coil conductor is somewhat reduced, but the stray capacitance can be further suppressed.
《第３の実施形態》
　図５は第３の実施形態に係るインダクタ１０３の分解平面図である。このインダクタ１０３は、第１、第２の実施形態で示したインダクタと同様に、絶縁性の基材層１１～１５が積層一体化された積層体を備える。この積層体に、コイル導体、端子電極、およびコイル導体と端子電極とを接続する接続導体が形成される。 << Third Embodiment >>
FIG. 5 is an exploded plan view of the inductor 103 according to the third embodiment. Similar to the inductors shown in the first and second embodiments, the inductor 103 includes a laminated body in which insulating base layers 11 to 15 are laminated and integrated. A coil conductor, a terminal electrode, and a connection conductor that connects the coil conductor and the terminal electrode are formed on the laminate.
　基材層１１，１２，１３，１４，１５の下面に面内コイル導体２１，２２，２３，２４，２５がそれぞれ形成される。基材層１２，１３，１４，１５には層間コイル導体６２，６３，６４，６５がそれぞれ形成される。層間コイル導体６２は面内コイル導体２１，２２の一端同士を接続し、層間コイル導体６３は面内コイル導体２２，２３の一端同士を接続し、層間コイル導体６４は面内コイル導体２３，２４の一端同士を接続し、層間コイル導体６５は面内コイル導体２４，２５の一端同士を接続する。このように、コイル導体は、面内コイル導体２１，２２，２３，２４，２５および層間コイル導体６２，６３，６４，６５により構成される。 The in- plane coil conductors 21, 22, 23, 24, and 25 are formed on the lower surfaces of the base material layers 11, 12, 13, 14, and 15, respectively. Interlayer coil conductors 62, 63, 64, and 65 are formed on the base material layers 12, 13, 14, and 15, respectively. The interlayer coil conductor 62 connects one ends of the in- plane coil conductors 21 and 22, the interlayer coil conductor 63 connects one ends of the in- plane coil conductors 22 and 23, and the interlayer coil conductor 64 connects the in- plane coil conductors 23 and 24. Are connected to each other, and the inter-layer coil conductor 65 connects one ends of the in- plane coil conductors 24 and 25 to each other. Thus, the coil conductor is constituted by the in- plane coil conductors 21, 22, 23, 24, 25 and the interlayer coil conductors 62, 63, 64, 65.
　基材層１５の下面には第１端子電極３１、第２端子電極３２がそれぞれ形成される。また、この基材層１５には、第１端子電極３１と面内コイル導体２５の端部とを面内で接続する面内接続導体５５が形成される。すなわち、接続導体のうち、コイル導体と第１端子電極３１とを接続する部分は、面内接続導体５５により構成される。 The first terminal electrode 31 and the second terminal electrode 32 are formed on the lower surface of the base material layer 15, respectively. In addition, an in-plane connection conductor 55 that connects the first terminal electrode 31 and the end of the in-plane coil conductor 25 in the plane is formed on the base material layer 15. That is, a portion of the connection conductor that connects the coil conductor and the first terminal electrode 31 is configured by the in-plane connection conductor 55.
　基材層１１の下面には面内コイル導体２１から連続する面内接続導体５１が形成される。基材層１２，１３，１４，１５には、層間接続導体４５，４６，４７，４８が形成される。これら層間接続導体４５～４８は面内接続導体５１の端部と第２端子電極３２とを接続する。このように、接続導体のうち、コイル導体と第２端子電極３２とを接続する部分は、面内接続導体５１および層間接続導体４５～４８により構成される。そして、第１端子電極３１から面内コイル導体２５までの経路長（面内接続導体５５の長さ）は、第２端子電極３２から面内コイル導体２１までの経路長（層間接続導体４５～４８の層方向長さおよび面内接続導体５１の長さ）よりも短い。 An in-plane connection conductor 51 continuous from the in-plane coil conductor 21 is formed on the lower surface of the base material layer 11. Interlayer connection conductors 45, 46, 47 and 48 are formed on the base material layers 12, 13, 14 and 15. These interlayer connection conductors 45 to 48 connect the end portion of the in-plane connection conductor 51 and the second terminal electrode 32. As described above, the portion of the connection conductor that connects the coil conductor and the second terminal electrode 32 is constituted by the in-plane connection conductor 51 and the interlayer connection conductors 45 to 48. The path length from the first terminal electrode 31 to the in-plane coil conductor 25 (the length of the in-plane connection conductor 55) is the path length from the second terminal electrode 32 to the in-plane coil conductor 21 (interlayer connection conductors 45 to 45). 48 in the layer direction and the length of the in-plane connection conductor 51).
　このように、基材層１５の第１端子電極３１および第２端子電極３２の間にコイル導体の一部が形成される。 Thus, a part of the coil conductor is formed between the first terminal electrode 31 and the second terminal electrode 32 of the base material layer 15.
　本実施形態によれば、少ない基材層でコイル導体の巻回数を増やすことができるので、所定のインダクタンスを有する小型のインダクタを構成できる。 According to this embodiment, since the number of turns of the coil conductor can be increased with a small number of base layers, a small inductor having a predetermined inductance can be configured.
《第４の実施形態》
　図６は第４の実施形態に係る帯域除去フィルタ１０４の分解平面図である。この帯域除去フィルタ１０４は、絶縁性の基材層１１～１５が積層一体化された積層体を備える。この例では700MHz～5GHzといった高周波領域で用いられる。高周波領域ではコイルの自己共振周波数を高くする必要があるので、基材層にはLCP等の低誘電率材料が用いられる。 << Fourth Embodiment >>
FIG. 6 is an exploded plan view of the band elimination filter 104 according to the fourth embodiment. The band elimination filter 104 includes a laminated body in which insulating base material layers 11 to 15 are laminated and integrated. In this example, it is used in a high frequency region such as 700 MHz to 5 GHz. Since it is necessary to increase the self-resonance frequency of the coil in the high frequency region, a low dielectric constant material such as LCP is used for the base material layer.
　本実施形態の帯域除去フィルタ１０４は、第１の実施形態で図２に示したインダクタ１０１の構成を含み、積層体にキャパシタを形成するための電極等を付加形成したものである。 The band elimination filter 104 of this embodiment includes the configuration of the inductor 101 shown in FIG. 2 in the first embodiment, and is formed by additionally forming an electrode and the like for forming a capacitor on the multilayer body.
　コイル導体２１，２２，２３，２４および層間コイル導体６２，６３，６４によってインダクタが構成されること、コイル導体と第２端子電極３２とを接続する部分が面内接続導体５１および層間接続導体４５～４８により構成されること等は、図１に示したインダクタ１０１と同じである。 The inductors are constituted by the coil conductors 21, 22, 23, 24 and the interlayer coil conductors 62, 63, 64, and the portions connecting the coil conductor and the second terminal electrode 32 are the in-plane connection conductor 51 and the interlayer connection conductor 45. The configuration including ˜48 is the same as the inductor 101 shown in FIG.
　基材層１２には、コイル導体２２の途中から引き出された第１引き出しパターン２８ａ，２８ｂが形成される。基材層１１には、第２引き出しパターンである面内接続導体５１が形成される。この面内接続導体５１は、平面視で第１引き出しパターン２８ａに重なる。したがって、第２引き出しパターンである面内接続導体５１と第１引き出しパターン２８ａとの対向部分にキャパシタＣ２が構成される。後に回路図で示すように、第２引き出しパターン５１は、第１引き出しパターン２８ａ，２８ｂよりも回路上第２端子電極３２寄りの位置から引き出される。 In the base material layer 12, first lead patterns 28a and 28b drawn from the middle of the coil conductor 22 are formed. An in-plane connection conductor 51 that is a second lead pattern is formed on the base material layer 11. The in-plane connection conductor 51 overlaps the first lead pattern 28a in plan view. Therefore, the capacitor C2 is formed in the facing portion between the in-plane connection conductor 51 that is the second lead pattern and the first lead pattern 28a. As shown later in the circuit diagram, the second lead pattern 51 is drawn from a position closer to the second terminal electrode 32 on the circuit than the first lead patterns 28a and 28b.
　基材層１４には、コイル導体２４の途中から引き出された第３引き出しパターン２６が形成される。また、基材層１３には、第３引き出しパターン２６に導通する第３引き出しパターン２７が形成される。この第３引き出しパターン２６，２７は、平面視で第１引き出しパターン２８ａに重なる。したがって、第３引き出しパターン２７と第１引き出しパターン２８ａとの対向部分にキャパシタＣ１が構成される。後に回路図で示すように、第３引き出しパターン２６，２７は第１引き出しパターンよりも回路上第１端子電極３１寄りの位置から引き出される。 The base layer 14 is formed with a third lead pattern 26 drawn from the middle of the coil conductor 24. In addition, a third lead pattern 27 that is electrically connected to the third lead pattern 26 is formed on the base material layer 13. The third lead patterns 26 and 27 overlap the first lead pattern 28a in plan view. Therefore, the capacitor C1 is formed in the portion where the third lead pattern 27 and the first lead pattern 28a face each other. As shown later in the circuit diagram, the third lead patterns 26 and 27 are drawn from a position closer to the first terminal electrode 31 on the circuit than the first lead pattern.
　基材層１３には、第２引き出しパターンである面内接続導体５１に繋がる（導通する）第２引き出しパターン２９が形成される。また、基材層１２には、第１引き出しパターン２８ａから延びる第１引き出しパターン２８ｂが形成される。第１引き出しパターン２８ｂは平面視で第２引き出しパターン２９に重なる。したがって、第１引き出しパターン２８ｂと第２引き出しパターン２９との対向部分にキャパシタＣ３が構成される。 The base layer 13 is provided with a second lead pattern 29 that is connected (conducted) to the in-plane connection conductor 51 that is the second lead pattern. Further, the base layer 12 is formed with a first lead pattern 28b extending from the first lead pattern 28a. The first lead pattern 28b overlaps the second lead pattern 29 in plan view. Therefore, the capacitor C3 is formed in the portion where the first lead pattern 28b and the second lead pattern 29 are opposed to each other.
　上記コイル導体は、コイル導体形成領域Ｚｔに形成される。第１引き出しパターン２８ａ，２８ｂ、第２引き出しパターン５１，２９および第３引き出しパターン２６，２７は、平面視でコイル導体の形成領域外Ｚｓに形成される。 The coil conductor is formed in the coil conductor formation region Zt. The first lead patterns 28a and 28b, the second lead patterns 51 and 29, and the third lead patterns 26 and 27 are formed outside the coil conductor formation region Zs in plan view.
　図７は図６に示した帯域除去フィルタ１０４の回路図である。図６、図７において、符号[B1][B2][A1][A2][A3][A4][A5][A6] は回路各部と導体パターン各部との対応関係を示すものである。また、回路素子の符号を括弧付きで図６に表す。このように、インダクタＬ１ａ，Ｌ１ｂ，Ｌ２を一続きのコイルで構成し、コイル導体の途中から第１、第２、第３の引き出しパターンを引き出し、それらの対向によってキャパシタＣ１，Ｃ２，Ｃ３を構成する。 FIG. 7 is a circuit diagram of the band elimination filter 104 shown in FIG. In FIGS. 6 and 7, the symbols [B1] [B2] [A1] [A2] [A3] [A4] [A5] [A6] indicate the correspondence between each part of the circuit and each part of the conductor pattern. Further, reference numerals of circuit elements are shown in FIG. 6 with parentheses. In this way, the inductors L1a, L1b, and L2 are formed by a continuous coil, and the first, second, and third lead patterns are drawn from the middle of the coil conductor, and the capacitors C1, C2, and C3 are formed by facing them. To do.
　本実施形態では、特に低誘電率基板を用いるので、大きな容量を確保するため、次の工夫をしている。 In this embodiment, since a low dielectric constant substrate is used in particular, the following measures are taken to ensure a large capacity.
(1) インダクタＬ１のインダクタンスを確保するために、第３引き出しパターン２６は、第４層である基材層１４から引き出されるが、第１引き出しパターン２８ａとの間での容量を大きくするため、第１引き出しパターン２８ａに近い位置に第３引き出しパターン２７が形成され、第３引き出しパターン２６と２７とが層間接続導体６６で接続される。 (1) In order to secure the inductance of the inductor L1, the third lead pattern 26 is drawn from the base material layer 14 which is the fourth layer, but in order to increase the capacity with the first lead pattern 28a, A third lead pattern 27 is formed at a position close to the first lead pattern 28 a, and the third lead patterns 26 and 27 are connected by the interlayer connection conductor 66.
(2) 第２引き出しパターンと第１引き出しパターンとを、積層方向で櫛状に形成することにより、小さな対向面積で所定のキャパシタンスを得る。 (2) A predetermined capacitance is obtained with a small facing area by forming the second lead pattern and the first lead pattern in a comb shape in the stacking direction.
　なお、第３引き出しパターン２６，２７は第２端子電極３２に平面視で重なっていない。そのため、第２端子電極３２と第３引き出しパターン２６，２７との間に生じるキャパシタ（浮遊容量）Ｃ４が抑制され、第１端子電極３１と第２端子電極３２との間に等価的に接続されるキャパシタンス成分は少ない。 The third lead patterns 26 and 27 do not overlap the second terminal electrode 32 in plan view. Therefore, the capacitor (floating capacitance) C4 generated between the second terminal electrode 32 and the third lead patterns 26 and 27 is suppressed, and is equivalently connected between the first terminal electrode 31 and the second terminal electrode 32. There are few capacitance components.
　図７において、インダクタＬ１ｂおよびキャパシタＣ１によって第１のＬＣ並列共振回路、インダクタＬ２およびキャパシタＣ２，Ｃ３によって第２のＬＣ並列共振回路がそれぞれ構成される。そして、この２つのＬＣ並列共振回路によって帯域除去特性を得る。 7, a first LC parallel resonant circuit is configured by the inductor L1b and the capacitor C1, and a second LC parallel resonant circuit is configured by the inductor L2 and the capacitors C2 and C3. The band elimination characteristic is obtained by the two LC parallel resonance circuits.
　図８（Ａ）（Ｂ）は上記帯域除去フィルタ１０４の挿入損失の周波数特性をシミュレーションした結果を示す図である。図８（Ａ）と図８（Ｂ）とは上記キャパシタＣ１のキャパシタンスとキャパシタ（Ｃ２＋Ｃ３）の合成キャパシタンスとを調整することによる特性の変化を示す。また、図８（Ａ）（Ｂ）において、特性ＩＬ１はキャパシタＣ４の値が小さい場合、特性ＩＬ２はキャパシタＣ４の値が大きい場合を示す。 8A and 8B are diagrams showing the results of simulating the frequency characteristics of the insertion loss of the band elimination filter 104. FIG. FIG. 8A and FIG. 8B show a change in characteristics by adjusting the capacitance of the capacitor C1 and the combined capacitance of the capacitor (C2 + C3). 8A and 8B, characteristic IL1 indicates a case where the value of capacitor C4 is small, and characteristic IL2 indicates a case where the value of capacitor C4 is large.
　図８（Ａ）（Ｂ）に表れているように、上記第１のＬＣ並列共振回路の共振周波数ｆ１を中心周波数とする第１の阻止帯域と、第２のＬＣ並列共振回路の共振周波数ｆ２を中心周波数とする第２の阻止帯域が生じる。この例では、挿入損失が所定の値以下の阻止帯域をハッチングで表す。このように、キャパシタＣ４の値を小さくすることで、第１の阻止帯域は広くなる。また、キャパシタＣ１とキャパシタ（Ｃ２＋Ｃ３）の値を調整することにより、第１、第２の阻止帯域を定めることができる。 As shown in FIGS. 8A and 8B, the first stop band whose center frequency is the resonance frequency f1 of the first LC parallel resonance circuit, and the resonance frequency f2 of the second LC parallel resonance circuit. A second stop band is generated with a center frequency. In this example, the stop band whose insertion loss is a predetermined value or less is represented by hatching. Thus, the first stop band is widened by reducing the value of the capacitor C4. Also, the first and second stop bands can be determined by adjusting the values of the capacitor C1 and the capacitor (C2 + C3).
《第５の実施形態》
　図９は第５の実施形態に係る帯域除去フィルタ１０５の分解平面図である。この帯域除去フィルタ１０５は、第４の実施形態で図６に示した第１引き出しパターン２８ｂおよび第２引き出しパターン２９を省略した例である。 << Fifth Embodiment >>
FIG. 9 is an exploded plan view of the band elimination filter 105 according to the fifth embodiment. This band elimination filter 105 is an example in which the first lead pattern 28b and the second lead pattern 29 shown in FIG. 6 in the fourth embodiment are omitted.
　図１０は上記帯域除去フィルタ１０５の回路図である。第１引き出しパターン２８ｂおよび第２引き出しパターン２９が無いので、図７に示したキャパシタＣ３は無い。 FIG. 10 is a circuit diagram of the band elimination filter 105. Since there is no first lead pattern 28b and second lead pattern 29, there is no capacitor C3 shown in FIG.
　インダクタＬ２とともにＬＣ並列共振回路を構成するキャパシタのキャパシタンスに応じては、このように、第２引き出しパターンを単純化してもよい。 Depending on the capacitance of the capacitor that constitutes the LC parallel resonant circuit together with the inductor L2, the second lead pattern may be simplified in this way.
　なお、絶縁性の基材層はLCP等の樹脂に限らず、例えばLTCCの誘電体セラミックスまたは磁性体セラミックスであってもよい。この場合、基材層の積層後、一体焼成することによって、セラミックス多層基板にインダクタを構成することができる。 The insulating base layer is not limited to resin such as LCP, but may be, for example, LTCC dielectric ceramics or magnetic ceramics. In this case, the inductor can be configured on the ceramic multilayer substrate by integrally firing after the base material layers are laminated.
Ｃ１，Ｃ２，Ｃ３…キャパシタ
Ｃ４…キャパシタ（浮遊容量）
Ｌ１ａ，Ｌ１ｂ，Ｌ２…インダクタ
Ｚｓ…コイル導体形成領域外
Ｚｔ…コイル導体形成領域
１０…積層体
１１～１５…基材層
２１～２５…面内コイル導体
２６，２７…第３引き出しパターン
２８ａ，２８ｂ…第１引き出しパターン
２９…第２引き出しパターン
３１…第１端子電極
３２…第２端子電極
４１，４５～４８…層間接続導体
５１…面内接続導体（第２引き出しパターン）
５５…面内接続導体
６２～６５…層間コイル導体
７１…補助導体
１０１～１０３…インダクタ
１０４，１０５…帯域除去フィルタ C1, C2, C3 ... capacitor C4 ... capacitor (floating capacitance)
L1a, L1b, L2 ... inductor Zs ... outside coil conductor formation area Zt ... coil conductor formation area 10 ... laminates 11 to 15 ... base material layers 21 to 25 ... in- plane coil conductors 26 and 27 ... third lead patterns 28a and 28b ... first lead pattern 29 ... second lead pattern 31 ... first terminal electrode 32 ... second terminal electrodes 41, 45 to 48 ... interlayer connection conductor 51 ... in-plane connection conductor (second lead pattern)
55: In-plane connection conductors 62-65 ... Interlayer coil conductor 71 ... Auxiliary conductors 101-103 ... Inductors 104, 105 ... Band elimination filter

Claims (9)

  1. 　コイル導体、端子電極、および前記コイル導体と前記端子電極とを接続する接続導体が、複数の基材層の積層体に形成され、
    　前記端子電極は共通の実装面に形成された第１端子電極および第２端子電極を含み、
    　前記コイル導体は複数の前記基材層に亘って形成され、
    　前記コイル導体の形成領域は、平面視で前記第１端子電極と重なる部分を有し、且つ前記第２端子電極とは重ならず、
    　前記第１端子電極から前記コイル導体までの経路長は前記第２端子電極から前記コイル導体までの経路長よりも短いことを特徴とするインダクタ。     Coil conductors, terminal electrodes, and connection conductors connecting the coil conductors and the terminal electrodes are formed in a laminate of a plurality of base material layers,
    The terminal electrode includes a first terminal electrode and a second terminal electrode formed on a common mounting surface,
    The coil conductor is formed across a plurality of the base material layers,
    The formation region of the coil conductor has a portion that overlaps the first terminal electrode in a plan view, and does not overlap the second terminal electrode.
    An inductor characterized in that a path length from the first terminal electrode to the coil conductor is shorter than a path length from the second terminal electrode to the coil conductor.
  2. 　前記コイル導体は、前記複数の基材層の積層方向において前記端子電極が形成された実装面から離れる方向に向かって周回しながら延伸するように、前記複数の基材層に亘って形成されており、
    　前記接続導体のうち、前記第２端子電極と前記コイル導体とを接続する部分は、前記コイル導体のうち、前記積層方向において前記実装面から最も離れた部分と前記第２端子電極とを接続する、請求項１に記載のインダクタ。     The coil conductor is formed across the plurality of base material layers so as to extend in a direction away from the mounting surface on which the terminal electrodes are formed in the stacking direction of the plurality of base material layers. And
    A portion of the connection conductor that connects the second terminal electrode and the coil conductor connects a portion of the coil conductor that is farthest from the mounting surface in the stacking direction to the second terminal electrode. The inductor according to claim 1.
  3. 　前記コイル導体と前記第１端子電極との間に形成され、前記第１端子電極に導通する補助導体を備える、請求項１または２に記載のインダクタ。 The inductor according to claim 1 or 2, further comprising an auxiliary conductor formed between the coil conductor and the first terminal electrode and conducting to the first terminal electrode.
  4. 　前記コイル導体の一部は、前記端子電極と同一面上で、且つ、前記第１端子電極および前記第２端子電極の間に形成される、請求項１～３のいずれかに記載のインダクタ。 4. The inductor according to claim 1, wherein a part of the coil conductor is formed on the same plane as the terminal electrode and between the first terminal electrode and the second terminal electrode.
  5. 　前記複数の基材層に形成された前記コイル導体は、平面視で実質的に同一経路を周回する、請求項１～４のいずれかに記載のインダクタ。 The inductor according to any one of claims 1 to 4, wherein the coil conductors formed on the plurality of base material layers circulate substantially along the same path in a plan view.
  6. 　前記コイル導体の形成領域は平面視で実質的に矩形状であり、
    　前記第１端子電極および前記第２端子電極は実質的に矩形状であり、
    　前記コイル導体の形成領域の第１辺は、平面視で前記第１端子電極の長手方向に重なり、
    　前記コイル導体の形成領域の第１辺に対向する第２辺は前記第２端子電極の長手方向と平行である、請求項１～５のいずれかに記載のインダクタ。     The formation area of the coil conductor is substantially rectangular in plan view,
    The first terminal electrode and the second terminal electrode are substantially rectangular;
    The first side of the coil conductor formation region overlaps in the longitudinal direction of the first terminal electrode in plan view,
    The inductor according to any one of claims 1 to 5, wherein a second side opposite to the first side of the coil conductor forming region is parallel to a longitudinal direction of the second terminal electrode.
  7. 　請求項１～６のいずれかに記載のインダクタと、このインダクタに対して並列接続されたキャパシタとを備え、
    　前記キャパシタは、
    　前記インダクタのコイル導体の途中から引き出された第１引き出しパターンと、
    　第１引き出しパターンよりも回路上第２端子電極寄りの位置から引き出され、平面視で第１引き出しパターンに重なるように形成された第２引き出しパターンと、
    　第１引き出しパターンよりも回路上第１端子電極寄りの位置から引き出され、平面視で第１引き出しパターンに重なるように形成された第３引き出しパターンとで構成され、
    　第１引き出しパターン、第２引き出しパターンおよび第３引き出しパターンは、平面視でコイル導体の形成領域外に形成される、帯域除去フィルタ。     An inductor according to any one of claims 1 to 6 and a capacitor connected in parallel to the inductor,
    The capacitor is
    A first lead pattern drawn from the middle of the coil conductor of the inductor;
    A second lead pattern that is drawn from a position closer to the second terminal electrode on the circuit than the first lead pattern, and is formed to overlap the first lead pattern in plan view;
    A third lead pattern that is drawn from a position closer to the first terminal electrode on the circuit than the first lead pattern and is formed so as to overlap the first lead pattern in plan view;
    The first lead pattern, the second lead pattern, and the third lead pattern are band elimination filters formed outside the coil conductor formation region in plan view.
  8. 　前記第２引き出しパターンは前記第２端子電極と前記コイル導体とを接続する接続導体である、請求項７に記載の帯域除去フィルタ。 The band elimination filter according to claim 7, wherein the second lead pattern is a connection conductor that connects the second terminal electrode and the coil conductor.
  9. 　前記第３引き出しパターンは前記第２端子電極に平面視で重なっていない、請求項７または８に記載の帯域除去フィルタ。 The band elimination filter according to claim 7 or 8, wherein the third lead pattern does not overlap the second terminal electrode in plan view.
PCT/JP2014/071145 2013-09-13 2014-08-11 Inductor and band elimination filter WO2015037374A1 (en)

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CN110233029B (en) * 2019-06-18 2021-09-24 电子科技大学 Large-inductance laminated chip inductor and design method thereof
CN110233604A (en) * 2019-07-10 2019-09-13 安徽安努奇科技有限公司 Resonant element production method and resonant element

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