WO2015035832A1 - 阵列基板及其制备方法和显示装置 - Google Patents
阵列基板及其制备方法和显示装置 Download PDFInfo
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- WO2015035832A1 WO2015035832A1 PCT/CN2014/082733 CN2014082733W WO2015035832A1 WO 2015035832 A1 WO2015035832 A1 WO 2015035832A1 CN 2014082733 W CN2014082733 W CN 2014082733W WO 2015035832 A1 WO2015035832 A1 WO 2015035832A1
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- 239000000758 substrate Substances 0.000 title claims abstract description 90
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 239000010410 layer Substances 0.000 claims abstract description 210
- 239000000463 material Substances 0.000 claims abstract description 109
- 239000011347 resin Substances 0.000 claims abstract description 70
- 229920005989 resin Polymers 0.000 claims abstract description 70
- 239000011241 protective layer Substances 0.000 claims abstract description 50
- 238000000034 method Methods 0.000 claims description 45
- 229920002120 photoresistant polymer Polymers 0.000 claims description 35
- 238000000059 patterning Methods 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 230000004888 barrier function Effects 0.000 claims description 14
- 229910052738 indium Inorganic materials 0.000 claims description 10
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 7
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 claims description 5
- 229910001195 gallium oxide Inorganic materials 0.000 claims description 5
- YZZNJYQZJKSEER-UHFFFAOYSA-N gallium tin Chemical compound [Ga].[Sn] YZZNJYQZJKSEER-UHFFFAOYSA-N 0.000 claims description 5
- 229910003437 indium oxide Inorganic materials 0.000 claims description 5
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 5
- 239000005011 phenolic resin Substances 0.000 claims description 5
- 229910001887 tin oxide Inorganic materials 0.000 claims description 5
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 claims description 4
- 239000004925 Acrylic resin Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 229920001568 phenolic resin Polymers 0.000 claims description 4
- KCTAWXVAICEBSD-UHFFFAOYSA-N prop-2-enoyloxy prop-2-eneperoxoate Chemical compound C=CC(=O)OOOC(=O)C=C KCTAWXVAICEBSD-UHFFFAOYSA-N 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 125000005395 methacrylic acid group Chemical group 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- 239000012044 organic layer Substances 0.000 claims 1
- 239000010409 thin film Substances 0.000 description 28
- 239000004065 semiconductor Substances 0.000 description 12
- 229910044991 metal oxide Inorganic materials 0.000 description 10
- 150000004706 metal oxides Chemical class 0.000 description 10
- 239000010949 copper Substances 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 239000011810 insulating material Substances 0.000 description 6
- 238000002161 passivation Methods 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 238000001755 magnetron sputter deposition Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 239000011733 molybdenum Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- -1 oxygen ions Chemical class 0.000 description 4
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-M hydroxide Chemical compound [OH-] XLYOFNOQVPJJNP-UHFFFAOYSA-M 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- SMZOUWXMTYCWNB-UHFFFAOYSA-N 2-(2-methoxy-5-methylphenyl)ethanamine Chemical compound COC1=CC=C(C)C=C1CCN SMZOUWXMTYCWNB-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 150000002148 esters Chemical class 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H—ELECTRICITY
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
- H01L21/441—Deposition of conductive or insulating materials for electrodes
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
- H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/469—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
- H01L21/4757—After-treatment
- H01L21/47573—Etching the layer
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
- H01L21/477—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
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Definitions
- the invention belongs to the technical field of display device preparation, and in particular relates to an array substrate, a preparation method thereof and a display device. Background technique
- Oxide thin film transistors are mainly used to improve carrier mobility, and have good uniformity and simple process, and can be used for transparent display.
- the oxide TFT array substrate is widely used in a display (for example, a liquid crystal display), and specifically includes: a TFT substrate, a thin film transistor gate disposed above the TFT substrate, a gate insulating layer covering the gate, and a gate insulating layer An active layer, a barrier layer covering the active layer, a source and a drain disposed above the barrier layer and connected to the active layer through the contact via, a passivation layer covering the source and the drain, and a through layer A pixel electrode of the passivation layer that contacts the via and the drain.
- a display for example, a liquid crystal display
- the gate insulating layer is usually a composite layer structure formed of silicon dioxide and silicon nitride. Since the dielectric constants of silicon dioxide and silicon nitride are between 6.5 and 7.3, the value of the dielectric constant of the gate insulating layer is large, so that the power consumption of the TFT array substrate is large. Summary of the invention
- the technical problem to be solved by the present invention includes providing an array substrate with low power consumption, a method for fabricating the same, and a display device in view of the above-mentioned deficiencies of the existing array substrate.
- the technical solution adopted to solve the technical problem of the present invention is to provide an array base a substrate, the array substrate includes: a gate, an active layer, and a gate insulating layer separating the gate from the active layer, the gate insulating layer comprising a two-layer structure of an organic resin material layer and a protective layer, a layer of an organic resin material is in contact with the gate; and the protective layer is in contact with the active layer.
- the gate insulating layer in the array substrate provided by the present invention has a two-layer structure including an organic resin material layer, and the organic resin material layer has a low dielectric constant, so the power consumption of the array substrate is low.
- the organic resin material layer covers the gate electrode, the protective layer is disposed above the organic resin material layer, and the active layer is disposed above the protective layer.
- the array substrate further includes: a pixel electrode, a source and a drain,
- the pixel electrode, the source, and the drain are formed by one patterning process.
- the protective layer covers the active layer, the organic resin material layer is disposed above the protective layer, and the gate is disposed above the organic resin material layer.
- the material of the protective layer is any one of silicon dioxide, silicon nitride and aluminum oxide, and the protective layer has a thickness of between 500 and 800 ⁇ .
- the material of the organic resin material layer is a methacrylic phenolic resin or an epoxy acrylate resin, and the thickness of the organic resin material layer is between 1.5 and 2.0 ⁇ m.
- the material of the active layer is any one of indium gallium oxide, indium oxide, indium tin oxide and indium gallium tin oxide, and the thickness of the active layer is between 1500 and 2200 ⁇ .
- a technical solution to solve the technical problem of the present invention is to provide a display device including the above array substrate.
- a technical solution to solve the technical problem of the present invention is to provide a method for preparing an array substrate, the method comprising the following steps:
- step S11 forming a layer of an organic resin material on the substrate on which step S11 is completed, and Forming a protective layer on the resin material layer;
- step S12 On the substrate on which step S12 is completed, a pattern including an active layer is formed by a patterning process.
- the forming the organic resin material layer comprises:
- the organic resin material layer is annealed and cured to form a flat surface.
- the method further includes:
- step S14 sequentially depositing a pixel electrode layer, a source/drain metal layer, and a photoresist layer, and exposing and developing the photoresist layer so that there is no conductive region above the active layer.
- a photoresist covering while retaining a photoresist on a region corresponding to the source and the drain and a photoresist on a region corresponding to the pixel electrode, and the source and the drain The thickness of the photoresist on the region corresponding to the pole is greater than the thickness of the photoresist on the region corresponding to the pixel electrode;
- a photoresist for removing a thickness of a photoresist on a region corresponding to the pixel electrode by etching, and a light source/drain metal layer;
- the remaining thickness of the photoresist and the exposed source/drain metal layer and the exposed pixel electrode layer are removed by etching.
- the photoresist layer is exposed to a gray scale mask.
- a technical solution to solve the technical problem of the present invention is another method for preparing an array substrate, the method comprising the following steps:
- step S21 forming a protective layer on the substrate on which step S21 is completed, and forming an organic resin material layer on the protective layer;
- FIG. 1 is a structural view of an array substrate according to a first embodiment of the present invention
- FIGS. 2A to 2F are flowcharts showing a method of fabricating an array substrate according to a third embodiment of the present invention.
- the embodiment provides an array substrate, including: a gate 2, an active layer 5, and a gate insulating layer separating the gate 2 from the active layer 5, wherein the gate insulating layer
- the layer includes a two-layer structure of the organic resin material layer 3 and the protective layer 4, and the organic resin material layer 3 is in contact with the gate electrode 2, and the protective layer 4 is in contact with the active layer 5.
- One of the two-layer structure of the gate insulating layer of the array substrate of the present embodiment is an organic resin material layer 3, and the material of the organic resin material layer 3 has a low dielectric constant, usually between 3.0 and 3.7. Therefore, the power consumption of the array substrate is low.
- the present embodiment can form the organic resin material layer 3 to be relatively thick, thereby increasing the distance between the gate electrode 2 of the thin film transistor and the active layer 5, thereby The capacitance of the storage capacitor on the array substrate (which is formed by the opposing gate metal lines and the source and drain metal lines) is reduced, thereby reducing the power consumption of the array substrate.
- the protective layer 4 is formed over the organic resin material layer 3, and the protective layer 4 can effectively prevent the oxygen ions in the organic resin material layer 3 from being combined with the oxygen ions in the material of the active layer 5 (metal oxide semiconductor material).
- the performance of the active layer 5 is lowered.
- the organic resin material layer 3 covers the gate electrode 2, the protective layer 4 is disposed above the organic resin material layer 3, and the active layer 5 is disposed above the protective layer 4. That is, the gate electrode 2 of the thin film transistor is provided on the substrate 1, the organic resin material layer 3 is formed on the substrate 1 on which the gate electrode 2 is formed, and the protective layer 4 is formed on the organic resin material layer 3, in the protective layer 4 An active layer 5 of a thin film transistor is provided above.
- the thin film transistor on the array substrate is a bottom gate type thin film transistor.
- the source and drain electrodes 8 of the thin film transistor and the pixel electrode 7 of the array substrate are preferably formed by one patterning process, so that the process of the array substrate is simple, and the production efficiency can be improved.
- the protective layer 4 covers the active layer 5, the organic resin material layer 3 is disposed above the protective layer 4, and the gate electrode 2 is disposed on the organic resin material layer 3.
- the active layer 5 of the thin film transistor is provided on the substrate 1, the protective layer 4 is formed over the active layer 5 of the thin film transistor, and the organic resin material layer 3 is formed over the protective layer 4 in the organic resin material layer.
- 3 is provided with a gate electrode 2 of a thin film transistor. It is easy to see that the thin film transistor on the array substrate is a top gate type thin film transistor.
- the material of the protective layer 4 of the array substrate of the embodiment may be any one of silicon dioxide, silicon nitride and aluminum oxide, or may be other insulating materials, and the thickness of the protective layer 4 is between 500 800 A. .
- the material of the organic resin material layer 3 may be a mercaptoacrylic phenol resin or an epoxy acrylate resin, and the organic resin material layer 3 has a thickness of between 1.5 and 2.0 ⁇ m.
- the material of the active layer 5 may be any one of indium gallium oxide, indium oxide, indium tin oxide, and indium gallium tin oxide. Of course, other metal oxide semiconductor materials may also be used.
- Layer 5 has a thickness between 1500 and 2200 ⁇ .
- the embodiment provides a display device, which includes the array substrate in the first embodiment, and the display device can be: OLED panel, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigation device, etc. A product or part that displays functionality. Since the display device of the present embodiment has the array substrate in the first embodiment, its power consumption is small.
- the display device of the embodiment may further include other conventional structures such as a power supply unit, a display driving unit, and the like.
- a third embodiment of the present invention will be described.
- this embodiment provides a method for preparing an array substrate, which includes the following steps:
- Step 1 Depositing a gate metal layer on the substrate 1 by magnetron sputtering, the material of which may be any one of molybdenum (Mo), aluminum (A1) and copper (Cu) or the like. An alloy or the like formed by any combination is formed into a pattern including the gate electrode 2 of the thin film transistor and a gate metal line by a patterning process as shown in FIG. 2A.
- Step 2 forming an organic resin material layer 3 on the substrate 1 on which the first step is completed, specifically, the layer may be formed by spin coating, and the thickness of the organic resin material layer 3 is between 1.5 and 2.0 ⁇ m, and the organic resin material layer
- the material of 3 may be a methacrylic phenolic resin, an epoxy acrylate resin or a non-photosensitive resin material; the organic resin material layer 3 is cured to form a flat surface (the step difference can be eliminated); and then formed into a flat surface
- the protective layer 4 is deposited on the organic resin material layer 3, and the thickness of the protective layer 4 is between 500 800 ⁇ .
- the material of the protective layer 4 may be any one of silicon dioxide, silicon nitride and aluminum oxide or other insulating materials.
- a gate insulating layer is formed, as shown in FIG.
- Step 3 forming a metal oxide semiconductor material layer on the substrate 1 completed in the second step.
- the metal oxide semiconductor material may be formed by using a magnetron sputtering method at room temperature, Ar, and 0 2 atmosphere conditions.
- Layer; A pattern of the active layer 5 including a thin film transistor is formed by a patterning process as shown in FIG. 2C.
- the material of the metal oxide semiconductor material layer may be any one of indium gallium oxide, indium oxide, indium tin oxide, and indium gallium tin oxide, or may be other oxide semiconductor materials, the thickness of the active layer 5. Between 1500 and 2200A.
- Step 4 forming a barrier layer 6 on the substrate 1 of the third step, the material of which may be an insulating material such as silicon dioxide, silicon nitride or aluminum oxide, by a patterning process.
- a contact via penetrating through the barrier layer 6 and for connecting the active layer 5 of the thin film transistor to the source and drain electrodes 8 is formed on the barrier layer 6, as shown in FIG. 2D.
- Step 5 sequentially depositing a pixel electrode layer, a source/drain metal layer and a photoresist layer 9 on the substrate 1 on which the step 4 is completed, and exposing and developing the photoresist layer 9 so as to be above the conductive region of the active layer 5.
- the thickness of the photoresist is greater than the thickness of the photoresist on the region corresponding to the pixel electrode 7, as shown in FIG. 2E;
- a photoresist for removing the thickness of the photoresist on the region corresponding to the pixel electrode 7 and an exposed source/drain metal layer by etching
- the remaining thickness of the photoresist and the exposed source/drain metal layer and the exposed pixel electrode layer are removed by etching to finally form the source and drain electrodes 8 and the pixel electrode 7, as shown in Fig. 2F.
- the material of the source and the drain 8 may be any one of molybdenum (Mo), aluminum (A1), and copper (Cu), or an alloy formed by any combination of the three, and the material of the pixel electrode 7 may be Indium tin oxide (ITO) or other transparent conductive material, the source and drain electrodes 8 and the pixel electrode 7 each have a thickness of between 400 and 700 ⁇ .
- Mo molybdenum
- Al aluminum
- Cu copper
- ITO Indium tin oxide
- the photoresist layer 9 may be exposed by a gray scale mask, or the photoresist layer 9 may be exposed by a halftone mask. In this way, different areas of the mask can be exposed to different precisions on a mask as required.
- the gate insulating layer of the thin film transistor has a two-layer structure, wherein one layer of the structure is an organic resin material layer 3, and the dielectric constant of the material of the organic resin material layer 3 is higher. Low, thus making the power consumption of the array substrate low; and forming the protective layer 4 over the organic resin material layer 3, the protective layer 4 can effectively prevent the hydroxide and the active layer 5 in the organic resin material layer 3
- the oxygen ions in the material combine to lower the performance of the active layer 5.
- the pixel electrode 7 and the source and drain electrodes 8 are formed by one patterning process, which simplifies the fabrication process of the array substrate and reduces the cost.
- This embodiment provides another method for preparing an array substrate, which is different from the method for preparing an array substrate in the third embodiment in that the thin film transistor of the array substrate prepared in the third embodiment is a bottom gate type.
- the thin film transistor, and the thin film transistor of the array substrate prepared in this embodiment is a top gate type thin film transistor.
- the method provided in this embodiment includes the following steps:
- Step 1 forming a metal oxide semiconductor material layer on the substrate 1.
- a metal oxide semiconductor material layer may be formed by a magnetron sputtering method under room temperature, Ar and 02 atmosphere conditions; A pattern of the active layer 5 including a thin film transistor.
- the material of the metal oxide semiconductor material layer may be any one of indium gallium oxide, indium oxide, indium tin oxide, and indium gallium tin oxide, or may be other oxide semiconductor materials, and the thickness of the active layer 5 is Between 1500 2200A.
- Step 2 forming a protective layer 4 on the substrate 1 of the first step, the thickness of the protective layer 4 is between 500 800 A, and the material of the protective layer 4 may be any one of silicon dioxide, silicon nitride and aluminum oxide or the like. Insulating material; further forming an organic resin material layer 3 over the protective layer 4, the thickness of the organic resin material layer 3 is between 1.5 and 2.0 ⁇ m, and the material of the organic resin material layer 3 may be a non-based acrylic phenolic resin or epoxy acrylic acid. An ester resin or a non-photosensitive resin material or the like; the organic resin material layer 3 is cured to form a flat surface (the step difference can be eliminated), and finally a gate insulating layer is formed.
- Step 3 On the substrate 1 of the second step, the gate metal layer is deposited by magnetron sputtering, and the material thereof may be any one of molybdenum (Mo), aluminum (A1) and copper (Cu). Or an alloy or the like formed by any combination of the three, a pattern including the gate electrode 2 of the thin film transistor and a gate metal line are formed by a patterning process.
- Mo molybdenum
- Al aluminum
- Cu copper
- Step 4 forming a barrier layer 6 on the substrate 1 on which the third step is completed, the material of which may be an insulating material such as silicon dioxide, silicon nitride or aluminum oxide; forming a through-barrier layer 6 on the barrier layer 6 by a patterning process and used for A contact via connecting the active layer 5 of the thin film transistor to the source and drain electrodes 8.
- the material of which may be an insulating material such as silicon dioxide, silicon nitride or aluminum oxide
- Step 5 On the substrate 1 on which the step 4 is completed, a pattern including a source and a drain 8 of the thin film transistor is formed by a patterning process, and the source and drain electrodes 8 pass in step four.
- the contact via formed in the middle is connected to the active layer 5.
- the material of the source and the drain 8 may be any one of molybdenum (Mo), aluminum (A1) and copper (Cu) or an alloy formed by any combination of the three, the source and the drain 8
- the thickness is between 400 700A.
- Step 6 On the substrate 1 on which the step 5 is completed, a passivation layer is formed, and the passivation layer is made of an insulating material; and a contact via penetrating through the passivation layer is formed in a region of the passivation layer corresponding to the drain electrode 8.
- Step 7 On the substrate 1 on which the step 6 is completed, a pattern including the pixel electrode 7 is formed by a patterning process, and the pixel electrode 7 is connected to the drain of the thin film transistor through the contact via formed in the step 6.
- the material of the pixel electrode 7 may be indium tin oxide (ITO) or other transparent conductive material, and the thickness of the pixel electrode 7 is between 400 and 700A.
- the gate insulating layer of the thin film transistor has a two-layer structure, wherein one layer of the structure is the organic resin material layer 3, and the dielectric constant of the material of the organic resin material layer 3
- one layer of the structure is the organic resin material layer 3, and the dielectric constant of the material of the organic resin material layer 3
- the protective layer can effectively prevent the hydroxide in the organic resin material layer 3 from
- the oxygen ions in the material of the active layer 5 metal oxide semiconductor material
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Abstract
Description
Claims
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US14/437,016 US20150279870A1 (en) | 2013-09-10 | 2014-07-22 | Array substrate, method for manufacturing the same, and display device |
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CN201310409085.4 | 2013-09-10 |
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CN103456745B (zh) * | 2013-09-10 | 2016-09-07 | 北京京东方光电科技有限公司 | 一种阵列基板及其制备方法、显示装置 |
JP6323055B2 (ja) * | 2014-02-21 | 2018-05-16 | 凸版印刷株式会社 | 薄膜トランジスタアレイおよびその製造方法 |
CN105629598B (zh) * | 2016-03-11 | 2018-12-11 | 深圳市华星光电技术有限公司 | Ffs模式的阵列基板及制作方法 |
KR102340066B1 (ko) * | 2016-04-07 | 2021-12-15 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 박리 방법 및 플렉시블 디바이스의 제작 방법 |
CN106057828A (zh) * | 2016-08-12 | 2016-10-26 | 京东方科技集团股份有限公司 | 一种基板及其制备方法、显示面板 |
CN109801923A (zh) * | 2017-11-16 | 2019-05-24 | 京东方科技集团股份有限公司 | 一种薄膜晶体管及其制备方法、阵列基板、显示装置 |
CN107968096A (zh) * | 2017-11-23 | 2018-04-27 | 信利(惠州)智能显示有限公司 | 阵列基板、显示面板及阵列基板的制备方法 |
CN110112212A (zh) * | 2019-04-25 | 2019-08-09 | 深圳市华星光电技术有限公司 | 薄膜晶体管和阵列基板 |
CN116247011B (zh) * | 2023-05-10 | 2023-10-13 | 长鑫存储技术有限公司 | 半导体结构及其制造方法 |
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US20150279870A1 (en) | 2015-10-01 |
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