WO2015035724A1 - 阵列基板及其驱动方法、显示装置 - Google Patents

阵列基板及其驱动方法、显示装置 Download PDF

Info

Publication number
WO2015035724A1
WO2015035724A1 PCT/CN2013/089286 CN2013089286W WO2015035724A1 WO 2015035724 A1 WO2015035724 A1 WO 2015035724A1 CN 2013089286 W CN2013089286 W CN 2013089286W WO 2015035724 A1 WO2015035724 A1 WO 2015035724A1
Authority
WO
WIPO (PCT)
Prior art keywords
common electrode
voltage
array substrate
pixel
pixel units
Prior art date
Application number
PCT/CN2013/089286
Other languages
English (en)
French (fr)
Inventor
姜清华
秦锋
李小和
李红敏
张晓洁
Original Assignee
合肥京东方光电科技有限公司
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 合肥京东方光电科技有限公司, 京东方科技集团股份有限公司 filed Critical 合肥京东方光电科技有限公司
Priority to US14/408,683 priority Critical patent/US9812079B2/en
Publication of WO2015035724A1 publication Critical patent/WO2015035724A1/zh

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a driving method thereof, and a display device. Background technique
  • the liquid crystal display is widely used by engineers because of its low power consumption, light weight and no radiation. It has been widely used in electronic products including computers and mobile phones. Among various electronic devices.
  • the liquid crystal display generally includes an array substrate, a color filter substrate, and a liquid crystal layer between the array substrate and the color filter substrate.
  • the display principle is mainly: changing the rotation angle of the liquid crystal molecules in the liquid crystal layer by changing the potential difference between the liquid crystal layers , the light transmittance of the liquid crystal is changed to display different images.
  • polarity of the voltage applied across the liquid crystal layer must be reversed every predetermined time to avoid permanent polarization due to polarization of the liquid crystal material.
  • Common pixel array polarity inversion methods include frame inversion, column inversion, line inversion, and dot inversion.
  • Embodiments of the present invention provide an array substrate, a driving method thereof, and a display device, which can reduce power consumption of an array substrate in a dot inversion driving mode.
  • An aspect of an embodiment of the present invention provides an array substrate including a plurality of pixel units arranged in a matrix by a plurality of gate lines and a plurality of data lines intersecting each other, each of the pixel units including pixels.
  • the common electrode of the same pixel unit having the same number of rows and columns has the same voltage polarity
  • the voltages of the common electrodes of adjacent pixel units are opposite in polarity.
  • a display device comprising the array substrate as described above.
  • an array substrate driving method includes a plurality of pixel units arranged in a matrix, which are divided into a plurality of gate lines and a plurality of data lines.
  • the pixel unit includes pixel electrodes, each of the pixel units further includes a common electrode, and the method includes:
  • n is a natural number.
  • the array substrate includes a plurality of pixel units arranged in a matrix, which are divided into a plurality of gate lines and a plurality of data lines intersecting each other, each pixel
  • the unit includes pixel electrodes, each of the pixel units further includes a common electrode; in the pixel unit matrix, the common electrode corresponding to the pixel unit having the same number of rows and columns
  • the voltages of the same polarity are the same; the voltages of the common electrodes of adjacent pixel units are opposite in polarity.
  • the array substrate with such a structure can greatly reduce the voltage swing of the data line driving voltage between the positive and negative gray scales while realizing the dot inversion driving, thereby effectively reducing the dot inversion driving mode. Power consumption of the array substrate.
  • FIG. 1 is a schematic diagram showing a polarity distribution of a pixel region of an array substrate in a dot inversion driving manner in the prior art
  • FIG. 2 is a schematic diagram of signal timing of driving an array substrate by using a dot inversion driving method in the prior art
  • FIG. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 4 is a cross-sectional view showing the structure of a TFT region in an array substrate according to an embodiment of the present invention
  • FIG. 5 is a schematic diagram of a pixel region polarity distribution and a common electrode connection of an array substrate in a dot inversion driving manner according to an embodiment of the present invention
  • FIG. 6 is a schematic diagram of another pixel region polarity distribution and a common electrode connection of an array substrate in a dot inversion driving manner according to an embodiment of the present invention
  • FIG. 7 is a schematic flow chart of a method for driving an array substrate according to an embodiment of the present invention. detailed description
  • the array substrate provided by the embodiment of the present invention includes a plurality of pixel units 33 arranged in a matrix, which are divided into a plurality of gate lines 31 and a plurality of data lines 32 intersecting each other.
  • the 33 further includes a pixel electrode 331, wherein each of the pixel units 33 further includes a common electrode 332.
  • the voltage of the common electrode 332 corresponding to the pixel unit 33 having the same sum of the number of rows and columns (i.e., the sum of the number of rows and the number of columns) is the same.
  • the voltages of the common electrodes 332 of the adjacent pixel units 33 are opposite in polarity.
  • the sum of the number of rows and columns of the pixel unit of the second row and the first column is equal to the sum of the number of rows and columns of the pixel unit of the first row and the second column, and the third row and the first column
  • the sum of the number of rows and columns of the pixel unit of the second row and the second column and the first row and the third column is equal, and so on.
  • the common electrodes corresponding to each group of diagonally arranged pixel units can be connected to form a plurality of sets of common electrode strips arranged obliquely, and a plurality of sets of common electrodes The bars are parallel to each other.
  • the common electrode strip composed of the common electrode corresponding to the pixel unit whose sum of the number of rows and columns is 2n may be referred to as an even-numbered common electrode strip, where n is a natural number.
  • dot inversion driving can be realized by controlling the voltages of the input pixel electrode 331 and the common electrode 332. Further, at the end of one frame display, the polarity of the voltage of each common electrode 332 is also inverted once, so that the frequency of voltage reversal can be increased, and polarization of the liquid crystal material can be further prevented, thereby improving the quality of the display device.
  • the array substrate provided by the embodiment of the invention includes a plurality of pixel units arranged in a matrix by a plurality of gate lines and a plurality of data lines intersecting each other, each pixel unit including a pixel electrode, and each pixel unit further
  • the common electrode is included; in the pixel unit matrix, the voltages of the common electrodes corresponding to the pixel units having the same number of rows and columns are the same; the voltages of the common electrodes of the adjacent pixel units are opposite in polarity.
  • the array substrate with such a structure can greatly reduce the voltage swing of the data line driving voltage between the positive and negative gray scales while realizing the dot inversion driving, thereby effectively reducing the dot inversion driving mode. Power consumption of the array substrate.
  • the adjacent pixel unit of one pixel unit refers to a pixel unit adjacent to the pixel unit array in the matrix of the pixel unit array arranged in a matrix form, that is, for one pixel.
  • the array substrate further includes a driving circuit 34 electrically connected to the common electrode 332 for controlling the voltage of each of the common electrodes 332.
  • the drive circuit 34 can include a first output 341 and a second output 342.
  • the first output terminal 341 is connected to the odd row common electrode strips, and the second output terminal 342 is connected to the even row common electrode strips.
  • the first output terminal 341 and the second output terminal 342 have opposite polarity of the output voltage.
  • the odd-numbered common electrode strips can all adopt the same voltage, and the same Even-numbered common electrode strips can also use the same voltage, so all odd-numbered common electrode strips can be made in a single structure, and all even-numbered common electrode strips can also be made in a single structure, which can greatly reduce the array.
  • the difficulty of making the substrate can be made in the embodiment of the present invention.
  • first output end 341 and the second output end 342 can each be made of a gate line metal layer.
  • the gate line metal layer is mainly used to form a pattern of the gate lines.
  • the gate lines and the first output end 341 and the second output end 342 may be simultaneously formed by performing a patterning process on the gate line metal layer.
  • the pattern can reduce the hierarchical structure of the array substrate and reduce the production difficulty of the product.
  • the driving circuit 34 can adopt a driving chip IC.
  • the strip-shaped common electrode 332 passes through the gate insulating layer and the passivation layer (not shown in FIG. 3) at the periphery of the panel.
  • the via is connected to the bottommost gate line metal layer, and the gate line metal layer is finally connected to the pin of the driving chip IC, so that the signal inside the driving chip IC can be loaded onto the common electrode 332, so that the oblique common electrode 332 Connecting in series helps to reduce the driving power consumption in the dot inversion mode.
  • the left and right adjacent pixels and the common electrodes 332 between the upper and lower adjacent pixels are not all connected together, but there are black matrices of a certain width on both sides of the gate lines 31 and the data lines 32 (in color It is made on the film substrate, so there is no light leakage.
  • the array substrate provided by the embodiments of the present invention can be applied to FFS (Fringe Field Switching) type, AD-SDS (Advanced-Super Dimensional Switching), and IPS (In Plane). Switch, Transverse Electric Field Effect) The production of a type of liquid crystal display device in which a pixel electrode and a common electrode are both disposed on an array substrate.
  • FFS Flexible Field Switching
  • AD-SDS Advanced-Super Dimensional Switching
  • IPS In Plane
  • Switch Transverse Electric Field Effect
  • an FFS type liquid crystal display device is taken as an example for description.
  • the pixel electrode 331 is connected to the gate line 31 and the data line 32 through TFT (Thin Film Transistor).
  • the cross-sectional view of the TFT region may be as shown in FIG. 4, including the gate electrode 41 of the TFT formed on the substrate 40, on which the gate insulating layer 42 is formed, and the active layer 43 is formed on the gate insulating layer 42 and located at the gate. Above the layer 41, one end of the source 441 of the TFT is located above the gate 41, and the other end is connected to a data line (not shown in FIG. 4). One end of the drain 442 is located above the gate 41, and the other end is connected to the pixel. The electrode 331 is connected, and a TFT channel region 45 is formed between the source 441 and the drain 442.
  • the passivation layer 46 is formed on the above-mentioned structural pattern, and the strips are arranged in common
  • the electrode 332 is formed on the passivation layer 46.
  • the common electrode 332 in the odd-line common electrode strips in the pixel region adopts the same voltage
  • the common electrode 332 in the even-numbered row common electrode strips adopts the same voltage
  • the odd-numbered rows The voltages of the common electrode strips and the even-numbered row common electrode strips are opposite in polarity
  • the pixel electrodes 331 in the adjacent pixel regions adopt opposite voltages
  • the edge electric field between the pixel electrodes 331 and the common electrode 332 drives the deflection of the liquid crystal molecules, thereby realizing Black and white and grayscale display.
  • the common electrode and the pixel electrode may be disposed in different layers, wherein the electrode located in the upper layer includes a plurality of strip electrodes, and the electrodes located in the lower layer may be flat or strip-shaped
  • the electrode is not limited in the present invention.
  • the different layer arrangement is for at least two patterns, and the at least two pattern different layer arrangement means: at least two layers of the film are respectively formed into at least two patterns by a patterning process.
  • the arrangement of the two layers of the pattern means that: by the patterning process, a pattern is formed by each of the two films.
  • the common electrode and the pixel electrode are disposed in different layers: the lower layer electrode is formed by a patterning process from the first layer of the transparent conductive film, and the upper layer electrode is formed by the patterning process by the second layer of the transparent conductive film, wherein the lower layer electrode is a common electrode (or The pixel electrode), the upper electrode is a pixel electrode (or a common electrode).
  • the lower layer electrode is a common electrode (or The pixel electrode)
  • the upper electrode is a pixel electrode (or a common electrode).
  • the power consumption of the array substrate can be effectively reduced while implementing the dot inversion driving mode.
  • the driving method of the array substrate provided by the embodiment of the present invention is exemplified below with reference to the schematic diagram of the pixel unit shown in FIG.
  • the definition shows that a gray scale requires a voltage difference of 2V between the pixel electrode and the common electrode, the common electrode voltage of the positive polarity pixel is -3V, and the common electrode of the negative polarity pixel is 3V, that is, the pixel of the oblique dotted line A in FIG.
  • the voltage of the common electrode is -3V, and the voltage of the common electrode of the pixel penetrating the solid line B is 3V.
  • the polarity of the pixel region defined by the gate line G3 and the data line D1 is positive, and the common electrode voltage ⁇ is ⁇ , and the data line voltage is -1V.
  • the voltages of the data lines D1, D3, D5, ... are in -IV and IV.
  • the flipping is repeated back and forth, and the frequency of the inversion is inverted once for each scanning line.
  • the voltages of the data lines D2, D4, D6 ⁇ are also flipped back and forth between -IV and IV, and the frequency of the inversion is inverted once per line of scanning lines.
  • the design structure is in the dot inversion driving mode, for the case where a voltage difference of 2V between the pixel electrode and the common electrode is required to display a certain gray scale, all the data lines D1, D2, D3...
  • the voltage of ... is constantly reversed between -IV and IV, and the frequency of inversion is inverted once every one scanning line.
  • the data line needs to be reversed between IV and 5V, which obviously saves power.
  • the array substrate with such a structure can greatly reduce the voltage swing of the data line driving voltage between the positive and negative gray scales while realizing the dot inversion driving, thereby effectively reducing the dot inversion driving mode. Power consumption of the array substrate.
  • Embodiments of the present invention also provide a display device including the array substrate as described above.
  • the display device may specifically include a liquid crystal display device, for example, the display device may be any product or component having a display function such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, or a tablet computer.
  • the array substrate can be applied to FFS (Fringe Field Switching) type, AD-SDS (Advanced-Super Dimensional Switching, ADS, advanced super-dimensional field switch) type and IPS (In Plane Switch). , Transverse electric field effect)
  • FFS Flexible Field Switching
  • AD-SDS Advanced-Super Dimensional Switching
  • IPS Intelligent-dimensional field switch
  • Transverse electric field effect The production of a type of liquid crystal display device in which a pixel electrode and a common electrode are both disposed on an array substrate.
  • the display device includes an array substrate, and the array substrate further includes a plurality of pixel units arranged in a matrix by a plurality of gate lines and a plurality of data lines intersecting each other, each pixel unit including a pixel electrode, each pixel unit further including a common electrode; in the pixel unit matrix,
  • the voltages of the common electrodes corresponding to the pixel units having the same sum of the number of rows and columns have the same polarity; the voltages of the common electrodes of the adjacent pixel units are opposite in polarity.
  • the array substrate with such a structure can greatly reduce the voltage swing of the data line driving voltage between the positive and negative gray scales while realizing the dot inversion driving, thereby effectively reducing the dot inversion driving mode. Power consumption of the array substrate.
  • the embodiment of the present invention further provides an array substrate driving method, the array substrate includes a plurality of pixel units arranged in a matrix by a plurality of gate lines and a plurality of data lines intersecting horizontally and vertically, each of the pixel units includes a pixel electrode, each of the pixel units further includes a common electrode, as shown in FIG. 7, the method includes:
  • S702 Input a second voltage to the common electrode corresponding to the pixel unit whose sum of the number of rows and columns in the matrix of the pixel unit is 2n, and the first voltage and the second voltage are opposite in polarity.
  • n is a natural number.
  • the sum of the number of rows and columns of the pixel unit of the second row and the first column is equal to the sum of the number of rows and columns of the pixel unit of the first row and the second column, and the third row and the first column
  • the sum of the number of rows and columns of the pixel unit of the second row and the second column and the first row and the third column is equal, and so on.
  • the common electrodes corresponding to each group of diagonally arranged pixel units can be connected to form a plurality of sets of common electrode strips arranged obliquely, and a plurality of sets of common electrodes The bars are parallel to each other.
  • the common electrode strip composed of the common electrode corresponding to the pixel unit having the sum of the number of rows and columns of 2n may be referred to as an even-numbered common electrode strip, where n is a natural number.
  • the array substrate includes a plurality of pixel units arranged in a matrix, which are divided into a plurality of gate lines and a plurality of data lines intersecting each other, each pixel
  • the unit includes pixel electrodes, each of the pixel units further includes a common electrode; in the pixel unit matrix, the common electrode corresponding to the pixel unit having the same number of rows and columns
  • the voltages of the same polarity are the same; the voltages of the common electrodes of adjacent pixel units are opposite in polarity.
  • the array substrate with such a structure can greatly reduce the voltage swing of the data line driving voltage between the positive and negative gray scales while realizing the dot inversion driving, thereby effectively reducing the dot inversion driving mode. Power consumption of the array substrate.
  • the method further includes:
  • dot inversion driving can be realized by controlling the voltages of the input pixel electrode and the common electrode. Further, at the end of one frame display, the polarity of the voltage of each common electrode is also inverted once, so that the frequency of voltage inversion can be increased, and polarization of the liquid crystal material can be further prevented, thereby improving the quality of the display device.
  • the array substrate provided by the embodiments of the present invention can be applied to FFS (Fringe Field Switching) type, AD-SDS (Advanced-Super Dimensional Switching), and IPS (In Plane). Switch, Transverse Electric Field Effect) The production of a type of liquid crystal display device in which a pixel electrode and a common electrode are both disposed on an array substrate.
  • FFS Flexible Field Switching
  • AD-SDS Advanced-Super Dimensional Switching
  • IPS In Plane
  • Switch Transverse Electric Field Effect
  • an FFS type liquid crystal display device is taken as an example for description.
  • the pixel electrode is connected to the gate line and the data line through a TFT (Thin Film Transistor).
  • TFT Thin Film Transistor
  • the array substrate of the FFS structure forms a multi-dimensional electric field through the pixel electrode field in the same plane, so that all the liquid crystal molecules in the liquid crystal cell and the liquid crystal molecules directly above the electrode can be rotated, thereby improving the working efficiency of the planar alignment liquid crystal. Great light transmission efficiency.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Geometry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)

Abstract

一种阵列基板（40）及其驱动方法、显示装置，涉及显示技术领域。该阵列基板（40）包括由横纵交叉的多条栅线（31）和数据线（32）划分成的呈矩阵状排列的多个像素单元（33），每个所述像素单元（33）包括像素电极（331），每个所述像素单元（33）还包括公共电极（332）；在所述像素单元（33）矩阵中，行列数之和相同的像素单元（33）对应的所述公共电极（332）的电压极性相同；相邻像素单元（33）的所述公共电极（332）的电压极性相反。采用这样一种结构的阵列基板（40），在实现了点反转驱动的同时，大大降低了数据线（32）驱动电压在正负极性灰阶之间的电压摆幅，从而有效降低了点反转驱动模式下阵列基板（40）的功耗。

Description

阵列基板及其驱动方法、 显示装置 技术领域
本发明涉及显示技术领域， 尤其涉及一种阵列基板及其驱动方法、 显示装置。 背景技术
液晶显示器 （Liquid Crystal Display, 筒称 LCD ) 因其所具有的功 耗低、 外形轻薄以及无辐射等特点而倍受工程师青睐， 因此已被广泛地 应用于包括电脑、 手机等电子产品在内的各种电子设备中。 液晶显示器 通常包括阵列基板、 彩膜基板以及位于阵列基板和彩膜基板之间的液晶 层， 其显示原理主要是： 通过改变液晶层两端的电位差， 即可改变液晶 层内液晶分子的旋转角度， 使得液晶的光透性发生改变， 以显示出不同 的图像。
一般而言， 施加在液晶层两端的电压极性必须每隔一预定时间进行 反转， 以避免液晶材料产生极化而造成永久性的破坏。 常见的像素阵列 极性反转的方式有帧反转、 列反转、 行反转和点反转四种。 其中， 在上 一帧写入结束、 下一帧写入开始之前， 如果在整帧上的像素所储存的电 压极性 Δ ν (定义 =像素电压 Vpixel-公共电压 Vc。m)都是相同的 （全部 是正或全部是负 ） ， 即称为帧反转； 若是同一列上的像素所储存的电压 极性都是相同的， 且相邻列上的像素所储存的电压极性相反， 即称为列 反转； 若是同一行上的像素所储存的电压极性都是相同的， 且相邻行上 的像素所储存的电压极性相反， 即称为行反转； 若是每个像素所储存的 电压极性， 都与其上下左右相邻的像素所储存的电压极性相反， 即称为 点反转。 为了提高整个显示画面的品质， 像素点反转驱动方式已逐渐成 为目前主流的驱动方式。
在现有的点反转驱动方式下， 数据线信号需要在每行栅线的扫描时 间内反转一次， 以实现如图 1所示的点反转驱动，其时序图如图 2所示， 其中定义每一像素单元显示某灰阶需要 Δ ν=2ν,每个像素单元的公共电 极电压 Vc。m=3V , 由于栅线 G1 和数据线所界定的像素单元极性为正 (Vpixel-Vc。m=2) , 则数据线 D1 电压为 5V, 栅线 G2和数据线 D1所界定 的像素区域极性为负（Vpixel-Vc。m=-2), 则数据线电压为 IV。 以此类推， 数据线 D1电压需要在 IV与 5V之间不断来回反转， 数据线 D2与数据 线 D1极性相反， 由于公共电极电压 Ve。m=3V, 故数据线 D2电压也需要 在 IV与 5V之间不断来回反转， 采用这样一种点反转驱动方式， 由于数 据线驱动电压在正负极性灰阶之间的电压摆幅相当大， 因而在正负极性 灰阶电压的切换过程中会带来很大的功耗。 发明内容
本发明的实施例提供一种阵列基板及其驱动方法、 显示装置， 可以 降低点反转驱动模式下阵列基板的功耗。
本发明实施例的一方面， 提供一种阵列基板， 包括由横纵交叉的多 条栅线和多条数据线划分成的呈矩阵状排列的多个像素单元， 每个所述 像素单元包括像素电极， 每个所述像素单元还包括公共电极；
在所述像素单元矩阵中， 行列数之和相同的像素单元对应的所述公 共电极的电压极性相同；
相邻像素单元的所述公共电极的电压极性相反。
本发明实施例的另一方面， 提供一种显示装置， 包括如上所述的阵 列基板。
本发明实施例的又一方面， 提供一种阵列基板驱动方法， 所述阵列 基板包括由横纵交叉的多条栅线和多条数据线划分成的呈矩阵状排列 的多个像素单元， 每个所述像素单元包括像素电极， 每个所述像素单元 还包括公共电极， 所述方法包括：
在进行第一帧画面显示时， 向在所述像素单元矩阵中行列数之和为 2n-l的像素单元对应的公共电极输入第一电压；
向在所述像素单元矩阵中行列数之和为 2n 的像素单元对应的公共 电极输入第二电压， 所述第一电压和所述第二电压极性相反；
其中， n为自然数。
本发明实施例提供的阵列基板及其驱动方法、 显示装置， 该阵列基 板包括由横纵交叉的多条栅线和多条数据线划分成的呈矩阵状排列的 多个像素单元， 每个像素单元包括像素电极， 每个像素单元还包括公共 电极； 在像素单元矩阵中， 行列数之和相同的像素单元对应的公共电极 的电压极性相同； 相邻像素单元的公共电极的电压极性相反。 采用这样 一种结构的阵列基板， 在实现了点反转驱动的同时， 大大降低了数据线 驱动电压在正负极性灰阶之间的电压摆幅， 从而有效降低了点反转驱动 模式下阵列基板的功耗。 附图说明
图 1为现有技术中一种采用点反转驱动方式下阵列基板的像素区域 极性分布示意图；
图 2为现有技术中采用点反转驱动方式驱动阵列基板的信号时序示 意图；
图 3为本发明实施例提供的一种阵列基板的结构示意图；
图 4 为本发明实施例提供的一种阵列基板中 TFT 区域的结构剖视 图；
图 5为本发明实施例提供的一种采用点反转驱动方式下阵列基板的 像素区域极性分布以及公共电极连接的示意图；
图 6为本发明实施例提供的另一采用点反转驱动方式下阵列基板的 像素区域极性分布以及公共电极连接的示意图；
图 7为本发明实施例提供的一种阵列基板驱动方法的流程示意图。 具体实施方式
下面将结合本发明实施例中的附图， 对本发明实施例中的技术方案 进行清楚、 完整地描述， 显然， 所描述的实施例仅仅是本发明一部分实 施例， 而不是全部的实施例。 基于本发明中的实施例， 本领域普通技术 人员所获得的所有其他实施例， 都属于本发明保护的范围。
本发明实施例提供的阵列基板， 如图 3所示， 包括由横纵交叉的多 条栅线 31和多条数据线 32划分成的呈矩阵状排列的多个像素单元 33 , 每个像素单元 33又包括像素电极 331 , 其中， 每个像素单元 33还包括 公共电极 332。
在像素单元 33 矩阵中， 行列数之和 （即， 行数和列数之和） 相同 的像素单元 33对应的公共电极 332的电压极性相同。
相邻像素单元 33的公共电极 332的电压极性相反。 例如， 在如图 3所示的像素单元 33矩阵中， 第 2行第 1列像素单 元的行列数之和与第 1行第 2列像素单元的行列数之和相等， 第 3行第 1列、 第 2行第 2列以及第 1行第 3列像素单元的行列数之和相等， 以 此类推。 由于行列数之和相等的像素单元呈一条斜线排列， 因此可以将 每一组斜向排列的像素单元所对应的公共电极相连接， 形成斜向排列的 多组公共电极条， 多组公共电极条相互平行。 其中， 可以将行列数之和 公共电极条， 将行列数之和均为 2n 的像素单元所对应的公共电极组成 的公共电极条称为偶数行公共电极条， 其中 n为自然数。
采用这样一种结构的阵列基板， 通过控制输入像素电极 331和公共 电极 332的电压可以实现点反转驱动。 进一步地， 在一帧画面显示结束 时， 每个公共电极 332的电压极性还将反转一次， 从而可以提高电压反 转的频率， 进一步避免液晶材料发生极化， 提高了显示装置的质量。
本发明实施例提供的阵列基板， 包括由横纵交叉的多条栅线和多条 数据线划分成的呈矩阵状排列的多个像素单元， 每个像素单元包括像素 电极， 每个像素单元还包括公共电极； 在像素单元矩阵中， 行列数之和 相同的像素单元对应的公共电极的电压极性相同； 相邻像素单元的公共 电极的电压极性相反。 采用这样一种结构的阵列基板， 在实现了点反转 驱动的同时， 大大降低了数据线驱动电压在正负极性灰阶之间的电压摆 幅， 从而有效降低了点反转驱动模式下阵列基板的功耗。
需要说明的是， 在本发明实施例中， 一个像素单元的相邻像素单元 具体是指在呈矩阵形式排列的像素单元阵列中与该像素单元上下左右 方向相邻的像素单元， 即对于一个像素单元来说， 最多可以有四个相邻 的像素单元。
进一步地， 在如图 3所示的阵列基板中， 该阵列基板还包括驱动电 路 34 , 该驱动电路 34与公共电极 332电连接， 用于控制每个公共电极 332的电压。
该驱动电路 34可以包括第一输出端 341和第二输出端 342。该第一 输出端 341连接奇数行公共电极条， 第二输出端 342连接偶数行公共电 极条， 该第一输出端 341与第二输出端 342输出电压的极性相反。
在本发明实施例中， 奇数行公共电极条均可以采用相同电压， 同样 偶数行公共电极条也可以采用相同电压， 因此可以将所有的奇数行公共 电极条采用一体结构制成， 将所有的偶数行公共电极条也采用一体结构 制成， 这样一来， 可以大大降低阵列基板的制作难度。
进一步地， 第一输出端 341和第二输出端 342均可以采用栅线金属 层制成。 其中， 栅线金属层主要用于形成栅线的图案， 在本发明实施例 中， 可以通过对栅线金属层进行一次构图工艺同时形成栅线以及第一输 出端 341和第二输出端 342的图案，这样可以筒化阵列基板的层级结构， 降低产品的生产难度。
具体的， 驱动电路 34可以采用驱动芯片 IC, 在图 3所示的阵列基 板中， 条状的公共电极 332在面板周边通过穿过栅绝缘层和钝化层 （图 3 中未示出） 的过孔与最底层的栅线金属层连接， 栅线金属层最终连接 到驱动芯片 IC的引脚上， 以便驱动芯片 IC内部的信号能加载到公共电 极 332上， 这样将斜向的公共电极 332串联在一起， 有利于降低点反转 模式下的驱动功耗。 这里需要特别说明的是， 左右相邻像素以及上下相 邻像素之间的公共电极 332 虽然不是全部连接在一起， 但是在栅线 31 和数据线 32 两边均会有一定宽度的黑矩阵 （在彩膜基板上制作） ， 因 此并不会产生漏光的现象。
本发明实施例提供的阵列基板可以适用于 FFS ( Fringe Field Switching , 边缘场开关 ) 型、 AD-SDS ( Advanced-Super Dimensional Switching, 筒称为 ADS , 高级超维场开关）型以及 IPS ( In Plane Switch, 横向电场效应） 型等像素电极与公共电极均设置于阵列基板上的一类液 晶显示装置的生产。
在如图 3所示的阵列基板中， 是以 FFS型的液晶显示装置为例进行 的说明。 该像素电极 331通过 TFT ( Thin Film Transistor , 薄膜晶体管） 分别与栅线 31和数据线 32相连接。
其中， TFT区域的剖面图可以如图 4所示， 包括形成在基板 40上 的 TFT的栅极 41 , 其上形成栅绝缘层 42 , 有源层 43形成在栅绝缘层 42上并位于栅极层 41的上方， TFT的源极 441的一端位于栅极 41的上 方， 另一端与数据线 （图 4中未示出） 连接， 漏极 442的一端位于栅极 41的上方， 另一端与像素电极 331连接， 源极 441与漏极 442之间形成 TFT沟道区域 45。 钝化层 46形成在上述结构图形上， 条状排列的公共 电极 332形成在钝化层 46上， 工作时， 像素区域内的奇数行公共电极 条中的公共电极 332采用相同的电压且偶数行公共电极条中的公共电极 332 采用相同的电压， 并且奇数行公共电极条和偶数行公共电极条的电 压极性相反， 相邻像素区域内的像素电极 331采用相反的电压， 通过像 素电极 331与公共电极 332之间的边缘电场驱动液晶分子的偏转， 从而 实现黑白和灰度的显示。
需要说明的是， 在 FFS型显示装置的阵列基板中， 公共电极和像素 电极可以异层设置， 其中位于上层的电极包含多个条形电极， 位于下层 的电极可以为平板形或同样采用条形电极， 本发明对此并不做限制。 其 中， 异层设置是针对至少两种图案而言的， 至少两种图案异层设置是指： 分别将至少两层薄膜通过构图工艺形成至少两种图案。 对于两种图案异 层设置是指： 通过构图工艺， 由两层薄膜各形成一种图案。 例如， 公共 电极和像素电极异层设置是指： 由第一层透明导电薄膜通过构图工艺形 成下层电极， 由第二层透明导电薄膜通过构图工艺形成上层电极， 其中， 下层电极为公共电极 （或像素电极） ， 上层电极为像素电极 （或公共电 极） 。 应当理解， 以上也仅是对本发明实施例所做的举例说明， 而并非 对本发明所做的限制。
采用本发明实施例所提供的这样一种阵列基板， 可以在实现点反转 驱动方式的同时有效降低阵列基板的功耗。
为了更好地理解上述原理， 以下参照图 5所示的像素单元示意图对 本发明实施例提供的阵列基板驱动方式进行举例说明。 定义显示某灰阶 需要像素电极和公共电极之间具有 2V 的电压差， 正极性像素的公共电 极电压为 -3V, 负极性像素的公共电极为 3V, 即图 5中斜虚线 A贯穿的 像素的公共电极的电压为 -3V, 斜实线 B 贯穿的像素的公共电极的电压 为 3V。
如图 5所示，由于栅线 G1和数据线 D1所界定的像素区域极性为正 (Vpixei-Vcom =2) ,公共电极电压 Vc。m为 -3 V ,则数据线电压为 2+( -3 )=- 1 V。 栅线 G2和数据线 D1所界定的像素区域极性为负（Vpixel-Vc。m =-2) , 公共 电极电压 。01为 3 ， 则数据线电压为 -2+3=lV。 同理可知栅线 G3与数 据线 D1 所界定的像素区域极性为正， 公共电极电压 ^ 为^ ， 则数 据线电压为 -1V。 依此规律， 数据线 Dl , D3 , D5……的电压在 -IV与 IV 之间不断来回翻转， 反转的频率为每扫描一行栅线反转一次。 栅线 G1和数据线 D2所界定的像素区域极性为负（Vpixel-Vc。m =-2), 公共电极电压 Vc。m为 3V, 则数据线电压为 -2+3=lV。 栅线 G2和数据线 D2 所界定的像素区域极性为正 (Vpixel-Vc。m =2) , 公共电极电压 U -3V, 则数据线电压为 2+ ( -3 ) =-lV。依次规律，数据线 D2, D4, D6 ··· ··· 的电压同样在 -IV与 IV之间不断来回翻转， 反转的频率为每扫描一行 栅线反转一次。
综上所述， 这种设计结构在点反转驱动方式下， 对于需要像素电极 和公共电极之间具有 2V 的电压差以显示某灰阶的情况而言， 所有数据 线 Dl , D2, D3……的电压均在 -IV与 IV之间不断来回反转， 反转的频 率为每扫描一行栅线反转一次。 相比传统奇偶行（列）公共电极均为 3V, 数据线需要在 IV与 5V之间不断来回反转， 明显可以节省功耗。
这里需要特别说明的是： 为使帧与帧之间像素的极性亦反转， 如图 6所示， 斜虚线 A的公共电极与斜虚线 B的公共电极的电压极性在每帧 画面结束后反转一次。 这种设计不但可以实现点反转的驱动模式， 而且 还可以节省数据线上的电压输出从而节省整个面板的驱动功耗。
采用这样一种结构的阵列基板， 在实现了点反转驱动的同时， 大大 降低了数据线驱动电压在正负极性灰阶之间的电压摆幅， 从而有效降低 了点反转驱动模式下阵列基板的功耗。
本发明实施例还提供了一种显示装置， 包括如上所述的阵列基板。 在本发明实施例中， 显示装置具体可以包括液晶显示装置， 例如该 显示装置可以为液晶显示器、 液晶电视、 数码相框、 手机或平板电脑等 任何具有显示功能的产品或者部件。
需要说明的是， 阵列基板可以适用于 FFS ( Fringe Field Switching , 边缘场开关） 型、 AD-SDS ( Advanced-Super Dimensional Switching, 筒 称为 ADS , 高级超维场开关）型以及 IPS ( In Plane Switch, 横向电场效 应） 型等像素电极与公共电极均设置于阵列基板上的一类液晶显示装置 的生产。
其中， 阵列基板的详细结构已在前述实施例中做了详细的描述， 此 处不再赘述。
本发明实施例提供的显示装置， 包括阵列基板， 该阵列基板又包括 由横纵交叉的多条栅线和多条数据线划分成的呈矩阵状排列的多个像 素单元， 每个像素单元包括像素电极， 每个像素单元还包括公共电极； 在像素单元矩阵中， 行列数之和相同的像素单元对应的公共电极的电压 极性相同； 相邻像素单元的公共电极的电压极性相反。 采用这样一种结 构的阵列基板， 在实现了点反转驱动的同时， 大大降低了数据线驱动电 压在正负极性灰阶之间的电压摆幅， 从而有效降低了点反转驱动模式下 阵列基板的功耗。
本发明实施例还提供了一种阵列基板驱动方法， 该阵列基板包括由 横纵交叉的多条栅线和多条数据线划分成的呈矩阵状排列的多个像素 单元， 每个像素单元包括像素电极， 每个像素单元还包括公共电极， 如 图 7所示， 该方法包括：
5701、 在进行第一帧画面显示时， 向在像素单元矩阵中行列数之和 为 2n- l的像素单元对应的公共电极输入第一电压。
5702、 向在像素单元矩阵中行列数之和为 2n 的像素单元对应的公 共电极输入第二电压， 该第一电压和第二电压极性相反。
其中， n为自然数。
需要说明的是， 在进行第一帧画面显示时， 步骤 S701和步骤 S702 并无严格的先后顺序， 二者的执行顺序可以相互倒换。
例如， 在如图 3所示的像素单元 33矩阵中， 第 2行第 1列像素单 元的行列数之和与第 1行第 2列像素单元的行列数之和相等， 第 3行第 1列、 第 2行第 2列以及第 1行第 3列像素单元的行列数之和相等， 以 此类推。 由于行列数之和相等的像素单元呈一条斜线排列， 因此可以将 每一组斜向排列的像素单元所对应的公共电极相连接， 形成斜向排列的 多组公共电极条， 多组公共电极条相互平行。 其中， 可以将行列数之和 公共电极条， 将行列数之和均为 2n 的像素单元所对应的公共电极组成 的公共电极条称为偶数行公共电极条， 其中 n为自然数。
本发明实施例提供的阵列基板及其驱动方法、 显示装置， 该阵列基 板包括由横纵交叉的多条栅线和多条数据线划分成的呈矩阵状排列的 多个像素单元， 每个像素单元包括像素电极， 每个像素单元还包括公共 电极； 在像素单元矩阵中， 行列数之和相同的像素单元对应的公共电极 的电压极性相同； 相邻像素单元的公共电极的电压极性相反。 采用这样 一种结构的阵列基板， 在实现了点反转驱动的同时， 大大降低了数据线 驱动电压在正负极性灰阶之间的电压摆幅， 从而有效降低了点反转驱动 模式下阵列基板的功耗。
进一步地， 如图 7所示， 所述方法还包括：
S703、 在进行第二帧画面显示时， 向第一帧画面显示时电压为第一 电压的公共电极输入第二电压， 向第一帧画面显示时电压为第二电压的 公共电极输入第一电压。
采用这样一种结构的阵列基板， 通过控制输入像素电极和公共电极 的电压可以实现点反转驱动。 进一步地， 在一帧画面显示结束时， 每个 公共电极的电压极性还将反转一次， 从而可以提高电压反转的频率， 进 一步避免液晶材料发生极化， 提高了显示装置的质量。
本发明实施例提供的阵列基板可以适用于 FFS ( Fringe Field Switching , 边缘场开关 ) 型、 AD-SDS ( Advanced-Super Dimensional Switching, 筒称为 ADS , 高级超维场开关）型以及 IPS ( In Plane Switch, 横向电场效应） 型等像素电极与公共电极均设置于阵列基板上的一类液 晶显示装置的生产。
在本发明实施例中， 是以 FFS型的液晶显示装置为例进行的说明。 该像素电极通过 TFT ( Thin Film Transistor, 薄膜晶体管 )分别与栅线和 数据线相连接。 这样一种 FFS结构的阵列基板通过同一平面内像素电极 场形成多维电场， 使液晶盒内像素电极间、 电极正上方所有取向液晶分 子都能够产生旋转， 从而提高了平面取向型液晶工作效率并增大了透光 效率。
本领域普通技术人员可以理解： 实现上述方法实施例的全部或部分 步骤可以通过程序指令相关的硬件来完成， 前述的程序可以存储于一计 算机可读取存储介质中， 该程序在执行时， 执行包括上述方法实施例的 步骤； 而前述的存储介质包括： ROM、 RAM, 磁碟或者光盘等各种可以 存储程序代码的介质。
以上所述， 仅为本发明的具体实施方式， 但本发明的保护范围并不 局限于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围 内， 可轻易想到变化或替换， 都应涵盖在本发明的保护范围之内。 因此, 本发明的保护范围应以权利要求的保护范围为准。

Claims

权 利 要 求 书
1、 一种阵列基板， 包括由横纵交叉的多条栅线和多条数据线划分 成的呈矩阵状排列的多个像素单元， 每个所述像素单元包括像素电极， 每个所述像素单元还包括公共电极；
在所述像素单元矩阵中， 行列数之和相同的像素单元对应的所述公 共电极的电压极性相同；
相邻像素单元的所述公共电极的电压极性相反。
2、 根据权利要求 1 所述的阵列基板， 其中， 每个所述公共电极的 电压在每一帧画面显示结束时极性反转一次。
3、 根据权利要求 1所述的阵列基板， 其中， 所述阵列基板还包括： 驱动电路， 所述驱动电路与所述公共电极电连接， 用于控制每个所 述公共电极的电压。
4、 根据权利要求 3 所述的阵列基板， 其中， 每个行列数之和相同 的像素单元的所述公共电极之间电连接以形成公共电极条， 其中行列数 之和为奇数的像素单元所对应的公共电极条为奇数行公共电极条， 行列 数之和为偶数的像素单元所对应的公共电极条为偶数行公共电极条； 所述驱动电路包括第一输出端和第二输出端；
所述第一输出端连接奇数行公共电极条， 所述第二输出端连接偶数 行公共电极条， 所述第一输出端与所述第二输出端输出电压的极性相 反。
5、 根据权利要求 4 所述的阵列基板， 其中， 所述多个奇数行公共 电极条为一体结构， 所述多个偶数行公共电极条为一体结构。
6、 根据权利要求 4 或 5所述的阵列基板， 其中， 所述第一输出端 和所述第二输出端均采用栅线金属层制成。
7、 一种显示装置， 包括如权利要求 1-6任一项所述的阵列基板。
8、 一种阵列基板驱动方法， 所述阵列基板包括由横纵交叉的多条 栅线和多条数据线划分成的呈矩阵状排列的多个像素单元， 每个所述像 素单元包括像素电极， 每个所述像素单元还包括公共电极， 所述方法包 括：
在进行第一帧画面显示时， 向在所述像素单元矩阵中行列数之和为 2n- l的像素单元对应的公共电极输入第一电压；
向在所述像素单元矩阵中行列数之和为 2n 的像素单元对应的公共 电极输入第二电压， 所述第一电压和所述第二电压极性相反；
其中， n为自然数。
9、 根据权利要求 8 所述的阵列基板驱动方法， 其中， 所述方法还 包括：
在进行第二帧画面显示时， 向第一帧画面显示时电压为所述第一电 压的所述公共电极输入所述第二电压， 向第一帧画面显示时电压为所述 第二电压的所述公共电极输入所述第一电压。
PCT/CN2013/089286 2013-09-13 2013-12-12 阵列基板及其驱动方法、显示装置 WO2015035724A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/408,683 US9812079B2 (en) 2013-09-13 2013-12-12 Array substrate, driving method thereof and display apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN2013104202949A CN103472605A (zh) 2013-09-13 2013-09-13 一种阵列基板及其驱动方法、显示装置
CN201310420294.9 2013-09-13

Publications (1)

Publication Number Publication Date
WO2015035724A1 true WO2015035724A1 (zh) 2015-03-19

Family

ID=49797512

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2013/089286 WO2015035724A1 (zh) 2013-09-13 2013-12-12 阵列基板及其驱动方法、显示装置

Country Status (3)

Country Link
US (1) US9812079B2 (zh)
CN (1) CN103472605A (zh)
WO (1) WO2015035724A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI571671B (zh) * 2016-02-19 2017-02-21 友達光電股份有限公司 液晶顯示面板
CN107749283B (zh) * 2017-11-06 2020-05-29 深圳市华星光电半导体显示技术有限公司 液晶显示装置
TWI712025B (zh) * 2019-12-25 2020-12-01 友達光電股份有限公司 畫素電路的驅動方法
CN113808515B (zh) * 2021-09-23 2022-07-12 惠科股份有限公司 公共电极结构、驱动方法及显示设备

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6335721B1 (en) * 1998-03-27 2002-01-01 Hyundai Electronics Industries Co., Ltd. LCD source driver
US20030095091A1 (en) * 2001-11-16 2003-05-22 Fujitsu Limited Liquid crystal display
JP2003255909A (ja) * 2002-03-05 2003-09-10 Casio Comput Co Ltd 表示駆動装置
US20050001808A1 (en) * 2003-07-04 2005-01-06 Lee Jae Kyun Method for driving in-plane switching mode liquid crystal display device
CN1677476A (zh) * 2004-02-19 2005-10-05 三星Sdi株式会社 液晶显示器及其驱动方法
CN101308271A (zh) * 2008-06-30 2008-11-19 昆山龙腾光电有限公司 液晶面板、液晶显示装置及其驱动方法
CN101446724A (zh) * 2008-12-16 2009-06-03 昆山龙腾光电有限公司 液晶显示装置、阵列基板及其缺陷修补方法
CN102231025A (zh) * 2011-08-04 2011-11-02 南京中电熊猫液晶显示科技有限公司 多畴垂直配向型液晶显示面板及其像素结构

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040084018A (ko) * 2003-03-26 2004-10-06 삼성전자주식회사 액정 표시 장치
KR101030694B1 (ko) * 2004-02-19 2011-04-26 삼성전자주식회사 액정표시패널 및 이를 갖는 액정표시장치
JP4593161B2 (ja) * 2004-04-30 2010-12-08 三菱電機株式会社 液晶表示装置
TWI255384B (en) * 2004-10-29 2006-05-21 Innolux Display Corp An IPS liquid crystal display apparatus
KR100892613B1 (ko) * 2007-04-25 2009-04-08 삼성전자주식회사 액정 패널 및 이를 구비하는 액정 표시 장치
TWI386902B (zh) * 2008-03-18 2013-02-21 Au Optronics Corp 基於點反轉操作之液晶顯示裝置
KR20090116095A (ko) * 2008-05-06 2009-11-11 삼성전자주식회사 액정 표시 장치
JP2012242761A (ja) 2011-05-23 2012-12-10 Kyocera Display Corp 液晶表示装置の駆動装置
KR101883338B1 (ko) * 2011-09-09 2018-07-31 엘지디스플레이 주식회사 액정표시장치의 도트 인버전 제어방법
CN102654988A (zh) * 2012-03-23 2012-09-05 京东方科技集团股份有限公司 液晶显示器驱动电路、液晶显示区及其驱动方法
CN102749775B (zh) * 2012-06-28 2015-02-11 京东方科技集团股份有限公司 阵列基板、显示装置和驱动所述阵列基板的方法
CN102955310B (zh) * 2012-10-26 2015-04-15 京东方科技集团股份有限公司 一种像素驱动结构、驱动方法及显示装置
CN203444220U (zh) * 2013-09-13 2014-02-19 合肥京东方光电科技有限公司 一种阵列基板及显示装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6335721B1 (en) * 1998-03-27 2002-01-01 Hyundai Electronics Industries Co., Ltd. LCD source driver
US20030095091A1 (en) * 2001-11-16 2003-05-22 Fujitsu Limited Liquid crystal display
JP2003255909A (ja) * 2002-03-05 2003-09-10 Casio Comput Co Ltd 表示駆動装置
US20050001808A1 (en) * 2003-07-04 2005-01-06 Lee Jae Kyun Method for driving in-plane switching mode liquid crystal display device
CN1677476A (zh) * 2004-02-19 2005-10-05 三星Sdi株式会社 液晶显示器及其驱动方法
CN101308271A (zh) * 2008-06-30 2008-11-19 昆山龙腾光电有限公司 液晶面板、液晶显示装置及其驱动方法
CN101446724A (zh) * 2008-12-16 2009-06-03 昆山龙腾光电有限公司 液晶显示装置、阵列基板及其缺陷修补方法
CN102231025A (zh) * 2011-08-04 2011-11-02 南京中电熊猫液晶显示科技有限公司 多畴垂直配向型液晶显示面板及其像素结构

Also Published As

Publication number Publication date
US20150339991A1 (en) 2015-11-26
US9812079B2 (en) 2017-11-07
CN103472605A (zh) 2013-12-25

Similar Documents

Publication Publication Date Title
JP5643422B2 (ja) 液晶表示装置
CN109426041B (zh) 一种阵列基板及显示装置
US10338445B2 (en) Pixel driving structure and liquid crystal display panel
CN104865737B (zh) 一种显示面板、其驱动方法及显示装置
US20170263170A1 (en) Array Substrate, Display Device and Driving Method Thereof
JP6324679B2 (ja) 画素ユニット、画素構造、表示装置及び画素駆動方法
US10424263B2 (en) Liquid crystal display device
WO2017059711A1 (zh) 阵列基板、显示面板及其驱动方法
KR101634854B1 (ko) 액정 표시 장치 및 전자 기기
US20070097052A1 (en) Liquid crystal display device
WO2015018168A1 (zh) 阵列基板、显示装置及显示装置驱动方法
WO2017031944A1 (zh) 像素单元驱动电路、驱动方法和显示装置
CN105629607A (zh) 一种阵列基板、显示面板和显示装置
WO2015035724A1 (zh) 阵列基板及其驱动方法、显示装置
WO2019192082A1 (zh) 一种液晶显示器
WO2013139149A1 (zh) 液晶显示器驱动电路、液晶显示器及其驱动方法
WO2013166815A1 (zh) 阵列基板、液晶面板以及显示装置
CN109416490B (zh) 液晶显示面板、液晶显示装置及操作液晶显示面板的方法
CN203444220U (zh) 一种阵列基板及显示装置
US20160357075A1 (en) Array substrate and display device
CN103616784A (zh) 一种液晶显示装置
KR102175279B1 (ko) 액정표시장치
CN104199205B (zh) 一种显示装置
WO2019144470A1 (zh) 一种显示面板及液晶显示器
KR101406290B1 (ko) 액정 표시 장치

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14408683

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13893491

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13893491

Country of ref document: EP

Kind code of ref document: A1