WO2015027237A1 - Entrelaceur paramétré destiné à un système multidébit - Google Patents

Entrelaceur paramétré destiné à un système multidébit Download PDF

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Publication number
WO2015027237A1
WO2015027237A1 PCT/US2014/052528 US2014052528W WO2015027237A1 WO 2015027237 A1 WO2015027237 A1 WO 2015027237A1 US 2014052528 W US2014052528 W US 2014052528W WO 2015027237 A1 WO2015027237 A1 WO 2015027237A1
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WO
WIPO (PCT)
Prior art keywords
interleaver
delay
arms
parameters
arm
Prior art date
Application number
PCT/US2014/052528
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English (en)
Inventor
Ed SCHELL
Carl Scarpa
Original Assignee
Sirius Xm Radio Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sirius Xm Radio Inc. filed Critical Sirius Xm Radio Inc.
Priority to CA2922121A priority Critical patent/CA2922121A1/fr
Publication of WO2015027237A1 publication Critical patent/WO2015027237A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2789—Interleaver providing variable interleaving, e.g. variable block sizes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2732—Convolutional interleaver; Interleavers using shift-registers or delay lines like, e.g. Ramsey type interleaver

Definitions

  • the present invention relates generally to digital coding and framing of signals on a
  • a parameterized interleaver structure is presented.
  • the interleaver is designed to specify and maintain a maximum delay, irrespective of code rate and number of code blocks.
  • the disclosed interleaver in effect concatenates two interleaver structures together.
  • the arm delay is calculated using a set of parameters M2, D2, and N, where M2 is a maximum delay for an interleaver arm, D2 is the delay decrement, and N is the arm index, running from 1 to N, where N is the total number of arms in the interleaver.
  • the delay can be calculated in a similar manner, but using a second set of parameters, namely Ml, Dl, and N instead, which involves a different delay length.
  • This approach has the dual benefit of specifying both the maximum delay of the interleaver and the minimum required delay to process data.
  • Fig. 1 illustrates an exemplary standard convolutional interleaver
  • Fig. 2 illustrates an exemplary uniform convolutional interleaver
  • Figs. 3-5 illustrate arm lengths of exemplary interleavers for respective delays of 0.25, 1.0, and 0.2, respectively, all other interleaver parameters being equal;
  • Fig. 6 depicts an exemplary multi-rate interleaver according to an exemplary embodiment of the present invention.
  • Fig. 7 depicts an alternate multi-rate interleaver according to an exemplary embodiment of the present invention.
  • Modern communication systems are often designed to be completely flexible. Thus, they generally contain the flexibility to simultaneously have different modulation, throughputs, delays, and coding rates merged within the same transmission scheme. These options are often programmable, and can be altered with a simple configuration change.
  • One of the challenges comes in designing a convenient and sensible interleaver structure that can easily accommodate the inherent flexibility in these modern designs.
  • Exemplary embodiments of the present invention include a new parameterized interleaver structure that is capable of addressing this problem.
  • Communication systems commonly employ a convolutional interleaver, as shown in Fig. 1.
  • the depicted interleaver delivers a fixed number of input bits on each arm, rotating through all the arms before repeating the sequence.
  • Each arm contains a FIFO of some configurable delay size.
  • the delay size of each arm can be any arbitrary size, depending on the desired dispersion effect.
  • the interleaver delivers an equal number of bits from the output of the FIFO on each interleaver arm.
  • Fig. 2 illustrates a more specific case of an interleaver, namely a uniform convolutional interleaver, where the delay size of each arm begins at zero and increments a fixed amount for each subsequent arm.
  • Such an interleaver is described by the number of arms (N), the delay unit increment per arm (D), and the size (S) of the delay unit (usually in bits or bytes).
  • Fig. 2 illustrates an example of a uniform convolutional interleaver.
  • the goal of the interleaver is to spread the encoded data in time, such that any momentary channel distortions, such as, for example, Fades, are evenly distributed to all of the encoded data blocks.
  • each coded block of data will experience a portion of the fade, allowing Forward Error Correction ("FEC") processing to recover the faded data without errors. If there were no interleaver, or if there was an insufficient interleaver, the FEC would fail to decode the data, resulting in errors in the final output. The effectiveness of the interleaver is thus dependent upon (i) the maximum delay and (ii) the distribution of delays amongst its various arms.
  • FEC Forward Error Correction
  • an interleaver structure allows for each code rate to have a different number of arms. Regardless of the code rate used in a block, each code block will be delivered in a single pass through the arms, beginning at the first arm for each new code block and stopping at every other arm in the interleaver exactly once. The number of arms is fixed within a system for each code rate, specified by the parameter N.
  • the size of N depends on the size of the delay unit, denoted by the parameter S. This also determines the number of symbols at a given time that are delivered to the interleaver arm. In exemplary embodiments of the present invention, the value of S may, for example, be chosen as common factor to all the code rates, in order to get the best memory efficiency in an actual implementation. However, in order to reach a common number for all of the different rates, it may be necessary in some embodiments to pad the block size. Table 1 below provides an exemplary set of interleaver parameters for a particular family of code rates with an uncoded data size of 12168 bits. Code Rate 1/3 3/8 2/5 3/7 1/2 6/11 3/5 2/3 3/4
  • the maximum delay may be specified as multiples of a Master Frame unit. It noted that in a system where multiple streams of data are multiplexed together, they are often synchronized to a larger unit of time called the Master Frame. For example, it may be assumed that the Master Frame duration is 0.5 seconds. Therefore, in exemplary embodiments of the present invention, an exemplary interleaver structure can first be specified by setting the maximum desired delay experienced by a given datastream to be integer multiples of the Master Frame, here 0.5s. This parameter will be denoted M2 in this disclosure.
  • D refers to a delay unit generally.
  • D2 refers to the longer delay unit in a multi rate interleaver, as shown in Figs. 6-7, and Dl to the shorter delay unit in such a structure; in some contexts, if there is no Dl, the maximum delay operative for the entire interleaver can be referred to as D2).
  • the value of, for example, D2 may be presented as either a fraction or an integer number.
  • the delay of the branches can thus be calculated as follows:
  • the delay may not change over a given number of nearby interleaver branches. This situation is depicted in Fig. 3, where the delay unit D2 is 0.25, and thus there are only 25 separate delay lengths used for the 100 arms of the exemplary interleaver.
  • Figs. 3-5 show the arm delays from the receiver perspective (the delays being shown in the blue (dark) bars at the left side of each plot).
  • a transmitter would implement the complement of this structure (essentially the white background), and thus given the interleaving on the transmitter and the de-interleaving process on the receiver the overall delay is uniform for data in any arm.
  • the parameters N (number of arms) and M (maximum delay) are constant, the only variance being in D, the unit delay length.
  • Fig. 3 illustrates arm length for a delay of 0.25
  • Fig. 5 illustrates arm length for a delay of 0.2.
  • the minimum system latency introduced by an interleaver is dependent on the FEC.
  • advanced coding systems such as, for example, Turbo or LDPC, can potentially decode the data with a little more than R*100% of the encoded symbols present, given a high enough SNR.
  • a rate 1 ⁇ 2 code can begin decoding the data with little more than 1 ⁇ 2 the number of interleaver arms filled with good data, i.e., it only needs about 50% of the encoded symbols to start decoding accurtaely. Therefore, the minimum delay of a rate 1 ⁇ 2 code depends on the size of the longest arm that is needed to supply a little more than 1 ⁇ 2 of the data to the FEC after startup.
  • the interleaver structure can take advantage of this fact by providing additional parameters so as to set a lower maximum delay within a subsection of the interleaver arms.
  • additional parameters are denoted Ml, Dl, and Nl, representing the Maximum Delay, Delay Decrement, and Highest Arm Number, respectively, for the
  • the inventive interleaver concatenates two interleaver structures together.
  • the arm delay is calculated using the M2, D2, and N parameters, as before.
  • the delay can be calculated in a similar manner, but using the additional Ml, Dl, and Nl parameters instead, which involves a different delay length.
  • This novel approach has the dual benefit of specifying both the maximum delay of the interleaver and the minimum required delay to process data.
  • Fig. 6 illustrates an exemplary configuration combining the two distinct parameter sets. With reference thereto, there is a maximum delay of 24 frames and a shorter delay of 10 frames within 1 ⁇ 2 of the number of arms.
  • Nl is here set to 50.
  • Nl could be set to 33 or 34.
  • An additional component of the disclosed design is the ability to specify a rate multiple.
  • the interleaver parameters were defined with reference to what a single code block would experience.
  • multiple code blocks are sent for a given rate within the same Master Frame unit.
  • multiple parallel interleaver structures working independently on each code block, a more convenient approach is to aggregate these into a single structure for a given rate.
  • an additional parameter representing the number of code blocks within a Master Frame Unit for a given rate can be used, denoted as RM or "Rate Multiple.” In this manner, every code block will still experience the same delay profile within a single structure.
  • this number is a simple scaling of the Ml, M2, Dl, and D2 parameters by RM. This is shown in Fig. 7, for example, where the RM factor is equal to 4.
  • the following is sample Matlab code that can be used to build the exemplary interleaver structure depicted in Fig. 7, which implements a Rate Multiple of 4, as noted. It may also be used to build the exemplary interleaver structure of Fig. 6, if RM is set to 1 instead of 4 (i.e., no Rate Multiple used).
  • N 100; %Number of Arms
  • Nl 50; %Arm number for cutoff of 1st stage
  • N N1;
  • armLen(i) M - mod(frx((N-i)*D),M+RM);
  • RM values may be, obviously whatever number is convenient, such as, for example, 6, 8, 12, 16, etc.
  • the interleaver structure described above provides a unique approach to dealing with multi- rate systems.
  • a convenient parameterized approach allows the specification of Maximum delays, common across all rate definitions.
  • the concatenation of two independent stages takes advantage of the higher performing iterative decodes by providing early access to the data with a Minimum Delay specification.
  • the concept of a rate multiplier makes it easy to aggregate the interleaving into a single structure, providing the same delay profile for each code block regardless of the amount of data being transmitted for a given rate.
  • the Rate Multiple is the number of code blocks being transmitted within a Master Frame Unit.
  • the number of code blocks being transmitted is dependent on the code rate chosen for the data, the size of the Master Frame Unit, and how much of that Master Frame Unit the user wants to allocate to that code rate.
  • the extension to this is a Master Frame Unit consisting of multiple "Pipes" of data, each with its own code rate and interleaver structure.
  • the novel interleaver disclosed herein may be used in a satellite radio communications system, such as that provided by Sirius XM Radio Inc., assignee hereof.
  • a satellite radio broadcasting service has a combination of terrestrial and satellite based signals that each receiver receives, such as Satellite Mobile, Terrestrial Mobile, etc.
  • the satellite channel can experience long signal blockage, such as when a vehicle having an SDARS receiver goes under a bridge. This would require a large value for M2 (multiple seconds), enough to be longer than such long signal blockages.
  • M2 multiple seconds
  • Ml could here be used to speed up the startup and recovery time by setting Nl equal to the minimum number of segments needed to decode the signal under high SNR.
  • M2 may be set much lower than the multiple second delay for the Satellite channel, here say 1-2 seconds, and Ml/Nl (the parameters for a faster subsection of the interleaver) may not be used at all (i.e., set to zero).
  • the structure of two combined interleavers into one is not limited to two subsections.
  • an effective bulk delay may be added to (or subtracted from) each arm in a subsection, if desired.
  • Fig. 6 it is useful in some contexts to have the smoothly changing delay values as a function of the arm number seen in the upper portion of the plot, in arms where N goes from 51-100. But as can be seen, and as explained in connection with Fig. 4, because the D2 value is 1.0, the values of the delays repeat in two portions of arms 51-100.
  • arms 100 to 51 would run from 24 down to 10, or 11, for example, and only the lower portion of the interleaver actually have delays less than 10. This adds a bulk delay to each arm above Nl, effectively. This can be handled by adding a delay to some arms in the D(i) equation (Equation A), or for example, by adjusting D2 such that is smoothly varies from M2 to Ml, depending upon the desired values. Various permutations are understood to be possible, and all within the scope of the present invention.
  • the ratio of M2 to Ml can be larger, or much smaller than, that shown in Figs. 6 and 7, depending upon the code rates, channel characteristics and other factors applying to any given real world system.
  • interleaver parameters may be chosen to achieve this.
  • a bulk delay can be added to (or subtracted from) the interleaver arms, as noted above, so as to synchronize interleaver cycles with frame boundaries in various exemplary embodiments.
  • any suitable programming language may be used to implement the routines of particular embodiments including C, C++, Java, JavaScript, Python, Ruby, CoffeeScript, assembly language, etc.
  • Different programming techniques may be employed such as procedural or object oriented.
  • the routines may execute on a single processing device or multiple processors. Although the steps, operations, or computations may be presented in a specific order, this order may be changed in different particular
  • Particular embodiments may be implemented in a computer-readable storage device or non- transitory computer readable medium for use by or in connection with the instruction execution system, apparatus, system, or device.
  • Particular embodiments may be implemented in the form of control logic in software or hardware or a combination of both.
  • the control logic when executed by one or more processors, may be operable to perform that which is described in particular embodiments.
  • Particular embodiments may be implemented by using a programmed general purpose digital computer, by using application specific integrated circuits ("ASICs"), programmable logic devices, field programmable gate arrays, optical, chemical, biological, quantum or nano- engineered, systems, components and mechanisms.
  • ASICs application specific integrated circuits
  • Such embodiments may be implemented using both ASICs and general purposes computers or data processors, or standard chipsets, for example, distributing different functions across various possible elements and modules, either hardware or software.
  • the functions of particular embodiments may be achieved by any means as is known in the art. Distributed, networked systems, components, and/or circuits may be used. Communication, or transfer, of data may be wired, wireless, or by any other means.
  • Particular embodiments may be implemented in both a transmitter and a receiver of a broadcast communications system and service, such as, for example, a satellite radio service, or an SDARS.
  • the transmitter based interleaver may be implemented in software, for example, and the receiver based interleaver in an ASIC.
  • Parameters including, for example, M2, Ml, N, Nl, D2 and Dl, and, if applicable, N3, D3 and M3m may be passed from the transmitter to the receiver at any time, thus modifying the interleaver on the receiver as may be desired.

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  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

L'invention concerne une structure d'entrelaceur paramétré. L'entrelaceur est conçu pour spécifier et maintenir un retard maximum indépendamment du rendement de code et du nombre de blocs de code. L'entrelaceur selon l'invention effectue en fait une concaténation de deux structures d'entrelaceur l'une avec l'autre. Si l'indice de branche est supérieur à un nombre défini N1, le retard de branche est calculé en utilisant un ensemble de paramètres M2, D2 et N, dans lequel M2 est un retard maximum pour une branche de l'entrelaceur, D2 est le décrément du retard et N est l'indice de branche, allant de 1 à N, N étant le nombre total de branches de l'entrelaceur. Si toutefois l'indice de branche N est inférieur ou égal à N1, le retard peut être calculé de manière similaire, mais en utilisant un second ensemble de paramètres, à savoir M1, D1 et N, ce qui implique une longueur différente du retard. Cette approche a pour double avantage de spécifier à la fois le retard maximum de l'entrelaceur et le retard minimum nécessaire pou traiter les données.
PCT/US2014/052528 2013-08-23 2014-08-25 Entrelaceur paramétré destiné à un système multidébit WO2015027237A1 (fr)

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CA2922121A CA2922121A1 (fr) 2013-08-23 2014-08-25 Entrelaceur parametre destine a un systeme multidebit

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060248431A1 (en) * 2000-07-05 2006-11-02 Lg Electronics Inc. Method of configuring transmission in mobile communication system
US20070226598A1 (en) * 2006-03-17 2007-09-27 Mao-Ching Chiu Encoding and decoding methods and systems
US20090172492A1 (en) * 2007-08-01 2009-07-02 Sirius Xm Radio Inc. Method and apparatus for interleaving low density parity check (LDPC) codes over mobile satellite channels
KR20100118988A (ko) * 2008-07-13 2010-11-08 엘지전자 주식회사 이동통신 시스템에서 ｃｔｃ(ｃｏｎｖｏｌｕｔｉｏｎａｌ ｔｕｒｂｏ ｃｏｄｅ) 인코더를 이용하여 데이터를 전송하기 위한 장치 및 그 방법
US20110289391A1 (en) * 2008-12-23 2011-11-24 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Interleaver device and receiver for a signal generated by the interleaver device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060248431A1 (en) * 2000-07-05 2006-11-02 Lg Electronics Inc. Method of configuring transmission in mobile communication system
US20070226598A1 (en) * 2006-03-17 2007-09-27 Mao-Ching Chiu Encoding and decoding methods and systems
US20090172492A1 (en) * 2007-08-01 2009-07-02 Sirius Xm Radio Inc. Method and apparatus for interleaving low density parity check (LDPC) codes over mobile satellite channels
KR20100118988A (ko) * 2008-07-13 2010-11-08 엘지전자 주식회사 이동통신 시스템에서 ｃｔｃ(ｃｏｎｖｏｌｕｔｉｏｎａｌ ｔｕｒｂｏ ｃｏｄｅ) 인코더를 이용하여 데이터를 전송하기 위한 장치 및 그 방법
US20110289391A1 (en) * 2008-12-23 2011-11-24 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Interleaver device and receiver for a signal generated by the interleaver device

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