WO2015014162A1 - 一种soc芯片的mcu唤醒装置和方法 - Google Patents
一种soc芯片的mcu唤醒装置和方法 Download PDFInfo
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- WO2015014162A1 WO2015014162A1 PCT/CN2014/079559 CN2014079559W WO2015014162A1 WO 2015014162 A1 WO2015014162 A1 WO 2015014162A1 CN 2014079559 W CN2014079559 W CN 2014079559W WO 2015014162 A1 WO2015014162 A1 WO 2015014162A1
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000001514 detection method Methods 0.000 claims abstract description 20
- 238000003708 edge detection Methods 0.000 claims description 10
- 230000007704 transition Effects 0.000 claims description 9
- 230000000630 rising effect Effects 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 3
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims 2
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- 238000010586 diagram Methods 0.000 description 6
- 230000005284 excitation Effects 0.000 description 4
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- 238000005516 engineering process Methods 0.000 description 1
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- 238000006467 substitution reaction Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- the present invention relates to the field of electronic circuit technologies, and in particular, to an MCU wake-up device and method for an SOC chip. Background technique
- the method of waking up the MCU basically adopts a standard interface or directly wakes up the MCU with a single signal.
- the standard interface wake-up can well avoid the squeaking, but the wake-up timing is complicated, the chip must also have this interface.
- a single signal directly wakes up the MCU. Although it is easy to wake up, it is sensitive to the donkey and can easily cause additional wakeup.
- the technical problem to be solved by the present invention is to provide an MCU wake-up device and method for a SOC chip to solve an error wakeup caused by an external interference signal when a single signal is used to directly wake up the MCU.
- an MCU wake-up device of an SOC chip includes an external wake-up signal detecting module, an interrupt request generating module, an interrupt service program module, and a gated clock, wherein: an external wake-up signal detecting module is configured to detect After the valid external wake-up signal, an internal wake-up signal is generated and output to the interrupt request generation module;
- An interrupt request generation module is configured to generate a gated clock enable signal after receiving an internal wakeup signal Output to the gated clock, generate an interrupt request signal output to the interrupt service routine module;
- a gated clock outputting a system clock to an interrupt request generation module and an MCU according to a gated clock enable signal, a sleep signal state, and a register configuration signal state;
- the interrupt service program module is configured to configure the gated clock control register to be in an active state after receiving the interrupt request signal, and generate an interrupt exit signal output to the MCU.
- the interrupt service program module is further configured to generate an internal wake-up signal clear signal output to the external wake-up signal detecting module; correspondingly, the external wake-up signal detecting module is further configured to receive the internal wake-up signal clear signal output by the interrupt service program module. , clear the internal wake-up signal.
- the effective external wake-up signal refers to a high level or low level signal for a predetermined period of time.
- the external wake-up signal detecting module comprises a counter, a comparator and a resetter, wherein: a counter, configured to sample and count the external wake-up signal under the excitation of the detection clock, and output the count value to the comparator; Receiving the counter value of the counter, and comparing the count value with a predetermined threshold value, when the counter value is greater than or equal to a predetermined threshold value, the internal wake-up signal is output, otherwise the internal wake-up signal is not output; the resetter is used for Receive external wake-up signal, internal wake-up signal and internal wake-up signal clear signal. When the internal wake-up signal clear signal is valid, or the external wake-up signal and internal wake-up signal are invalid, a valid counter reset signal is output to the counter, otherwise the output invalid counter is reset. Signal to the counter.
- a counter configured to sample and count the external wake-up signal under the excitation of the detection clock, and output the count value to the comparator
- Receiving the counter value of the counter and comparing the count value with a
- the counter is specifically configured to: when the counter reset signal is valid, the count value is zero; when the counter reset signal is invalid, the count value is incremented by one each time the detection clock detects that the external wake-up signal is valid on the rising edge.
- the interrupt request generating module includes: an enable signal generating unit, a peer unit and a edge detecting unit, wherein: an enable signal generating unit, configured to receive an internal wake-up signal, generated according to an effective level of the internal wake-up signal Gated clock enable signal; the same unit, for receiving the system clock and the internal wake-up signal, the internal wake-up signal is the same as the system clock domain, and the internal wake-up signal is output to the edge detection unit; the edge detection Unit, used to detect the jump of the internal wake-up signal After the change edge, the interrupt request signal is output.
- an enable signal generating unit configured to receive an internal wake-up signal, generated according to an effective level of the internal wake-up signal Gated clock enable signal
- the same unit for receiving the system clock and the internal wake-up signal, the internal wake-up signal is the same as the system clock domain, and the internal wake-up signal is output to the edge detection unit
- the edge detection Unit used to detect the jump of the internal wake-up signal After the change edge, the interrupt request signal is output
- the enable signal generating unit is specifically configured to: if the active level of the internal wake-up signal is high, the gated clock enable signal is an internal wake-up signal, otherwise the gated clock enable signal is the reverse of the internal wake-up signal value.
- an MCU wake-up method of an SOC chip includes: generating an internal wake-up signal after detecting a valid external wake-up signal;
- the gating clock control register is configured to be in an active state, and an interrupt exit signal is generated to be outputted to, preferably, an internal wake-up signal is generated after detecting a valid external wake-up signal, further comprising: receiving an external wake-up signal;
- the MCU wake-up device and method for the SOC chip provided by the present invention wake up the MCU with a single signal, but the external single signal is not directly used to wake up the MCU, and the external wake-up signal detection module filters out the fake wake-up signal, and then utilizes the detected true
- the wake-up signal is used to generate the system interrupt, and finally the MCU is completely woken up in the interrupt handler module, avoiding the error wake-up action generated by the external interference signal. Whether it is used for internal wake-up or external wake-up, it is simple and reliable, which not only ensures the security of wake-up, but also avoids the amount.
- FIG. 1 is a schematic structural diagram of an MCU wake-up device of an SOC chip according to an embodiment of the present invention.
- 2 is a schematic structural diagram of an external wake-up signal detecting module according to a preferred embodiment of the present invention.
- FIG. 3 is a schematic structural diagram of an interrupt request generating module according to a preferred embodiment of the present invention.
- FIG. 4 is a flowchart of an MCU wake-up method of an SOC chip according to an embodiment of the present invention.
- FIG. 5 is a flowchart of an MCU wakeup method of a SOC chip according to a preferred embodiment of the present invention. detailed description
- FIG. 1 is a schematic structural diagram of an MCU wake-up device of an SOC chip according to an embodiment of the present invention.
- the device includes: an external wake-up signal detecting module 10, an interrupt request generating module 20, a gated clock 30, and an interrupt service program module 40. among them:
- the external wake-up signal detecting module 10 is configured to generate an internal wake-up signal after detecting a valid external wake-up signal, and output the interrupt request generating module 20;
- the interrupt request generation module 20 is configured to: after receiving the internal wake-up signal, generate a gated clock enable signal to the gated clock 30, and generate an interrupt request signal to the interrupt service program module 40;
- a gated clock 30, configured to output a system clock to the interrupt request generation module 20 and the MCU according to the gated clock enable signal, the sleep signal state, and the gated clock register configuration signal state;
- the interrupt service program module 40 is configured to configure the control register of the gated clock 40 to be in an active state after receiving the interrupt request signal, and generate an interrupt exit signal output to the MCU.
- the interrupt service program module 40 is further configured to generate an internal wake-up signal clear signal output to the external wake-up signal detecting module 10; correspondingly, externally
- the wake-up signal detecting module 10 is further configured to receive an interrupt service routine After the internal wake-up signal is cleared by the sequence module 40, the internal wake-up signal is cleared.
- the effective external wake-up signal means that the external wake-up signal is a high level or low level signal for a predetermined period of time.
- the input signal of the external wake-up signal detecting module 10 is an external wake-up signal and a detection clock, and the external wake-up signal detecting module 10 generates an internal wake-up after detecting a valid external wake-up signal according to a certain standard under the excitation of the detection clock.
- the signal is output to the interrupt request generation module 20.
- the input signal of the interrupt request generating module 20 is an internal wake-up signal and a system clock, and the interrupt request generating module 20 generates a gated clock enable signal and an interrupt request signal respectively after receiving the internal wake-up signal, and outputs the gated clock enable signal.
- the interrupt request signal is output to the interrupt service routine module 40; wherein the gated clock enable signal and the interrupt request signal are invalidated as the internal wake-up signal is invalid.
- the input signals of the gated clock 30 are a gated clock enable signal, a gated clock control register configuration signal, and a sleep signal. When it is detected that the gated clock enable signal is valid and the gated clock control register configuration signal is valid and the sleep signal is invalid. , output system clock, stop outputting system clock when it detects that the gate clock enable signal is invalid and the gate clock control register configuration signal is invalid and the sleep signal is valid.
- the input signal of the interrupt service program module 40 is an interrupt request signal, and the output signal is an internal wake-up signal clear signal, a gated clock control register configuration signal, and an interrupt exit signal, and the interrupt service program module 40 causes the MCU to enter an interrupt according to the received interrupt request signal.
- the service program configures the gated clock control register to an active state in the interrupt service routine, and then generates an internal wake-up signal clear signal, and finally generates an interrupt exit signal.
- the input signals of the MCU are the system clock and the interrupt exit signal.
- the MCU is the carrier of the interrupt service program module 40. The functions in the interrupt service program module 40 need to be completed by the MCU, and the sleep signal of the MCU entering the sleep mode is also sent by the MCU.
- FIG. 2 is a schematic structural diagram of an external wake-up signal detecting module according to a preferred embodiment of the present invention.
- the module includes a counter 101, a comparator 102, and a resetter 103, where:
- a counter 101 configured to sample and count an external wake-up signal under the excitation of the detection clock, The count value is output to the comparator 102;
- the comparator 102 is configured to receive the counter value of the counter 101, and compare the count value with a predetermined threshold value. When the counter value of the counter is greater than or equal to a predetermined threshold value, the internal wake-up signal is output, otherwise the internal wake-up signal is not output. ;
- the resetter 103 is configured to receive an external wake-up signal, an internal wake-up signal, and an internal wake-up signal clear signal.
- an internal wake-up signal clear signal is valid, or both the external wake-up signal and the internal wake-up signal are invalid, a valid counter reset signal is output to the counter 101. Otherwise, an invalid counter reset signal is output to the counter 101.
- the input signals of the counter 101 are an external wake-up signal, a detection clock, and a counter reset signal, and the output signal is a counter count value.
- the counter 101 samples and counts the external wake-up signal under the excitation of the detection clock, and then outputs the count value to Comparator 102.
- the counter 101 when the counter reset signal is valid, the counter 101 has a count value of zero, otherwise the value of the counter 101 is incremented by one every time the detection clock detects that the external wake-up signal is valid on the rising edge.
- the input signal of the comparator 102 is the count value of the counter 10, the output signal is an internal wake-up signal, and the comparator 102 functions to compare the count value and the threshold value of the counter 101.
- the output When the count value of the counter 101 is greater than or equal to the threshold value, the output is output. Internal wake-up signal, otherwise the internal wake-up signal is not output.
- the threshold value is a relatively fixed value. It represents the high level or low level of how many detection clock cycles the external wake-up signal lasts. It can be set differently depending on the application scenario. Value.
- the input signal of the resetter 103 is an external wake-up signal, an internal wake-up signal clear signal and an internal wake-up signal, and the output signal is a counter reset signal. When the internal wake-up signal clear signal is valid or the external wake-up signal and the internal wake-up signal are invalid, the output is output. A valid counter reset signal, otherwise an invalid counter reset signal is output.
- the working principle of the external wake-up signal detecting module is to use the counter 101 to count the external wake-up signal.
- the external wake-up signal is satisfied, and then the external wake-up condition is satisfied.
- An internal wake-up signal is generated. If the external wake-up signal transitions to an inactive state during counting, the resetter 103 generates a counter reset signal for clearing the counter count value, and when it is checked again that the external wake-up signal is valid, Restart counting.
- the external wake-up signal detecting module can also be implemented by other means as long as it can be judged that the external wake-up signal is a high level or low level signal for a predetermined period of time.
- FIG. 3 is a schematic structural diagram of an interrupt request generating module according to a preferred embodiment of the present invention.
- the module includes an enable signal generating unit 201, a peer unit 202, and a edge detecting unit 203, wherein: an enable signal generating unit 201, configured to receive an internal wake-up signal, and generate a gated clock enable signal according to an active level of the internal wake-up signal;
- the peer unit 202 is configured to receive the system clock and the internal wake-up signal, and compare the internal wake-up signal to the system clock domain, and output the internal wake-up signal to the edge detection unit 203;
- the edge detection unit 203 is configured to output an interrupt request signal after detecting a transition edge of the internal wake-up signal.
- the input signal of the enable signal generating unit 201 is an internal wake-up signal
- the output signal is a gated clock enable signal
- the enable signal generating unit 201 generates a gated clock enable signal according to an active level of the internal wake-up signal.
- the gated clock enable signal is equal to the internal wake-up signal, otherwise the gated clock enable signal is equal to the opposite value of the internal wake-up signal.
- the input signal of the peer unit 202 is the system clock and the internal wake-up signal, and the output is the internal wake-up signal homologous signal, and the peer unit 202 is used to clamp the internal wake-up signal to the system clock domain, that is, only on the rising edge of the system clock.
- the internal wake-up signal is sampled and the internal wake-up signal is updated. When there is no system clock, the internal wake-up signal remains unchanged.
- the input signal of the edge detection unit 203 is an internal wake-up signal and the output signal is an interrupt request signal, and the edge detection unit 203 is configured to detect the edge of the internal wake-up signal, that is, from the high level to A low level transition, or a low level to a high level transition, when a transition edge is detected, the edge detection unit 203 outputs a pulse signal of a system clock width, that is, an interrupt request signal.
- FIG. 4 is a flowchart of an MCU wakeup method of an SOC chip according to an embodiment of the present invention, where the method includes the following steps:
- the S40 U generates an internal wake-up signal after detecting a valid external wake-up signal
- the MCU sleep and wake-up are implemented by a gated clock.
- the gated clock When the gated clock is turned off, the MCU enters a sleep state, and when the gated clock is turned on, the MCU starts to work.
- the MCU When the MCU needs to go to sleep, the MCU only needs to issue a sleep command, and it can immediately go to sleep.
- the wake-up process is relatively complicated, and the MCU will start to work normally when the above conditions are met.
- FIG. 5 is a flowchart of an MCU wake-up method of a SOC chip according to a preferred embodiment of the present invention, where the S50 U receives an external wake-up signal;
- step S503 determining whether the external wake-up signal meets the wake-up request, if the wake-up request is not met, executing step S503; if the wake-up request is met, executing step S504;
- the external wake-up signal that satisfies the wake-up requirement should be a high level or low level signal that lasts for a while.
- the external wake-up signal is a single wake-up signal external to the MCU, and the external wake-up signal detecting module analyzes the received external wake-up signal. If the external wake-up signal does not meet the requirement, the current wake-up request is discarded, and the MCU does not Wake-up, if the external wake-up signal meets the requirements, the external wake-up signal detection module generates an internal wake-up signal of a certain level according to the external wake-up signal, and maintains this level, and then the internal wake-up signal is used as the gated clock. The signal can be used to turn on the gated clock and serve as the interrupt request input signal of the MCU. When the MCU operating clock is turned on, the interrupt request can be detected.
- the MCU enters the interrupt service routine.
- the software configures the gated clock control register as The active state, then generating an internal wake-up signal clear signal that maintains a certain level for a period of time, is used to clear the internal wake-up signal. Since the gated clock control register is already active, the gated clock remains on until the next sleep. Start.
- the MCU wake-up device and method for the SOC chip provided by the embodiment of the present invention wake up the MCU by using a single signal, but the external single signal is not directly used to wake up the MCU, and the external wake-up signal detecting module filters out the fake wake-up signal, and then detects the detected The real wake-up signal generates a system interrupt, and finally wakes up the MCU completely in the interrupt handler module, avoiding the error wake-up action generated by the external interference signal.
- it is used for internal wake-up or external wake-up, it is simple and reliable, which not only ensures the security of wake-up, but also avoids additional wake-up and reduces system power consumption more effectively.
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Abstract
本发明公开了一种SOC芯片的MCU唤醒装置和方法,属于电子电路技术领域。该装置包括:外部唤醒信号检测模块、中断请求产生模块、门控时钟以及中断服务程序模块,外部唤醒信号检测模块检测到有效的外部唤醒信号后产生内部唤醒信号;中断请求产生模块接收到内部唤醒信号后产生门控时钟使能信号和中断请求信号;门控时钟根据门控时钟使能信号、睡眠信号状态和寄存器配置信号状态输出***时钟到中断请求产生模块和MCU;中断服务程序模块接收到中断请求信号后,将门控时钟控制寄存器配置为有效状态,并产生中断退出信号输出到MCU。本发明既保证了唤醒的安全性,又避免额外的唤醒,有效地降低***功耗。
Description
说 明 书
一种 S0C芯片的 MCU唤醒装置和方法
技术领域
本发明涉及电子电路技术领域, 尤其涉及一种 S0C芯片的 MCU唤醒装置和 方法。 背景技术
为了降低 SOC (System on Chip, 片上***)芯片的功耗, 现在大多数芯片都 拥有睡眠和唤醒的功能, 睡眠模式下关断***时钟, 从而达到降低***功耗的 目的。 但是唤醒 MCU (Micro Control Unit , 微控制单元)的方法基本采用标准接 口或者利用单一信号直接唤醒 MCU, 标准接口唤醒虽然可以很好的避免毛剌, 但 是唤醒时序复杂, 还要求芯片必须具有此接口, 单一信号直接唤醒 MCU虽然唤醒 方便, 但是对毛剌比较敏感, 容易造成额外唤醒。 发明内容
有鉴于此, 本发明要解决的技术问题是提供一种 S0C芯片的 MCU唤醒装置 和方法, 以解决利用单一信号直接唤醒 MCU 时由于外部干扰信号产生的错误唤 醒。
本发明解决上述技术问题所采用的技术方案如下:
根据本发明的一个方面, 提供的一种 S0C芯片的 MCU唤醒装置包括外部唤 醒信号检测模块、 中断请求产生模块、 中断服务程序模块以及门控时钟, 其中: 外部唤醒信号检测模块, 用于检测到有效的外部唤醒信号后产生内部唤醒 信号, 输出到中断请求产生模块;
中断请求产生模块, 用于接收到内部唤醒信号后, 产生门控时钟使能信号
输出到门控时钟, 产生中断请求信号输出到中断服务程序模块;
门控时钟, 根据门控时钟使能信号、 睡眠信号状态和寄存器配置信号状态 输出***时钟到中断请求产生模块和 MCU;
中断服务程序模块, 用于接收到中断请求信号后, 将门控时钟控制寄存器 配置为有效状态, 并产生中断退出信号输出到给 MCU。
优选地, 中断服务程序模块, 还用于产生内部唤醒信号清除信号输出到外 部唤醒信号检测模块; 相应地, 外部唤醒信号检测模块还用于接收到中断服务 程序模块输出的内部唤醒信号清除信号后, 清除内部唤醒信号。
优选地, 有效的外部唤醒信号是指持续预定的时间段的高电平或者低电平 信号。
优选地, 外部唤醒信号检测模块包括计数器、 比较器和复位器, 其中: 计 数器, 用于在检测时钟的激励下对外部唤醒信号进行采样和计数, 将计数值输 出到比较器; 比较器, 用于接收计数器的计数值, 并比较计数值和预定的门限 值, 当计数器的计数值大于或等于预定的门限值时, 输出内部唤醒信号, 否则 不输出内部唤醒信号; 复位器, 用于接收外部唤醒信号、 内部唤醒信号和内部 唤醒信号清除信号, 当内部唤醒信号清除信号有效、 或者外部唤醒信号和内部 唤醒信号都无效时, 输出有效的计数器复位信号到计数器, 否则输出无效的计 数器复位信号到计数器。
优选地, 计数器具体用于: 当计数器复位信号有效时, 计数值为零; 当计 数器复位信号无效时, 每当检测时钟在上升沿检测到外部唤醒信号有效时, 计 数值递增 1。
优选地, 中断请求产生模块包括: 使能信号产生单元、 同歩单元和跳变沿 检测单元, 其中: 使能信号产生单元, 用于接收内部唤醒信号, 根据内部唤醒 信号的有效电平, 产生门控时钟使能信号; 同歩单元, 用于接收***时钟和内 部唤醒信号, 将内部唤醒信号同歩到***时钟域, 输出内部唤醒信号同歩信号 到跳变沿检测单元; 跳变沿检测单元, 用于检测到内部唤醒信号同歩信号的跳
变沿后, 输出中断请求信号。
优选地, 使能信号产生单元具体用于: 如果内部唤醒信号的有效电平为高 电平, 则门控时钟使能信号为内部唤醒信号, 否则门控时钟使能信号为内部唤 醒信号的相反值。
优选地, 同歩单元具体用于: 当在***时钟的上升沿时, 采样内部唤醒信 号并更新内部唤醒信号同歩信号, 当没有***时钟时, 内部唤醒信号同歩信号 保持不变。 根据本发明的另一个方面, 提供的一种 S0C芯片的 MCU唤醒方法包括: 检测到有效的外部唤醒信号后产生内部唤醒信号;
根据内部唤醒信号产生门控时钟使能信号和中断请求信号;
根据门控时钟使能信号、 门控时钟寄控制存器状态和睡眠信号状态输出系 统时钟信号;
将门控时钟控制寄存器配置为有效状态, 并产生中断退出信号输出到给 优选地, 检测到有效的外部唤醒信号后产生内部唤醒信号进一歩包括: 接收外部唤醒信号;
判断外部唤醒信号是否满足唤醒要求, 如果不满足唤醒要求, 则舍弃本次 唤醒信号, 结束流程; 如果满足唤醒要求, 产生内部唤醒信号。
本发明提供的 S0C芯片的 MCU唤醒装置和方法, 采用单一信号唤醒 MCU, 但 是外部单一信号不直接用来唤醒 MCU ,而经过外部唤醒信号检测模块滤除假的唤 醒信号, 然后利用检测到的真实唤醒信号来产生***中断, 最后在中断处理程 序模块里面彻底唤醒 MCU, 避免了外部干扰信号产生的错误唤醒动作。不管用于 芯片内部唤醒还是外部唤醒, 都简单可靠, 既保证了唤醒的安全性, 又避免额
附图说明
图 1是本发明实施例提供的一种 S0C芯片的 MCU唤醒装置的结构示意图。 图 2是本发明优选实施例提供的一种外部唤醒信号检测模块的结构示意图。 图 3是本发明优选实施例提供的一种中断请求产生模块的结构示意图。 图 4是本发明实施例提供的一种 S0C芯片的 MCU唤醒方法的流程图。
图 5是本发明优选实施例提供的一种 S0C芯片的 MCU唤醒方法的流程图。 具体实施方式
为了使本发明所要解决的技术问题、 技术方案及有益效果更加清楚、 明白, 以下结合附图和实施例, 对本发明进行进一歩详细说明。 应当理解, 此处所描 述的具体实施例仅仅用以解释本发明, 并不用于限定本发明。
实施例一
如图 1是本发明实施例提供的一种 S0C芯片的 MCU唤醒装置的结构示意图, 该装置包括: 外部唤醒信号检测模块 10、 中断请求产生模块 20、 门控时钟 30 以及中断服务程序模块 40, 其中:
外部唤醒信号检测模块 10, 用于检测到有效的外部唤醒信号后产生内部唤 醒信号, 输出到中断请求产生模块 20 ;
中断请求产生模块 20, 用于接收到内部唤醒信号后, 产生门控时钟使能信 号输出到门控时钟 30, 产生中断请求信号输出到中断服务程序模块 40;
门控时钟 30, 用于根据门控时钟使能信号、 睡眠信号状态和门控时钟寄存 器配置信号状态输出***时钟到中断请求产生模块 20和 MCU;
中断服务程序模块 40, 用于接收到中断请求信号后, 将门控时钟 40的控制 寄存器配置为有效状态, 并产生中断退出信号输出到给 MCU。
作为本实施例的一种优选方案, 为了使得 MCU下次可以正常的进入睡眠模 式, 中断服务程序模块 40, 还用于产生内部唤醒信号清除信号输出到外部唤醒 信号检测模块 10; 相应地, 外部唤醒信号检测模块 10还用于接收到中断服务程
序模块 40输出的内部唤醒信号清除信号后, 清除内部唤醒信号。
作为本实施例的另一种优选方案, 为了避免额外的唤醒, 有效的外部唤醒 信号是指外部唤醒信号为持续预定的时间段的高电平或者低电平信号。
具体来说, 外部唤醒信号检测模块 10的输入信号为外部唤醒信号和检测时 钟, 外部唤醒信号检测模块 10在检测时钟的激励下, 根据一定的标准检测到有 效的外部唤醒信号后, 产生内部唤醒信号, 并将内部唤醒信号输出到中断请求 产生模块 20。 中断请求产生模块 20的输入信号为内部唤醒信号和***时钟, 中 断请求产生模块 20在收到内部唤醒信号后, 分别产生门控时钟使能信号和中断 请求信号, 并将门控时钟使能信号输出到门控时钟 30, 将中断请求信号输出到 中断服务程序模块 40; 其中, 门控时钟使能信号和中断请求信号会随着内部唤 醒信号的无效而无效。 门控时钟 30的输入信号是门控时钟使能信号、 门控时钟 控制寄存器配置信号和睡眠信号, 当检测到门控时钟使能信号有效且门控时钟 控制寄存器配置信号有效且睡眠信号无效时, 输出***时钟, 当检测到门控时 钟使能信号无效且门控时钟控制寄存器配置信号无效且睡眠信号有效时, 停止 输出***时钟。 中断服务程序模块 40的输入信号为中断请求信号, 输出信号为 内部唤醒信号清除信号、 门控时钟控制寄存器配置信号和中断退出信号, 中断 服务程序模块 40根据收到的中断请求信号使 MCU进入中断服务程序, 在中断服 务程序里面把门控时钟控制寄存器配置为有效状态, 然后产生内部唤醒信号清 除信号, 最后产生中断退出信号。 MCU的输入信号为***时钟和中断退出信号, MCU是中断服务程序模块 40的载体, 中断服务程序模块 40中的功能需要借助 MCU来完成, 并且 MCU进入睡眠模式的睡眠信号也是由 MCU发出的。 实施例二
如图 2 是本发明优选实施例提供的一种外部唤醒信号检测模块的结构示意 图, 该模块包括计数器 101、 比较器 102和复位器 103, 其中:
计数器 101, 用于在检测时钟的激励下对外部唤醒信号进行采样和计数, 将
计数值输出到比较器 102;
比较器 102,用于接收计数器 101的计数值,并比较计数值和预定的门限值, 当计数器的计数值大于或等于预定的门限值时, 输出内部唤醒信号, 否则不输 出内部唤醒信号;
复位器 103, 用于接收外部唤醒信号、 内部唤醒信号和内部唤醒信号清除信 号, 当内部唤醒信号清除信号有效、 或者外部唤醒信号和内部唤醒信号都无效 时, 输出有效的计数器复位信号到计数器 101, 否则输出无效的计数器复位信号 到计数器 101。
具体来说计数器 101 的输入信号为外部唤醒信号、 检测时钟和计数器复位 信号, 输出信号为计数器计数值, 计数器 101 在检测时钟的激励下对外部唤醒 信号进行采样和计数, 然后把计数值输出到比较器 102。 其中, 当计数器复位信 号有效时, 计数器 101 的计数值为零, 否则每当检测时钟在上升沿检测到外部 唤醒信号有效时, 计数器 101 的数值递增 1。 比较器 102 的输入信号为计数器 10的计数值, 输出信号为内部唤醒信号, 比较器 102功能是比较计数器 101的 计数值和门限值, 当计数器 101 的计数值大于等于门限值时, 输出内部唤醒信 号, 否则不输出内部唤醒信号, 其中门限值是一个相对固定的值, 代表外部唤 醒信号持续多少个检测时钟周期的高电平或者低电平, 可以根据应用场景不同 而设置为不同的值。 复位器 103 的输入信号为外部唤醒信号、 内部唤醒信号清 除信号和内部唤醒信号, 输出信号为计数器复位信号, 当内部唤醒信号清除信 号有效或者外部唤醒信号和内部唤醒信号都无效的情况下, 输出有效的计数器 复位信号, 否则输出无效的计数器复位信号。
在本实施例中, 外部唤醒信号检测模块的工作原理为利用计数器 101 对外 部唤醒信号进行计数, 当计数器 101 的计数值大于等于门限值时, 代表外部唤 醒信号满足外部唤醒条件, 那么就会产生内部唤醒信号, 如果在计数的过程中, 一旦外部唤醒信号跳变到无效状态, 那么复位器 103 就会产生计数器复位信号 用来清除计数器计数值, 当再次检査到外部唤醒信号有效时, 重新开始计数。
显然, 外部唤醒信号检测模块还可以通过其他方式来实现, 只要能判断出外部 唤醒信号为持续预定的时间段的高电平或者低电平信号即可。 实施例三
如图 3 是本发明优选实施例提供的一种中断请求产生模块的结构示意图, 该模块包括使能信号产生单元 201、同歩单元 202和跳变沿检测单元 203,其中: 使能信号产生单元 201, 用于接收内部唤醒信号, 根据内部唤醒信号的有效 电平, 产生门控时钟使能信号;
同歩单元 202, 用于接收***时钟和内部唤醒信号, 将内部唤醒信号同歩到 ***时钟域, 输出内部唤醒信号同歩信号到跳变沿检测单元 203 ;
跳变沿检测单元 203, 用于检测到内部唤醒信号同歩信号的跳变沿后, 输出 中断请求信号。
具体来说, 使能信号产生单元 201 的输入信号为内部唤醒信号, 输出信号 为门控时钟使能信号, 使能信号产生单元 201 根据内部唤醒信号的有效电平, 产生门控时钟使能信号。 其中, 如果内部唤醒信号的有效电平为高电平, 那么 门控时钟使能信号就等于内部唤醒信号, 否则门控时钟使能信号等于内部唤醒 信号的相反值。 同歩单元 202 的输入信号为***时钟和内部唤醒信号, 输出为 内部唤醒信号同歩信号, 同歩单元 202用于将内部唤醒信号同歩到***时钟域, 即只有在***时钟的上升沿才会采样内部唤醒信号, 并更新内部唤醒信号同歩 信号, 当没有***时钟的时候, 内部唤醒信号同歩信号保持不变。 跳变沿检测 单元 203 的输入信号为内部唤醒信号同歩信号, 输出信号为中断请求信号, 跳 变沿检测单元 203用于检测内部唤醒信号同歩信号的跳变沿, 即由高电平到低 电平跳变, 或者由低电平到高电平跳变, 当检测到跳变沿后, 跳变沿检测单元 203会输出一个***时钟宽度的脉冲信号, 即中断请求信号。
实施例四
如图 4是本发明实施例提供的一种 S0C芯片的 MCU唤醒方法的流程图, 该 方法包括以下歩骤:
S40 U 检测到有效的外部唤醒信号后产生内部唤醒信号;
5402、 根据内部唤醒信号产生门控时钟使能信号和中断请求信号;
5403、 根据门控时钟使能信号、 门控时钟寄控制存器状态和睡眠状态输出 ***时钟信号;
5404、 将门控时钟控制寄存器配置为有效状态, 并产生中断退出信号输出 到给 MCU。
需要说明地是, 本实施例中, MCU睡眠和唤醒都是通过门控时钟来实现的, 门控时钟关闭时 MCU进入睡眠状态, 打开门控时钟时 MCU开始工作。 当 MCU需 要进入睡眠状态时, MCU只需要发出睡眠指令, 就可以马上进入睡眠状态。 为了 保证唤醒的安全性, 避免外部唤醒信号的干扰, 唤醒过程相对比较复杂, 同时 满足上述条件时 MCU才会开始正常工作。 实施例五
如图 5是本发明优选实施例提供的一种 S0C芯片的 MCU唤醒方法的流程图, S50 U 接收外部唤醒信号;
5502、 判断外部唤醒信号是否满足唤醒要求, 如果不满足唤醒要求, 则执 行歩骤 S503 ; 如果满足唤醒要求, 则执行歩骤 S504;
其中, 满足唤醒要求的外部唤醒信号应该为持续一段时间的高电平或者低 电平信号。
5503、 舍弃本次唤醒信号, 结束流程;
5504、 产生内部唤醒信号;
5505、 根据内部唤醒信号产生门控时钟使能信号和中断请求信号 ·,
5506、 根据门控时钟使能信号、 门控时钟寄控制存器状态和睡眠信号状态
输出***时钟信号;
5507、 将门控时钟控制寄存器配置为有效状态, 产生内部唤醒信号清除信 号, 并产生中断退出信号输出到给 MCU。
5508、 清除内部唤醒信号。
具体来说, 外部唤醒信号为 MCU外部的单一唤醒信号, 外部唤醒信号检测 模块对接收到的外部唤醒信号进行分析, 如果本次外部唤醒信号不满足要求, 则舍弃本次唤醒请求, MCU不会被唤醒, 如果本次外部唤醒信号满足要求, 则外 部唤醒信号检测模块根据外部唤醒信号产生某个电平的内部唤醒信号, 并维持 这个电平, 然后这个内部唤醒信号会作为门控时钟的使能信号来打开门控时钟, 同时作为 MCU的中断请求输入信号, 当 MCU工作时钟打开以后就可以检测到中 断请求, 然后 MCU进入中断服务程序, 在中断服务程序里面软件配置门控时钟 控制寄存器为有效状态, 然后产生维持某个电平一段时间的内部唤醒信号清除 信号, 用来清除内部唤醒信号, 由于门控时钟控制寄存器已经处于有效状态, 所以门控时钟会保持为打开状态直到下次睡眠开始。
以上参照附图说明了本发明的优选实施例, 并非因此局限本发明的权利范 围。 本领域技术人员不脱离本发明的范围和实质, 可以有多种变型方案实现本 发明, 比如作为一个实施例的特征可用于另一实施例而得到又一实施例。 凡在 运用本发明的技术构思之内所作的任何修改、 等同替换和改进, 均应在本发明 的权利范围之内。
工业实用性
本发明实施例提供的 S0C芯片的 MCU唤醒装置和方法, 采用单一信号唤醒 MCU, 但是外部单一信号不直接用来唤醒 MCU , 而经过外部唤醒信号检测模块滤 除假的唤醒信号, 然后利用检测到的真实唤醒信号来产生***中断, 最后在中 断处理程序模块里面彻底唤醒 MCU, 避免了外部干扰信号产生的错误唤醒动作。 不管用于芯片内部唤醒还是外部唤醒, 都简单可靠, 既保证了唤醒的安全性, 又避免额外的唤醒, 更加有效地降低***功耗。
Claims
1、 一种 S0C芯片的 MCU唤醒装置, 该装置包括: 外部唤醒信号检测模块、 中断请求产生模块、 中断服务程序模块以及门控时钟, 其中:
所述外部唤醒信号检测模块, 用于检测到有效的外部唤醒信号后产生内部 唤醒信号, 输出到所述中断请求产生模块;
所述中断请求产生模块, 用于接收到内部唤醒信号后, 产生门控时钟使能 信号输出到所述门控时钟, 产生中断请求信号输出到所述中断服务程序模块; 所述门控时钟, 根据门控时钟使能信号、 睡眠信号状态和寄存器配置信号 状态输出***时钟到中断请求产生模块和所述 MCU;
所述中断服务程序模块, 用于接收到中断请求信号后, 将门控时钟控制寄 存器配置为有效状态, 并产生中断退出信号输出到给 MCU。
2、 根据权利要求 1所述的 S0C芯片的 MCU唤醒装置, 其中, 所述中断服务 程序模块, 还用于产生内部唤醒信号清除信号输出到外部唤醒信号检测模块; 相应地, 所述外部唤醒信号检测模块还用于接收到所述中断服务程序模块输出 的内部唤醒信号清除信号后, 清除内部唤醒信号。
3、 根据权利要求 1或 2所述的 S0C芯片的 MCU唤醒装置, 其中, 所述有效 的外部唤醒信号是指持续预定的时间段的高电平或者低电平信号。
4、 根据权利要求 3所述的 S0C芯片的 MCU唤醒装置, 其中, 所述外部唤醒 信号检测模块包括计数器、 比较器和复位器, 其中:
所述计数器, 用于在检测时钟的激励下对外部唤醒信号进行采样和计数, 将计数值输出到比较器;
所述比较器, 用于接收所述计数器的计数值, 并比较所述计数值和预定的 门限值, 当计数器的计数值大于或等于预定的门限值时, 输出内部唤醒信号, 否则不输出内部唤醒信号;
所述复位器, 用于接收外部唤醒信号、 内部唤醒信号和内部唤醒信号清除
信号, 当内部唤醒信号清除信号有效、 或者外部唤醒信号和内部唤醒信号都无 效时, 输出有效的计数器复位信号到所述计数器, 否则输出无效的计数器复位 信号到所述计数器。
5、 根据权利要求 4所述的 S0C芯片的 MCU唤醒装置, 其中, 所述计数器具 体用于: 当计数器复位信号有效时, 计数值为零; 当计数器复位信号无效时, 每当检测时钟在上升沿检测到外部唤醒信号有效时, 计数值递增 1。
6、 根据权利要求 1或 2所述的 S0C芯片的 MCU唤醒装置, 其中, 所述中断 请求产生模块包括: 使能信号产生单元、 同歩单元和跳变沿检测单元, 其中: 所述使能信号产生单元, 用于接收内部唤醒信号, 根据内部唤醒信号的有 效电平, 产生门控时钟使能信号;
所述同歩单元, 用于接收***时钟和内部唤醒信号, 将内部唤醒信号同歩 到***时钟域, 输出内部唤醒信号同歩信号到跳变沿检测单元;
所述跳变沿检测单元, 用于检测到内部唤醒信号同歩信号的跳变沿后, 输 出中断请求信号。
7、 根据权利要求 6所述的 S0C芯片的 MCU唤醒装置, 其中, 所述使能信号 产生单元具体用于: 如果内部唤醒信号的有效电平为高电平, 则门控时钟使能 信号为内部唤醒信号, 否则门控时钟使能信号为内部唤醒信号的相反值。
8、 根据权利要求 6所述的 S0C芯片的 MCU唤醒装置, 其中, 所述同歩单元 具体用于: 当在***时钟的上升沿时, 采样内部唤醒信号并更新内部唤醒信号 同歩信号, 当没有***时钟时, 内部唤醒信号同歩信号保持不变。
9、 一种 S0C芯片的 MCU唤醒方法, 该方法包括:
检测到有效的外部唤醒信号后产生内部唤醒信号;
根据内部唤醒信号产生门控时钟使能信号和中断请求信号;
根据门控时钟使能信号、 门控时钟寄控制存器状态和睡眠信号状态输出系 统时钟信号;
将门控时钟控制寄存器配置为有效状态, 并产生中断退出信号输出到给
10、 根据权利要求 9所述的 SOC芯片的 MCU唤醒方法, 其中, 所述检测到 有效的外部唤醒信号后产生内部唤醒信号进一歩包括:
接收外部唤醒信号;
判断所述外部唤醒信号是否满足唤醒要求, 如果不满足唤醒要求, 则舍弃 本次唤醒信号, 结束流程; 如果满足唤醒要求, 产生内部唤醒信号。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105322977A (zh) * | 2015-11-10 | 2016-02-10 | 上海十贝电子科技有限公司 | 一种有源rfid标签低功耗数据接收装置及其方法 |
CN113454723A (zh) * | 2021-05-25 | 2021-09-28 | 长江存储科技有限责任公司 | 用于半导体设备中的功率节省的方法和装置 |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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CN114710176B (zh) * | 2022-02-23 | 2024-04-16 | 苏州市江海通讯发展实业有限公司 | 一种基于信号检测的救生电台节能延时方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1877494A (zh) * | 2006-07-19 | 2006-12-13 | 北京天碁科技有限公司 | 片上***芯片及其功耗控制方法 |
CN101387896A (zh) * | 2008-10-22 | 2009-03-18 | 炬力集成电路设计有限公司 | Soc中实现片上主***唤醒和睡眠功能的方法和装置 |
CN102541247A (zh) * | 2012-02-02 | 2012-07-04 | 钜泉光电科技(上海)股份有限公司 | 片上***及其休眠和唤醒方法 |
CN103412634A (zh) * | 2013-07-30 | 2013-11-27 | 深圳市汇顶科技股份有限公司 | 一种soc芯片的mcu唤醒装置和方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100410846C (zh) * | 2005-09-22 | 2008-08-13 | 联想(北京)有限公司 | 笔记本电脑实时时钟唤醒的实现方法 |
JP4644747B1 (ja) * | 2009-11-02 | 2011-03-02 | パナソニック株式会社 | 情報処理装置、制御方法および制御プログラム |
-
2013
- 2013-07-30 CN CN201310325903.2A patent/CN103412634B/zh active Active
-
2014
- 2014-06-10 WO PCT/CN2014/079559 patent/WO2015014162A1/zh active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1877494A (zh) * | 2006-07-19 | 2006-12-13 | 北京天碁科技有限公司 | 片上***芯片及其功耗控制方法 |
CN101387896A (zh) * | 2008-10-22 | 2009-03-18 | 炬力集成电路设计有限公司 | Soc中实现片上主***唤醒和睡眠功能的方法和装置 |
CN102541247A (zh) * | 2012-02-02 | 2012-07-04 | 钜泉光电科技(上海)股份有限公司 | 片上***及其休眠和唤醒方法 |
CN103412634A (zh) * | 2013-07-30 | 2013-11-27 | 深圳市汇顶科技股份有限公司 | 一种soc芯片的mcu唤醒装置和方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105322977A (zh) * | 2015-11-10 | 2016-02-10 | 上海十贝电子科技有限公司 | 一种有源rfid标签低功耗数据接收装置及其方法 |
CN113454723A (zh) * | 2021-05-25 | 2021-09-28 | 长江存储科技有限责任公司 | 用于半导体设备中的功率节省的方法和装置 |
US11967393B2 (en) | 2021-05-25 | 2024-04-23 | Yangtze Memory Technologies Co., Ltd. | Method and apparatus for power saving in semiconductor devices |
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