WO2015014106A1 - 一种nand闪存存储设备及其带外数据读取方法 - Google Patents
一种nand闪存存储设备及其带外数据读取方法 Download PDFInfo
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- WO2015014106A1 WO2015014106A1 PCT/CN2014/070692 CN2014070692W WO2015014106A1 WO 2015014106 A1 WO2015014106 A1 WO 2015014106A1 CN 2014070692 W CN2014070692 W CN 2014070692W WO 2015014106 A1 WO2015014106 A1 WO 2015014106A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0409—Online test
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0411—Online error correction
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- the invention belongs to the technical field of NAND flash memory devices, and in particular relates to a NAND flash memory storage device and an outband data reading method thereof.
- NAND flash memory has the advantages of non-volatility, high reliability, low power consumption, small size, etc., and with the advancement of technology, the storage density is getting higher and higher, and the cost per unit of storage capacity is also declining. Based on the above advantages, NAND is made. Flash storage devices are becoming more widely used.
- NAND flash memory is widely used in memory cards, USB flash drives, mobile audio and video playback devices, smart phones, and the like.
- a NAND flash can be structurally divided into 1024 or 2048 or other numbers of blocks, each of which can be divided into 64 or 128 or other numbers of pages, each of which can be 2K or 4K or other number of bytes.
- NAND flash The basic operations of NAND flash can be divided into block erase, page write, and page read.
- a page write operation When a page write operation is performed, the block in which the page is located is first erased.
- NAND flash has a certain erase/write life, which means that after a certain number of erases, the block will be damaged. The higher the erased frequency, the faster the damage will be.
- Out-of-band data is typically used to indicate the type of data stored in the NAND flash page, the number of erases of the block in which the NAND flash page is located, and the logical block address corresponding to the NAND flash page (Logical) Block Address, LBA) and so on.
- the page size mentioned above is 2K, 4K bytes, which actually only indicates the size of the data area.
- the page also includes certain error detection/error correction codes and out-of-band data areas.
- the actual size of a 2K byte page may be 2048+128 bytes, and 128 bytes are used to store error detection/error correction coding and out-of-band data.
- the data size for error detection/error correction can be 512 or 1K bytes, or other sizes are also possible.
- the storage form in which error detection/error correction coding and out-of-band data are generally employed is as shown in FIGS. 1A and 1B.
- out-of-band data and the last data are used together for error detection/error correction, wherein 101 denotes a data unit, 102 denotes an error detection/error correction unit, and 103 denotes an out-of-band data unit.
- out-of-band data can also be spread across multiple data areas.
- NAND flash storage devices there are some specific operations that do not require reading the data area in the NAND flash memory, and only the out-of-band data is sufficient. For example, when the NAND flash storage device is powered on, it is necessary to rebuild the mapping table of the logical block address to the physical block address.
- the read operation still needs to read the entire data page, and at least the error detection/error correction unit where the out-of-band data is located is read out.
- the NAND flash controller is required to support partial page read operations).
- the reading of the NAND flash memory is a serial operation, and the time required for reading the entire page of data is considerable. Taking a 4K-byte page and taking a faster synchronous 66 MHz interface as an example, it takes about 25 microseconds to move data from the NAND flash memory location to the NAND flash memory cache (different NAND flash memories are different). Reading data from the NAND flash memory takes about 31 microseconds. As shown in FIG.
- the time required to read one full page of data from each NAND flash memory 201 is 25+31 ⁇ 4 microseconds, but for such a long time. Only the out-of-band data is valid in the data read out during the time.
- the technical problem to be solved by the present invention is to provide a NAND flash memory device and an out-of-band data reading method thereof, aiming at shortening the transmission time of the NAND flash memory device and the time for reconstructing the table.
- the present invention is implemented as a NAND flash memory device including a plurality of NAND flash channels including a plurality of NAND flash memories, the NAND flash memory having at least one data storage unit and one out-of-band a data storage unit, each of the at least one data storage unit corresponding to an error detection/error correction unit for encoding data and out-of-band data, the out-of-band data storage unit corresponding to a school
- the inspection unit is used to verify the out-of-band data when the out-of-band data is read.
- the check unit is a cyclic redundancy check unit, and the cyclic redundancy check unit is configured to encode out-of-band data.
- the data length in the cyclic redundancy check unit is 1, 2 or 4 bytes.
- the invention also provides an out-of-band data reading method for a NAND flash memory storage device, comprising the following steps:
- Step 1 The NAND flash storage device sets a plurality of NAND flash channels, and a plurality of NAND flash memories are disposed in each of the NAND flash channels;
- Step 2 The NAND flash memory is provided with a plurality of data units, a plurality of error detection/error correction units, a check unit and an out-of-band data storage unit, and the error detection/error correction unit is configured to encode data and out-of-band data. ;
- Step 3 The data in the data unit and the out-of-band data in the out-of-band data unit are detected in the error detection/error correction unit;
- Step 4 The out-of-band data in the out-of-band data unit is separately tested in the check unit.
- the check unit is a cyclic redundancy check unit, and the cyclic redundancy check unit is configured to encode out-of-band data.
- step 4 includes:
- Step 41 Read out-of-band data and cyclic redundancy check code
- Step 42 Perform verification verification according to the out-of-band data and the cyclic redundancy check code.
- Step 43 When there is an error in the verification result, the entire data page is read, and error detection/error correction is performed; when the verification result has no error, the next out-of-band data is continuously read.
- the invention has the beneficial effects that not only the data and the out-of-band data can be read out at the same time, the inversion of the bits occurring during the reading and writing process can be eliminated, and the transmission time can be effectively shortened.
- the read efficiency of the NAND flash memory device is greatly improved.
- 1A is a storage form diagram of error detection/error correction coding and out-of-band data provided by the prior art
- 1B is another storage form diagram of error detection/error correction coding and out-of-band data provided by the prior art
- FIG. 2 is a schematic diagram of four NAND flash memories in a NAND flash channel provided by the prior art
- 3A is a schematic diagram of a storage format of a NAND flash memory storage device according to an embodiment of the present invention.
- FIG. 3B is a schematic diagram of a storage format of a NAND flash memory storage device according to another embodiment of the present invention.
- FIG. 5 is a schematic diagram of a NAND flash memory channel having four NAND flash memories according to an embodiment of the present invention
- FIG. 6 is a structural diagram of a NAND flash controller provided by an embodiment of the present invention.
- the invention adopts cyclic redundancy check and traditional error detection/error correction algorithm: data and out-of-band data adopt error detection/error correction algorithm, and out-of-band data adopts cyclic redundancy check separately (Cyclic Redundancy Check, CRC) algorithm to detect errors.
- CRC Cyclic Redundancy Check
- a NAND flash memory device includes a plurality of NAND flash channels, and the NAND flash channel includes a plurality of NAND flash memories 201, and the NAND flash memory 201 has at least one data storage.
- the unit 101 and an out-of-band data storage unit 103 each corresponding to an error detection/error correction unit 102 for encoding data and out-of-band data,
- the out-of-band data storage unit 103 corresponds to a check unit for verifying out-of-band data when the out-of-band data is read.
- the check unit is a cyclic redundancy check unit 301, and the cyclic redundancy check unit 301 is configured to encode out-of-band data.
- the data storage unit 101 and the error detection/error correction unit 102 are arranged adjacent to each other, the out-of-band data storage unit 103 is located behind the last data storage unit 101, and the cyclic redundancy check unit 301 is located at the The end of the NAND flash storage device.
- the error detection/error correction unit 102 can facilitate the error detection and correction of the data in the data storage unit 101.
- the plurality of data storage units 101 are adjacently arranged, the out-of-band data storage unit 103 is located behind the data storage unit 101, and the error detection/error correction unit 102 is sequentially arranged next to the out-of-band data storage unit 103, which is located at the end of the NAND flash storage device.
- the cyclic redundancy check unit 301 can separately check the out-of-band data storage unit 103.
- the out-of-band data length is several to several tens of bytes.
- algorithms such as CRC-8, CRC-16, and CRC-32 can be used.
- the data length of CRC encoding is 1, 2, and 4 byte.
- the length of the out-of-band data and the CRC code is much smaller than the true data and error detection/error correction coding, so the transmission time is greatly shortened.
- FIG. 5 there are four of the NAND flash memory devices 201 in one NAND flash channel. Similarly, there may be five, six, seven or more of the NAND flash memory devices in a NAND flash channel. The effect is even more pronounced when the number of NAND flash memories in a channel is larger.
- the NAND flash controller can quickly scan all NAND flashes to quickly reconstruct a mapping table of logical block addresses to physical block addresses.
- the structure of the NAND flash controller is shown in Figure 6.
- the controller has both an error detection/error correction (ECC) unit 102 and a cyclic redundancy check unit 301 (CRC-16).
- ECC error detection/error correction
- CRC-16 cyclic redundancy check unit 301
- NAND flash memory there are four NAND flash channels, each with eight NAND flash memories 201, each with a flash controller.
- NAND flash memory is a single-stage memory unit (Single-level Cell, SLC)
- SLC Single-level Cell
- the time required to reconstruct the table is only 13% of the conventional method.
- the NAND flash memory is a multi-level cell (Multi-level cell, In MLC, the time required to reconstruct the table is 25% of the traditional method.
- the flash controller mentioned above is implemented in a 90nm process.
- the NAND flash page size is 4K bytes, produced in a 25nm process, the CRC-16 uses CCITT, and the polynomial is x16+x12+x5+1.
- a method for reading out-of-band data of a NAND flash memory device includes the following steps:
- Step 1 NAND flash storage device sets a number of NAND flash memory channels, each NAND flash memory channel is provided with a plurality of NAND flash memory 201;
- Step 2 The NAND flash memory 201 is provided with a plurality of data units 101, a plurality of error detection/error correction units 102, a check unit and an out-of-band data storage unit 103, and the error detection/error correction unit 102 is used for data and Out-of-band data for encoding;
- Step 3 The data in the data unit 101 and the out-of-band data in the out-of-band data unit 103 are error-detected in the error detection/error correction unit 102;
- Step 4 The out-of-band data in the out-of-band data unit 103 is separately detected in the check unit.
- the NANDA flash memory storage device of the present invention can adopt not only a conventional error detection/error correction algorithm but also a cyclic redundancy check algorithm. After using the cyclic redundancy check mechanism, the method of reading out-of-band data is:
- Step 41 Read out-of-band data and cyclic redundancy check code
- Step 42 Perform verification verification according to the out-of-band data and the cyclic redundancy check code.
- Step 43 When there is an error in the verification result, the entire data page is read, and error detection/error correction is performed; when the verification result has no error, the next out-of-band data is continuously read.
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Abstract
本发明适用于NAND闪存存储设备技术领域,提供了一种NAND闪存存储设备,该NAND闪存存储设备包括若干NAND闪存通道,所述NAND闪存通道包括若干个NAND闪存,所述NAND闪存中具有至少一个数据存储单元和一带外数据存储单元,所述至少一个数据存储单元各自对应有错误检测/错误纠正单元,所述错误检测/错误纠正单元用于对数据和带外数据进行编码,所述带外数据存储单元对应有一校验单元,用于在带外数据读出时对带外数据进行校验。本发明所述的NAND闪存存储设备采用循环冗余校验快速对NAND闪存进行扫描,构建逻辑块地址到物理块地址映射表的方法可以缩短传输时间,提高存储效率。
Description
本发明属于NAND闪存存储设备技术领域,尤其涉及一种NAND闪存存储设备及其带外数据读取方法。
NAND闪存具备非挥发性,可靠性高,功耗低,尺寸小等优点,并且随着技术的进步,存储密度越来越高,单位存储容量的成本也在不断下降,基于以上的优点使得NAND闪存的存储设备得到越来越广泛的应用。现在NAND闪存大量应用于存储卡、USB闪存驱动器、移动影音播放设备、智能手机等。
一个NAND闪存在结构上可以分为1024或者2048或者其它数目的块,每个块可以分为64或者128或者其它数目的页,每个页的大小可以是2K或者4K或者其它数目的字节。
NAND闪存的基本操作可以分为块擦除、页写入和页读取。在进行页写入操作的时候,该页所在块要先进行擦除操作。NAND闪存具备一定的擦除/写入寿命,也就是说在擦除一定次数之后,这个块就会损坏,所擦除的频率越高,损坏就会越快。
由于NAND闪存物理结构的特点,在读写过程中会出现某些比特的反转,就是读出的数据与实际写入的数据不同。为了保证数据的完整性需要对数据做错误检测/错误纠正(Error
Correcting
Code,ECC)处理。在数据写入的时候在数据中添加一段按照某种算法算出的错误检测/错误纠正编码,在数据读出的时候再按照特定的算法对数据和错误检测/错误纠正编码进行检查和纠错。同时在NAND闪存中还需要一个额外数据,我们称为带外数据(Out
of
Band,OOB)。带外数据通常用来表明该NAND闪存页存储数据的类型、该NAND闪存页所在的块的擦除次数、该NAND闪存页所对应的逻辑块地址(Logical
Block
Address,LBA)等。前面所说的页大小为2K、4K字节实际上只是表明数据区的大小,页当中还包括一定的错误检测/错误纠正编码和带外数据区域。比如2K字节的页实际大小可能为2048+128字节,128字节用来存储错误检测/错误纠正编码和带外数据。进行错误检测/错误纠正的数据大小可以是512或者1K字节,或者其它大小也可以。一般采用错误检测/错误纠正编码和带外数据的存储形式如图1A、图1B所示。
在图1A当中带外数据和最后一个数据一起做错误检测/错误纠正,其中101表示数据单元、102表示错误检测/错误纠正单元、103表示带外数据单元。实际上也可以将带外数据分散到多个数据区。
在NAND闪存存储设备中,有一些特定的操作不需要读取NAND闪存中的数据区,只需要带外数据就够了。比如NAND闪存存储设备刚刚上电,需要重新构建逻辑块地址到物理块地址的映射表的时候。
根据前面的分析,当NAND闪存存储设备读取操作只需要带外数据的时候,读取操作仍然需要将整个数据页读出,至少也要将带外数据所在的错误检测/错误纠正单元读出(需要NAND闪存控制器支持部分页读取操作)。NAND闪存的读取是串行操作,整页数据的读出所需要的时间相当可观。以一个4K字节的页,采用较快的同步66兆赫兹接口为例,将数据从NAND闪存的存储单元搬到NAND闪存的缓存中需要约25微秒(不同NAND闪存各不相同),将数据从NAND闪存的缓存中读出需要约31微秒的时间。如图2所示,假定一个NAND闪存通道中有4个NAND闪存201,从每个NAND闪存201中读出一个整页数据所需要的时间为25+31×4微秒,但在这么久的时间内读出的数据中有效的只有带外数据。
因此,现有技术存在缺陷,需要改进。
本发明所要解决的技术问题在于提供一种NAND闪存存储设备及其带外数据读取方法,旨在缩短NAND闪存存储设备的传输时间和重建表的时间。
本发明是这样实现的,一种NAND闪存存储设备,该NAND闪存存储设备包括若干NAND闪存通道,所述NAND闪存通道包括若干个NAND闪存,所述NAND闪存中具有至少一个数据存储单元和一带外数据存储单元,所述至少一个数据存储单元各自对应有错误检测/错误纠正单元,所述错误检测/错误纠正单元用于对数据和带外数据进行编码,所述带外数据存储单元对应有一校验单元,用于在带外数据读出时对带外数据进行校验。
进一步地,所述校验单元为循环冗余校验单元,所述循环冗余校验单元用于对带外数据进行编码。
进一步地,所述NAND闪存通道中有四个所述NAND闪存。
进一步地,所述循环冗余校验单元中的数据长度为1、2或4字节。
本发明还提供一种NAND闪存存储设备的带外数据读取方法,包括以下步骤:
步骤1:NAND闪存存储设备设置若干NAND闪存通道,所述每一NAND闪存通道内设置若干NAND闪存;
步骤2:所述NAND闪存中设置有若干数据单元、若干错误检测/错误纠正单元、校验单元和带外数据存储单元,所述错误检测/错误纠正单元用于对数据和带外数据进行编码;
步骤3:所述数据单元中的数据和所述带外数据单元中的带外数据在所述错误检测/错误纠正单元中进行检错;
步骤4:所述带外数据单元中的带外数据单独在所述校验单元中进行检错。
进一步地,所述校验单元为循环冗余校验单元,所述循环冗余校验单元用于对带外数据进行编码。
进一步地,所述步骤4中包括:
步骤41:读取带外数据和循环冗余校验编码;
步骤42:根据所述带外数据和循环冗余校验编码进行校验判断;
步骤43:当校验结果有错误时,进行整个数据页的读取,再进行错误检测/错误纠正;当校验结果无错误时,继续读取下一个带外数据。
本发明与现有技术相比,有益效果在于:不仅可以同时读出数据和带外数据,能杜绝读写过程中出现的比特的反转的情况,还能有效地缩短传输时间。使NAND闪存存储设备的读取效率得到很大地提高。
图1A是现有技术提供的采用错误检测/错误纠正编码和带外数据的存储形式图;
图1B是现有技术提供的采用错误检测/错误纠正编码和带外数据的另一种存储形式图;
图2是现有技术提供的一个NAND闪存通道中四个NAND闪存的示意图;
图3A是本发明实施例提供的NAND闪存存储设备存储格式的示意图;
图3B是本发明另一实施例提供的NAND闪存存储设备存储格式的示意图;
图4是本发明实施例提供的只读带外数据时的流程图;
图5是本发明实施例提供的一个NAND闪存通道具有四个NAND闪存的示意图;
图6是本发明实施例提供的NAND闪存控制器的结构图。
为了使本发明的目的、技术方案及优点更加清楚明白,以下结合附图及实施例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。
本发明采用循环冗余校验和传统的错误检测/错误纠正算法:数据和带外数据采用错误检测/错误纠正算法,同时带外数据单独采用循环冗余校验(Cyclic
Redundancy
Check,CRC)算法来检错。在只需要读取带外数据的时候,首先读取带外数据和CRC编码进行检错,如果有错误就进行整个数据页的读取,进行错误检测/错误纠正。如果没有错误就继续读取下一个带外数据。
如图3A、图3B所示,一种NAND闪存存储设备,该NAND闪存存储设备包括若干NAND闪存通道,所述NAND闪存通道包括若干个NAND闪存201,所述NAND闪存201中具有至少一个数据存储单元101和一带外数据存储单元103,所述至少一个数据存储单元101各自对应有错误检测/错误纠正单元102,所述错误检测/错误纠正单元102用于对数据和带外数据进行编码,所述带外数据存储单元103对应有一校验单元,用于在带外数据读出时对带外数据进行校验。
与上述实施例相结合,所述校验单元为循环冗余校验单元301,所述循环冗余校验单元301用于对带外数据进行编码。所述数据存储单元101和所述错误检测/错误纠正单元102相邻排列,所述带外数据存储单元103位于最后一个数据存储单元101的后面,所述循环冗余校验单元301位于所述NAND闪存存储设备的末端。采用该设置方案可以方便错误检测/错误纠正单元102对数据存储单元101中的数据进行检错及纠正。
与上述实施例相结合,另一实施例为,所述若干数据存储单元101相邻排列,所述带外数据存储单元103位于所述数据存储单元101的后面,所述错误检测/错误纠正单元102紧挨着所述带外数据存储单元103依次排列,所述循环冗余校验单元301位于所述NAND闪存存储设备的末端。所述循环冗余校验单元301可以单独对所述带外数据存储单元103进行校验。
一般带外数据长度在几个到几十个字节,对带外数据进行CRC编码可以采用CRC-8,CRC-16,CRC-32等算法,CRC编码的数据长度为1,2,4个字节。带外数据和CRC编码的长度相比真正的数据和错误检测/错误纠正编码来说小很多,所以传输时间大为缩短。如图5所示,一个NAND闪存通道中有四个所述NAND闪存存储设备201。同理,一个NAND闪存通道中也可以有5个、6个、7个或更多的所述NAND闪存存储设备。当一个通道中NAND闪存的数目更多时,效果更加明显。
当增加专门针对带外数据的循环冗余校验之后,NAND闪存控制器可以实现快速对所有NAND闪存的扫描,从而快速重建逻辑块地址到物理块地址的映射表。在具体的实现当中,NAND闪存控制器的结构如图6所示。
控制器中同时具备一个错误检测/错误纠正(ECC)单元102,另外有一个循环冗余校验单元301(CRC-16)。在写入操作时,错误检测/错误纠正单元102负责对数据和带外数据进行编码,循环冗余校验单元301对带外数据进行编码。在正常的数据读取操作中,只有错误检测/错误纠正单元102工作,CRC单元不工作。在带外数据只读操作中只有CRC单元工作。
在我们实现的NAND闪存存储设备中,有四个NAND闪存通道,每个通道有8个NAND闪存201,每个通道各自有一个闪存控制器。通过实际比对,NAND闪存为单阶存储单元(Single-level
cell, SLC)时采用本发明中的方法,重建表所需要的时间仅为传统方法的13%。当NAND闪存为多阶存储单元(Multi-level cell,
MLC)时,重建表所需要的时间为传统方法的25%。上面提到的闪存控制器采用90nm工艺实现,NAND闪存页大小为4K字节,25nm工艺制作,CRC-16采用CCITT,多项式为x16+x12+x5+1。
与上述各实施例相结合,结合图3A、图3B、图4所示,一种NAND闪存存储设备的带外数据读取方法,包括以下步骤:
步骤1:NAND闪存存储设备设置若干NAND闪存通道,所述每一NAND闪存通道内设置若干NAND闪存201;
步骤2:所述NAND闪存201中设置有若干数据单元101、若干错误检测/错误纠正单元102、校验单元和带外数据存储单元103,所述错误检测/错误纠正单元102用于对数据和带外数据进行编码;
步骤3:所述数据单元101中的数据和所述带外数据单元103中的带外数据在所述错误检测/错误纠正单元102中进行检错;
步骤4:所述带外数据单元103中的带外数据单独在所述校验单元中进行检错。
本发明所述的NANDA闪存存储设备不仅可以采用传统的错误检测/错误纠正算法,同时也可以采用循环冗余校验算法。采用循环冗余校验机制之后,只读带外数据的方法为:
步骤41:读取带外数据和循环冗余校验编码;
步骤42:根据所述带外数据和循环冗余校验编码进行校验判断;
步骤43:当校验结果有错误时,进行整个数据页的读取,再进行错误检测/错误纠正;当校验结果无错误时,继续读取下一个带外数据。
以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本发明的保护范围之内。
Claims (7)
- 一种NAND闪存存储设备,其特征在于,该NAND闪存存储设备包括若干NAND闪存通道,所述NAND闪存通道包括若干个NAND闪存,所述NAND闪存中具有至少一个数据存储单元和一带外数据存储单元,所述至少一个数据存储单元各自对应有错误检测/错误纠正单元,所述错误检测/错误纠正单元用于对数据和带外数据进行编码,所述带外数据存储单元对应有一校验单元,用于在带外数据读出时对带外数据进行校验。
- 根据权利要求1所述的NAND闪存存储设备,其特征在于,所述校验单元为循环冗余校验单元,所述循环冗余校验单元用于对带外数据进行编码。
- 根据权利要求1所述的NAND闪存存储设备,其特征在于,所述NAND闪存通道中有四个所述NAND闪存。
- 根据权利要求2所述的NAND闪存存储设备,其特征在于,所述循环冗余校验单元中的数据长度为1、2或4字节。
- 一种NAND闪存存储设备的带外数据读取方法,其特征在于,包括以下步骤:步骤1:NAND闪存存储设备设置若干NAND闪存通道,所述每一NAND闪存通道内设置若干NAND闪存;步骤2:所述NAND闪存中设置有若干数据单元、若干错误检测/错误纠正单元、校验单元和带外数据存储单元,所述错误检测/错误纠正单元用于对数据和带外数据进行编码;步骤3:所述数据单元中的数据和所述带外数据单元中的带外数据在所述错误检测/错误纠正单元中进行检错;步骤4:所述带外数据单元中的带外数据单独在所述校验单元中进行检错。
- 根据权利要求5所述的NAND闪存存储设备的带外数据读取方法,其特征在于,所述校验单元为循环冗余校验单元,所述循环冗余校验单元用于对带外数据进行编码。
- 根据权利要求6所述的NAND闪存存储设备的带外数据读取方法,其特征在于,所述步骤4中包括:步骤41:读取带外数据和循环冗余校验编码;步骤42:根据所述带外数据和循环冗余校验编码进行校验判断;步骤43:当校验结果有错误时,进行整个数据页的读取,再进行错误检测/错误纠正;当校验结果无错误时,继续读取下一个带外数据。
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