WO2015010646A1 - Procédé, module, processeur et dispositif terminal d'accès aux données de mémoire hybride - Google Patents

Procédé, module, processeur et dispositif terminal d'accès aux données de mémoire hybride Download PDF

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Publication number
WO2015010646A1
WO2015010646A1 PCT/CN2014/082974 CN2014082974W WO2015010646A1 WO 2015010646 A1 WO2015010646 A1 WO 2015010646A1 CN 2014082974 W CN2014082974 W CN 2014082974W WO 2015010646 A1 WO2015010646 A1 WO 2015010646A1
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Prior art keywords
data
accessed
dram
error
processor
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PCT/CN2014/082974
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English (en)
Chinese (zh)
Inventor
陈荔城
陈明宇
崔泽汉
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华为技术有限公司
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Publication of WO2015010646A1 publication Critical patent/WO2015010646A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature

Definitions

  • the present invention relates to the field of computers, and in particular, to a data access method, a module, a processor, and a terminal device of a hybrid memory.
  • NVM Non-Volatile Memory, non- Volatile memory
  • PCM Phase Change Memory
  • MRAM Magnetic Random Access Memory
  • flash memory Flash
  • the memory access when using a mixed memory composed of DRAM and extended memory, the memory access still uses the DDRx memory synchronous access interface, wherein X refers to the generations of DDR protocols, such as DDR3, DDR4, and DDR (Double Data Rate). , double rate)
  • X refers to the generations of DDR protocols, such as DDR3, DDR4, and DDR (Double Data Rate). , double rate
  • the memory synchronous access interface requires the access command to have a fixed timing delay, so the non-uniform access latency due to the mixed memory cannot be directly handled, and the non-uniform access delay needs to be processed.
  • OS Operating System
  • software is required to maintain which pages are currently in use. (Page) is located in DRAM, which pages are only in extended memory, which is usually achieved by adding flag bits to the page table entry.
  • the OS When the OS receives the memory access request, that is, the data access request, first query the page table to obtain whether the data accessed in the data access request is in the DRAM, and if so, directly access the DRAM; if not, the page fault needs to be generated. Then, the page corresponding to the accessed data is migrated from the extended memory to the DRAM, and the flag bit in the corresponding page table entry is updated, and finally the memory access request is resent to the DRAM.
  • the page table that is, the data access request
  • the data access method of the above mixed memory needs to redesign the memory management part of the operating system of the existing processor, such as establishing and updating the flag bit in the page table item, generating a page fault interrupt, etc., and the code modification amount is compared. Large, the data access process is more complicated.
  • Embodiments of the present invention provide a data access method, a module, a processor, and a terminal device of a hybrid memory, which can simplify the data access process.
  • the first aspect provides a data access method for a hybrid memory, which is applied to a serial connection module, and includes:
  • the preset error data is sent to the memory controller, so that the memory controller triggers the processor to generate an error correction code ECC error interrupt according to the preset error data.
  • the access data is data accessed in the data access request;
  • the serial module migrates the to-be-accessed data located in the non-volatile memory NVM to the DRAM when the processor interrupts the ECC error.
  • the method before the sending the preset error data to the memory controller, the method further includes:
  • the address mapping table records data currently located in the DRAM in the storage module and data located in the NVM, and the storage module is a mixed memory composed of the DRAM and the NVM;
  • the migrating the to-be-accessed data located in the NVM to the DRAM includes:
  • the to-be-accessed data located in the NVM is migrated to the DRAM according to a preset migration granularity.
  • the data access request includes a physical address of the to-be-accessed data
  • the generating a data migration request according to the data access request includes:
  • the data migration request is generated according to the data access request, where the data migration request includes a physical address of the to-be-accessed data, and the data migration request further includes the preset migration granularity.
  • the preset migration granularity is the same as the granularity of the DRAM line buffer.
  • the address mapping table further records a cache flag, where the cache flag is used to identify whether the data is located in the cache.
  • the method further includes: querying a cache flag in the address mapping, and determining whether the to-be-accessed data is located in a cache;
  • the migration of the data to be accessed located in the NVM is stopped from being migrated into the DRAM.
  • the preset error data is data that has at least two errors.
  • the second aspect provides a data access method for a hybrid memory, which is applied to a processor, including:
  • the method before the generating an error correction code ECC error interrupt according to the preset error data, the method further includes:
  • the ECC check is performed on the preset error data to determine whether the error mode of the preset error data is an ECC error interrupt mode.
  • the method Also includes:
  • the preset error data is data that has at least two errors.
  • a serial connection module including:
  • a sending unit configured to send preset error data to the memory controller when the data to be accessed is not in the dynamic random access memory (DRAM), so that the memory controller triggers the processor to generate an error correction code according to the preset error data.
  • the ECC error is interrupted, and the to-be-accessed data is data accessed in the data access request;
  • a migration unit configured to migrate the to-be-accessed data located in the non-volatile memory NVM into the DRAM when the processor interrupts the ECC error processing.
  • the concatenation module further includes: an establishing unit, configured to establish an address mapping table, the address mapping, before sending the preset error data to the memory controller
  • the table records that the storage module is currently located in the Data in the DRAM and data located in the NVM, the storage module being a hybrid memory composed of the DRAM and the NVM;
  • a receiving unit configured to receive the data access request
  • a determining unit configured to query the address mapping table according to the data access request, and determine whether the to-be-accessed data is in the DRAM;
  • An execution unit configured to: when the determining unit determines that the to-be-accessed data is in the DRAM, acquire the to-be-accessed data in the DRAM, and determine, by the determining unit, that the to-be-accessed data is In the DRAM, the sending unit is triggered to send the preset error data.
  • the migration unit specifically includes:
  • a generating sub-unit configured to generate a data migration request according to the data access request, where the data requested to be migrated in the data migration request is the to-be-accessed data;
  • a migration subunit configured to migrate the to-be-accessed data located in the NVM to the DRAM according to the preset migration granularity according to the data migration request.
  • the data access request includes a physical address of the to-be-accessed data
  • the generating sub-unit is specifically configured to: generate the data migration request according to the data access request, where the data migration request includes a physical address of the to-be-accessed data, and the data migration request further includes the preset migration granularity .
  • the preset migration granularity is the same as the granularity of the DRAM line buffer.
  • the address mapping table further records a cache flag, where the cache flag is used to identify whether the data is located in the cache.
  • the determining unit is further configured to query a cache flag in the address mapping, and determine whether the to-be-accessed data is located in a cache.
  • the execution unit is further configured to stop migrating the to-be-accessed data located in the NVM to the DRAM when the to-be-accessed data is in a cache.
  • the receiving unit is further configured to receive the data access request that is resent by the processor;
  • the determining unit is further configured to query the address mapping table according to the data access request, and determine that the to-be-accessed data is in the DRAM, and obtain the to-be-accessed data in the DRAM.
  • the preset error data is data that has at least two errors.
  • a processor including:
  • a receiving unit configured to receive a trigger message sent by the memory controller, where the trigger message is sent by the memory controller after receiving preset error data sent by the serial module, where the preset error data is the serial connection
  • the module is configured to: when the data to be accessed is not in the DRAM, the processing unit is configured to generate an error correction code ECC error interrupt according to the preset error data, so that the serial module interrupts the ECC error in the processor At the time of processing, the to-be-accessed data located in the NVM is migrated into the DRAM.
  • the processor further includes: a determining unit, configured to: before the generating an error correction code ECC error according to the preset error data, by using the The error data is set to perform ECC check, and it is determined whether the error mode of the preset error data is an ECC error interrupt mode.
  • the processor further includes:
  • a sending unit configured to resend the data access request to the serial module after the serial module migrates the to-be-accessed data located in the NVM to the DRAM, to facilitate the string
  • the module acquires the to-be-accessed data in the DRAM.
  • the preset error data is data that has at least two errors.
  • a fifth aspect provides a terminal device, including:
  • the storage module is a hybrid memory composed of the DRAM and the NVM;
  • the serial connection module is any of the above-mentioned serial connection modules, and is configured to send preset error data to the memory controller when the data to be accessed is not in the dynamic random access memory (DRAM), So that the memory controller triggers the processor to generate an error correction code ECC error interrupt according to the preset error data, the data to be accessed is data accessed in the data access request; and the processor interrupts the ECC error. Processing, the serial module migrates the to-be-accessed data located in the non-volatile memory NVM into the DRAM;
  • DRAM dynamic random access memory
  • the processor is any processor that is configured to receive a trigger message sent by a memory controller, where the trigger message is sent by the memory controller after receiving preset error data sent by the serial module.
  • the preset error data is sent by the serial module when the data to be accessed is not in the DRAM; generating an error correction code ECC error interrupt according to the preset error data, so as to interrupt the ECC error in the processor
  • the concatenation module migrates the to-be-accessed data located in the NVM into the DRAM.
  • An embodiment of the present invention provides a data access method, a module, a processor, and a terminal device of a hybrid memory, including: when the data to be accessed is not in the dynamic random access memory (DRAM), sending preset error data to the memory controller, so that The memory controller triggers the processor to generate an error correction code ECC error interrupt according to the preset error data, the data to be accessed is data accessed in the data access request; and the processor interrupts the ECC error processing.
  • the serial module migrates the data to be accessed located in the non-volatile memory NVM into the DRAM.
  • the ECC error interrupt is triggered by transmitting the preset error data, so that the data to be accessed is migrated when the ECC error is interrupted, and the existing ECC processing mechanism is utilized.
  • FIG. 1 is a flowchart of a method for accessing data of a hybrid memory according to an embodiment of the present invention
  • FIG. 2 is a flowchart of another method for accessing data of a hybrid memory according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a terminal device with a mixed memory in the prior art
  • FIG. 4 is a schematic structural diagram of a terminal device with a mixed memory according to an embodiment of the present invention
  • FIG. 5 is a flowchart of still another method for data access of a hybrid memory according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a method for generating preset error data according to an embodiment of the present invention
  • FIG. 7 is a schematic diagram of an address mapping table according to an embodiment of the present invention
  • FIG. 8 is a schematic structural diagram of a serial connection module according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of another serial connection module according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a migration unit in a serial connection module according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a processor according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of another processor according to an embodiment of the present invention.
  • the structure of the terminal device 10 having the mixed memory may be as shown in FIG. 1, including: a processor 101, a memory controller 102, and a storage module 103.
  • the storage module 103 includes: a DRAM 1031, an NVM 1032, that is, the The storage module 103 is a hybrid memory composed of the DRAM 1031 and the NVM 1032, wherein the memory controller 102 can exchange information with the storage module 103.
  • the memory controller is responsible for controlling the memory and making The memory exchanges data with the CPU, and in the terminal device 10, the operating system running by the processor 101 needs to modify and establish the flag bit in the page table entry by modifying the code amount, and generates a page fault when the DRAM 1031 does not have data to be accessed. Interrupt and so on.
  • the structure of the terminal device 20 can be as shown in FIG. 2, including: a processor 201, a memory controller 202, a serial connection module 203, and a storage module 204.
  • the storage module 204 includes: a DRAM 2041, an NVM 2042,
  • the memory controller 202 can perform information interaction with the serial module 203, and the memory access still uses the DDRx memory synchronous access interface.
  • the hardware structure of the memory controller 202 is the same as that of a normal memory controller.
  • the serial connection module 203 may be configured by an FPGA (Field-Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit), and the terminal device 20 may be an operating system (Operating System).
  • a system device, such as a server, can also be a virtual machine or the like.
  • An embodiment of the present invention provides a data access method for a hybrid memory, as shown in FIG. 3, which is applied to a serial connection module, and includes:
  • Step 301 When the data to be accessed is not in the dynamic random access memory (DRAM), send preset error data to the memory controller, so that the memory controller triggers the processor to generate an ECC according to the preset error data (Error Correcting Code). , error correction code) Error interrupt.
  • DRAM dynamic random access memory
  • the to-be-accessed data is data accessed in a data access request.
  • the storage space in the serial module in which the preset error data is stored may have a mapping relationship with the kernel space.
  • Step 302 When the processor interrupts the ECC error processing, the serial module migrates the to-be-accessed data located in the non-volatile memory NVM into the DRAM.
  • the data migration request may be generated according to the data access request, where the data requested to be migrated in the data migration request is the to-be-accessed data.
  • the data access request includes a physical address of the to-be-accessed data.
  • the splicing module generates the data migration request according to the data access request, where the data migration request includes a physical address of the data to be accessed, and the data migration request further includes the preset migration granularity;
  • the request, according to the preset migration granularity can be the same as the granularity of the DRAM line buffer.
  • a request queue may be set in the serial connection module, and the serial connection module first adds the data migration request to the request queue, and then sequentially according to the sequence of data migration requests in the request queue. Perform the migration of the corresponding data.
  • the ECC error interrupt is triggered by transmitting the preset error data, so that the data to be accessed is migrated when the ECC error is interrupted, and the existing ECC processing mechanism is utilized.
  • an address mapping table is further needed, where the address mapping table records data currently located in the DRAM and data located in the NVM in the storage module; receiving the data access request; The data access request queries the address mapping table to determine whether the data to be accessed is in the DRAM. Specifically, the address mapping table further records a cache flag, where the cache flag is used to identify whether the data is located in a cache (Cache); since the capacity of the DRAM is smaller than the NVM capacity, the DRAM is used for the cache of the NVM, that is, only Can store part of the NVM data. When the processor needs to access the data of the NVM, it needs to put the data into the DRAM first.
  • the cache flag is used to optimize the selection replacement process: the data in the cache is not replaced from the DRAM into the NVM, that is, the address map can be queried before the preset error data is sent to the memory controller.
  • a cache flag determining whether the to-be-accessed data is located in a cache; when the to-be-accessed data is located in a cache, stopping migrating the to-be-accessed data located in the NVM to the DRAM, so that the data is located in the cache The data to be accessed is not replaced from DRAM.
  • the serial module further needs to receive the data access request resent by the processor; query the address mapping table according to the data access request, and determine that the to-be-accessed data is in the In the DRAM, the to-be-accessed data is acquired in the DRAM.
  • An embodiment of the present invention provides a data access method for a hybrid memory, which is applied to a processor.
  • the CPU is a CPU (Central Processing Unit), as shown in FIG. 2, and includes: Step 401: Receive a trigger message sent by the memory controller, where the trigger message is sent by the memory controller after receiving the preset error data sent by the serial module, where the preset error data is the serial connection module. Sent when the data to be accessed is not in DRAM.
  • the preset error data may be data having at least two errors.
  • Step 402 Generate an ECC error interrupt according to the preset error data, so that when the serial module interrupts the ECC error interrupt processing, the serial module will be located in the NVM to be accessed. Data is migrated into the DRAM.
  • the processor may resend the data access request to the serial connection module, so that the serial connection module acquires the to-be-accessed data in the DRAM.
  • the trigger message sent by the memory controller is triggered to trigger the ECC error interrupt, so that the serial module performs the migration of the data to be accessed when the ECC error is interrupted.
  • the existing ECC processing mechanism reduces the memory management part of the existing processor core, reduces the amount of code modification, and simplifies the data access process.
  • the processor may perform an ECC check on the preset error data to determine whether the error mode of the preset error data is an ECC error interrupt mode, and the ECC error interrupt mode and the existing The ECC error interrupt mode is the same, and the present invention will not go into details.
  • the data access method of the mixed memory in the terminal device 20, as shown in FIG. 5, includes:
  • Step 501 The memory controller sends a data access request to the serial module.
  • the data access request of the memory controller may be generated and sent by the processor, and directly forwarded to the serial module by the memory controller, or may be generated by the memory controller according to the related data request sent by the processor.
  • a request queue may be established in the memory controller, and one or more of the data access requests are stored in the data request queue, and sequentially sent to the serial connection module.
  • Step 502 The serial module determines whether the data to be accessed is in the DRAM. When the data to be accessed is in the DRAM, step 508 is performed. When the data to be accessed is not in the DRAM, step 503 is performed.
  • the concatenation module may establish an address mapping table prior to step 501, the address mapping table recording data currently in the DRAM and data located in the NVM in the storage module. After receiving the data access request sent by the memory controller, querying the address mapping table according to the data access request to determine whether the to-be-accessed data is in the DRAM.
  • the address mapping table may set an In-DRAM field for indicating whether the data to be accessed is in the DRAM. In the In-DRAM field, 1 may be used to represent the data to be accessed in the DRAM, and 0 is the data to be accessed is not in the DRAM. Medium, but only in NVM.
  • Step 503 The serial module sends preset error data to the memory controller. Go to step 504.
  • the serial connection module can set a storage space, and the storage space stores preset error data, and the preset error data can trigger the ECC to process the ECC error interrupt mode, that is, the ECC error interrupt.
  • the serial module redirects the data access request to the storage space, and the preset error data is sent from the storage space to the memory controller.
  • the storage space in which the preset error data is stored in the serial connection module has a mapping relationship with the kernel space.
  • the storage space can be mapped to the kernel space by using the ioremap (10 address space remapping) system call, so as to ensure that the storage space is in addition to the serial module access, other parts, such as an OS, an application, etc. Will not visit.
  • the storage space is set to a space in which the preset error data is stored, and the preset error data is data having at least two errors.
  • the kernel space is a part of the specific space in the Linux system. When the Linux system divides itself, some core software is independent of the normal application and runs at a higher privilege level. They reside in the protected area. In the memory space, you have all the permissions to access the hardware device. This space is called kernel space.
  • FIG. 6 shows an example of generating preset error data.
  • the preset error data has 4 errors.
  • the preset data A is obtained, and the preset data A is subjected to an ECC operation to obtain preset data.
  • the ECC value of A, the 16 bits of the binary value of the preset data A are all 1, and then the preset data A is modified to obtain the error data B, so that the data of the specified four positions of the binary value of the error data B is more preset data.
  • A is inverted (from 1 to 0).
  • the binary values of the preset data A are reversed from the right, left 9, 9, 15, and 16 bits to obtain the ECC of the preset data A.
  • the value is the ECC value of the error data B, that is, the error data B and the preset data A have the same ECC value, but the binary values are different, and finally the binary value of the error data B and the ECC value of the error data B are used as preset errors. data.
  • Step 504 The memory controller sends a trigger message to the processor.
  • the memory controller calculates a corresponding ECC value according to the received data, and then compares it with the read ECC value, and compares whether the calculated ECC value and the read ECC value are the same to determine whether an error occurs, when returning data.
  • the memory controller directly corrects the position of the error.
  • the memory controller receives the preset error data, so it will determine that there is an error, and The processor sends a trigger message, and the trigger message includes preset error data.
  • Step 505 The processor determines whether the error mode of the preset error data is an ECC error interrupt mode. When the error mode of the preset error data is the ECC error interrupt mode, step 506 is performed, and when the error mode of the preset error data is not the ECC error interrupt mode, step 510 is performed.
  • the processor performs ECC check on the preset error data in the trigger message. Specifically, the error mode is first determined. Because there are at least two errors in the data returned by the memory controller, the processor generates an ECC error interrupt.
  • the processor performs the ECC check on the preset error data, but there are at least two errors in the returned data.
  • the ECC error is the normal error mode
  • the other is the ECC error interrupt mode. Therefore, it is necessary to determine whether the error mode of the preset error data is the ECC error interrupt mode.
  • the ECC error interrupt mode is related to the preset error data. For example, as shown in FIG. 6, when the preset error data is composed of the error data B and the ECC value of the preset data A, when the error data B is ECC When the ECC value of the error data B as shown in Fig. 6 is obtained by the operation, it indicates that the ECC error interrupt mode has occurred.
  • Step 506 The processor generates an ECC error interrupt. Go to step 507. in. Go to step 508.
  • the contiguous module may generate a data migration request according to the data access request, where the data requested to be migrated in the data migration request is the to-be-accessed data. Specifically, the data access request includes a physical address of the to-be-accessed data.
  • the splicing module generates the data migration request according to the data access request, where the data migration request includes a physical address of the to-be-accessed data, and the data migration request further includes the preset migration granularity;
  • the migration request may be set in the serial connection module according to the preset application, and the serial connection module may first add the data migration request to the request queue, and then follow each data migration request in the request queue. The order of the data is migrated in sequence.
  • the size of the row buffer (Row Buffer) of the DRAM may be selected as the granularity of the NVM to DRAM migration, so that when the row address of the data to be accessed is migrated to the DRAM, if the serial module receives the memory
  • the address mapping table can be directly used to query the address mapping table to query whether the data to be accessed is in the DRAM. If not, the migration operation from step 503 to step 506 can be repeated immediately. Inquiries, which can reduce the time delay caused by part of the data migration operation and improve data access performance.
  • Step 508 The processor resends the data access request to the serial module. Steps
  • the first status register may be included in the serial connection module, and each time the ECC error interrupt mode occurs, the serial connection module sets the value of the corresponding indication register to 1; and these registers can be mapped into the kernel space, each time When the ECC error is interrupted, the memory controller first reads these status registers. If it is 1, it recognizes the ECC error interrupt mode. If it is 0, it recognizes the normal error mode.
  • the serial connection module includes a second status register
  • the second status register indicates whether the work of migrating the data to be accessed from the NVM to the DRAM is completed, the serial connection module is provided with a migration queue, and the serial connection module adds the data migration request to the
  • the status register is set to 0, after the data migration to be accessed is completed, the status register is set to 1; the memory controller queries the second register, Once the value of the second register is found to be 1, indicating that the migration has completed, the data access request can be resent.
  • Step 509 The serial module sends the to-be-accessed data in the DRAM to the memory controller.
  • Step 510 The processor executes a normal ECC processing procedure.
  • the address mapping table may further record other state information, such as data located in the cache.
  • the serial module may query the address mapping table. Data in the cache that exceeds a preset time limit migrates to the DRAM.
  • the address mapping table may be as shown in FIG. 7.
  • ADDR Address
  • In-DRAM is used to indicate whether data is in DRAM, and 1 may be used in the In-DRAM field.
  • the first data is in the DRAM, 0 means that the data is not in the DRAM, but only in the NVM;
  • the address mapping table also records a cache flag, and the cache flag is used to identify whether the data is in the cache, such as using In-Cache Indicates whether the data is in the cache.
  • the serial module can determine whether to replace the data in the DRAM according to the In-Cache; lru is the replacement indication of the data in the DRAM; NVM-ADDR indicates the address where the data is stored in the NVM.
  • the In-Cache When data is read from the DRAM into the cache, the In-Cache is set to 1. When the data is replaced from the cache into the DRAM, the In-Cache is reset to 0.
  • the replacement strategy of the DRAM in this embodiment. Medium, select one of the oldest data blocks in the cache that exceeds the preset time limit and is not accessed, and replace it with DRAM, that is, look forward from the lru position and find the first In-Cache 0 data block from the cache. Replaced with DRAM.
  • the data is data that needs to be queried or data to be accessed.
  • the cache flag in the address mapping may be queried to determine whether the to-be-accessed data is located in the cache; Stopping migrating the to-be-accessed data located in the NVM into the DRAM.
  • the ECC error interrupt is triggered by receiving the preset error data, so that the serial module performs the migration of the data to be accessed when the ECC error is interrupted.
  • Some ECC processing mechanisms eliminate the need to change the hardware structure of the memory controller, reduce the redesign of the memory management part of the operating system running on the existing processor, reduce the amount of code modification, and simplify the data access process.
  • the embodiment of the present invention provides a serial connection module 60.
  • the serial connection module 60 is composed of an FPGA or an ASIC. As shown in FIG. 8, the method includes:
  • the sending unit 601 is configured to send preset error data to the memory controller when the data to be accessed is not in the dynamic random access memory (DRAM), so that the memory controller triggers the processor to generate an ECC error according to the preset error data.
  • the data to be accessed is the data accessed in the data access request.
  • the migration unit 602 is configured to migrate the to-be-accessed data located in the non-volatile memory NVM into the DRAM when the processor interrupts the ECC error processing.
  • the transmitting unit triggers the ECC error interrupt by transmitting the preset error data, so that the migration unit performs the migration of the data to be accessed when the ECC error is interrupted, and the existing data is utilized.
  • the ECC processing mechanism eliminates the need to change the hardware structure of the memory controller, reduces the redesign of the memory management part of the operating system running on the existing processor, reduces the amount of code modification, and simplifies the data access process.
  • serial connection module 60 further includes:
  • the establishing unit 603 is configured to: before the sending the preset error data to the memory controller, establish an address mapping table, where the address mapping table records data currently located in the DRAM in the storage module And data located in the NVM, the storage module is a hybrid memory composed of the DRAM and the NVM.
  • the receiving unit 604 is configured to receive the data access request.
  • the determining unit 605 is configured to query the address mapping table according to the data access request, and determine whether the to-be-accessed data is in the DRAM.
  • the executing unit 606 is configured to: when the determining unit 604 determines that the to-be-accessed data is in the DRAM, acquire the to-be-accessed data in the DRAM, and determine, by the determining unit, that the to-be-accessed When the data is in the DRAM, the sending unit 601 is triggered to send the preset error data.
  • the receiving unit 604 is further configured to receive the data access request that is resent by the processor.
  • the determining unit 605 is further configured to query the address mapping table according to the data access request, and determine that the to-be-accessed data is obtained. In the DRAM, the to-be-accessed data is acquired in the DRAM.
  • the migration unit 602 specifically includes:
  • a generating sub-unit 6021 configured to generate a data migration request according to the data access request, where the data requested to be migrated in the data migration request is the to-be-accessed data;
  • the migration sub-unit 6022 is configured to: according to the data migration request, the data access request according to the preset migration granularity, including the physical address of the to-be-accessed data,
  • the generating sub-unit 6021 is specifically configured to: generate the data migration request according to the data access request, where the data migration request includes a physical address of the to-be-accessed data, and the data migration request further includes the preset migration granularity.
  • the preset migration granularity may be the same as the granularity of the DRAM row buffer.
  • the address mapping table may also record a cache flag, and the cache flag is used to identify whether the data is located in the cache.
  • the preset error data may be data having at least two errors. Since the capacity of the DRAM is smaller than the NVM capacity, the DRAM is used for the cache of the NVM, that is, only part of the NVM data can be stored. When the processor needs to access the data of the NVM, it needs to put the data into the DRAM first. If the capacity in the DRAM is full, that is, there is no free space, you need to first replace the data in the DRAM and put it back in the NVM.
  • this cache flag is used to optimize this selection replacement process: the data located in the cache is not replaced from the DRAM into the NVM, that is, the migration unit 602 can be used to replace the data in the selected DRAM and put it back into the NVM.
  • the flag for identifying whether the data is located in the cache (Cache) needs to be queried, and if the data is in the cache, it is not replaced from the DRAM.
  • the determining unit 605 is further configured to query a cache flag in the address mapping, and determine whether the to-be-accessed data is located in a cache.
  • the executing unit 606 is further configured to: when the to-be-accessed data is located in a cache, Stop migrating the to-be-accessed data located in the NVM into the DRAM.
  • the sending unit when the data to be accessed is not in the dynamic random access memory DRAM, the sending unit triggers the ECC error interrupt by sending the preset error data, so that the migration unit performs the data to be accessed when the ECC error is interrupted.
  • Migration using the existing ECC processing mechanism, without changing the hardware structure of the memory controller, reducing the redesign of the memory management part of the operating system running on the existing processor, reducing the amount of code modification, simplifying data access process.
  • the embodiment of the present invention provides a processor 70, as shown in FIG. 11, including:
  • the receiving unit 701 is configured to receive a trigger message sent by the memory controller, where the trigger message is sent by the memory controller after receiving preset error data sent by the serial module, where the preset error data is the string
  • the module is sent when the data to be accessed is not in the DRAM.
  • the processing unit 702 is configured to generate an ECC error interrupt according to the preset error data, so that the serial connection module migrates the to-be-accessed data located in the NVM when the processor interrupts the ECC error processing. To the DRAM.
  • the receiving unit triggers the processing unit to perform an ECC error interrupt by receiving a trigger message sent by the memory controller, so that the serial module performs the access when the ECC error is interrupted.
  • DRAM dynamic random access memory
  • the processing mechanism reduces the memory management part of the existing processor core, reduces the amount of code modification, and simplifies the data access process.
  • the processor 70 further includes:
  • the determining unit 703 is configured to determine whether the error mode of the preset error data is an ECC error interrupt by performing an ECC check on the preset error data before the generating an ECC error interrupt according to the preset error data. mode.
  • the sending unit 704 is configured to resend the data access request to the serial module after the serial module migrates the to-be-accessed data located in the NVM into the DRAM, to facilitate the The serial module acquires the data to be accessed in the DRAM.
  • the preset error data may be data having at least two errors.
  • the processor provided by the embodiment of the present invention, when the data to be accessed is not in the dynamic random access memory (DRAM), the receiving unit triggers the processing unit to perform an ECC error interrupt by receiving a trigger message sent by the memory controller, so that the serial module fails in the ECC.
  • the data to be accessed is migrated during the interruption, and the existing ECC processing mechanism is used to reduce the redesign of the memory management part of the existing processor core, which reduces the amount of code modification and simplifies the data access process.
  • the embodiment of the present invention provides a terminal device 20, as shown in FIG. 2, including: a processor 201, a memory controller 202, a serial connection module 203, and a storage module 204.
  • the storage module 204 includes: a DRAM 2041, an NVM 2042, where The memory controller 202 can exchange information with the serial module 203.
  • the memory access still uses the DDRx memory synchronous access interface.
  • the hardware structure of the memory controller 202 is the same as that of a normal memory controller.
  • the serial connection module 203 is composed of an FPGA or an ASIC, and the terminal device 20 may be a device running an OS (Operating System), a virtual machine, or the like.
  • the serial connection module 203 is a serial connection module according to any embodiment of the present invention, configured to send preset error data to the memory controller when the data to be accessed is not in the dynamic random access memory (DRAM), so as to facilitate the memory.
  • the controller triggers the processor to generate an error correction code ECC error interrupt according to the preset error data, and the to-be-accessed data is data accessed in the data access request;
  • ECC error interrupt processing is performed, migrates the to-be-accessed data located in the non-volatile memory NVM into the DRAM.
  • the processor 201 is configured to receive a trigger message sent by a memory controller, where the trigger message is after the memory controller receives the preset error data sent by the serial module. And sending, the preset error data is sent by the serial module when the data to be accessed is not in the DRAM; generating an error correction code ECC error interrupt according to the preset error data, so as to be in the processor pair
  • the serial module migrates the to-be-accessed data located in the NVM into the DRAM.
  • the disclosed systems, devices, and methods may be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be electrical, mechanical or otherwise.
  • the components displayed for the unit may or may not be physical units, ie may be located in one place, or may be distributed over multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may be physically included separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • the foregoing program may be stored in a computer readable storage medium, and when executed, the program includes the steps of the foregoing method embodiment; and the foregoing storage medium includes: ROM, RAM
  • ROM read-only memory
  • RAM random access memory

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Abstract

La présente invention concerne un procédé, un module, un processeur et un dispositif terminal d'accès aux données de mémoire hybride, capables de simplifier le processus d'accès aux données, le procédé comprenant les étapes suivantes : lorsque les données qui doivent être accédées ne se trouvent pas dans une mémoire vive dynamique (DRAM), la transmission de données d'erreurs préétablies vers un contrôleur de mémoire, pour que le contrôleur de mémoire déclenche un processeur selon les données d'erreurs préétablies pour générer une interruption d'erreur d'un code de correction d'erreurs (ECC), les données qui doivent être accédées étant les données dans une demande d'accès aux données ; lors de la gestion d'interruption d'erreur de code ECC par le processeur, un module de concaténation transfère les données qui doivent être accédées dans la mémoire non volatile (NVM) vers la mémoire DRAM. Le procédé, le module, le processeur et le dispositif terminal d'accès à une mémoire hybride de données sont utilisés pour l'accès à des données de mémoire hybride.
PCT/CN2014/082974 2013-07-25 2014-07-25 Procédé, module, processeur et dispositif terminal d'accès aux données de mémoire hybride WO2015010646A1 (fr)

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CN106569960B (zh) * 2016-11-08 2019-05-28 郑州云海信息技术有限公司 一种混合主存的末级缓存管理方法
CN109952565B (zh) * 2016-11-16 2021-10-22 华为技术有限公司 内存访问技术
CN110807125B (zh) * 2019-08-03 2020-12-22 北京达佳互联信息技术有限公司 推荐***、数据访问方法及装置、服务器、存储介质
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