WO2015010404A1 - Transistor à couches minces, son procédé de fabrication, substrat de matrice et dispositif d'affichage - Google Patents

Transistor à couches minces, son procédé de fabrication, substrat de matrice et dispositif d'affichage Download PDF

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Publication number
WO2015010404A1
WO2015010404A1 PCT/CN2013/088101 CN2013088101W WO2015010404A1 WO 2015010404 A1 WO2015010404 A1 WO 2015010404A1 CN 2013088101 W CN2013088101 W CN 2013088101W WO 2015010404 A1 WO2015010404 A1 WO 2015010404A1
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Prior art keywords
electrode
gate
active layer
substrate
thin film
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PCT/CN2013/088101
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English (en)
Chinese (zh)
Inventor
张文余
谢振宇
田宗民
李婧
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北京京东方光电科技有限公司
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Publication of WO2015010404A1 publication Critical patent/WO2015010404A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • Embodiments of the present invention relate to a thin film transistor, a method of fabricating the same, an array substrate, and a display device. Background technique
  • the liquid crystal display panel includes an array substrate, a counter substrate, and a liquid crystal disposed between the array substrate and the counter substrate.
  • the array substrate includes: a substrate substrate 1, a plurality of gate lines 2 formed on the substrate substrate 1, and a plurality of data lines 4, and the gate lines 2 and the data lines 4 are formed to cross each other.
  • Each pixel unit includes a thin film transistor (TFT) 3 that functions as a switch.
  • the thin film transistor 3 includes: a gate electrode 31 disposed on the substrate 1 , a gate insulating layer 7 , an active layer 8 , and an active layer 8 on both sides of the gate Drain 33 and source 32.
  • the gate 31 is connected to the gate line 2, the source 32 is connected to the data line 4, and the drain 33 is connected to the pixel electrode 5.
  • the gate line 2 supplies a gate signal to the gate 31 and the data line 4 supplies a data signal to the source 32, the source 32 and the drain 33 of the thin film transistor 3 are turned on to charge the pixel electrode 5 connected to the drain 33.
  • the channel length of the TFT is inversely proportional to the channel length, that is, the channel length is larger, the larger the on-state current of the TFT, the larger the drain current.
  • the channel length is the distance between the source and the drain, as shown in Figure 2, the channel length is b.
  • the channel length of the TFT is generally only a minimum of 3 to 4 um, which causes the on-state current of the TFT to be not too large. Summary of the invention
  • a thin film transistor includes a gate electrode disposed on a substrate substrate, a gate insulating layer, an active layer, and first and second electrodes insulated from each other.
  • the first electrode is disposed on a side of the active layer adjacent to the substrate
  • the second electrode is disposed on a side of the active layer away from the substrate, and the An electrode and the second electrode are in contact with the active layer.
  • the gate is disposed in the same layer as the first electrode, and the gate and the first electrode Insulation.
  • the first electrode is a drain and the second electrode is a source.
  • the gate insulating layer covers the gate, the active layer and the drain, and the source is formed on the gate insulating layer, whereby the gate insulating layer is disposed on the source And the active layer; and the source is in contact with the active layer through a first via provided on the gate insulating layer.
  • the thin film transistor further includes: a gate auxiliary electrode, the gate auxiliary electrode is disposed on the upper surface of the gate insulating layer, and the gate auxiliary electrode passes through the second via hole disposed on the gate insulating layer The gate is electrically connected.
  • the drain, the active layer, and the source are sequentially disposed in an overlapping manner.
  • the active layer in the direction perpendicular to the substrate of the substrate, includes an amorphous silicon semiconductor layer located in the middle, and an ohmic contact layer on both sides of the amorphous silicon semiconductor layer.
  • the gate insulating layer is made of a material having a dielectric constant of 3-15.
  • an array substrate comprising the thin film transistor of any of the above.
  • the array substrate further includes a pixel electrode, the first electrode is a drain, a gate insulating layer is disposed between the drain and the pixel electrode, and the pixel electrode passes through a third via disposed on the gate insulating layer The drain is electrically connected.
  • the array substrate further includes a pixel electrode, the first electrode is a drain, and the pixel electrode is disposed under the drain and is in direct contact with the drain.
  • a display device comprising any of the array substrates as described above.
  • a method of fabricating a thin film transistor comprising: forming a gate, a gate insulating layer, an active layer, and a first electrode and a second electrode insulated from each other on a substrate.
  • the first electrode is disposed on a side of the active layer adjacent to the substrate
  • the second electrode is disposed on a side of the active layer away from the substrate, and the An electrode and the second electrode are in contact with the active layer.
  • the gate is disposed in the same layer as the first electrode, and the gate is insulated from the first electrode.
  • the gate and the first electrode are formed by one patterning process.
  • the first electrode is a drain and the second electrode is a source.
  • the gate insulating layer covers the gate, the active layer and the drain, and the source is formed on the gate insulating layer, whereby the gate insulating layer is disposed on the source And the active layer; and the source is in contact with the active layer through a first via provided on the gate insulating layer.
  • the method further includes: forming a gate auxiliary electrode, wherein the gate auxiliary electrode is disposed in the same layer as the second electrode, and passing through the second via and the gate disposed on the gate insulating layer Electrical connection.
  • the gate auxiliary electrode and the second electrode are formed by one patterning process.
  • the drain, the active layer, and the source are sequentially disposed in an overlapping manner.
  • 1 is a schematic top plan view of a conventional array substrate
  • FIG. 2 is a cross-sectional structural view of the thin film transistor of FIG. 1;
  • FIG. 3 is a cross-sectional structural view of a thin film transistor according to an embodiment of the present invention
  • FIG. 4 is a cross-sectional structural view of another thin film transistor according to an embodiment of the present invention
  • An embodiment of the present invention provides a thin film transistor including a gate electrode disposed on a substrate substrate, a gate insulating layer, an active layer, and first and second electrodes insulated from each other; and a direction perpendicular to the substrate of the substrate.
  • the first electrode is disposed on a side of the active layer adjacent to the substrate, the second electrode is disposed on a side of the active layer away from the substrate, and the first electrode and the second electrode are The active layer is in contact. It should be noted that the first electrode and the second electrode are in contact with the active layer, and may be a direct contact or a via contact.
  • the contact manner of the embodiment of the present invention is not specifically limited.
  • a thin film transistor includes a gate, a gate insulating layer, an active layer, and first and second electrodes insulated from each other, in a direction perpendicular to the substrate substrate, the first embodiment of the present invention
  • An electrode is disposed on a side of the active layer adjacent to the substrate, the second electrode is disposed on a side of the active layer away from the substrate, and the first electrode and the second electrode are coupled to the active Layer contact.
  • the channel length of the thin film transistor is determined by the thickness of the active layer, so that the channel length can be reduced by appropriately setting the thickness of the active layer between the source and the drain. Increasing the on-state current of the thin film transistor, thereby improving the characteristics of the thin film transistor.
  • the gate is disposed in the same layer as the first electrode, and the gate is insulated from the first electrode.
  • the gate is disposed in the same layer as the second electrode, and the gate is insulated from the second electrode.
  • the gate electrode may not be disposed in the same layer as the first electrode or the second electrode, and the thin film transistor may be turned on after a voltage is applied to the gate electrode.
  • the gate is provided in the same layer as the first electrode, and the gate is insulated from the first electrode as an example for detailed description.
  • the first electrode is a drain and the second electrode is a source.
  • the drain electrode 33 is disposed on a side of the active layer 8 adjacent to the substrate substrate 1
  • the source electrode 32 is disposed on a side of the active layer 8 away from the substrate substrate 1.
  • the first electrode is a drain and the second electrode is a source.
  • the first electrode may also be a source
  • the second electrode is a drain.
  • the first electrode is a drain and the second electrode is a source.
  • the gate insulating layer is disposed between the source and the active layer, and the source is in contact with the active layer through a first via provided on the gate insulating layer.
  • a gate insulating layer 7 covers the gate electrode 31, the active layer 8 and the drain electrode 33, and a source electrode 32 is formed on the gate insulating layer 7, thereby making the gate insulating layer 7 is located between the source 32 and the active layer 8, and the source 32 is in contact with the active layer 8 through a first via provided on the gate insulating layer 7.
  • the thin film transistor further includes: a gate auxiliary electrode, the gate auxiliary electrode is disposed on the upper surface of the gate insulating layer, and the gate auxiliary electrode passes through the second via hole disposed on the gate insulating layer The gate is electrically connected.
  • the thin film transistor further includes a gate auxiliary electrode 34 disposed on the upper surface of the gate insulating layer 7 and passing through the second via hole on the gate insulating layer 7. Electrically connected to the gate 31, the distance between the gate 31 and the active layer 8 can be reduced. If the gate auxiliary electrode is not provided, the distance between the gate 31 and the active layer 8 is its horizontal distance d, which is limited by the exposure process, and the distance is large, which affects the opening effect.
  • the distance between the gate auxiliary electrode 34 and the active layer 8 is c, c is equal to the thickness of the gate insulating layer, and the opening effect can be effectively improved by controlling the thickness c of the gate insulating layer.
  • the drain, the active layer, and the source are sequentially overlapped and stacked.
  • the drain 33, the active layer 8, and the source 32 are sequentially arranged in an overlapping manner.
  • the formed thin film transistor has good flatness, which is advantageous for improving the display effect.
  • the active layer in the direction perpendicular to the substrate of the substrate, includes an amorphous silicon semiconductor layer located in the middle, and an ohmic contact layer on both sides of the amorphous silicon semiconductor layer.
  • the active layer 8 includes an amorphous silicon semiconductor layer 80 in the middle and an ohmic contact layer 81 on both sides of the amorphous silicon semiconductor layer 80 in a direction perpendicular to the substrate of the substrate. .
  • the gate insulating layer is made of a material having a dielectric constant of 3-15. It should be noted that the higher the dielectric constant of the gate insulating layer, the more favorable it is to increase the on-state current of the thin film transistor.
  • the gate insulating layer may be SiN x , SiO x , SiON, a resin, or the like.
  • An embodiment of the present invention provides an array substrate, including the thin film transistor according to any one of the embodiments of the present invention.
  • the array substrate further includes a pixel electrode, the first electrode is a drain, a gate insulating layer is disposed between the drain and the pixel electrode, and the pixel electrode passes through a third via disposed on the gate insulating layer
  • the drain is electrically connected.
  • the pixel electrode 5 is electrically connected to the drain 33 through a third via provided on the gate insulating layer 7, and is charged by the drain 33 to effect display.
  • the array substrate further includes a pixel electrode, the first electrode is a drain, and the pixel electrode is disposed under the drain and is in direct contact with the drain.
  • the pixel electrode 5 is disposed under the drain 33, which is electrically connected in direct contact with the drain 33, and is charged by the drain 33 to effect display.
  • the array substrate includes the thin film transistor provided by the embodiment of the invention, and the first electrode may be a drain or a source.
  • the second electrode is a source when the first electrode is a drain, and the second electrode is a drain when the first electrode is a source.
  • the array substrate may also include other thin film or layer structures. As shown in FIG. 3 to FIG. 5, a flat layer is disposed on the array substrate. 9. Other thin films or layer structures may be disposed on the array substrate according to actual needs, and are not described herein.
  • An embodiment of the present invention provides a display device, including any of the array substrates provided by the embodiments of the present invention.
  • the display device may be a display device such as a liquid crystal display, an electronic paper, an OLED (Organic Light-Emitting Diode) display, or any display-enabled product such as a television, a digital camera, a mobile phone, a tablet, or the like including the display device. Or parts.
  • a display device such as a liquid crystal display, an electronic paper, an OLED (Organic Light-Emitting Diode) display, or any display-enabled product such as a television, a digital camera, a mobile phone, a tablet, or the like including the display device. Or parts.
  • Embodiments of the present invention provide a method of fabricating a thin film transistor, including: forming a gate, a gate insulating layer, an active layer, and a first electrode and a second electrode insulated from each other on a substrate of the substrate; a direction of the substrate of the substrate, the first electrode is disposed on a side of the active layer adjacent to the substrate, the second electrode is disposed on a side of the active layer away from the substrate, and the first electrode and the The second electrode is in contact with the active layer.
  • the gate is disposed in the same layer as the first electrode, and the gate is insulated from the first electrode.
  • the gate electrode and the first electrode may be formed by one patterning process.
  • the so-called "patterning process” is a process of forming a film into a layer containing at least one pattern.
  • the patterning process generally comprises: coating the film on the film, exposing the photoresist by using a mask, etching away the photoresist to be removed by using a developing solution, and etching away the portion of the film not covered with the photoresist, Finally, the remaining photoresist is stripped.
  • the "primary patterning process” refers to a process of forming a desired layer structure by one exposure.
  • the gate and the first electrode are formed by one patterning process to reduce the number of exposures, thereby reducing the fabrication process and reducing the production cost.
  • the gate is disposed in the same layer as the second electrode, and the gate is insulated from the second electrode.
  • the gate electrode and the second electrode may be formed by one patterning process.
  • the gate electrode may not be disposed in the same layer as the first electrode or the second electrode, as long as the thin film transistor can be turned on after a voltage is applied to the gate.
  • the gate is provided in the same layer as the first electrode, and the gate is insulated from the first electrode as an example.
  • the first electrode is a drain and the second electrode is a source.
  • the first electrode may also be a source, and the second electrode is a drain.
  • the first electrode is a drain and the second electrode is a source.
  • first electrode and the second electrode are in contact with the active layer, which may be a direct contact or a contact through a via. Limited.
  • the manufacturing method of the thin film transistor includes the following steps:
  • Step S101 forming a first electrode and a gate on the substrate of the village.
  • the first electrode is a drain.
  • a metal film having a thickness of ⁇ to 7000A can be prepared on a substrate substrate using a magnetron sputtering method.
  • the metal thin film can usually be made of a metal such as molybdenum, aluminum, an aluminum-nickel alloy, a molybdenum-tungsten alloy, chromium, or copper, or a combination of the above-mentioned materials.
  • a drain 33 and a gate 31 as shown in Figs. 3 to 5 are formed on the substrate of the village by a patterning process. It should be noted that the gate and the drain may also be separately formed by two patterning processes.
  • Step S102 forming an active layer on the substrate of the village.
  • the substrate substrate may be a substrate substrate having a gate and a drain formed after the step S101.
  • a semiconductor thin film can be deposited on a substrate substrate on which a drain and a gate are formed by chemical vapor deposition.
  • an active layer 8 as shown in Figs. 3 to 5 is formed on the substrate of the village by a patterning process.
  • an amorphous silicon film and an n+ amorphous silicon film having a thickness of ⁇ to 6000A are deposited on the substrate on which the drain electrode 33 and the gate electrode 31 are formed.
  • an active layer 8 as shown in Fig. 5 is formed on the substrate of the substrate by a patterning process, and the active layer 8 includes an amorphous silicon semiconductor layer 80 in the middle and a contact layer 81.
  • the substrate substrate may be a substrate substrate on which an active layer is formed after step S102.
  • an insulating film having a thickness of 1000 A to 6000 A may be continuously deposited on a substrate by chemical vapor deposition.
  • the material of the insulating film is usually silicon nitride, and silicon oxide, silicon oxynitride or the like may also be used.
  • a gate insulating layer 7 having a first via hole as shown in Figs. 3 to 5 is formed by a patterning process. The source and the active layer are in contact through the first via.
  • Step S104 forming a second electrode on the substrate of the village.
  • the substrate substrate may be a village substrate on which a gate insulating layer is formed after step S103.
  • the second electrode is a source.
  • a metal thin film having a thickness of ⁇ to 7000A can be prepared on a substrate of a village using a magnetron sputtering method.
  • the metal film can usually be made of a metal such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper, or a group of the above-mentioned materials. Structure.
  • a source electrode 32 that is in contact with the active layer 8 through the first via hole is formed on the substrate of the village by a patterning process.
  • the manufacturing method further includes: forming a gate auxiliary electrode on the substrate.
  • the gate auxiliary electrode is formed in the same layer as the second electrode and is formed by one patterning process. That is, the gate auxiliary electrode and the second electrode are simultaneously formed by a patterning process on the substrate of the village.
  • other thin film transistors of the embodiment of the present invention may also form a gate auxiliary electrode as needed.
  • the method for fabricating the thin film transistor provided by the embodiment of the present invention is not limited to the specific examples described above.
  • the embodiment of the present invention is described by taking the above specific example as an example.
  • a passivation layer 9 and a pixel electrode 5 may be formed on the substrate substrate after forming the thin film transistor, wherein The pixel electrode 5 is electrically connected to the drain 33 through a second via formed on the passivation layer 9 and the gate insulating layer 7.
  • the steps of fabricating the pixel electrode and the passivation layer will not be described in detail herein.
  • the pixel electrode 5 may be formed before step S101, and the passivation layer 9 is formed after step S104.
  • the steps of fabricating the pixel electrode and the passivation layer will not be described in detail herein.
  • the manufacturing method may be different according to the type of the array substrate.
  • Other thin films or layer structures may be disposed on the array substrate according to actual needs, and are not described herein.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

Cette invention concerne un transistor à couches minces, son procédé de fabrication, un substrat de matrice et un dispositif d'affichage. Ledit transistor à couches minces comprend une électrode grille (31), une couche d'isolation de grille (7), une couche active (8), une première électrode et une seconde électrode, ladite électrode grille (31), la couche d'isolation de grille (7) et la couche active (8) étant agencées sur un substrat (1), tandis que la première électrode et la seconde électrode sont mutuellement isolées. Le long du sens perpendiculaire au substrat (1), la première électrode est disposée sur un côté de la couche active, à proximité du substrat (1), la seconde électrode est disposée sur un côté de la couche active (8), à l'écart du substrat (1), et la première électrode ainsi que la seconde électrode sont en contact avec la couche active (8).
PCT/CN2013/088101 2013-07-25 2013-11-29 Transistor à couches minces, son procédé de fabrication, substrat de matrice et dispositif d'affichage WO2015010404A1 (fr)

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CN201310316885.1A CN103413834B (zh) 2013-07-25 2013-07-25 一种薄膜晶体管及其制作方法、阵列基板及显示装置
CN201310316885.1 2013-07-25

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Cited By (2)

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EP3278368A4 (fr) * 2015-03-18 2018-12-05 BOE Technology Group Co., Ltd. Transistor à couches minces, substrat de matrice, et leur procédé de fabrication, et dispositif d'affichage
CN113437156A (zh) * 2021-06-07 2021-09-24 惠州华星光电显示有限公司 半导体器件及其制备方法

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CN103413834B (zh) * 2013-07-25 2016-01-20 北京京东方光电科技有限公司 一种薄膜晶体管及其制作方法、阵列基板及显示装置
CN103700667B (zh) * 2013-12-18 2017-02-01 北京京东方光电科技有限公司 一种像素阵列结构及其制作方法、阵列基板和显示装置
CN106952948A (zh) * 2016-01-06 2017-07-14 中华映管股份有限公司 主动元件及其制作方法
CN108987484A (zh) 2018-07-27 2018-12-11 京东方科技集团股份有限公司 一种薄膜晶体管的制备方法和薄膜晶体管

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