WO2014207893A1 - Computation circuit and computer - Google Patents

Computation circuit and computer Download PDF

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Publication number
WO2014207893A1
WO2014207893A1 PCT/JP2013/067816 JP2013067816W WO2014207893A1 WO 2014207893 A1 WO2014207893 A1 WO 2014207893A1 JP 2013067816 W JP2013067816 W JP 2013067816W WO 2014207893 A1 WO2014207893 A1 WO 2014207893A1
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WO
WIPO (PCT)
Prior art keywords
arithmetic
unit
redundant
arithmetic unit
fpga
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Application number
PCT/JP2013/067816
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French (fr)
Japanese (ja)
Inventor
本村　哲朗
Original Assignee
株式会社日立製作所
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Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to PCT/JP2013/067816 priority Critical patent/WO2014207893A1/en
Publication of WO2014207893A1 publication Critical patent/WO2014207893A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/183—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components
    • G06F11/184—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components where the redundant components implement processing functionality
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • G06F11/1645—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components and the comparison itself uses redundant hardware

Definitions

  • the present invention relates to a technique for improving the reliability of a redundant arithmetic circuit.
  • FPGA Field Programmable Gate Array
  • ASIC Application Specific Integrated Circuit
  • the SRAM type FPGA implements the user-defined internal configuration by loading bitstream data defining the internal configuration into a CRAM (Configuration RAM). Each bit of the bit stream data data loaded into the CRAM indicates a circuit configuration defined by the user.
  • CRAM Configuration RAM
  • Patent Literature 1 and Patent Literature 2 are known as techniques that use triplexing to ensure redundancy.
  • the present invention provides a redundant arithmetic unit including a first arithmetic unit and a second arithmetic unit that operate on input data in parallel, an arithmetic result of the first arithmetic unit, and the second arithmetic unit.
  • a redundant arithmetic unit including a first arithmetic unit and a second arithmetic unit that operate on input data in parallel, an arithmetic result of the first arithmetic unit, and the second arithmetic unit.
  • a redundant arithmetic unit including two arithmetic units and an arithmetic circuit having one third arithmetic unit, the redundant arithmetic unit and the third arithmetic unit are tripled only when an error occurs. It is possible to restore the operation result by performing the operation with the converted operation unit and performing the majority process with the majority circuit, and it is possible to improve the reliability while suppressing the manufacturing cost of the operation circuit.
  • FIG. 1 is a block diagram illustrating an example of a computer system according to a first embodiment of this invention.
  • FIG. It is a block diagram which shows the 1st Example of this invention and shows an example of a matching engine (ME) server.
  • ME matching engine
  • 1 is a block diagram illustrating an example of an FPGA board according to a first embodiment of this invention.
  • FIG. It is a sequence diagram which shows a 1st Example of this invention and shows an example of the process performed with a computer system. It is a sequence diagram which shows a 1st Example of this invention and shows an example of the process performed within an FPGA board.
  • FIG. 10 is a diagram illustrating a relationship between the output of the FPGA and the clock according to the second embodiment of this invention. It is a block diagram which shows the 3rd Example of this invention and shows an example of an FPGA board. It is a flowchart which shows a 3rd Example of this invention and shows an example of the process performed by CPU of an FPGA board.
  • FIG. 1 shows a first embodiment of the present invention and is a block diagram showing an example of a computer system.
  • the computer system of the present invention an example is shown in which transactions such as securities are processed in parallel on an FPGA board equipped with a large number of FPGAs (Field Programmable Gate Array).
  • FPGAs Field Programmable Gate Array
  • the transaction request (Order) received by the gateway device 12 is distributed to a plurality of nodes 10-1 to 10-n via the network 13.
  • Each of the nodes 10-1 to 10-n includes a primary matching engine (hereinafter referred to as ME) server 1-P and a secondary matching engine (ME in the figure) server 1-S.
  • ME primary matching engine
  • ME secondary matching engine
  • the primary ME server 1-P receives Order, executes predetermined arithmetic processing by an FPGA board described later, and returns the processing result to the gateway device 12.
  • the gateway device 12 transmits the processing result to the Order transmission source.
  • the gateway device 12 distributes the received Order to each of the nodes 10-1 to 10-n by a known or well-known method such as round robin or weighted round robin.
  • Order is, for example, a transaction request for securities, and a large amount of Order is processed in parallel by a plurality of nodes 10-1 to 10-n.
  • the FPGA boards of the nodes 10-1 to 10-n perform processing.
  • FIG. 2 is a block diagram showing an example of the ME server 1-P. Since the primary ME server 1-P and the secondary ME server 1-S have the same configuration, only the ME server 1-P will be described.
  • the ME server 1-P includes a CPU 2 that performs arithmetic processing, a memory 3 that stores data and programs, a NIC card (or network I / F) 6 that communicates with the network 13 (or the inter-server network 11), and Order.
  • the FPGA board 5 that executes the above process, and the PCI express 4 as an interconnect (or bus) that connects the CPU 2 to the FPGA board 5 and the NIC card 6.
  • the FPGA board 5 is connected to the PCI express 4 via the socket 41, and the NIC card 6 is connected to the PCI express 4 via the socket 42.
  • PCI express 4 is used as an interconnect for connecting the CPU 2 to the FPGA board 5 as an I / O device and the NIC card 6 is shown, a PCI bus or the like may be used.
  • FIG. 3 is a block diagram showing an example of the FPGA board 5.
  • the FPGA board 5 includes a data transfer FPGA 50 that transmits and receives data and commands to and from the PCI express 4, and redundant FPGAs (Dual Modular Redundancy FPGAs in the figure, DMR FPGAs in the figure) 51 that execute arithmetic processing including a plurality of FPGAs. -1 to 51-n, a third FPGA 52 that performs an operation when an error occurs in the redundant FPGAs 51-1 to 51-n, and the redundant FPGAs 51-1 to 51-n.
  • the circuit monitors the output to detect an error in the operation result, and when there is an error, switches between an error detection / recovery module 55 (Detect and Recovery Module in the figure) that functions as a control unit that repairs the operation result
  • the circuit includes selectors (Sel1 to Sel3 in the figure) 53, 54-1, and 54-2.
  • the selector 53 (Sel1) functions as a first selector that switches the input of the third FPGA 52, and the selector 54-1 (Sel2) functions as a second selector that switches the primary FPGA 500-1 to be input to the majority circuit 57.
  • the selector 54-2 (Sel3) functions as a third selector for switching the secondary FPGA 500-2 to be input to the majority circuit 57.
  • the data transfer FPGA 50 and the error detection / repair module 55 are configured by a flash memory type FPGA.
  • the redundant FPGAs 51-1 to 51-n and the third FPGA 52 are of SRAM type.
  • the generic name of the redundant FPGAs 51-1 to 51-n is denoted by reference numeral 51.
  • symbol which shows a generic name deletes a subscript, and displays it.
  • the data transfer FPGA 50 has a memory 60 for holding data to be transmitted and received, a signal line 40 connected to the PCI express 4 via the socket 41, a signal line 45 for transferring data and commands to each redundant FPGA 51, and an error A signal line 59 for receiving an output from the detection / repair module 55 and a signal line 58 for receiving a command from the error detection / repair module 55 are connected.
  • the data transfer FPGA 50 When the data transfer FPGA 50 receives data (Order data) from the PCI express 4, the data transfer FPGA 50 distributes the data to the plurality of redundant FPGAs 51. At this time, if there is no redundant FPGA 51 to which data is allocated, the data is distributed to the plurality of redundant FPGAs 51 by a known or well-known method such as queuing for holding the data in the memory 60.
  • the connection between the data transfer FPGA 50 and the redundant FPGA 51 is an example in which the connection is made through a PCI express signal line 45.
  • the redundant FPGA 51-1 includes a primary FPGA (FPG Pri in the figure) 500-1 serving as an active system and a secondary FPGA (FPGA Sec in the figure) 500-2 serving as a standby system.
  • the primary FPGA 500-1 is connected with a memory 61-1 for holding data, calculation results, and the like
  • the secondary FPGA 500-2 is connected with a memory 61-2 for holding data, calculation results, and the like.
  • the primary FPGA 500-1 functions as a first arithmetic unit
  • the secondary FPGA 500-2 functions as a second arithmetic unit
  • the third FPGA 52 functions as a third arithmetic unit
  • each FPGA has the same arithmetic processing Execute.
  • Order data is transmitted to the redundant FPGA 51-1 through the PCI express signal line 45.
  • the redundant FPGA 51-1 is connected with a signal line 58 for receiving a command from the error detection / repair module 55 and a signal line 46-1 for transmitting data to the selector 53.
  • the primary FPGA 500-1 and the secondary FPGA 500-2 each execute predetermined calculation processing on the data received from the data transfer FPGA 50, and output the calculation result to the comparison circuit 56-1. Note that the primary FPGA 500-1 and the secondary FPGA 500-2 respectively execute the same calculation process for one Order data.
  • the output side of the primary FPGA 500-1 is connected to the comparison circuit 56-1 of the error detection / repair module 55 through the signal line 70-1, and the output side of the secondary FPGA 500-2 is also in error through the signal line 71-1. It is connected to the comparison circuit 56-1 of the detection / repair module 55.
  • the redundant FPGAs 51-2 to 51-n are connected to the error detection / repair module 55 through the signal lines 70-2 to 70-n and 71-2 to 71-n. 56-2 to 56-n.
  • the third FPGA 52 is configured in the same manner as the primary FPGA 500-1, and includes a memory 62.
  • the third FPGA 52 is connected to the selector 53 on the input side, and receives Order data from the redundant FPGA 51 in which an error has occurred via the signal lines 46-1 to 46-n.
  • the output side of the third FPGA 52 is connected to a majority circuit (Vota in the figure) 57 of the error detection / repair module 55.
  • the error detection / repair module 55 includes the redundancy circuits selected by the comparison circuits 56-1 to 56-n corresponding to each redundant FPGA 51, the selector (second selector) 54-1 and the selector (third selector) 54-2.
  • the comparison circuit 56 When the comparison result of the two inputs from the redundant FPGA 51 (the two calculation results of the primary FPGA 500-1 and the secondary FPGA 500-2) matches, the comparison circuit 56 outputs the calculation result from the signal line 59 and outputs data. It transmits to transfer FPGA50.
  • the data transfer FPGA 50 outputs the calculation result from the error detection / repair module 55 to the PCI express 4.
  • the comparison circuit 56 compares the calculation result of the primary FPGA 500-1 of the redundant FPGA 51 with the calculation result of the secondary FPGA 500-2, and detects an error if the calculation results do not match.
  • the error detection / repair module 55 instructs the selectors 53, 54-1 and 54-2 to connect to the redundant FPGA 51 where the error has occurred via the signal line 58.
  • the selector 53 connects the redundant FPGA 51 and the third FPGA 52 in which the error has occurred
  • the selector 54-1 connects the signal line 70 of the redundant FPGA 51 in which the error has occurred and the majority circuit 57
  • the selector 54-2 The signal line 71 of the redundant FPGA 51 in which an error has occurred and the majority circuit 57 are connected.
  • the error detection / repair module 55 instructs the third FPGA 52 to transmit the data of the redundant FPGA 51 in which an error has occurred via the signal line 58. After that, the error detection / repair module 55 causes the third FPGA 52 and the redundant FPGA 51 in which the error has occurred to execute the calculation for the Order data again.
  • the second selector 54-1 is connected to the signal line 70 of the redundant FPGA 51 in which an error has occurred
  • the third selector 54-2 is connected to the signal line 71 of the redundant FPGA 51 in which an error has occurred. Therefore, the majority circuit 57 includes three processing operations of the third FPGA 52, the calculation result of the primary FPGA 500-1 of the redundant FPGA 51 in which an error has occurred, and the secondary FPGA 500-2 of the redundant FPGA 51 in which the error has also occurred. The calculation result is input.
  • the two FPGAs 500-1 and 500-2 of the redundant FPGA 51 in which the error has occurred and the arithmetic circuit of the FPGA tripled by the third FPGA 52 are temporarily stored. Is set automatically. Then, the majority circuit 57 compares the operation results of the temporary triple circuit, and performs the majority process of outputting the operation result with the largest number of matches to the signal line 59.
  • the data transfer FPGA 50 outputs the calculation result received from the error detection / repair module 55 (majority decision circuit 57) to the PCI express 4 as a calculation result for the Order data.
  • the CPU 2 and the NIC card 6 transmit the calculation result output from the FPGA board 5 to the PCI express 4 to the gateway device 12.
  • the error detection / repair module 55 notifies the data transfer FPGA 50 of the identifier of the redundant FPGA 51 in which an error has occurred.
  • the data transfer FPGA 50 notifies the CPU 2 of the identifier of the redundant FPGA 51 in which an error has occurred via the PCI express 4.
  • the error detection / repair module 55 may notify the data transfer FPGA 50 that an error has occurred.
  • the CPU 2 When the CPU 2 receives the identifier of the redundant FPGA 51 in which an error has occurred from the FPGA board 5 via the PCI express 4, the CPU 2 switches the device for processing the Order data from the primary ME server 1-P to the secondary ME server 1-S. .
  • the redundant FPGA 51 configured with the SRAM type FPGA, it is possible to switch to the secondary ME server 1-S after correcting the error using the third FPGA 52.
  • an error is detected using n redundant FPGAs 51 that are duplicated, and when an error occurs, two FPGAs 500-1, 500 of the third FPGA 52 and the redundant FPGA 51 in which the error has occurred are detected. -2 configures a temporary triple FPGA, and calculates again with the same data. Then, the three operation results of the triple FPGA are compared by the majority circuit 57, and the operation result with the most consistent number is output as the repaired operation result.
  • n redundant FPGAs 51 including two FPGAs 500-1 and 500-2 and one third FPGA 52 perform computation again with the triplexed FPGA only when an error occurs.
  • the operation result can be repaired.
  • only one third FPGA 52 is required to be tripled, so that the manufacturing cost of the FPGA board 5 can be suppressed.
  • the error detection / repair module 55 resets the selectors 53, 54-1, and 54-2, and the redundant FPGA 51, the third FPGA 52, and the majority circuit 57 in which an error has occurred. Disconnect from.
  • the error detection / repair module 55 functions as a control unit that performs error detection of the comparison circuit 56, control of the selectors 53, 54-1, and 54-2. It is not limited to.
  • a control circuit that controls the selectors 53, 54-1 and 54-2 based on the comparison result of the comparison circuit 56 may be provided independently.
  • FIG. 4 is a sequence diagram showing an example of processing performed in the computer system. In the illustrated example, an example in which an error has occurred in the redundant FPGA 51 is shown.
  • the gateway device 12 transfers the Order to a predetermined node 10 via the network 13 (S1). As described above, the gateway device 12 selects the node 10 as the transfer destination of Order by a load balancing method such as round robin. In the following description, an example is shown in which the gateway device 12 transfers Order to the node 10-1.
  • the primary ME server 1 -P receives Order, and the CPU 2 receives Order through the NIC card 6 and stores it in the memory 3.
  • the CPU 2 executes a predetermined program (hereinafter referred to as a node control program) for processing the received Order by the FPGA board 5.
  • the CPU 2 that executes the Order control program transfers the Order written in the memory 3 to the secondary ME server 1-S.
  • the secondary ME server 1-S also executes the node control program, and copies the Order received from the primary ME server 1-P to the memory 3. Then, the CPU 2 of the secondary ME server 1-S transmits a response (Ack in the figure) indicating that the Order copy has been saved to the primary ME server 1-P (S4).
  • the CPU 2 of the primary ME server 1-P that executes the node control program transmits the Order stored in the memory 3 to the FPGA board 5 (S3).
  • the CPU 2 of the primary ME server 1-P receives a response from the secondary ME server 1-S, it sends a calculation start command to the FPGA board 5 (S5).
  • the FPGA board 5 when the CPU 2 or Order is received, the Order is stored in the queue set in the memory 60 by the data transfer FPGA 50.
  • the data transfer FPGA 50 transmits Order to the redundant FPGA 51 corresponding to the queue to execute a predetermined calculation (S6).
  • the order includes a transaction request for securities
  • the redundant FPGA 51 of the FPGA board 5 executes a matching process for establishing a transaction for data included in the Order as a predetermined process.
  • ME indicates a matching engine indicating the function of the redundant FPGA 51.
  • the two computation results of the primary FPGA 500-1 and the secondary FPGA 500-2 of the redundant FPGA 51 are input to the comparison circuit 56, and an error occurs if the two computation results do not match (error 1 in the figure).
  • the error detection / repair module 55 of the FPGA board 5 connects the redundant FPGA 51 and the third FPGA 52 in which an error has occurred with the selectors 53, 54-1, and 54-2, and performs the operation again (S7). ).
  • the majority circuit 57 selects a calculation result from the output of the triple FPGA, and outputs the calculation result from the FPGA board 5 as a calculation result of correcting the error. (S8), and responds to the gateway device 12 via the network 13. Note that the calculation result output from the FPGA board 5 is received by the CPU 2 from the PCI express 4, and the calculation result is output from the NIC card 6.
  • the CPU 2 of the primary ME server 1-P that executes the node control program receives the identifier of the redundant FPGA 51 in which an error has occurred from the FPGA board 5, it instructs the standby secondary ME server 1-S to take over the processing. (S9).
  • the next received Order is processed by the secondary ME server 1-S and responds to the gateway device 12.
  • FIG. 5 is a sequence diagram illustrating an example of processing performed in the FPGA board 5 according to the first embodiment of this invention.
  • the data transfer FPGA 50 receives the order (S11).
  • the data transfer FPGA 50 transmits the data included in the Order to a predetermined redundancy FPGA 51, and the primary FPGA 500-1 and the secondary FPGA 500-2 each calculate the received data (S12). , S13).
  • the calculation result (Re in the figure) of the primary FPGA 500-1 and the secondary FPGA 500-2 is determined by the comparison circuit 56 of the error detection / repair module 55 to determine whether or not they match (S14). If they do not match, an error occurs, and the error detection / repair module 55 switches the selectors 53, 54-1, 54-2, and, as described above, the primary and secondary of the redundant FPGA 51 in which the error has occurred.
  • the FPGA and the third FPGA 52 are tripled and connected to the majority circuit 57 (S15).
  • the error detection / repair module 55 instructs the redundant FPGA 51 in which an error has occurred to transmit the current data to the third FPGA 52.
  • the redundant FPGA 51 in which the error has occurred transmits the currently held data to the third FPGA 52 (S16).
  • the error detection / repair module 55 instructs the triple redundant FPGA 51 and the third FPGA 52 to execute an operation with the currently held data (S17).
  • the redundant FPGA 51 in which an error has occurred the primary and secondary FPGAs 500-1 and 500-2 calculate the previous data again, and the third FPGA 52 calculates the data copied from the redundant FPGA 51. Then, the operation result of these tripled FPGAs is input to the majority circuit 57 (S18).
  • the majority circuit 57 executes a majority vote on the three input operation results, and outputs the operation result with the most consistent number (S19).
  • the output calculation result is transferred to the data transfer FPGA 50 via the signal line 59 shown in FIG. 3, and is output to the PCI express 4 (S20).
  • the n-redundant FPGA 51 including the two FPGAs 500-1 and 500-2 and the one third FPGA 52 constitute the FPGA board 5, and the triple FPGA only when an error occurs. It is possible to restore the calculation result by performing the calculation again, and to improve the reliability while suppressing the manufacturing cost of the FPGA board 5.
  • the communication between the FPGA board 5 of the primary ME server 1-P and the secondary ME server 1-S is transmitted and received from the NIC card 6 mainly by the CPU 2. It is not limited.
  • the data transfer FPGA 50 of the FPGA board 5 may notify the secondary ME server 1-S of data transfer or processing takeover by remote DMA.
  • the majority circuit 57 can perform majority processing on the three calculation results, and can identify an FPGA having a different calculation result as the FPGA in which an error has occurred.
  • FIG. 6A is a block diagram illustrating an example of the FPGA 500 according to the second embodiment.
  • FIG. 6A shows the configuration of the primary FPGA 500-1, but the secondary FPGA 500-2 and the third FPGA 52 have the same configuration.
  • the primary FPGA 500-1 includes a PCI express interface 501 connected to the PCI express 4, a controller 502, an arithmetic module A (503A), an arithmetic module B (503B), an output of the arithmetic module A, and an output of the arithmetic module B as a clock signal CLK.
  • the main selector 504 is configured to switch the output accordingly, and the memory interface 505 that controls the memory 61-1 is mainly configured.
  • the arithmetic module A and the arithmetic module B are obtained by dividing the arithmetic unit of the primary FPGA 500-1 of the first embodiment.
  • the arithmetic module A performs processing from receiving data from the data line 510 (DIN in the figure) of the PCI express interface 501 until writing to the memory 61-1 via the memory interface 505.
  • the calculation module B reads data from the memory 61-1 via the memory interface 505, executes a predetermined matching process, and outputs a calculation result.
  • the matching process is the same as in the first embodiment, and the calculation result is the same as in the first embodiment.
  • the internal selector 504 switches between the output of the arithmetic module A and the output of the arithmetic module B in accordance with a command from the controller 502 and outputs the result to the signal line 70-1. For this reason, the controller 502 is connected with a control line 511 (CIN in the figure) of the PCI express interface 501 and a clock signal line 520 for inputting an external clock signal CLK.
  • the external clock signal CLK for example, a signal generated by the CPU 2 can be used.
  • the relationship between the clock signal CLK and the output of the internal selector 504 is shown in FIG. 6B.
  • the clock signal CLK is “0” and the internal selector 504 selects the output of the arithmetic module A
  • the clock signal CLK is “1” and the internal selector 504 selects the output of the arithmetic module B.
  • the external clock signal CLK is input to the primary FPGA 500-1, the secondary FPGA 500-2, and the third FPGA 52 of the redundant FPGAs 51-1 to 51-n shown in FIG. Then, after an error has occurred in the redundant FPGA 51, it is tripled with the third FPGA 52, and the majority circuit 57 receives the calculation results of the three FPGAs.
  • the clock signal CLK is “1”, and the majority circuit 57 determines whether or not the calculation results of the calculation module B match. Since all the operation results do not match in the redundant FPGA 51 in which an error has occurred, the error detection / repair module 55 can specify whether the FPGA that has output a different operation result is the primary FPGA 500-1 or the secondary FPGA 500-2. .
  • the majority circuit 57 determines whether or not the calculation results of the calculation module A match.
  • the error detection / recovery module 55 can determine that an error has occurred in the FPGA calculation module B that has output a different calculation result in the first determination by the majority circuit 57.
  • the error detection / recovery module 55 indicates that an error has occurred in the calculation module A of the FPGA that output a different calculation result in the determination of the majority circuit 57 this time (second time). Can be identified.
  • the FPGA configuring the redundant FPGA 51 is divided into a plurality of parts, and a plurality of operation results of the divided operation units are switched by the internal selector 504 and output.
  • the error detection / repair module 55 can specify the part (arithmetic unit) where the error has occurred in addition to the FPGA where the error has occurred.
  • the error detection / repair module 55 shows an example of specifying an FPGA in which an error has occurred (one of the primary FPGA 500-1 or the secondary FPGA 500-2) and specifying a site (arithmetic unit) in which the error has occurred
  • the part where the error occurred in the data transfer FPGA 50 or the CPU 2 may be specified.
  • FIG. 7 and 8 show the third embodiment.
  • FIG. 7 is a block diagram showing an example of the FPGA board 5.
  • FIG. 8 is a flowchart illustrating an example of processing performed by the CPU of the FPGA board 5.
  • n redundant FPGAs 51 and one third FPGA 52 are combined, and when the error occurs, the redundant FPGA 51 and the third FPGA 52 are combined to be tripled.
  • the third embodiment shows an example in which one of the n redundant FPGAs 51-1 to 51-n is used as the third FPGA.
  • the redundant FPGA 51 includes a primary FPGA 500-1 and a secondary FPGA 500-2, and the outputs of the FPGAs 500-1 and 500-2 are connected to the comparison circuit 56 via signal lines 70 and 71, respectively.
  • the outputs of the FPGAs 500-1 and 500-2 are connected from the signal lines 70 and 71 to the majority circuit 57 via the selectors 54-1 and 54-2.
  • the local CPU 80 selects any one of the redundant FPGAs 51-1 to 51-n as the third FPGA.
  • one redundant FPGA 51 includes two FPGAs 500-1 and 500-2, the local CPU 80 selects one of them as the third FPGA.
  • the local CPU 80 selects the redundant FPGA 51 that is the third FPGA in round robin, and selects the primary FPGA 500-1 of the redundant FPGA 51 as the third FPGA.
  • the error detection / repair module 55 is obtained by omitting the control of the selectors 54-1, 545-2 from the configuration of the first embodiment.
  • the error detection / repair module 55 notifies the local CPU 80 of the identifier of the redundant FPGA 51 in which the mismatch error has occurred via the signal line 58.
  • the local CPU 80 causes the selectors 54-1 and 54-2 to connect the signal lines 70 and 71 of the redundant FPGA 51 in which an error has occurred and the signal line 70 of the redundant FPGA 51 functioning as the third FPGA to the majority circuit 57. Command. Then, the local CPU 80 copies the current data from the redundant FPGA 51 in which the error has occurred to the third FPGA. Thereafter, the local CPU 80 instructs the redundant FPGA 51 and the third FPGA in which an error has occurred to execute the calculation.
  • the repaired calculation result is output from the majority circuit 57 of the error detection / repair module 55. Thereafter, the local CPU 80 notifies the secondary ME server 1-S of the takeover of processing via the data transfer FPGA 50.
  • the flowchart of FIG. 8 is executed in a state where the activation of the FPGA board 5 is completed and the third FPGA is selected.
  • the local CPU 80 monitors the signal line 58 and waits until the error detection / repair module 55 notifies the error (S31).
  • the local CPU 80 receives the identifier from the signal line 58 and identifies the redundant FPGA 51 in which the error has occurred (S32).
  • the local CPU 80 causes the selectors 54-1 and 54-2 to connect the signal lines 70 and 71 of the redundant FPGA 51 in which an error has occurred and the signal line 70 of the redundant FPGA 51 functioning as the third FPGA to the majority circuit 57.
  • Command (S33, S34).
  • the local CPU 80 copies the current data from the redundant FPGA 51 in which the error has occurred to the third FPGA (S35).
  • the local CPU 80 instructs the redundant FPGA 51 and the third FPGA in which an error has occurred to execute the calculation (S36).
  • the primary and secondary FPGAs 500-1 and 500-2 calculate the previous data again, and the third FPGA calculates the data copied from the redundant FPGA 51. Then, the operation result of the triple FPGA is input to the majority circuit 57.
  • the majority circuit 57 executes a majority vote on the three input operation results, and outputs the operation result having the most matched number to the signal line 59 (S37).
  • the local CPU 80 instructs the standby secondary ME server 1-S to take over the processing (S38).
  • one of the n redundant FPGAs 51 including the two FPGAs 500-1 and 500-2 is set as the third FPGA, and, as in the first embodiment, the triplicate is performed only when an error occurs. It is possible to perform the calculation again with the converted FPGA and restore the calculation result, and it is possible to improve the reliability while suppressing the manufacturing cost of the FPGA board 5.
  • the third FPGA can be selected from the n redundant FPGAs 51, when an error occurs in the third FPGA, the processing is taken over to the secondary FPGA 500-2 or another redundant FPGA 51. The redundancy of the third FPGA can be ensured.
  • a plurality of redundant FPGAs 51 including two FPGAs 500-1 and 500-2 may be arranged, so that semiconductor design and manufacture can be facilitated.
  • the present invention is not limited to the above-described embodiments, and includes various modifications.
  • the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described.

Abstract

Provided is a computation circuit, comprising: a redundant computation unit, further comprising a first computation unit and a second computation unit, which computes on inputted data in parallel; a comparison circuit which compares the computation result of the first computation unit and the computation result of the second computation unit; a third computation unit which computes the data of the redundant computation unit when the comparison result of the computation unit is not a match; and selectors which connect the output of the first computation unit, the output of the second computation unit, and the output of the third computation unit to a voter circuit when the comparison result of the comparison circuit is not a match.

Description

演算回路及び計算機Arithmetic circuit and computer
　本発明は、冗長化された演算回路の信頼性を向上させる技術に関する。 The present invention relates to a technique for improving the reliability of a redundant arithmetic circuit.
　少量生産のＩＴ機器では開発コストの高いＡＳＩＣ（Application Specific Integrated Circuit）に代わって、カスタマイズを低コストで実現できるＦＰＧＡ（Field Programmable Gate Array）を演算ユニットとして利用することが望まれている。 For small-volume IT devices, it is desired to use FPGA (Field Programmable Gate Array) that can be customized at low cost instead of ASIC (Application Specific Integrated Circuit), which has a high development cost.
　ＳＲＡＭ型のＦＰＧＡでは、内部構成を定義したビットストリームデータをＣＲＡＭ（Ｃｏｎｆｉｇｕｒａｔｉｏｎ　ＲＡＭ）にロードすることで、ユーザが定義した内部構成を実現する。ＣＲＡＭにロードされたビットストリームデータデータの各ビットが、ユーザの定義による回路構成を示す。 The SRAM type FPGA implements the user-defined internal configuration by loading bitstream data defining the internal configuration into a CRAM (Configuration RAM). Each bit of the bit stream data data loaded into the CRAM indicates a circuit configuration defined by the user.
　近年、半導体プロセスの微細化に伴って、ＳＲＡＭ型のＦＰＧＡでは、集積度が向上している。一方、半導体プロセスの微細化が進むにつれて、環境放射線（地上における宇宙線中性子やα線）によるＣＲＡＭ（ＳＲＡＭ）のビットエラーが発生する傾向があった。 In recent years, with the miniaturization of semiconductor processes, the integration degree of SRAM type FPGAs has been improved. On the other hand, as semiconductor processes have become finer, bit errors in CRAM (SRAM) due to environmental radiation (cosmic neutrons and alpha rays on the ground) tend to occur.
　１ビットエラーを回復するには、ＥＣＣ等の既存の手法で回復可能であるが、隣接する２ビットでエラーが発生した場合には、ＦＰＧＡの多重化（３重化など）で対処する必要がある。冗長性を確保するために３重化を用いる技術としては、例えば、特許文献１や特許文献２が知られている。 To recover a 1-bit error, it is possible to recover using an existing method such as ECC. However, when an error occurs in 2 adjacent bits, it is necessary to deal with multiplexing of FPGA (such as triple). is there. For example, Patent Literature 1 and Patent Literature 2 are known as techniques that use triplexing to ensure redundancy.
米国特許第６，３８９，０４１号US Pat. No. 6,389,041 特開２０１３－４６１８１号公報JP 2013-46181 A
　しかしながら、上記ＦＰＧＡの３重化によって冗長性を確保できるものの、演算回路または演算装置のコストが増大するという問題があった。特に、多数のＦＰＧＡで並列的に演算処理を行う演算装置では、ひとつの演算処理に３つのＦＰＧＡを使用するため、並列化の数が多くなるにつれて演算回路または演算装置のコストが過大になるという問題があった。 However, although redundancy can be ensured by triple the FPGA, there is a problem that the cost of the arithmetic circuit or the arithmetic unit increases. In particular, in an arithmetic device that performs arithmetic processing in parallel with a large number of FPGAs, three FPGAs are used for one arithmetic processing, so that the cost of the arithmetic circuit or arithmetic device increases as the number of parallelization increases. There was a problem.
　本発明は、入力されたデータを並列して演算する第１の演算ユニットと第２の演算ユニットを含む冗長化演算ユニットと、前記第１の演算ユニットの演算結果と、前記第２の演算ユニットの演算結果とを比較する比較回路と、前記比較回路の比較結果が一致しないときに、前記冗長化演算ユニットのデータを演算する第３の演算ユニットと、前記比較回路の比較結果が一致しないときに、前記第１の演算ユニットの出力と、前記第２の演算ユニットの出力と、前記第３の演算ユニットの出力とを多数決回路に接続するセレクタと、を備える。 The present invention provides a redundant arithmetic unit including a first arithmetic unit and a second arithmetic unit that operate on input data in parallel, an arithmetic result of the first arithmetic unit, and the second arithmetic unit. When the comparison result of the comparison circuit and the comparison result of the comparison circuit do not match, the comparison result of the comparison circuit of the third calculation unit that calculates the data of the redundant calculation unit does not match And a selector for connecting the output of the first arithmetic unit, the output of the second arithmetic unit, and the output of the third arithmetic unit to a majority circuit.
　本発明によれば、２つの演算ユニットを含む冗長化演算ユニットと、１つの第３の演算ユニットを有する演算回路で、エラーが発生したときのみ冗長化演算ユニットと第３の演算ユニットで３重化した演算ユニットで演算を行い、多数決回路で多数決処理を行うことで演算結果の修復が可能となり、演算回路の製造コストを抑制しながら信頼性を向上させることが可能となるのである。 According to the present invention, a redundant arithmetic unit including two arithmetic units and an arithmetic circuit having one third arithmetic unit, the redundant arithmetic unit and the third arithmetic unit are tripled only when an error occurs. It is possible to restore the operation result by performing the operation with the converted operation unit and performing the majority process with the majority circuit, and it is possible to improve the reliability while suppressing the manufacturing cost of the operation circuit.
本発明の第１の実施例を示し、計算機システムの一例を示すブロック図である。1 is a block diagram illustrating an example of a computer system according to a first embodiment of this invention. FIG. 本発明の第１の実施例を示し、マッチングエンジン（ＭＥ）サーバの一例を示すブロック図である。It is a block diagram which shows the 1st Example of this invention and shows an example of a matching engine (ME) server. 本発明の第１の実施例を示し、ＦＰＧＡボードの一例を示すブロック図である。1 is a block diagram illustrating an example of an FPGA board according to a first embodiment of this invention. FIG. 本発明の第１の実施例を示し、計算機システムで行われる処理の一例を示すシーケンス図である。It is a sequence diagram which shows a 1st Example of this invention and shows an example of the process performed with a computer system. 本発明の第１の実施例を示し、ＦＰＧＡボード内で行われる処理の一例を示すシーケンス図である。It is a sequence diagram which shows a 1st Example of this invention and shows an example of the process performed within an FPGA board. 本発明の第２の実施例を示し、ＦＰＧＡの一例を示すブロック図である。It is a block diagram which shows the 2nd Example of this invention and shows an example of FPGA. 本発明の第２の実施例を示し、ＦＰＧＡの出力とクロックの関係を示す図である。FIG. 10 is a diagram illustrating a relationship between the output of the FPGA and the clock according to the second embodiment of this invention. 本発明の第３の実施例を示し、ＦＰＧＡボードの一例を示すブロック図である。It is a block diagram which shows the 3rd Example of this invention and shows an example of an FPGA board. 本発明の第３の実施例を示し、ＦＰＧＡボードのＣＰＵで行われる処理の一例を示すフローチャートである。It is a flowchart which shows a 3rd Example of this invention and shows an example of the process performed by CPU of an FPGA board.
　以下、本発明の一実施形態について添付図面を用いて説明する。 Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.
　図１は、本発明の実施例１を示し、計算機システムの一例を示すブロック図である。本発明の計算機システムでは、証券等の取引を多数のＦＰＧＡ（Field Programmable Gate Array）を搭載したＦＰＧＡボードで並列的に処理する一例を示す。 FIG. 1 shows a first embodiment of the present invention and is a block diagram showing an example of a computer system. In the computer system of the present invention, an example is shown in which transactions such as securities are processed in parallel on an FPGA board equipped with a large number of FPGAs (Field Programmable Gate Array).
　ゲートウェイ装置１２で受け付けた取引要求（Ｏｒｄｅｒ）は、ネットワーク１３を介して複数のノード１０－１～１０－ｎに分配される。各ノード１０－１～１０－ｎは、プライマリのマッチングエンジン（以下、ＭＥとする）サーバ１－Ｐと、セカンダリのマッチングエンジン（図中ＭＥ）サーバ１－Ｓで構成される。 The transaction request (Order) received by the gateway device 12 is distributed to a plurality of nodes 10-1 to 10-n via the network 13. Each of the nodes 10-1 to 10-n includes a primary matching engine (hereinafter referred to as ME) server 1-P and a secondary matching engine (ME in the figure) server 1-S.
　ノードが正常な時には、プライマリのＭＥサーバ１－ＰがＯｒｄｅｒを受信して、後述するＦＰＧＡボードで所定の演算処理を実行し、処理結果をゲートウェイ装置１２に応答する。ゲートウェイ装置１２はＯｒｄｅｒの送信元に処理結果を送信する。プライマリ（現用系）のＭＥサーバ１－Ｐに障害が発生すると、セカンダリ（待機系）のＭＥサーバ１－Ｓに処理が引き継がれる。 When the node is normal, the primary ME server 1-P receives Order, executes predetermined arithmetic processing by an FPGA board described later, and returns the processing result to the gateway device 12. The gateway device 12 transmits the processing result to the Order transmission source. When a failure occurs in the primary (active) ME server 1-P, the processing is taken over by the secondary (standby) ME server 1-S.
　なお、プライマリのＭＥサーバ１－ＰとセカンダリのＭＥサーバ１－Ｓは、サーバ間ネットワーク１１で接続される。また、サーバ間ネットワーク１１とネットワーク１３は、同一のネットワークであってもよい。また、ゲートウェイ装置１２は、受信したＯｒｄｅｒをラウンドロビンや重み付きラウンドロビンなどの公知または周知の手法により各ノード１０－１～１０－ｎに分配する。なお、Ｏｒｄｅｒは、例えば、証券の取引要求であり、大量のＯｒｄｅｒが、複数のノード１０－１～１０－ｎで並列的に処理される。Ｏｒｄｅｒの処理については各ノード１０－１～１０－ｎのＦＰＧＡボードが処理を実施する。 Note that the primary ME server 1-P and the secondary ME server 1-S are connected by an inter-server network 11. Further, the inter-server network 11 and the network 13 may be the same network. The gateway device 12 distributes the received Order to each of the nodes 10-1 to 10-n by a known or well-known method such as round robin or weighted round robin. Order is, for example, a transaction request for securities, and a large amount of Order is processed in parallel by a plurality of nodes 10-1 to 10-n. For the order processing, the FPGA boards of the nodes 10-1 to 10-n perform processing.
　図２は、ＭＥサーバ１－Ｐの一例を示すブロック図である。プライマリのＭＥサーバ１－ＰとセカンダリのＭＥサーバ１－Ｓは同一の構成であるので、ＭＥサーバ１－Ｐのみについて説明する。 FIG. 2 is a block diagram showing an example of the ME server 1-P. Since the primary ME server 1-P and the secondary ME server 1-S have the same configuration, only the ME server 1-P will be described.
　ＭＥサーバ１－Ｐは、演算処理を行うＣＰＵ２と、データやプログラムを保持するメモリ３と、ネットワーク１３（またはサーバ間ネットワーク１１）と通信を行うＮＩＣカード（またはネットワークＩ／Ｆ）６と、Ｏｒｄｅｒの処理を実行するＦＰＧＡボード５と、ＣＰＵ２とＦＰＧＡボード５及びＮＩＣカード６とを接続するインターコネクト（またはバス）としてのＰＣＩｅｘｐｒｅｓｓ４とを備える。 The ME server 1-P includes a CPU 2 that performs arithmetic processing, a memory 3 that stores data and programs, a NIC card (or network I / F) 6 that communicates with the network 13 (or the inter-server network 11), and Order. The FPGA board 5 that executes the above process, and the PCI express 4 as an interconnect (or bus) that connects the CPU 2 to the FPGA board 5 and the NIC card 6.
　なお、図中ＦＰＧＡボード５はソケット４１を介してＰＣＩｅｘｐｒｅｓｓ４に接続され、ＮＩＣカード６はソケット４２を介してＰＣＩｅｘｐｒｅｓｓ４に接続される。また、ＣＰＵ２とＩ／ＯデバイスとしてのＦＰＧＡボード５、ＮＩＣカード６を接続するインターコネクトとしてＰＣＩｅｘｐｒｅｓｓ４を採用した例を示したが、ＰＣＩバスなどであってもよい。 In the figure, the FPGA board 5 is connected to the PCI express 4 via the socket 41, and the NIC card 6 is connected to the PCI express 4 via the socket 42. Further, although an example in which PCI express 4 is used as an interconnect for connecting the CPU 2 to the FPGA board 5 as an I / O device and the NIC card 6 is shown, a PCI bus or the like may be used.
　図３は、ＦＰＧＡボード５の一例を示すブロック図である。ＦＰＧＡボード５は、ＰＣＩｅｘｐｒｅｓｓ４との間でデータやコマンドの送受信を行うデータ転送ＦＰＧＡ５０と、複数のＦＰＧＡを含んで演算処理を実行する冗長化ＦＰＧＡ（図中Dual Modular Redundancy FPGAs、図中ＤＭＲ　ＦＰＧＡｓ）５１－１～５１－ｎと、冗長化ＦＰＧＡ５１－１～５１－ｎでエラーが発生したときに演算を行う第３のＦＰＧＡ（図中ＦＰＧＡ　Ｔｈｉｒｄ）５２と、冗長化ＦＰＧＡ５１－１～５１－ｎの出力を監視して演算結果のエラーを検出し、エラーがあったときには演算結果を修復する制御部として機能するエラー検知・修復モジュール（図中Detect and Recovery Module）５５と、データの入出力を切り替えるセレクタ（図中Ｓｅｌ１～Ｓｅｌ３）５３、５４－１、５４－２を含む回路で構成される。 FIG. 3 is a block diagram showing an example of the FPGA board 5. The FPGA board 5 includes a data transfer FPGA 50 that transmits and receives data and commands to and from the PCI express 4, and redundant FPGAs (Dual Modular Redundancy FPGAs in the figure, DMR FPGAs in the figure) 51 that execute arithmetic processing including a plurality of FPGAs. -1 to 51-n, a third FPGA 52 that performs an operation when an error occurs in the redundant FPGAs 51-1 to 51-n, and the redundant FPGAs 51-1 to 51-n. Monitors the output to detect an error in the operation result, and when there is an error, switches between an error detection / recovery module 55 (Detect and Recovery Module in the figure) that functions as a control unit that repairs the operation result The circuit includes selectors (Sel1 to Sel3 in the figure) 53, 54-1, and 54-2.
　なお、セレクタ５３（Ｓｅｌ１）は第３のＦＰＧＡ５２の入力を切り替える第１のセレクタとして機能し、セレクタ５４－１（Ｓｅｌ２）は多数決回路５７へ入力するプライマリＦＰＧＡ５００－１を切り替える第２のセレクタとして機能し、セレクタ５４－２（Ｓｅｌ３）は多数決回路５７へ入力するセカンダリＦＰＧＡ５００－２を切り替える第３のセレクタとして機能する。 The selector 53 (Sel1) functions as a first selector that switches the input of the third FPGA 52, and the selector 54-1 (Sel2) functions as a second selector that switches the primary FPGA 500-1 to be input to the majority circuit 57. The selector 54-2 (Sel3) functions as a third selector for switching the secondary FPGA 500-2 to be input to the majority circuit 57.
　本実施例では、データ転送ＦＰＧＡ５０と、エラー検知・修復モジュール５５はフラッシュメモリ型のＦＰＧＡで構成される。一方、冗長化ＦＰＧＡ５１－１～５１－ｎと、第３のＦＰＧＡ５２はＳＲＡＭ型で構成される。なお、以下では冗長化ＦＰＧＡ５１－１～５１－ｎの総称を符号５１で表す。なお、他の構成要素についても、総称を示す符号は添え字を削除して表示する。 In this embodiment, the data transfer FPGA 50 and the error detection / repair module 55 are configured by a flash memory type FPGA. On the other hand, the redundant FPGAs 51-1 to 51-n and the third FPGA 52 are of SRAM type. In the following, the generic name of the redundant FPGAs 51-1 to 51-n is denoted by reference numeral 51. In addition, also about another component, the code | symbol which shows a generic name deletes a subscript, and displays it.
　データ転送ＦＰＧＡ５０は、送受信するデータなどを保持するメモリ６０を有し、ソケット４１を介してＰＣＩｅｘｐｒｅｓｓ４に接続される信号線４０と、データやコマンドを各冗長化ＦＰＧＡ５１に転送する信号線４５と、エラー検知・修復モジュール５５からの出力を受け付ける信号線５９と、エラー検知・修復モジュール５５からの指令等を受け付ける信号線５８とが接続される。 The data transfer FPGA 50 has a memory 60 for holding data to be transmitted and received, a signal line 40 connected to the PCI express 4 via the socket 41, a signal line 45 for transferring data and commands to each redundant FPGA 51, and an error A signal line 59 for receiving an output from the detection / repair module 55 and a signal line 58 for receiving a command from the error detection / repair module 55 are connected.
　データ転送ＦＰＧＡ５０は、ＰＣＩｅｘｐｒｅｓｓ４からデータ（Ｏｒｄｅｒのデータ）を受け付けると、複数の冗長化ＦＰＧＡ５１にデータを分配する。この際、データを割り当てる冗長化ＦＰＧＡ５１が存在しない場合には、データをメモリ６０に保持するキューイングなどの公知または周知の手法により、データを複数の冗長化ＦＰＧＡ５１に分配する。なお、本実施例では、データ転送ＦＰＧＡ５０と冗長化ＦＰＧＡ５１の接続は、ＰＣＩｅｘｐｒｅｓｓの信号線４５で接続する例を示す。 When the data transfer FPGA 50 receives data (Order data) from the PCI express 4, the data transfer FPGA 50 distributes the data to the plurality of redundant FPGAs 51. At this time, if there is no redundant FPGA 51 to which data is allocated, the data is distributed to the plurality of redundant FPGAs 51 by a known or well-known method such as queuing for holding the data in the memory 60. In the present embodiment, the connection between the data transfer FPGA 50 and the redundant FPGA 51 is an example in which the connection is made through a PCI express signal line 45.
　演算を実行する冗長化ＦＰＧＡ５１－１～５１－ｎは、同一の構成であるので、冗長化ＦＰＧＡ５１－１についてのみ説明する。 Since the redundant FPGAs 51-1 to 51-n that execute the operation have the same configuration, only the redundant FPGA 51-1 will be described.
　冗長化ＦＰＧＡ５１－１は、現用系となるプライマリＦＰＧＡ（図中ＦＰＧＡ　Ｐｒｉ）５００－１と、待機系となるセカンダリＦＰＧＡ（図中ＦＰＧＡ　Ｓｅｃ）５００－２を含む。プライマリＦＰＧＡ５００－１にはデータや演算結果等を保持するメモリ６１－１が接続され、セカンダリＦＰＧＡ５００－２にもデータや演算結果等を保持するメモリ６１－２が接続される。プライマリＦＰＧＡ５００－１は第１の演算ユニットとして機能し、セカンダリＦＰＧＡ５００－２は第２の演算ユニットとして機能し、第３のＦＰＧＡ５２は第３の演算ユニットとして機能し、各ＦＰＧＡは、同一の演算処理を実行する。 The redundant FPGA 51-1 includes a primary FPGA (FPG Pri in the figure) 500-1 serving as an active system and a secondary FPGA (FPGA Sec in the figure) 500-2 serving as a standby system. The primary FPGA 500-1 is connected with a memory 61-1 for holding data, calculation results, and the like, and the secondary FPGA 500-2 is connected with a memory 61-2 for holding data, calculation results, and the like. The primary FPGA 500-1 functions as a first arithmetic unit, the secondary FPGA 500-2 functions as a second arithmetic unit, the third FPGA 52 functions as a third arithmetic unit, and each FPGA has the same arithmetic processing Execute.
　冗長化ＦＰＧＡ５１－１には、ＰＣＩｅｘｐｒｅｓｓの信号線４５を介してＯｒｄｅｒのデータが送信される。また、冗長化ＦＰＧＡ５１－１には、エラー検知・修復モジュール５５からの指令等を受け付ける信号線５８と、セレクタ５３へデータを送信する信号線４６－１が接続される。 Order data is transmitted to the redundant FPGA 51-1 through the PCI express signal line 45. The redundant FPGA 51-1 is connected with a signal line 58 for receiving a command from the error detection / repair module 55 and a signal line 46-1 for transmitting data to the selector 53.
　冗長化ＦＰＧＡ５１－１では、データ転送ＦＰＧＡ５０から受け付けたデータについて、プライマリＦＰＧＡ５００－１とセカンダリＦＰＧＡ５００－２がそれぞれ所定の演算処理を実行し、演算結果を比較回路５６－１へ出力する。なお、プライマリＦＰＧＡ５００－１とセカンダリＦＰＧＡ５００－２は、ひとつのＯｒｄｅｒのデータについて同一の演算処理をそれぞれ実行する。 In the redundant FPGA 51-1, the primary FPGA 500-1 and the secondary FPGA 500-2 each execute predetermined calculation processing on the data received from the data transfer FPGA 50, and output the calculation result to the comparison circuit 56-1. Note that the primary FPGA 500-1 and the secondary FPGA 500-2 respectively execute the same calculation process for one Order data.
　プライマリＦＰＧＡ５００－１の出力側は信号線７０－１を介してエラー検知・修復モジュール５５の比較回路５６－１に接続され、セカンダリＦＰＧＡ５００－２の出力側は信号線７１－１を介して同じくエラー検知・修復モジュール５５の比較回路５６－１に接続される。 The output side of the primary FPGA 500-1 is connected to the comparison circuit 56-1 of the error detection / repair module 55 through the signal line 70-1, and the output side of the secondary FPGA 500-2 is also in error through the signal line 71-1. It is connected to the comparison circuit 56-1 of the detection / repair module 55.
　他の冗長化ＦＰＧＡ５１も同様であり、冗長化ＦＰＧＡ５１－２～５１－ｎは、信号線７０－２～７０－ｎと７１－２～７１－ｎを介してエラー検知・修復モジュール５５の比較回路５６－２～５６－ｎへ接続される。 The same applies to the other redundant FPGAs 51. The redundant FPGAs 51-2 to 51-n are connected to the error detection / repair module 55 through the signal lines 70-2 to 70-n and 71-2 to 71-n. 56-2 to 56-n.
　また、第３のＦＰＧＡ５２は、プライマリＦＰＧＡ５００－１と同様に構成され、メモリ６２を備える。第３のＦＰＧＡ５２は、入力側をセレクタ５３に接続されており、エラーが発生した冗長化ＦＰＧＡ５１から信号線４６－１～４６－ｎを介してＯｒｄｅｒのデータを受信する。そして、第３のＦＰＧＡ５２の出力側はエラー検知・修復モジュール５５の多数決回路（図中Ｖｏｔｅｒ）５７に接続される。 The third FPGA 52 is configured in the same manner as the primary FPGA 500-1, and includes a memory 62. The third FPGA 52 is connected to the selector 53 on the input side, and receives Order data from the redundant FPGA 51 in which an error has occurred via the signal lines 46-1 to 46-n. The output side of the third FPGA 52 is connected to a majority circuit (Vota in the figure) 57 of the error detection / repair module 55.
　エラー検知・修復モジュール５５は、各冗長化ＦＰＧＡ５１に対応する比較回路５６－１～５６－ｎと、セレクタ（第２セレクタ）５４－１とセレクタ（第３セレクタ）５４－２で選択された冗長化ＦＰＧＡ５１のプライマリＦＰＧＡ５００－１とセカンダリＦＰＧＡ５００－２の出力と、第３のＦＰＧＡ５２の出力の多数決を演算する多数決回路５７を含む。 The error detection / repair module 55 includes the redundancy circuits selected by the comparison circuits 56-1 to 56-n corresponding to each redundant FPGA 51, the selector (second selector) 54-1 and the selector (third selector) 54-2. A majority circuit 57 for calculating the majority of the outputs of the primary FPGA 500-1 and the secondary FPGA 500-2 of the generalized FPGA 51 and the output of the third FPGA 52.
　比較回路５６は、冗長化ＦＰＧＡ５１からの２つの入力（プライマリＦＰＧＡ５００－１とセカンダリＦＰＧＡ５００－２の２つの演算結果）を比較した結果が一致した場合、この演算結果を信号線５９から出力してデータ転送ＦＰＧＡ５０に送信する。データ転送ＦＰＧＡ５０は、エラー検知・修復モジュール５５からの演算結果をＰＣＩｅｘｐｒｅｓｓ４に出力する。 When the comparison result of the two inputs from the redundant FPGA 51 (the two calculation results of the primary FPGA 500-1 and the secondary FPGA 500-2) matches, the comparison circuit 56 outputs the calculation result from the signal line 59 and outputs data. It transmits to transfer FPGA50. The data transfer FPGA 50 outputs the calculation result from the error detection / repair module 55 to the PCI express 4.
　比較回路５６は、冗長化ＦＰＧＡ５１のプライマリＦＰＧＡ５００－１の演算結果と、セカンダリＦＰＧＡ５００－２の演算結果を比較して、演算結果が一致しない場合はエラーとして検知する。エラー検知・修復モジュール５５は、比較回路５６がエラーを検知すると、信号線５８を介してセレクタ５３、５４－１、５４－２に対して、エラーが発生した冗長化ＦＰＧＡ５１に接続するよう指令する。セレクタ５３はエラーが発生した冗長化ＦＰＧＡ５１と第３のＦＰＧＡ５２を接続し、セレクタ５４－１は、エラーが発生した冗長化ＦＰＧＡ５１の信号線７０と多数決回路５７を接続し、セレクタ５４－２は、エラーが発生した冗長化ＦＰＧＡ５１の信号線７１と多数決回路５７を接続する。 The comparison circuit 56 compares the calculation result of the primary FPGA 500-1 of the redundant FPGA 51 with the calculation result of the secondary FPGA 500-2, and detects an error if the calculation results do not match. When the comparison circuit 56 detects an error, the error detection / repair module 55 instructs the selectors 53, 54-1 and 54-2 to connect to the redundant FPGA 51 where the error has occurred via the signal line 58. . The selector 53 connects the redundant FPGA 51 and the third FPGA 52 in which the error has occurred, the selector 54-1 connects the signal line 70 of the redundant FPGA 51 in which the error has occurred and the majority circuit 57, and the selector 54-2 The signal line 71 of the redundant FPGA 51 in which an error has occurred and the majority circuit 57 are connected.
　次に、エラー検知・修復モジュール５５は、信号線５８を介してエラーが発生した冗長化ＦＰＧＡ５１のデータを、第３のＦＰＧＡ５２へ送信するよう指令する。その後、エラー検知・修復モジュール５５は、第３のＦＰＧＡ５２と、エラーが発生した冗長化ＦＰＧＡ５１で、Ｏｒｄｅｒのデータについての演算を再度実行させる。 Next, the error detection / repair module 55 instructs the third FPGA 52 to transmit the data of the redundant FPGA 51 in which an error has occurred via the signal line 58. After that, the error detection / repair module 55 causes the third FPGA 52 and the redundant FPGA 51 in which the error has occurred to execute the calculation for the Order data again.
　第２のセレクタ５４－１は、エラーが発生した冗長化ＦＰＧＡ５１の信号線７０に接続され、第３のセレクタ５４－２は、エラーが発生した冗長化ＦＰＧＡ５１の信号線７１に接続される。したがって、多数決回路５７には、第３のＦＰＧＡ５２の演算処理と、エラーが発生した冗長化ＦＰＧＡ５１のプライマリＦＰＧＡ５００－１の演算結果と、同じくエラーが発生した冗長化ＦＰＧＡ５１のセカンダリＦＰＧＡ５００－２の３つの演算結果が入力される。 The second selector 54-1 is connected to the signal line 70 of the redundant FPGA 51 in which an error has occurred, and the third selector 54-2 is connected to the signal line 71 of the redundant FPGA 51 in which an error has occurred. Therefore, the majority circuit 57 includes three processing operations of the third FPGA 52, the calculation result of the primary FPGA 500-1 of the redundant FPGA 51 in which an error has occurred, and the secondary FPGA 500-2 of the redundant FPGA 51 in which the error has also occurred. The calculation result is input.
　本実施例のＦＰＧＡボード５では、エラーが発生したときには、エラーが発生した冗長化ＦＰＧＡ５１の２つのＦＰＧＡ５００－１、５００－２と、第３のＦＰＧＡ５２で３重化されたＦＰＧＡの演算回路が一時的に設定される。そして、多数決回路５７は、一時的な３重化回路の演算結果を比較して、一致する数が最大の演算結果を信号線５９へ出力する多数決処理を行う。データ転送ＦＰＧＡ５０は、エラー検知・修復モジュール５５（多数決回路５７）から受信した演算結果を、Ｏｒｄｅｒのデータに対する演算結果としてＰＣＩｅｘｐｒｅｓｓ４に出力する。ＣＰＵ２とＮＩＣカード６は、ＦＰＧＡボード５からＰＣＩｅｘｐｒｅｓｓ４へ出力された演算結果を、ゲートウェイ装置１２へ送信する。 In the FPGA board 5 of the present embodiment, when an error occurs, the two FPGAs 500-1 and 500-2 of the redundant FPGA 51 in which the error has occurred and the arithmetic circuit of the FPGA tripled by the third FPGA 52 are temporarily stored. Is set automatically. Then, the majority circuit 57 compares the operation results of the temporary triple circuit, and performs the majority process of outputting the operation result with the largest number of matches to the signal line 59. The data transfer FPGA 50 outputs the calculation result received from the error detection / repair module 55 (majority decision circuit 57) to the PCI express 4 as a calculation result for the Order data. The CPU 2 and the NIC card 6 transmit the calculation result output from the FPGA board 5 to the PCI express 4 to the gateway device 12.
　また、エラー検知・修復モジュール５５は、エラーが発生した冗長化ＦＰＧＡ５１の識別子をデータ転送ＦＰＧＡ５０に通知する。データ転送ＦＰＧＡ５０は、ＰＣＩｅｘｐｒｅｓｓ４を介してＣＰＵ２へエラーが発生した冗長化ＦＰＧＡ５１の識別子を通知する。なお、エラー検知・修復モジュール５５は、データ転送ＦＰＧＡ５０にエラーが発生したことを通知するようにしても良い。 Further, the error detection / repair module 55 notifies the data transfer FPGA 50 of the identifier of the redundant FPGA 51 in which an error has occurred. The data transfer FPGA 50 notifies the CPU 2 of the identifier of the redundant FPGA 51 in which an error has occurred via the PCI express 4. The error detection / repair module 55 may notify the data transfer FPGA 50 that an error has occurred.
　ＣＰＵ２は、ＰＣＩｅｘｐｒｅｓｓ４を介してＦＰＧＡボード５からエラーが発生した冗長化ＦＰＧＡ５１の識別子を受信すると、Ｏｒｄｅｒのデータを処理する装置を、プライマリのＭＥサーバ１－ＰからセカンダリのＭＥサーバ１－Ｓに切り替える。これにより、ＳＲＡＭ型のＦＰＧＡで構成された冗長化ＦＰＧＡ５１にエラーが発生しても、第３のＦＰＧＡ５２を用いてエラーを修復してからセカンダリのＭＥサーバ１－Ｓに切り替えることが可能となる。 When the CPU 2 receives the identifier of the redundant FPGA 51 in which an error has occurred from the FPGA board 5 via the PCI express 4, the CPU 2 switches the device for processing the Order data from the primary ME server 1-P to the secondary ME server 1-S. . As a result, even if an error occurs in the redundant FPGA 51 configured with the SRAM type FPGA, it is possible to switch to the secondary ME server 1-S after correcting the error using the third FPGA 52.
　本発明では、２重化されたｎ個の冗長化ＦＰＧＡ５１を用いてエラーを検知し、エラーが発生したときには、第３のＦＰＧＡ５２と、エラーが発生した冗長化ＦＰＧＡ５１の２つのＦＰＧＡ５００－１、５００－２で一時的に３重化したＦＰＧＡを構成し、同一のデータで再度演算する。そして、３重化したＦＰＧＡの３つの演算結果を多数決回路５７で比較し、最も一致した数の多い演算結果を、修復した演算結果として出力する。 In the present invention, an error is detected using n redundant FPGAs 51 that are duplicated, and when an error occurs, two FPGAs 500-1, 500 of the third FPGA 52 and the redundant FPGA 51 in which the error has occurred are detected. -2 configures a temporary triple FPGA, and calculates again with the same data. Then, the three operation results of the triple FPGA are compared by the majority circuit 57, and the operation result with the most consistent number is output as the repaired operation result.
　したがって、ＦＰＧＡボード５では、２つのＦＰＧＡ５００－１と５００－２を含むｎ個の冗長化ＦＰＧＡ５１と、１つの第３のＦＰＧＡ５２で、エラーが発生したときのみ３重化したＦＰＧＡで再度演算を行って、演算結果の修復が可能となる。これにより、３重化するための第３のＦＰＧＡ５２が１つあれば良いので、ＦＰＧＡボード５の製造コストを抑制することが可能となるのである。 Therefore, in the FPGA board 5, n redundant FPGAs 51 including two FPGAs 500-1 and 500-2 and one third FPGA 52 perform computation again with the triplexed FPGA only when an error occurs. Thus, the operation result can be repaired. As a result, only one third FPGA 52 is required to be tripled, so that the manufacturing cost of the FPGA board 5 can be suppressed.
　なお、多数決回路５７が演算結果を出力すると、エラー検知・修復モジュール５５は各セレクタ５３、５４－１、５４－２をリセットし、エラーが発生した冗長化ＦＰＧＡ５１と第３のＦＰＧＡ５２及び多数決回路５７との接続を解除する。 When the majority circuit 57 outputs the calculation result, the error detection / repair module 55 resets the selectors 53, 54-1, and 54-2, and the redundant FPGA 51, the third FPGA 52, and the majority circuit 57 in which an error has occurred. Disconnect from.
　また、図３の例では、エラー検知・修復モジュール５５が、比較回路５６のエラー検出やセレクタ５３、５４－１、５４－２の制御などを行う制御部として機能する例を示したが、これに限定されるものではない。例えば、比較回路５６の比較結果からセレクタ５３、５４－１、５４－２を制御する制御回路を独立して設けてもよい。 In the example of FIG. 3, the error detection / repair module 55 functions as a control unit that performs error detection of the comparison circuit 56, control of the selectors 53, 54-1, and 54-2. It is not limited to. For example, a control circuit that controls the selectors 53, 54-1 and 54-2 based on the comparison result of the comparison circuit 56 may be provided independently.
　図４は、計算機システムで行われる処理の一例を示すシーケンス図である。図示の例では、冗長化ＦＰＧＡ５１でエラーが発生した例を示す。 FIG. 4 is a sequence diagram showing an example of processing performed in the computer system. In the illustrated example, an example in which an error has occurred in the redundant FPGA 51 is shown.
　まず、ゲートウェイ装置１２は、外部の計算機（図示省略）からＯｒｄｅｒを受信すると、ネットワーク１３を介して所定のノード１０にＯｒｄｅｒを転送する（Ｓ１）。ゲートウェイ装置１２は、上述したようにラウンドロビンなどの負荷分散手法によりＯｒｄｅｒを転送先のノード１０を選択する。以下の説明では、ゲートウェイ装置１２がノード１０－１にＯｒｄｅｒを転送した例を示す。 First, when receiving an Order from an external computer (not shown), the gateway device 12 transfers the Order to a predetermined node 10 via the network 13 (S1). As described above, the gateway device 12 selects the node 10 as the transfer destination of Order by a load balancing method such as round robin. In the following description, an example is shown in which the gateway device 12 transfers Order to the node 10-1.
　ノード１０－１では、プライマリのＭＥサーバ１－ＰがＯｒｄｅｒを受信し、ＮＩＣカード６を介してＣＰＵ２がＯｒｄｅｒを受信してメモリ３に格納する。ＣＰＵ２は、受信したＯｒｄｅｒをＦＰＧＡボード５で処理する所定のプログラム（以下、ノード制御プログラムとする）を実行する。Ｏｒｄｅｒ制御プログラムを実行するＣＰＵ２は、メモリ３に書き込んだＯｒｄｅｒをセカンダリのＭＥサーバ１－Ｓに転送する。 In the node 10-1, the primary ME server 1 -P receives Order, and the CPU 2 receives Order through the NIC card 6 and stores it in the memory 3. The CPU 2 executes a predetermined program (hereinafter referred to as a node control program) for processing the received Order by the FPGA board 5. The CPU 2 that executes the Order control program transfers the Order written in the memory 3 to the secondary ME server 1-S.
　セカンダリのＭＥサーバ１－Ｓも、ノード制御プログラムを実行しており、プライマリのＭＥサーバ１－Ｐから受信したＯｒｄｅｒを、メモリ３にコピーする。そして、セカンダリのＭＥサーバ１－ＳのＣＰＵ２は、Ｏｒｄｅｒのコピーを保存したことを示す応答（図中Ａｃｋ）をプライマリのＭＥサーバ１－Ｐに送信する（Ｓ４）。 The secondary ME server 1-S also executes the node control program, and copies the Order received from the primary ME server 1-P to the memory 3. Then, the CPU 2 of the secondary ME server 1-S transmits a response (Ack in the figure) indicating that the Order copy has been saved to the primary ME server 1-P (S4).
　ノード制御プログラムを実行するプライマリのＭＥサーバ１－ＰのＣＰＵ２は、メモリ３に格納したＯｒｄｅｒをＦＰＧＡボード５に送信する（Ｓ３）。そして、プライマリのＭＥサーバ１－ＰのＣＰＵ２は、セカンダリのＭＥサーバ１－Ｓから応答を受信すると、ＦＰＧＡボード５に演算開始の指令を送信する（Ｓ５）。 The CPU 2 of the primary ME server 1-P that executes the node control program transmits the Order stored in the memory 3 to the FPGA board 5 (S3). When the CPU 2 of the primary ME server 1-P receives a response from the secondary ME server 1-S, it sends a calculation start command to the FPGA board 5 (S5).
　ＦＰＧＡボード５では、ＣＰＵ２かＯｒｄｅｒを受信すると、データ転送ＦＰＧＡ５０がメモリ６０に設定したキューにＯｒｄｅｒを格納する。そして、ＣＰＵ２から演算開始の指令を受信すると、データ転送ＦＰＧＡ５０は、キューに対応する冗長化ＦＰＧＡ５１にＯｒｄｅｒを送信し、所定の演算を実行させる（Ｓ６）。本実施例では、Ｏｒｄｅｒとして証券の取引要求を含み、ＦＰＧＡボード５の冗長化ＦＰＧＡ５１では、所定の処理としてＯｒｄｅｒに含まれるデータの取引を成立させるマッチング処理を実行する。なお、図中ＭＥは冗長化ＦＰＧＡ５１の機能を示すマッチングエンジンを示す。 In the FPGA board 5, when the CPU 2 or Order is received, the Order is stored in the queue set in the memory 60 by the data transfer FPGA 50. When receiving a calculation start command from the CPU 2, the data transfer FPGA 50 transmits Order to the redundant FPGA 51 corresponding to the queue to execute a predetermined calculation (S6). In this embodiment, the order includes a transaction request for securities, and the redundant FPGA 51 of the FPGA board 5 executes a matching process for establishing a transaction for data included in the Order as a predetermined process. In the figure, ME indicates a matching engine indicating the function of the redundant FPGA 51.
　冗長化ＦＰＧＡ５１のプライマリＦＰＧＡ５００－１とセカンダリＦＰＧＡ５００－２の２つの演算結果は比較回路５６へ入力され、２つの演算結果が一致しない場合にはエラーとなる（図中ｅｒｒｏｒ１）。ＦＰＧＡボード５のエラー検知・修復モジュール５５は、エラーが発生した冗長化ＦＰＧＡ５１と第３のＦＰＧＡ５２をセレクタ５３、５４－１、５４－２で接続して３重化し、再度演算を実行する（Ｓ７）。そして、エラー検知・修復モジュール５５では、上述したように多数決回路５７が、３重化されたＦＰＧＡの出力から演算結果を選択し、この演算結果をエラーを修復した演算結果としてＦＰＧＡボード５から出力し（Ｓ８）、ネットワーク１３を介してゲートウェイ装置１２に応答する。なお、ＦＰＧＡボード５からの演算結果の出力は、ＰＣＩｅｘｐｒｅｓｓ４からＣＰＵ２が演算結果を受信し、この演算結果をＮＩＣカード６から出力する。 The two computation results of the primary FPGA 500-1 and the secondary FPGA 500-2 of the redundant FPGA 51 are input to the comparison circuit 56, and an error occurs if the two computation results do not match (error 1 in the figure). The error detection / repair module 55 of the FPGA board 5 connects the redundant FPGA 51 and the third FPGA 52 in which an error has occurred with the selectors 53, 54-1, and 54-2, and performs the operation again (S7). ). In the error detection / repair module 55, as described above, the majority circuit 57 selects a calculation result from the output of the triple FPGA, and outputs the calculation result from the FPGA board 5 as a calculation result of correcting the error. (S8), and responds to the gateway device 12 via the network 13. Note that the calculation result output from the FPGA board 5 is received by the CPU 2 from the PCI express 4, and the calculation result is output from the NIC card 6.
　ノード制御プログラムを実行するプライマリのＭＥサーバ１－ＰのＣＰＵ２は、ＦＰＧＡボード５からエラーが発生した冗長化ＦＰＧＡ５１の識別子を受け付けると、待機系のセカンダリのＭＥサーバ１－Ｓに処理を引き継ぐよう指令する（Ｓ９）。ノード１０－１では、次に受信したＯｒｄｅｒをセカンダリのＭＥサーバ１－Ｓで処理し、ゲートウェイ装置１２へ応答する。 When the CPU 2 of the primary ME server 1-P that executes the node control program receives the identifier of the redundant FPGA 51 in which an error has occurred from the FPGA board 5, it instructs the standby secondary ME server 1-S to take over the processing. (S9). In the node 10-1, the next received Order is processed by the secondary ME server 1-S and responds to the gateway device 12.
　図５は、本発明の第１の実施例を示し、ＦＰＧＡボード５内で行われる処理の一例を示すシーケンス図である。ＦＰＧＡボード５では、ＰＣＩｅｘｐｒｅｓｓ４からＯｒｄｅｒを受け付けると、データ転送ＦＰＧＡ５０が受信する（Ｓ１１）。データ転送ＦＰＧＡ５０は、ＣＰＵ２から演算開始の指令を受信すると、Ｏｒｄｅｒに含まれるデータを所定の冗長化ＦＰＧＡ５１に送信し、プライマリＦＰＧＡ５００－１とセカンダリＦＰＧＡ５００－２は、受信したデータをそれぞれ演算する（Ｓ１２、Ｓ１３）。 FIG. 5 is a sequence diagram illustrating an example of processing performed in the FPGA board 5 according to the first embodiment of this invention. In the FPGA board 5, when Order is received from the PCI express 4, the data transfer FPGA 50 receives the order (S11). When the data transfer FPGA 50 receives a calculation start command from the CPU 2, the data transfer FPGA 50 transmits the data included in the Order to a predetermined redundancy FPGA 51, and the primary FPGA 500-1 and the secondary FPGA 500-2 each calculate the received data (S12). , S13).
　プライマリＦＰＧＡ５００－１とセカンダリＦＰＧＡ５００－２の演算結果（図中Ｒｅ）は、エラー検知・修復モジュール５５の比較回路５６で、一致するか否かの判定が行われる（Ｓ１４）。一致しない場合には、エラーの発生となり、エラー検知・修復モジュール５５は各セレクタ５３、５４－１、５４－２を切り替えて、上述したように、エラーが発生した冗長化ＦＰＧＡ５１のプライマリ及びセカンダリのＦＰＧＡと第３のＦＰＧＡ５２を３重化して多数決回路５７に接続する（Ｓ１５）。 The calculation result (Re in the figure) of the primary FPGA 500-1 and the secondary FPGA 500-2 is determined by the comparison circuit 56 of the error detection / repair module 55 to determine whether or not they match (S14). If they do not match, an error occurs, and the error detection / repair module 55 switches the selectors 53, 54-1, 54-2, and, as described above, the primary and secondary of the redundant FPGA 51 in which the error has occurred. The FPGA and the third FPGA 52 are tripled and connected to the majority circuit 57 (S15).
　そして、エラー検知・修復モジュール５５は、エラーが発生した冗長化ＦＰＧＡ５１に、現在のデータを第３のＦＰＧＡ５２へ送信するように指令する。エラーが発生した冗長化ＦＰＧＡ５１は、現在保持しているデータを第３のＦＰＧＡ５２に送信する（Ｓ１６）。 Then, the error detection / repair module 55 instructs the redundant FPGA 51 in which an error has occurred to transmit the current data to the third FPGA 52. The redundant FPGA 51 in which the error has occurred transmits the currently held data to the third FPGA 52 (S16).
　次に、エラー検知・修復モジュール５５は、３重化した冗長化ＦＰＧＡ５１と第３のＦＰＧＡ５２に対して、現在保持しているデータで演算を実行するように指令する（Ｓ１７）。エラーが発生した冗長化ＦＰＧＡ５１では、プライマリとセカンダリのＦＰＧＡ５００－１と５００－２が、前回のデータを再度演算し、第３のＦＰＧＡ５２は冗長化ＦＰＧＡ５１からコピーしたデータを演算する。そして、これら３重化したＦＰＧＡの演算結果は多数決回路５７へ入力される（Ｓ１８）。 Next, the error detection / repair module 55 instructs the triple redundant FPGA 51 and the third FPGA 52 to execute an operation with the currently held data (S17). In the redundant FPGA 51 in which an error has occurred, the primary and secondary FPGAs 500-1 and 500-2 calculate the previous data again, and the third FPGA 52 calculates the data copied from the redundant FPGA 51. Then, the operation result of these tripled FPGAs is input to the majority circuit 57 (S18).
　多数決回路５７は、入力された３つの演算結果について多数決を実行し、最も一致した数の多い演算結果を出力する（Ｓ１９）。出力された演算結果は、図３に示した信号線５９を介してデータ転送ＦＰＧＡ５０に転送され、ＰＣＩｅｘｐｒｅｓｓ４へ出力される（Ｓ２０）。 The majority circuit 57 executes a majority vote on the three input operation results, and outputs the operation result with the most consistent number (S19). The output calculation result is transferred to the data transfer FPGA 50 via the signal line 59 shown in FIG. 3, and is output to the PCI express 4 (S20).
　以上の処理により、２つのＦＰＧＡ５００－１と５００－２を含むｎ個の冗長化ＦＰＧＡ５１と、１つの第３のＦＰＧＡ５２でＦＰＧＡボード５を構成し、エラーが発生したときのみ３重化したＦＰＧＡで再度演算を行って、演算結果の修復が可能となり、ＦＰＧＡボード５の製造コストを抑制しながら信頼性を向上させることが可能となるのである。 Through the above processing, the n-redundant FPGA 51 including the two FPGAs 500-1 and 500-2 and the one third FPGA 52 constitute the FPGA board 5, and the triple FPGA only when an error occurs. It is possible to restore the calculation result by performing the calculation again, and to improve the reliability while suppressing the manufacturing cost of the FPGA board 5.
　なお、上記では、プライマリのＭＥサーバ１－ＰのＦＰＧＡボード５と、セカンダリのＭＥサーバ１－Ｓとの通信は、ＣＰＵ２が主体となってＮＩＣカード６から送受信する例を示したが、これに限定されるものではない。例えば、ＦＰＧＡボード５のデータ転送ＦＰＧＡ５０がセカンダリのＭＥサーバ１－Ｓに対してリモートＤＭＡでデータの転送や処理の引き継ぎの通知を行うようにしても良い。 In the above description, the communication between the FPGA board 5 of the primary ME server 1-P and the secondary ME server 1-S is transmitted and received from the NIC card 6 mainly by the CPU 2. It is not limited. For example, the data transfer FPGA 50 of the FPGA board 5 may notify the secondary ME server 1-S of data transfer or processing takeover by remote DMA.
　また、多数決回路５７は、３つの演算結果について多数決処理を行って、演算結果が他とは異なるＦＰＧＡを、エラーが発生したＦＰＧＡとして特定することができる。 In addition, the majority circuit 57 can perform majority processing on the three calculation results, and can identify an FPGA having a different calculation result as the FPGA in which an error has occurred.
　図６Ａは、第２の実施例を示し、ＦＰＧＡ５００の一例を示すブロック図である。図６Ａは、プライマリＦＰＧＡ５００－１の構成を示すが、セカンダリＦＰＧＡ５００－２と第３のＦＰＧＡ５２も同様の構成である。 FIG. 6A is a block diagram illustrating an example of the FPGA 500 according to the second embodiment. FIG. 6A shows the configuration of the primary FPGA 500-1, but the secondary FPGA 500-2 and the third FPGA 52 have the same configuration.
　プライマリＦＰＧＡ５００－１は、ＰＣＩｅｘｐｒｅｓｓ４に接続するＰＣＩｅｘｐｒｅｓｓインターフェース５０１と、コントローラ５０２と、演算モジュールＡ（５０３Ａ）と演算モジュールＢ（５０３Ｂ）と、演算モジュールＡの出力と演算モジュールＢの出力をクロック信号ＣＬＫに応じて切り替えて出力する内部セレクタ５０４と、メモリ６１－１を制御するメモリインターフェース５０５を主体に構成される。 The primary FPGA 500-1 includes a PCI express interface 501 connected to the PCI express 4, a controller 502, an arithmetic module A (503A), an arithmetic module B (503B), an output of the arithmetic module A, and an output of the arithmetic module B as a clock signal CLK. The main selector 504 is configured to switch the output accordingly, and the memory interface 505 that controls the memory 61-1 is mainly configured.
　演算モジュールＡと演算モジュールＢは、前記実施例１のプライマリＦＰＧＡ５００－１の演算ユニットを分割したものである。演算モジュールＡは、ＰＣＩｅｘｐｒｅｓｓインターフェース５０１のデータ線５１０（図中ＤＩＮ）からデータを受信し、メモリインターフェース５０５を介してメモリ６１－１へ書き込むまでの処理を行う。演算モジュールＢは、メモリインターフェース５０５を介してメモリ６１－１からデータを読み込んで、所定のマッチング処理を実行し演算結果を出力する。マッチング処理は前記実施例１と同様であり、演算結果も前記実施例１と同様となる。 The arithmetic module A and the arithmetic module B are obtained by dividing the arithmetic unit of the primary FPGA 500-1 of the first embodiment. The arithmetic module A performs processing from receiving data from the data line 510 (DIN in the figure) of the PCI express interface 501 until writing to the memory 61-1 via the memory interface 505. The calculation module B reads data from the memory 61-1 via the memory interface 505, executes a predetermined matching process, and outputs a calculation result. The matching process is the same as in the first embodiment, and the calculation result is the same as in the first embodiment.
　内部セレクタ５０４は、コントローラ５０２からの指令に応じて、演算モジュールＡの出力と、演算モジュールＢの出力を切り替えて信号線７０－１へ出力する。このため、コントローラ５０２には、ＰＣＩｅｘｐｒｅｓｓインターフェース５０１の制御線５１１（図中ＣＩＮ）と、外部からのクロック信号ＣＬＫを入力するクロック信号線５２０が接続される。 The internal selector 504 switches between the output of the arithmetic module A and the output of the arithmetic module B in accordance with a command from the controller 502 and outputs the result to the signal line 70-1. For this reason, the controller 502 is connected with a control line 511 (CIN in the figure) of the PCI express interface 501 and a clock signal line 520 for inputting an external clock signal CLK.
　外部のクロック信号ＣＬＫとしては、例えば、ＣＰＵ２が生成した信号を用いることができる。このクロック信号ＣＬＫと内部セレクタ５０４の出力の関係を図６Ｂに示す。図６Ｂの例では、クロック信号ＣＬＫが"０"で内部セレクタ５０４は演算モジュールＡの出力を選択し、クロック信号ＣＬＫが"１"で内部セレクタ５０４は演算モジュールＢの出力を選択する。 As the external clock signal CLK, for example, a signal generated by the CPU 2 can be used. The relationship between the clock signal CLK and the output of the internal selector 504 is shown in FIG. 6B. In the example of FIG. 6B, the clock signal CLK is “0” and the internal selector 504 selects the output of the arithmetic module A, and the clock signal CLK is “1” and the internal selector 504 selects the output of the arithmetic module B.
　図３で示した冗長化ＦＰＧＡ５１－１～５１－ｎのプライマリＦＰＧＡ５００－１とセカンダリＦＰＧＡ５００－２及び第３のＦＰＧＡ５２に、外部のクロック信号ＣＬＫが入力される。そして、冗長化ＦＰＧＡ５１にエラーが発生した後に、第３のＦＰＧＡ５２と３重化され、多数決回路５７には、３つのＦＰＧＡの演算結果が入力される。 The external clock signal CLK is input to the primary FPGA 500-1, the secondary FPGA 500-2, and the third FPGA 52 of the redundant FPGAs 51-1 to 51-n shown in FIG. Then, after an error has occurred in the redundant FPGA 51, it is tripled with the third FPGA 52, and the majority circuit 57 receives the calculation results of the three FPGAs.
　このとき、クロック信号ＣＬＫが"１"で多数決回路５７は演算モジュールＢの演算結果が一致するか否かを判定する。エラーが発生した冗長化ＦＰＧＡ５１では全ての演算結果は一致しないので、エラー検知・修復モジュール５５では、異なる演算結果を出力したＦＰＧＡがプライマリＦＰＧＡ５００－１とセカンダリＦＰＧＡ５００－２の何れであるかを特定できる。 At this time, the clock signal CLK is “1”, and the majority circuit 57 determines whether or not the calculation results of the calculation module B match. Since all the operation results do not match in the redundant FPGA 51 in which an error has occurred, the error detection / repair module 55 can specify whether the FPGA that has output a different operation result is the primary FPGA 500-1 or the secondary FPGA 500-2. .
　次に、再度３重化したＦＰＧＡで同一のデータで演算を実行させる。そして、クロック信号ＣＬＫを"０"として多数決回路５７は演算モジュールＡの演算結果が一致するか否かを判定する。３つの演算結果が一致した場合、エラー検知・修復モジュール５５は、第１回目の多数決回路５７の判定で、異なる演算結果を出力したＦＰＧＡの演算モジュールＢでエラーが発生したことを特定できる。一方、３つの演算結果が一致しない場合、エラー検知・修復モジュール５５は、今回（第２回目）の多数決回路５７の判定で、異なる演算結果を出力したＦＰＧＡの演算モジュールＡでエラーが発生したことを特定できる。 Next, the calculation is executed with the same data in the triple FPGA again. Then, with the clock signal CLK set to “0”, the majority circuit 57 determines whether or not the calculation results of the calculation module A match. When the three calculation results match, the error detection / recovery module 55 can determine that an error has occurred in the FPGA calculation module B that has output a different calculation result in the first determination by the majority circuit 57. On the other hand, if the three calculation results do not match, the error detection / recovery module 55 indicates that an error has occurred in the calculation module A of the FPGA that output a different calculation result in the determination of the majority circuit 57 this time (second time). Can be identified.
　以上のように、実施例２によれば、冗長化ＦＰＧＡ５１を構成するＦＰＧＡを複数に分割して、分割された演算ユニットの複数の演算結果を内部セレクタ５０４で切り替えて出力する。これにより、エラー検知・修復モジュール５５は、エラーが発生したＦＰＧＡに加えて、エラーが発生した部位（演算ユニット）を特定することができる。 As described above, according to the second embodiment, the FPGA configuring the redundant FPGA 51 is divided into a plurality of parts, and a plurality of operation results of the divided operation units are switched by the internal selector 504 and output. As a result, the error detection / repair module 55 can specify the part (arithmetic unit) where the error has occurred in addition to the FPGA where the error has occurred.
　なお、上記ではエラー検知・修復モジュール５５は、エラーが発生したＦＰＧＡの特定（プライマリＦＰＧＡ５００－１とセカンダリＦＰＧＡ５００－２のいずれか）と、エラーが発生した部位（演算ユニット）を特定する例を示したが、データ転送ＦＰＧＡ５０やＣＰＵ２でエラーが発生した部位の特定を行うようにしてもよい。 In the above description, the error detection / repair module 55 shows an example of specifying an FPGA in which an error has occurred (one of the primary FPGA 500-1 or the secondary FPGA 500-2) and specifying a site (arithmetic unit) in which the error has occurred However, the part where the error occurred in the data transfer FPGA 50 or the CPU 2 may be specified.
　図７、図８は実施例３を示す。図７は、ＦＰＧＡボード５の一例を示すブロック図である。図８は、ＦＰＧＡボード５のＣＰＵで行われる処理の一例を示すフローチャートである。 7 and 8 show the third embodiment. FIG. 7 is a block diagram showing an example of the FPGA board 5. FIG. 8 is a flowchart illustrating an example of processing performed by the CPU of the FPGA board 5.
　図７は、前記実施例１の図３に示した第３のＦＰＧＡ５２に代わって多数の冗長化ＦＰＧＡ５１のうちのひとつを３重化するＦＰＧＡとして使用し、信号線５８に接続したローカルＣＰＵ８０で冗長化ＦＰＧＡ５１と、エラー検知・修復モジュール５５の制御を行う例を示す。なお、前記実施例１の図３に示したセレクタ５３は削除して、ローカルＣＰＵ８０によってデータのコピーなど実行される。ローカルＣＰＵ８０は、プログラムやデータを保持するローカルメモリ８１を有する。また、その他の構成は前記実施例１と同様である。 7 uses one of a number of redundant FPGAs 51 as a triplex FPGA instead of the third FPGA 52 shown in FIG. 3 of the first embodiment, and the local CPU 80 connected to the signal line 58 is redundant. An example in which the control FPGA 51 and the error detection / repair module 55 are controlled will be described. Note that the selector 53 shown in FIG. 3 of the first embodiment is deleted, and data is copied by the local CPU 80. The local CPU 80 has a local memory 81 that holds programs and data. Other configurations are the same as those of the first embodiment.
　前記実施例１では、ｎ個の冗長化ＦＰＧＡ５１とひとつの第３のＦＰＧＡ５２で、エラーが発生したときには冗長化ＦＰＧＡ５１と第３のＦＰＧＡ５２を組み合わせて３重化する。 In the first embodiment, n redundant FPGAs 51 and one third FPGA 52 are combined, and when the error occurs, the redundant FPGA 51 and the third FPGA 52 are combined to be tripled.
　これに対して本実施例３では、ｎ個の冗長化ＦＰＧＡ５１－１～５１－ｎのうちのとひとつを、第３のＦＰＧＡとして用いる例を示す。冗長化ＦＰＧＡ５１は、プライマリＦＰＧＡ５００－１とセカンダリＦＰＧＡ５００－２を備え、各ＦＰＧＡ５００－１、５００－２の出力は信号線７０，７１を介して比較回路５６に接続される。また、各ＦＰＧＡ５００－１、５００－２の出力は信号線７０、７１からセレクタ５４－１、５４－２を介して多数決回路５７に接続される。 On the other hand, the third embodiment shows an example in which one of the n redundant FPGAs 51-1 to 51-n is used as the third FPGA. The redundant FPGA 51 includes a primary FPGA 500-1 and a secondary FPGA 500-2, and the outputs of the FPGAs 500-1 and 500-2 are connected to the comparison circuit 56 via signal lines 70 and 71, respectively. The outputs of the FPGAs 500-1 and 500-2 are connected from the signal lines 70 and 71 to the majority circuit 57 via the selectors 54-1 and 54-2.
　ローカルＣＰＵ８０は、起動すると冗長化ＦＰＧＡ５１－１～５１－ｎのいずれかひとつを第３のＦＰＧＡとして選択する。ここで、ひとつの冗長化ＦＰＧＡ５１には、２つのＦＰＧＡ５００－１と５００－２が含まれるので、ローカルＣＰＵ８０は、何れか一方を第３のＦＰＧＡとして選択する。例えば、ローカルＣＰＵ８０は、ラウンドロビンで第３のＦＰＧＡとする冗長化ＦＰＧＡ５１を選択し、当該冗長化ＦＰＧＡ５１のプライマリＦＰＧＡ５００－１を第３のＦＰＧＡとして選択する。 When activated, the local CPU 80 selects any one of the redundant FPGAs 51-1 to 51-n as the third FPGA. Here, since one redundant FPGA 51 includes two FPGAs 500-1 and 500-2, the local CPU 80 selects one of them as the third FPGA. For example, the local CPU 80 selects the redundant FPGA 51 that is the third FPGA in round robin, and selects the primary FPGA 500-1 of the redundant FPGA 51 as the third FPGA.
　エラー検知・修復モジュール５５は、前記実施例１の構成からセレクタ５４－１、５４５－２の制御を省略したものである。エラー検知・修復モジュール５５は、比較回路５６が演算結果の不一致を検出すると、信号線５８を介してローカルＣＰＵ８０に不一致のエラーが発生した冗長化ＦＰＧＡ５１の識別子を通知する。 The error detection / repair module 55 is obtained by omitting the control of the selectors 54-1, 545-2 from the configuration of the first embodiment. When the comparison circuit 56 detects a mismatch in the operation result, the error detection / repair module 55 notifies the local CPU 80 of the identifier of the redundant FPGA 51 in which the mismatch error has occurred via the signal line 58.
　ローカルＣＰＵ８０は、エラーが発生した冗長化ＦＰＧＡ５１の信号線７０，７１と、第３のＦＰＧＡとして機能する冗長化ＦＰＧＡ５１の信号線７０を多数決回路５７に接続するようセレクタ５４－１、５４－２に指令する。そして、ローカルＣＰＵ８０は、エラーが発生した冗長化ＦＰＧＡ５１から、現在のデータを第３のＦＰＧＡにコピーする。その後、ローカルＣＰＵ８０は、エラーが発生した冗長化ＦＰＧＡ５１と第３のＦＰＧＡに演算の実行を指令する。 The local CPU 80 causes the selectors 54-1 and 54-2 to connect the signal lines 70 and 71 of the redundant FPGA 51 in which an error has occurred and the signal line 70 of the redundant FPGA 51 functioning as the third FPGA to the majority circuit 57. Command. Then, the local CPU 80 copies the current data from the redundant FPGA 51 in which the error has occurred to the third FPGA. Thereafter, the local CPU 80 instructs the redundant FPGA 51 and the third FPGA in which an error has occurred to execute the calculation.
　上記処理により、エラー検知・修復モジュール５５の多数決回路５７からは修復された演算結果が出力される。ローカルＣＰＵ８０は、その後、データ転送ＦＰＧＡ５０を介してセカンダリのＭＥサーバ１－Ｓに処理の引き継ぎを通知する。 Through the above processing, the repaired calculation result is output from the majority circuit 57 of the error detection / repair module 55. Thereafter, the local CPU 80 notifies the secondary ME server 1-S of the takeover of processing via the data transfer FPGA 50.
　上記処理の内容を、図８を参照しながら説明する。図８のフローチャートは、ＦＰＧＡボード５の起動が完了して、第３のＦＰＧＡが選択された状態で実行される。ローカルＣＰＵ８０は、信号線５８を監視してエラー検知・修復モジュール５５がエラーを通知するまで待機する（Ｓ３１）。エラー検知・修復モジュール５５はエラーが発生した冗長化ＦＰＧＡ５１の識別子を通知すると、ローカルＣＰＵ８０は信号線５８から識別子を受信して、エラーが発生した冗長化ＦＰＧＡ５１を特定する（Ｓ３２）。 The contents of the above processing will be described with reference to FIG. The flowchart of FIG. 8 is executed in a state where the activation of the FPGA board 5 is completed and the third FPGA is selected. The local CPU 80 monitors the signal line 58 and waits until the error detection / repair module 55 notifies the error (S31). When the error detection / repair module 55 notifies the identifier of the redundant FPGA 51 in which the error has occurred, the local CPU 80 receives the identifier from the signal line 58 and identifies the redundant FPGA 51 in which the error has occurred (S32).
　ローカルＣＰＵ８０は、エラーが発生した冗長化ＦＰＧＡ５１の信号線７０，７１と、第３のＦＰＧＡとして機能する冗長化ＦＰＧＡ５１の信号線７０を多数決回路５７に接続するようセレクタ５４－１、５４－２に指令する（Ｓ３３、Ｓ３４）。 The local CPU 80 causes the selectors 54-1 and 54-2 to connect the signal lines 70 and 71 of the redundant FPGA 51 in which an error has occurred and the signal line 70 of the redundant FPGA 51 functioning as the third FPGA to the majority circuit 57. Command (S33, S34).
　ローカルＣＰＵ８０は、エラーが発生した冗長化ＦＰＧＡ５１から、現在のデータを第３のＦＰＧＡにコピーする（Ｓ３５）。ローカルＣＰＵ８０は、エラーが発生した冗長化ＦＰＧＡ５１と第３のＦＰＧＡに演算の実行を指令する（Ｓ３６）。 The local CPU 80 copies the current data from the redundant FPGA 51 in which the error has occurred to the third FPGA (S35). The local CPU 80 instructs the redundant FPGA 51 and the third FPGA in which an error has occurred to execute the calculation (S36).
　エラーが発生した冗長化ＦＰＧＡ５１では、プライマリとセカンダリのＦＰＧＡ５００－１と５００－２が、前回のデータを再度演算し、第３のＦＰＧＡは冗長化ＦＰＧＡ５１からコピーしたデータを演算する。そして、これら３重化したＦＰＧＡの演算結果は多数決回路５７へ入力される。多数決回路５７は、入力された３つの演算結果について多数決を実行し、最も一致した数の多い演算結果を信号線５９へ出力する（Ｓ３７）。 In the redundant FPGA 51 in which an error has occurred, the primary and secondary FPGAs 500-1 and 500-2 calculate the previous data again, and the third FPGA calculates the data copied from the redundant FPGA 51. Then, the operation result of the triple FPGA is input to the majority circuit 57. The majority circuit 57 executes a majority vote on the three input operation results, and outputs the operation result having the most matched number to the signal line 59 (S37).
　ローカルＣＰＵ８０は、待機系のセカンダリのＭＥサーバ１－Ｓに対して処理を引き継ぐよう指令する（Ｓ３８）。 The local CPU 80 instructs the standby secondary ME server 1-S to take over the processing (S38).
　以上の処理により、２つのＦＰＧＡ５００－１と５００－２を含むｎ個の冗長化ＦＰＧＡ５１のうちの１つを第３のＦＰＧＡとして、前記実施例１と同様に、エラーが発生したときのみ３重化したＦＰＧＡで再度演算を行って、演算結果の修復を行うことが可能となり、ＦＰＧＡボード５の製造コストを抑制しながら信頼性を向上させることが可能となるのである。 With the above processing, one of the n redundant FPGAs 51 including the two FPGAs 500-1 and 500-2 is set as the third FPGA, and, as in the first embodiment, the triplicate is performed only when an error occurs. It is possible to perform the calculation again with the converted FPGA and restore the calculation result, and it is possible to improve the reliability while suppressing the manufacturing cost of the FPGA board 5.
　本実施例３では、第３のＦＰＧＡをｎ個の冗長化ＦＰＧＡ５１の中から選択できるため、第３のＦＰＧＡにエラーが生じた場合は、セカンダリＦＰＧＡ５００－２や他の冗長化ＦＰＧＡ５１へ処理を引き継ぐことができ、第３のＦＰＧＡの冗長性を確保することができるのである。 In the third embodiment, since the third FPGA can be selected from the n redundant FPGAs 51, when an error occurs in the third FPGA, the processing is taken over to the secondary FPGA 500-2 or another redundant FPGA 51. The redundancy of the third FPGA can be ensured.
　また、本実施例３では、２つのＦＰＧＡ５００－１、５００－２を含む冗長化ＦＰＧＡ５１を複数配置すれば良いので、半導体の設計及び製造を容易にすることができる。 Further, in the third embodiment, a plurality of redundant FPGAs 51 including two FPGAs 500-1 and 500-2 may be arranged, so that semiconductor design and manufacture can be facilitated.
　また、本発明は上記した実施例に限定されるものではなく、様々な変形例が含まれる。例えば、上記した実施例は本発明をわかりやすく説明するために詳細に説明したものであり、必ずしも説明した全ての構成を備えるものに限定されるものではない。 Further, the present invention is not limited to the above-described embodiments, and includes various modifications. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described.

Claims (12)

  1. 　入力されたデータを並列して演算する第１の演算ユニットと第２の演算ユニットを含む冗長化演算ユニットと、
    　前記第１の演算ユニットの演算結果と、前記第２の演算ユニットの演算結果とを比較する比較回路と、
    　前記比較回路の比較結果が一致しないときに、前記冗長化演算ユニットのデータを演算する第３の演算ユニットと、
    　前記比較回路の比較結果が一致しないときに、前記第１の演算ユニットの出力と、前記第２の演算ユニットの出力と、前記第３の演算ユニットの出力とを多数決回路に接続するセレクタと、
    を備えたことを特徴とする演算回路。     A redundant computing unit including a first computing unit and a second computing unit that computes input data in parallel;
    A comparison circuit for comparing the calculation result of the first calculation unit and the calculation result of the second calculation unit;
    A third arithmetic unit that calculates data of the redundant arithmetic unit when the comparison result of the comparison circuit does not match;
    A selector that connects the output of the first arithmetic unit, the output of the second arithmetic unit, and the output of the third arithmetic unit to a majority circuit when the comparison result of the comparison circuit does not match;
    An arithmetic circuit comprising:
  2. 　請求項１に記載の演算回路であって、
    　前記冗長化演算ユニットを複数備え、
    　前記複数の冗長化演算ユニットにそれぞれ接続される複数の前記比較回路と、
    　前記複数の冗長化演算ユニットに接続された前記比較回路のうち、比較結果が一致しないときに、当該冗長化演算ユニットのエラーの発生を検出する制御部をさらに有し、
    　前記制御部は、
    　前記エラーが発生した冗長化演算ユニットの第１の演算ユニットの出力と、前記第２の演算ユニットの出力とを前記多数決回路に接続するように前記セレクタに指令し、
    　前記エラーが発生した冗長化演算ユニットに、現在のデータを前記第３の演算ユニットに転送させ、
    　前記冗長化演算ユニットに前記現在のデータで再度演算を実行させ、前記第３の演算ユニットに前記転送されたデータを演算させ、
    　前記多数決回路は、
    　前記セレクタを介して一時的に３重化された冗長化演算ユニットと第３の演算ユニットの演算結果を受け付けて、多数決処理を行うことを特徴とする演算回路。     The arithmetic circuit according to claim 1,
    A plurality of the redundant arithmetic units are provided,
    A plurality of the comparison circuits respectively connected to the plurality of redundant arithmetic units;
    Among the comparison circuits connected to the plurality of redundant arithmetic units, further comprising a control unit that detects the occurrence of an error in the redundant arithmetic units when the comparison result does not match,
    The controller is
    Instructing the selector to connect the output of the first arithmetic unit of the redundant arithmetic unit in which the error has occurred and the output of the second arithmetic unit to the majority circuit,
    Causing the redundant arithmetic unit in which the error has occurred to transfer the current data to the third arithmetic unit;
    Causing the redundant computing unit to perform the computation again with the current data, causing the third computing unit to compute the transferred data,
    The majority circuit is
    An arithmetic circuit that receives the arithmetic results of the redundant arithmetic unit and the third arithmetic unit that are temporarily tripled through the selector and performs majority processing.
  3. 　請求項１に記載の演算回路であって、
    　前記第３の演算ユニットは、
    　前記冗長化演算ユニットで構成されて、前記第１の演算ユニットと第２の演算ユニットの一方を当該第３の演算ユニットとして使用することを特徴とする演算回路。     The arithmetic circuit according to claim 1,
    The third arithmetic unit is
    An arithmetic circuit comprising the redundant arithmetic unit, wherein one of the first arithmetic unit and the second arithmetic unit is used as the third arithmetic unit.
  4. 　請求項１に記載の演算回路であって、
    　前記第３の演算ユニットは、
    　前記多数決回路に常時接続されることを特徴とする演算回路。     The arithmetic circuit according to claim 1,
    The third arithmetic unit is
    An arithmetic circuit which is always connected to the majority circuit.
  5. 　請求項１に記載の演算回路であって、
    　前記多数決回路は、
    　前記第１の演算ユニットの演算結果と、前記第２の演算ユニットの演算結果と、前記第３の演算ユニットの演算結果とを受け付けて、他とは異なる演算結果を出力する演算ユニットをエラーが発生した演算ユニットとして特定することを特徴とする演算回路。     The arithmetic circuit according to claim 1,
    The majority circuit is
    An error occurs in the arithmetic unit that receives the arithmetic result of the first arithmetic unit, the arithmetic result of the second arithmetic unit, and the arithmetic result of the third arithmetic unit and outputs an arithmetic result different from the others. An arithmetic circuit characterized by specifying the generated arithmetic unit.
  6. 　請求項１に記載の演算回路であって、
    　前記第１の演算ユニットと、第２の演算ユニット及び第３の演算ユニットは、
    　入力を受け付ける第１の演算モジュールと、前記第１の演算モジュールの出力を受け付ける第２の演算モジュールと、第１の演算モジュールの出力と第２の演算モジュールの出力とをクロックに応じて切り替える内部セレクタと、をそれぞれ含み、
    　前記第１の演算ユニットと、第２の演算ユニット及び第３の演算ユニットに同一のクロックを入力することを特徴とする演算回路。     The arithmetic circuit according to claim 1,
    The first arithmetic unit, the second arithmetic unit, and the third arithmetic unit are:
    A first arithmetic module that accepts an input, a second arithmetic module that accepts an output of the first arithmetic module, and an internal that switches between the output of the first arithmetic module and the output of the second arithmetic module according to a clock. Each including a selector,
    An arithmetic circuit, wherein the same clock is input to the first arithmetic unit, the second arithmetic unit, and the third arithmetic unit.
  7. 　プロセッサと、メモリと、前記プロセッサに接続される演算回路と、を備えた計算機であって、
    　前記演算回路は、
    　入力されたデータを並列して演算する第１の演算ユニットと第２の演算ユニットを含む冗長化演算ユニットと、
    　前記第１の演算ユニットの演算結果と、前記第２の演算ユニットの演算結果とを比較する比較回路と、
    　前記比較回路の比較結果が一致しないときに、前記冗長化演算ユニットのデータを演算する第３の演算ユニットと、
    　前記比較回路の比較結果が一致しないときに、前記第１の演算ユニットの出力と、前記第２の演算ユニットの出力と、前記第３の演算ユニットの出力とを多数決回路に接続するセレクタと、
    を備えたことを特徴とする計算機。     A computer comprising a processor, a memory, and an arithmetic circuit connected to the processor,
    The arithmetic circuit is:
    A redundant computing unit including a first computing unit and a second computing unit that computes input data in parallel;
    A comparison circuit for comparing the calculation result of the first calculation unit and the calculation result of the second calculation unit;
    A third arithmetic unit that calculates data of the redundant arithmetic unit when the comparison result of the comparison circuit does not match;
    A selector that connects the output of the first arithmetic unit, the output of the second arithmetic unit, and the output of the third arithmetic unit to a majority circuit when the comparison result of the comparison circuit does not match;
    A computer characterized by comprising:
  8. 　請求項７に記載の計算機であって、
    　前記演算回路は、
    　前記冗長化演算ユニットを複数備え、
    　前記複数の冗長化演算ユニットにそれぞれ接続される複数の前記比較回路と、
    　前記複数の冗長化演算ユニットに接続された前記比較回路のうち、比較結果が一致しないときに、当該冗長化演算ユニットのエラーの発生を検出する制御部をさらに有し、
    　前記制御部は、
    　前記エラーが発生した冗長化演算ユニットの第１の演算ユニットの出力と、前記第２の演算ユニットの出力とを前記多数決回路に接続するように前記セレクタに指令し、
    　前記エラーが発生した冗長化演算ユニットに、現在のデータを前記第３の演算ユニットに転送させ、
    　前記冗長化演算ユニットに前記現在のデータで再度演算を実行させ、前記第３の演算ユニットに前記転送されたデータを演算させ、
    　前記多数決回路は、
    　前記セレクタを介して一時的に３重化された冗長化演算ユニットと第３の演算ユニットの演算結果を受け付けて、多数決処理を行うことを特徴とする計算機。     The computer according to claim 7,
    The arithmetic circuit is:
    A plurality of the redundant arithmetic units are provided,
    A plurality of the comparison circuits respectively connected to the plurality of redundant arithmetic units;
    Among the comparison circuits connected to the plurality of redundant arithmetic units, further comprising a control unit that detects the occurrence of an error in the redundant arithmetic units when the comparison result does not match,
    The controller is
    Instructing the selector to connect the output of the first arithmetic unit of the redundant arithmetic unit in which the error has occurred and the output of the second arithmetic unit to the majority circuit,
    Causing the redundant arithmetic unit in which the error has occurred to transfer the current data to the third arithmetic unit;
    Causing the redundant computing unit to perform the computation again with the current data, causing the third computing unit to compute the transferred data,
    The majority circuit is
    A computer that receives the operation results of the redundant operation unit and the third operation unit that are temporarily tripled through the selector and performs majority processing.
  9. 　請求項７に記載の計算機であって、
    　前記第３の演算ユニットは、
    　前記冗長化演算ユニットで構成されて、前記第１の演算ユニットと第２の演算ユニットの一方を当該第３の演算ユニットとして使用することを特徴とする計算機。     The computer according to claim 7,
    The third arithmetic unit is
    A computer comprising the redundant arithmetic unit, wherein one of the first arithmetic unit and the second arithmetic unit is used as the third arithmetic unit.
  10. 　請求項７に記載の計算機であって、
    　前記第３の演算ユニットは、
    　前記多数決回路に常時接続されることを特徴とする計算機。     The computer according to claim 7,
    The third arithmetic unit is
    A computer that is always connected to the majority circuit.
  11. 　請求項７に記載の計算機であって、
    　前記多数決回路は、
    　前記第１の演算ユニットの演算結果と、前記第２の演算ユニットの演算結果と、前記第３の演算ユニットの演算結果とを受け付けて、他とは異なる演算結果を出力する演算ユニットをエラーが発生した演算ユニットとして特定することを特徴とする計算機。     The computer according to claim 7,
    The majority circuit is
    An error occurs in the arithmetic unit that receives the arithmetic result of the first arithmetic unit, the arithmetic result of the second arithmetic unit, and the arithmetic result of the third arithmetic unit and outputs an arithmetic result different from the others. A computer characterized by being identified as an arithmetic unit that has occurred.
  12. 　請求項７に記載の計算機であって、
    　前記第１の演算ユニットと、第２の演算ユニット及び第３の演算ユニットは、
    　入力を受け付ける第１の演算モジュールと、前記第１の演算モジュールの出力を受け付ける第２の演算モジュールと、第１の演算モジュールの出力と第２の演算モジュールの出力とをクロックに応じて切り替える内部セレクタと、をそれぞれ含み、
    　前記第１の演算ユニットと、第２の演算ユニット及び第３の演算ユニットに同一のクロックを入力することを特徴とする計算機。     The computer according to claim 7,
    The first arithmetic unit, the second arithmetic unit, and the third arithmetic unit are:
    A first arithmetic module that accepts an input, a second arithmetic module that accepts an output of the first arithmetic module, and an internal that switches between the output of the first arithmetic module and the output of the second arithmetic module according to a clock. Each including a selector,
    A computer, wherein the same clock is input to the first arithmetic unit, the second arithmetic unit, and the third arithmetic unit.
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