WO2014201746A1

WO2014201746A1 - Storage device and method for manufacture thereof

Info

Publication number: WO2014201746A1
Application number: PCT/CN2013/079518
Authority: WO
Inventors: 朱慧珑
Original assignee: 中国科学院微电子研究所
Priority date: 2013-06-20
Filing date: 2013-07-17
Publication date: 2014-12-24
Also published as: CN104241289B; CN104241289A

Abstract

Disclosed in the present application are a storage device and method for manufacture thereof. An exemplary storage device may comprise: a substrate; a back gate formed on the substrate; a transistor comprising fins formed on the two opposite sides of the back gate on the substrate; a gate stack formed on the substrate and intersecting the fins; and back gate dielectric layers formed on the bottom surface and side surfaces of the back gate, wherein the back gate floats electrically so as to work as a floating gate for the storage device.

Description

存储器件及其制造方法本申请要求了 2013年 6月 20日提交的、申请号为 201310247278.4、发明名称为 "存储器件及其制造方法" 的中国专利申请的优先权，其全部内容通过引用结合在本申请中。技术领域 The present application claims priority to Chinese Patent Application No. 201310247278.4, filed on Jun. In this application. Technical field

本公开涉及半导体领域，更具体地，涉及一种存储器件及其制造方法。背景技术 The present disclosure relates to the field of semiconductors, and more particularly to a memory device and a method of fabricating the same. Background technique

浮栅晶体管结构一种常见的闪存器件实现方式。然而，随着器件的不断小型化，浮栅中能够存储的电荷越来越少。这导致器件的阔值电压波动并因此导致误差。此外，由于浮栅晶体管结构需要两层栅介质层，因此难以进一步小型化，因为总的栅介质厚度较大。发明内容 Floating Gate Transistor Structure A common implementation of flash memory devices. However, as devices continue to be smaller, less charge can be stored in the floating gate. This causes the device's threshold voltage to fluctuate and thus causes errors. In addition, since the floating gate transistor structure requires two gate dielectric layers, it is difficult to further miniaturize because the total gate dielectric thickness is large. Summary of the invention

本公开的目的至少部分地在于提供一种存储器件及其制造方法。 It is an object of the present disclosure to at least partially provide a memory device and a method of fabricating the same.

根据本公开的一个方面，提供了一种存储器件，包括：衬底；在衬底上形成的背栅；晶体管，包括：在衬底上在背栅的相对两侧形成的鰭；以及在衬底上形成的栅堆叠，所述栅堆叠与鰭相交；以及在背栅的底面和侧面上形成的背栅介质层，其中，背栅电浮置，从而充当该存储器件的浮栅。 According to an aspect of the present disclosure, a memory device is provided, including: a substrate; a back gate formed on the substrate; a transistor including: a fin formed on opposite sides of the back gate on the substrate; and a lining a gate stack formed on the bottom, the gate stack intersecting the fins; and a back gate dielectric layer formed on the bottom surface and sides of the back gate, wherein the back gate is electrically floating to serve as a floating gate of the memory device.

根据本公开的另一方面，提供了一种制造存储器件的方法，包括：在衬底中形成背栅槽；在背栅槽的底壁和侧壁上形成背栅介质层；向背栅槽中填充导电材料，形成背栅；对衬底进行构图，以形成与背栅介质层邻接的鰭；以及在衬底上形成栅堆叠，所述栅堆叠与所述鰭相交，其中，背栅电浮置，从而充当该存储器件的浮栅。 In accordance with another aspect of the present disclosure, a method of fabricating a memory device is provided, comprising: forming a back gate trench in a substrate; forming a back gate dielectric layer on a bottom wall and sidewalls of the back gate trench; toward the back gate trench Filling a conductive material to form a back gate; patterning the substrate to form a fin adjacent to the back gate dielectric layer; and forming a gate stack on the substrate, the gate stack intersecting the fin, wherein the back gate is electrically floating Set to act as the floating gate of the memory device.

根据本发明的示例性实施例，两个鰭之间夹有背栅，从而整体上构成一种三明治鰭（sandwich Fin, 或者简称为 sFin )。以这种 sFin为基础，可以制造三明治鰭式场效应晶体管（sFinFET )。在制造过程中，背栅可以充当鰭的支撑结构，有助于改善结构的可靠性。背栅可以电浮置从而充当浮栅（floating gate ), 从而得到一种浮（背 )栅 sFinFET结构。这种浮（背 )栅 sFinFET结构可以构成存储器件如闪存。 According to an exemplary embodiment of the present invention, a back gate is sandwiched between the two fins to integrally form a sandwich Fin (or simply sFin). Based on this sFin, a sandwich fin field effect transistor (sFinFET) can be fabricated. The back gate can act as a support for the fin during the manufacturing process. Structure helps to improve the reliability of the structure. The back gate can be electrically floating to act as a floating gate, resulting in a floating (back) gate sFinFET structure. Such a floating (back) gate sFinFET structure can constitute a memory device such as a flash memory.

另外，浮 (背 )栅的体积相对较大 (特别是相对于常规浮栅晶体管结构中的浮栅），从而可以降低其中储存的电荷的波动，并因此改善存储器件的可靠性。附图说明 In addition, the volume of the floating (back) gate is relatively large (especially with respect to the floating gate in a conventional floating gate transistor structure), so that the fluctuation of the charge stored therein can be reduced, and thus the reliability of the memory device can be improved. DRAWINGS

通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中： The above and other objects, features and advantages of the present disclosure will become more apparent from

图 1-4是示出了根据本公开一个实施例的存储器件的透视图，其中图 2是示出了图 1所示的存储器件沿 Al-ΑΓ线切开后的透视图，图 3是示出了图 1 所示的存储器件沿 A2-A2'线切开后的透视图，图 4是示出了图 1所示的存储器件沿 B-B'线切开后的透视图； 1-4 are perspective views showing a memory device according to an embodiment of the present disclosure, wherein FIG. 2 is a perspective view showing the memory device shown in FIG. 1 cut along an Al-ΑΓ line, and FIG. 3 is a perspective view. 1 is a perspective view showing the memory device shown in FIG. 1 taken along line A2-A2', and FIG. 4 is a perspective view showing the memory device shown in FIG. 1 taken along line BB';

图 5-24是示出了根据本公开另一实施例的制造存储器件的流程中多个阶段的示意图； 5-24 are schematic diagrams showing a plurality of stages in a process of fabricating a memory device in accordance with another embodiment of the present disclosure;

图 25是示出了根据本公开另一实施例的存储器件的存取原理的示意图。具体实施方式 FIG. 25 is a schematic diagram showing an access principle of a memory device according to another embodiment of the present disclosure. detailed description

以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。 Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that the description is only illustrative, and is not intended to limit the scope of the disclosure. In addition, descriptions of well-known structures and techniques are omitted in the following description in order to avoid unnecessarily obscuring the concept of the present disclosure.

在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域 / 层。 Various structural schematics in accordance with embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, and some details are exaggerated for clarity of presentation and some details may be omitted. The various regions, the shapes of the layers, and the relative sizes and positional relationships therebetween are merely exemplary, and may vary in practice due to manufacturing tolerances or technical limitations, and may be Areas/layers with different shapes, sizes, and relative positions can be additionally designed as needed.

在本公开的上下文中，当将一层 /元件称作位于另一层 /元件 "上" 时，该层 /元件可以直接位于该另一层 /元件上，或者它们之间可以存在居中层 /元件。另外，如果在一种朝向中一层 /元件位于另一层 /元件"上"，那么当调转朝向时，该层 /元件可以位于该另一层 /元件 "下"。 In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, Layers/elements may be located directly on the other layer/element, or a centering layer/element may be present between them. In addition, if one layer/element is "on" another layer/element, the layer/element may be "under" the other layer/element when the orientation is reversed.

根据本公开的实施例，提供了一种存储器件。该存储器件可以包括具有浮栅配置的晶体管，其中由背栅充当浮栅。根据一有利示例，该晶体管可以包括在衬底上在背栅的相对两侧形成的鰭。这样，背栅和鰭形成三明治鰭（sFin ) 结构。晶体管还可以包括在衬底上形成的栅堆叠，该栅堆叠与鰭（以及它们之间的背栅）相交。从而，该晶体管可以配置为 sFinFET。栅堆叠在鰭中限定了沟道区（形成于鰭中与栅堆叠相交的部分），并因此限定了源 /漏区（至少部分地形成于鰭中位于沟道区相对两侧的部分，并且还可以包括例如下面详细描述的在鰭的表面上生长的半导体层）。为了避免栅堆叠和背栅之间的干扰，它们之间可以形成有电介质层并因此电隔离。 According to an embodiment of the present disclosure, a memory device is provided. The memory device can include a transistor having a floating gate configuration in which the back gate acts as a floating gate. According to an advantageous example, the transistor can include fins formed on opposite sides of the back gate on the substrate. Thus, the back gate and fin form a sandwich fin (sFin) structure. The transistor can also include a gate stack formed on the substrate that intersects the fins (and the back gate therebetween). Thus, the transistor can be configured as an sFinFET. The gate stack defines a channel region (formed in the fin that intersects the gate stack) in the fin, and thus defines source/drain regions (at least partially formed in portions of the fin on opposite sides of the channel region, and It may also include, for example, a semiconductor layer grown on the surface of the fin as described in detail below). In order to avoid interference between the gate stack and the back gate, a dielectric layer may be formed between them and thus electrically isolated.

另外，背栅的底面和侧面上可以形成有背栅介质层。背栅介质层可以具有基本上均匀的厚度。通过这样的背栅介质层，可以使背栅电浮置，从而充当 "浮栅"，相应地背栅介质层可以充当 "浮栅介质层"。这样，背栅与背栅介质层一起构成了针对 sFinFET的浮栅配置。这种浮栅配置可以与常规浮栅晶体管中的浮栅配置相似地起作用，只不过在本公开的浮栅配置中，浮栅与控制栅（即，上述栅堆叠 )设于鰭（沟道区 )的不同侧面，而不是如常规技术中那样浮栅和控制栅通常叠置在沟道区上。 In addition, a back gate dielectric layer may be formed on the bottom surface and the side surface of the back gate. The back gate dielectric layer can have a substantially uniform thickness. Through such a back gate dielectric layer, the back gate can be electrically floated to act as a "floating gate", and accordingly the back gate dielectric layer can serve as a "floating gate dielectric layer." Thus, the back gate and the back gate dielectric layer together form a floating gate configuration for the sFinFET. Such a floating gate configuration can function similarly to a floating gate configuration in a conventional floating gate transistor, except that in the floating gate configuration of the present disclosure, the floating gate and the control gate (ie, the above-described gate stack) are disposed on the fin (channel The different sides of the regions, rather than the floating gates and control gates, are typically stacked on the channel region as in the conventional art.

根据一示例 ,背栅介质层的厚度可以被设置为在晶体管导通时允许载流子注入，从而晶体管中的至少一部分载流子（例如，对于 n型器件为电子，对于 p型器件为空穴）能够注入并因此存储到背栅中。例如，这种载流子注入可以通过热载流子注入或 Fowler-Nordheim隧穿等效应而实现。 According to an example, the thickness of the back gate dielectric layer can be set to allow carrier injection when the transistor is turned on, such that at least a portion of the carriers in the transistor are (eg, electrons for the n-type device and empty for the p-type device) The holes can be injected and thus stored in the back gate. For example, such carrier injection can be achieved by effects such as hot carrier injection or Fowler-Nordheim tunneling.

根据另一示例，载流子可以被捕获并存储于背栅介质层中，如同具有 ONO (氧化物 -氮化物-氧化物）电介质叠层的常规闪存中的情况。这种情况下，例如背栅介质层也可以包括 ONO叠层。 According to another example, carriers can be captured and stored in the back gate dielectric layer, as is the case in conventional flash memories with ONO (oxide-nitride-oxide) dielectric stacks. In this case, for example, the back gate dielectric layer may also include an ONO stack.

在利用热载流子注入的示例中，当 sFinFET导通时，载流子可以通过鰭（其中形成沟道区）从其源区流向漏区。于是，可以在漏区附近产生热载流子。例如通过调整晶体管的各端子（例如，与源 /漏区电接触的源 /漏端子）处的偏置，可以使得热载流子注入并存储到浮（背）栅中。另一方面，通过施加不同的偏置，可以使得浮（背）栅中存储的载流子（如果存在的话）排出。这些偏置的施加可以与常规浮栅晶体管中类似。这样，该存储器件可以表现出（至少）两种状态：浮（背）栅中存储有电荷，浮（背）栅中没有存储电荷（例如，可以将浮 (背）栅中存储有电荷的状态认为是逻辑 "1" , 而将浮 (背）栅中没有存储电荷的状态认为是逻辑 "0" ; 反之亦然）。 In the example using hot carrier injection, when the sFinFET is turned on, carriers can flow from their source regions to the drain regions through the fins in which the channel regions are formed. Thus, hot carriers can be generated in the vicinity of the drain region. For example, by adjusting the bias at each terminal of the transistor (eg, the source/drain terminals in electrical contact with the source/drain regions), Hot carriers can be injected and stored into the floating (back) gate. On the other hand, carriers (if present) stored in the floating (back) gate can be discharged by applying different offsets. The application of these biases can be similar to in conventional floating gate transistors. Thus, the memory device can exhibit (at least) two states: a charge is stored in the floating (back) gate, and no charge is stored in the floating (back) gate (eg, a state in which a charge can be stored in the floating (back) gate) It is considered to be a logic "1", and a state in which no charge is stored in the floating (back) gate is considered to be a logic "0"; and vice versa).

另一方面，由于背栅与 sFinFET的鰭之间的相邻设置，背栅中的电荷会影响 sFinFET的阔值电压。这样，根据背栅中存储电荷与否， sFinFET可以表现出不同的阔值电压并因此表现出不同的电学特性。因此，可以根据 sFinFET的电学特性，来读出存储器件的状态（或者， "数据"）。 On the other hand, due to the adjacent arrangement between the back gate and the fins of the sFinFET, the charge in the back gate affects the threshold voltage of the sFinFET. Thus, depending on whether the charge is stored in the back gate, the sFinFET can exhibit different threshold voltages and thus exhibit different electrical characteristics. Therefore, the state of the memory device (or "data") can be read out based on the electrical characteristics of the sFinFET.

在一些示例中，为了电隔离栅堆叠与衬底，该存储器件可以包括在衬底上形成的隔离层，这种隔离层露出 sFin中鰭的一部分（该部分用作 sFinFET的真正鰭，即限定了沟道的宽度），而栅堆叠形成于隔离层上。由于鰭的底部被隔离层遮挡，所以栅堆叠难以对鰭的底部进行有效控制，从而可能造成源漏之间经由鰭底部的漏电流。为抑制这种漏电流， sFinFET可以包括位于鰭的露出部分下方的穿通阻挡部（PTS )。例如，该 PTS可以基本上位于 sFin的鰭中被隔离层遮挡的部分中。 In some examples, to electrically isolate the gate stack from the substrate, the memory device can include an isolation layer formed over the substrate that exposes a portion of the fin in the sFin (this portion serves as the true fin of the sFinFET, ie, is defined The width of the channel), and the gate stack is formed on the isolation layer. Since the bottom of the fin is blocked by the isolation layer, it is difficult for the gate stack to effectively control the bottom of the fin, which may cause leakage current between the source and the drain through the bottom of the fin. To suppress such leakage current, the sFinFET may include a feedthrough barrier (PTS) located below the exposed portion of the fin. For example, the PTS can be located substantially in the portion of the fin of the sFin that is blocked by the isolation layer.

根据一些示例，为了增强器件性能，可以应用应变源 /漏技术。例如，源 / 漏区可以包括与鰭不同材料的半导体层，从而可以向沟道区施加应力。例如，对于 p型器件，可以施加压应力；而对于 n型器件，可以施加拉应力。 According to some examples, strain source/drain techniques may be applied to enhance device performance. For example, the source/drain regions may include a semiconductor layer of a different material than the fins so that stress can be applied to the channel region. For example, for a p-type device, a compressive stress can be applied; and for an n-type device, a tensile stress can be applied.

根据本公开的一些示例，存储器件可以如下来制作。例如，可以在衬底中形成背栅槽，通过向该背栅槽中填充导电材料如金属、掺杂的多晶硅等来形成背栅。另外，在填充背栅槽之前，可以在背栅槽的侧壁和底壁上形成背栅介质层。接下来，可以对衬底进行构图，来形成与背栅介质层邻接的鰭。例如，可以如此对衬底进行构图，使得在背栅槽的侧壁（更具体地，背栅槽侧壁上形成的背栅介质层）上留有衬底的（鰭状）部分。然后，可以在衬底上形成与鰭相交的栅堆叠。 According to some examples of the present disclosure, a memory device can be fabricated as follows. For example, a back gate trench may be formed in the substrate, and a back gate may be formed by filling a conductive material such as metal, doped polysilicon or the like into the back gate trench. Alternatively, a back gate dielectric layer may be formed on the sidewalls and the bottom wall of the back gate trench before filling the back gate trench. Next, the substrate can be patterned to form fins that are adjacent to the back gate dielectric layer. For example, the substrate can be patterned such that a (fin) portion of the substrate remains on the sidewalls of the back gate trench (more specifically, the back gate dielectric layer formed on the sidewalls of the back gate trench). A gate stack that intersects the fins can then be formed on the substrate.

为了便于背栅槽和鰭的构图，根据一有利示例，可以在衬底上形成构图辅助层。该构图辅助层可以被构图为具有与背栅槽相对应的开口，并且在其与开口相对的侧壁上可以形成图案转移层。这样，可以构图辅助层和图案转移层为掩模，来构图背栅槽（以下称作 "第一构图"）；另外，可以图案转移层为掩模，来构图鰭（以下称作 "第二构图"）。 To facilitate patterning of the back gate trenches and fins, according to an advantageous example, a patterning auxiliary layer can be formed on the substrate. The patterning auxiliary layer may be patterned to have an opening corresponding to the back gate groove, and open and open A pattern transfer layer may be formed on the opposite side walls of the mouth. Thus, the auxiliary layer and the pattern transfer layer can be patterned as a mask to pattern the back gate trench (hereinafter referred to as "first pattern"); in addition, the pattern transfer layer can be used as a mask to pattern the fin (hereinafter referred to as "second Composition ").

这样，鰭通过两次构图形成：在第一构图中，形成鰭的一个侧面；而在第二构图中，形成鰭的另一个侧面。在第一构图中，鰭尚与衬底的主体相连并因此得到支撑。另外，在第二构图中，鰭与背栅相连并因此得到支撑。结果，可以防止鰭的制造过程中坍塌，并因此可以更高的产率来制造较薄的鰭。 Thus, the fin is formed by two patterning: in the first pattern, one side of the fin is formed; and in the second pattern, the other side of the fin is formed. In the first pattern, the fins are still connected to the body of the substrate and are thus supported. Additionally, in the second pattern, the fins are connected to the back gate and thus supported. As a result, collapse of the fin during the manufacturing process can be prevented, and thus a thinner fin can be manufactured with higher yield.

在第二构图之前，可以在背栅槽中形成电介质层，以覆盖背栅。该电介质层一方面可以使背栅（例如与栅堆叠）电隔离，另一方面可以防止第二构图对背栅造成影响。 Prior to the second patterning, a dielectric layer may be formed in the back gate trench to cover the back gate. The dielectric layer on the one hand electrically isolates the back gate (e.g., from the gate stack) and on the other hand prevents the second pattern from affecting the back gate.

另外，为了便于构图，根据一有利示例，可以按侧墙（spacer )形成工艺，来在构图辅助层的侧壁上形成图案转移层。由于侧墙形成工艺不需要掩模，从而可以减少工艺中使用的掩模数量。 In addition, in order to facilitate patterning, according to an advantageous example, a pattern transfer layer may be formed on the sidewalls of the patterning auxiliary layer by a spacer forming process. Since the sidewall forming process does not require a mask, the number of masks used in the process can be reduced.

根据一示例，衬底可以包括 Si、 Ge、 SiGe、 GaAs、 GaSb、 AlAs、 InAs、 InP、 GaN、 SiC、 InGaAs、 InSb、 InGaSb, 而构图辅助层可以包括非晶硅。在这种情况下，为了避免在构图背栅槽期间不必要地刻蚀构图辅助层，可以在构图辅助层的顶面上形成保护层。另外，在形成构图辅助层之前，还可以在衬底上形成停止层。对于构图辅助层的构图（以在其中形成开口）可以停止于该停止层。例如，刻蚀保护层可以包括氮化物（如，氮化硅），图案转移层可以包括氮化物，停止层可以包括氧化物（如，氧化硅）。 According to an example, the substrate may include Si, Ge, SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb, InGaSb, and the patterning auxiliary layer may include amorphous silicon. In this case, in order to avoid unnecessarily etching the patterning auxiliary layer during patterning of the back gate trench, a protective layer may be formed on the top surface of the patterning auxiliary layer. Further, a stop layer may be formed on the substrate before the formation of the patterning auxiliary layer. The patterning of the patterning auxiliary layer (to form an opening therein) may stop at the stop layer. For example, the etch protection layer may include a nitride (e.g., silicon nitride), the pattern transfer layer may include a nitride, and the stop layer may include an oxide (e.g., silicon oxide).

另外，根据本公开的一些示例，可以先在形成有 sFin的衬底上形成隔离层，该隔离层露出 sFin (特别是其中的鰭）的一部分。然后，可以在隔离层上形成与 sFin相交的栅堆叠。为了形成上述的 PTS, 可以在形成隔离层之后且在形成栅堆叠之前，进行离子注入。由于 sFin的形状因子及其顶部存在的各电介质层（例如，图案转移层等）， PTS可以基本上形成于 sFin的鰭中被隔离层遮挡的部分中。之后，还可以去除 sFin 中鰭顶部的电介质层（例如，图案转移层等）。这样，随后形成的栅堆叠可以与鰭露出的侧面及顶面接触。 In addition, according to some examples of the present disclosure, an isolation layer may be formed on a substrate on which sFin is formed, which exposes a portion of sFin (particularly, fins therein). A gate stack that intersects sFin can then be formed on the isolation layer. In order to form the PTS described above, ion implantation may be performed after the isolation layer is formed and before the gate stack is formed. Due to the shape factor of sFin and the respective dielectric layers (e.g., pattern transfer layer, etc.) present at the top, the PTS can be formed substantially in the portion of the fin of the sFin that is blocked by the isolation layer. After that, the dielectric layer on the top of the fin in sFin (for example, pattern transfer layer, etc.) can also be removed. In this way, the subsequently formed gate stack can be in contact with the exposed sides and top surface of the fin.

本公开可以各种形式呈现，以下将描述其中一些示例。 The present disclosure can be presented in various forms, some of which are described below.

图 1是示出了根据本公开一个实施例的存储器件的透视图，且图 2是示出了图 1所示的存储器件沿 Al-ΑΓ线切开后的透视图，图 3是示出了图 1所示的存储器件沿 A2-A2'线切开后的透视图，图 4是示出了图 1所示的存储器件沿 B-B'线切开后的透视图。 1 is a perspective view showing a memory device according to an embodiment of the present disclosure, and FIG. 2 is a view 1 is a perspective view of the memory device shown in FIG. 1 taken along the line A2-A2, and FIG. 3 is a perspective view showing the memory device shown in FIG. A perspective view of the memory device shown in Fig. 1 taken along line BB' is shown.

如图 1所示，该存储器件包括衬底 100。衬底 100可以包括体半导体衬底如 Si、 Ge, 化合物半导体衬底如 SiGe、 GaAs、 GaSb、 AlAs、 InAs、 InP、 GaN、 SiC、 InGaAs, InSb、 InGaSb, 绝缘体上半导体衬底 ( SOI )等。为方便说明，以下以体硅衬底以及硅系材料为例进行描述。 As shown in FIG. 1, the memory device includes a substrate 100. The substrate 100 may include a bulk semiconductor substrate such as Si, Ge, a compound semiconductor substrate such as SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb, InGaSb, a semiconductor-on-insulator (SOI), etc. . For convenience of explanation, the following description will be made by taking a bulk silicon substrate and a silicon-based material as an example.

该存储器件还可以包括在衬底上形成的 sFin结构。具体地，该 sFin结构可以包括在衬底上形成的两个鰭 104以及夹于它们之间的背栅 120。鰭 104的宽度例如为约 3-28nm, 且与背栅 120之间夹有背栅介质层 1160。另外，背栅介质层 116还可以形成于背栅 120的底面，使得背栅 120与衬底 100隔开。背栅介质层 116可以包括各种合适的电介质材料，例如氧化物（如氧化硅）和 / 或高 K 电介质，其等效氧化物厚度（EOT )为约 10-30nm。背栅介质层 116 不限于单层结构，也可以是电介质材料的叠层结构。背栅介质层 116在其延伸范围内（特别是在与鰭 104 相对的区域中）可以具有大致均匀的厚度。背栅 120可以包括各种合适的导电材料，如掺杂的多晶硅、金属如 W、金属氮化物如 TiN或其组合，其宽度（图中纸面内水平方向上的维度）例如为约 5-30nm。背栅 120的顶面可以与各鰭 104的顶面基本上持平或高于鰭的顶面。 The memory device can also include an sFin structure formed on the substrate. Specifically, the sFin structure may include two fins 104 formed on the substrate and a back gate 120 sandwiched therebetween. The fin 104 has a width of, for example, about 3-28 nm, and a back gate dielectric layer 1160 is interposed between the back gate 120. Additionally, a back gate dielectric layer 116 may also be formed on the bottom surface of the back gate 120 such that the back gate 120 is spaced from the substrate 100. Back gate dielectric layer 116 may comprise various suitable dielectric materials, such as oxide (e.g., silicon oxide) and/or high K dielectric, having an equivalent oxide thickness (EOT) of about 10-30 nm. The back gate dielectric layer 116 is not limited to a single layer structure, and may be a laminated structure of a dielectric material. The back gate dielectric layer 116 may have a substantially uniform thickness over its extent, particularly in the region opposite the fins 104. The back gate 120 may include various suitable conductive materials such as doped polysilicon, metal such as W, metal nitride such as TiN or a combination thereof, and the width (dimension in the horizontal direction in the drawing) is, for example, about 5 - 30nm. The top surface of the back gate 120 may be substantially flat or higher than the top surface of each fin 104.

衬底 100中可以形成有阱区（未示出）。背栅 120可以进入该阱区中，从而可以经由背栅介质层 116与该阱区形成耦合电容。这可以增大背栅储存电荷的容量，并因此可以降低背栅中储存电荷的波动并因此改善存储器件的可靠性。 A well region (not shown) may be formed in the substrate 100. The back gate 120 can enter the well region, thereby forming a coupling capacitance with the well region via the back gate dielectric layer 116. This can increase the capacity of the back gate to store charge, and thus can reduce fluctuations in stored charge in the back gate and thus improve the reliability of the memory device.

在图 1的示例中，鰭 104与衬底 100—体，由衬底 100的一部分形成。但是，本公开不限于此。例如，鰭 104可通过在衬底 100上外延的另外半导体层形成。 In the example of FIG. 1, the fins 104 are formed integrally with the substrate 100 by a portion of the substrate 100. However, the present disclosure is not limited to this. For example, fins 104 may be formed by additional semiconductor layers epitaxial on substrate 100.

图 1中还示出了位于背栅 120顶面上的电介质层 124。电介质层 124例如可以包括氮化物（如氮化硅）。电介质层 124可以将背栅 120与衬底 100正面 (图 1中上表面）形成的其余部件（例如，栅堆叠）电隔离。 Also shown in FIG. 1 is a dielectric layer 124 on the top surface of the back gate 120. Dielectric layer 124 can include, for example, a nitride such as silicon nitride. Dielectric layer 124 can electrically isolate back gate 120 from the remaining features (e.g., gate stack) formed on the front side of substrate 100 (the upper surface in Figure 1).

另外，图 1中还示出了位于鰭 104顶部的电介质层 106 (例如，氧化物）和 114 (例如，氮化物）。这些电介质层是在该存储器件的制造过程中残留的，它们可以留于鰭 104顶部，或者可以根据需要去除。 In addition, a dielectric layer 106 (eg, oxide) on top of the fins 104 is also shown in FIG. And 114 (for example, nitride). These dielectric layers are left in the manufacturing process of the memory device, they may be left on top of the fins 104, or may be removed as needed.

如图 1-3所示，该存储器件还可以包括在衬底 100上形成的栅堆叠。栅堆叠可以包括栅介质层 138和栅导体层 140。例如，栅介质层 138可以包括高 K 栅介质如 Hf0₂, 厚度为 l-5nm; 栅导体层 140可以包括金属栅导体。另外，栅介质层 138还可以包括一层薄的氧化物（高 K栅介质形成于该氧化物上 ), 例如厚度为 0.3-1.2nm。在栅介质层 138和栅导体 140之间，还可以形成功函数调节层（图中未示出）。另外，栅堆叠两侧形成有栅侧墙 130。例如，栅侧墙 130可以包括氮化物，厚度为约 5-20nm。背栅 220通过其顶面上的电介质层 124与栅堆叠隔离。 As shown in FIGS. 1-3, the memory device can also include a gate stack formed on the substrate 100. The gate stack may include a gate dielectric layer 138 and a gate conductor layer 140. For example, the gate dielectric layer 138 may include a high-k gate dielectric such as Hf0 ₂ having a thickness of 1-5 nm; the gate conductor layer 140 may include a metal gate conductor. In addition, the gate dielectric layer 138 may also include a thin oxide (on which the high-k gate dielectric is formed), for example, having a thickness of 0.3-1.2 nm. Between the gate dielectric layer 138 and the gate conductor 140, a success function adjustment layer (not shown) may also be formed. In addition, a gate spacer 130 is formed on both sides of the gate stack. For example, the gate spacer 130 may include a nitride having a thickness of about 5-20 nm. Back gate 220 is isolated from the gate stack by dielectric layer 124 on its top surface.

另外，在图 1的示例中，该存储器件还包括在衬底上形成的隔离层 102, 栅堆叠通过该隔离层 102与衬底 100隔离。例如，隔离层 102可以包括氧化物 (如，氧化硅）。这里需要指出的是，在某些情况下，例如衬底 100为 SOI衬底的情况下，可以不需要单独形成隔离层 102。鰭 104例如可以通过 SOI衬底中的 SOI半导体形成，而 SOI衬底的埋入绝缘层可以充当这种隔离层。 Additionally, in the example of FIG. 1, the memory device further includes an isolation layer 102 formed over the substrate through which the gate stack is isolated from the substrate 100. For example, the isolation layer 102 can include an oxide (e.g., silicon oxide). It should be noted here that in some cases, such as the case where the substrate 100 is an SOI substrate, it may not be necessary to separately form the isolation layer 102. The fins 104 can be formed, for example, by an SOI semiconductor in an SOI substrate, and the buried insulating layer of the SOI substrate can serve as such an isolation layer.

由于栅堆叠的存在，在 sFin 中限定了沟道区（对应于鰭与栅堆叠相交的部分）和源 /漏区（对应于鰭中位于沟道区相对两侧的部分）。在图 1所示的存可以包括不同于鰭 104的材料，以便能够向鰭 104 (特别是其中的沟道区）施加应力。例如，在鰭 104包括 Si的情况下，对于 n型器件，半导体层 132可以包括 Si:C ( C的原子百分比例如为约 0.2-2% ), 以施加拉应力；对于 p型器件，半导体层 132可以包括 SiGe (例如， Ge的原子百分比为约 15-75% ), 以施加压应力。另外，半导体层 132 的存在还展宽了源 /漏区，从而有利于后继制造与源 /漏区的接触部。 Due to the presence of the gate stack, a channel region (corresponding to the portion where the fin intersects the gate stack) and source/drain regions (corresponding to portions of the fin located on opposite sides of the channel region) are defined in sFin. The reservoir shown in Figure 1 may include a different material than the fins 104 to enable stress to the fins 104, particularly the channel regions therein. For example, in the case where the fin 104 includes Si, for the n-type device, the semiconductor layer 132 may include Si:C (the atomic percentage of C is, for example, about 0.2 to 2%) to apply tensile stress; for the p-type device, the semiconductor layer 132 may include SiGe (eg, an atomic percentage of Ge of about 15-75%) to apply compressive stress. In addition, the presence of the semiconductor layer 132 also broadens the source/drain regions to facilitate subsequent fabrication of contacts with the source/drain regions.

如图 2所示，栅堆叠与鰭 104 (与背栅 120相反一侧 ) 的侧面相交。具体地，栅介质层 138与鰭 104的该侧面接触，从而栅导体层 140可以通过栅介质层 138控制在鰭 104的该侧面上产生导电沟道。因此，该存储器件可以构成双栅器件。另外，在去除鰭 104顶部的电介质层 106和 114的情况下，还可以在鰭 104的顶面上也产生导电沟道，从而该存储器件可以构成四栅器件。如图 2-4所示，背栅 120经由背栅介质层 116与鰭 104相对，从而与背栅介质层 116—起形成针对由栅堆叠（控制栅）和鰭 104构成的 FinFET的浮栅配置。现有技术中针对浮栅的配置同样适用于该示例中的浮（背）栅 120和浮 (背）栅介质层 116 , 除了浮 (背）栅 120的体积可以更大之外。 As shown in FIG. 2, the gate stack intersects the sides of the fins 104 (on the side opposite the back gate 120). Specifically, the gate dielectric layer 138 is in contact with the side of the fin 104 such that the gate conductor layer 140 can control the creation of a conductive channel on the side of the fin 104 through the gate dielectric layer 138. Therefore, the memory device can constitute a dual gate device. Additionally, in the case of removing the dielectric layers 106 and 114 on top of the fins 104, a conductive channel can also be created on the top surface of the fins 104 such that the memory device can constitute a quad-gate device. As shown in FIGS. 2-4, the back gate 120 is opposite the fins 104 via the back gate dielectric layer 116, thereby forming a floating gate configuration for the FinFETs formed by the gate stack (control gate) and the fins 104 together with the back gate dielectric layer 116. . The configuration for the floating gate in the prior art is equally applicable to the floating (back) gate 120 and the floating (back) gate dielectric layer 116 in this example, except that the volume of the floating (back) gate 120 can be larger.

图 5-24是示出了根据本公开另一实施例的制造存储器件的流程中多个阶段的示意图。 5-24 are schematic diagrams showing a plurality of stages in a process of fabricating a memory device in accordance with another embodiment of the present disclosure.

如图 5所示，提供衬底 1000 , 例如体硅衬底。在衬底 1000中，例如通过离子注入，形成有阱区 1000-1。例如，对于 p型器件，可以形成 n型阱区；而对于 n型器件，可以形成 p型阱区。例如， n型阱区可以通过在衬底 1000中注入 n型杂质如 P或 As来形成， p型阱区可以通过在衬底 1000中注入 p型杂质如 B 来形成。如果需要，在注入之后还可以进行退火。本领域技术人员能够想到多种方式来形成 n型阱、 p型阱，在此不再赘述。 As shown in FIG. 5, a substrate 1000, such as a bulk silicon substrate, is provided. In the substrate 1000, a well region 1000-1 is formed, for example, by ion implantation. For example, for a p-type device, an n-type well region can be formed; and for an n-type device, a p-type well region can be formed. For example, the n-type well region can be formed by implanting an n-type impurity such as P or As in the substrate 1000, and the p-type well region can be formed by implanting a p-type impurity such as B into the substrate 1000. If necessary, annealing can also be performed after the implantation. A person skilled in the art can think of various ways to form an n-type well and a p-type well, which will not be described herein.

在衬底 1000 上可以依次形成停止层 1006、构图辅助层 1008 和保护层 1010。例如，停止层 1006可以保护氧化物（如氧化硅），厚度为约 5-25nm; 构图辅助层 1008可以包括非晶硅，厚度为约 50-200nm; 保护层 1010可以包括氮化物（如氮化硅），厚度为约 5-15nm。这些层的材料选择主要是为了在后继处理过程中提供刻蚀选择性。本领域技术人员应当理解，这些层可以包括其他合适的材料，并且其中的一些层在某些情况下可以省略。 A stop layer 1006, a patterning auxiliary layer 1008, and a protective layer 1010 may be sequentially formed on the substrate 1000. For example, the stop layer 1006 can protect an oxide (such as silicon oxide) having a thickness of about 5-25 nm; the patterning auxiliary layer 1008 can comprise amorphous silicon having a thickness of about 50-200 nm; and the protective layer 1010 can include a nitride (such as nitride). Silicon), having a thickness of about 5-15 nm. The choice of materials for these layers is primarily to provide etch selectivity during subsequent processing. Those skilled in the art will appreciate that these layers may include other suitable materials, and some of the layers may be omitted in some cases.

接着，在保护层 1010上可以形成光刻胶 1012。例如通过光刻，对光刻胶 1012 进行构图，以在其中形成与将要形成的背栅相对应的开口。开口的宽度 D1例如可以为约 15-100nm。 Next, a photoresist 1012 may be formed on the protective layer 1010. The photoresist 1012 is patterned, for example, by photolithography to form an opening therein corresponding to the back gate to be formed. The width D1 of the opening may be, for example, about 15-100 nm.

接着，如图 6所示，可以光刻胶 1012为掩模，依次对保护层 1010和构图辅助层 1008进行刻蚀，如反应离子刻蚀（RIE ), 从而在保护层 1010和构图辅助层 1008中形成开口。刻蚀可以停止于停止层 1006。当然，如果构图辅助层 1008与之下的衬底 1000之间具有足够的刻蚀选择性，甚至可以去除这种停止层 1006。之后，可以去除光刻胶 1012。 Next, as shown in FIG. 6, the protective layer 1010 and the patterning auxiliary layer 1008 may be sequentially etched by using the photoresist 1012 as a mask, such as reactive ion etching (RIE), thereby forming the protective layer 1010 and the patterning auxiliary layer 1008. An opening is formed in the middle. Etching can stop at stop layer 1006. Of course, if there is sufficient etch selectivity between the patterning auxiliary layer 1008 and the underlying substrate 1000, such a stop layer 1006 can be removed. Thereafter, the photoresist 1012 can be removed.

然后，如图 7所示，可以在构图辅助层 1008 (与开口相对）的侧壁上，形成图案转移层 1014。图案转移层 1014可以按照侧墙形成工艺来制作。例如，可以通过在图 6所示结构（去除光刻胶 1012 ) 的表面上淀积一层氮化物，然后对氮化物进行 RIE, 来形成侧墙形式的图案转移层。所淀积的氮化物层的厚度可以为约 3-28nm (基本上确定随后形成的鰭的宽度）。这种淀积例如可以通过原子层淀积（ ALD )来进行。本领域技术人员知道多种方式来形成这种侧墙，在此不再赘述。 Then, as shown in FIG. 7, a pattern transfer layer 1014 may be formed on the sidewall of the patterning auxiliary layer 1008 (opposite the opening). The pattern transfer layer 1014 can be fabricated in accordance with a sidewall forming process. For example, a layer of nitride can be deposited on the surface of the structure shown in FIG. 6 (removing photoresist 1012). The nitride is then RIEd to form a pattern transfer layer in the form of a sidewall. The deposited nitride layer may have a thickness of about 3-28 nm (substantially determining the width of the subsequently formed fin). This deposition can be carried out, for example, by atomic layer deposition (ALD). A person skilled in the art knows various ways to form such a side wall, which will not be described herein.

接下来，如图 8所示，可以构图辅助层 1008和图案转移层 1014为掩模，对衬底 1000进行构图，以在其中形成背栅槽 BG。在此，可以依次对停止层 1006和衬底 1000进行 RIE, 来形成背栅槽 BG。由于保护层 1010的存在，这些 RIE不会影响到构图辅助层 1008。当然，如果构图辅助层 1008的材料与停止层 1006和衬底 1000的材料之间具有足够的刻蚀选择性，甚至可以去除保护层 1010。 Next, as shown in FIG. 8, the substrate 1000 may be patterned by patterning the auxiliary layer 1008 and the pattern transfer layer 1014 to form a back gate trench BG therein. Here, the stop layer 1006 and the substrate 1000 may be sequentially subjected to RIE to form the back gate trench BG. These RIEs do not affect the patterning auxiliary layer 1008 due to the presence of the protective layer 1010. Of course, if the material of the patterning auxiliary layer 1008 has sufficient etching selectivity between the material of the stop layer 1006 and the substrate 1000, the protective layer 1010 can be removed.

根据一有利实施例，背栅槽 BG进入到阱区 1000-1中。例如，如图 8所示，背栅槽 BG的底面相比于阱区 1000-1的顶面下凹 D_eap的深度。 D_eap可以在约 20-300匪的范围。 According to an advantageous embodiment, the back gate trench BG enters the well region 1000-1. For example, as shown in FIG. 8, the bottom surface of the back gate trench BG is recessed to a depth of D _eap compared to the top surface of the well region 1000-1. D _eap can be in the range of about 20-300 。.

随后，如图 9所示，可以在背栅槽 BG的侧壁和底壁上形成背栅介质层 1016。背栅介质层 1016可以包括各种合适的电介质材料，如氧化物（如氧化硅 )和 /或高 K栅介质 (如 Hf0₂ ), 其 EOT可以为约 10-30nm。之后，可以在背栅槽 BG 中填充导电材料（例如，掺杂的多晶硅，掺杂浓度可以为约 lE18cm"³-lE21cm"³ ), 来形成背栅 1020。例如，这种背栅介质层 1016和背栅 1020 可以如下形成。具体地，依次淀积一层薄背栅电介质材料（在氧化物的情况下可以通过热氧化形成）和一层厚的导电材料。淀积进行至导电材料完全充满背栅槽 BG, 然后对淀积的导电材料进行回蚀。回蚀后背栅 1020的顶面可以与衬底 1000的表面持平或高于衬底 1000的表面（在该示例中，衬底 1000 的表面对应于随后形成的鰭的顶面）。然后可以对背栅电介质材料进行 RIE。在此，对电介质材料的 RIE可以按照侧墙（spacer )工艺来进行。 Subsequently, as shown in FIG. 9, a back gate dielectric layer 1016 may be formed on the sidewalls and the bottom wall of the back gate trench BG. Back gate dielectric layer 1016 can comprise various suitable dielectric materials, such as oxides (e.g., silicon oxide) and/or high-k gate dielectrics (e.g., Hf0 ₂ ), which can have an EOT of about 10-30 nm. Thereafter, the back gate trench BG may be filled with a conductive material (for example, doped polysilicon, and the doping concentration may be about 1E18 cm" ³ -1 E21 cm" ³ ) to form the back gate 1020. For example, such back gate dielectric layer 1016 and back gate 1020 can be formed as follows. Specifically, a thin back gate dielectric material (which may be formed by thermal oxidation in the case of an oxide) and a thick conductive material are sequentially deposited. The deposition is performed until the conductive material completely fills the back gate trench BG, and then the deposited conductive material is etched back. The top surface of the back gate 1020 after etch back may be flat with or higher than the surface of the substrate 1000 (in this example, the surface of the substrate 1000 corresponds to the top surface of the subsequently formed fin). The back gate dielectric material can then be RIE. Here, the RIE of the dielectric material can be performed in accordance with a spacer process.

为了避免背栅 1020与随后形成的栅堆叠之间的干扰，可以如图 10所示，在背栅槽 BG中进一步填充电介质层 1024, 以覆盖背栅 1020。例如，电介质层 1024可以包括氮化物，且可以通过淀积氮化物然后回蚀来形成。在回蚀过助层 1008。根据一有利示例，在填充电介质层 1024之前，可以例如通过选择性刻蚀，去除背栅 1020表面上方的背栅介质层部分。 In order to avoid interference between the back gate 1020 and the subsequently formed gate stack, a dielectric layer 1024 may be further filled in the back gate trench BG to cover the back gate 1020 as shown in FIG. For example, dielectric layer 1024 can include nitride and can be formed by depositing nitride and then etch back. The help layer 1008 is etched back. According to an advantageous example, before filling the dielectric layer 1024, for example by selection Etching, removing portions of the back gate dielectric layer above the surface of the back gate 1020.

在如上所述形成背栅之后，接下来可以对衬底 1000进行构图，来形成鰭。具体地，如图 11所示，可以通过选择性刻蚀，如通过 TMAH溶液进行湿法刻蚀，来去除构图辅助层 1008, 留下图案转移层 1014。然后，如图 12所示，可以图案转移层 1014为掩模，进一步选择性刻蚀如 RIE停止层 1006和衬底 1000。这样，就在背栅 1020两侧留下了鰭状的衬底部分 1004, 它们对应于图案转移层 1014的形状。 After forming the back gate as described above, the substrate 1000 can next be patterned to form fins. Specifically, as shown in FIG. 11, the patterning auxiliary layer 1008 may be removed by selective etching, such as wet etching by a TMAH solution, leaving the pattern transfer layer 1014. Then, as shown in FIG. 12, the pattern transfer layer 1014 may be used as a mask to further selectively etch such as the RIE stop layer 1006 and the substrate 1000. Thus, finned substrate portions 1004 are left on either side of the back gate 1020, which correspond to the shape of the pattern transfer layer 1014.

这里需要指出的是，尽管在图 12的示例中，将鰭 1004示出为在其中包括阱区 1000-1的一部分，但是本公开不限于此。例如，鰭 1004中可以不包括阱区 1000-1 , 特别是在如下所述形成穿通阻挡部（PTS )的情况下。另外，才艮据本公开的示例，为了使得背栅 1020 (更具体地，背栅中存储的电荷）能够有效地控制鰭 1004, 在竖直方向上鰭 1004的延伸范围优选不超过背栅 1020的延伸范围。 It is to be noted here that although the fin 1004 is shown as including a portion of the well region 1000-1 therein in the example of Fig. 12, the present disclosure is not limited thereto. For example, well region 1000-1 may not be included in fin 1004, particularly where a through via barrier (PTS) is formed as described below. In addition, according to the example of the present disclosure, in order to enable the back gate 1020 (more specifically, the charge stored in the back gate) to effectively control the fin 1004, the extending range of the fin 1004 in the vertical direction preferably does not exceed the back gate 1020 The extent of the extension.

这样，就得到了才艮据该实施例的 sFin结构。如图 12所示，该 sFin结构包括背栅 1020以及位于背栅 1020相对两侧的鰭 1004。另夕卜，在该 sFin中，鰭 1004的顶面被电介质层（包括停止层 1006和图案转移层 1014 )所覆盖。因此，随后形成的栅堆叠可以与每一鰭各自（与背栅 1020相反一侧）的侧面相交，并控制在该侧面中产生沟道，并因此得到双栅器件。 Thus, the sFin structure according to this embodiment is obtained. As shown in FIG. 12, the sFin structure includes a back gate 1020 and fins 1004 on opposite sides of the back gate 1020. In addition, in the sFin, the top surface of the fin 1004 is covered by a dielectric layer (including the stop layer 1006 and the pattern transfer layer 1014). Therefore, the subsequently formed gate stack can intersect the side of each fin (opposite side of the back gate 1020) and control the generation of a channel in the side, and thus a dual gate device.

在通过上述流程得到 sFin之后，可以 sFin为基础，来制造 sFinFET。这里需要指出的是，在图 12所示的示例中，一起形成了三个 sFin。但是本公开不限于此。例如，可以根据需要，形成更多或更少的 sFin。另外，所形成的 sFin的布局也不一定是如图所示的并行设置。 After obtaining sFin through the above process, sFinFET can be fabricated based on sFin. It should be noted here that in the example shown in Figure 12, three sFins are formed together. However, the present disclosure is not limited to this. For example, more or fewer sFins can be formed as needed. In addition, the layout of the formed sFin is not necessarily the parallel arrangement as shown.

在以下，将说明制造 sFinFET的示例方法流程。 In the following, an example method flow for fabricating an sFinFET will be explained.

为制造 sFinFET, 可以在衬底 1000上形成隔离层。例如，如图 13所示，可以在衬底上例如通过淀积形成电介质层 1002 (例如，可以包括氧化物），然后对淀积的电介质层进行回蚀，来形成隔离层。通常，淀积的电介质层可以完全覆盖 sFin , 并且在回蚀之前可以对淀积的电介质进行平坦化，如化学机械抛光（CMP )。根据一优选示例，可以通过溅射来对淀积的电介质层进行平坦化处理。例如，溅射可以使用等离子体，如 Ar或 N等离子体。为改善器件性能，特别是降低源漏泄漏，根据本公开的一示例，如图 14 中的箭头所示，可以通过离子注入来形成穿通阻挡部（PTS ) 1046。例如，对于 n型器件而言，可以注入 p型杂质，如：8、 BF₂或 In; 对于 p型器件，可以注入 n型杂质，如 As或 P。离子注入可以垂直于衬底表面。控制离子注入的参数，使得 PTS形成于鰭 1004位于隔离层 1002表面之下的部分中，并且具有期望的掺杂浓度，例如约 5E17-2E19 cm-³, 并且掺杂浓度应高于衬底中阱区 1000-1 的掺杂浓度。应当注意，由于 sFin的形状因子（细长形）及其顶部存在的各电介质层，有利于在深度方向上形成陡峭的掺杂分布。可以进行退火如尖峰退火、激光退火和 /或快速退火，以激活注入的掺杂剂。这种 PTS有助于减小源漏泄漏。 To fabricate the sFinFET, an isolation layer can be formed over the substrate 1000. For example, as shown in FIG. 13, dielectric layer 1002 (e.g., oxide may be included) may be formed over a substrate, such as by deposition, and then the deposited dielectric layer is etched back to form an isolation layer. Typically, the deposited dielectric layer can completely cover the sFin and the deposited dielectric can be planarized prior to etch back, such as chemical mechanical polishing (CMP). According to a preferred example, the deposited dielectric layer can be planarized by sputtering. For example, sputtering may use a plasma such as an Ar or N plasma. To improve device performance, particularly to reduce source and drain leakage, in accordance with an example of the present disclosure, a through barrier (PTS) 1046 can be formed by ion implantation as indicated by the arrows in FIG. For example, for an n-type device, a p-type impurity such as 8, BF ₂ or In may be implanted; for a p-type device, an n-type impurity such as As or P may be implanted. Ion implantation can be perpendicular to the surface of the substrate. The parameters of the ion implantation are controlled such that the PTS is formed in a portion of the fin 1004 below the surface of the isolation layer 1002 and has a desired doping concentration, such as about 5E17-2E19 cm- ³ , and the doping concentration should be higher than in the substrate. Doping concentration of well region 1000-1. It should be noted that due to the shape factor (elongated shape) of sFin and the respective dielectric layers present at the top thereof, it is advantageous to form a steep doping profile in the depth direction. Annealing such as spike annealing, laser annealing, and/or rapid annealing may be performed to activate the implanted dopant. This PTS helps to reduce source and drain leakage.

接下来，可以在隔离层 1002上形成与 sFin相交的栅堆叠。例如，这可以如下进行。具体地，如图 15所示，例如通过淀积，形成栅介质层 1026。例如，栅介质层 1026可以包括氧化物，厚度为约 0.8-1.5nm。在图 15所示的示例中，仅示出了形成于 sFin顶面和侧面上的栅介质层 1026。但是，栅介质层 1026也可以包括在隔离层 1002的顶面上延伸的部分。然后，例如通过淀积，形成栅导体层 1028。例如，栅导体层 1028可以包括多晶硅。栅导体层 1028可以填充 sFin之间的间隙，并可以进行平坦化处理例如 CMP。 Next, a gate stack intersecting sFin may be formed on the isolation layer 1002. For example, this can be done as follows. Specifically, as shown in Fig. 15, a gate dielectric layer 1026 is formed, for example, by deposition. For example, gate dielectric layer 1026 can comprise an oxide having a thickness of between about 0.8 and 1.5 nm. In the example shown in Fig. 15, only the gate dielectric layer 1026 formed on the top and side faces of the sFin is shown. However, the gate dielectric layer 1026 may also include a portion that extends over the top surface of the isolation layer 1002. Then, a gate conductor layer 1028 is formed, for example, by deposition. For example, gate conductor layer 1028 can comprise polysilicon. The gate conductor layer 1028 can fill the gap between sFins and can be planarized, such as CMP.

如图 16所示，对栅导体层 1028进行构图。在图 16的示例中，栅导体层 1028被构图为与 sFin相交的条形。根据另一实施例，还可以构图后的栅导体层 1028为掩模，进一步对栅介质层 1026进行构图。 As shown in Fig. 16, the gate conductor layer 1028 is patterned. In the example of Fig. 16, the gate conductor layer 1028 is patterned into a stripe shape that intersects sFin. According to another embodiment, the patterned gate conductor layer 1028 can also be used as a mask to further pattern the gate dielectric layer 1026.

在形成构图的栅导体之后，例如可以栅导体为掩模，进行晕圈（halo )注入和延伸区 ( extension ) 注入。 After the patterned gate conductor is formed, for example, a halo implant and an extension implant may be performed using the gate conductor as a mask.

接下来，如图 17 (图 17 ( b )示出了沿图 17 ( a ) 中 C1C1'线的截面图，图 17 ( c )示出了沿图 17 ( a ) 中 C2C2'线的截面图）所示，可以在栅导体层 1028的侧壁上形成栅侧墙 1030。例如，可以通过淀积形成厚度约为 5-20nm的氮化物（如氮化硅），然后对氮化物进行 RIE, 来形成栅侧墙 1030。在此，在形成栅侧墙时可以控制 RIE的量，使得栅侧墙 1030基本上不会形成于 sFin的侧壁上。本领域技术人员知道多种方式来形成这种侧墙，在此不再赘述。 Next, as shown in Fig. 17 (Fig. 17 (b) shows a cross-sectional view taken along line C1C1' in Fig. 17 (a), and Fig. 17 (c) shows a cross-sectional view along line C2C2' in Fig. 17 (a) As shown, the gate spacers 1030 can be formed on the sidewalls of the gate conductor layer 1028. For example, the gate spacer 1030 may be formed by depositing a nitride (e.g., silicon nitride) having a thickness of about 5 to 20 nm and then performing RIE on the nitride. Here, the amount of RIE can be controlled when the gate spacer is formed, so that the gate spacer 1030 is not substantially formed on the sidewall of the sFin. A person skilled in the art knows various ways to form such a side wall, which will not be described herein.

在形成侧墙之后，可以栅导体及侧墙为掩模，进行源 /漏（ S/D )注入。随后，可以通过退火，激活注入的离子，以形成源 /漏区，得到 sFinFET。 After the sidewalls are formed, source/drain (S/D) implantation may be performed using the gate conductor and the sidewall as a mask. With Thereafter, the implanted ions can be activated by annealing to form source/drain regions to obtain an sFinFET.

为改善器件性能，根据本公开的一示例，可以利用应变源 /漏技术。具体地，如图 18 (图 18 ( b )示出了沿图 18 ( a ) 中 BB'线的截面图）所示，首选可以选择性去除外露的栅介质层 1026。然后，可以通过外延，在鰭 1004被栅堆叠露出的部分（对应于源 /漏区）的表面上形成半导体层 1032。根据本公开的一实施例，可以在生长半导体层 1032的同时，对其进行原位掺杂。例如，对于 n型器件，可以进行 n型原位掺杂；而对于 p型器件，可以进行 p型原位掺杂。另外，为了进一步提升性能，半导体层 1032 可以包括不同于鰭 1004 的材料，以便能够向鰭 1004 (其中将形成器件的沟道区）施加应力。例如，在鰭 1004包括 Si的情况下，对于 n型器件，半导体层 1032可以包括 Si:C ( C 的原子百分比例如为约 0.2-2% ),以施加拉应力；对于 p型器件，半导体层 1014 可以包括 SiGe (例如， Ge的原子百分比为约 15-75% ), 以施加压应力。另一方面，生长的半导体层 1032在横向上展宽一定程度，从而有助于随后形成到源 /漏区的接触部。 To improve device performance, strain source/drain techniques can be utilized in accordance with an example of the present disclosure. Specifically, as shown in Fig. 18 (Fig. 18(b) shows a cross-sectional view taken along line BB' in Fig. 18(a)), it is preferred to selectively remove the exposed gate dielectric layer 1026. Then, the semiconductor layer 1032 can be formed on the surface of the portion (corresponding to the source/drain regions) where the fins 1004 are exposed by the gate stack by epitaxy. According to an embodiment of the present disclosure, the semiconductor layer 1032 may be doped in situ while being grown. For example, for n-type devices, n-type in-situ doping can be performed; for p-type devices, p-type in-situ doping can be performed. Additionally, to further enhance performance, the semiconductor layer 1032 can include a different material than the fins 1004 to enable stress to be applied to the fins 1004 where the channel regions of the device will be formed. For example, in the case where the fin 1004 includes Si, for the n-type device, the semiconductor layer 1032 may include Si:C (the atomic percentage of C is, for example, about 0.2 to 2%) to apply tensile stress; for the p-type device, the semiconductor layer 1014 may include SiGe (eg, an atomic percentage of Ge of about 15-75%) to apply compressive stress. On the other hand, the grown semiconductor layer 1032 is stretched to a certain extent in the lateral direction to facilitate subsequent formation of contacts to the source/drain regions.

这样，就得到了一种浮栅配置的存储器件。 Thus, a memory device of a floating gate configuration is obtained.

在上述实施例中，在形成 sFin之后，直接形成了栅堆叠。本公开不限于此。例如，替代栅工艺同样适用于本公开。 In the above embodiment, the gate stack is directly formed after the formation of sFin. The present disclosure is not limited to this. For example, an alternative gate process is equally applicable to the present disclosure.

根据本公开的另一实施例，在图 15 中形成的栅介质层 1026和栅导体层 1028为牺牲栅介质层和牺牲栅导体层（这样，通过结合图 18、 19描述的操作得到的栅堆叠为牺牲栅堆叠）。接下来，可以同样按以上结合图 17描述的操作来形成栅侧墙 1030。另外，同样可以按以上结合图 18描述的操作，来应用应变源 /漏技术。 According to another embodiment of the present disclosure, the gate dielectric layer 1026 and the gate conductor layer 1028 formed in FIG. 15 are a sacrificial gate dielectric layer and a sacrificial gate conductor layer (thus, a gate stack obtained by the operations described in connection with FIGS. 18, 19) To sacrifice the gate stack). Next, the gate spacer 1030 can be formed also in the same manner as described above in connection with FIG. Alternatively, the strain source/drain technique can be applied in the same manner as described above in connection with FIG.

接下来，可以根据替代栅工艺，对牺牲栅堆叠进行处理，以形成器件的真正栅堆叠。例如，这可以如下进行。 Next, the sacrificial gate stack can be processed according to a replacement gate process to form a true gate stack of the device. For example, this can be done as follows.

具体地，如图 19 (图 19 ( b )示出了沿图 19 ( a ) 中 C1C1'线的截面图，图 19 ( c )示出了沿图 19 ( a ) 中 C2C2'线的截面图）所示，例如通过淀积，形成电介质层 1034。该电介质层 1034例如可以包括氧化物。随后，对该电介质层 1034进行平坦化处理例如 CMP。该 CMP可以停止于栅侧墙 1030, 从而露出牺牲栅导体层 1028。随后，如图 20 (图 20 ( a ) 的截面图对应于图 19 ( b ) 的截面图，图 20 ( b ) 的截面图对应于图 19 ( c ) 的截面图 )所示，例如通过 TMAH溶液，选择性去除牺牲栅导体 1028,从而在栅侧墙 1030内侧形成了栅槽 1036。根据另一示例，还可以进一步去除牺牲栅介质层 1026。 Specifically, as shown in Fig. 19 (Fig. 19(b) shows a cross-sectional view taken along line C1C1' in Fig. 19(a), and Fig. 19(c) shows a cross-sectional view along line C2C2' in Fig. 19(a) The dielectric layer 1034 is formed, for example, by deposition. The dielectric layer 1034 can comprise, for example, an oxide. Subsequently, the dielectric layer 1034 is subjected to a planarization process such as CMP. The CMP can stop at the gate spacers 1030 to expose the sacrificial gate conductor layer 1028. Subsequently, as shown in Fig. 20 (the cross-sectional view of Fig. 20(a) corresponds to the cross-sectional view of Fig. 19(b), the cross-sectional view of Fig. 20(b) corresponds to the cross-sectional view of Fig. 19(c), for example, by TMAH The solution selectively removes the sacrificial gate conductor 1028 such that a gate trench 1036 is formed inside the gate spacer 1030. According to another example, the sacrificial gate dielectric layer 1026 can also be further removed.

然后，如图 21 (图 21 ( a )对应于图 20 ( a ) 的截面图，图 21 ( b )对应于图 20 ( b ) 的截面图，图 21 ( c )对应于图 15的截面图）、图 22 (示出了图 21 所示结构的俯视图 )所示，通过在栅槽中形成栅介质层 1038 和栅导体层 1040, 形成最终的栅堆叠。栅介质层 1038可以包括高 K栅介质例如 Hf0₂, 厚度为约 l-5nm。另外，栅介质层 1038还可以包括一层薄的氧化物（高 K栅介质形成于该氧化物上），例如厚度为 0.3-1.2nm。栅导体层 1040可以包括金属栅导体。优选地，在栅介质层 1038和栅导体层 1040之间还可以形成功函数调节层（未示出）。 Then, as shown in Fig. 21 (Fig. 21 (a) corresponds to the cross-sectional view of Fig. 20 (a), Fig. 21 (b) corresponds to the cross-sectional view of Fig. 20 (b), and Fig. 21 (c) corresponds to the cross-sectional view of Fig. 15. 22, a top gate stack is formed by forming a gate dielectric layer 1038 and a gate conductor layer 1040 in the gate trenches, as shown in FIG. 22 (showing a top view of the structure shown in FIG. 21). The gate dielectric layer 1038 can include a high-k gate dielectric such as HfO ₂ having a thickness of about 1-5 nm. In addition, the gate dielectric layer 1038 may further include a thin oxide (the high-k gate dielectric is formed on the oxide), for example, having a thickness of 0.3-1.2 nm. The gate conductor layer 1040 may include a metal gate conductor. Preferably, a success function adjustment layer (not shown) may also be formed between the gate dielectric layer 1038 and the gate conductor layer 1040.

这样，就得到了根据该实施例的 sFinFET。如图 21、 22所示，该 sFinFET 包括在衬底 1000 (或者，隔离层 1002 )上形成的鰭 1004 (与背栅 1020构成 sFin结构 ) 以及与鰭相交的栅堆叠（包括栅介质层 1038和栅导体层 1040 )。如图 21 ( c )清楚所示，栅导体层 1040可以经由栅介质层 1038, 控制鰭 1004 在（与背栅 1020相反一侧的 )侧面上产生导电沟道，从而该 sFinFET是双栅器件。另外，背栅 1020可以与减背栅介质层 1016构成浮栅配置。背栅 1020 可以通过电介质层 1024与栅堆叠电隔离。 Thus, the sFinFET according to this embodiment is obtained. As shown in FIGS. 21 and 22, the sFinFET includes a fin 1004 formed on the substrate 1000 (or the isolation layer 1002) (which forms an sFin structure with the back gate 1020) and a gate stack intersecting the fin (including the gate dielectric layer 1038 and Gate conductor layer 1040). As clearly shown in Fig. 21(c), the gate conductor layer 1040 can control the fin 1004 to create a conductive channel on the side (opposite side of the back gate 1020) via the gate dielectric layer 1038, so that the sFinFET is a dual gate device. In addition, the back gate 1020 may be configured as a floating gate with the reduced back gate dielectric layer 1016. Back gate 1020 can be electrically isolated from the gate stack by dielectric layer 1024.

在如上所述形成 sFinFET之后，还可以制作各种电接触。例如，如图 23 所示，可以在图 22所示结构的表面上淀积层间电介质（ ILD )层 1042。该 ILD 层 1042例如可以包括氧化物。可以对 ILD层 1042进行平坦化处理例如 CMP, 使其表面大致平坦。然后，例如可以通过光刻，形成接触孔，并在接触孔中填充导电材料如金属（例如， W或 Cu等），来形成接触部，例如与栅堆叠的接触部 1044-1、与源 /漏区之一（例如，源区）的接触部 1044-2、与阱区 1000-1 (或者，背栅电容）的接触部 1044-3以及与源 /漏区中另一个（例如，漏区）的接触部 1044-4。 After the formation of the sFinFET as described above, various electrical contacts can also be made. For example, as shown in Fig. 23, an interlayer dielectric (ILD) layer 1042 may be deposited on the surface of the structure shown in Fig. 22. The ILD layer 1042 can comprise, for example, an oxide. The ILD layer 1042 can be planarized, such as CMP, to have a substantially flat surface. Then, for example, a contact hole may be formed by photolithography, and a conductive material such as a metal (for example, W or Cu or the like) may be filled in the contact hole to form a contact portion, for example, a contact portion 1044-1 with the gate stack, and a source/ a contact portion 1044 of one of the drain regions (eg, a source region), a contact portion 1044-3 with the well region 1000-1 (or a back gate capacitance), and another one of the source/drain regions (eg, a drain region) Contact portion 1044-4.

图 24 ( a )、（b )分别示出了沿图 23中 Β1ΒΓ线、 B2B2'线的截面图。如图 24所示，接触部 1044-1穿透 ILD层 1042, 到达栅导体 1040, 并因此与栅导体 1040电接触。该接触部 1044-1可以与存储器件的字线相连。接触部 1044-2 穿透 ILD层 1042以及电介质层 1034, 达到一侧的源 /漏区（在该示例中为半导体层 1032 ),并因此与该侧的源 /漏区（例如，源区）电接触。该接触部 1044-2 可以与存储器件的位线相连。接触部 1044-3穿透 ILD层 1042、电介质层 1034 以及隔离层 1002, 到达衬底 1000 (特别是，其中的阱区 1000-1 ), 并因此与背栅电容电接触。接触部 1044-4穿透 ILD层 1042以及电介质层 1034, 达到另一侧的源 /漏区（在该示例中为半导体层 1032 ), 并因此与该侧的源 /漏区（例如，漏区）电接触。通过这些电接触，可以施加存储器操作如写入、读取等所需的电信号。 24(a) and (b) are cross-sectional views taken along line Β1ΒΓ and line B2B2' of Fig. 23, respectively. As shown in FIG. 24, the contact portion 1044-1 penetrates the ILD layer 1042, reaches the gate conductor 1040, and thus is aligned with the gate. Body 1040 is in electrical contact. The contact portion 1044-1 can be connected to a word line of the memory device. The contact portion 1044-2 penetrates the ILD layer 1042 and the dielectric layer 1034 to reach the source/drain region on one side (the semiconductor layer 1032 in this example), and thus the source/drain regions (eg, source regions) with the side Electrical contact. The contact portion 1044-2 can be connected to a bit line of the memory device. The contact portion 1044-3 penetrates the ILD layer 1042, the dielectric layer 1034, and the isolation layer 1002 to reach the substrate 1000 (particularly, the well region 1000-1 therein) and is thus in electrical contact with the back gate capacitor. The contact portion 1044-4 penetrates the ILD layer 1042 and the dielectric layer 1034 to reach the source/drain region (in this example, the semiconductor layer 1032) on the other side, and thus the source/drain regions (eg, the drain region) ) Electrical contact. Through these electrical contacts, electrical signals required for memory operations such as writing, reading, etc. can be applied.

下面，将结合图 25 (沿图 24 ( b ) 中 D1D1'线的截面图）描述根据本公开实施例的存储器件的工作原理。 Next, the operation of the memory device according to an embodiment of the present disclosure will be described with reference to Fig. 25 (a cross-sectional view taken along line D1D1' in Fig. 24(b)).

当例如通过接触部 1044-1向栅极 1040施加导通电压而使该存储器件（具体地，其中的 sFinFET )导通时，可以存在从源极到漏极的载流子（器件的多数载流子，例如，对于 n型器件，为电子；而对于 p型器件，为空穴）流动。在漏区附近（具体地，漏区的耗尽层附近），可以产生热载流子。如果将接触部 1044-4电浮置，则热载流子可以通过背栅介质层 1016注入并因此存储于背栅 1020 (或者，背栅电容）或背栅介质 1016中，如图 25中的实线箭头所示。在进行这些操作时，可以将接触部 1044-3接地。背栅 1020或背栅介质 1016 中存储有电荷，将引起器件的阔值电压发生变化。 When the storage device (specifically, the sFinFET therein) is turned on, for example, by applying a turn-on voltage to the gate 1040 through the contact portion 1044-1, there may be carriers from the source to the drain (the majority of the device) The flow, for example, is an electron for an n-type device and a hole for a p-type device. Hot carriers can be generated near the drain region (specifically, near the depletion layer of the drain region). If the contact portion 1044-4 is electrically floating, hot carriers can be implanted through the back gate dielectric layer 1016 and thus stored in the back gate 1020 (or back gate capacitance) or back gate dielectric 1016, as in FIG. The solid arrow is shown. When these operations are performed, the contact portion 1044-3 can be grounded. The charge stored in the back gate 1020 or the back gate dielectric 1016 will cause a change in the threshold voltage of the device.

另一方面，在例如通过接触部 1044-1向栅极 1040施加导通电压而使该存储器件（具体地，其中的 sFinFET )导通同时，例如通过接触部 1044-2向源极施加一定的偏置且将接触部 1044-4电浮置时，背栅 1020 (或者，背栅电容）或背栅介质 1016中存储的电荷（如果存在的话）可以隧穿通过背栅介质层 1016 从而被拉出背栅，如图 28中的虚线箭头所示。这样，可以对背栅进行放电。在进行这些操作时，可以将接触部 1044-3接地。背栅 1020 (或者，背栅电容）或背栅介质 1016中存储的电荷被释放之后，器件的阔值电压将发生改变。 On the other hand, the storage device (specifically, the sFinFET therein) is turned on while applying a turn-on voltage to the gate electrode 1040 via the contact portion 1044-1, for example, by applying a certain amount to the source via the contact portion 1044-2. When biased and electrically floating contact 1044-4, back gate 1020 (or back gate capacitance) or charge stored in back gate dielectric 1016 (if present) can tunnel through back gate dielectric layer 1016 to be pulled The back grid is shown as indicated by the dashed arrow in FIG. In this way, the back gate can be discharged. When these operations are performed, the contact portion 1044-3 can be grounded. After the back gate 1020 (or back gate capacitance) or the charge stored in the back gate dielectric 1016 is released, the device's threshold voltage will change.

在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。 In the above description, detailed descriptions of the technical details such as patterning and etching of the respective layers have not been made. However, it should be understood by those skilled in the art that layers, regions, and the like of a desired shape can be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design and The methods described above are not exactly the same. In addition, although the respective embodiments have been described above, this does not mean that the measures in the respective embodiments are not advantageously used in combination.

以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。 The embodiments of the present disclosure have been described above. However, the examples are for illustrative purposes only and are not intended to limit the scope of the disclosure. The scope of the disclosure is defined by the appended claims and their equivalents. Numerous alternatives and modifications may be made by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to fall within the scope of the present disclosure.

Claims

权利要求书 Claim

1. 一种存储器件，包括： A storage device comprising:

衬底； Substrate

在衬底上形成的背栅； a back gate formed on the substrate;

晶体管，包括：在衬底上在背栅的相对两侧形成的鰭；以及在衬底上形成的栅堆叠，所述栅堆叠与鰭相交；以及 a transistor comprising: a fin formed on opposite sides of a back gate on a substrate; and a gate stack formed on the substrate, the gate stack intersecting the fin;

在背栅的底面和侧面上形成的背栅介质层， a back gate dielectric layer formed on the bottom surface and side surfaces of the back gate,

其中，背栅电浮置，从而充当该存储器件的浮栅。 Wherein, the back gate is electrically floating to serve as a floating gate of the memory device.

2. 根据权利要求 1所述的存储器件，其中，背栅介质层的厚度被设置为在晶体管导通时允许载流子注入，从而晶体管中的至少一部分载流子能够注入并因此存储到背栅中。 2. The memory device according to claim 1, wherein a thickness of the back gate dielectric layer is set to allow carrier injection when the transistor is turned on, so that at least a part of carriers in the transistor can be injected and thus stored to the back In the grid.

3. 根据权利要求 2所述的存储器件，其中，所述载流子注入包括热载流子注入，或者由于 Fowler-Nordheim隧穿而导致的载流子注入。 3. The memory device of claim 2, wherein the carrier injection comprises hot carrier injection, or carrier injection due to Fowler-Nordheim tunneling.

4. 根据权利要求 1所述的存储器件，其中，载流子被捕获并存储于背栅介质层中。 4. The memory device of claim 1, wherein the carriers are captured and stored in the back gate dielectric layer.

5. 根据权利要求 1所述的存储器件，其中，背栅介质层具有大致均匀的厚度。 5. The memory device of claim 1, wherein the back gate dielectric layer has a substantially uniform thickness.

6. 根据权利要求 1所述的存储器件，其中，背栅介质层包括氧化物和 / 或高 K电介质，且其等效氧化物厚度 EOT为约 10-30nm。 6. The memory device of claim 1, wherein the back gate dielectric layer comprises an oxide and/or a high K dielectric and has an equivalent oxide thickness EOT of about 10-30 nm.

7. 根据权利要求 1所述的存储器件，其中，衬底中包括阱区，其中背栅进入阱区中约 20-300nm。 7. The memory device of claim 1, wherein the substrate includes a well region, wherein the back gate enters the well region by about 20-300 nm.

8. 根据权利要求 1所述的存储器件，其中，背栅的顶面与各鰭的顶面基本上持平或高于鰭的顶面。 8. The memory device of claim 1, wherein a top surface of the back gate is substantially flat or higher than a top surface of each fin.

9. 根据权利要求 1所述的存储器件，其中，背栅包括导电材料，且宽度为 5-30nm。 9. The memory device of claim 1, wherein the back gate comprises a conductive material and has a width of 5-30 nm.

10. 根据权利要求 1所述的存储器件，其中，鰭包括 Si、 Ge、 SiGe、 GaAs、 GaSb、 AlAs、 InAs、 InP、 GaN、 SiC、 InGaAs, InSb、 InGaSb, 且宽度为约 3-28匪。 10. The memory device of claim 1, wherein the fins comprise Si, Ge, SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb, InGaSb, and have a width of about 3-28 匪. .

11. 根据权利要求 1所述的存储器件，还包括在每一鰭位于栅堆叠相对两侧的部分的表面上生长的半导体层。 11. The memory device of claim 1, further comprising a semiconductor layer grown on a surface of a portion of each of the fins on opposite sides of the gate stack.

12. 根据权利要求 1所述的存储器件，还包括： 12. The memory device of claim 1, further comprising:

在衬底上形成的隔离层，所述隔离层露出鰭的一部分，其中，栅堆叠通过隔离层与衬底电隔离；以及 An isolation layer formed on the substrate, the isolation layer exposing a portion of the fin, wherein the gate stack is electrically isolated from the substrate by the isolation layer;

在所述鰭被隔离层露出的部分下方形成的穿通阻挡部，所述穿通阻挡部的掺杂浓度高于阱区的掺杂浓度。 A punch-through barrier formed under a portion where the fin is exposed by the isolation layer, the doping concentration of the punch-through barrier being higher than a doping concentration of the well region.

13. 一种制造存储器件的方法，包括： 13. A method of fabricating a memory device, comprising:

在衬底中形成背栅槽； Forming a back gate trench in the substrate;

在背栅槽的底壁和侧壁上形成背栅介质层； Forming a back gate dielectric layer on the bottom wall and the sidewall of the back gate trench;

向背栅槽中填充导电材料，形成背栅； Filling the back gate trench with a conductive material to form a back gate;

对衬底进行构图，以形成与背栅介质层邻接的鰭；以及 Patterning the substrate to form a fin adjacent to the back gate dielectric layer;

在衬底上形成栅堆叠，所述栅堆叠与所述鰭相交， Forming a gate stack on the substrate, the gate stack intersecting the fins,

14. 根据权利要求 13所述的方法，其中， 14. The method according to claim 13, wherein

形成背栅槽包括： Forming the back gate trench includes:

在衬底上形成构图辅助层，该构图辅助层被构图为具有与背栅槽相对应的开口； Forming a patterning auxiliary layer on the substrate, the patterning auxiliary layer being patterned to have an opening corresponding to the back gate trench;

在构图辅助层与开口相对的侧壁上形成图案转移层； Forming a pattern transfer layer on a sidewall of the patterning auxiliary layer opposite to the opening;

以该构图辅助层及图案转移层为掩模，对衬底进行刻蚀，以形成背栅槽，以及 Etching the substrate with the patterning auxiliary layer and the pattern transfer layer as a mask to form a back gate trench, and

形成鰭包括： Forming the fins includes:

选择性去除构图辅助层；以及 Selectively removing the patterning auxiliary layer;

以图案转移层为掩模，对衬底进行刻蚀，以形成鰭。 The substrate is etched using the pattern transfer layer as a mask to form fins.

15. 根据权利要求 14所述的方法，其中，衬底包括 Si、 Ge、 SiGe、 GaAs、 GaSb、 AlAs、 InAs、 InP、 GaN、 SiC、 InGaAs, InSb、 InGaSb, 构图辅助层包括非晶硅，以及 15. The method according to claim 14, wherein the substrate comprises Si, Ge, SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb, InGaSb, and the patterning auxiliary layer comprises amorphous silicon, as well as

该方法还包括：在构图辅助层的顶面上形成保护层，以在背栅槽的刻蚀期间保护构图辅助层。 The method also includes forming a protective layer on a top surface of the patterning auxiliary layer to protect the patterning auxiliary layer during etching of the back gate trench.

16. 根据权利要求 15所述的方法, 还包括：在衬底上形成停止层，构图辅助层形成于该停止层上。 16. The method of claim 15, further comprising: forming a stop layer on the substrate, the patterned auxiliary layer being formed on the stop layer.

17. 根据权利要求 16所述的方法, 其中，保护层包括氮化物，图案转移层包括氮化物，停止层包括氧化物。 17. The method of claim 16, wherein the protective layer comprises a nitride, the pattern transfer layer comprises a nitride, and the stop layer comprises an oxide.

18. 根据权利要求 14所述的方法, 其中，按侧墙形成工艺，在构图辅助层的侧壁上形成图案转移层。 18. The method according to claim 14, wherein the pattern transfer layer is formed on the sidewall of the patterning auxiliary layer by a sidewall forming process.