WO2014192429A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2014192429A1 WO2014192429A1 PCT/JP2014/060243 JP2014060243W WO2014192429A1 WO 2014192429 A1 WO2014192429 A1 WO 2014192429A1 JP 2014060243 W JP2014060243 W JP 2014060243W WO 2014192429 A1 WO2014192429 A1 WO 2014192429A1
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- esd protection
- electrode
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- electrodes
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Definitions
- the present invention relates to a semiconductor device including a rewiring layer on a semiconductor substrate on which a functional element is formed.
- One of the semiconductor devices is an ESD (Electro-Static-Discharge) protection device.
- the ESD protection device protects semiconductor ICs and the like from surges such as electrostatic discharge.
- Various electronic devices such as a mobile communication terminal, a digital camera, and a notebook PC are provided with a semiconductor integrated circuit constituting a logic circuit or a memory circuit.
- Such a semiconductor integrated circuit is a low-voltage driving circuit composed of a fine wiring pattern formed on a semiconductor substrate, and is generally vulnerable to a surge caused by electrostatic discharge or the like. Therefore, an ESD protection device is used to protect such a semiconductor integrated circuit from a surge.
- Patent Document 1 discloses an ESD protection device in which a rewiring layer containing an epoxy resin is formed on the surface of a Si substrate on which an ESD protection circuit is configured. A wiring electrode that is electrically connected to the Si substrate is formed on the resin layer of the rewiring layer.
- This Patent Document 1 is a CSP (Chip Size Package) type device, which realizes miniaturization.
- Patent Document 1 there may be a gap between the wiring electrode and the resin layer in the rewiring layer during manufacturing, and impurities such as moisture may enter from the gap, and the wiring electrode may be oxidized or corroded. is there. In this case, there is a problem that the resistance value of the wiring electrode increases due to the corrosion, and the clamp voltage during electrostatic discharge cannot be lowered.
- an object of the present invention is to provide a semiconductor device that avoids an increase in resistance value of the wiring electrode due to oxidation or corrosion of the wiring electrode.
- the semiconductor device includes a semiconductor substrate on which a functional element is formed, a metal film formed on the functional element formation surface of the semiconductor substrate and connected to the functional element, and the functional element formation on the semiconductor substrate.
- An insulating layer formed on the surface; a wiring electrode formed on the insulating layer so as to oppose the functional element formation surface of the semiconductor substrate; and a conductive electrode connected to the metal film; and formed on a part of the wiring electrode.
- an insulating resin layer formed on the insulating layer. The opening is formed so as to expose a part of the inner side of the outer electrode in a plan view.
- the wiring electrode has a Ti film on a surface layer other than a portion where the external electrode is formed, a main material is Cu, and the external electrode is a film formed by plating the wiring electrode Is preferred.
- the bonding strength between the insulating resin layer and the wiring electrode is increased by forming the Ti film.
- the external electrode can be selectively plated without forming a resist film by having a Ti film on the surface layer other than the portion where the external electrode is formed, the manufacture is facilitated.
- the functional element is an ESD protection circuit and the wiring electrode is an ESD current path.
- the present invention since no gap is formed between the external electrode and the resin layer, it is possible to prevent a problem such that an impurity such as moisture enters the gap and the electrode is oxidized or corroded. As a result, an increase in the resistance value of the wiring electrode can be prevented, and an increase in loss at the wiring electrode can be avoided.
- FIG. 1 Front sectional view of an ESD protection device according to an embodiment Plan view of each layer of ESD protection device
- the figure which shows the example of a connection of the ESD protection device which concerns on embodiment The figure which shows the example of a connection of the ESD protection device which concerns on embodiment
- the figure for demonstrating the principle of operation of the ESD protection device which concerns on embodiment The figure for demonstrating the principle of operation of the ESD protection device which concerns on embodiment
- the figure which shows another example of the opening which exposes a part of external electrode The figure which shows another example of the opening which exposes a part of external electrode
- FIG. 1 is a front sectional view of an ESD protection device 1 according to this embodiment.
- FIG. 2 is a plan view of each layer of the ESD protection device 1.
- the ESD protection device 1 is a CSP type device, and a rewiring layer 20 including a plurality of resin layers and the like is formed on a Si substrate 10 on which an ESD protection circuit 10A including a diode and a Zener diode is configured.
- the Si substrate 10 corresponds to the semiconductor substrate according to the present invention, but the semiconductor substrate according to the present invention is not limited to the Si substrate, and may be a GaAs substrate or the like.
- FIG. 3 is a diagram showing a planar configuration of the ESD protection circuit 10A formed on the Si substrate 10
- FIG. 4 is a circuit diagram of the ESD protection circuit 10A.
- FIG. 5 is a cross-sectional view of a main part of the ESD protection device 1 according to this embodiment.
- an element formation layer 10 ⁇ / b> L for forming a plurality of elements is provided on the surface of a p + Si substrate 10.
- An element isolation region 110 is formed. These element isolation regions 110 are trench isolations in which a Si oxide film (SiOx) is formed on the inner surface of a trench and polysilicon is filled therein. Two elements separated by the element isolation region 110 (two elements sandwiching the element isolation region 110) are n epitaxial layers that are opposite to the type (p +) of the semiconductor substrate 10 on the surface of the element formation layer 10L. I have. Thus, diodes D1a, D1b, D3a, D3b, D2, D4, and Zener diodes are formed on the surface and thickness direction of the Si substrate 10.
- An Al electrode 10B and Al pads (hereinafter referred to as pads) P1 and P2 are provided on the surface layer of the Si substrate 10, and these elements form the circuit shown in FIG.
- the diodes D1a and D1b are represented as one diode D1
- the diodes D3a and D3b are represented as one diode D3.
- the formed diodes D1, D2 are aligned in the forward direction and connected in series, and the diodes D3, D4 are aligned in the forward direction and connected in series.
- the diodes D1 and D2 and the diodes D3 and D4 connected in series are aligned in the forward direction and connected in parallel to the Zener diode Dz.
- a Zener diode Dz is interposed between the formation positions of the diodes D1 and D4 and between the formation positions of the diodes D2 and D3.
- a connection point between the formed diodes D1a and D1b and the diode D2 serves as a first input / output terminal of the ESD protection circuit 10A and is connected to a pad P1 formed on the Si substrate 10.
- a connection point between the formed diodes D3a and D3b and the diode D4 serves as a second input / output terminal of the ESD protection circuit 10A and is connected to an Al pad (hereinafter referred to as a pad) P2 formed on the Si substrate 10. is doing.
- the pads P1 and P2 correspond to the metal film according to the present invention.
- the rewiring layer 20 formed on the surface layer of the Si substrate 10 is SiN (or SiO 2 ) formed on the surface (functional element formation surface) of the Si substrate 10 so as to cover a part of the peripheral portion of the pads P1 and P2.
- the protective film 21 and the resin layer 22 covering the SiN protective film 21 and the pads P1 and P2 are included.
- the SiN protective film 21 is formed by sputtering, and the resin layer 22 is formed by spin coating of an epoxy (or polyimide) solder girest.
- openings (contact holes) 22A and 22B for exposing parts of the pads P1 and P2 are formed.
- Ti / Cu / Ti electrodes 21A and 21B are formed in the openings 22A and 22B and the peripheral regions of the openings 22A and 22B.
- FIG. 1 only the Ti / Cu / Ti electrode 21B is illustrated, but the Ti / Cu / Ti electrode 21B is formed by laminating a Ti electrode 211, a Cu electrode 212, and a Ti electrode 213 in order from the resin layer 22 side.
- the Ti / Cu / Ti electrode 21A has the same structure.
- Ti / Cu / Ti electrodes 21 ⁇ / b> A and 21 ⁇ / b> B have a planar portion facing the surface of Si substrate 10, and are electrically connected to pads P ⁇ b> 1 and P ⁇ b> 2 through the opening of resin layer 22.
- the Ti / Cu / Ti electrodes 21 ⁇ / b> A and 21 ⁇ / b> B are current paths for surge current (ESD current) of the ESD protection device 1.
- External electrodes 23A and 23B are formed on part of the planar portions of the Ti / Cu / Ti electrodes 21A and 21B. Although only the external electrode 23B is shown in FIG. 1, the external electrode 23B has a Ni electrode 231 formed on the Ti / Cu / Ti electrode 21B side, and an Au electrode 232 formed on the surface of the Ni electrode 231. Yes.
- the external electrode 23A has a similar structure. The portions of the Ti / Cu / Ti electrodes 21A and 21B where the external electrodes 23A and 23B are formed are such that the Ti electrode 213 is etched and the Cu electrode 212 is exposed, and the external electrodes 23A and 23B are exposed Cu electrodes 212. Part is selectively plated.
- the external electrodes 23A and 23B are electrodes for input / output terminals of the ESD protection device 1.
- the rewiring layer 20 includes a resin layer 26 further formed on the resin layer 22.
- the resin layer 26 is, for example, a low dielectric constant epoxy resin (or polyimide resin, liquid crystal polymer, or the like) layer. Since the Ti / Cu / Ti electrodes 21A and 21B have the Ti electrode 213 on the surface layer, the bonding strength between the Ti / Cu / Ti electrodes 21A and 21B and the resin layer 26 is high. Openings (via holes) 26 ⁇ / b> A and 26 ⁇ / b> B are formed in the resin layer 26. The openings 26A and 26B expose part of the external electrodes 23A and 23B. In the figure showing the resin layer 26 in FIG.
- the external electrodes 23A and 23B are indicated by broken lines, and the relationship with the openings 26A and 26B is shown. As shown, the peripheral portions of the external electrodes 23A and 23B are covered with the resin layer 26, and the inner sides of the peripheral portions are exposed from the openings 26A and 26B.
- the distance from the openings 26A and 26B of the resin layer 26 to the joints of the Ti / Cu / Ti electrodes 21A and 21B and the external electrodes 23A and 23B is increased. . For this reason, impurities such as moisture that have entered from the openings 26A and 26B are unlikely to enter the joint portions, and corrosion of the exposed Cu portions of the Ti / Cu / Ti electrodes 21A and 21B can be prevented.
- the ESD protection device 1 when the ESD protection device 1 is soldered and mounted on a substrate, a load is generated on the external electrodes 23A and 23B due to a deflection of the substrate to be mounted or an impact on the substrate, and the external electrodes 23A and 23B are caused by the load. There is a possibility that the edge portion of 23B is turned over. Therefore, by covering the peripheral portions of the external electrodes 23A and 23B with the resin layer 26, the edge portions of the external electrodes 23A and 23B can be prevented from being turned over, and the intrusion of impurities can be further avoided. Even if a gap is formed at the interface due to the difference in thermal expansion coefficient between the external electrodes 23A and 23B and the resin layer 26, the peripheral edges of the external electrodes 23A and 23B are covered with the resin layer. Intrusion can be avoided.
- the Zener diode Dz or the like is formed on the Si substrate 10 to configure the ESD protection circuit 10A.
- a variable capacitance element or the like is formed on the Si substrate 10 and used. May be configured.
- FIGS 6A and 6B are diagrams showing connection examples of the ESD protection device 1 according to the present embodiment.
- the ESD protection device 1 is mounted on an electronic device. Examples of electronic devices include notebook PCs, tablet terminal devices, mobile phones, digital cameras, DVC (Digital Video Cassette), and portable music players.
- electronic devices include notebook PCs, tablet terminal devices, mobile phones, digital cameras, DVC (Digital Video Cassette), and portable music players.
- FIG. 6A shows an example in which the ESD protection device 1 is connected between the signal line connecting the I / O port 100 and the IC 101 to be protected and GND.
- the I / O port 100 is a port to which an antenna is connected, for example.
- the ESD protection device 1 according to the present embodiment is a bidirectional type, and either the first input / output terminal or the second input / output terminal may be on the input side. For example, when the first input / output terminal is the input side, the first input / output terminal is connected to the signal line, and the second input / output terminal is connected to the GND.
- the surge current is discharged from the ESD protection device 1 to the ground.
- the ESD protection device 1 prevents corrosion of exposed Cu. If Cu corrodes due to the intrusion of impurities, the resistance value of the current path of the ESD protection device 1 indicated by the broken line in FIG. 6A increases. In this case, the surge current is not discharged to the ground by this resistance, and the ESD protection device 1 does not function normally. In this embodiment, since corrosion of Cu is prevented, an increase in the resistance value indicated by the broken line in FIG. 6A can be prevented, and the ESD protection device 1 can function normally by lowering the clamp voltage at the time of occurrence of ESD. Can do.
- FIG. 6B shows an example in which the ESD protection device 1 is connected between the signal line connecting the connector 102 and the IC 101 and the GND line.
- the signal line in this example is, for example, a high-speed transmission line (differential transmission line), and the ESD protection device 1 is connected between each of the plurality of signal lines and the GND line.
- the ESD protection device 1 uses the external electrodes 23A and 23B as the first input / output terminal and the second input / output terminal, and is connected between the signal line and the GND line.
- This signal line is a line connected to an input / output terminal of an IC (not shown) to be protected from electrostatic discharge voltage.
- the ESD protection device according to this embodiment is a bidirectional type, and either the first input / output terminal or the second input / output terminal may be on the input side. For example, when the first input / output terminal is the input side, the first input / output terminal is connected to the signal line, and the second input / output terminal is connected to the GND line.
- FIG. 7 is a diagram for explaining a case where a current flows from the pad P1 connected to the first input / output terminal (external electrode 23A) to the pad P2 connected to the second input / output terminal (external electrode 23B).
- a surge voltage exceeding the Zener voltage of the Zener diode Dz is applied, the surge current that has entered from the first input terminal is routed from the pad P1 to the diode D1, the Zener diode Dz, and the diode D4, as indicated by the broken line in the figure. And discharged from the pad P2 to the ground.
- FIG. 8 is a diagram for explaining a case where a current flows from the pad P2 connected to the second input / output terminal (external electrode 23B) to the pad P1 connected to the first input / output terminal (external electrode 23A).
- the surge current that has entered from the second input terminal flows from the pad P2 through the diode D3, the Zener diode Dz, and the diode D2, and is discharged from the pad P1 to the ground.
- FIG. 9 is a diagram illustrating a manufacturing process of the ESD protection device 1.
- the ESD protection device 1 is manufactured by the following process.
- pads P1 and P2 that are electrically connected to the ESD protection circuit 10A are formed on the Si substrate 10 on which the ESD protection circuit 10A is formed by photolithography. Further, the SiN protective film 21 is sputtered on the substrate surface, and openings H1 and H2 are formed by etching.
- the parasitic capacitance formed between the pads P1 and P2 and the opposing substrate can be reduced by reducing their area.
- By reducing the parasitic capacitance it is possible to suppress an impedance shift, and as a result, it is possible to reduce the loss of the high-frequency signal in the signal line.
- the resin layer 22 is formed on the Si substrate 10 by spin coating with an epoxy solder girest, and then the openings 22A and 22B are formed.
- a Ti electrode 211, a Cu electrode 212, and a Ti electrode 213 are formed on the surface of the resin layer 22 by sputtering at a thickness of about 0.1 ⁇ m / 1.0 ⁇ m / 0.1 ⁇ m. After that, wet etching is performed to form the electrodes 21A and 21B.
- a part of the surface of the Ti / Cu / Ti electrodes 21A and 21B is etched to expose Cu, and the exposed Cu portion is exposed to Au on the surface of the Ni electrode 231 as described in FIG.
- the Au / Ni external electrodes 23A and 23B formed by the electrode 232 are formed by electrolytic plating (electroplating) with a thickness of about 0.1 ⁇ m / 3.0 ⁇ m.
- the external electrodes 23A and 23B are selectively plated only on the exposed Cu surface. By forming the external electrodes 23A and 23B by selective plating, a resist film is not formed, and masking is not required, so that manufacturing is facilitated.
- the resin layer 26 is formed on the surface of the resin layer 22 by spin coating with epoxy solder girest. Openings 26A and 26B are formed in the resin layer 26. At this time, the peripheral portions of the external electrodes 23A and 23B are covered with the resin layer 26, and the inner sides of the peripheral portions are exposed from the openings 26A and 26B.
- the external electrodes 23A and 23B by electrolytic plating and then forming the resin layer 26, it is possible to avoid the possibility that the plating solution remains and the Ti / Cu / Ti electrodes 21A and 21B are corroded. By avoiding the corrosion, it is possible to prevent an increase in the resistance value of the Ti / Cu / Ti electrodes 21A and 21B that become a path of the surge current of the device 1 by ESD protection.
- FIG. 10A, 10B, and 10C are diagrams showing another example of the openings 26A and 26B that expose part of the external electrodes 23A and 23B.
- the corners of the openings 26A and 26B may be curved to protect the portions (corners) where cracks are likely to occur.
- FIG. 10B only the opening 26A may have a shape in which the central portion protrudes inward. In this case, for example, by making the openings 26A and 26B have different shapes, the direction of the ESD protection element 1 can be easily recognized. Further, as shown in FIG.
- each of the openings 26A and 26B may be divided (subdivided) into two.
- the ESD protection element 1 may be mounted with an inclination due to the difference in the amount of solder when the ESD protection element 1 is mounted, but the inclination can be suppressed by subdividing the openings 26A and 26B.
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Abstract
SED保護デバイス(1)は、ESD保護回路(10A)が形成されたSi基板(10)と、Si基板(10)に形成され、ESD保護回路(10A)の入出力端となるパッド(P1,P2)と、Si基板(10)に形成された樹脂層(22)と、樹脂層(22)に形成され、パッド(P1,P2)に導通するTi/Cu/Ti電極(21A,21B)と、Ti/Cu/Ti電極(21A,21B)の一部に形成された外部電極(23A,23B)と、平面視で外部電極(23A,23B)の周縁部より内側の一部を露出させる開口(26A,26B)が形成された樹脂層(26)とを備える。これにより、配線電極の酸化又は腐食による配線電極の抵抗値増大を回避した半導体装置を提供する。
Description
本発明は、機能素子が形成された半導体基板上に再配線層を備える半導体装置に関する。
半導体装置の一つとしてESD(Electro-Static-Discharge)保護デバイスがある。ESD保護デバイスは半導体IC等を静電気放電などのサージから保護する。移動体通信端末、デジタルカメラ、ノート型PCをはじめとする各種電子機器には、ロジック回路又はメモリー回路等を構成する半導体集積回路が備えられている。このような半導体集積回路は、半導体基板上に形成された微細配線パターンで構成された低電圧駆動回路であるため、一般に、静電気放電などによるサージに対しては脆弱である。そこで、このような半導体集積回路をサージから保護するため、ESD保護デバイスが用いられる。
特許文献1には、ESD保護回路が構成されたSi基板の表面に、エポキシ樹脂を含む再配線層が形成されたESD保護デバイスが開示されている。再配線層の樹脂層には、Si基板と導通する配線電極が形成されている。この特許文献1は、CSP(Chip Size Package)タイプのデバイスであり小型化を実現している。
しかしながら、特許文献1において、製造時に、再配線層における配線電極と樹脂層との間に隙間が生じる場合があり、その隙間から水分などの不純物が侵入し、配線電極が酸化又は腐食するおそれがある。この場合、その腐食により、配線電極の抵抗値が大きくなり、静電気放電時のクランプ電圧を低くできないといった問題がある。
そこで、本発明の目的は、配線電極の酸化又は腐食による配線電極の抵抗値増大を回避した半導体装置を提供することにある。
本発明に係る半導体装置は、機能素子が形成された半導体基板と、前記半導体基板の前記機能素子形成面に形成され、前記機能素子と接続された金属膜と、前記半導体基板の前記機能素子形成面に形成された絶縁層と、前記半導体基板の前記機能素子形成面に対向するように前記絶縁層に形成され、前記金属膜に導通する配線電極と、前記配線電極上の一部に形成された外部電極と、平面視で前記外部電極の周縁部より内側の一部を露出させる開口が形成され、前記絶縁層に形成された絶縁樹脂層と、を備えることを特徴とする。
この構成では、少なくとも外部電極周縁部と樹脂層との間に隙間が生じない。仮に外部電極の側面に隙間が形成されていても、外部電極周縁部に樹脂層(レジスト)が形成されることで、隙間から水分などの不純物が侵入して、電極が酸化又は腐食するといった不具合を防止できる。この結果、配線電極の抵抗値の増加を防止できるため、配線電極での損失の増大が回避できる。また、例えば基板上に半導体装置をはんだ付け実装する際、基板のたわみ、または基板への衝撃などにより、外部電極へ負荷が生じ、その負荷によって、外部電極のエッジ部がめくれるおそれがあるが、配線電極の周縁部を樹脂層で覆うことで、そのめくれを防止でき、外部電極と樹脂層との間に隙間が生じることをさらに回避できる。
前記配線電極は、前記外部電極が形成された部分以外の表層にTiの膜を有し、主材がCuであり、前記外部電極は、前記配線電極に対してめっき形成された膜である構成が好ましい。
この構成では、Tiの膜を形成することによって絶縁樹脂層と配線電極との接合強度が高まる。また、外部電極が形成された部分以外の表層にTiの膜を有することによってレジスト膜を形成することなく外部電極を選択的めっきできるので、製造が容易となる。
前記機能素子はESD保護回路であり、前記配線電極はESD電流の電流路であることが好ましい。
この構成では、ESD電流の電流路である配線電極の抵抗値の増加を防ぐことができるので、静電気放電時のクランプ電圧を低くできる。
本発明によれば、外部電極と樹脂層との間に隙間が生じないので、その隙間に水分などの不純物が侵入して、電極が酸化又は腐食するといった不具合を防止できる。この結果、配線電極の抵抗値の増加を防止できるため、配線電極での損失の増大が回避できる。
以下では、本発明に係る半導体装置についてESD保護デバイスを例に挙げて説明する。
図1は本実施形態に係るESD保護デバイス1の正面断面図である。図2はESD保護デバイス1の各層の平面図である。ESD保護デバイス1は、CSPタイプのデバイスであり、ダイオードおよびツェナーダイオードを含むESD保護回路10Aが構成されたSi基板10に、複数の樹脂層等を含む再配線層20が形成されている。Si基板10は、本発明に係る半導体基板に相当するが、本発明に係る半導体基板はSi基板には限定されず、GaAs基板などであってもよい。
図3はSi基板10に形成されたESD保護回路10Aの平面構成を示す図であり、図4はESD保護回路10Aの回路図である。図5は本実施形態に係るESD保護デバイス1の要部断面図である。
このESD保護デバイス1は、p+のSi基板10の表面に、複数の素子を形成する素子形成層10Lが設けられ、素子形成層10Lの表面から半導体基板10内部へ素子形成層10Lより深い複数の素子分離領域110が形成されている。これらの素子分離領域110は、トレンチの内面に酸化Si膜(SiOx)が形成され、内部にポリシリコンが充填されたトレンチアイソレーションである。素子分離領域110で分離された2つの素子(素子分離領域110を挟む2つの素子)は、素子形成層10Lの表面において、半導体基板10の型(p+)とは逆型であるnエピタキシャル層を備えている。これにより、Si基板10の表面及び厚み方向に、ダイオードD1a,D1b,D3a,D3b,D2,D4及びツェナーダイオードが形成されている。そして、Si基板10の表層には、Al電極10B、Alパッド(以下、パッドという。)P1,P2が設けられ、これら各素子は、図4に示す回路を形成している。なお、図4では、ダイオードD1a、D1bを一つのダイオードD1として表し、ダイオードD3a,D3bを一つのダイオードD3として表している。
形成されたダイオードD1,D2は順方向が揃って直列接続されていて、ダイオードD3,D4は順方向が揃って直列接続されている。また、直列接続したダイオードD1,D2及びダイオードD3,D4それぞれは、順方向が揃ってツェナーダイオードDzに対し並列接続されている。さらに、ダイオードD1,D4の形成位置の間及びダイオードD2,D3の形成位置の間に、ツェナーダイオードDzが介在している。形成されたダイオードD1a,D1bとダイオードD2との接続点が、ESD保護回路10Aの第1の入出力端となり、Si基板10に形成されたパッドP1に接続している。また、形成されたダイオードD3a,D3bとダイオードD4との接続点が、ESD保護回路10Aの第2の入出力端となり、Si基板10に形成されたAlパッド(以下、パッドという。)P2に接続している。パッドP1,P2は、本発明に係る金属膜に相当する。
Si基板10の表層に形成された再配線層20は、パッドP1,P2の周縁部の一部を覆うように、Si基板10の表面(機能素子形成面)に形成されたSiN(又はSiO2)保護膜21と、SiN保護膜21およびパッドP1,P2を覆う樹脂層22とを含んでいる。SiN保護膜21はスパッタリングにより形成され、樹脂層22は、エポキシ系(またはポリイミド系)ソルダージレストのスピンコーティングにより形成されている。樹脂層22には、パッドP1,P2の一部を露出させる開口(コンタクトホール)22A,22B(図2参照)が形成されている。
この開口22A,22Bおよびこの開口22A,22Bの周辺領域には、Ti/Cu/Ti電極21A,21Bが形成されている。図1では、Ti/Cu/Ti電極21Bについてのみ図示しているが、Ti/Cu/Ti電極21Bは、樹脂層22側から順にTi電極211、Cu電極212、Ti電極213が積層されて形成されている。なお、Ti/Cu/Ti電極21Aも同様の構造である。Ti/Cu/Ti電極21A,21Bは、Si基板10の表面に対向する平面部分を有し、かつ、樹脂層22の開口を通じてパッドP1,P2に導通している。Ti/Cu/Ti電極21A,21Bは、ESD保護デバイス1のサージ電流(ESD電流)の電流経路である。
Ti/Cu/Ti電極21A,21Bの平面部分の一部には、外部電極23A,23Bが形成されている。図1では、外部電極23Bについてのみ図示しているが、外部電極23Bは、Ti/Cu/Ti電極21B側にNi電極231が形成され、そのNi電極231の表面にAu電極232が形成されている。外部電極23Aも同様の構造である。外部電極23A,23Bが形成されるTi/Cu/Ti電極21A,21Bの部分は、Ti電極213がエッチングされてCu電極212が露出されていて、外部電極23A,23Bは、露出したCu電極212部分に選択的めっきされている。この外部電極23A,23Bは、ESD保護デバイス1の入出力端子用の電極である。
再配線層20は、樹脂層22にさらに形成された樹脂層26を含んでいる。樹脂層26は、例えば低誘電率のエポキシ樹脂(または、ポリイミド樹脂、液晶ポリマー等)の層である。なお、Ti/Cu/Ti電極21A,21Bは表層にTi電極213を有しているため、Ti/Cu/Ti電極21A,21Bと樹脂層26との接合強度は高い。この樹脂層26には、開口(ビアホール)26A,26Bが形成されている。開口26A,26Bは外部電極23A,23Bの一部を露出させている。図2の樹脂層26を表す図では、外部電極23A,23Bを破線で示し、開口26A,26Bとの関係を示している。これに示すように、外部電極23A,23Bの周縁部は樹脂層26に覆われていて、その周縁部より内側が開口26A,26Bから露出している。
外部電極23A,23Bの周縁部を樹脂層26で覆うことにより、樹脂層26の開口26A,26BからTi/Cu/Ti電極21A,21Bおよび外部電極23A,23Bの接合部までの距離が長くなる。このため、開口26A,26Bから侵入した水分等の不純物は、その接合部分まで侵入しにくく、Ti/Cu/Ti電極21A,21Bの露出したCu部分の腐食を防止できる。
また、例えば基板上にESD保護デバイス1をはんだ付け実装する際、実装する基板のたわみ、またはその基板への衝撃などにより、外部電極23A,23Bへ負荷が生じ、その負荷によって、外部電極23A,23Bのエッジ部がめくれるおそれがある。そこで、外部電極23A,23Bの周縁部を樹脂層26で覆うことにより、外部電極23A,23Bのエッジ部のめくれを防止でき、不純物の侵入をさらに回避できる。また、外部電極23A,23Bと樹脂層26との熱膨張係数の違いによって界面に隙間が出来たとしても外部電極23A,23Bの周縁部が樹脂層で覆われているため、水分などの不純物の浸入を回避することが出来る。
なお、本実施形態では、Si基板10にツェナーダイオードDzなど形成して、ESD保護回路10Aを構成した例を示したが、例えば、可変容量素子等をSi基板10に形成して、それを用いた回路を構成してもよい。
以下に、本実施形態に係るESD保護デバイスの接続例及び動作原理を説明する。
図6A及び図6Bは、本実施形態に係るESD保護デバイス1の接続例を示す図である。ESD保護デバイス1は電子機器に搭載される。電子機器の例として、ノートPC、タブレット型端末装置、携帯電話機、デジタルカメラ、DVC(Digital Video Cassette)、携帯型音楽プレーヤなどが挙げられる。
図6Aでは、I/Oポート100と保護すべきIC101とを接続する信号ラインと、GNDとの間にESD保護デバイス1を接続した例を示す。I/Oポート100は、例えばアンテナが接続されるポートである。本実施形態に係るESD保護デバイス1は双方向型であって、第1入出力端及び第2入出力端の何れが入力側であってもよい。例えば第1入出力端を入力側とした場合、信号ラインに第1入出力端が接続され、第2入出力端がGNDに接続される。
ESD保護デバイス1ツェナーダイオードDzのツェナー電圧を超えるサージ電圧が信号ラインから印加されると、サージ電流はESD保護デバイス1からグランドへ放電される。ESD保護デバイス1は、前記の通り、露出したCuの腐食を防止している。仮に不純物の侵入によりCuが腐食した場合、図6Aの破線で示す、ESD保護デバイス1の電流経路の抵抗値が増大する。この場合、この抵抗によりサージ電流がグランドへ放電されなくなり、ESD保護デバイス1は正常に機能しなくなる。本実施形態では、Cuの腐食を防止しているため、図6Aの破線で示す抵抗値の増大を防止でき、ESD発生時のクランプ電圧を低くして、ESD保護デバイス1を正常に機能させることができる。
図6Bでは、コネクタ102とIC101とを接続する信号ラインと、GNDラインとの間にESD保護デバイス1を接続した例を示す。この例の信号ラインは、例えば、高速伝送線路(差動伝送線路)であって、複数の信号ラインそれぞれと、GNDラインとの間にESD保護デバイス1が接続されている。
図7及び図8は、本実施形態に係るESD保護デバイス1の動作原理を説明するための図である。ESD保護デバイス1は、外部電極23A,23Bを第1入出力端及び第2入出力端とし、信号ラインとGNDラインとの間に接続される。この信号ラインは、静電気放電の電圧から保護すべきIC(不図示)の入出力端子に繋がるラインである。本実施形態に係るESD保護デバイスは双方向型であって、第1入出力端及び第2入出力端の何れが入力側であってもよい。例えば第1入出力端を入力側とした場合、信号ラインに第1入出力端が接続され、第2入出力端がGNDラインに接続される。
図7は、第1入出力端(外部電極23A)に繋がるパッドP1から、第2入出力端(外部電極23B)に繋がるパッドP2へ電流が流れる場合を説明するための図である。ツェナーダイオードDzのツェナー電圧を超えるサージ電圧が印加されると、図中破線で示すように、第1入力端から入ってきたサージ電流は、パッドP1からダイオードD1、ツェナーダイオードDz及びダイオードD4の経路を流れ、パッドP2からグランドへ放電される。
図8は、第2入出力端(外部電極23B)に繋がるパッドP2から、第1入出力端(外部電極23A)に繋がるパッドP1へ電流が流れる場合を説明するための図である。この場合、図中破線で示すように、第2入力端から入ってきたサージ電流は、パッドP2からダイオードD3、ツェナーダイオードDz及びダイオードD2の経路を流れ、パッドP1からグランドへ放電される。
以下に、ESD保護デバイス1の製造工程について説明する。図9はESD保護デバイス1の製造工程を示す図である。ESD保護デバイス1は次の工程で製造される。
(A)まず、ESD保護回路10Aが形成されたSi基板10に、ESD保護回路10Aと導通するパッドP1,P2がフォトリソグラフィにより形成される。また、基板表面にSiN保護膜21がスパッタリングされ、エッチングにより開口H1,H2が形成される。
なお、パッドP1,P2は、それらの面積を小さくすることで、対向する基板(ESD保護回路10A)との間に形成される寄生容量を小さくできる。この寄生容量を小さくすることで、インピーダンスのずれを抑制でき、その結果、信号ラインにおける高周波信号の損失を低減できる。
(B)次に、Si基板10にエポキシ系ソルダージレストのスピンコーティングにより、樹脂層22が形成され、その後、開口22A,22Bが形成される。
(C)樹脂層22の表面に、図1で説明したように、Ti電極211、Cu電極212、Ti電極213が約0.1μm/1.0μm/0.1μmの厚みでスパッタリングにより成膜された後、ウエットエッチングされて、電極21A,21Bが形成される。
(D)Ti/Cu/Ti電極21A,21Bの表面の一部をエッチングして、Cuを露出させ、その露出したCu部分には、図1で説明したように、Ni電極231の表面にAu電極232が形成したAu/Niの外部電極23A,23Bが約0.1μm/3.0μmの厚みで電解めっき(電気めっき)により成膜される。この外部電極23A,23Bは、露出されたCu表面にのみ選択めっきされる。選択めっきにより外部電極23A,23Bを成膜することで、レジスト膜を形成することなく、また、マスキングを必要としないため、製造が容易となる。
(E)その後、樹脂層22の表面に、エポキシ系ソルダージレストのスピンコーティングにより樹脂層26が形成される。この樹脂層26には、開口26A,26Bが形成される。このとき、外部電極23A,23Bの周縁部は樹脂層26で覆われ、その周縁部の内側が開口26A,26Bから露出する。
このように、電解めっきにより外部電極23A,23Bを製膜した後に、樹脂層26を形成することで、めっき液が残り、Ti/Cu/Ti電極21A,21Bが腐食するおそれを回避できる。腐食を回避することで、ESD保護でデバイス1のサージ電流の経路となるTi/Cu/Ti電極21A,21Bの抵抗値の増大を防止できる。
なお、外部電極23A,23Bの一部を露出させる樹脂層26に形成された開口26A,26Bの形状は、適宜変更可能である。図10A、図10B及び図10Cは、外部電極23A,23Bの一部を露出させる開口26A,26Bの別の例を示す図である。図10Aに示すように、開口26A,26Bの角部を曲状として、クラックの生じやすい個所(角部)を保護するようにしてもよい。また、図10Bに示すように、開口26Aのみ、中央部を内側に突出させた形状としてもよい。この場合、例えば、開口26A,26Bそれぞれを異なる形状とすることで、ESD保護素子1の方向を認識しやすくできる。さらに、図10Cに示すように、開口26A,26Bそれぞれを二つに分割(細分化)してもよい。この場合、ESD保護素子1の実装時におけるはんだ量の違いから、ESD保護素子1が傾いて実装される場合があるが、開口26A,26Bを細分化することで、その傾きを抑制できる。
1-ESD保護デバイス
10-Si基板
10A-ESD保護回路
20-再配線層
21-SiN保護膜
21A,21B-Ti/Cu/Ti電極
22-樹脂層
22A,22B-開口
23A,23B-外部電極
26-樹脂層
26A,26B-開口
D1,D2,D3,D4-ダイオード(機能素子)
Dz-ツェナーダイオード(機能素子)
P1,P2-パッド(金属膜)
10-Si基板
10A-ESD保護回路
20-再配線層
21-SiN保護膜
21A,21B-Ti/Cu/Ti電極
22-樹脂層
22A,22B-開口
23A,23B-外部電極
26-樹脂層
26A,26B-開口
D1,D2,D3,D4-ダイオード(機能素子)
Dz-ツェナーダイオード(機能素子)
P1,P2-パッド(金属膜)
Claims (3)
- 機能素子が形成された半導体基板と、
前記半導体基板の前記機能素子形成面に形成され、前記機能素子と接続された金属膜と、
前記半導体基板の前記機能素子形成面に形成された絶縁層と、
前記半導体基板の前記機能素子形成面に対向するように前記絶縁層に形成され、前記金属膜に導通する配線電極と、
前記配線電極上の一部に形成された外部電極と、
平面視で前記外部電極の周縁部より内側の一部を露出させる開口が形成され、前記絶縁層に形成された絶縁樹脂層と、
を備える、半導体装置。 - 前記配線電極は、前記外部電極が形成された部分以外の表層にTiの膜を有し、主材がCuであり、
前記外部電極は、前記配線電極に対してめっき形成された膜である、
請求項1に記載の半導体装置。 - 前記機能素子はESD保護回路であり、前記配線電極はESD電流の電流路である、請求項1または2に記載の半導体装置。
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WO2023021993A1 (ja) * | 2021-08-19 | 2023-02-23 | 株式会社村田製作所 | 過渡電圧吸収素子 |
CN115831961A (zh) * | 2023-02-15 | 2023-03-21 | 成都吉莱芯科技有限公司 | 一种低电容的esd保护器件及制作方法 |
Citations (2)
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JP2006005325A (ja) * | 2004-05-20 | 2006-01-05 | Denso Corp | パワー複合集積型半導体装置およびその製造方法 |
JP2010050177A (ja) * | 2008-08-20 | 2010-03-04 | Sharp Corp | 半導体装置 |
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JP2006005325A (ja) * | 2004-05-20 | 2006-01-05 | Denso Corp | パワー複合集積型半導体装置およびその製造方法 |
JP2010050177A (ja) * | 2008-08-20 | 2010-03-04 | Sharp Corp | 半導体装置 |
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WO2023021993A1 (ja) * | 2021-08-19 | 2023-02-23 | 株式会社村田製作所 | 過渡電圧吸収素子 |
CN115831961A (zh) * | 2023-02-15 | 2023-03-21 | 成都吉莱芯科技有限公司 | 一种低电容的esd保护器件及制作方法 |
CN115831961B (zh) * | 2023-02-15 | 2023-04-28 | 成都吉莱芯科技有限公司 | 一种低电容的esd保护器件及制作方法 |
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