WO2014190584A1 - 抗色偏显示面板 - Google Patents

抗色偏显示面板 Download PDF

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Publication number
WO2014190584A1
WO2014190584A1 PCT/CN2013/078351 CN2013078351W WO2014190584A1 WO 2014190584 A1 WO2014190584 A1 WO 2014190584A1 CN 2013078351 W CN2013078351 W CN 2013078351W WO 2014190584 A1 WO2014190584 A1 WO 2014190584A1
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WIPO (PCT)
Prior art keywords
sub
pixel
transistor
gate
source
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PCT/CN2013/078351
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English (en)
French (fr)
Inventor
杜鹏
姜佳丽
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深圳市华星光电技术有限公司
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Priority to US14/000,222 priority Critical patent/US8987745B2/en
Publication of WO2014190584A1 publication Critical patent/WO2014190584A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections

Definitions

  • the present invention relates to display technology, and more particularly to an anti-color shift display panel.
  • a liquid crystal display panel In a liquid crystal display panel, it is usually composed of a plurality of liquid crystal cells, and the display effect of these liquid crystal cells is controlled by a transistor. Usually these transistors are continuously turned on in accordance with the order of the scan signals. In the traditional Trigate LCD panel, the cost is saved, and the source side of the transistor is often high pin (high). Pin The design of count), for example, uses only one set of outputs (fanout) and one chip (IC) on the source side. Such fanout resistance difference (Rmax-Rmin) is generally large.
  • the impedance difference is too large, and it is easy to cause color shift on both sides of the display panel when displaying the mixed color picture, that is, the display color deviates from the original display due to the display deviation of the monochrome in the mixed color.
  • the signal delay is more serious, which tends to cause the first charged sub-pixel to be charged less than the second sub-pixel ideal, especially on both sides of the panel.
  • fanout has the highest impedance, the difference in charging conditions is especially serious, which may cause color shift.
  • the invention is directed to the defects that the existing display panel is prone to color shift during the color mixing process, and provides a color-resistant display panel to solve the above problems.
  • the scan lines are arranged in the row direction;
  • the data lines are distributed perpendicular to the row direction and interlaced with the scan lines;
  • each sub-pixel Pmn is located adjacent to each other Scan line Gm, Gm+1 and two adjacent data lines Dn, Dn+1;
  • Each sub-pixel includes a transistor having a gate connected to the scan line, a source connected to the data line, and a drain electrically connected to the two capacitors;
  • each pixel unit when the data line is connected to the source of the transistor in the pixel unit, the data lines are respectively connected to the sources of two adjacent sub-pixels in the same row, and the gates of the two sub-pixels are respectively connected to the row. Two scan lines on either side of the sub-pixel.
  • the anti-color shift display panel of the present invention forms a pixel unit every 4 ⁇ 4 sub-pixels; in the pixel unit:
  • a gate of the transistor is connected to the first scan line, and a source is connected to the first data line;
  • a gate of the transistor is connected to the first scan line, and a source is connected to the third data line;
  • a gate of the transistor is connected to the second scan line, and a source is connected to the third data line;
  • a gate of the transistor is connected to the second scan line, and a source is connected to the fifth data line;
  • a gate of the transistor is connected to the third scan line, and a source is connected to the second data line;
  • a gate of the transistor is connected to the second scan line, and a source is connected to the second data line;
  • a gate of the transistor is connected to the second scan line, and a source is connected to the fourth data line;
  • An eighth sub-pixel a gate of the transistor is connected to the third scan line, and a source is connected to the fourth data line;
  • a ninth sub-pixel a gate of the transistor is connected to the fourth scan line, and a source is connected to the first data line;
  • a gate of the transistor is connected to the fourth scan line, and a source is connected to the third data line;
  • the eleventh sub-pixel, the gate of the transistor is connected to the third scan line, and the source is connected to the third data line;
  • a gate of the transistor is connected to the third scan line, and a source is connected to the fifth data line;
  • a gate of the transistor is connected to the fourth scan line, and a source is connected to the second data line;
  • a gate of the transistor is connected to the fifth scan line, and a source is connected to the second data line;
  • a gate of the transistor is connected to the fifth scan line, and a source is connected to the second data line;
  • the sixteenth sub-pixel, the gate of the transistor is connected to the fourth scan line, and the source is connected to the fourth data line.
  • the anti-color-biased display panel of the present invention forms a pixel unit every 2 ⁇ 4 sub-pixels
  • a gate of the transistor is connected to the first scan line, and a source is connected to the first data line;
  • a gate of the transistor is connected to the first scan line, and a source is connected to the third data line;
  • a gate of the transistor is connected to the second scan line, and a source is connected to the third data line;
  • a gate of the transistor is connected to the second scan line, and a source is connected to the fifth data line;
  • a gate of the transistor is connected to the third scan line, and a source is connected to the second data line;
  • a gate of the transistor is connected to the second scan line, and a source is connected to the second data line;
  • a gate of the transistor is connected to the second scan line, and a source is connected to the fourth data line;
  • the eighth sub-pixel, the gate of the transistor is connected to the third scan line, and the source is connected to the fourth data line.
  • the anti-color shift display panel of the present invention forms a pixel unit every 4 ⁇ 2 sub-pixels; in the pixel unit:
  • a gate of the transistor is connected to the first scan line, and a source is connected to the first data line;
  • a gate of the transistor is connected to the first scan line, and a source is connected to the third data line;
  • a gate of the transistor is connected to the third scan line, and a source is connected to the second data line;
  • a gate of the transistor is connected to the second scan line, and a source is connected to the second data line;
  • a gate of the transistor is connected to the fourth scan line, and a source is connected to the first data line;
  • a gate of the transistor is connected to the fourth scan line, and a source is connected to the third data line;
  • a gate of the transistor is connected to the fourth scan line, and a source is connected to the second data line;
  • the eighth sub-pixel, the gate of the transistor is connected to the fifth scan line, and the source is connected to the second data line.
  • each row of sub-pixels displays the same color in red, green, and blue, and successive three-row sub-pixels sequentially display red, green, and blue.
  • the anti-color shift display panel of the present invention comprises:
  • the scan lines are arranged in the row direction;
  • the data lines are distributed perpendicular to the row direction and interlaced with the scan lines;
  • Sub-pixels distributed in an array form a plurality of pixel units, each pixel unit comprising m ⁇ n sub-pixels arranged in m rows and n columns; wherein m and n are natural numbers; each sub-pixel is located at two adjacent Between the scan line and two adjacent data lines;
  • each pixel unit when the data line is charged to the sub-pixels in the pixel unit, the data lines are respectively charged to two adjacent sub-pixels in the same row, and two adjacent sub-pixels in the same row are respectively located in the row of sub-pixels. Scan the two scan lines on both sides.
  • each row of sub-pixels displays the same color in red, green, and blue, and successive three-row sub-pixels sequentially display red, green, and blue.
  • each of the single-color pixels in each pixel unit always charges two sub-pixels by the data line, so that the sub-pixels in which the color shift occurs are occupied as a whole.
  • the proportion of the mixed color sub-pixels is lowered, and the degree of color shift is effectively suppressed.
  • FIG. 1 is a schematic view showing a connection of a display panel according to a first embodiment of the present invention
  • 2 is a color mixing signal in the middle of a display panel according to a first embodiment of the present invention
  • 3 is a color mixing signal at an edge of a display panel according to a first embodiment of the present invention.
  • FIG. 4 is a schematic view showing a connection of a display panel according to a second embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a connection of a display panel according to a third embodiment of the present invention.
  • the solution adopted by the present invention is to use m ⁇ n sub-pixels as one pixel unit, and the connection manner of the sub-pixel transistors at corresponding positions in each pixel unit is the same.
  • the data line Dn is connected to the source of the sub-pixel Pmn of one of the pixel units, the sources of two adjacent sub-pixels Pmn and Pmn-1 are simultaneously connected, and the gates of the two sub-pixels are respectively connected. Go to the adjacent two scan lines Gm and Gm+1.
  • the adjacent two sub-pixels can always be charged at the same time. Even if an RC delay occurs on one sub-pixel, resulting in color distortion, this amount of distortion accounts for a small portion of the entire color mixture, and the color shift can be effectively suppressed.
  • FIG. 1 is a schematic diagram showing a connection of a display panel according to a first embodiment of the present invention.
  • the display panel includes a first scan line 201, a second scan line 202, ... the mth scan line, and a first data line 101, a second data line 102, ... the nth data are vertically arranged. line.
  • a sub-pixel is disposed in the middle, the sub-pixel includes a transistor, the gate of the transistor is connected to the scan line, the source is connected to the data line, and the drain is connected.
  • the sub-pixel of each row corresponds to one color.
  • the first row corresponds to red (R)
  • the second row corresponds to green (G)
  • the third row corresponds to blue (B) and is repeated in this manner.
  • Each 4 ⁇ 4 sub-pixels constitute one pixel unit, and the gate and source connection modes of the transistors of the sub-pixels corresponding to each pixel unit are correspondingly the same.
  • the details in this embodiment are as follows:
  • each data line can always charge transistors in two sub-pixels of the same color at the same time. For example, purple is now displayed, purple is mixed with red and blue; the third data line is charged, and the third data line is for the second sub-pixel 312, the third sub-pixel 313, the tenth sub-pixel 332, and the eleventh.
  • the sub-pixel 333 is charged; and the scan line is scanned from top to bottom, so the order of display is sequentially the second sub-pixel 312 -> the third sub-pixel 313 -> the eleventh sub-pixel 333 -> the tenth sub-pixel 332.
  • the delay of the signal is not the same at different positions of the panel: when the pixel unit of FIG. 1 is located in the middle of the panel, the delay amount is small, in the second sub-pixel 312->the third sub-pixel 313->the eleventh sub- All the sub-pixels in the scanning process of the pixel 333->the tenth sub-pixel 332 are hardly distorted as shown in FIG. 2; and when the pixel unit of FIG. 1 is at the edge position of the display panel, the scanning signal at this time may be delayed. And it becomes shown in Figure 3.
  • partial distortion occurs at the time of scanning of the second sub-pixel 312, it is completed by two red sub-pixels and two blue sub-pixels during the entire purple display process, and the entire distortion portion is occupied.
  • the display portion is extremely small, so that the purple bluish phenomenon caused by the distortion can be effectively suppressed.
  • the above is the case of purple mixed color.
  • FIG. 4 is a second embodiment of the present invention.
  • the color lines of the data lines, the scan lines, and the rows of sub-pixels are the same as those of the first embodiment, except that in this embodiment, 2 ⁇ 4 is used.
  • the sub-pixels are used as pixel units. In each pixel unit, the transistor connections of each sub-pixel are as follows:
  • each data line can always charge the adjacent two sub-pixels of the same row at the same time, so that the display panel is displayed.
  • the color shift phenomenon in the edge region is suppressed.
  • a single pixel unit includes only two rows of sub-pixels, each pixel unit cannot be made purple as in the first embodiment, but considering that the entire display panel is repeatedly arranged by a plurality of pixel units, The purple effect exhibited by the overall display is exactly the same as that of the first embodiment.
  • a third embodiment of the present invention is shown.
  • the color lines of the data lines, the scan lines, and the rows of sub-pixels are the same as the first two embodiments.
  • the pixel unit of this embodiment is composed of 4 ⁇ 2 sub-pixels, and the connection manner of the transistors in each sub-pixel is as follows:
  • each data line can always charge two adjacent sub-pixels of the same row at the same time, so that The color shift phenomenon in the edge area of the display panel is suppressed.
  • one data line can control the adjacent two sub-pixels in one line for display.

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  • Crystallography & Structural Chemistry (AREA)
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  • Chemical & Material Sciences (AREA)
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Abstract

一种抗色偏显示面板, 包括横向的扫描线(201, 202, 203, 204, 205)和纵向的数据线(101, 102, 103, 104, 105)，还包括设置在相邻扫描线(201, 202, 203, 204, 205)和数据线(101, 102, 103, 104, 105)之间的以阵列形式分布的子像素(311, 312, 313, 314, 321, 322, 323, 324, 331, 332, 333, 334, 341, 342, 343, 344)，每mXn个子像素(311, 312, 313, 314, 321, 322, 323, 324, 331, 332, 333, 334, 341, 342, 343, 344)构成像素单元；每个子像素(311, 312, 313, 314, 321, 322, 323, 324, 331, 332, 333, 334, 341, 342, 343, 344)包括一晶体管，其栅极与扫描线(201, 202, 203, 204, 205)连接，源极与数据线(101, 102, 103, 104, 105)连接，漏极与两个电容分别电连接；每个像素单元对应的子像素(311, 312, 313, 314, 321, 322, 323, 324, 331, 332, 333, 334, 341, 342, 343, 344)的晶体管连接方式相同；数据线(101, 102, 103, 104, 105)与像素单元内的源极连接时，分别连接同一行内相邻的两个子像素(311, 312, 313, 314, 321, 322, 323, 324, 331, 332, 333, 334, 341, 342, 343, 344)，该两个子像素(311, 312, 313, 314, 321, 322, 323, 324, 331, 332, 333, 334, 341, 342, 343, 344)的栅极分别连接到上下两根扫描线(201, 202, 203, 204, 205)上。因此，在进行混色的时候，有效的抑制了色偏的程度，提高了显示面板的颜色显示效果，尤其适合窄边框显示器使用。

Description

抗色偏显示面板 技术领域
本发明涉及显示技术，更具体地说，涉及一种抗色偏显示面板。
背景技术
在液晶显示面板中，通常是由复数个液晶单胞组成，通过晶体管来控制这些液晶单胞的显示效果。通常这些晶体管是由扫描信号依据行列次序进行连续开启。而在传统的三栅极型（Trigate）液晶面板中，了节省成本，晶体管源极侧（source）往往采用高引脚（high pin count）的设计，例如在source侧只使用一组输出端（fanout）和一颗芯片（IC），这样的fanout电阻差异（Rmax-Rmin）一般比较大。在实际工作时，阻抗差异太大，容易使得显示混色画面时，在显示面板两侧有色偏产生，即由于混色中的单色出现显示偏差造成显示的颜色偏离原定显示。这是因为在混色画面下，由于fanout阻抗较大，信号的延迟比较严重，容易导致第一个充电的子像素充电情况不如第二个子像素理想，特别是在面板两侧，source fanout走线阻抗最大的地方，充电情况的差异尤其严重，这样就可能会导致色偏现象。
发明内容
本发明针对现有的显示面板在混色过程中容易出现色偏的缺陷，提供一种抗色偏显示面板以解决上述问题。
本发明解决上述问题的方案是，构造一种抗色偏显示面板，包括：
多根扫描线，扫描线沿行方向排布；
多根数据线，数据线沿垂直于行方向分布，并与扫描线交错；
以阵列形式分布的子像素，子像素构成多个像素单元，每个像素单元包括排成m行、n列的m×n个子像素；其中m、n为自然数；每个子像素Pmn位于两相邻的扫描线Gm，Gm+1和两相邻的数据线Dn，Dn+1之间；
每个子像素包括一晶体管，其栅极与扫描线连接，源极与数据线连接，漏极与两个电容分别电连接；
在每个像素单元中，当数据线与像素单元内的晶体管源极连接时，数据线分别连接同一行内相邻的两个子像素的源极，该两个子像素的栅极分别连接到位于该行子像素两侧的两根扫描线上。
本发明的抗色偏显示面板，每4×4个子像素构成像素单元；所述像素单元内：
第一子像素，晶体管的栅极与第一扫描线连接，源极与第一数据线连接；
第二子像素，晶体管的栅极与第一扫描线连接，源极与第三数据线连接；
第三子像素，晶体管的栅极与第二扫描线连接，源极与第三数据线连接；
第四子像素，晶体管的栅极与第二扫描线连接，源极与第五数据线连接；
第五子像素，晶体管的栅极与第三扫描线连接，源极与第二数据线连接；
第六子像素，晶体管的栅极与第二扫描线连接，源极与第二数据线连接；
第七子像素，晶体管的栅极与第二扫描线连接，源极与第四数据线连接；
第八子像素，晶体管的栅极与第三扫描线连接，源极与第四数据线连接；
第九子像素，晶体管的栅极与第四扫描线连接，源极与第一数据线连接；
第十子像素，晶体管的栅极与第四扫描线连接，源极与第三数据线连接；
第十一子像素，晶体管的栅极与第三扫描线连接，源极与第三数据线连接；
第十二子像素，晶体管的栅极与第三扫描线连接，源极与第五数据线连接；
第十三子像素，晶体管的栅极与第四扫描线连接，源极与第二数据线连接；
第十四子像素，晶体管的栅极与第五扫描线连接，源极与第二数据线连接；
第十五子像素，晶体管的栅极与第五扫描线连接，源极与第二数据线连接；
第十六子像素，晶体管的栅极与第四扫描线连接，源极与第四数据线连接。
本发明的抗色偏显示面板，每2×4个子像素构成像素单元；所述像素单元内：
第一子像素，晶体管的栅极与第一扫描线连接，源极与第一数据线连接；
第二子像素，晶体管的栅极与第一扫描线连接，源极与第三数据线连接；
第三子像素，晶体管的栅极与第二扫描线连接，源极与第三数据线连接；
第四子像素，晶体管的栅极与第二扫描线连接，源极与第五数据线连接；
第五子像素，晶体管的栅极与第三扫描线连接，源极与第二数据线连接；
第六子像素，晶体管的栅极与第二扫描线连接，源极与第二数据线连接；
第七子像素，晶体管的栅极与第二扫描线连接，源极与第四数据线连接；
第八子像素，晶体管的栅极与第三扫描线连接，源极与第四数据线连接。
本发明的抗色偏显示面板，每4×2个子像素构成像素单元；所述像素单元内：
第一子像素，晶体管的栅极与第一扫描线连接，源极与第一数据线连接；
第二子像素，晶体管的栅极与第一扫描线连接，源极与第三数据线连接；
第三子像素，晶体管的栅极与第三扫描线连接，源极与第二数据线连接；
第四子像素，晶体管的栅极与第二扫描线连接，源极与第二数据线连接；
第五子像素，晶体管的栅极与第四扫描线连接，源极与第一数据线连接；
第六子像素，晶体管的栅极与第四扫描线连接，源极与第三数据线连接；
第七子像素，晶体管的栅极与第四扫描线连接，源极与第二数据线连接；
第八子像素，晶体管的栅极与第五扫描线连接，源极与第二数据线连接。
本发明的抗色偏显示面板，每一行子像素显示红色、绿色、蓝色中的同一种颜色，且连续的每三行子像素依次显示红色、绿色、蓝色。
本发明的抗色偏显示面板，包括：
多根扫描线，扫描线沿行方向排布；
多根数据线，数据线沿垂直于行方向分布，并与扫描线交错；
以阵列形式分布的子像素，子像素构成多个像素单元，每个像素单元包括排成m行、n列的m×n个子像素；其中m、n为自然数；每个子像素位于两相邻的扫描线和两相邻的数据线之间；
在每个像素单元中，当数据线向像素单元内的子像素充电时，数据线分别向同一行内相邻的两个子像素的充电，同一行内相邻的两个子像素分别由位于该行子像素两侧的两根扫描线进行扫描。
本发明的抗色偏显示面板，每一行子像素显示红色、绿色、蓝色中的同一种颜色，且连续的每三行子像素依次显示红色、绿色、蓝色。
实施本发明的抗色偏显示面板，在进行混色的时候，在每个像素单元内的每一种单色总是由数据线进行两个子像素的充电，从而使得出现色偏的子像素占整体混色子像素的比例下降，有效的抑制了色偏的程度。采用本发明的显示面板，在面板两侧的混色效果与面板中部的混色效果接近，提高了显示面板的颜色显示效果，尤其适合窄边框显示器使用。
附图说明
以下结合附图对本发明进行说明，其中：
图1为本发明第一实施例的显示面板连线示意图；
图2为本发明第一实施例显示面板中部的混色信号；
图3为本发明第一实施例显示面板边缘处的混色信号；
图4为本发明的第二实施例的显示面板连线示意图；
图5为本发明的第三实施例的显示面板连线示意图。
具体实施方式
以下通过附图和具体实施方式对本发明进行详细说明。
本发明采用的方案是将m×n个子像素作为一个像素单元，每个像素单元内对应位置的子像素晶体管的连线方式相同。当数据线Dn与像素单元内其中一行的子像素Pmn的源极进行连接时，会同时连接两个相邻的子像素Pmn和Pmn-1的源极，这两个子像素的栅极再分别连接到相邻的两根扫描线Gm和Gm+1上。这样在数据线对子像素进行充电的时候，总是能同时为相邻的两个子像素进行充电。即使在一个子像素上出现RC延迟，导致颜色失真，但是这个失真量占整个混色的部分较少，能够有效抑制色偏。
如图1所示为本发明的第一实施例的显示面板连线示意图。在本实施例中，显示面板包括横向排布第一扫描线201、第二扫描线202……第m扫描线；竖向排布第一数据线101、第二数据线102……第n数据线。两根相邻的扫描线与两根相邻的数据线相互交错后，在中间设置子像素，子像素内包括一个晶体管，晶体管的栅极与扫描线相连，源极与数据线相连，漏极连接有两个电容，分别作为液晶电容和储存电容，液晶电容和储存电容的一端连接到晶体管的漏极上，另一端连接到共用线上。每一行的子像素对应一个颜色，例如在本实施例中第一行对应红色（R），第二行对应绿色（G）、第三行对应蓝色（B）并以此规律重复。
每4×4个子像素构成一个像素单元，每个像素单元对应位置的子像素的晶体管中栅极和源极连接方式对应相同。本实施例中具体如下：
表1
子像素 栅极 源极
第一子像素311 第一扫描线201 第一数据线101
第二子像素312 第一扫描线201 第三数据线103
第三子像素313 第二扫描线202 第三数据线103
第四子像素314 第二扫描线202 第五数据线105
第五子像素321 第三扫描线203 第二数据线102
第六子像素322 第二扫描线202 第二数据线102
第七子像素323 第二扫描线202 第四数据线104
第八子像素324 第三扫描线203 第四数据线104
第九子像素331 第四扫描线204 第一数据线101
第十子像素332 第四扫描线204 第三数据线103
第十一子像素333 第三扫描线203 第三数据线103
第十二子像素334 第三扫描线203 第五数据线105
第十三子像素341 第四扫描线204 第二数据线102
第十四子像素342 第五扫描线205 第二数据线102
第十五子像素343 第五扫描线205 第四数据线104
第十六子像素344 第四扫描线204 第四数据线104
该像素单元在进行混色时，每一根数据线总是能够同时对同一种颜色的两个子像素内的晶体管进行充电。例如现在要显示紫色，紫色为红色与蓝色进行混色；对第三数据线进行充电，第三数据线会对第二子像素312、第三子像素313、第十子像素332、第十一子像素333进行充电；而扫描线自上而下进行扫描，因此显示的次序依次为第二子像素312->第三子像素313->第十一子像素333->第十子像素332。
由于在面板的不同位置，信号的延迟并不相同：当图1的像素单元位于面板的中部时，延迟量较小，在第二子像素312->第三子像素313->第十一子像素333->第十子像素332的扫描过程中所有的子像素几乎不失真，如图2所示；而当图1的像素单元处于显示面板的边缘位置时，此时的扫描信号会因为延迟而变成图3所示。尽管此时在第二子像素312的扫描时会出现部分的失真，但是在整个紫色的显示过程中是通过2个红色子像素和2个蓝色子像素来完成的，整个失真的部分占全部显示部分极小，因此可以有效的压制因失真而带来的紫色偏蓝现象。以上为紫色混色的情况，在显示其他颜色的时候，仅需在对应的扫描线和数据线进行适应性改动即可。
如图4为本发明的第二实施例，在该实施例中，数据线、扫描线、各行子像素的颜色设置均与第一实施例相同，不同点在于，本实施例中以2×4个子像素作为像素单元。在每个像素单元中，各个子像素的晶体管连接方式如下：
表2
子像素 栅极 源极
第一子像素311 第一扫描线201 第一数据线101
第二子像素312 第一扫描线201 第三数据线103
第三子像素313 第二扫描线202 第三数据线103
第四子像素314 第二扫描线202 第五数据线105
第五子像素321 第三扫描线203 第二数据线102
第六子像素322 第二扫描线202 第二数据线102
第七子像素323 第二扫描线202 第四数据线104
第八子像素324 第三扫描线203 第四数据线104
采用本实施例的像素单元进行混色的时候与第一实施例的工作方式相同，在混色的时候，每个数据线总是能够同时为同一行的相邻两个子像素进行充电，使得在显示面板边缘区域的色偏现象得到抑制。尽管在本实施例中，单个像素单元只包括两行子像素，不能使每个像素单元都能如第一实施例中显示出紫色，但是考虑到整个显示面板是多个像素单元重复排列的，在整体显示的效果上，其显示出的紫色效果与第一实施例完全相同。
如图5所示为本发明的第三实施例，在本实施例中，数据线、扫描线、各行子像素的颜色设置均与前两个实施例相同。本实施例的像素单元是由4×2的子像素组成，每个子像素内，晶体管的连接方式如下：
表3
子像素 栅极 源极
第一子像素311 第一扫描线201 第一数据线101
第二子像素312 第一扫描线201 第三数据线103
第三子像素321 第三扫描线203 第二数据线102
第四子像素322 第二扫描线202 第二数据线102
第五子像素331 第四扫描线204 第一数据线101
第六子像素332 第四扫描线204 第三数据线103
第七子像素341 第四扫描线204 第二数据线102
第八子像素342 第五扫描线205 第二数据线102
采用本实施例的像素单元进行混色的时候与第一、二实施例的工作方式相同，在混色的时候，每个数据线总是能够同时为同一行的两个相邻子像素进行充电，使得在显示面板边缘区域的色偏现象得到抑制。
以上给出了在子像素内使用晶体管以控制子像素显示的几个实施例，本发明还可以应用到其他类型的子像素中以进行抑制色偏。只要其满足在混色时一条数据线能够控制一行内的相邻两个子像素进行显示即可。将多根扫描线沿行方向排布；将多根数据线沿垂直于行方向分布，并与扫描线交错；以阵列形式分布的子像素，子像素构成多个像素单元，每个像素单元包括排成m行、n列的m×n个子像素；其中m、n为自然数；每个子像素位于两相邻的扫描线和两相邻的数据线之间；并不限定在子像素中设置晶体管，只要在每个像素单元中，当数据线向像素单元内的子像素充电时，数据线分别向同一行内相邻的两个子像素的充电，同一行内相邻的两个子像素分别由位于该行子像素两侧的两根扫描线进行扫描。即在混色过程中保证同时点亮两个相邻的子像素即可。
以上仅为本发明具体实施方式，不能以此来限定本发明的范围，本技术领域内的一般技术人员根据本创作所作的均等变化，以及本领域内技术人员熟知的改变，都应仍属本发明涵盖的范围。

Claims (7)

  1. 一种抗色偏显示面板，包括：
    多根扫描线，所述扫描线沿行方向排布；
    多根数据线，所述数据线沿垂直于行方向分布，并与所述扫描线交错；
    以阵列形式分布的子像素，所述子像素构成多个像素单元，每个所述像素单元包括排成m行、n列的m×n个子像素；其中所述m、n为自然数；每个子像素位于两相邻的扫描线和两相邻的数据线之间；
    每个所述子像素包括一晶体管，所述晶体管的栅极与所述扫描线连接，源极与所述数据线连接，漏极与两个电容分别电连接；
    在每个所述像素单元中，当所述数据线与所述像素单元内的晶体管源极连接时，所述数据线分别连接同一行内相邻的两个子像素的源极，所述同一行内相邻的两个子像素的栅极分别连接到位于该行子像素两侧的两根扫描线上。
  2. 根据权利要求1所述的抗色偏显示面板，其中：每4×4个子像素构成一个所述像素单元；所述像素单元内：
    第一子像素，晶体管的栅极与第一扫描线连接，源极与第一数据线连接；
    第二子像素，晶体管的栅极与第一扫描线连接，源极与第三数据线连接；
    第三子像素，晶体管的栅极与第二扫描线连接，源极与第三数据线连接；
    第四子像素，晶体管的栅极与第二扫描线连接，源极与第五数据线连接；
    第五子像素，晶体管的栅极与第三扫描线连接，源极与第二数据线连接；
    第六子像素，晶体管的栅极与第二扫描线连接，源极与第二数据线连接；
    第七子像素，晶体管的栅极与第二扫描线连接，源极与第四数据线连接；
    第八子像素，晶体管的栅极与第三扫描线连接，源极与第四数据线连接；
    第九子像素，晶体管的栅极与第四扫描线连接，源极与第一数据线连接；
    第十子像素，晶体管的栅极与第四扫描线连接，源极与第三数据线连接；
    第十一子像素，晶体管的栅极与第三扫描线连接，源极与第三数据线连接；
    第十二子像素，晶体管的栅极与第三扫描线连接，源极与第五数据线连接；
    第十三子像素，晶体管的栅极与第四扫描线连接，源极与第二数据线连接；
    第十四子像素，晶体管的栅极与第五扫描线连接，源极与第二数据线连接；
    第十五子像素，晶体管的栅极与第五扫描线连接，源极与第二数据线连接；
    第十六子像素，晶体管的栅极与第四扫描线连接，源极与第四数据线连接。
  3. 根据权利要求1所述的抗色偏显示面板，其中：每2×4个子像素构成一个所述像素单元；所述像素单元内：
    第一子像素，晶体管的栅极与第一扫描线连接，源极与第一数据线连接；
    第二子像素，晶体管的栅极与第一扫描线连接，源极与第三数据线连接；
    第三子像素，晶体管的栅极与第二扫描线连接，源极与第三数据线连接；
    第四子像素，晶体管的栅极与第二扫描线连接，源极与第五数据线连接；
    第五子像素，晶体管的栅极与第三扫描线连接，源极与第二数据线连接；
    第六子像素，晶体管的栅极与第二扫描线连接，源极与第二数据线连接；
    第七子像素，晶体管的栅极与第二扫描线连接，源极与第四数据线连接；
    第八子像素，晶体管的栅极与第三扫描线连接，源极与第四数据线连接。
  4. 根据权利要求1所述的抗色偏显示面板，其中：每4×2个子像素构成一个所述像素单元；所述像素单元内：
    第一子像素，晶体管的栅极与第一扫描线连接，源极与第一数据线连接；
    第二子像素，晶体管的栅极与第一扫描线连接，源极与第三数据线连接；
    第三子像素，晶体管的栅极与第三扫描线连接，源极与第二数据线连接；
    第四子像素，晶体管的栅极与第二扫描线连接，源极与第二数据线连接；
    第五子像素，晶体管的栅极与第四扫描线连接，源极与第一数据线连接；
    第六子像素，晶体管的栅极与第四扫描线连接，源极与第三数据线连接；
    第七子像素，晶体管的栅极与第四扫描线连接，源极与第二数据线连接；
    第八子像素，晶体管的栅极与第五扫描线连接，源极与第二数据线连接。
  5. 根据权利要求1所述的抗色偏显示面板，其中：每一行子像素显示红色、绿色、蓝色中的同一种颜色，且连续的每三行子像素依次显示红色、绿色、蓝色。
  6. 一种抗色偏显示面板，包括：
    多根扫描线，所述扫描线沿行方向排布；
    多根数据线，所述数据线沿垂直于行方向分布，并与所述扫描线交错；
    以阵列形式分布的子像素，所述子像素构成多个像素单元，每个所述像素单元包括排成m行、n列的m×n个子像素；其中所述m、n为自然数；每个子像素位于两相邻的扫描线和两相邻的数据线之间；
    在每个所述像素单元中，当所述数据线向所述像素单元内的子像素充电时，所述数据线分别向同一行内相邻的两个子像素的充电，所述同一行内相邻的两个子像素分别由位于该行子像素两侧的两根扫描线进行扫描。
  7. 根据权利要求6所述的抗色偏显示面板，其中：每一行子像素显示红色、绿色、蓝色中的同一种颜色，且连续的每三行子像素依次显示红色、绿色、蓝色。
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