WO2014186945A1 - 实现物理资源和虚拟资源对应的方法和基础输入输出*** - Google Patents

实现物理资源和虚拟资源对应的方法和基础输入输出*** Download PDF

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Publication number
WO2014186945A1
WO2014186945A1 PCT/CN2013/075964 CN2013075964W WO2014186945A1 WO 2014186945 A1 WO2014186945 A1 WO 2014186945A1 CN 2013075964 W CN2013075964 W CN 2013075964W WO 2014186945 A1 WO2014186945 A1 WO 2014186945A1
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Prior art keywords
cpu
correspondence
location
memory
host
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PCT/CN2013/075964
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English (en)
French (fr)
Inventor
许利霞
郭海涛
卢广
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华为技术有限公司
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Priority to CN201380001075.5A priority Critical patent/CN103620558A/zh
Priority to PCT/CN2013/075964 priority patent/WO2014186945A1/zh
Publication of WO2014186945A1 publication Critical patent/WO2014186945A1/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3051—Monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring the presence of processing resources, peripherals, I/O links, software programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3006—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system is distributed, e.g. networked systems, clusters, multiprocessor systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/301—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system is a virtual computing platform, e.g. logically partitioned systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/815—Virtual

Definitions

  • the present invention relates to the field of device management technologies, and in particular, to a method and a basic input/output system for implementing physical resources and virtual resources.
  • BACKGROUND OF THE INVENTION With the increasing number of devices in data centers, virtualization technologies have been widely used to improve device utilization and other advantages. However, while enjoying the benefits of virtualization technology, it also introduces how to achieve unified management of physical and virtual resources in virtualization technology.
  • server management system (out-of-band system) manages physical resources
  • business resource management system (in-band system) manages virtual resources, in virtualized applications, generally to improve equipment usage and management efficiency
  • the virtual resources are often pooled and managed, so the management of the virtual resources by the business resource management system (in-band system) is to manage the virtual resource pool.
  • the management physical node and the virtual machine running on the physical node can be realized, that is, the correspondence relationship information between the physical nodes and the virtual machines running on the physical nodes, the virtual resources and the physical resources are established. The correlation between the two is coarser.
  • the physical nodes here can be devices such as servers, workstations, customers, network users, or personal computers.
  • the coarser association between virtual resources and physical resources leads to problems such as energy-saving management of resources in the host and low efficiency of fault management, mainly CPU and memory resources in the host.
  • the service resource management system detects that there is a problem with the virtual resources of the CPU, but the virtual resources cannot directly correspond to the physical resources, the maintenance personnel cannot distinguish which component of the physical device of the CPU is faulty.
  • the server management system finds that there is a problem with the physical resources of the memory, the virtual resources of the affected memory cannot be accurately located, and the fine isolation on the application cannot be achieved. Only the entire virtual virtual node can be migrated. Machines cause waste of resources and are not conducive to energy conservation.
  • the present invention provides a method and a basic input/output system for realizing physical resources and virtual resources, realizing accurate correspondence between virtual resources and physical resources, and improving efficiency of fault management and energy saving management.
  • a first aspect provides a method for implementing a correspondence between a physical resource and a virtual resource, where the method includes: acquiring a correspondence between each CPU of the CPU and a location of the host; Generating a correspondence between each core of each CPU and a location of the associated CPU; and transmitting a correspondence between each core and a location of the associated CPU to the baseboard management controller
  • the BMC saves and reports the correspondence between each core and the location of the CPU to the operating system OS through CPU information.
  • the location of the CPU includes a slot number of the CPU or a port number and a slot number of the CPU.
  • the method further includes:
  • the physical address addressing method of the memory of the host is used to generate a correspondence between the physical address of each memory module and the location of the memory stick, and send the information to the BMC for storage.
  • the location of the memory module includes a slot number of the memory module or a port where the memory module is located. Number and slot number.
  • a second aspect provides a method for implementing a correspondence between a physical resource and a virtual resource, where the method includes: acquiring a correspondence between each memory module in the host and a location;
  • the physical address addressing method of the memory of the host is used to generate a correspondence between the physical address of each memory module and the location of the memory stick, and the data is sent to the baseboard management controller BMC for storage.
  • the location of the memory module includes a slot number of the memory module or a port number and a slot number of the memory module.
  • the method further includes:
  • the location of the CPU includes a slot number of the CPU or a port number and slot where the CPU is located. Bit number.
  • a third aspect provides a method for implementing a physical resource and a virtual resource, where the method includes: Obtaining a correspondence between each central processing unit CPU in the host and a location, and a unique number of each core in each of the CPUs;
  • the location of the CPU includes a slot number of the CPU or a port number and a slot number of the CPU.
  • the method further includes:
  • the location of the memory module includes a slot number of the memory module or a port where the memory module is located. Number and slot number.
  • a fourth aspect provides a method for implementing a correspondence between a physical resource and a virtual resource, where the method includes: acquiring a correspondence between each memory module in the host and a location;
  • the location of the memory module includes a slot number of the memory module or a port number and a slot number of the memory module.
  • the method further includes:
  • the location of the CPU includes a slot number of the CPU or a port number and slot where the CPU is located. Bit number.
  • a basic input/output system comprising:
  • An obtaining unit configured to acquire a correspondence between each CPU of the CPU and the location of the host; and a processing unit, configured to generate, according to the correspondence between each CPU and the location, the generated CPU The correspondence between each core and the location of the own CPU;
  • a sending unit configured to send a correspondence between each core and a location of the associated CPU to the baseboard management controller BMC; and pass the correspondence between each core and the location of the associated CPU
  • the CPU information is reported to the operating system os.
  • the location of the CPU includes a slot number of the CPU or a port number and a slot number of the CPU.
  • the obtaining unit is further configured to acquire a correspondence between each memory module and the location of the host, where the processing unit is further configured to: according to the correspondence between each memory module and the location, The physical address addressing method of the memory of the host is used to generate a correspondence between a physical address of each memory module and a location of the memory module;
  • the sending unit is further configured to send a correspondence between a physical address of each of the memory modules and a location of the memory module to the BMC for saving.
  • the location of the memory module includes a slot number of the memory module or a port where the memory module is located Number and slot number.
  • a basic input/output system comprising:
  • An obtaining unit configured to acquire a correspondence between each memory module in the host and a location thereof;
  • a processing unit configured to generate, according to a correspondence between each of the memory modules and a location, a physical address addressing method of the memory of the host, and a physical address of the memory module and a location of the memory module Correspondence between
  • the location of the memory module includes a slot number of the memory module or a port number and a slot number of the memory module.
  • the obtaining unit is further configured to acquire a correspondence between each CPU of the host and a location of the host;
  • the processing unit is further configured to generate, according to the correspondence between each CPU and the location, a correspondence between each core of each CPU and a location of the CPU to which the CPU belongs;
  • the sending unit is further configured to send a correspondence between the core and the location of the CPU to be saved by the BMC; and, the correspondence between each core and the location of the CPU The CPU information is reported to the operating system os.
  • the location of the CPU includes a slot number of the CPU or a port number and a slot number of the CPU.
  • a basic input/output system comprising:
  • An obtaining unit configured to acquire a correspondence between each CPU of the CPU and a location in the host, and a unique number of each core in each CPU;
  • a processing unit configured to generate a unique number of each core in each CPU and a CPU according to a corresponding relationship between each CPU and a location and a unique number of each core in each CPU Correspondence between locations;
  • the storage unit is configured to save a correspondence between the unique number of each core and the location of the CPU to which it belongs.
  • the location of the CPU includes a slot number of the CPU or a port number and a slot number where the CPU is located.
  • the obtaining unit is further configured to acquire a correspondence between each memory module and the location of the host, where the processing unit is further configured to: according to the correspondence between each memory module and the location, Generating a correspondence between a unique identifier in the serial detection SPD information of the module of each of the memory modules and a location of each of the memory modules, and a unique identifier in the SPD information of each of the memory modules Corresponding relationship with the physical address of each of the memory modules;
  • the storage unit is further configured to save a unique identifier in the SPD information of each of the memory modules and each of the The correspondence between the locations where the memory modules are located, and the correspondence between the unique identifiers in the SPD information of each of the memory modules and the physical addresses of the memory modules.
  • the location of the memory module includes a slot number of the memory module or a port where the memory module is located Number and slot number.
  • a basic input/output system comprising:
  • An obtaining unit configured to obtain a correspondence between each memory module in the host and a location thereof, where the processing unit is configured to generate, according to a correspondence between each of the memory modules and the location, each of the memory modules a correspondence between a unique identifier in the serial detection SPD information of the module and a location of each of the memory modules, and a unique identifier in the SPD information of each of the memory modules and each of the memory modules Correspondence between physical addresses;
  • a storage unit configured to save a correspondence between a unique identifier in the SPD information of each of the memory modules and a location of each of the memory modules, and a unique identifier and a unique identifier in the SPD information of each of the memory modules The correspondence between the physical addresses of each memory bank.
  • the location of the CPU includes a slot number of the CPU or a port number and a slot number where the CPU is located.
  • the obtaining unit is further configured to acquire a correspondence between each CPU of the host and a location of the host, and a unique number of each core in each CPU;
  • the processing unit is further configured to generate a unique number of each core in each CPU according to a correspondence between each CPU and a location and a unique number of each core in each CPU Correspondence between the locations of the CPUs to which they belong;
  • the storage unit is further configured to save a correspondence between a unique number of each core and a location of the associated CPU.
  • the location of the memory module includes a slot number of the memory module or a port where the memory module is located Number and slot number.
  • the correspondence between the virtual resources and the physical resources in the host is implemented by the method described in the embodiment of the present invention.
  • the association granularity between the virtual resource and the physical resource implemented by the method in the embodiment of the present invention is relatively fine, and the efficiency of fault management and energy-saving management can be effectively improved.
  • FIG. 1 is a flowchart of a method for implementing physical resource and virtual resource corresponding according to the first embodiment of the present invention
  • FIG. 2 is a flowchart of a method for implementing physical resource and virtual resource according to Embodiment 2 of the present invention
  • FIG. 4 is a flowchart of a method for implementing physical resource and virtual resource corresponding to the fourth embodiment of the present invention
  • FIG. 4 is a flowchart of a method for implementing physical resource and virtual resource according to Embodiment 4 of the present invention
  • FIG. 6 is a network topology diagram when a single server is used;
  • FIG. 7 is a flowchart of a method for implementing physical resource and virtual resource corresponding according to Embodiment 6 of the present invention
  • FIG. 8 is a flowchart of a method for implementing physical resource and virtual resource corresponding to Embodiment 7 of the present invention
  • Network topology diagram when the server is used
  • FIG. 10 is a flowchart of a method for implementing physical resource and virtual resource correspondence according to Embodiment 8 of the present invention
  • FIG. 11 is a structural diagram of a basic input/output system according to Embodiment 1 of the present invention.
  • FIG. 12 is a structural diagram of a basic input/output system according to Embodiment 2 of the present invention.
  • FIG. 13 is a structural diagram of a basic input/output system according to Embodiment 3 of the present invention.
  • FIG. 14 is a structural diagram of a basic input/output system according to Embodiment 4 of the present invention.
  • FIG. 15 is a structural diagram of another basic input/output system according to Embodiment 1 of the present invention.
  • FIG. 16 is a structural diagram of another basic input/output system according to Embodiment 2 of the present invention.
  • FIG. 17 is a structural diagram of another basic input/output system according to Embodiment 3 of the present invention.
  • FIG. 18 is a structural diagram of another basic input/output system according to Embodiment 4 of the present invention. detailed description
  • the invention provides a method and a basic input and output system for realizing physical resources and virtual resources, realizing accurate correspondence between virtual resources and physical resources, and improving efficiency of fault management and energy saving management.
  • the core idea of the method provided by the embodiment of the present invention is to implement the correspondence between physical resources and virtual resources by using location information, for example, slot (slot) mapping technology, to solve the problem that the correlation granularity in the prior art is not fine enough.
  • location information for example, slot (slot) mapping technology
  • FIG. 1 is a flowchart of a method for implementing physical resource and virtual resource corresponding to the first embodiment of the present invention. As shown in FIG. 1, the method includes the following steps:
  • Step S101 The BIOS (Basic Input Output System) acquires the correspondence between each CPU (Central Processing Unit) in the host and the location.
  • BIOS Basic Input Output System
  • Step S102 The BIOS generates a correspondence between each core of each CPU and a location of the associated CPU.
  • Step S103 The BIOS sends the correspondence between each core and the location of the CPU to be saved to the baseboard management controller BMC, and the correspondence between each core and the location of the associated CPU is passed. The CPU information is reported to the OS (Operating System).
  • the BIOS processes the correspondence between each CPU and the location of the acquired host, and generates a relationship between each core of each CPU and the location of the CPU.
  • the corresponding relationship is sent to the BMC to be saved and reported to the operating system OS through the CPU information, so as to implement the correspondence between the virtual resources and the physical resources in the host.
  • the granularity of the association between the virtual resource and the physical resource implemented by the method in the embodiment of the present invention is relatively fine, and the efficiency of fault management and energy-saving management can be effectively improved.
  • the method in the first embodiment of the present invention implements a correspondence between a virtual resource and a physical resource for a CPU in a host. Further, the method can also implement a correspondence between a virtual resource and a physical resource for a memory stick in the host.
  • the method may further include: acquiring a correspondence between each memory module in the host and a location; and combining the physical address addressing method of the memory of the host, generating the physicality of each of the memory modules The correspondence between the address and the location of the memory module is sent to the BMC for storage.
  • the physical address addressing method of the memory refers to the representation of the physical address of the memory stick in the host. In practical applications, when the memory is addressed in different ways, the physical address will behave differently.
  • the BIOS processes the correspondence between each memory module and the location of the obtained host, and generates a physical address of each memory module in the host and the memory. Correspondence between the locations of the strips, and the corresponding relationship is sent to the BMC to save the correspondence between the virtual resources and the physical resources in the host.
  • the granularity of the association between the virtual resource and the physical resource implemented by the method in the embodiment of the present invention is relatively fine, and the efficiency of fault management and energy-saving management can be effectively improved.
  • FIG. 2 is a flowchart of a method for implementing physical resource and virtual resource according to Embodiment 2 of the present invention. Figure. As shown in FIG. 2, the method includes the following steps:
  • Step S201 The BIOS (Basic Input Output System) acquires the correspondence between each memory module in the host and the location.
  • BIOS Basic Input Output System
  • Step S202 The BIOS combines the physical address addressing method of the memory of the host to generate a correspondence between the physical address of each memory module and the location of the memory module, and sends the information to the baseboard management controller BMC for storage.
  • the physical address addressing method of the memory refers to the representation of the physical address of the memory stick in the host. In practical applications, when the memory is addressed in different ways, the physical address will behave differently.
  • the BIOS processes the correspondence between each memory module in the host and the location of the host, and generates a physical address of each memory module in the host and the memory module. Correspondence between the locations, and the corresponding relationship is sent to the BMC to save, and the correspondence between the virtual resources and the physical resources in the host is implemented.
  • the correlation granularity between the virtual resource and the physical resource implemented by the method in the embodiment of the present invention is relatively fine, and the efficiency of fault management and energy-saving management can be effectively improved.
  • the method of the second embodiment of the present invention implements a correspondence between a virtual resource and a physical resource for a memory module in the host. Further, the method can also implement a correspondence between the virtual resource and the physical resource for the CPU in the host.
  • the method may further include: the BIOS acquiring a correspondence between each CPU of the CPU and a location of the host; generating a location of each core and a CPU of each CPU Corresponding relationship between each core and the location of the associated CPU is sent to the BMC to save, and the correspondence between each core and the location of the associated CPU is reported by the CPU information. To the operating system OS.
  • the BIOS processes the correspondence between each CPU and the location of the host, and generates a location of each core in each CPU and the location of the CPU.
  • the corresponding relationship is sent to the BMC for storage and reported to the operating system OS by the CPU information to implement the correspondence between the virtual resources and the physical resources in the host.
  • the granularity of the association between the virtual resource and the physical resource implemented by the method in the embodiment of the present invention is relatively fine, and the efficiency of fault management and energy-saving management can be effectively improved.
  • FIG. 3 is a flowchart of a method for implementing physical resource and virtual resource corresponding to the third embodiment of the present invention. As shown in FIG. 3, the method includes the following steps:
  • Step S301 The basic input/output system BIOS acquires each central processing unit CPU and the host in the host. The correspondence between the settings and the unique number of each core in each CPU.
  • Step S302 The BIOS generates a correspondence between a unique number of each core in each CPU and a location of the associated CPU.
  • Step S303 The BIOS saves the correspondence between the unique number of each core and the location of the associated CPU in the BIOS.
  • the BIOS processes the correspondence between each CPU and the location of the host, and generates a unique number and a CPU of each core in each CPU of the host.
  • the granularity of the association between the virtual resource and the physical resource implemented by the method in the embodiment of the present invention is relatively fine, and the efficiency of fault management and energy-saving management can be effectively improved.
  • the method in the third embodiment of the present invention implements a correspondence between a virtual resource and a physical resource for a CPU in a host. Further, the method can also implement a correspondence between a virtual resource and a physical resource for a memory stick in the host.
  • the method may further include: acquiring a correspondence between each memory module in the host and a location; generating a unique identifier in the serial detection SPD information of the module of each memory module Corresponding relationship between the location of each of the memory modules and the correspondence between the unique identifier in the SPD information of each of the memory modules and the physical address of each of the memory modules is stored in the BIOS. .
  • the method of the third embodiment of the present invention further processes the correspondence between each memory module and the location of the obtained host, and generates a unique identifier and the memory in the SPD information of each memory module in the host.
  • the correspondence between the locations of the strips and the correspondence between the unique identifiers in the SPD information of the memory modules and the physical addresses of the memory modules, and the above correspondences are saved in the BIOS to implement virtual resources in the host. Correspondence with physical resources.
  • the granularity of the association between the virtual resource and the physical resource implemented by the method in the embodiment of the present invention is relatively fine, and the efficiency of fault management and energy-saving management can be effectively improved.
  • FIG. 4 it is a flowchart of a method for implementing physical resource and virtual resource corresponding to Embodiment 4 of the present invention. As shown in FIG. 4, the method includes the following steps:
  • Step S401 The basic input/output system BIOS acquires a correspondence between each memory stick in the host and the location.
  • Step S402 The BIOS generates a correspondence between a unique identifier in the serial detection SPD information of the module of each memory module and a location of each of the memory modules, and a corresponding relationship between each memory module.
  • the correspondence between the unique identifier in the SPD information and the physical address of each of the memory modules is stored in the BIOS of the basic input/output system.
  • the BIOS processes the correspondence between each memory module and the location of the obtained host, and generates a unique identifier in the SPD information of each memory module in the host.
  • Corresponding relationship between the location of the memory module and the unique identifier in the SPD information of each memory module and the physical address of the memory module, and storing the above correspondences in the BIOS to implement virtualization in the host The correspondence between resources and physical resources.
  • the association granularity between the virtual resource and the physical resource implemented by the method in the embodiment of the present invention is relatively fine, and the efficiency of fault management and energy-saving management can be effectively improved.
  • the method in the fourth embodiment of the present invention implements a correspondence between a virtual resource and a physical resource for a memory module in the host. Further, the method can implement a correspondence between a virtual resource and a physical resource for the CPU in the host.
  • the method may further include: acquiring a correspondence between each CPU of the CPU and a location of the host, and a unique number of each core in each CPU; generating each CPU Corresponding relationship between the unique number of each core and the location of the associated CPU; the correspondence between the unique number of each core and the location of the associated CPU is saved in the BIOS.
  • the BIOS processes the correspondence between each CPU and the location of the acquired host, and generates a unique number and associated name of each core in each CPU in the host. Corresponding relationship between the locations where the CPUs are located, and storing the above correspondences in the BIOS to implement correspondence between virtual resources and physical resources in the host.
  • the association granularity between the virtual resource and the physical resource implemented by the method in the embodiment of the present invention is relatively fine, and the efficiency of fault management and energy-saving management can be effectively improved.
  • the location of the CPU includes the slot number of the CPU or the port number and the slot number of the CPU.
  • the location of the memory module includes the slot number of the memory module or the memory. Port number and slot number where the strip is located.
  • the above host may be a general computer, a mobile terminal, a workstation or a server, a dedicated server, or the like.
  • the location of the device may be the slot number of each device.
  • the location of the device may be the port number and slot number of each device. .
  • a host is taken as an example.
  • the location of the device is the slot where each device is located.
  • FIG. 5 is a flowchart of a method for implementing physical resource and virtual resource according to Embodiment 5 of the present invention. As shown in FIG. 5, the method includes the following steps:
  • Step S501 The BMC located in the host acquires each CPU and each memory module in the host respectively. The correspondence between the slots in the standby device is saved in the BMC.
  • the physical resource mainly includes a CPU and a memory bar disposed in the host.
  • a host includes at least one CPU and at least one memory module.
  • Each CPU and a memory module are respectively installed in a slot of the host chassis frame. Therefore, each CPU and the memory module and the slot in the slot are located. There is a one-to-one correspondence between the bit numbers.
  • the network topology is a single host.
  • the host includes two CPUs 100 and eight memory sticks 200.
  • the number of CPUs and memory modules included in the host may be specifically set according to requirements.
  • the correspondence obtained by the BMC can be as follows:
  • the host includes two CPUs, which are located in slot 1 (first slot) and slot.
  • the SPD (Serial Presence Detect) information refers to the configuration information of the memory module, such as the number of P-Banks, the voltage, the number of row/column addresses, the bit width, and various main operation timings. Wait.
  • the SPD information is programmed by the manufacturer of the memory module in an EEPROM (Electrically Erasable Programmable Read Only Memory).
  • Step S502 The BIOS obtains the correspondence between each CPU in the host and the slot where the CPU is located, and processes the corresponding relationship between each core core of each CPU in the host and the slot where the CPU belongs.
  • the CPU information is stored in the BMC, and the CPU information including the corresponding relationship is reported to the virtualized OS.
  • the CPU information includes the correspondence between each core of each CPU in the host and the slot where the CPU is located.
  • the CPU information obtained by the BIOS processing may be as shown in Table 1 below:
  • Table 1 CPU information obtained after BIOS processing Physical resource after BIOS processing
  • Step S503 The BIOS obtains a correspondence between each memory module in the host and a slot where the memory module is located, and combines a physical address addressing method of the memory to generate a physical address of each memory module in the host and the memory module.
  • the corresponding relationship between the slots is sent to the BMC for storage, and the conventional memory information is reported to the virtualization OS.
  • the physical address addressing method of the memory may include two types.
  • the physical address representation of the memory stick in the host is different.
  • Table 2 the memory address physical address representation corresponding to the two memory addressing methods respectively.
  • the memory addressing method one is a method of addressing by a memory chip, and the physical address of the memory is 0-127M, 128-255M, 896-1023M;
  • the second method is a method of addressing with a smaller particle than the memory stick and combining the cross-storage technology, and the physical address of the memory is 0-1, 16-17, ....
  • the above memory addressing methods are well known in the art and will not be described in detail herein.
  • the BIOS processes the corresponding relationship between the received memory module and the slot according to the actual physical address addressing method, and obtains the physical address of each memory module in the host and the slot where the memory module is located. Correspondence between the bits, and send the corresponding relationship to the BMC for saving. Therefore, in the method of the embodiment of the present invention, the correspondence between the virtual resource and the physical resource may be accurate to the physical address of each memory module and the slot where the memory bar is located.
  • Step S504 After the virtualized OS is started, the CPU information and the memory strip information reported by the BIOS are received to form a resource pool.
  • the resource pool formed by the virtualization OS is as follows:
  • the virtualized OS combines the virtualized processing, pulls the virtual resources and the physical resources, and realizes the correspondence between the virtual resources and the physical resources.
  • the BMC may also obtain the correspondence between each CPU in the host and the slot where the device is located, and save the information in the BMC.
  • the method does not include step S503, and in step S504, after the virtualized OS is started, only the CPU information reported by the BIOS is received, and a resource pool is formed.
  • the BMC can also obtain only the correspondence between each memory module in the host and the slot where the device is located, and save the information in the BMC.
  • the method does not include step S502, and in step S504, after the virtualized OS is started, only the memory strip information reported by the BIOS is received, and a resource pool is formed.
  • the virtualized OS receives the CPU information reported by the BIOS and includes the correspondence between each core and the slot in each CPU of the host, so that the virtualized OS forms a CPU.
  • the resource pool includes the correspondence between each core and slot in the CPU.
  • the virtualized OS detects a vCPU error, it can determine the core corresponding to the vCPU that is in error according to the correspondence, for example, (Slot l , core 3), the virtualized OS can directly isolate the (Slot l, core 3) and notify the BMC that the (Slot 1, core 3) error.
  • the BIOS processes the correspondence between the obtained CPU and/or the memory module and the slot, and obtains the correspondence between each core and the slot in each CPU of the host. Relationship between the virtual address and the physical resource in the host, and the corresponding relationship between the physical address of the memory module and the slot in which the memory module resides is sent to the BMC.
  • the granularity of the association between the virtual resource and the physical resource implemented by the method in the embodiment of the present invention is relatively fine, and the efficiency of fault management and energy-saving management can be effectively improved.
  • the virtualized OS detects a vCPU error
  • the OS corresponds the vCPU of the error to the core of the specific CPU
  • the BMC finds the core according to the correspondence between each core and the slot of each CPU in the host.
  • An alarm is generated in the slot where the corresponding CPU is located.
  • the maintenance personnel are prompted to directly check the CPU of the slot.
  • the virtualized OS detects a vCPU error, it assumes that the core corresponding to the vCPU is (Slot 1, core 3 ). If the OS determines that the core corresponding to the error vCPU (Slot 1, core 3 ) has been faulted multiple times, If used, the OS directly isolates the core (Slot 1, core 3) and notifies the BMC. The BMC finds the slot where the core ( Slot 1, core 3 ) is located according to the corresponding relationship between each core and the slot in the CPU. The alarm is generated to alert the maintenance personnel that the CPU in the first slot is faulty. Need to be repaired or replaced.
  • (CPU, slot l) issues an alert, and the virtualized OS needs to be notified for isolation.
  • the BMC determines (Slot 1, core 1 ), (Slot 1) according to the correspondence between each core and each slot in each CPU. , core 2 ), ( Slot 1 , core 3 ) and P ( Slot 1 , core 4) need to be isolated, reported to the virtualized OS, and the core is isolated.
  • the OS detects a memory address error, the OS maps the faulty memory address to a specific physical address and notifies the BMC.
  • the BMC corresponds to the physical address of each memory module in the host and the slot where the memory module resides. Relationship, find the slot where the memory module is located, and issue a warning to remind the maintenance personnel to directly repair the memory module of the slot.
  • the virtualization OS detects that the memory address 0 123M is faulty. If it is determined that the segment memory has been repeatedly faulty and cannot be used, the OS directly isolates the segment memory and notifies the BMC. Assuming that the physical address corresponding to the memory address is 0 to 123 M, the BMC combines the physical address of each memory module with the slot of the memory module, and combines the memory physical address addressing method currently used by the BIOS. For the addressing method, the memory module corresponding to the faulty memory segment is identified as (memory, slot l), and the BMC issues a warning to remind the maintenance personnel that the memory module in the first slot needs to be repaired or replaced.
  • (memory, slot 1) has an early warning, and the currently used memory physical address addressing method is the addressing method one, assuming that the affected memory segment is 0 127M, and the BMC reports the virtualized OS; the virtualized OS The memory segment with a physical address of 0 127M is processed. Therefore, the method according to the fifth embodiment of the present invention can accurately match the virtual resource and the physical resource, so that the maintenance personnel can accurately identify which component of the host has a problem, facilitate fault maintenance, and migrate with existing needs. Compared with the entire virtual machine on the wrong physical node, it saves resources and is conducive to energy saving.
  • the BMC corresponding to the faulty vCPU or the error memory address is notified to the BMC, and the BMC finds the corresponding relationship according to the correspondence relationship.
  • the step of finding the slot where the CPU corresponding to the core corresponding to the error or the memory address corresponding to the faulty memory address is located according to the corresponding relationship may also be implemented by the BIOS. Specifically, the following is a detailed introduction.
  • a host is taken as an example.
  • the location of the device is the slot where each device is located.
  • FIG. 7 is a flowchart of a method for implementing physical resource and virtual resource corresponding according to Embodiment 6 of the present invention. As shown in FIG. 7, the method includes the following steps:
  • Step S601 The BMC of the host acquires the correspondence between each CPU and each memory module in the host and the slot where the device is located, and saves the corresponding relationship between each memory module and the slot in which the device resides.
  • the correspondence between the unique identifier in the SPD information of each memory module and the slot in which each memory module is located is included.
  • the SPD information that the manufacturer burns in the memory module includes unique identification information of the memory module.
  • the unique identification information of different memory modules is different.
  • the unique identification information can be directly located to the memory module corresponding to the unique identifier. Therefore, the correspondence between the unique identifier and the slot in the SPD information of each memory module is equivalent to the correspondence between each memory module and the slot.
  • Step S602 The BIOS obtains a correspondence between each CPU in the host and a slot in the host, and a unique number of each core in each CPU preset by the system, and generates each core of each CPU in the host.
  • the correspondence between the unique number and the slot where the CPU belongs is stored in the BIOS, and the regular CPU information is reported to the virtualization OS.
  • each core of the CPU has a unique number (APICID) in the system, and the unique number is preset by the system, and the BIOS can directly obtain the unique number from the system.
  • APID unique number
  • virtual The OS can also directly obtain the unique number of each core of each CPU from the system.
  • the BIOS only saves the correspondence between the unique number of each core in the CPU and the slot where the CPU is located, and does not need to report the corresponding relationship to the virtual 0S.
  • the CPU information reported by the BIOS to the virtualized OS is the same as the prior art, and is only conventional CPU information, and does not contain the above-mentioned correspondence.
  • the virtualization OS When the virtualization OS detects a core error on the CPU, it can determine the unique number of the faulted core based on the unique number of each core of each CPU obtained from the system, and notify BI0S.
  • the BIOS determines the CPU of the slot based on the unique number of the faulted core and the unique number of each core in the CPU and the slot in which the CPU resides.
  • Step S603 The BIOS obtains a correspondence between the memory modules in the host and the slot in the host, and processes the corresponding relationship between the unique identifier in the SPD information of each memory module and the slot where the memory module is located, and The correspondence between the unique identifier in the SPD information of each memory module and the physical address of the memory module is stored in the BIOS, and the conventional memory information is reported to the virtualized OS.
  • Step S604 After the virtualized OS is started, the CPU information and the memory strip information reported by the BIOS are received to form a resource pool.
  • the BMC may also obtain the correspondence between each CPU of the host and the slot where the device is located, and save the BMC in the BMC.
  • the method does not include step S603, and in step S604, after the virtualized OS is started, only the CPU information reported by the BIOS is received, and a resource pool is formed.
  • the BMC can also obtain only the correspondence between each memory module in the host and the slot where the device is located, and save the information in the BMC.
  • the method does not include step S602, and in step S604, after the virtualized OS is started, only the memory strip information reported by the BIOS is received, and a resource pool is formed.
  • the technology for forming a resource pool by the virtualized OS is the same as that of the prior art, and details are not described herein again.
  • the virtualized OS combines virtualization processing to pull through virtual resources and physical resources.
  • the BIOS processes the correspondence between the obtained CPU and the memory module and the slot, and obtains a unique number of each core of each CPU in the host and the CPU. Correspondence between slots, and the correspondence between the unique identifier in the SPD information of each memory module and the physical address of the memory module, and the unique identifier in the SPD information of each memory module and the slot of the memory module Correspondence relationship, thereby realizing the correspondence between virtual resources and physical resources in the host.
  • the association granularity between the virtual resource and the physical resource implemented by the method in the embodiment of the present invention is relatively fine, and the efficiency of fault management and energy-saving management can be effectively improved.
  • the virtualization OS detects a certain core error of the CPU
  • the unique number of the core of the error is determined according to the unique number of each core of each CPU acquired from the system, and the BI0S is notified.
  • the BIOS determines which slot has a CPU error based on the unique number of the faulted core and the correspondence between the unique number of each core in the CPU and the slot in which the CPU is located, and notifies the BMC.
  • the BMC After receiving the message from the BIOS, the BMC sends an alarm to remind the maintenance personnel which CPU in the slot has a fault and needs to be repaired or replaced.
  • the BIOS is based on the unique number of each core of each CPU stored therein and the CPU. Corresponding relationship between the slots, determining the number of the core affected by the CPU failure, and notifying the virtualization OS; the virtualization OS isolating the affected cores according to the received number of affected cores.
  • the virtualization OS When the virtualization OS detects a memory error, it notifies BI0S of the physical address corresponding to the errored memory.
  • the BIOS determines the unique identifier of the erroneous memory according to the physical address of the erroneous memory, and the corresponding relationship between the unique identifier in the SPD information of each memory module and the physical address of the memory module, and informs the BMC of the memory corresponding to the unique identifier. .
  • the BMC determines the slot where the erroneous memory is located according to the unique identifier and the corresponding relationship between the memory module and the slot, and sends an alarm to remind the maintenance personnel that the memory module on the slot needs to be faulty. Repair or replace.
  • the BIOS determines, according to the correspondence between the unique identifier in the SPD information and the physical address of the memory module, the memory segments corresponding to the physical addresses affected by the fault, and notifies the virtualized os.
  • the virtualized OS isolates the affected memory segments.
  • the method in the embodiment of the present invention can implement an accurate correspondence between the virtual resource and the physical resource, so that the maintenance personnel can accurately identify which component of the host has a problem and facilitate fault maintenance; Compared with the entire virtual machine on the physical node, it saves resources and is conducive to energy saving.
  • the BIOS corresponding to the faulty CPU or the faulty memory address is notified to the BIOS, and the BIOS finds the corresponding relationship according to the correspondence.
  • the unique identifier in the SPD information corresponding to the CPU corresponding to the faulty core or the faulty memory address and notify the BMC; the BMC sends an alarm to remind the maintenance personnel which slot of the CPU or the memory corresponding to the unique identifier is faulty. , remind maintenance personnel to overhaul.
  • FIG. 8 is a flowchart of a method for implementing physical resource and virtual resource corresponding according to Embodiment 7 of the present invention. As shown in FIG. 8, the method includes the following steps:
  • Step S701 The BMC located in the host acquires the correspondence between each CPU and each memory module in the host and the port and slot where the device resides, and saves.
  • Embodiment 7 of the present invention is applicable to a scenario of multiple hosts, as shown in FIG. 9, which is a network topology diagram when multiple hosts are used.
  • a plurality of hosts 300 are connected to a virtualization management center 400 through a switch (not shown in FIG. 9), and virtualization management is performed by the virtualization management center 400.
  • Each host has a uniquely determined switch port number.
  • the BMC 600 in the host 300 of each port is managed by the upper DMS (Device Manager System) 500.
  • DMS Device Manager System
  • the correspondence obtained by the BMC can be as follows, and the fifth host is taken as an example (the port number is 5):
  • Step S702 The BIOS obtains a correspondence between each CPU in the host and a port and a slot where the CPU is located, and processes the port and slot of each core core and the CPU to which the CPU belongs.
  • the corresponding relationship is sent to the BMC for saving, and the CPU information corresponding to the corresponding relationship is reported to the virtualized OS; wherein the CPU information includes the port and slot where each core and the CPU of each CPU in the host are located.
  • the CPU information obtained by the BIOS processing may be as shown in Table 3 below: Table 3: CPU information obtained after BIOS processing
  • Step S703 The BIOS obtains a correspondence between each memory module in the host and a slot and a port where the memory module is located, and combines a memory physical address addressing method to generate a physical address of each memory module in the host and the memory.
  • the correspondence between the port and the slot where the strip is located is sent to the BMC for storage, and the conventional memory information is reported to the virtualized OS.
  • the physical address addressing method of the memory may include two types.
  • the physical address representation of the memory stick in the host is different.
  • the memory address physical address representation corresponding to the two memory addressing methods respectively.
  • Memory preparation method 1 BIOS reporting memory, slot 1 , 5 0-127M 0-1, 16-17, 0-1023M memory, slot 2, 5 128-255M 2-3, 18-19,
  • the BIOS is combined with the physical memory address addressing method actually used, between the received memory module and the port and slot where the memory module is located.
  • the corresponding relationship is processed, and the corresponding relationship between the physical address of each memory module in the host and the port and slot where the memory is located is reported to the operating system OS. Therefore, in the method of the embodiment of the present invention, the correspondence between the virtual resource and the physical resource may be accurate to the physical address of each memory module and the port and slot where the memory module is located.
  • Step S704 After the virtualized OS is started, the CPU information and the memory stick information reported by the BIOS are received to form a resource pool.
  • the resource pool formed by the virtualization OS is as follows:
  • Step S705 Combine the virtualization processing to pull the virtual resource and the physical resource.
  • step S701 the BMC may also obtain the correspondence between each CPU in the host and the slot where the device is located, and save the information in the BMC.
  • the method does not include step S703, and in step S704, after the virtualized OS is started, only the CPU information reported by the BIOS is received, and a resource pool is formed.
  • the BMC can also obtain only the correspondence between each memory module in the host and the slot where the device is located, and save the information in the BMC.
  • the method does not include step S702, and in step S704, after the virtualized OS is started, only the memory strip information reported by the BIOS is received, and a resource pool is formed.
  • the BIOS processes the correspondence between the obtained CPU and the memory module and the slot and the port respectively, and obtains a slot for each core in each CPU of the host and the CPU.
  • the association granularity between the virtual resource and the physical resource implemented by the method in the embodiment of the present invention is finer, and the efficiency of fault management and energy-saving management can be effectively improved.
  • Step S801 The BMC located in the host obtains a correspondence between each CPU and each memory module and a port and a slot where the device is located, and saves, where the memory module is located between the memory module and the slot where the memory module is located.
  • Step S802 The BIOS obtains a correspondence between each CPU in the host and a port and a slot where the CPU is located, and a unique number of each core in each CPU preset by the system, and generates each CPU in the host.
  • the correspondence between the unique number of each core and the port and slot where the CPU belongs is stored in the BIOS and the regular CPU information is reported to the virtualization OS.
  • Step S803 The BIOS obtains a correspondence between each memory module in the host and a port and a slot where the memory module is located, and processes the unique identifier in the SPD information of each memory module and the port where the memory module is located.
  • the correspondence between the slots and the correspondence between the unique identifiers in the SPD information of each memory module and the physical addresses of the memory modules are stored in the BIOS, and the conventional memory information is reported to the virtualization OS.
  • Step S804 After the virtualized OS is started, the CPU information and the memory stick information reported by the BIOS are received to form a resource pool.
  • the virtualized OS combines virtualization processing to pull through virtual resources and physical resources.
  • step S801 the BMC may also obtain the correspondence between each CPU in the host and the slot where the device is located, and save the information in the BMC.
  • the method does not include step S803, and in step S804, after the virtualized OS is started, only the CPU information reported by the BIOS is received, and a resource pool is formed.
  • the BMC can also obtain only the correspondence between each memory module in the host and the slot where the device is located, and save the information in the BMC.
  • the method S802 will not be included, and in step S804, after the virtualized OS is started, only the memory strip information reported by the BIOS is received, and a resource pool is formed.
  • the BIOS processes the correspondence between the obtained CPU and/or the memory module and the port and the slot, and obtains a unique number of each core of each CPU in the host.
  • the correspondence between the port and the slot so as to achieve the correspondence between the virtual resource and the physical resource in the host.
  • the granularity of the association between the virtual resource and the physical resource implemented by the method in the embodiment of the present invention is relatively fine, and the efficiency of the fault management and the energy-saving management can be effectively improved.
  • FIG. 11 is a structural diagram of a basic input/output system according to Embodiment 1 of the present invention. As shown in FIG. 11, the system includes: an obtaining unit 901, a processing unit 902, and a sending unit 903.
  • the obtaining unit 901 is configured to acquire a correspondence between each CPU of the CPU and the location of the host.
  • the processing unit 902 is configured to generate, according to the correspondence between each CPU and the location, a correspondence between each core of each CPU and a location of the CPU.
  • the sending unit 903 is configured to send a correspondence between each core and a location of the CPU to be saved to the baseboard management controller BMC; and, between each core and a location of the CPU The correspondence is reported to the operating system OS by the CPU information.
  • the correspondence between each cpu and the location of the acquired host is processed, and the correspondence between each core of each CPU and the location of the CPU is generated.
  • the corresponding relationship is sent to the BMC to be saved and reported to the operating system OS through the CPU information, so as to implement the correspondence between the virtual resources and the physical resources in the host.
  • the granularity of the association between the virtual resource and the physical resource implemented by the system in the embodiment of the present invention is relatively fine, and the efficiency of fault management and energy-saving management can be effectively improved.
  • the system in the first embodiment of the present invention implements a correspondence between a virtual resource and a physical resource for a CPU in a host. Further, the system can also implement a correspondence between a virtual resource and a physical resource for a memory stick in the host.
  • the acquiring unit 901 is further configured to acquire a correspondence between each memory module in the host and a location.
  • the processing unit 902 is further configured to generate a physical address and a memory of each of the memory modules according to a physical address addressing method of the memory of the host according to a correspondence between each of the memory modules and a location The correspondence between the locations of the bars.
  • the sending unit 903 is further configured to send a correspondence between a physical address of each of the memory modules and a location of the memory module to the BMC for saving.
  • the system of the first embodiment of the present invention processes the correspondence between each memory module and the location of the obtained host, and generates a physical address between each memory module in the host and a location of the memory module.
  • the corresponding relationship is sent to the BMC to save the correspondence between the virtual resources and the physical resources in the host.
  • the granularity of the association between the virtual resource and the physical resource implemented by the system in the embodiment of the present invention is relatively fine, and the efficiency of fault management and energy-saving management can be effectively improved.
  • FIG. 12 is a structural diagram of a basic input/output system according to Embodiment 2 of the present invention.
  • the system includes: an obtaining unit 1001, a processing unit 1002, and a transmitting unit 1003.
  • the obtaining unit 1001 is configured to acquire a correspondence between each memory module in the host and a location.
  • the processing unit 1002 is configured to generate a physical address and a memory bar of each of the memory modules according to a physical address addressing method of the memory of the host according to a correspondence between each of the memory modules and a location The correspondence between the locations.
  • the sending unit 1003 is configured to send a correspondence between a physical address of each of the memory modules and a location of the memory module to the baseboard management controller BMC for storage.
  • the correspondence between each memory module in the obtained host and the location of the host is processed, and a physical address of each memory module in the host is generated between the physical address of the memory module and the location of the memory module.
  • Correspondence relationship and send the corresponding relationship to the BMC to save, and realize the correspondence between the virtual resources and the physical resources in the host.
  • the association granularity between the virtual resource and the physical resource implemented by the system in the embodiment of the present invention is relatively fine, and the efficiency of fault management and energy-saving management can be effectively improved.
  • the system in the second embodiment of the present invention implements a correspondence between a virtual resource and a physical resource for a memory module in the host. Further, the system can also implement a correspondence between a virtual resource and a physical resource for the CPU in the host.
  • the obtaining unit 1001 is further configured to acquire a correspondence between each CPU of the host and the location of the host.
  • the processing unit 1002 is further configured to generate, according to the correspondence between each CPU and the location, a correspondence between each core of each CPU and a location of the CPU.
  • the sending unit 1003 is further configured to send a correspondence between each core and a location of the associated CPU to the BMC, and perform a correspondence between each core and a location of the associated CPU. The relationship is reported to the operating system os through the CPU information.
  • the system of the second embodiment of the present invention further processes the correspondence between each CPU and the location of the acquired host, and generates a correspondence between each core of each CPU and the location of the CPU.
  • the relationship is sent to the BMC and sent to the operating system OS through the CPU information to implement the correspondence between the virtual resources and the physical resources in the host.
  • the granularity of the association between the virtual resource and the physical resource implemented by the system in the embodiment of the present invention is relatively fine, and the efficiency of fault management and energy-saving management can be effectively improved.
  • FIG. 13 is a structural diagram of a basic input/output system according to Embodiment 3 of the present invention. As shown in FIG. 13, the system includes: an obtaining unit 1101, a processing unit 1102, and a storage unit 1103.
  • the obtaining unit 1101 is configured to acquire a correspondence relationship between each central processing unit CPU in the host and a location, and a unique number of each core in each CPU.
  • the processing unit 1102 is configured to: according to the correspondence between each CPU and a location, and each The unique number of each core in the CPU generates a correspondence between the unique number of each core in each CPU and the location of the associated CPU.
  • the storage unit 1103 is configured to save a correspondence between a unique number of each core and a location of the associated CPU.
  • the correspondence between each CPU and the location of the obtained host is processed, and a unique number of each core in each CPU of the host is generated between the CPU and the location of the CPU.
  • the association granularity between the virtual resource and the physical resource implemented by the system in the embodiment of the present invention is relatively fine, and the efficiency of fault management and energy-saving management can be effectively improved.
  • the system in the third embodiment of the present invention implements the correspondence between the virtual resource and the physical resource for the CPU in the host. Further, the system can also implement the correspondence between the virtual resource and the physical resource for the memory module in the host.
  • the acquiring unit 1101 is further configured to acquire a correspondence between each memory module in the host and a location.
  • the processing unit 1102 is further configured to generate, according to the correspondence between each of the memory modules and the location, a unique identifier in the serial detection SPD information existing in the module of each of the memory modules, and each of the The correspondence between the locations where the memory modules are located, and the correspondence between the unique identifiers in the SPD information of each of the memory modules and the physical addresses of the memory modules.
  • the storage unit 1103 is further configured to save a correspondence between a unique identifier in the SPD information of each of the memory modules and a location of each of the memory modules, and in the SPD information of each of the memory modules A unique identifier is associated with a physical address of each of the memory modules.
  • the system of the third embodiment of the present invention further processes the correspondence between each memory module and the location of the obtained host, and generates a unique identifier and the memory in the SPD information of each memory module in the host.
  • the correspondence between the locations of the strips and the correspondence between the unique identifiers in the SPD information of the memory modules and the physical addresses of the memory modules, and the above correspondences are saved in the BIOS to implement virtual resources in the host.
  • the granularity of the association between the virtual resource and the physical resource implemented by the system in the embodiment of the present invention is relatively fine, and the efficiency of fault management and energy-saving management can be effectively improved.
  • FIG. 14 is a structural diagram of a basic input/output system according to Embodiment 4 of the present invention. As shown in FIG. 14, the system includes: an obtaining unit 1201, a processing unit 1202, and a storage unit 1203.
  • the obtaining unit 1201 is configured to acquire a correspondence between each memory module in the host and a location.
  • the processing unit 1202 is configured to generate a correspondence according to the relationship between each of the memory modules and the location a correspondence between a unique identifier in the serial detection SPD information existing in the module of each of the memory modules and a location of each of the memory modules, and a unique identifier in the SPD information of each of the memory modules Correspondence with the physical address of each of the memory modules.
  • the storage unit 1203 is configured to save a correspondence between a unique identifier in the SPD information of each of the memory modules and a location of each of the memory modules, and a unique one of the SPD information of each of the memory modules A correspondence between the physical address of each of the memory modules is identified.
  • the correspondence between each memory module and the location of the obtained host is processed, and the unique identifier in the SPD information of each memory module in the host and the memory module are generated.
  • the correspondence between the locations and the correspondence between the unique identifiers in the SPD information of the memory modules and the physical addresses of the memory modules, and the foregoing correspondences are saved in the BIOS to implement virtual resources and physics in the host. Correspondence between resources.
  • the association granularity between the virtual resource and the physical resource implemented by the system in the embodiment of the present invention is relatively fine, and the efficiency of fault management and energy-saving management can be effectively improved.
  • the system in the fourth embodiment of the present invention implements a correspondence between a virtual resource and a physical resource for a memory module in the host. Further, the system can also implement a correspondence between the virtual resource and the physical resource for the CPU in the host.
  • the obtaining unit 1201 is further configured to acquire a correspondence between each CPU of the host and the location of the host, and a unique number of each core in each CPU.
  • the processing unit 1202 is further configured to generate, according to a correspondence between each CPU and a location, and a unique number of each core in each CPU, a unique number and a membership of each core in each CPU. The correspondence between the locations of the CPUs.
  • the storage unit 1203 is further configured to save a correspondence between the unique number of each core and the location of the CPU.
  • the system of the fourth embodiment of the present invention further processes the correspondence between each CPU and the location of the obtained host, and generates a unique number of each core in each CPU and a location of the CPU to which the CPU belongs. Corresponding relationship between the virtual resource and the physical resource in the host is saved in the BIOS. The granularity of the association between the virtual resource and the physical resource implemented by the system in the embodiment of the present invention is relatively fine, and the efficiency of fault management and energy-saving management can be effectively improved.
  • the location of the CPU includes the slot number of the CPU or the port number and the slot number of the CPU.
  • the location of the memory module includes the slot number of the memory module or the memory. Port number and slot number where the strip is located.
  • BIOS basic input/output system BIOS
  • FIG. 15 is a structural diagram of a basic input/output system according to Embodiment 1 of the present invention. As shown in FIG. 15, the system includes: an acquirer 1301, a processor 1302, and a transmitter 1303.
  • the acquirer 1301 is configured to obtain a correspondence between each CPU of the CPU and the location of the host.
  • the processor 1302 is configured to generate, according to a correspondence between each CPU and a location, a correspondence between each core of each CPU and a location of an associated CPU.
  • the transmitter 1303 is configured to send a correspondence between each core and a location of the CPU to be saved to the baseboard management controller BMC; and, between each core and a location of the CPU The corresponding relationship is reported to the operating system os through the cpu information.
  • the BIOS of the basic input/output system processes the correspondence between each CPU and the location of the acquired host, and generates each core of each CPU and its own CPU.
  • the correspondence between the locations is sent to the BMC and reported to the operating system OS by the CPU information to implement the correspondence between the virtual resources and the physical resources in the host.
  • the granularity of association between virtual resources and physical resources implemented by the system in the embodiment of the present invention is relatively fine, and the efficiency of fault management and energy-saving management can be effectively improved.
  • the system in the first embodiment of the present invention implements a correspondence between a virtual resource and a physical resource for a CPU in a host. Further, the system can also implement a correspondence between a virtual resource and a physical resource for a memory stick in the host.
  • the acquirer 1301 is further configured to acquire a correspondence between each memory module in the host and a location.
  • the processor 1302 is further configured to generate a physical address and a memory of each of the memory modules according to a physical address addressing method of the memory of the host according to a correspondence between each of the memory modules and a location The correspondence between the locations of the bars.
  • the transmitter 1303 is further configured to send a correspondence between a physical address of each of the memory modules and a location of the memory module to the BMC for saving.
  • the corresponding relationship between each memory module in the host and the location of the host is processed, and the physical address of each memory module in the host and the location of the memory module are generated.
  • Correspondence between the virtual resource and the physical resource in the host is sent to the BMC to save the corresponding relationship.
  • the granularity of the association between the virtual resource and the physical resource implemented by the system in the embodiment of the present invention is relatively fine, and the efficiency of fault management and energy-saving management can be effectively improved.
  • 16 is a structural diagram of a basic input/output system according to Embodiment 2 of the present invention. As shown in FIG. 16, the system includes: an acquirer 1401, a processor 1402, and a transmitter 1403.
  • the acquirer 1401 is configured to acquire a correspondence between each memory module in the host and a location.
  • the processor 1402 is configured to generate a physical address and a memory bar of each of the memory modules according to a physical address addressing method of the memory of the host according to a correspondence between each of the memory modules and a location The correspondence between the locations.
  • the transmitter 1403 is configured to send a correspondence between a physical address of each of the memory modules and a location of the memory module to the BMC for saving.
  • the correspondence between each memory module in the obtained host and the location of the host is processed, and a physical address of each memory module in the host is generated between the physical address of the memory module and the location of the memory module.
  • Correspondence relationship and send the corresponding relationship to the BMC to save, and realize the correspondence between the virtual resources and the physical resources in the host.
  • the association granularity between the virtual resource and the physical resource implemented by the system in the embodiment of the present invention is relatively fine, and the efficiency of fault management and energy-saving management can be effectively improved.
  • the system in the second embodiment of the present invention implements a correspondence between a virtual resource and a physical resource for a memory module in the host. Further, the system can also implement a correspondence between a virtual resource and a physical resource for the CPU in the host.
  • the acquirer 1401 is further configured to acquire a correspondence between each CPU of the host and the location of the host.
  • the processor 1402 is further configured to generate, according to a correspondence between each CPU and a location, a correspondence between each core of each CPU and a location of the CPU.
  • the transmitter 1403 is further configured to send a correspondence between each core and a location of the CPU to be saved to the baseboard management controller BMC; and, between each core and a location of the CPU The correspondence is reported to the operating system OS by the CPU information.
  • the system of the second embodiment of the present invention further processes the correspondence between each CPU and the location of the acquired host, and generates a correspondence between each core of each CPU and the location of the CPU.
  • the relationship is sent to the BMC and sent to the operating system OS through the CPU information to implement the correspondence between the virtual resources and the physical resources in the host.
  • the granularity of the association between the virtual resource and the physical resource implemented by the system in the embodiment of the present invention is relatively fine, and the efficiency of fault management and energy-saving management can be effectively improved.
  • FIG. 17 a block diagram of a basic input/output system according to a third embodiment of the present invention is shown. As shown in FIG. 17, the system includes: an acquirer 1501, a processor 1502, and a memory 1503.
  • the acquirer 1501 is configured to obtain a correspondence between each CPU of the CPU and the location of the host Relationships and unique numbers for each core in each CPU.
  • the processor 1502 is configured to generate a unique number and a CPU of each core in each CPU according to a correspondence between each CPU and a location and a unique number of each core in each CPU. The correspondence between the locations.
  • the memory 1503 is configured to save a correspondence between the unique number of each core and the location of the associated CPU.
  • the correspondence between each CPU and the location of the obtained host is processed, and a unique number of each core in each CPU of the host is generated between the CPU and the location of the CPU.
  • the association granularity between the virtual resource and the physical resource implemented by the system in the embodiment of the present invention is relatively fine, and the efficiency of fault management and energy-saving management can be effectively improved.
  • the system in the third embodiment of the present invention implements a correspondence between a virtual resource and a physical resource for a CPU in a host. Further, the system can also implement a correspondence between a virtual resource and a physical resource for a memory stick in the host.
  • the acquirer 1501 is further configured to acquire a correspondence between each memory module in the host and a location thereof.
  • the processor 1502 is further configured to generate, according to the correspondence between each of the memory modules and the location, a unique identifier in the serial detection SPD information of the module of each of the memory modules and each of the The correspondence between the locations where the memory modules are located, and the correspondence between the unique identifiers in the SPD information of each of the memory modules and the physical addresses of the memory modules.
  • the memory 1503 is further configured to save a correspondence between a unique identifier in the SPD information of each of the memory modules and a location of each of the memory modules, and a unique one in the SPD information of each of the memory modules A correspondence between the physical address of each of the memory modules is identified.
  • the system of the third embodiment of the present invention further processes the correspondence between each memory module and the location of the obtained host, and generates a unique identifier and the memory in the SPD information of each memory module in the host.
  • the correspondence between the locations of the strips and the correspondence between the unique identifiers in the SPD information of the memory modules and the physical addresses of the memory modules, and the above correspondences are saved in the BIOS to implement virtual resources in the host.
  • the granularity of the association between the virtual resource and the physical resource implemented by the system in the embodiment of the present invention is relatively fine, and the efficiency of fault management and energy-saving management can be effectively improved.
  • the system includes: an acquirer 1601, a processor 1602, and a memory 1603.
  • the acquirer 1601 is configured to obtain a correspondence between each memory module in the host and a location.
  • the processor 1602 is configured to generate, according to the correspondence between each of the memory modules and the location, a unique identifier in the serial detection SPD information existing in the module of each of the memory modules, and each of the Correspondence between the locations where the memory modules are located, and the correspondence between the unique identifiers in the SPD information of each of the memory modules and the physical addresses of the memory modules.
  • the memory 1603 is configured to save a correspondence between a unique identifier in the SPD information of each of the memory modules and a location of each of the memory modules, and a unique identifier in the SPD information of each of the memory modules Correspondence with the physical address of each of the memory modules.
  • the correspondence between each memory module and the location of the obtained host is processed, and the unique identifier in the SPD information of each memory module in the host and the memory module are generated.
  • the correspondence between the locations and the correspondence between the unique identifiers in the SPD information of the memory modules and the physical addresses of the memory modules, and the foregoing correspondences are saved in the BIOS to implement virtual resources and physics in the host. Correspondence between resources.
  • the association granularity between the virtual resource and the physical resource implemented by the system in the embodiment of the present invention is relatively fine, and the efficiency of fault management and energy-saving management can be effectively improved.
  • the system in the fourth embodiment of the present invention implements a correspondence between a virtual resource and a physical resource for a memory module in the host. Further, the system can also implement a correspondence between the virtual resource and the physical resource for the CPU in the host.
  • the acquirer 1601 is further configured to obtain a correspondence between each central processing unit CPU in the host and a location, and a unique number of each core in each CPU.
  • the processor 1602 is further configured to generate, according to a correspondence between each CPU and a location, and a unique number of each core in each CPU, a unique number and a membership of each core in each CPU. The correspondence between the locations of the CPUs.
  • the memory 1603 is further configured to save a correspondence between a unique number of each core and a location of the associated CPU.
  • the system of the fourth embodiment of the present invention further processes the correspondence between each CPU and the location of the obtained host, and generates a unique number of each core in each CPU and a location of the CPU to which the CPU belongs. Corresponding relationship between the virtual resource and the physical resource in the host is saved in the BIOS. The granularity of the association between the virtual resource and the physical resource implemented by the system in the embodiment of the present invention is relatively fine, and the efficiency of fault management and energy-saving management can be effectively improved.
  • the location of the CPU includes the slot number of the CPU or the port number and the slot number of the CPU.
  • the location of the memory module includes the slot number of the memory module or the memory. Port number and slot number where the strip is located.
  • the disclosed systems, devices, and methods may be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, i.e., may be located in one place, or may be distributed over multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the functions, if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium.
  • the technical solution of the present invention which is essential or contributes to the prior art, or a part of the technical solution, may be embodied in the form of a software product, which is stored in a storage medium, including
  • the instructions are used to cause a computer device (which may be a personal computer, server, or network device, etc.) or a processor to perform all or part of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a U disk, a removable hard disk, a Read-Only Memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and the like, which can store program codes.

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Abstract

一种实现物理资源和虚拟资源对应的方法及一种基础输入输出***，该方法包括：获取主机中每个中央处理器CPU与所在位置之间的对应关系；生成所述每个CPU中每个核心与所属CPU的所在位置之间的对应关系；将所述每个核心与所属CPU的所在位置之间的对应关系发送至基板管理BMC控制单元保存，并将所述每个核心与所属CPU的所在位置之间的对应关系通过CPU信息上报至操作***OS。本方法能够实现虚拟资源和物理资源之间精确对应，提高故障管理和节能管理的效率。

Description

实现物理资源和虚拟资源对应的方法和基础输入输出***
技术领域 本发明涉及设备管理技术领域，特别涉及一种实现物理资源和虚拟资源对应的方 法和基础输入输出***。 背景技术 随着数据中心的设备日益增加， 为提高设备的利用率及其他优点，虚拟化技术得 到了广泛的应用。但是， 在享受虚拟化技术带来的好处的同时， 也引入了如何能够实 现对虚拟化技术中的物理资源和虚拟资源的统一管理的问题。
目前， 比较常规的设备管理方法为：服务器管理***（带外***）管理物理资源; 业务资源管理***（带内***）管理虚拟资源， 在虚拟化应用中， 一般为了提升设备 的使用和管理效率， 往往将虚拟资源进行池化管理， 所以业务资源管理***（带内系 统）对虚拟资源的管理也就是管理虚拟资源池。现有技术中， 仅仅能够实现管理物理 节点和该物理节点上运行的虚拟机之间的对应关系，即建立物理节点和物理节点上运 行了哪些虚拟机的对应关系信息，虚拟资源和物理资源之间的关联粒度较粗。这里的 的物理节点可以是服务器、 工作站、 客户、 网络用户或个人计算机等设备。
而虚拟资源和物理资源之间的关联粒度较粗会导致主机中资源的节能管理和故 障管理的效率较低等问题， 主要是主机中的 CPU和内存资源。 例如， 如果业务资源 管理***检测到有 CPU的虚拟资源出现了问题， 但由于虚拟资源不能直接与物理资 源对应， 维护人员无法辨别具体是 CPU的物理设备的哪个部件出现了问题， 给排除 故障带来障碍； 再例如， 如果服务器管理***发现内存的物理资源出现问题， 由于不 能准确定位到受影响的内存的虚拟资源，无法实现应用上的精细隔离， 只能迁移该物 理节点上的整台虚拟机， 造成资源浪费， 不利于节能。 发明内容 本发明提供一种实现物理资源和虚拟资源对应的方法和基础输入输出***，实现 虚拟资源和物理资源之间的精确对应， 提高故障管理和节能管理的效率。
第一方面， 提供一种实现物理资源和虚拟资源对应的方法， 所述方法包括： 获取主机中每个中央处理器 CPU与所在位置之间的对应关系； 生成所述每个 CPU中每个核心与所属 CPU的所在位置之间的对应关系； 将所述每个核心与所属 CPU的所在位置之间的对应关系发送至基板管理控制器
BMC保存， 并将所述每个核心与所属 CPU所在位置之间的对应关系通过 CPU信息 上报至操作*** OS。
在第一方面的第一种可能的实现形式中，所述 CPU的所在位置包括所述 CPU所 在槽位号或者所述 CPU所在端口号和槽位号。
结合第一方面或第一方面的第一种可能的实现形式，在第一方面的第二种可能的 实现形式中， 还包括：
获取所述主机中每个内存条与所在位置之间的对应关系；
结合所述主机的内存的物理地址编址方法，生成所述每个内存条的物理地址与内 存条所在位置之间的对应关系， 发送至所述 BMC保存。
结合第一方面的第二种可能的实现形式， 在第一方面的第三种可能的实现形式 中，所述内存条的所在位置包括所述内存条所在槽位号或者所述内存条所在端口号和 槽位号。
第二方面， 提供一种实现物理资源和虚拟资源对应的方法， 所述方法包括： 获取主机中每个内存条与所在位置之间的对应关系；
结合所述主机的内存的物理地址编址方法，生成所述每个内存条的物理地址与内 存条所在位置之间的对应关系， 发送至基板管理控制器 BMC保存。
在第二方面的第一种可能的实现形式中，所述内存条的所在位置包括所述内存条 所在槽位号或者所述内存条所在端口号和槽位号。
结合第二方面或第二方面的第一种可能的实现形式，在第二方面的第二种可能的 实现形式中， 还包括：
获取所述主机中每个中央处理器 CPU与所在位置之间的对应关系；
生成所述每个 CPU中每个核心与所属 CPU的所在位置之间的对应关系； 将所述每个核心与所属 CPU的所在位置之间的对应关系发送至所述 BMC保存， 并将所述每个核心与所属 CPU所在位置之间的对应关系通过 CPU信息上报至操作系 统 OS。
结合第二方面的第二种可能的实现形式， 在第二方面的第三种可能的实现形式 中， 所述 CPU的所在位置包括所述 CPU所在槽位号或者所述 CPU所在端口号和槽 位号。
第三方面， 提供一种实现物理资源和虚拟资源对应的方法， 所述方法包括： 获取主机中每个中央处理器 CPU与所在位置之间的对应关系以及所述每个 CPU 中每个核心的唯一编号；
生成所述每个 CPU中每个核心的唯一编号与所属 CPU的所在位置之间的对应关 系；
将所述每个核心的唯一编号与所属 CPU的所在位置之间的对应关系保存在基础 输入输出*** BIOS中。
在第三方面的第一种可能的实现形式中，所述 CPU的所在位置包括所述 CPU所 在槽位号或者所述 CPU所在端口号和槽位号。
结合第三方面或第三方面的第一种可能的实现形式，在第三方面的第二种可能的 实现形式中， 还包括：
获取所述主机中每个内存条与所在位置之间的对应关系；
生成所述每个内存条的模组存在的串行检测 SPD信息中的唯一标识与所述每个 内存条所在位置之间的对应关系、 以及所述每个内存条的 SPD信息中的唯一标识与 所述每个内存条的物理地址之间的对应关系， 保存在所述 BIOS中。
结合第三方面的第二种可能的实现形式， 在第三方面的第三种可能的实现形式 中，所述内存条的所在位置包括所述内存条所在槽位号或者所述内存条所在端口号和 槽位号。
第四方面， 提供一种实现物理资源和虚拟资源对应的方法， 所述方法包括： 获取主机中每个内存条与所在位置之间的对应关系；
生成所述每个内存条的模组存在的串行检测 SPD信息中的唯一标识与所述每个 内存条所在位置之间的对应关系、 以及所述每个内存条的 SPD信息中的唯一标识与 所述每个内存条的物理地址之间的对应关系， 保存在基础输入输出*** BIOS中。
在第四方面的第一种可能的实现形式中，所述内存条的所在位置包括所述内存条 所在槽位号或者所述内存条所在端口号和槽位号。
结合第四方面或第四方面的第一种可能的实现形式，在第四方面的第二种可能的 实现形式中， 还包括：
获取所述主机中每个中央处理器 CPU与所在位置之间的对应关系以及所述每个 CPU中每个核心的唯一编号；
生成所述每个 CPU中每个核心的唯一编号与所属 CPU的所在位置之间的对应关 系；
将所述每个核心的唯一编号与所属 CPU的所在位置之间的对应关系保存在所述 BIOS中。
结合第四方面的第二种可能的实现形式， 在第四方面的第三种可能的实现形式 中， 所述 CPU的所在位置包括所述 CPU所在槽位号或者所述 CPU所在端口号和槽 位号。
第五方面， 提供一种基础输入输出***， 所述***包括：
获取单元， 用于获取主机中每个中央处理器 CPU与所在位置之间的对应关系； 处理单元， 用于根据所述每个 CPU与所在位置之间的对应关系， 生成所述每个 CPU中每个核心与所属 CPU的所在位置之间的对应关系；
发送单元， 用于将所述每个核心与所属 CPU的所在位置之间的对应关系发送至 基板管理控制器 BMC保存； 并， 将所述每个核心与所属 CPU所在位置之间的对应 关系通过 CPU信息上报至操作*** os。
在第五方面的第一种可能的实现形式中，所述 CPU的所在位置包括所述 CPU所 在槽位号或者所述 CPU所在端口号和槽位号。
结合第五方面或第五方面的第一种可能的实现形式，在第五方面的第二种可能的 实现形式中，
所述获取单元， 还用于获取所述主机中每个内存条与所在位置之间的对应关系； 所述处理单元， 还用于根据所述每个内存条与所在位置之间的对应关系， 结合所 述主机的内存的物理地址编址方法，生成所述每个内存条的物理地址与内存条所在位 置之间的对应关系；
所述发送单元，还用于将所述每个内存条的物理地址与内存条所在位置之间的对 应关系发送至所述 BMC保存。
结合第五方面的第二种可能的实现形式， 在第五方面的第三种可能的实现形式 中，所述内存条的所在位置包括所述内存条所在槽位号或者所述内存条所在端口号和 槽位号。
第六方面， 提供一种基础输入输出***， 所述***包括：
获取单元， 用于获取主机中每个内存条与所在位置之间的对应关系；
处理单元， 用于根据所述每个内存条与所在位置之间的对应关系， 结合所述主机 的内存的物理地址编址方法，生成所述每个内存条的物理地址与内存条所在位置之间 的对应关系；
发送单元，用于将所述每个内存条的物理地址与内存条所在位置之间的对应关系 发送至基板管理控制器 BMC保存。 在第六方面的第一种可能的实现形式中，所述内存条的所在位置包括所述内存条 所在槽位号或者所述内存条所在端口号和槽位号。
结合第六方面或第六方面的第一种可能的实现形式，在第六方面的第二种可能的 实现形式中，
所述获取单元， 还用于获取所述主机中每个中央处理器 CPU与所在位置之间的 对应关系；
所述处理单元， 还用于根据所述每个 CPU与所在位置之间的对应关系， 生成所 述每个 CPU中每个核心与所属 CPU的所在位置之间的对应关系；
所述发送单元， 还用于将所述每个核心与所属 CPU的所在位置之间的对应关系 发送至所述 BMC保存； 并， 将所述每个核心与所属 CPU所在位置之间的对应关系 通过 CPU信息上报至操作*** os。
结合第六方面的第二种可能的实现形式，所述 CPU的所在位置包括所述 CPU所 在槽位号或者所述 CPU所在端口号和槽位号。
第七方面， 提供一种基础输入输出***， 所述***包括：
获取单元， 用于获取主机中每个中央处理器 CPU与所在位置之间的对应关系以 及所述每个 CPU中每个核心的唯一编号；
处理单元， 用于根据所述每个 CPU 与所在位置之间的对应关系以及所述每个 CPU中每个核心的唯一编号， 生成所述每个 CPU中每个核心的唯一编号与所属 CPU 的所在位置之间的对应关系；
存储单元， 用于保存所述每个核心的唯一编号与所属 CPU的所在位置之间的对 应关系。
在第七方面的第一种可能的实现形式中，所述 CPU的所在位置包括所述 CPU所 在槽位号或者所述 CPU所在端口号和槽位号。
结合第七方面或第七方面的第一种可能的实现形式，在第七方面的第二种可能的 实现形式中，
所述获取单元， 还用于获取所述主机中每个内存条与所在位置之间的对应关系； 所述处理单元， 还用于根据所述每个内存条与所在位置之间的对应关系， 生成所 述每个内存条的模组存在的串行检测 SPD信息中的唯一标识与所述每个内存条所在 位置之间的对应关系、 以及所述每个内存条的 SPD信息中的唯一标识与所述每个内 存条的物理地址之间的对应关系；
所述存储单元， 还用于保存所述每个内存条的 SPD信息中的唯一标识与所述每 个内存条所在位置之间的对应关系、 以及所述每个内存条的 SPD信息中的唯一标识 与所述每个内存条的物理地址之间的对应关系。
结合第七方面的第二种可能的实现形式， 在第七方面的第三种可能的实现形式 中，所述内存条的所在位置包括所述内存条所在槽位号或者所述内存条所在端口号和 槽位号。
第八方面， 提供一种基础输入输出***， 所述***包括：
获取单元， 用于获取主机中每个内存条与所在位置之间的对应关系； 处理单元， 用于根据所述每个内存条与所在位置之间的对应关系， 生成所述每个 内存条的模组存在的串行检测 SPD信息中的唯一标识与所述每个内存条所在位置之 间的对应关系、 以及所述每个内存条的 SPD信息中的唯一标识与所述每个内存条的 物理地址之间的对应关系；
存储单元， 用于保存所述每个内存条的 SPD信息中的唯一标识与所述每个内存 条所在位置之间的对应关系、 以及所述每个内存条的 SPD信息中的唯一标识与所述 每个内存条的物理地址之间的对应关系。
在第八方面的第一种可能的实现形式中，所述 CPU的所在位置包括所述 CPU所 在槽位号或者所述 CPU所在端口号和槽位号。
结合第八方面或第八方面的第一种可能的实现形式，在第八方面的第二种可能的 实现形式中，
所述获取单元， 还用于获取所述主机中每个中央处理器 CPU与所在位置之间的 对应关系以及所述每个 CPU中每个核心的唯一编号；
所述处理单元， 还用于根据所述每个 CPU与所在位置之间的对应关系以及所述 每个 CPU中每个核心的唯一编号，生成所述每个 CPU中每个核心的唯一编号与所属 CPU的所在位置之间的对应关系；
所述存储单元， 还用于保存所述每个核心的唯一编号与所属 CPU的所在位置之 间的对应关系。
结合第八方面的第二种可能的实现形式， 在第八方面的第三种可能的实现形式 中，所述内存条的所在位置包括所述内存条所在槽位号或者所述内存条所在端口号和 槽位号。
通过本发明实施例中所述的方法， 实现了主机中虚拟资源和物理资源之间的对 应。本发明实施例所述方法实现的虚拟资源和物理资源之间的关联粒度比较精细， 能 够有效提高故障管理和节能管理的效率。 附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现 有技术描述中所需要使用的附图作简单地介绍， 显而易见地， 下面描述中的附图仅仅 是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前 提下， 还可以根据这些附图获得其他的附图。
图 1为本发明实施例一所述的实现物理资源和虚拟资源对应的方法流程图； 图 2为本发明实施例二所述的实现物理资源和虚拟资源对应的方法流程图； 图 3为本发明实施例三所述的实现物理资源和虚拟资源对应的方法流程图； 图 4为本发明实施例四所述的实现物理资源和虚拟资源对应的方法流程图； 图 5为本发明实施例五所述的实现物理资源和虚拟资源对应的方法流程图； 图 6为单台服务器时的网络拓扑图；
图 7为本发明实施例六所述的实现物理资源和虚拟资源对应的方法流程图； 图 8为本发明实施例七所述的实现物理资源和虚拟资源对应的方法流程图； 图 9为多台服务器时的网络拓扑图；
图 10为本发明实施例八所述的实现物理资源和虚拟资源对应的方法流程图； 图 11为本发明实施例一所述的基础输入输出***的结构图；
图 12为本发明实施例二所述的基础输入输出***的结构图；
图 13为本发明实施例三所述的基础输入输出***的结构图；
图 14为本发明实施例四所述的基础输入输出***的结构图；
图 15为本发明实施例一所述的另一种基础输入输出***的结构图；
图 16为本发明实施例二所述的另一种基础输入输出***的结构图；
图 17为本发明实施例三所述的另一种基础输入输出***的结构图；
图 18为本发明实施例四所述的另一种基础输入输出***的结构图。 具体实施方式
本发明提供一种实现物理资源和虚拟资源对应的方法和基础输入输出***，实现 虚拟资源和物理资源之间的精确对应， 提高故障管理和节能管理的效率。
本发明实施例提供的方法的核心思路在于： 利用位置信息， 例如 slot (槽位） 映 射技术实现物理资源和虚拟资源的对应， 解决现有技术中关联粒度不够精细的问题。
为了使本技术领域的人员更好地理解本发明实施例中的技术方案，并使本发明实 施例的上述目的、特征和优点能够更加明显易懂， 下面结合附图对本发明实施例中技 术方案作进一步详细的说明。
参照图 1， 为本发明实施例一所述的实现物理资源和虚拟资源对应的方法流程 图。 如图 1所示， 所述方法包括以下步骤：
步骤 S101 : BIOS (Basic Input Output System, 基础输入输出***） 获取主机中 每个 CPU (Central Processing Unit, 中央处理器） 与所在位置之间的对应关系。
步骤 S102:所述 BIOS生成所述每个 CPU中每个核心与所属 CPU的所在位置之 间的对应关系。
步骤 S103 : 所述 BIOS将所述每个核心与所属 CPU的所在位置之间的对应关系 发送至基板管理控制器 BMC保存， 并将所述每个核心与所属 CPU所在位置之间的 对应关系通过 CPU信息上报至 OS (Operating System, 操作***）。
本发明实施例一所述方法中， 所述 BIOS对获取到的主机中每个 CPU与所在位 置之间的对应关系进行处理，生成每个 CPU中每个核心分别与所属 CPU所在位置之 间的对应关系， 将上述对应关系发送至 BMC保存并通过 CPU信息上报至操作*** OS, 实现主机中虚拟资源和物理资源之间的对应。 本发明实施例所述方法实现的虚 拟资源和物理资源之间的关联粒度比较精细，能够有效提高故障管理和节能管理的效 率。
本发明实施例一所述方法针对主机中的 CPU实现了虚拟资源与物理资源之间的 对应，进一步的， 该方法还能针对主机中的内存条实现了虚拟资源与物理资源之间的 对应。
具体的， 所述方法还可以包括： 获取所述主机中每个内存条与所在位置之间的对 应关系； 结合所述主机的内存的物理地址编址方法， 生成所述每个内存条的物理地址 与内存条所在位置之间的对应关系， 发送至所述 BMC保存。
需要说明的是，本文所说的内存的物理地址编址方法是指主机中内存条的物理地 址的表示形式。在实际应用中， 当内存的编址方式不同时， 该物理地址的表现形式也 会有所区别。
本发明实施例一所述方法， 进一步的， 所述 BIOS对获取到的主机中的每个内存 条与所在位置之间的对应关系进行处理，生成主机中每个内存条的物理地址与该内存 条所在位置之间的对应关系， 并将上该对应关系发送至 BMC保存， 实现主机中虚拟 资源和物理资源之间的对应。本发明实施例所述方法实现的虚拟资源和物理资源之间 的关联粒度比较精细， 能够有效提高故障管理和节能管理的效率。
参照图 2， 为本发明实施例二所述的实现物理资源和虚拟资源对应的方法流程 图。 如图 2所示， 所述方法包括以下步骤：
步骤 S201 : BIOS (Basic Input Output System, 基础输入输出***） 获取主机中 每个内存条与所在位置之间的对应关系。
步骤 S202:所述 BIOS结合所述主机的内存的物理地址编址方法， 生成所述每个 内存条的物理地址与内存条所在位置之间的对应关系， 发送至基板管理控制器 BMC 保存。
需要说明的是，本文所说的内存的物理地址编址方法是指主机中内存条的物理地 址的表示形式。在实际应用中， 当内存的编址方式不同时， 该物理地址的表现形式也 会有所区别。
本发明实施例二所述方法中， 所述 BIOS对获取到的主机中的每个内存条与所在 位置之间的对应关系进行处理，生成主机中每个内存条的物理地址与该内存条所在位 置之间的对应关系， 并将上该对应关系发送至 BMC保存， 实现主机中虚拟资源和物 理资源之间的对应。本发明实施例所述方法实现的虚拟资源和物理资源之间的关联粒 度比较精细， 能够有效提高故障管理和节能管理的效率。
本发明实施例二所述方法针对主机中的内存条实现了虚拟资源与物理资源之间 的对应， 进一步的， 该方法还能针对主机中的 CPU实现了虚拟资源与物理资源之间 的对应。
具体的， 所述方法还可以包括： 所述 BIOS获取所述主机中每个中央处理器 CPU 与所在位置之间的对应关系；生成所述每个 CPU中每个核心与所属 CPU的所在位置 之间的对应关系； 将所述每个核心与所属 CPU的所在位置之间的对应关系发送至所 述 BMC保存， 并将所述每个核心与所属 CPU所在位置之间的对应关系通过 CPU信 息上报至操作*** OS。
本发明实施例二所述方法， 进一步的， 所述 BIOS对获取到的主机中每个 CPU 与所在位置之间的对应关系进行处理，生成每个 CPU中每个核心分别与所属 CPU所 在位置之间的对应关系， 将上述对应关系发送至 BMC保存并通过 CPU信息上报至 操作*** OS， 实现主机中虚拟资源和物理资源之间的对应。 本发明实施例所述方法 实现的虚拟资源和物理资源之间的关联粒度比较精细，能够有效提高故障管理和节能 管理的效率。
参照图 3， 为本发明实施例三所述的实现物理资源和虚拟资源对应的方法流程 图。 如图 3所示， 所述方法包括以下步骤：
步骤 S301 : 基础输入输出*** BIOS获取主机中每个中央处理器 CPU与所在位 置之间的对应关系以及每个 CPU中每个核心的唯一编号。
步骤 S302:所述 BIOS生成所述每个 CPU中每个核心的唯一编号与所属 CPU的 所在位置之间的对应关系。
步骤 S303 : 所述 BIOS将所述每个核心的唯一编号与所属 CPU的所在位置之间 的对应关系保存在所述 BIOS中。
本发明实施例三所述方法中， 所述 BIOS对获取到的主机中每个 CPU与所在位 置之间的对应关系进行处理， 生成主机中每个 CPU 中每个核心的唯一编号与所属 CPU所在位置之间的对应关系， 并将上述对应关系保存在所述 BIOS中， 实现主机中 虚拟资源和物理资源之间的对应。本发明实施例所述方法实现的虚拟资源和物理资源 之间的关联粒度比较精细， 能够有效提高故障管理和节能管理的效率。
本发明实施例三所述方法针对主机中的 CPU实现了虚拟资源与物理资源之间的 对应，进一步的， 该方法还能针对主机中的内存条实现了虚拟资源与物理资源之间的 对应。
具体的， 所述方法还可以包括： 获取所述主机中每个内存条与所在位置之间的对 应关系； 生成所述每个内存条的模组存在的串行检测 SPD信息中的唯一标识与所述 每个内存条所在位置之间的对应关系、 以及所述每个内存条的 SPD信息中的唯一标 识与所述每个内存条的物理地址之间的对应关系， 保存在所述 BIOS中。
本发明实施例三所述方法， 进一步的， 对获取到的主机中每个内存条与所在位置 之间的对应关系进行处理， 生成主机中每个内存条的 SPD信息中的唯一标识与该内 存条所在位置之间的对应关系和各内存条的 SPD信息中的唯一标识与该内存条的物 理地址之间的对应关系， 并将上述各对应关系保存在所述 BIOS中， 实现主机中虚拟 资源和物理资源之间的对应。本发明实施例所述方法实现的虚拟资源和物理资源之间 的关联粒度比较精细， 能够有效提高故障管理和节能管理的效率。
参照图 4， 为本发明实施例四所述的实现物理资源和虚拟资源对应的方法流程 图。 如图 4所示， 所述方法包括以下步骤：
步骤 S401 :基础输入输出*** BIOS获取获取主机中每个内存条与所在位置之间 的对应关系。
步骤 S402: 所述 BIOS生成所述每个内存条的模组存在的串行检测 SPD信息中 的唯一标识与所述每个内存条所在位置之间的对应关系、以及所述每个内存条的 SPD 信息中的唯一标识与所述每个内存条的物理地址之间的对应关系，保存在基础输入输 出*** BIOS中。 本发明实施例四所述方法中， 所述 BIOS对获取到的主机中每个内存条与所在位 置之间的对应关系进行处理， 生成主机中每个内存条的 SPD信息中的唯一标识与该 内存条所在位置之间的对应关系和各内存条的 SPD信息中的唯一标识与该内存条的 物理地址之间的对应关系， 并将上述各对应关系保存在所述 BIOS中， 实现主机中虚 拟资源和物理资源之间的对应。本发明实施例所述方法实现的虚拟资源和物理资源之 间的关联粒度比较精细， 能够有效提高故障管理和节能管理的效率。
本发明实施例四所述方法针对主机中的内存条实现了虚拟资源与物理资源之间 的对应， 进一步的， 该方法还能针对主机中的 CPU实现了虚拟资源与物理资源之间 的对应。
具体的， 所述方法还可以包括： 获取所述主机中每个中央处理器 cpu与所在位 置之间的对应关系以及所述每个 CPU中每个核心的唯一编号；生成所述每个 CPU中 每个核心的唯一编号与所属 CPU的所在位置之间的对应关系； 将所述每个核心的唯 一编号与所属 CPU的所在位置之间的对应关系保存在所述 BIOS中。
本发明实施例四所述方法， 进一步的， 所述 BIOS 对获取到的主机中每个 CPU 与所在位置之间的对应关系进行处理， 生成主机中每个 CPU中每个核心的唯一编号 与所属 CPU所在位置之间的对应关系， 并将上述对应关系保存在所述 BIOS中， 实 现主机中虚拟资源和物理资源之间的对应。本发明实施例所述方法实现的虚拟资源和 物理资源之间的关联粒度比较精细， 能够有效提高故障管理和节能管理的效率。
上述各实施例中， 所述 CPU所在位置包括所述 CPU所在槽位号或者所述 CPU 所在端口号和槽位号；所述内存条所在位置包括所述内存条所在槽位号或者所述内存 条所在端口号和槽位号。
需要说明的是， 上述主机可以为普通的计算机、 移动终端、 工作站或服务器、 专 用服务器等。
具体的， 对于一个主机的情景， 上述设备所在位置可以仅仅是各设备所在的槽位 号； 而当处于多台主机的情景时， 上述设备所在位置可以是各设备所在的端口号加槽 位号。
本发明实施例三和四中， 以一个主机为例进行说明， 此时， 所述设备所在位置为 各设备所在的槽位。
参照图 5， 为本发明实施例五所述的实现物理资源和虚拟资源对应的方法流程 图。 如图 5所示， 所述方法包括以下步骤：
步骤 S501 : 位于主机的 BMC获取所述主机中每个 CPU和每个内存条分别与设 备所在槽位之间的对应关系， 并保存在所述 BMC中。
本发明实施例所述方法中， 所述物理资源主要包括设置在主机中的 CPU和内存 条。 一般情况下， 一台主机中包括至少一个 CPU和至少一个内存条， 各 CPU和内存 条分别安装在主机机箱框架的某一槽位上， 因此， 各 CPU和内存条与所在的槽位的 槽位号之间存在一一对应关系。
如图 6所示， 为单台主机时的网络拓扑图。 该主机包括两个 CPU 100和 8根内 存条 200。 当然， 本发明实施例中， 仅是以图 6所示的主机为例进行说明， 在实际应 用中， 主机包括的 CPU和内存条的个数可以根据需要具体设定。
针对图 6所示的主机， 所述 BMC获取的对应关系可以如下所示：
CPU, slot 1 , 在位
CPU, slot 2, 在位
Memory, slot 1 在位， SPD信
Memory, slot 2 在位， SPD信
Memory, slot 3 在位， SPD信
Memory, slot 4 在位， SPD信
Memory, slot 5 在位， SPD信
Memory, slot 6 在位， SPD信
Memory, slot 7 在位， SPD信
Memory, slot 8 在位， SPD信』
上述对应关系表明， 该主机包括的两个 CPU, 分别位于 slot 1 (第一槽位）和 slot
2 (第二槽位）； 8根内存条， 分别位于 slot 1 (第一槽位） 至 slot 8 (第八槽位）。
其中， SPD ( Serial Presence Detect, 模组存在的串行检测）信息是指关于内存模 组的配置信息， 如 P-Bank数量、 电压、 行地址 /列地址数量、 位宽、 各种主要操作时 序等。 该 SPD 信息是由内存条的厂商烧录在 EEPROM ( Electrically Erasable Programmable Read Only Memory, 电擦除可编程只读存储器） 中的。
步骤 S502: BIOS获取主机中每个 CPU与该 CPU所在槽位之间的对应关系并进 行处理， 生成该主机中每个 CPU中每个核心 core与所属 CPU所在槽位的对应关系， 并发送至 BMC中保存， 同时上报包含对应关系的 CPU信息至虚拟化 OS; 其中， 所 述 CPU信息中包含该主机中各 CPU中每个 core与该 CPU所在槽位的对应关系。
具体的， 所述 BIOS处理后得到的 CPU信息可以如下表 1所示：
表 1： BIOS处理后得到的 CPU信息 物理资源 BIOS处理后
CPU , slot 1 (Slot 1, core 1)
(Slot 1, core 2)
(Slot 1, core 3)
(Slot 1, core 4)
CPU , slot 2 (Slot 2, core 1)
(Slot 2, core 2)
(Slot 2, core 3)
(Slot 2, core 4) 由上表 1可知， 经所述 BIOS处理后得到的 CPU信息中， 可以得到 CPU中各个 core与槽位之间的对应关系， 由此可以使得本发明实施例所述方法中， 虚拟资源与物 理资源的对应关系可以精确到 CPU的每个 core与所在槽位之间。
步骤 S503 :所述 BIOS获取主机中每个内存条与该内存条所在槽位之间的对应关 系， 结合内存的物理地址编址方法， 生成该主机中每个内存条的物理地址与该内存条 所在槽位之间的对应关系， 发送至所述 BMC保存， 同时上报常规的内存信息至虚拟 化 OS。
具体的， 在实际应用中， 所述内存的物理地址编址方法可以包括两种， 对于不同 的物理地址编址方法，主机中内存条的物理地址的表示形式不同。具体的，表 2所示， 为两种内存编址方法下分别对应的内存条物理地址表示形式。
表 2:
物理资源 内存编址方法一 内存编址方法二 BIOS上报 memory, slot 1 0-127M 0-1， 16-17， 0-1023M memory, slot 2 128-255M 2-3 , 18-19，
memory, slot 3 256-383M 4-5， 20-21 , memory, slot 4 384-511M 6-7， 22-23 ,
memory, slot 5 512-639M 8-9， 24-25, memory, slot 6 640-767M 10-11， 26-27,
memory, slot 7 768-895M 12-13 , 28-29, memory, slot 8 896-1023M 13-15, 30-31 , 由表 2可知， 当内存的编址方法不同时， 对应的内存的物理地址的表现形式也有 所不同。以表 2中所示为例，其中内存编址方法一，是以内存条颗粒进行编址的方法， 其内存的物理地址表现为 0-127M、 128-255M、 896-1023M; 而内存编址方法 二， 则是以比内存条更小的颗粒、 结合交叉存储技术进行编址的方法， 其内存的物理 地址表现为 0-1， 16-17， ……。 上述内存编址方法均为本领域的公知技术， 在此不再 详述。
所述 BIOS结合实际使用的内存物理地址编址方法， 对接收到的所述内存条与槽 位之间的对应关系进行处理，得到该主机中每根内存条的物理地址与该内存条所在槽 位之间的对应关系， 并将该对应关系发送至 BMC保存。 由此使得， 本发明实施例所 述方法中，虚拟资源与物理资源的对应关系可以精确到每根内存条的物理地址与内存 条所在的槽位之间。
步骤 S504: 所述虚拟化 OS启动后， 接收所述 BIOS上报的 CPU信息和内存条 信息， 形成资源池。
具体的， 所述虚拟化 OS形成的资源池如下所示：
CPU Pool:
(Slot 1, core 1) (Slot 1, core 2) (Slot 1, core 3) (Slot 1, core 4) (Slot 2, core 1) (Slot 2, core 2) (Slot 2, core 3) (Slot 2, core 4)
Memory Pool:
0-1023M
然后， 虚拟化 OS结合虚拟化处理， 拉通虚拟资源和物理资源， 实现虚拟资源与 物理资源之间的对应。
需要说明的是， 本发明实施例五所述方法中， 步骤 S501中， BMC也可以仅获取 所述主机中每个 CPU与设备所在槽位之间的对应关系， 并保存在所述 BMC中， 此 时所述方法中将不包括步骤 S503 , 且在步骤 S504中， 所述虚拟化 OS启动后， 也仅 接收所述 BIOS上报的 CPU信息， 形成资源池。 或者， 在步骤 S501中， BMC也可 以仅获取所述主机中每个内存条与设备所在槽位之间的对应关系， 并保存在所述 BMC中。 此时所述方法中将不包括步骤 S502, 且在步骤 S504中， 所述虚拟化 OS 启动后， 也仅接收所述 BIOS上报的内存条信息， 形成资源池。
本发明实施例五所述方法中， 所述虚拟化 OS接收到 BIOS上报的包含所述主机 中各 CPU中每个 core与槽位的对应关系的 CPU信息， 使得所述虚拟化 OS形成的 CPU资源池中包括 CPU中每个 core与槽位的对应关系。 当虚拟化 OS检测到 vCPU 出错时， 能够根据该对应关系， 确定出错的 vCPU对应的 core, 例如为 （Slot l , core 3 )， 虚拟化 OS可以直接隔离该 （Slot l , core 3 ), 并通知 BMC该 （Slot 1， core 3 ) 出错。
本发明实施例所述方法中， 所述 BIOS对获取到的 CPU和 /或内存条分别与槽位 之间的对应关系进行处理，得到主机中每个 CPU中每个 core分别与槽位的对应关系、 和 /或每根内存条的物理地址与该内存条所在槽位之间的对应关系， 并将上述各对应 关系发送至 BMC保存， 实现主机中虚拟资源和物理资源之间的对应。 本发明实施例 所述方法实现的虚拟资源和物理资源之间的关联粒度比较精细，能够有效提高故障管 理和节能管理的效率。
具体的， 当虚拟化 OS检测到 vCPU出错时， OS将出错的 vCPU对应到具体的 CPU中的 core, 由 BMC根据主机中每个 CPU中每个 core分别与槽位的对应关系， 找到该 core对应的 CPU所在的槽位， 发出告警， 提醒维护人员直接对该槽位的 CPU 进行检修。
例如， 虚拟化 OS检测到 vCPU出错， 假设该 vCPU对应的 core为 （Slot 1， core 3 )， 如果 OS经过判断确定该出错的 vCPU对应的 core ( Slot 1， core 3 ) 已经出错多 次， 不能使用了， 则 OS直接隔离 core ( Slot 1， core 3 ), 并通知 BMC。 由 BMC根 据主机中每个 CPU中每个 core分别与槽位的对应关系， 找到 core ( Slot 1， core 3 ) 所在的槽位， 发出告警， 提醒维护人员该第一槽位上的 CPU发生故障需要进行维修 或更换。
或者是， (CPU, slot l )发出预警， 需要通知虚拟化 OS进行隔离， 则 BMC根据 每个 CPU中每个 core分别与槽位的对应关系，确定（ Slot 1， core 1 )、（ Slot 1， core 2 )、 ( Slot 1 , core 3 ) 禾 P ( Slot 1 , core 4) 需要隔离， 上报至虚拟化 OS， 对上述 core进 行隔离处理。 当 OS检测到内存地址出错时， OS将该出错的内存地址对应到具体的 物理地址， 并通知 BMC; 由 BMC根据主机中每根内存条的物理地址与该内存条所 在槽位之间的对应关系， 找到该内存条所在的槽位， 并发出警告， 提醒维护人员直接 对该槽位的内存条进行检修。
例如， 虚拟化 OS检测到内存地址 0 123M出错，， 如果经过判断确定该段内存 已经多次出错， 不能使用了， 则 OS直接隔离该段内存， 并通知 BMC。 假设该内存 地址对应的物理地址为 0~123M， 则由 BMC根据每根内存条的物理地址与该内存条 所在槽位之间的对应关系， 结合 BIOS当前采用的内存物理地址编址方法， 即为编址 方法一， 确定发生故障的内存段对应的内存条为 （memory, slot l ), 由 BMC发出警 告， 提醒维护人员第一槽位上的内存条发生故障需要进行维修或更换。 或者是， （memory, slot 1 )发生预警， 且当前采用的内存物理地址编址方法为编 址方法一， 假设可以确定受影响的内存段为 0 127M, 由 BMC上报虚拟化 OS; 虚拟 化 OS对物理地址为 0 127M的内存段进行处理。 由此可知， 本发明实施例五所述方 法， 能够实现虚拟资源和物理资源之间的精确对应， 使得维护人员能够精确辨别是主 机的哪个部件出现了问题， 方便故障维护； 与现有需要迁移出错的物理节点上的整台 虚拟机相比， 节省资源， 利于节能。
由上述内容可见， 本发明实施例五所述方法中， 当虚拟化 OS检测到 vCPU出错 或内存地址出错时，将出错的 vCPU对应的 core或出错的内存地址通知 BMC，由 BMC 根据对应关系找到出错的 core对应的 CPU所在的槽位或者出错的内存地址对应的内 存条所在的槽位， 并发出告警， 以通知维护人员哪个槽位的 cpu或内存条出错， 提 醒维护人员检修。
在本发明实施例五所述方法中， 所述根据对应关系找到出错的 core对应的 CPU 所在的槽位或者出错的内存地址对应的内存条所在的槽位这一步骤， 也可以由 BIOS 来实现， 具体的， 下面进行详细介绍。
本发明实施例六中， 仍以一个主机为例进行说明， 此时， 所述设备所在位置为各 设备所在的槽位。
参照图 7，为本发明实施例六所述的实现物理资源和虚拟资源对应的方法流程图。 如图 7所示， 所述方法包括以下步骤：
步骤 S601 : 位于主机的 BMC获取主机中每个 CPU和每个内存条分别与设备所 在槽位之间的对应关系， 并保存； 其中， 所述每个内存条与所在槽位之间的对应关系 中包括每个内存条的 SPD信息中的唯一标识与每个内存条所在槽位之间的对应关系。
具体的， 对于每个内存条， 厂商烧录在内存条中的 SPD信息中包含有该内存条 的唯一标识信息。不同内存条的唯一标识信息不同。通过该唯一标识信息可以直接定 位到该唯一标识对应的内存条。 因此， 各内存条的 SPD信息中的唯一标识与槽位之 间的对应关系就相当于各内存条与槽位之间的对应关系。
步骤 S602: 所述 BIOS获取主机中每个 CPU与所在槽位之间的对应关系、 以及 ***预设的每个 CPU中每个 core的唯一编号， 生成该主机中每个 CPU中每个 core 的唯一编号与所属 CPU所在槽位之间的对应关系， 保存在 BIOS中， 并上报常规的 CPU信息至虚拟化 OS。
需要说明的是， CPU的每个 core都有一个***内的唯一编号 （APICID), 该唯 一编号是由***预先设定的， BIOS能够直接从***中获取该唯一编号。 同时， 虚拟 化 OS也可以从***中直接获取各 CPU的每个 core的唯一编号。
因此，本发明实施例六所述方法中，所述 BIOS仅仅是保存所述 CPU中各个 core 的唯一编号与该 CPU所在槽位之间的对应关系， 并不需要将所述对应关系上报给虚 拟化 0S。 此时 BIOS上报至虚拟化 OS的 CPU信息与现有技术相同， 仅仅是常规的 CPU信息， 不含有上述的对应关系。
当虚拟化 OS检测到 CPU上的某个 core出错时， 可以根据从***获取的各 CPU 的每个 core的唯一编号， 确定该出错的 core的唯一编号， 并通知 BI0S。 由 BIOS根 据该出错的 core的唯一编号、 以及 CPU中各个 core的唯一编号与该 CPU所在槽位 之间的对应关系， 确定是哪个槽位上的 CPU出错。
步骤 S603 :所述 BIOS获取主机中各内存条与所在槽位之间的对应关系并进行处 理， 生成各内存条的 SPD信息中的唯一标识与该内存条所在槽位之间的对应关系、 以及各内存条的 SPD信息中的唯一标识与该内存条的物理地址之间的对应关系， 保 存在 BIOS中， 并上报常规的内存信息至虚拟化 0S。
步骤 S604: 所述虚拟化 OS启动后， 接收所述 BIOS上报的 CPU信息和内存条 信息， 形成资源池。
需要说明的是， 本发明实施例六所述方法中， 步骤 S601中， BMC也可以仅获取 所述主机中每个 CPU与设备所在槽位之间的对应关系， 并保存在所述 BMC中， 此 时所述方法中将不包括步骤 S603 , 且在步骤 S604中， 所述虚拟化 OS启动后， 也仅 接收所述 BIOS上报的 CPU信息， 形成资源池。 或者， 在步骤 S601中， BMC也可 以仅获取所述主机中每个内存条与设备所在槽位之间的对应关系， 并保存在所述 BMC中。 此时所述方法中将不包括步骤 S602, 且在步骤 S604中， 所述虚拟化 OS 启动后， 也仅接收所述 BIOS上报的内存条信息， 形成资源池。
本发明实施例所述方法中， 虚拟化 OS形成资源池的技术与现有技术相同， 在此 不再赘述。
然后， 所述虚拟化 OS结合虚拟化处理， 拉通虚拟资源和物理资源。 本发明实施 例六所述方法中， 所述 BIOS对获取到的 CPU和内存条分别与槽位之间的对应关系 进行处理，得到主机中每个 CPU的每个内核的唯一编号与该 CPU所在槽位的对应关 系、 以及各内存条的 SPD信息中的唯一标识与该内存条的物理地址之间的对应关系 和各内存条的 SPD信息中的唯一标识与该内存条的槽位之间的对应关系， 从而实现 主机中虚拟资源和物理资源之间的对应。本发明实施例所述方法实现的虚拟资源和物 理资源之间的关联粒度比较精细， 能够有效提高故障管理和节能管理的效率。 具体的，当虚拟化 OS检测到 CPU的某个 core出错时，根据从***获取的各 CPU 的每个 core的唯一编号， 确定该出错的 core的唯一编号， 并通知 BI0S。 BIOS根据 该出错的 core的唯一编号、 以及 CPU中各个 core的唯一编号与该 CPU所在槽位之 间的对应关系， 确定是哪个槽位上的 CPU出错， 并通知 BMC。 BMC得到 BIOS告 知的消息后发出告警， 提醒维护人员哪个槽位上的 CPU发生了故障需要进行维修或 更换。
或者是， 当 BMC检测到某个槽位上的 CPU发生故障， 将该 CPU所在的槽位上 报 BIOS;所述 BIOS根据其中保存的所述每个 CPU的每个 core的唯一编号与该 CPU 所在槽位的对应关系， 确定该 CPU故障会影响的 core的编号， 并通知虚拟化 OS; 所述虚拟化 OS根据接收到的受影响的 core的编号， 对这些受故障影响的 core进行 隔离处理。
当虚拟化 OS检测到一段内存出错时， 将出错的内存对应的物理地址通知 BI0S。 BIOS根据出错的内存的物理地址，结合各内存条的 SPD信息中的唯一标识与该内存 条的物理地址之间的对应关系， 确定出错的内存的唯一标识， 告知 BMC该唯一标识 对应的内存出错。 所述 BMC根据该唯一标识， 结合所述内存条与槽位之间的对应关 系， 确定出错的内存所在的槽位， 并发出告警， 提醒维护人员哪个槽位上的内存条发 生了故障需要进行维修或更换。
或者是， 当 BMC检测到某个槽位上的内存条发生故障， 读取发生故障的内存条 的 SPD信息中的唯一标识， 上报至 BI0S。所述 BIOS根据其中保存的 SPD信息中的 唯一标识与该内存条的物理地址之间的对应关系，确定该故障影响哪些物理地址对应 的内存段， 并通知虚拟化 os。 所述虚拟化 OS对这些受影响的内存段进行隔离处理。
由此可知， 本发明实施例所述方法， 能够实现虚拟资源和物理资源之间的精确对 应， 使得维护人员能够精确辨别是主机的哪个部件出现了问题， 方便故障维护； 与现 有需要迁移出错的物理节点上的整台虚拟机相比， 节省资源， 利于节能。
由上述内容可见， 本发明实施例六所述方法中， 当虚拟化 OS检测到 CPU出错 或内存地址出错时，将出错的 CPU对应的 core或出错的内存地址通知 BIOS，由 BIOS 根据对应关系找到出错的 core对应的 CPU所在的槽位或者出错的内存地址对应的 SPD信息中的唯一标识， 并通知 BMC; 由 BMC发出告警， 提醒维护人员哪个槽位 的 CPU或该唯一标识对应的内存条出错， 提醒维护人员检修。
对于多台主机的情景中， 各设备所在位置就不仅仅是各设备所在的槽位号， 还包 括各设备所属主机的端口号。 具体的， 下面进行详细介绍。 参照图 8，为本发明实施例七所述的实现物理资源和虚拟资源对应的方法流程图。 如图 8所示， 所述方法包括以下步骤：
步骤 S701 : 位于主机的 BMC获取主机中每个 CPU和每个内存条分别与设备所 在的端口和槽位之间的对应关系， 并保存。
本发明实施例七所述方法适用于多台主机的情景中， 如图 9所示， 为多台主机时 的网络拓扑图。 图 9中， 多台主机 300通过交换机（图 9中未示出）连接到虚拟化管 理中心 400， 由所述虚拟化管理中心 400实现虚拟化的相关管理。 每台主机都有一个 唯一确定的交换机端口号。 各端口的主机 300 内的 BMC 600 由上层 DMS (Device Manager System, 设备管理***） 500统一管理。
对于图 9所示情景， 在获取 CPU和内存条分别与槽位的对应关系的同时， 还需 要确定该槽位对应主机的端口号， 即为第几个端口对应的主机的第几个槽位。 因此， 本发明实施例七所述的方法中， 需要获取 CPU和内存条分别与设备所在端口和槽位 之间的对应关系， 并发送至 BIOS。
针对图 9所示的多主机***， 所述 BMC获取的对应关系可以如下所示， 以第 5 台主机为例 （其端口号为 5 ) 进行说明：
CPU, slot 1， 5， 在位
CPU, slot 2, 5， 在位
Memory, slot 1,5， 在位， SPD信
Memory, slot 2,5, 在位， SPD信
Memory, slot 3,5, 在位， SPD信
Memory, slot 4,5， 在位， SPD信
Memory, slot 5,5， 在位， SPD信
Memory, slot 6,5， 在位， SPD信
Memory, slot 7,5， 在位， SPD信
Memory, slot 8,5， 在位， SPD信』
步骤 S702:所述 BIOS获取主机中每个 CPU与该 CPU所在端口和槽位之间的对 应关系并进行处理，生成该主机中每个 CPU中每个核心 core与所属 CPU所在端口和 槽位之间的对应关系， 并发送至 BMC中保存， 同时上报包含对应关系的 CPU信息 至虚拟化 OS;其中，所述 CPU信息中包括该主机中每个 CPU中每个 core与所属 CPU 所在端口和槽位的对应关系。
具体的， 所述 BIOS处理后得到的 CPU信息可以如下表 3所示： 表 3： BIOS处理后得到的 CPU信息
Figure imgf000022_0001
由上表 3可知， 经所述 BIOS处理后得到的 CPU信息中， 可以得到 CPU中各个 core与该 CPU所在端口和槽位之间的对应关系， 由此可以使得本发明实施例所述方 法中，虚拟资源与物理资源的对应关系可以精确到 CPU的每个 core与该 CPU所在端 口和槽位之间。
步骤 S703 :所述 BIOS获取主机中每个内存条与该内存条所在槽位和端口之间的 对应关系， 结合内存物理地址编址方法， 生成该主机中每个内存条的物理地址与该内 存条所在的端口和槽位之间的对应关系， 发送至所述 BMC保存， 同时上报常规的内 存信息至虚拟化 OS。
具体的， 在实际应用中， 所述内存的物理地址编址方法可以包括两种， 对于不同 的物理地址编址方法，主机中内存条的物理地址的表示形式不同。具体的，表 4所示， 为两种内存编址方法下分别对应的内存条物理地址表示形式。
表 4:
物理资源 内存编制方法一 内存编制方法二 BIOS上报 memory, slot 1 ,5 0-127M 0-1， 16-17， 0-1023M memory, slot 2 ,5 128-255M 2-3 , 18-19，
memory, slot 3 ,5 256-383M 4-5， 20-21 , memory, slot 4 ,5 384-511M 6-7， 22-23 ,
memory, slot 5 ,5 512-639M 8-9， 24-25, memory, slot 6 ,5 640-767M 10-11， 26-27, memory, slot 7 ,5 768-895M 12-13 , 28-29,
memory, slot 8 ,5 896-1023M 13-15, 30-31 , 所述 BIOS结合实际使用的内存物理地址编址方法， 对接收到的所述内存条与该 内存条所在端口和槽位之间的对应关系进行处理，得到该主机中每根内存条的物理地 址与该内存条所在端口和槽位之间的对应关系， 上报至操作*** OS。 由此使得， 本 发明实施例所述方法中，虚拟资源与物理资源的对应关系可以精确到每根内存条的物 理地址与内存条所在的端口和槽位之间。
步骤 S704: 所述虚拟化 OS启动后， 接收所述 BIOS上报的 CPU信息和内存条 信息， 形成资源池。
具体的， 所述虚拟化 OS形成的资源池如下所示：
CPU Pool:
(Slot 1, core 1,5) (Slot 1, core 2,5) (Slot 1, core 3,5) (Slot 1, core 4,5) (Slot 2, core 1,5)
(Slot 2, core 2,5) (Slot 2, core 3,5) (Slot 2, core 4,5)
Memory Pool:
0-1023M
步骤 S705: 结合虚拟化处理， 拉通虚拟资源和物理资源。
需要说明的是， 本发明实施例七所述方法中， 步骤 S701中， BMC也可以仅获取 所述主机中每个 CPU与设备所在槽位之间的对应关系， 并保存在所述 BMC中， 此 时所述方法中将不包括步骤 S703 , 且在步骤 S704中， 所述虚拟化 OS启动后， 也仅 接收所述 BIOS上报的 CPU信息， 形成资源池。 或者， 在步骤 S701中， BMC也可 以仅获取所述主机中每个内存条与设备所在槽位之间的对应关系， 并保存在所述 BMC中。 此时所述方法中将不包括步骤 S702, 且在步骤 S704中， 所述虚拟化 OS 启动后， 也仅接收所述 BIOS上报的内存条信息， 形成资源池。
本发明实施例所述方法中， 所述 BIOS对获取到的 CPU和内存条分别与槽位和 端口之间的对应关系进行处理，得到主机中每个 CPU中每个 core分别与该 CPU的槽 位和端口的对应关系、以及每根内存条的物理地址与该内存条所在槽位和端口之间的 对应关系， 并将上述各对应关系保存在所述 BIOS中， 实现主机中虚拟资源和物理资 源之间的对应。本发明实施例所述方法实现的虚拟资源和物理资源之间的关联粒度比 较精细， 能够有效提高故障管理和节能管理的效率。
同样的， 本发明实施例六所述方法也可以适用于多台主机的情景。 具体的， 参照 图 10， 为本发明实施例八所述的实现物理资源和虚拟资源对应的方法流程图。 如图 10所示， 所述方法包括以下步骤： 步骤 S801 : 位于主机的 BMC获取每个 CPU和每个内存条分别与设备所在端口 和槽位之间的对应关系， 并保存； 其中， 所述每个内存条与该内存条所在槽位之间的 对应关系中包括每个内存条的 SPD信息中的唯一标识与该内存条所在端口和槽位之 间的对应关系。
步骤 S802:所述 BIOS获取主机中每个 CPU与该 CPU所在端口和槽位之间的对 应关系、 以及***预设的每个 CPU中每个 core的唯一编号， 生成该主机中每个 CPU 中每个 core的唯一编号与所属 CPU所在端口和槽位之间的对应关系， 保存在 BIOS 中， 并上报常规的 CPU信息至虚拟化 OS。
步骤 S803 :所述 BIOS获取主机中每个内存条与该内存条所在端口和槽位之间的 对应关系并进行处理， 生成每个内存条的 SPD信息中的唯一标识与该内存条所在端 口和槽位之间的对应关系、 以及每个内存条的 SPD信息中的唯一标识与该内存条的 物理地址之间的对应关系， 保存在 BIOS中， 并上报常规的内存信息至虚拟化 OS。
步骤 S804: 所述虚拟化 OS启动后， 接收所述 BIOS上报的 CPU信息和内存条 信息， 形成资源池。
然后， 所述虚拟化 OS结合虚拟化处理， 拉通虚拟资源和物理资源。
需要说明的是， 本发明实施例八所述方法中， 步骤 S801中， BMC也可以仅获取 所述主机中每个 CPU与设备所在槽位之间的对应关系， 并保存在所述 BMC中， 此 时所述方法中将不包括步骤 S803 , 且在步骤 S804中， 所述虚拟化 OS启动后， 也仅 接收所述 BIOS上报的 CPU信息， 形成资源池。 或者， 在步骤 S801中， BMC也可 以仅获取所述主机中每个内存条与设备所在槽位之间的对应关系， 并保存在所述 BMC中。 此时所述方法中将不包括步骤 S802, 且在步骤 S804中， 所述虚拟化 OS 启动后， 也仅接收所述 BIOS上报的内存条信息， 形成资源池。
本发明实施例八所述方法中， 所述 BIOS对获取到的 CPU和 /或内存条分别与端 口和槽位之间的对应关系进行处理， 得到主机中每个 CPU的每个内核的唯一编号与 该 CPU所在端口和槽位的对应关系 /或各内存条的 SPD信息中的唯一标识与该内存条 的物理地址之间的对应关系和各内存条的 SPD信息中的唯一标识与该内存条的端口 和槽位之间的对应关系， 从而实现主机中虚拟资源和物理资源之间的对应。本发明实 施例所述方法实现的虚拟资源和物理资源之间的关联粒度比较精细，能够有效提高故 障管理和节能管理的效率。
对应于本发明实施例提供的实现物理资源和虚拟资源对应的方法，本发明实施例 还提供一种基础输入输出*** BIOS。 参照图 11，为本发明实施例一所述的基础输入输出***的结构图。如图 11所示， 所述***包括： 获取单元 901、 处理单元 902和发送单元 903。
所述获取单元 901， 用于获取主机中每个中央处理器 CPU与所在位置之间的对 应关系。
所述处理单元 902， 用于根据所述每个 CPU与所在位置之间的对应关系， 生成 所述每个 CPU中每个核心与所属 CPU的所在位置之间的对应关系。
所述发送单元 903， 用于将所述每个核心与所属 CPU的所在位置之间的对应关 系发送至基板管理控制器 BMC保存； 并， 将所述每个核心与所属 CPU所在位置之 间的对应关系通过 CPU信息上报至操作*** OS。
本发明实施例一所述***中， 对获取到的主机中每个 cpu与所在位置之间的对 应关系进行处理，生成每个 CPU中每个核心分别与所属 CPU所在位置之间的对应关 系， 将上述对应关系发送至 BMC保存并通过 CPU信息上报至操作*** OS， 实现主 机中虚拟资源和物理资源之间的对应。本发明实施例所述***实现的虚拟资源和物理 资源之间的关联粒度比较精细， 能够有效提高故障管理和节能管理的效率。
本发明实施例一所述***针对主机中的 CPU实现了虚拟资源与物理资源之间的 对应，进一步的， 该***还能针对主机中的内存条实现了虚拟资源与物理资源之间的 对应。
具体的， 所述获取单元 901， 还用于获取所述主机中每个内存条与所在位置之间 的对应关系。
所述处理单元 902， 还用于根据所述每个内存条与所在位置之间的对应关系， 结 合所述主机的内存的物理地址编址方法，生成所述每个内存条的物理地址与内存条所 在位置之间的对应关系。
所述发送单元 903， 还用于将所述每个内存条的物理地址与内存条所在位置之间 的对应关系发送至所述 BMC保存。
本发明实施例一所述***，对获取到的主机中的每个内存条与所在位置之间的对 应关系进行处理，生成主机中每个内存条的物理地址与该内存条所在位置之间的对应 关系， 并将上该对应关系发送至 BMC保存， 实现主机中虚拟资源和物理资源之间的 对应。 本发明实施例所述***实现的虚拟资源和物理资源之间的关联粒度比较精细， 能够有效提高故障管理和节能管理的效率。
参照图 12，为本发明实施例二所述的基础输入输出***的结构图。如图 12所示， 所述***包括： 获取单元 1001、 处理单元 1002和发送单元 1003。 所述获取单元 1001， 用于获取主机中每个内存条与所在位置之间的对应关系。 所述处理单元 1002， 用于根据所述每个内存条与所在位置之间的对应关系， 结 合所述主机的内存的物理地址编址方法，生成所述每个内存条的物理地址与内存条所 在位置之间的对应关系。
所述发送单元 1003， 用于将所述每个内存条的物理地址与内存条所在位置之间 的对应关系发送至基板管理控制器 BMC保存。
本发明实施例二所述***中，对获取到的主机中的每个内存条与所在位置之间的 对应关系进行处理，生成主机中每个内存条的物理地址与该内存条所在位置之间的对 应关系， 并将上该对应关系发送至 BMC保存， 实现主机中虚拟资源和物理资源之间 的对应。 本发明实施例所述***实现的虚拟资源和物理资源之间的关联粒度比较精 细， 能够有效提高故障管理和节能管理的效率。
本发明实施例二所述***针对主机中的内存条实现了虚拟资源与物理资源之间 的对应， 进一步的， 该***还能针对主机中的 CPU实现了虚拟资源与物理资源之间 的对应。
具体的， 所述获取单元 1001， 还用于获取所述主机中每个中央处理器 CPU与所 在位置之间的对应关系。
所述处理单元 1002， 还用于根据所述每个 CPU与所在位置之间的对应关系， 生 成所述每个 CPU中每个核心与所属 CPU的所在位置之间的对应关系。
所述发送单元 1003， 还用于将所述每个核心与所属 CPU的所在位置之间的对应 关系发送至所述 BMC保存； 并， 将所述每个核心与所属 CPU所在位置之间的对应 关系通过 CPU信息上报至操作*** os。
本发明实施例二所述***， 进一步的， 对获取到的主机中每个 CPU与所在位置 之间的对应关系进行处理，生成每个 CPU中每个核心分别与所属 CPU所在位置之间 的对应关系，将上述对应关系发送至 BMC保存并通过 CPU信息上报至操作*** OS， 实现主机中虚拟资源和物理资源之间的对应。本发明实施例所述***实现的虚拟资源 和物理资源之间的关联粒度比较精细， 能够有效提高故障管理和节能管理的效率。
参照图 13，为本发明实施例三所述的基础输入输出***的结构图。如图 13所示， 所述***包括： 获取单元 1101、 处理单元 1102和存储单元 1103。
所述获取单元 1101， 用于获取主机中每个中央处理器 CPU与所在位置之间的对 应关系以及每个 CPU中每个核心的唯一编号。
所述处理单元 1102， 用于根据所述每个 CPU与所在位置之间的对应关系以及每 个 CPU中每个核心的唯一编号， 生成所述每个 CPU中每个核心的唯一编号与所属 CPU的所在位置之间的对应关系。
所述存储单元 1103， 用于保存所述每个核心的唯一编号与所属 CPU的所在位置 之间的对应关系。
本发明实施例三所述***中， 对获取到的主机中每个 CPU与所在位置之间的对 应关系进行处理，生成主机中每个 CPU中每个核心的唯一编号与所属 CPU所在位置 之间的对应关系， 并将上述对应关系保存在所述 BIOS中， 实现主机中虚拟资源和物 理资源之间的对应。本发明实施例所述***实现的虚拟资源和物理资源之间的关联粒 度比较精细， 能够有效提高故障管理和节能管理的效率。
本发明实施例三所述***针对主机中的 cpu实现了虚拟资源与物理资源之间的 对应，进一步的， 该***还能针对主机中的内存条实现了虚拟资源与物理资源之间的 对应。
具体的， 所述获取单元 1101， 还用于获取所述主机中每个内存条与所在位置之 间的对应关系。
所述处理单元 1102， 还用于根据所述每个内存条与所在位置之间的对应关系， 生成所述每个内存条的模组存在的串行检测 SPD信息中的唯一标识与所述每个内存 条所在位置之间的对应关系、 以及所述每个内存条的 SPD信息中的唯一标识与所述 每个内存条的物理地址之间的对应关系。
所述存储单元 1103， 还用于保存所述每个内存条的 SPD信息中的唯一标识与所 述每个内存条所在位置之间的对应关系、 以及所述每个内存条的 SPD信息中的唯一 标识与所述每个内存条的物理地址之间的对应关系。
本发明实施例三所述***， 进一步的， 对获取到的主机中每个内存条与所在位置 之间的对应关系进行处理， 生成主机中每个内存条的 SPD信息中的唯一标识与该内 存条所在位置之间的对应关系和各内存条的 SPD信息中的唯一标识与该内存条的物 理地址之间的对应关系， 并将上述各对应关系保存在所述 BIOS中， 实现主机中虚拟 资源和物理资源之间的对应。本发明实施例所述***实现的虚拟资源和物理资源之间 的关联粒度比较精细， 能够有效提高故障管理和节能管理的效率。
参照图 14，为本发明实施例四所述的基础输入输出***的结构图。如图 14所示， 所述***包括： 获取单元 1201、 处理单元 1202和存储单元 1203。
所述获取单元 1201， 用于获取主机中每个内存条与所在位置之间的对应关系。 所述处理单元 1202， 用于根据所述每个内存条与所在位置之间的对应关系， 生 成所述每个内存条的模组存在的串行检测 SPD信息中的唯一标识与所述每个内存条 所在位置之间的对应关系、 以及所述每个内存条的 SPD信息中的唯一标识与所述每 个内存条的物理地址之间的对应关系。
所述存储单元 1203， 用于保存所述每个内存条的 SPD信息中的唯一标识与所述 每个内存条所在位置之间的对应关系、 以及所述每个内存条的 SPD信息中的唯一标 识与所述每个内存条的物理地址之间的对应关系。
本发明实施例四所述***中，对获取到的主机中每个内存条与所在位置之间的对 应关系进行处理， 生成主机中每个内存条的 SPD信息中的唯一标识与该内存条所在 位置之间的对应关系和各内存条的 SPD信息中的唯一标识与该内存条的物理地址之 间的对应关系， 并将上述各对应关系保存在所述 BIOS中， 实现主机中虚拟资源和物 理资源之间的对应。本发明实施例所述***实现的虚拟资源和物理资源之间的关联粒 度比较精细， 能够有效提高故障管理和节能管理的效率。
本发明实施例四所述***针对主机中的内存条实现了虚拟资源与物理资源之间 的对应， 进一步的， 该***还能针对主机中 CPU的实现了虚拟资源与物理资源之间 的对应。
具体的， 所述获取单元 1201， 还用于获取主机中每个中央处理器 CPU与所在位 置之间的对应关系以及每个 CPU中每个核心的唯一编号。
所述处理单元 1202， 还用于根据所述每个 CPU与所在位置之间的对应关系以及 每个 CPU中每个核心的唯一编号，生成所述每个 CPU中每个核心的唯一编号与所属 CPU的所在位置之间的对应关系。
所述存储单元 1203， 还用于保存所述每个核心的唯一编号与所属 CPU的所在位 置之间的对应关系。
本发明实施例四所述***， 进一步的， 对获取到的主机中每个 CPU与所在位置 之间的对应关系进行处理， 生成主机中每个 CPU中每个核心的唯一编号与所属 CPU 所在位置之间的对应关系， 并将上述对应关系保存在所述 BIOS中， 实现主机中虚拟 资源和物理资源之间的对应。本发明实施例所述***实现的虚拟资源和物理资源之间 的关联粒度比较精细， 能够有效提高故障管理和节能管理的效率。
上述各实施例中， 所述 CPU所在位置包括所述 CPU所在槽位号或者所述 CPU 所在端口号和槽位号；所述内存条所在位置包括所述内存条所在槽位号或者所述内存 条所在端口号和槽位号。
对应于本发明实施例提供的实现物理资源和虚拟资源对应的方法，本发明实施例 还提供一种基础输入输出*** BIOS。
参照图 15，为本发明实施例一所述的基础输入输出***的结构图。如图 15所示， 所述***包括： 获取器 1301、 处理器 1302和发送器 1303。
所述获取器 1301， 用于获取主机中每个中央处理器 CPU与所在位置之间的对应 关系。
所述处理器 1302， 用于根据所述每个 CPU与所在位置之间的对应关系， 生成所 述每个 CPU中每个核心与所属 CPU的所在位置之间的对应关系。
所述发送器 1303， 用于将所述每个核心与所属 CPU的所在位置之间的对应关系 发送至基板管理控制器 BMC保存； 并， 将所述每个核心与所属 CPU所在位置之间 的对应关系通过 cpu信息上报至操作*** os。
本发明实施例一所述***中， 所述基础输入输出*** BIOS对获取到的主机中每 个 CPU与所在位置之间的对应关系进行处理，生成每个 CPU中每个核心分别与所属 CPU所在位置之间的对应关系， 将上述对应关系发送至 BMC保存并通过 CPU信息 上报至操作*** OS， 实现主机中虚拟资源和物理资源之间的对应。 本发明实施例所 述***实现的虚拟资源和物理资源之间的关联粒度比较精细，能够有效提高故障管理 和节能管理的效率。
本发明实施例一所述***针对主机中的 CPU实现了虚拟资源与物理资源之间的 对应，进一步的， 该***还能针对主机中的内存条实现了虚拟资源与物理资源之间的 对应。
具体的， 所述获取器 1301， 还用于获取所述主机中每个内存条与所在位置之间 的对应关系。
所述处理器 1302， 还用于根据所述每个内存条与所在位置之间的对应关系， 结 合所述主机的内存的物理地址编址方法，生成所述每个内存条的物理地址与内存条所 在位置之间的对应关系。
所述发送器 1303， 还用于将所述每个内存条的物理地址与内存条所在位置之间 的对应关系发送至所述 BMC保存。
本发明实施例一所述***， 进一步的， 对获取到的主机中的每个内存条与所在位 置之间的对应关系进行处理，生成主机中每个内存条的物理地址与该内存条所在位置 之间的对应关系， 并将上该对应关系发送至 BMC保存， 实现主机中虚拟资源和物理 资源之间的对应。本发明实施例所述***实现的虚拟资源和物理资源之间的关联粒度 比较精细， 能够有效提高故障管理和节能管理的效率。 参照图 16，为本发明实施例二所述的基础输入输出***的结构图。如图 16所示， 所述***包括： 获取器 1401、 处理器 1402和发送器 1403。
所述获取器 1401， 用于获取主机中每个内存条与所在位置之间的对应关系。 所述处理器 1402， 用于根据所述每个内存条与所在位置之间的对应关系， 结合 所述主机的内存的物理地址编址方法，生成所述每个内存条的物理地址与内存条所在 位置之间的对应关系。
所述发送器 1403， 用于将所述每个内存条的物理地址与内存条所在位置之间的 对应关系发送至所述 BMC保存。
本发明实施例二所述***中，对获取到的主机中的每个内存条与所在位置之间的 对应关系进行处理，生成主机中每个内存条的物理地址与该内存条所在位置之间的对 应关系， 并将上该对应关系发送至 BMC保存， 实现主机中虚拟资源和物理资源之间 的对应。 本发明实施例所述***实现的虚拟资源和物理资源之间的关联粒度比较精 细， 能够有效提高故障管理和节能管理的效率。
本发明实施例二所述***针对主机中的内存条实现了虚拟资源与物理资源之间 的对应， 进一步的， 该***还能针对主机中的 CPU实现了虚拟资源与物理资源之间 的对应。
具体的， 所述获取器 1401， 还用于获取主机中每个中央处理器 CPU与所在位置 之间的对应关系。
所述处理器 1402， 还用于根据所述每个 CPU与所在位置之间的对应关系， 生成 所述每个 CPU中每个核心与所属 CPU的所在位置之间的对应关系。
所述发送器 1403， 还用于将所述每个核心与所属 CPU的所在位置之间的对应关 系发送至基板管理控制器 BMC保存； 并， 将所述每个核心与所属 CPU所在位置之 间的对应关系通过 CPU信息上报至操作*** OS。
本发明实施例二所述***， 进一步的， 对获取到的主机中每个 CPU与所在位置 之间的对应关系进行处理，生成每个 CPU中每个核心分别与所属 CPU所在位置之间 的对应关系，将上述对应关系发送至 BMC保存并通过 CPU信息上报至操作*** OS， 实现主机中虚拟资源和物理资源之间的对应。本发明实施例所述***实现的虚拟资源 和物理资源之间的关联粒度比较精细， 能够有效提高故障管理和节能管理的效率。
参照图 17，为本发明实施例三所述的基础输入输出***的结构图。如图 17所示， 所述***包括： 获取器 1501、 处理器 1502和存储器 1503。
所述获取器 1501， 用于获取主机中每个中央处理器 CPU与所在位置之间的对应 关系以及每个 CPU中每个核心的唯一编号。
所述处理器 1502， 用于根据所述每个 CPU与所在位置之间的对应关系以及每个 CPU中每个核心的唯一编号， 生成所述每个 CPU中每个核心的唯一编号与所属 CPU 的所在位置之间的对应关系。
所述存储器 1503， 用于保存所述每个核心的唯一编号与所属 CPU的所在位置之 间的对应关系。
本发明实施例三所述***中， 对获取到的主机中每个 CPU与所在位置之间的对 应关系进行处理，生成主机中每个 CPU中每个核心的唯一编号与所属 CPU所在位置 之间的对应关系， 并将上述对应关系保存在所述 BIOS中， 实现主机中虚拟资源和物 理资源之间的对应。本发明实施例所述***实现的虚拟资源和物理资源之间的关联粒 度比较精细， 能够有效提高故障管理和节能管理的效率。
本发明实施例三所述***针对主机中的 CPU实现了虚拟资源与物理资源之间的 对应，进一步的， 该***还能针对主机中的内存条实现了虚拟资源与物理资源之间的 对应。
具体的， 所述获取器 1501， 还用于获取所述主机中每个内存条与所在位置之间 的对应关系。
所述处理器 1502， 还用于根据所述每个内存条与所在位置之间的对应关系， 生 成所述每个内存条的模组存在的串行检测 SPD信息中的唯一标识与所述每个内存条 所在位置之间的对应关系、 以及所述每个内存条的 SPD信息中的唯一标识与所述每 个内存条的物理地址之间的对应关系。
所述存储器 1503， 还用于保存所述每个内存条的 SPD信息中的唯一标识与所述 每个内存条所在位置之间的对应关系、 以及所述每个内存条的 SPD信息中的唯一标 识与所述每个内存条的物理地址之间的对应关系。
本发明实施例三所述***， 进一步的， 对获取到的主机中每个内存条与所在位置 之间的对应关系进行处理， 生成主机中每个内存条的 SPD信息中的唯一标识与该内 存条所在位置之间的对应关系和各内存条的 SPD信息中的唯一标识与该内存条的物 理地址之间的对应关系， 并将上述各对应关系保存在所述 BIOS中， 实现主机中虚拟 资源和物理资源之间的对应。本发明实施例所述***实现的虚拟资源和物理资源之间 的关联粒度比较精细， 能够有效提高故障管理和节能管理的效率。
参照图 18，为本发明实施例四所述的基础输入输出***的结构图。如图 18所示， 所述***包括： 获取器 1601、 处理器 1602和存储器 1603。 所述获取器 1601， 用于获取主机中每个内存条与所在位置之间的对应关系。 所述处理器 1602， 用于根据所述每个内存条与所在位置之间的对应关系， 生成 所述每个内存条的模组存在的串行检测 SPD信息中的唯一标识与所述每个内存条所 在位置之间的对应关系、 以及所述每个内存条的 SPD信息中的唯一标识与所述每个 内存条的物理地址之间的对应关系。
所述存储器 1603， 用于保存所述每个内存条的 SPD信息中的唯一标识与所述每 个内存条所在位置之间的对应关系、 以及所述每个内存条的 SPD信息中的唯一标识 与所述每个内存条的物理地址之间的对应关系。
本发明实施例四所述***中，对获取到的主机中每个内存条与所在位置之间的对 应关系进行处理， 生成主机中每个内存条的 SPD信息中的唯一标识与该内存条所在 位置之间的对应关系和各内存条的 SPD信息中的唯一标识与该内存条的物理地址之 间的对应关系， 并将上述各对应关系保存在所述 BIOS中， 实现主机中虚拟资源和物 理资源之间的对应。本发明实施例所述***实现的虚拟资源和物理资源之间的关联粒 度比较精细， 能够有效提高故障管理和节能管理的效率。
本发明实施例四所述***针对主机中的内存条实现了虚拟资源与物理资源之间 的对应， 进一步的， 该***还能针对主机中的 CPU实现了虚拟资源与物理资源之间 的对应。
具体的， 所述获取器 1601， 还用于获取主机中每个中央处理器 CPU与所在位置 之间的对应关系以及每个 CPU中每个核心的唯一编号。
所述处理器 1602， 还用于根据所述每个 CPU与所在位置之间的对应关系以及每 个 CPU中每个核心的唯一编号， 生成所述每个 CPU中每个核心的唯一编号与所属 CPU的所在位置之间的对应关系。
所述存储器 1603， 还用于保存所述每个核心的唯一编号与所属 CPU的所在位置 之间的对应关系。
本发明实施例四所述***， 进一步的， 对获取到的主机中每个 CPU与所在位置 之间的对应关系进行处理， 生成主机中每个 CPU中每个核心的唯一编号与所属 CPU 所在位置之间的对应关系， 并将上述对应关系保存在所述 BIOS中， 实现主机中虚拟 资源和物理资源之间的对应。本发明实施例所述***实现的虚拟资源和物理资源之间 的关联粒度比较精细， 能够有效提高故障管理和节能管理的效率。
上述各实施例中， 所述 CPU所在位置包括所述 CPU所在槽位号或者所述 CPU 所在端口号和槽位号；所述内存条所在位置包括所述内存条所在槽位号或者所述内存 条所在端口号和槽位号。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单 元及算法步骤， 能够以电子硬件、 或者计算机软件和电子硬件的结合来实现。这些功 能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专 业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实 现不应认为超出本发明的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的***、 装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中， 应该理解到， 所揭露的***、 装置和方法， 可 以通过其它的方式实现。 例如， 以上所描述的装置实施例仅仅是示意性的， 例如， 所 述单元的划分， 仅仅为一种逻辑功能划分， 实际实现时可以有另外的划分方式， 例如 多个单元或组件可以结合或者可以集成到另一个***， 或一些特征可以忽略， 或不执 行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些 接口， 装置或单元的间接耦合或通信连接， 可以是电性， 机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显 示的部件可以是或者也可以不是物理单元， 即可以位于一个地方， 或者也可以分布到 多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例 方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中， 也可以 是各个单元单独物理存在， 也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以 存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或 者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现 出来， 该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机 设备 （可以是个人计算机， 服务器， 或者网络设备等） 或处理器 （processor)执行本 发明各个实施例所述方法的全部或部分步骤。 而前述的存储介质包括： U盘、移动硬 盘、只读存储器（ROM, Read-Only Memory ) 随机存取存储器（RAM, Random Access Memory), 磁碟或者光盘等各种可以存储程序代码的介质。
以上所述， 仅为本发明的具体实施方式， 但本发明的保护范围并不局限于此， 任 何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可轻易想到变化或替换， 都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应所述以权利要求的保 护范围为准。

Claims

权 利 要 求
1、 一种实现物理资源和虚拟资源对应的方法， 其特征在于， 所述方法包括: 获取主机中每个中央处理器 CPU与所在位置之间的对应关系；
生成所述每个 CPU中每个核心与所属 CPU的所在位置之间的对应关系； 将所述每个核心与所属 CPU的所在位置之间的对应关系发送至基板管理控 制器 BMC保存， 并将所述每个核心与所属 CPU所在位置之间的对应关系通过
CPU信息上报至操作*** os。
2、 根据要求 1 所述的方法， 其特征在于， 所述 CPU的所在位置包括所述 CPU所在槽位号或者所述 CPU所在端口号和槽位号。
3、 根据要求 1或 2所述的方法， 其特征在于， 还包括：
获取所述主机中每个内存条与所在位置之间的对应关系；
结合所述主机的内存的物理地址编址方法，生成所述每个内存条的物理地址 与内存条所在位置之间的对应关系， 发送至所述 BMC保存。
4、 根据要求 3所述的方法， 其特征在于， 所述内存条的所在位置包括所述 内存条所在槽位号或者所述内存条所在端口号和槽位号。
5、 一种实现物理资源和虚拟资源对应的方法， 其特征在于， 所述方法包括: 获取主机中每个内存条与所在位置之间的对应关系；
结合所述主机的内存的物理地址编址方法，生成所述每个内存条的物理地址 与内存条所在位置之间的对应关系， 发送至基板管理控制器 BMC保存。
6、 根据要求 5所述的方法， 其特征在于， 所述内存条的所在位置包括所述 内存条所在槽位号或者所述内存条所在端口号和槽位号。
7、 根据要求 5或 6所述的方法， 其特征在于， 还包括：
获取所述主机中每个中央处理器 CPU与所在位置之间的对应关系； 生成所述每个 CPU中每个核心与所属 CPU的所在位置之间的对应关系； 将所述每个核心与所属 CPU 的所在位置之间的对应关系发送至所述 BMC 保存，并将所述每个核心与所属 CPU所在位置之间的对应关系通过 CPU信息上 报至操作*** OS。
8、 根据要求 7所述的方法， 其特征在于， 所述 CPU的所在位置包括所述 CPU所在槽位号或者所述 CPU所在端口号和槽位号。
9、 一种实现物理资源和虚拟资源对应的方法， 其特征在于， 所述方法包括: 获取主机中每个中央处理器 CPU与所在位置之间的对应关系以及所述每个 CPU中每个核心的唯一编号；
生成所述每个 CPU中每个核心的唯一编号与所属 CPU的所在位置之间的对 应关系；
将所述每个核心的唯一编号与所属 CPU的所在位置之间的对应关系保存在 基础输入输出*** BIOS中。
10、 根据要求 9所述的方法， 其特征在于， 所述 CPU的所在位置包括所述 CPU所在槽位号或者所述 CPU所在端口号和槽位号。
11、 根据要求 9或 10所述的方法， 其特征在于， 还包括：
获取所述主机中每个内存条与所在位置之间的对应关系；
生成所述每个内存条的模组存在的串行检测 SPD信息中的唯一标识与所述 每个内存条所在位置之间的对应关系、 以及所述每个内存条的 SPD信息中的唯 一标识与所述每个内存条的物理地址之间的对应关系， 保存在所述 BIOS中。
12、 根据要求 11所述的方法， 其特征在于， 所述内存条的所在位置包括所 述内存条所在槽位号或者所述内存条所在端口号和槽位号。
13、一种实现物理资源和虚拟资源对应的方法，其特征在于，所述方法包括： 获取主机中每个内存条与所在位置之间的对应关系；
生成所述每个内存条的模组存在的串行检测 SPD信息中的唯一标识与所述 每个内存条所在位置之间的对应关系、 以及所述每个内存条的 SPD信息中的唯 一标识与所述每个内存条的物理地址之间的对应关系，保存在基础输入输出*** BIOS中。
14、 根据要求 13所述的方法， 其特征在于， 所述内存条的所在位置包括所 述内存条所在槽位号或者所述内存条所在端口号和槽位号。
15、 根据要求 13或 14所述的方法， 其特征在于， 还包括：
获取所述主机中每个中央处理器 CPU与所在位置之间的对应关系以及所述 每个 CPU中每个核心的唯一编号；
生成所述每个 CPU中每个核心的唯一编号与所属 CPU的所在位置之间的对 应关系；
将所述每个核心的唯一编号与所属 CPU的所在位置之间的对应关系保存在 所述 BIOS中。
16、 根据要求 15所述的方法， 其特征在于， 所述 CPU的所在位置包括所述
CPU所在槽位号或者所述 CPU所在端口号和槽位号。
17、 一种基础输入输出***， 其特征在于， 所述***包括： 获取单元， 用于获取主机中每个中央处理器 CPU与所在位置之间的对应关 系；
处理单元， 用于根据所述每个 CPU与所在位置之间的对应关系， 生成所述 每个 CPU中每个核心与所属 CPU的所在位置之间的对应关系；
发送单元， 用于将所述每个核心与所属 CPU的所在位置之间的对应关系发 送至基板管理控制器 BMC保存； 并， 将所述每个核心与所属 CPU所在位置之 间的对应关系通过 CPU信息上报至操作*** OS。
18、 根据要求 17所述的基础输入输出***， 其特征在于， 所述 CPU的所在 位置包括所述 CPU所在槽位号或者所述 CPU所在端口号和槽位号。
19、 根据要求 17或 18所述的基础输入输出***， 其特征在于， 所述获取单元，还用于获取所述主机中每个内存条与所在位置之间的对应关 系；
所述处理单元， 还用于根据所述每个内存条与所在位置之间的对应关系， 结 合所述主机的内存的物理地址编址方法，生成所述每个内存条的物理地址与内存 条所在位置之间的对应关系；
所述发送单元，还用于将所述每个内存条的物理地址与内存条所在位置之间 的对应关系发送至所述 BMC保存。
20、 根据要求 19所述的基础输入输出***， 其特征在于， 所述内存条的所 在位置包括所述内存条所在槽位号或者所述内存条所在端口号和槽位号。
21、 一种基础输入输出***， 其特征在于， 所述***包括：
获取单元， 用于获取主机中每个内存条与所在位置之间的对应关系； 处理单元， 用于根据所述每个内存条与所在位置之间的对应关系， 结合所述 主机的内存的物理地址编址方法，生成所述每个内存条的物理地址与内存条所在 位置之间的对应关系；
发送单元，用于将所述每个内存条的物理地址与内存条所在位置之间的对应 关系发送至基板管理控制器 BMC保存。
22、 根据要求 21所述的基础输入输出***， 其特征在于， 所述内存条的所 在位置包括所述内存条所在槽位号或者所述内存条所在端口号和槽位号。
23、 根据要求 20或 21所述的基础输入输出***， 其特征在于， 所述获取单元， 还用于获取所述主机中每个中央处理器 CPU与所在位置之 间的对应关系；
所述处理单元， 还用于根据所述每个 CPU与所在位置之间的对应关系， 生 成所述每个 CPU中每个核心与所属 CPU的所在位置之间的对应关系； 所述发送单元， 还用于将所述每个核心与所属 CPU的所在位置之间的对应 关系发送至所述 BMC保存； 并， 将所述每个核心与所属 CPU所在位置之间的 对应关系通过 CPU信息上报至操作*** OS。
24、 根据要求 23所述的基础输入输出***， 其特征在于， 所述 CPU的所在 位置包括所述 CPU所在槽位号或者所述 CPU所在端口号和槽位号。
25、 一种基础输入输出***， 其特征在于， 所述***包括：
获取单元， 用于获取主机中每个中央处理器 CPU与所在位置之间的对应关 系以及所述每个 CPU中每个核心的唯一编号；
处理单元， 用于根据所述每个 cpu与所在位置之间的对应关系以及所述每 个 CPU中每个核心的唯一编号，生成所述每个 CPU中每个核心的唯一编号与所 属 CPU的所在位置之间的对应关系；
存储单元， 用于保存所述每个核心的唯一编号与所属 CPU的所在位置之间 的对应关系。
26、 根据要求 25所述的基础输入输出***， 其特征在于， 所述 CPU的所在 位置包括所述 CPU所在槽位号或者所述 CPU所在端口号和槽位号。
27、 根据要求 25或 26所述的基础输入输出***， 其特征在于， 所述获取单元，还用于获取所述主机中每个内存条与所在位置之间的对应关 系；
所述处理单元， 还用于根据所述每个内存条与所在位置之间的对应关系， 生 成所述每个内存条的模组存在的串行检测 SPD信息中的唯一标识与所述每个内 存条所在位置之间的对应关系、 以及所述每个内存条的 SPD信息中的唯一标识 与所述每个内存条的物理地址之间的对应关系；
所述存储单元， 还用于保存所述每个内存条的 SPD信息中的唯一标识与所 述每个内存条所在位置之间的对应关系、 以及所述每个内存条的 SPD信息中的 唯一标识与所述每个内存条的物理地址之间的对应关系。
28、 根据要求 27所述的基础输入输出***， 其特征在于， 所述内存条的所 在位置包括所述内存条所在槽位号或者所述内存条所在端口号和槽位号。
29、 一种基础输入输出***， 其特征在于， 所述***包括：
获取单元， 用于获取主机中每个内存条与所在位置之间的对应关系； 处理单元， 用于根据所述每个内存条与所在位置之间的对应关系， 生成所述 每个内存条的模组存在的串行检测 SPD信息中的唯一标识与所述每个内存条所 在位置之间的对应关系、 以及所述每个内存条的 SPD信息中的唯一标识与所述 每个内存条的物理地址之间的对应关系；
存储单元， 用于保存所述每个内存条的 SPD信息中的唯一标识与所述每个 内存条所在位置之间的对应关系、 以及所述每个内存条的 SPD信息中的唯一标 识与所述每个内存条的物理地址之间的对应关系。
30、 根据要求 29所述的基础输入输出***， 其特征在于， 所述 CPU的所在 位置包括所述 CPU所在槽位号或者所述 CPU所在端口号和槽位号。
31、 根据要求 29或 30所述的基础输入输出***， 其特征在于， 所述获取单元， 还用于获取所述主机中每个中央处理器 CPU与所在位置之 间的对应关系以及所述每个 cpu中每个核心的唯一编号；
所述处理单元， 还用于根据所述每个 CPU与所在位置之间的对应关系以及 所述每个 CPU中每个核心的唯一编号，生成所述每个 CPU中每个核心的唯一编 号与所属 CPU的所在位置之间的对应关系；
所述存储单元， 还用于保存所述每个核心的唯一编号与所属 CPU的所在位 置之间的对应关系。
32、 根据要求 31所述的基础输入输出***， 其特征在于， 所述内存条的所 在位置包括所述内存条所在槽位号或者所述内存条所在端口号和槽位号。
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